Ericsson AXE HARDWARE EVOLUTION Service Manual

The hardware used in the AXE system has
been updated continuously. Initially, all
telephony-related hardware in AXE was ana­logue. Over the years, almost all hardware
has been redesigned to take advantage of the
formidable advances in electronics. This has
been a continuous, ongoing process. Digi­talisation was gradually introduced in the
early 1980s, followed by application­specific integrated circuits (ASIC) in the
mid-1980s. A major breakthrough came in

19861. In the late 1980s and early 1990s, the
evolution continued in small steps. A few
original products have remained, however.
Today, these last remaining products are
being replaced. At the same time, almost all
other hardware products that make up the
basic AXE system are being rationalised.

52

Ericsson Review No. 2, 1997

AXE hardware evolution

Urban Hägg and Tomas Lundqvist

The AXE system is the most widely deployed switching system in the world.
It is used in public telephony-oriented applications of every type, including
traditional fixed network applications in local, transit, international and
combined networks. AXE is also deployed for all major mobile standards –
analogue as well as digital. AXE is very strong in intelligent networks and
other real-time database applications. Recent designs also enable data
communication capabilities to be added to the system.
From its inception, the AXE system was designed to accommodate con­tinuous change. Throughout the years, new applications have been intro­duced, its array of functions has grown, and its hardware has been steadily
updated.
The authors describe how the latest advances in hardware technology have
been brought into the system, thereby dramatically improving such charac­teristics as floor space, power consumption, system handling, and cost of
ownership. As always, backwards compatibility has been maintained to the
greatest possible extent, in order to protect previous investments in AXE.

DL2

DLMUX

APT dev

TSM-DL3

DL3

DL1
DL2

APT dev

RP4

RP

RP

RP

RPB-S

RPH-S

RPH

IOG

CP

Generic device

magazine

AXE evolution

Extensions

GSS64K

RPB-P

DL2

DLMUX

APT dev

DL3 DL2

APT dev

RP4

RP4

RP

RPB-S

RPH-S

RPH-P

CP

Generic device

magazine

GSS64K

AXE evolution

New deliveries

DL3

DLMUX

DL_IO

DL2

Generic device

magazine or

BYB 202 equipment

RPV2

RPB-P

IOG20

Figure 1
The figures show how the new interfaces are
used for extensions and new deliveries.

Ericsson Review No. 2, 1997

53

Architecture

As the AXE system continues to evolve, sys­tem designers ensure that the very solid and
proven system architecture is maintained.
The fundamental principle of a central pro­cessor (CP) that controls regional processors
(RP), which in turn control hardware ser­vices, has proved to be superior. Strict in­terfaces ensure that different system com­ponents can be developed independently. To
ensure non-stop operation, all vital traffic
and operation and maintenance (O&M) sys­tem products are built in duplicated struc­tures.

In order to fully exploit the advantages of
modern electronics, some fundamental sys­tem hardware interfaces are now being im­proved and extended. It goes without say­ing that compatibility is maintained in
AXE.

Traditionally, a parallel bus, or a region­al processor bus (RPB), has been used for
communication between the central and re­gional processors. Now, however, in order
to increase capacity (data transfer rate) and

to decrease the need for interface hardware,
a serial bus is being introduced alongside
the existing RPB (Figure 1). The new RPB
permits single-board regional processors to
be housed in the same subrack as the devices
they control, thus minimising hardware and
cable interconnections between hardware
devices.

In earlier generations of AXE, an ex­tension module (EM) bus and cables were
used to connect regional processors to ap­plication hardware (extension modules). In
the new hardware design, however, most re­gional processors are located in the same
subrack as the extension modules they con­trol. By locating the regional processors in
this way, designers have all but eliminated
the EM bus, except in the backplane. The
new location makes it much easier for
operators to install and extend equipment.

The traditional AXE interface (called the
digital link 2, DL2) between the group
switch (GS) and its connected devices was
at the 2 Mbit/s primary multiplexing pulse
code modulation (PCM) level.

Now, a new high-speed interface is being

ALI Alarm interface
ANSI American National Standards

Institute

ASIC Application-specific integrated

circuit

AST-DR-V3 Announcement service terminal

version 3
ATM Asynchronous transfer mode
BGA Ball grid array
BM Building module (1 BM=40.64

mm)
BSC Base station controller
CANS Code answer
CCD Conference call device
CMOS Complementary metal-oxide semi-

conductor
CP Central processor
CSFSK Code sender for FSK tones
CSK Code sender for DTMF tones
CSR Code sender/receiver
D-AMPS Digital AMPS
DL2 Digital link interface 2
DL3 Digital link interface 3
DSP Digital signal processor
DTMF Dual-tone multifrequency
E0 64 kbit/s digital link
E1 2 Mbit/s digital link
ECP 303 Echo canceller in pool

generation 3
ECP 404 Echo canceller in pool

generation 4

EM Extension module
EMB Extension module bus
EMC Electromagnetic compatibility
EMI Electromagnetic interference
ETC5 Exchange terminal circuit

generation 5

ETSI European Telecommunications

Standards Institute
FSK Frequency shift keying
GDM Generic device magazine (sub-

rack)
GS Group switch
GSM Global system for mobile commu-

nication
GSS Group switch subsystem
HLR Home location register
IN Intelligent network
I/O Input/output
IOG11 I/O system 11
IOG20 I/O system 20
IP Internet protocol
ISDN Integrated services digital network
ITU-T International Telecommunication

Union - Telecommunications Stan-

dardization Sector
IWU Interworking unit
KRD Keyset receiver device
LED Light-emitting diode
LUM Line unit module
MSC Mobile switching centre
MTBF Mean time between failures

MW Megaword
O&M Operation and maintenance
PCM Pulse code modulation
PDC Pacific digital cellular
PROM Programmable read-only memory
PSTN Public switched telephone network
RAM Random access memory
RMS Remote measurement subsystem
ROM Read-only memory
RP Regional processor
RP4 Regional processor generation 4
RPB Regional processor bus
RPD Regional processor device
RPG Regional processor with group

switch interface

RPV Regional processor connected to

VME
SCP Service control point
SCSI Small computer system interface
SNT Switching network terminal
SPM Space switch module
STC Signalling terminal central
STM Synchronous transfer mode
STP Signalling transfer point
T1 1.5 Mbit/s digital link
TCD Trunk continuity check device
TSM Time switch module
TSM-1 155 Mbit/s time switch module
VME Versa Module Eurocard

Box A Abbreviations

introduced at the third level in the basic
PCM hierarchy. The interface, which is
called DL3 (digital link 3), works at the
32 Mbit/s level (overhead excluded).

The introduction of the DL3 interface dra­matically decreases group switch and device
hardware. Equally important, it removes
massive amounts of internal system cabling.
The DL2 interface has been retained to en­sure compatibility.

Each DL3 interface contains 16 multi­plexed DL2 interfaces. In fact, the DL2s run
in the backplane of the new device subracks,
which means that only one sixteenth of the
cabling is needed between the group switch
and the devices that are connected to it.

Basic technology

In general, designers taking part in the AXE
hardware evolution programme have used
ASICs, high-performance microprocessors,
digital signal processors (DSP) and faster in­terfaces to improve AXE hardware. ASICs
were chosen where volumes of circuits are
very high or where performance is critical.
Commercial microprocessors, which are be­coming commonplace for more and more
applications, have also been integrated into
the hardware. These changes allow design­ers to integrate commercial operating sys­tems and software – especially at the re­gional processor level.

Also, inasmuch as the processing capaci­ty of regional processors has kept pace with
developments in general-purpose processor
technology, the new AXE hardware requires
fewer processors than were used before. This
was another important factor in reducing
the size of the exchange.

The most common type of processor in
AXE systems today is the digital signal pro­cessor. DSPs, which are used in many kinds
of application, are flexible platforms that
may easily be programmed to provide new
functions. Moreover, software at the DSP
level may be sourced from other manufac­turers, which allows designers to introduce
new functionality with shorter time to mar­ket.

Today almost all AXE hardware uses a

3.3 V power supply. This change and the
use of submicron technology (0.25-0.5 µm)

have reduced power consumption to levels
far below that of previous hardware genera­tions.

Equipment practice

Owing to the introduction of high-speed in­terfaces and tougher requirements for elec­tromagnetic compatibility (EMC), AXE
hardware designers constructed a new
equipment practice, called the BYB 5012.
The BYB 501 has excellent EMC character­istics and fulfils Class B requirements with
good margin. Compared with the BYB 202,
whose cabinet shields against electromag­netic interference (EMI), the new equip­ment practice provides shielding at the sub­rack level. Note: the standard on which the
BYB 501 is based uses the term subrack.
However, in AXE terminology, the word
magazine is often used.

The equipment practice supports multi­point and single-point earthing. The multi-

54

Ericsson Review No. 2, 1997

D
L

M
U
L
T

I
P
L
E
X
E
R

D
L

M
U
L
T

I
P
L
E
X
E
R

CAT

CSKD

KRDD

CCD

CSR

TCD

CSFSK

ECP404

TRA

ASTV3

ETCJ32

ETC24

ETC5

ETC5
DL2_IO
DL2_IO
DL2_IO

STC
SS7

AUTH

DL2_IO

ICM

RCM

CLM

RP4

RP4 RP4 RP4 RP4

external

sync.

external

sync.

ETC5 sync.

test
phone

test
instr.

test
instr.

RSM

PCD-D

PCD
TRU

RPHP RPHS RPHS RPHP

CP

CP

Terminal V24
Terminal V24

Billing X.25
OMC X.25

Alarm V.24

Alarm

printer V.24

OD

HD

IOG20

RPB-P

RPB-P

TSM

DL3

DL3

D
L

M

U
L
T

I
P
L
E
X
E
R

D
L

M
U
L
T

I
P
L
E
X
E
R

SPM

RPB-S

RPB-S

DL2

DL2

EMB

RPB-S

DL2

EMB

RPB-S

GS

EMB

EMB

Cable
Backplane

Figure 2
AXE hardware architecture using new hard­ware.