Epson SED1751 Technical Manual

SED1751

SED1751

Contents

OVERVIEW...................................................................................................................................5-1

TERMINAL FUNCTIONS ..............................................................................................................5-3

ABSOLUTE MAXIMUM RATINGS................................................................................................5-9

MLS Driver Chip Set EPSON i
Technical Manual

SED1751

OVERVIEW

Description

The SED1751 is an 120 output, 3-level low-resistance common (row) driver suitable for high-quality,
high-response-speed MLS (Multi Line Selection) driving.
The SED1751 receives signals from LCD controllers such as the SED1335, and when used is used in
conjunction with the SED1580, can be used to structure a 4-line MLS drive.
The SED1751 uses a slim-chip form that is useful for making LCD panels slimmer. It also supports reduced
logic system voltage operation, making it suitable for a broad range of applications.
The SED1751 has a pad layout supporting easy mounting, and supports bi-directional selection of driver
output order, and has the highest use efficiency for 1/240 and 1/480 duty panels.

Features

• LCD driver outputs......................................120

• Low output ON resistance

• High duty drive supported ........................... 1/480 (Reference value)

• Broad range of LC drive voltages ...............+ 14 to + 42 V (V

• Output shift direction pin select is possible

• Can be switched between 100 and 120 outputs

• Non-biased display OFF function

• Logic system power source .........................2.7 V to 5.5 V

• LC power source offset bias can be adjusted relative to the VDDH and GND levels

• Slim chip shape

•D

0B .............................................................. Au Bump die

•T0A ...............................................................TCP

CC = 2.7 to 5.5 V)

Pad Layout

131

132

155

1

Chip size 12.19 mm × 2.38 mm
Pad pitch 80 µm (Min.)
Chip thickness 525 µm ± 25 µm

1) Au Bump Specifications (SED1751D
Au vertical bump

Parallel to Scribe × Perpendicular to Scribe ± Tolerance
Bump Size A 60 µm × 75 µm ± 4 µm (Pad No. 1 to 35, 60 to 131)
Bump Size B 80 µm × 50 µm ± 4 µm (Pad No. 36 to 59, 132 to 155)
Bump height 17 to 28 µm (The details specified in the acceptance specifications.)

Y

X

OB) Reference Values Only

60

59

36

35

MLS Driver Chip Set EPSON 5–1
Technical Manual

SED1751

Pad Coordinates

Pin Name X Y

1VDDHL –5812 –1012
2+V1L –5717
3VCL –5622
4–V1L –5527
5 GNDL –5432
6 SHL –5094
7 SEL –4869
8VCC –4531

9 LSEL –4192
10 DOFF –3828
11 FR –3081
12 CSEL –2336
13 LP –1998
14 DM –1162
15 CIO2 –755
16 DM –347
17 DM 0
18 DM 347
19 CIO1 755
20 DM 1162
21 YD 1998
22 DM 2336
23 DM 2674
24 DM 3081
25 DM 3489
26 DM 3828
27 F1 4192
28 DM 4531
29 F2 4869
30 TEST1 5094
31 GNDR 5432
32 –V1R 5527
33 VCR 5622
34 +V1R 5717
35 V

DDHR 5812

Units: µm

Pin Name X Y

36 COM1 5945 –902
37 COM2 –822
38 COM3 –742
39 COM4 –662

↓↓ ↓ ↓

57 COM22 5945 778
58 COM23 5945 858
59 COM24 5945 938
60 COM25 5709 1034
61 COM26 5549 1034
62 COM27 5389 1034

↓↓ ↓ ↓

93 COM58 429 1034
94 COM59 269
95 COM60 109
96 COM61 –109
97 COM62 –269
98 COM63 –429

↓↓ ↓ ↓

129 COM94 –5389 1034
130 COM95 –5549 1034
131 COM96 –5709 1034
132 COM97 –5945 938
133 COM98 –5945 858
134 COM99 –5945 778

↓↓ ↓ ↓

152 COM117 –5945 –662
153 COM118 –742
154 COM119 –822
155 COM120 –902

COMn XY coordinates:

COM1 to COM24: (5945, –902 + [80 × (n–1)])
COM25 to COM60: (5709 – [160 × (n–25)], 1034)
COM61 to COM96: (–109 – [160 × (n–61)], 1034)
COM97 to COM120:(–5945, 938 – [80 × (n–97)])

5–2 EPSON MLS Driver Chip Set

Technical Manual

TERMINAL FUNCTIONS

SED1751

Terminal Name I/O Function

COM1 to
COM120 Output transition occurs on falling edge of LP.

Common (row) output to drive LC.

O

Number of

Terminals

Carry signal I/O.
CIO1
CIO2 the SHL input. Output transition occurs on falling edge

This is set to input or output depending on the level of

I/O

of LP.
YD I Frame start/pulse input, with terminator. (*1) 1
F1, F2 I Drive pattern select signal input, with terminator. (*1) 2

LP I

Shift clock input for display data.

(Triggers on falling edge.) With terminator. (*1)

Shift direction select and CIO terminal I/O control input.

SHL Output Shift Direction

SHL I 1

L 1(9) → 120(108) Input Output

CIO

CIO1 CIO2

H 120(108) → 1(9) Output Input

The numbers in parentheses are for 100 output mode.

Select input for the number of COM output terminals:
SEL I

120 outputs ←→ 100 outputs

L: COM1 to COM120

H: COM9 to COM108
LSEL I

1/2 H operation select signal input.

L: Normal operation. H: 1/2 operation.

Chip select signal input for when a cascade connection
CSEL I

is used.

L: Leading chip

H: Other chips
FR I LC drive output AC signal input. With terminator (*1) 1

LC display blanking control input. With a low level input,
DOFF I

all common outputs are temporarily set to the V

The contents of the latches are maintained. With

C level.

terminator (*1)
TEST1 I Test1 signal input. Normally tied at L. 1

CC, GNDL,

V
GNDR GND: 0 V , VCC: +2.7 to 5.5 V

CL, VCR,

V

1L, +V1R,

+V

-V1L, -V1R,
VDDHL, VDDHR

Power source for logic:

Power

LC Drive Power:

Power

GND: 0 V, 8

DDH: + 14.0 to 42.0 V, VDDH ≥ +V1 ≥ VC ≥ –V1 ≥ GND

V
DM Dummy pad 11

Total 155

Note: *1

Input

120

2

1

1

1

1

1

3

TEST1

MLS Driver Chip Set EPSON 5–3
Technical Manual

SED1751

Block Diagram

V

DDHL

COM 1 COM 120

GNDL

+V1L

VCL

–V1L

DOFF

V

CC

TEST1

FR

F1
F2

Decoder

GNDR

+V1R

VCR

LCD Driver: 120-bits

–V1R

Level Shifter: 3x120-bits

Data Register:

120-bits

LP

YD

CIO1

SHL SEL LSEL CSEL

Bi-directional Shift Register: 30-bits

CIO2

5–4 EPSON MLS Driver Chip Set

Technical Manual

SED1751

Explanation of Each Block

Shift Register

This is a bi-directional shift register used for transmitting common data. The display data shifts on the
falling edge of LP.

Level Shifter

The level shifter is a voltage level converter circuit which converts the signal voltage level from a logic
system level to the LC driver system voltage level.

LCD Driver

The LCD driver outputs the LC drive voltage.
The relationship between the display blanking signal DOFF, the field recognition signals F1 & F2, the AC
signal FR, and the common output voltage is as follows:

DOFF HL

FR L H —

F1,F2 1,1 0,1 1,0 0,0 1,1 0,1 1,0 0,0 —

Line 1 +V1 +V1 –V1 +V1 –V1 –V1 +V1 –V1 VC
Line 2 –V1 +V1 +V1 +V1 +V1 –V1 –V1 –V1 VC
Line 3 +V1 –V1 +V1 +V1 –V1 +V1 –V1 –V1 VC
Line 4 +V1 +V1 +V1 –V1 –V1 –V1 –V1 +V1 VC

Voltage level relationships: + V1 > VC > –V1 (VC is the center voltage level)

MLS Driver Chip Set EPSON 5–5
Technical Manual

SED1751

Timing Diagram (1)

1/240 duty, normal operation.
SHL = L, SEL = L, LSEL = L, CSEL = L (This diagram provided only as a reference.)

240 lines

YD
LP
FR

1

2 3 4 5

120 121 122 123 240 1 2 3 4

LP
CIO 1
CIO 2

Driver 1

COM1

COM2

COM3

COM4

COM5

COM6

COM7

COM8

1 2 3 4 5 30 31 32 33 60 61 62 63 90 91 92 93 120 121 122 123

1 Frame (240 lines)

LP

Field 1 Field 2 Field 3

1 2 3 60 61 62 63 120 121 122 123 180 181 182 183 240 1 2 3

Field 4

FR

F1
F2

+V1

VC

–V1

+V1

VC

–V1

+V1

VC

–V1

+V1

VC

–V1

+V1

VC

–V1

+V1

VC

–V1

+V1

VC

–V1

+V1

VC

–V1

+V1

Driver 2

COM120

–V1

VC

5–6 EPSON MLS Driver Chip Set

Technical Manual

Timing Diagram (2)

1/240 duty, 1/2 H operation.
SHL = L, SEL = L, LSEL = H, CSEL = L (This diagram provided only as a reference.)

240 lines

YD
LP
FR

LP
CIO
CIO

Driver 1

COM1

COM2

COM3

COM4

COM5

COM6

COM7

COM8

1/1

2/1 1/2 2/2 1/3

1/1

1/2

1/3 1/30

2/1

1

2/2

1/120 2/120 1/121 2/121 2/240 1/1 2/1 1/2 2/2

1/31

1/60

1/61

1/90

2/30

2/31

2/60

2/61

2

1 Frame (240 lines)

Field 1 Field 2 Field 3

2/240 2/1 2/60 2/61 2/120 2/121 2/180 2/181 2/240 2/1

LP

1/1 1/1 1/61 1/62 1/121 1/122 1/181 1/182 1/1 1/1

FR

F1
F2

+V1

VC

–V1

+V1

VC

–V1

+V1

VC

–V1

+V1

VC

–V1

+V1

VC

–V1

+V1

VC

–V1

+V1

VC

–V1

+V1

VC

–V1

2/90

1/91

2/91

Field 4

1/120

2/120

SED1751

1/121

2/121

+V1

Driver 2

–V1

VC

COM120

MLS Driver Chip Set EPSON 5–7
Technical Manual

SED1751

ABSOLUTE MAXIMUM RATINGS

Item Signal Rated Value Units
Power voltage (1) VCC –0.3 to +7.0 V
Power voltage (2) VDDH –0.3 to + 45.0 V
Power voltage (3) ± V1, VC GND – 0.3 to VDDH + 0.3 V
Input voltage VI GND – 0.3 to VCC + 0.3 V
Output voltage VO GND – 0.3 to VCC + 0.3 V
CIO output current IO1 20 mA
Operating temperature Topr –30 to +85 °C
Storage temperature 1 Tstg1 –65 to +150 °C
Storage temperature 2 Tstg2 –55 to +100 °C

NOTE 1: The voltages are all relative to GND = 0 V.
NOTE 2: Storage temperature 1 is for the chip alone, and storage temperature 2 is for the TCP

NOTE 3: Ensure that the relationship between +V

product.

DDH ≥ +V1 ≥ VC ≥ –V1 ≥ GND.

V

1, VC, and –V1 is always as follows:

DDH

(+V1)

V

DDH

/2 (VC)

V

V

CC

GND (–V1)

Logic System

LCD System

NOTE 4: The LSI may be permanently damaged if the logic system power is floating or VCC is less

than or equal to 2.6 V when power is applied to the LC drive system. Special caution must
be paid to the power sequences during power up and power down.

5–8 EPSON MLS Driver Chip Set

Technical Manual

Electrical Characteristics

DC Characteristics

SED1751

Unless otherwise noted, GND = 0 V, V

Item Signal Parameter

Power Supply

Voltage (1)

Range Operating

Voltages

Power Supply

Voltage (2)

Power Supply

Voltage (3)

Power Supply

Voltage (4)
High-level Input

Voltage

Low-level Input

Voltage
High-level Output

Voltage

Low-level Output

Voltage 0.3mA

Input Leakage Current I

Input/Output Leakage

Current

Static Current I

Output Resistance RCOM Recommended

Average Operating
Consumption Current ICC

(1)

Average Operating V
Consumption Current I
(2) All other parameters

Input Terminal
Capacity

Input/Output Terminal
Capacity

V

CC VCC 2.7 5.0 5.5 V

V

DDH Function VDDH 8.0 42.0 V

+V

1 Recommended Value +V1 VDDH V

VC Recommended Value VC VDDH/2 V

–V

1 Recommended Value –V1 GND V

V

IH 0.8VCC V

V

CC = 2.7 to 5.5V

V

IL 0.2VCC V

VOH

CC = 2.7 to 5.5V

V

OL

V

LI GND ≤ VIN ≤ VCC 2.0 µA

LI/O GND ≤ VIN ≤ VCC CIO1,CIO2 5.0 µA

I

VDDH = 14.0~42.0V

GND

VIH = VCC, VIL = GND
∆V

ON = 0.5 V

parameter
V

CC = +5.0 V, VIH = VCC

IOH =
–0.3mA

IOL =

V

DDH =

+30.0V

DDH =

V
+40.0V

VIL = GND, fLP = 16.8 kHz

fFR = 70 Hz,

Input data: 1/240 No load

CC = 3.0 V

V
All other parameters 7 17
the same as VCC = 5.0 V.

V

DDH = +V1 = +30.0 V,
C = VDDH/2, –V1 = 0.0 V,

DDH VCC = 5.0 V VDDH 613µA

the same as the ICC item.

CI

Freq. = 1 MHz
Chip alone
Ta = 25°C

I/O

C

CC = + 5.0 V ± 10%, Ta = –30 to 85°C

Applicable

Terminals

CIO1,CIO2,FR,

YD,LP,SHL,SEL,

LSEL,CSEL,
DOFF,F1,F2,

TEST1

Min Typ Max Unit

CC–0.4 V

V

CIO1,CIO2

0.4 V

LP,YD,SHL,SEL,

LSEL,CSEL,F1,

F2,DOFF,TEST1,

FR

GND 25 µA

COM1 to
COM120

0.55 0.7

0.5 0.7

10 25

V

CC µA

LP,YD,SHL,SEL,

LSEL,CSEL,F1,F2,

DOFF,TEST1,FR

10 pF

CIO1,CIO2 18 pF

kΩ

MLS Driver Chip Set EPSON 5–9
Technical Manual

SED1751

Range of Operating Voltages: VCC – VDDH

It is necessary to set the voltage for VDDH within the VCC – VDDH operating voltage range shown in the
diagram below.

50

42
40

30
28

(V)

DDH

V

20

Range of
Operating

Voltage

10

8

0

2.0 3.02.7 4.0

5.0 6.05.5

VCC (V)

5–10 EPSON MLS Driver Chip Set

Technical Manual

SED1751

AC Characteristics

Input Timing Characteristics

FR

t

FRDStFRDH

F1, F2

LP

YD
CIO1, 2
(IN)

The FR latched at the nth LP is reflected in the output at the n+1th LP.

Item Signal Parameter Min Max Units

LP Frequency tCCL 500 ns
LP “H” Pulse Width tWCLH 55 ns
LP “L” Pulse Width tWCLL 330 ns
FR Setup Time tFRDS 100 ns
FR Hold Time tFRDH 40
F1, F2 Setup Time tFFDS 100
F1, F2 Hold Time tFFDH 40
Input Signal Rise Time tr50ns
Input Signal Fall Time tf50ns
CIO Setup Time tDS 100 ns
CIO Hold Time tDH 40 ns
YD → LP Allowable Time

t

FFDStFFDH

t

SET

t

t

DS

DH

t

r

t

WCLH

t

f

t

WCLD

t

CCL

(VCC = +5.0 V ± 10%, Ta = –30 to +85°C)

tSET 80 ns

(VCC = +2.7 V to 4.5 V, Ta = –30 to +85°C)

Item Signal Parameter Min Max Units

LP Frequency tCCL 800 ns
LP “H” Pulse Width tWCLH 100 ns
LP “L” Pulse Width tWCLL 660 ns
FR Setup Time tFRDS 200 ns
FR Hold Time tFRDH 80
F1, F2 Setup Time tFFDS 200
F1, F2 Hold Time tFFDH 80
Input Signal Rise Time tr 100 ns
Input Signal Fall Time tf 100 ns
CIO Setup Time tDS 200 ns
CIO Hold Time tDH 80 ns
YD → LP Allowable Time

MLS Driver Chip Set EPSON 5–11
Technical Manual

tSET 150 ns

SED1751

Output Timing Characteristics

LP

t

pdDOC

CIO1, 2
(OUT)

t

pdCCL

DOFF

t

pdCDOF

COM
Output

(VCC = 5.0 V ± 10%, VDDH = +14.0 to +42.0 V, Ta = –30 to +85°C)

Item Signal Parameter Min Max Units

Delay time from LP to CIO output tpdDOC

CL = 15 pF

Delay time from LP to COM output tpdCCL VDDH =350ns
Delay time from DOFF to COM output tpdCDOF

14.0 V to 40.0 V

300 ns

700 ns

(VCC = +2.7 V to 4.5 V, VDDH = +14.0 to +28.0 V, Ta = –30 to +85°C)

Item Signal Parameter Min Max Units

Delay time from LP to CIO output tpdDOC

CL = 15 pF

600 ns

Delay time from LP to COM output tpdCCL VDDH =500ns
Delay time from DOFF to COM output tpdCDOF

14.0 V to 40.0 V

1400 ns

5–12 EPSON MLS Driver Chip Set

Technical Manual

The Power Supply

Method of Forming Each Voltage Level

SED1751

V1

V

CC

GND

Logic System

LCD Controller

V

DDx

V

SSx

Logic System LCD System

SED1580D

Capacitor

Coupling

0B

V3
V2

VC
–V2
–V3

V

DDy

V

SSy

Logic System LCD System

SED1751D

VC

–V1

0B

When the SED1580 and the SED1751 are used to form an extremely low power module system, the power
relationships as shown in the figure above between the SED1580 and SED1751 logic systems, and the LCD
system power supply, and the LCD controller power supply are optimal.
In this case, care is required when it comes to signal propagation in the logic system.
LCD Controller → SED1580 Direct
LCD Controller → SED1751 Capacitor coupling is required
SED1580 → SED1751 Capacitor coupling is required
SED1751 → SED1580 Capacitor coupling is required

Cautions at Power Up and Power Down

Because the voltage level in the LCD system is high voltage, if the logic system power supply of this LSI
is floating or if V

CC is 2.6 V or less when the LCD system high voltage (30 V or above) is applied, or if

the LCD drive signal is output before the voltage level that is applied to the LCD system has stabilized,
then there is the risk that there will be an over current condition in this LSI, resulting in permanent damage
to this LSI.
It is recommended that the display OFF function (DOFF) is used until the LCD system voltage stabilizes
to insure that the LCD drive output power level is at the VC level.
Be sure to follow the sequences below when turning the power supplies ON and OFF:

When turning the power supply ON:

Logic system ON → LCD drive system ON, or simultaneously ON.

When turning the power supply OFF:

LCD drive system OFF → Logic system OFF, or simultaneously OFF.

As a countermeasure to guard against over current conditions, it is effective to insert a high-speed fuse or
a guard resistance in series with the LC power supply. The guard resistance value must be optimized
depending on the capacity of the LC cell.

MLS Driver Chip Set EPSON 5–13
Technical Manual

SED1751

Example of Connection

Large Screen LCD Structure Diagram

EIO1
BSEL
LSEL
F1O~F2O

F2S
F1S
SEL
CA
YD
FR
LP
XSCL
DOFF
D0~7
EIO2

EIO1
BSEL
LSEL
F1O~F2O

F2S
F1S
SEL
CA
YD
FR
LP
XSCL
DOFF
D0~7
EIO2

EIO1
BSEL
LSEL
F1O~F2O

F2S
F1S
SEL
CA
YD
FR
LP
XSCL
DOFF
D0~7
EIO2

EIO1
BSEL
LSEL
F1O~F2O

F2S
F1S
SEL
CA
YD
FR
LP
XSCL
DOFF
D0~7
EIO2

160

SED1580

160

SED1580

160

SED1580

160

SED1580

120

SED1751

CIO1YDLPFRDOFF

EIO2
D0~7

DOFF

XSCL

LP
FR
YD
CA

160

SHL
F1S

SED1580

F2S

F1O~F2O

LSEL
BSEL
EIO1

EIO2
D0~7

DOFF

XSCL

LP
FR
YD
CA

160

SHL
F1S

SED1580

F2S

F1O~F2O

LSEL
BSEL
EIO1

EIO2
D0~7

DOFF

XSCL

160

160

LP
FR
YD
CA

SHL
F1S

SED1580

F2S

F1O~F2O

LSEL
BSEL
EIO1

EIO2
D0~7

DOFF

XSCL

LP
FR
YD
CA

SHL
F1S

SED1580

F2S

F1O~F2O

LSEL
BSEL
EIO1

1/240 DUTY

640 × 480 DOT

120

SED1751

SHL

SEL

LSEL

CSEL

F1~F2

CIO2

CIO1YDLPFRDOFF

SHL

SEL

LSEL

CSEL

F1~F2

CIO2

120

SED1751

CIO1YDLPFRDOFF

120

SED1751

SHL

SEL

LSEL

CSEL

F1~F2

CIO2

CIO1YDLPFRDOFF

SHL

SEL

LSEL

CSEL

F1~F2

CIO2

DU0~7

LP

FR

YD

FS2

FS1

SHLU

XSCL

DOFF

SEL

SHL

LSEL

YSCL

Controller

SHLL

DL0~7

5–14 EPSON MLS Driver Chip Set

Technical Manual

Example of External Connections

SED1751

Detail drawing for the test pad section

Output terminal pattern shape

Specifications :

Base : Eupirex-S? , 75?u?m

Copper foil : 31P (14.25mm)

Sn plated

Product pitch : 31P (14.25mm)

Solder resist position tolerance : ±0.3

(Molding range) (Molding range)

(Molding range) (Molding range)

(Rear surface should
be P1 coated.)

(Rear surface

should be

P1 coated.)

(Rear surface should be P1 coated.) (Rear surface should be P1 coated.)

MLS Driver Chip Set EPSON 5–15
Technical Manual