Page 1
S1D13706 Embedded Memory LCD Controller
S5U13706P00C100 Evaluation Board
User Manual
Document Number: X31B-G-021-01
Status: Revision 1.1
Issue Date: 2009/03/03
© SEIKO EPSON CORPORATION 2007 - 2009. All Rights Reserved.
Information in this document is subject to change without notice. You may download and use this document, but only for your own use in
evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any
representation that the contents of this document are accurate or current. The Programs/Technologies described in this document may contain
material protected under U.S. and/or International Patent laws.
EPSON is a registered trademark of Seiko Epson Corporation. All other Trademarks are the property of their respective owners
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Table of Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3 Installation and Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.1 Configuration DIP Switches . . . . . . . . . . . . . . . . . . . . . . . . . .7
3.2 Configuration Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
4 CPU Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.1 CPU Interface Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.2 CPU Bus Connector Pin Mapping . . . . . . . . . . . . . . . . . . . . . . 12
5 LCD Interface Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6 Technical Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6.1 PCI Bus Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6.2 Direct Host Bus Interface Support . . . . . . . . . . . . . . . . . . . . . . 16
6.3 S1D13706 Embedded Memory . . . . . . . . . . . . . . . . . . . . . . . . 16
6.4 Software Adjustable LCD Backlight Intensity Support Using PWM . . . . . . . . . 16
6.5 Passive/Active LCD Panel Support . . . . . . . . . . . . . . . . . . . . . . 17
6.5.1 Buffered LCD Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.5.2 Extended LCD Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.6 External oscillator support for CLKI and CLKI2 . . . . . . . . . . . . . . . . . 17
7 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
7.1 Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
7.2 Document Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
8 Parts List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
9 Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
10 Board Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
11 Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
11.1 EPSON LCD Controllers (S1D13706) . . . . . . . . . . . . . . . . . . . . . 28
S5U13706P00C100 Evaluation Board User Manual S1D13706
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1 Introduction
This manual describes the setup and operation of the S5U13706P00C100 Evaluation
Board. The board is designed as an evaluation platform for the S1D13706 Embedded
Memory LCD Controller.
This user manual is updated as appropriate. Please check the Epson Research and Development website at www.erd.epson.com for the latest revision of this document before
beginning any development.
We appreciate your comments on our documentation. Please contact us via email at
documentation@erd.epson.com.
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2 Features
Following are some features of the S5U13706P00C100 Evaluation Board:
• 100-pin TQFP S1D13706F00A Embedded Memory LCD Controller with 80K bytes of
embedded SRAM.
• Headers for connecting to various Host Bus Interfaces.
• Configuration options.
• Software adjustable backlight intensity support.
• 4/8-bit 3.3V or 5V single monochrome passive LCD panel support.
• 4/8/16-bit 3.3V or 5V single color passive LCD panel support.
• 9/12/18-bit 3.3V or 5V active matrix TFT LCD panel support.
• Direct interface for 18-bit Epson D-TFD LCD panel support.
• Direct interface for 18-bit Sharp HR-TFT LCD panel support.
• Software initiated power save mode.
• Hardware or software Video Invert support.
• External oscillator for CLKI and CLKI2.
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DIP Switch - SW1
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3 Installation and Configuration
The S5U13706P00C100 is designed to support as many platforms as possible. The
S5U13706P00C100 incorporates a DIP switch and three jumpers which allow both the
evaluation board and S1D13706 LCD controller t o be configured fo r a specified ev aluation
platform.
3.1 Configuration DIP Switches
The S1D13706 has configuration inputs (CNF[7:0]) which are read on the rising edge of
RESET#. In order to configure the S1D13706 for multiple Host Bus Interfaces a tenposition DIP switch (S1) is provided. The following figure shows the location of DIP
switch SW1 on the S5U13706P00C100.
Figure 3-1: Configuration DIP Switch (SW1) Location
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The S1D13706 has 8 con figur ation input s (CNF[7: 0]) which ar e re ad on t he risi ng edge of
RESET#. All S1D13706 configuration inputs are fully configurable using a ten position
DIP switch as described below.
Table 3-1: Configuration DIP Switch Settings
Value on this pin at rising edge of RESET# is used to configure:
Closed (On/1) Open (Off/0)
CNF2 CNF1 CNF0 Host Bus Interface
000 SH-4/SH-3
0 0 1 MC68K #1
0 1 0 MC68K #2
0 1 1 Generic #1
1 0 0 Generic #2
101 RedCap 2
1 1 0 DragonBall
111 Reserved
Little Endian bus interface
CNF7 CNF6 CLKI to BClk Divide Ratio
00 1 : 1
01 2 : 1
10 3 : 1
11 4 : 1
1
Hardware Video Invert - normal video data
1
1
S1D13706
Signal
Select host bus interface as follows:
Note: The host bus interface is 16-bit.
CLKI to BClk divide select:
- Hardware Video Invert - invert video data
Switch
SW1-[3:1] CNF[2:0]
SW1-4 CNF3 Enable GPIO pins Enable additional pins for D-TFD/HR-TFT
SW1-5 CNF4 Big Endian bus interface
SW1-6 CNF5 WAIT# is active high WAIT# is active low
SW1-[8:7] CNF[7:6]
SW1-9
SW1-10 - Disable FPGA for non-PCI host Enable FPGA for PCI host
= Required settings when used with PCI Bridge FPGA
1
To enable the Hardware Video Invert function the following are required:
• GPIO pins must be enabled (S1-4 closed).
• GPIO0 must be connected to S1-9 (Jumper JP1 set to 1-2).
• GPIO Pin Input Enable (REG[A9h] bit 7) must be set to 1b.
• GPIO0 Pin IO Configuration (REG[A8h] bit 0) must be set to 0b.
• Hardware Video Invert Enable bit (REG[70h] bit 5) must be set to 1b.
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Note
JP1
GPIO0 connected
GPIO0 disconnected
to SW1-9
from SW1-9
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3.2 Configuration Jumpers
The S5U13706P00C100 has seven jumper blocks which configure various setting on the
evaluation board. The jumper positions for each function are shown below.
Table 3-2: Jumper Summary
Jumper Function Position 1-2 Position 2-3 No Jumper
GPIO0 connected to
JP1 GPIO0 Connection
JP4 GP0 Polarity on H1
JP6 LCD Panel Voltage +5V LCDVCC +3.3V LCDVCC —
= recommended settings
SW1-9 for hardware vide o
invert
Normal (Active High) Inverted (Active Low) —
—
JP1 - GPIO0 Connection
JP1 selects whether GPIO0 is connected to SW1-9. SW1-9 is used t o enable hardware video
invert on the S1D13706.
When the jumper is on (position 1-2), SW1-9 controls the hardware video invert feature
(default setting).
When the jumper is off, t he har dware vi deo inv ert f eature is di sabled . This se ttin g must be
used for HR-TFT and D-TFD pane ls as GPIO0 is required for both panel s. For detail s, refer
to the S1D13706 Hardware Functional Specification, document number X31B-A-001-xx.
GPIO0 disconnected from
SW1-9 for direct
HR-TFT/D-TFD or GPIO
testing
When configured for Sharp HR-TFT or Epson D-TFD panels, JP1 must be set to no
jumper and JP6 must be set to position 2-3.
Figure 3-2: Configuration Jumper (JP1) Location
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JP4
Inverted
Normal
JP6
5.0V 3.3V
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JP4 - GPO Polarity on H1
JP4 selects the polarity of the GPO signal available on LCD Connector H1.
Position 1-2 sends the GPO signal directly to H1 (default setting).
Position 2-3 inverts the GPO signal before sending it to H1.
Figure 3-3: Configuration Jumper (JP4) Location
JP6 - LCD Panel Voltage
JP6 selects the voltage level to the LCD panel.
Position 1-2 sets the voltage level to 5.0V.
Position 2-3 sets the voltage level to 3.3V (default setting).
When configured for Sharp HR-TFT or Epson D-TFD panels, JP1 must be set to no
jumper and JP6 must be set to position 2-3.
Figure 3-4: Configuration Jumper (JP6) Location
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4 CPU Interface
4.1 CPU Interface Pin Mapping
Table 4-1: CPU Interface Pin Mapping
Motorola
S1D13706
Pin Name
Generic #1 Generic #2
Hitachi
SH-3 /SH-4
Motorola
MC68K #1
Motorola
MC68K #2
Motorola
REDCAP2
AB[16:1] A[16:1] A[16:1] A[16:1] A[16:1] A[16:1] A[16:1] A[16:1]
AB0 A0
1
A0 A0
DB[15:0] D[15:0] D[15:0] D[15:0] D[15:0] D[15:0]
1
LDS# A0 A0
2
1
D[15:0] D[15:0]
CS# External Decode CSn# External Decode CSn# CSA#
M/R# External Decode
CLKI BUSCLK BUSCLK CKIO CLK CLK CLK CLK
BS# Connected to V
RD/WR# RD1#
3
DD
Connected to
3
V
DD
RD# RD0# RD# RD#
WE0# WE0# WE# WE0#
BS# AS# AS# Connected to V
RD/WR# R/W# R/W# R/W#
Connected to
Connected to
3
V
DD
3
V
DD
SIZ1 OE# OE#
SIZ0 EB1# LWE#
WE1# WE1# BHE# WE1# UDS# DS# EB0# UWE#
WAIT# WAIT# WAIT#
WAIT#/
RDY#
DTACK# DSACK1# N/A DTACK#
RESET# RESET# RESET# RESET# RESET# RESET# RESET# RESET#
MC68EZ328/
MC68VZ328
DragonBall
1
A0
3
DD
Connected to
3
V
DD
1
A0 for these busses is not used internally by the S1D 13706.
2
If the target MC68K bus is 32-bit, then these signals should be connected to D[31:16].
3
These pins are not used in their corresponding Host Bus Interface mode. Systems are
responsible for externa lly connecting them to the host interf ace IO V
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4.2 CPU Bus Connector Pin Mapping
Table 4-2: CPU Bus Connector (H3) Pinout
Connector
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
Comments
Connecte d to DB0 of the S1D13706
Connecte d to DB1 of the S1D13706
Connecte d to DB2 of the S1D13706
Connecte d to DB3 of the S1D13706
Ground
Ground
Connecte d to DB4 of the S1D13706
Connecte d to DB5 of the S1D13706
Connecte d to DB6 of the S1D13706
Connecte d to DB7 of the S1D13706
Ground
Ground
Connecte d to DB8 of the S1D13706
Connecte d to DB9 of the S1D13706
Connected to DB10 of the S1D13706
Connected to DB11 of the S1D13706
Ground
Ground
Connected to DB12 of the S1D13706
Connected to DB13 of the S1D13706
Connected to DB14 of the S1D13706
Connected to DB15 of the S1D13706
Connected to RESET# of the S1D13706
Ground
Ground
Ground
+12 volt supply
+12 volt supply
Connected to WE0# of the S1D13706
Connected to WAIT# of the S1D13706
Connecte d to CS# of the S1D13706
Connected to MR# of the S1D13706
Connected to WE1# of the S1D13706
Connected to TXVDD1
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Connector
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
Table 4-3: CPU Bus Connector (H4) Pinout
Comments
Connected to A0 of the S1D13706
Connected to A1 of the S1D13706
Connected to A2 of the S1D13706
Connected to A3 of the S1D13706
Connected to A4 of the S1D13706
Connected to A5 of the S1D13706
Connected to A6 of the S1D13706
Connected to A7 of the S1D13706
Ground
Ground
Connected to A8 of the S1D13706
Connected to A9 of the S1D13706
Connected to A10 of the S1D13706
Connected to A11 of the S1D13706
Connected to A12 of the S1D13706
Connected to A13 of the S1D13706
Ground
Ground
Connected to A14 of the S1D13706
Connected to A15 of the S1D13706
Connected to A16 of the S1D13706
Not connected
Not connected
Not connected
Ground
Ground
+5 volt supply
+5 volt supply
Connected to RD/WR# of the S1D13706
Connected to BS# of the S1D13706
Connected to BUSCLK of the S1D13706
Connected to RD# of the S1D13706
Not connected
Not connected
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5 LCD Interface Pin Mapping
Table 5-1: LCD Signal Connector (H1)
Monochrome
Passive
Pin
Name
Connector
Pin No.
Single
4-bit 8-bit 4-bit 8-bit 8-bit 16-Bit 9-bit 12-bit 18-bit 18-bit 18-bit
FPDAT0 1 driven 0 D0 driven 0 D0 (B5)1D0 (G3)1D0 (R6)
FPDAT1 3
FPDAT2 5
FPDAT3 7
FPDAT4 9 D0 D4 D0 ( R2)
FPDAT5 11 D1 D5 D1 (B1)
FPDAT6 13 D2 D6 D2 (G1)
FPDAT7 15 D3 D7 D3 (R1)
FPDAT8 17
FPDAT9 19
FPDAT10 21
FPDAT11 23
FPDAT12 25
FPDAT13 27
FPDAT14 29
FPDAT15 31
FPDAT16 4
FPDAT17 6
FPSHIFT 33 FPSHIFT CLK XSCL
DRDY 35 & 38 MOD FPSHIFT2 MO D DRDY
FPLINE 37 FPLINE LP LP
FPFRAME 39 FPFRAME SPS DY
GND
PWMOUT 28 PWMOUT
VCC 32 LCDVCC (3.3V / 5.0V)
+12V 34 +12V
GPO 40 GPO
2, 8, 14, 20,
26
NC 30 Not connected
NC 36 Not connected
driven 0 D1 driven 0 D1 (R5)1D1 (R3)1D1 (G5)
driven 0 D2 driven 0 D2 (G4)1D2 (B2)1D2 (B4)
driven 0 D3 driven 0 D3 (B3)1D3 (G2)1D3 (R4)
driven 0 driven 0 driven 0 driven 0 driven 0 D4 (G3)
driven 0 driven 0 driven 0 driven 0 driven 0 D5 (B2)1driven 0 R0 R2 R2 R2
driven 0 driven 0 driven 0 driven 0 driven 0 D6 (R2)1driven 0 dr iven 0 R1 R 1 R1
driven 0 driven 0 driven 0 driven 0 driven 0 D7 (G1)1driven 0 dr iven 0 R0 R 0 R0
driven 0 driven 0 driven 0 driven 0 driven 0 D12 (R3)1driven 0 G0 G2 G 2 G2
driven 0 driven 0 driven 0 driven 0 driven 0 D13 (G2)1driven 0 dr iven 0 G1 G1 G1
driven 0 driven 0 driven 0 driven 0 driven 0 D14 (B1)1driven 0 dr iven 0 G0 G0 G0
driven 0 driven 0 driven 0 driven 0 driven 0 D15 (R1)1driven 0 B0 B2 B2 B2
driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 B1 B1 B1
driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 B0 B0 B0
Color Passive Panel Color TFT Panel
Single
Format 1 Format 2
1
R2 R3 R5 R5 R5
1
R1 R2 R4 R4 R4
1
R0 R1 R3 R3 R3
1
1
D4 (R3)1D4 (R2)1D8 (B5)
1
D5 (G2)1D5 (B1)1D9 (R5)
1
D6 (B1)1D6 (G1)1D10 (G4)
1
D7 (R1)1D7 (R1)1D11 (B3)
GND
2
(for controlling on-board LCD bias power supply on/off) MOD
G2 G3 G5 G5 G5
1
G1 G2 G4 G4 G4
1
G0 G1 G3 G3 G3
1
B2 B3 B5 B5 B5
1
B1 B2 B4 B4 B4
1
B0 B1 B3 B3 B3
Others
Sharp
HR-TFT
connect
no
Epson
1
D-TFD
GCP
3
GPO
1
2
1
These pin mappings use signal names commonly used for each panel type, however
signal names may differ between panel manufacturers. The values shown in brackets
represent the color components as mapped to the corresponding FPDATxx signals at
the first valid edge of FPSHIFT. For further FPDATxx to LCD interface mapping, see
the S1D13706 Hardware Functional Specification, document number
X31B-A-001-xx.
2
GPO on H1 can be inverted by setting JP4 to 2-3.
3
The Sharp HR-TFT MOD signal controls the panel power. This must not be confused
with the MOD signal used on many passive panels.
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Table 5-2: Extended LCD Signal Connector (H2)
Monochrome
Pin
Name
GPIO0 1 GPIO0 PS XINH
GPIO1 3 GPIO1 CLS YSCL
GPIO2 5 GPIO2 REV FR
GPIO3 7 GPIO3 SPL FRS
GPIO4 9 GPIO4 GPIO4 RES
GPIO5 11 GPIO5 GPIO5 DD_P1
GPIO6 13 GPIO6 GPIO6 YSCLD
CVOUT 15 CVOUT
GND
Connector
Pin No.
2, 4, 6, 8, 10,
12, 14, 16
Passive Panel
Single
4-bit 8-bit 4-bit 8-bit 8-bit 16-Bit 9-bit 12-bit 18-bit 18-bit 18-bit
1
When dip switch SW1-4 is open (CNF3 = 0 at RESET#), GPIO[6:0] are at low output
Color Passive Panel Color TFT Panel
Single
Format 1 Format 2
GND
Others HR-TFT
1
D-TFD
1
states after reset. If REG[10h] bits 1-0 are set for either HR-TFT or D-TFD, some
of the pins are used for the HR-TFT or D-TFD interfaces and are not available as
GPIO pins.
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6 Technical Description
6.1 PCI Bus Support
The S1D13706 does not have on-chip PCI bus int erfa ce suppo rt. The S1D1370 6P00C1 00
uses the PCI Bridge FPGA to support the PCI bus.
6.2 Direct Host Bus Interface Support
The S5U13706P00C100 is specifically designed to work using the PCI Bri dge FPGA i n a
standard PCI bus envir onment. However , the S1D13706 directl y supports many other host
bus interfaces. Connectors H3 and H4 provide the necessary IO pins to interface to these
host buses. For further information on the host bus interfaces supported, see “CPU
Interface” on page 11.
The PCI Bridge FPGA must be disabled using SW1-10 in o rde r for direct host bus int er faces to operate properly.
6.3 S1D13706 Embedded Memory
The S1D13706 has 80K bytes of embedded SRAM. The 80K byte display buffer address
space is directly and contiguously available through the 17-bit address bus.
6.4 Software Adjustable LCD Backlight Intensity Support Using PWM
The S1D13706 provides Pulse Width Modulati on output on PWMOUT. PWMOUT can be
used to control LCD panels which support PWM control of the backlight inverter. The
PWMOUT signal is provided on the buffered LCD connector (H1).
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6.5 Passive/Active LCD Panel Support
The S1D13706 directly supports:
• 4/8-bit single monochrome passive panels.
• 4/8/16-bit single color passive panels.
• 9/12/18-bit TFT active matrix panels.
• 18-bit Sharp HR-TFT panels.
• 18-bit Epson D-TFD panels.
All the necessary signals are provided on the 40-pin LCD connector, H1, and 16-pin
Extended LCD Connector, H2. For co nnection inf ormation, see Sect ion 5, “ LCD Interfa ce
Pin Mapping” on page 14.
The S5U13706P00C100 does not provi de a power supply fo r the LCD bias volta ge needed
by passive LCD panels. An external power supply is required to provide the bias LCD
voltage to the LCD panel.
6.5.1 Buffered LCD Connector
The buffered LCD connector (H1) provides the same LCD panel signals as those directly
from S1D13706, but with voltage-adapting buffers selectable to 3.3V or 5.0V. Pin 32 on
this connector provi des a voltage level of 3.3V or 5.0V to the LCD panel logic (see “JP6 LCD Panel Voltage” on page 10 for information on setting the panel voltage).
6.5.2 Extended LCD Connector
The S1D13706 directly supports Sharp 18-bit HR-TFT and Epson 18-bit D-TFD panels.
The extended LCD connector (H2) provides the extra signals required to support these
panels. The signals o n th is connector are also buffered f ro m the S1D13706 and adjustable
to 3.3V or 5.0V (see “JP6 - LCD Panel Volt age” o n page 10 f or detail s on set ting the panel
voltage).
6.6 External oscillator support for CLKI and CLKI2
The S1D13706 uses CLKI and CLKI2 signa ls provided by two +5V oscillators. Th e os ci llators are mounted o n the evaluat ion board in 1 4-pin DIP so ckets. The 5V cl ock signals a re
shifted to 3.3V which is accepted by the S1D13706.
S5U13706P00C100 Evaluation Board User Manual S1D13706
Issue Date: 2009/03/03 X31B-G-021-01
Revision 1.1
Page 18
Page 18 Epson Research and Development
Vancouver Design Center
7 References
7.1 Documents
• Epson Research and Development, Inc., S1D1370 6 Hardware Function al Specifi cation ,
document number X31B-A-001-xx.
• Epson Research and Development, Inc., S1D13706 Programming Notes and Examples,
document number X31B-G-003-xx.
7.2 Document Sources
• Epson Research and Development: http://www.erd.epson.com.
S1D13706 S5U13706P00C100 Evaluation Board User Manual
X31B-G-021-01 Issue Date: 2009/03/03
Revision 1.1
Page 19
Epson Research and Development Page 19
Vancouver Design Center
8 Parts List
Table 8-1: Parts List
Item Qty Reference Part Description
C1, C2, C3, C4, C5, C6,
C7, C8, C9, C10, C11,
116
2 0 C26, C12 10u 10V 10u 10V
3 0 C15, C14 n/p 1206 pckg.
4 0 C22, C28 22u 10V
59
6 0 C24, C32 10u 63V
7 4 C30, C34, C35, C37 68u 10V
80 C31 1n
9 2 C36, C33 33u 20V
10 0 D2, D1 1N5819
11 1 H1 HEADER 20X2
12 1 H2 HEADER 8X2
13 2 H4, H3 HEADER 17X2
14 1 JP7, JP1 HEADER 2
15 2
16 0 L2, L1 47uH
17 0 Q1 MMBT3906 PNP Transistor / SOT-23
C13, C16, C17, C18,
C19, C20, C21, C25,
C27, C29
C23, C38, C39, C40,
C41, C42, C43, C44,
C45, C46
JP2, JP3, JP4, JP5,
JP6
0.1u
0.22uF
HEADER 3
50V X7R +/-5%, 1206
pckg.
Tantalum C-Size, 10V +/-
10%
Ceramic Chip 0.22uF,
50V, X7R +/-5%, 1206
pckg
Electrolytic, Radial Lead
63V +/-20%
Tantalum D-Size,
68uF,10V, +/-10%
50V X7R +/-5%, 1206
pckg
Tantalum D-Size,
33uF,20V, +/-10%
Schottky Barrier Rectifier,
MELF pckg.
20x2, shrouded header,
keyed, straight
8x2, shrouded header,
keyed, straight
17x2, 0.1” pitch, .025” sq.
unshrouded header
2x1 .1” pitch unshrouded
header
3x1 .1” pitch unshrouded
header
Shielded SMT power
inductor, +/-20%, 1.17A,
0.18 ohm
Manufacturer / P art No. /
Assembly Instruc tion s
Panasonic-ECG ECJ-
3VB1H104K. Do not
populate C9, C10, C11,
C25, C27
Do not purchase. Do not
populate.
Do not purchase. Do not
populate.
Do not purchase. Do not
populate.
Kemet C1206C224J5RAC
or equivalent capacitor
Do not purchase. Do not
populate.
Kemet T491D686K010 AS
(altern -Panasonic
ECST1AD686R (Digikey).
Do not purchase. Do not
populate.
Kemet T491D336K020 AS
(altern -Panasonic
ECST1AD336R (Digikey)
Do not purchase. Do not
populate.
Samtec TST-120-01-G-D
Samtec TST-108-01-G-D
Samtec TSW-117-05-G-D
Do not populate JP7
Do not populate JP2, JP3 ,
JP5
Do not purchase. Do not
populate.
Do not purchase. Do not
populate.
S5U13706P00C100 Evaluation Board User Manual S1D13706
Issue Date: 2009/03/03 X31B-G-021-01
Revision 1.1
Page 20
Page 20 Epson Research and Development
Vancouver Design Center
Table 8-1: Parts List
Item Qty Reference Part Description
18 0 Q2 MMFT3055VL
19 0 Q3 FZT792A
20 0 Q4, Q5 MMBT2222A
21 14
R1-R9, R33, R36, R37,
R38, R39
15K 1206 / 5%
N-channel FET, SOT -223
pckg.
High gain transistor, SOT-
223 pckg.
NPN transistor, SOT-23
pckg.
Manufacturer / P art No. /
Assembly Instructions
Do not purchase. Do not
populate.
Do not purchase. Do not
populate.
Do not purchase. Do not
populate.
R10, R11, R12, R13,
22 9
R14, R15, R16, R17,
330K 1206 / 5%
R18
23 0 R19 12.4K 1% 1206 / 1%, E-96 series
24 0 R20, R21 80K 1206 / 5%
25 0 R22 402 1% 1206 / 1%, E-96 series
26 0 R23 301 1% 1206 / 1%, E-96 series
27 0 R24 200 POT Trim POT
28 0 R25 0.22 1/4W 1210 / 5% / 1/4W
29 0 R26 470 1206 / 5%
30 0 R27 22K 1206 / 5%
Do not purchase. Do not
populate.
Do not purchase. Do not
populate.
Do not purchase. Do not
populate.
Do not purchase. Do not
populate.
Do not purchase. Do not
populate.
Do not purchase. Do not
populate.
Do not purchase. Do not
populate.
Do not purchase. Do not
populate.
31 1 R28, R29, R32 100K 1206 / 5% Do not populate R28, R29
32 0 R30 1.2M 1206 / 5%
33 0 R31 500K POT Trim POT
Do not purchase. Do not
populate.
Do not purchase. Do not
populate.
34 3 R34, R35, R40, R41 1K 1206 / 5% Do not populate R41
35 1 SW1 SW DIP-10 Dip Switch 10-Position
36 0 S1 SW DIP-4 DIP switch, 4-position
37 1 U1 S1D13706F00A
38 0 U2 LT1117CST-5
100-pin TQFP15 surface
mount package
5V fixed voltage regulator,
SOT-223
39 1 U3 74AHC04 SO-14 package
40 0 U4 ICD2061A Wide SO-16 package
Grayhill 76SB10ST
(Digikey GH1117-ND)
Do not purchase. Do not
populate.
Do not purchase. Do not
populate.
TI 74AHC04, SO-14
package
Do not purchase. Do not
populate.
S1D13706 S5U13706P00C100 Evaluation Board User Manual
X31B-G-021-01 Issue Date: 2009/03/03
Revision 1.1
Page 21
Epson Research and Development Page 21
Vancouver Design Center
Table 8-1: Parts List
Item Qty Reference Part Description
41 2 U6, U5 Test Socket
14 pin narrow DIP, screw
machine socket
Manufacturer / P art No. /
Assembly Instruc tion s
42 4 U7, U8, U9, U10 74HCT244 Buffer, SO-20 package TI74HCT244 or equivalent
43 0 U11 MAX754 16 pin narrow SO pckg.
3.3V fixed voltage
44 1 U12 LT1117CM-3.3
regulator, 3 Lead Plastic
DD
45 0 U13 MAX749 8 pin SO pckg.
Do not purchase. Do not
populate.
Linear Technology
LT1117CM-3.3
Do not purchase. Do not
populate.
46 1 U14 EPF6016TC144-2 144-pin QFP Altera EPF6016TC144-2
47 1 U15 8-pin DIP socket 8-pin DIP socket Machined socket, 8-pin
48 1 (U15) EPC1PI8N 8-pin DIP pckg
49 0 Y1 14.31818MHz Vertical-mount HC-49
Altera EPC1PI8N,
programmed, socketed
Do not purchase. Do not
populate.
50 3 (JP1), (JP4), (JP6) Micro Shunt
51 1 Bracket
Computer Bracket, Bl ank -
PCI
Keystone - Cat. No. 9203
Screw, pan head, # 4-40 x
52 2 Screw Pan head, #4-40 x 1/4”
1/4”-please assemble
bracket onto board
53 2
Resistor SMD 0805
0ohm
0 0805 Resistor, 0 ohm
54 1 (U6) 50MHz Oscillator DIP14, 50MHz
55 1 (U5) 6.5MHz Oscillator DIP14, 6.5MHz
please mount on solder
side to short pins 2-3 of
JP2 and JP3
Epson SG8002DB,
50MHz, socketed
Epson SG8002DB,
6.5MHz, socketed
S5U13706P00C100 Evaluation Board User Manual S1D13706
Issue Date: 2009/03/03 X31B-G-021-01
Revision 1.1
Page 22
Page 22 Epson Research and Development
5
5
4
4
3
3
2
2
1
1
D
D
C
C
B B
A A
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB8
DB9
DB10
DB11
DB12
DB13
DB14
DB15
AB[16:0]
DB[15:0]
FPDAT13
FPDAT5
FPDAT8
FPDAT1
FPDAT0
FPDAT16
FPDAT14
FPDAT11
FPDAT17
FPDAT3
FPDAT7
FPDAT9
FPDAT4
FPDAT2
FPDAT10
FPDAT6
FPDAT12
FPDAT15
GPIO0
AB0
AB1
AB2
AB3
AB4
AB5
AB6
AB7
AB8
AB9
AB10
AB11
AB12
AB13
AB14
AB15
AB16
+3.3V
+3.3V
AB[16:0]
4,5
DB[15:0]
4,5
CLKI22CLKI
2,4,5
WAIT#
4,5
RD/WR#
4,5
RESET#
4,5
WE1#
4,5
WE0#
4,5
RD#
4,5
BS#
4,5
M/R#
4,5
CS#
4,5
FPDAT[17:0]
3
FPFRAME3FPLINE3FPSHIFT3DRDY3CVOUT3PWMOUT3GPO3GPIO03GPIO13GPIO23GPIO33GPIO43GPIO53GPIO6
3
nCONFIG
5
Title
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B
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Title
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Date:
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<Doc>
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B
15Monday, March 05 , 2007
R12
330K
R12
330K
R10
330K
R10
330K
R4
15KR415K
R13
330K
R13
330K
U1
S1D13706F00AU1S1D13706F00A
AB05AB14AB2
3
AB3
2
AB499AB598AB697AB796AB895AB9
94
AB1093AB1192AB12
91
AB13
90
AB1489AB15
88
AB16
87
DB035DB134DB2
33
DB3
32
DB4
31
DB530DB6
29
DB7
28
DB827DB924DB10
23
DB1122DB12
21
DB1320DB14
19
DB15
18
CLKI
15
CLKI2
77
CS#
6
M/R#
7
BS#
8
RD#
9
WE0#
10
WE1#
11
RD/WR#
12
RESET#13WAIT#
17
CNF0
85
CNF184CNF283CNF382CNF481CNF580CNF679CNF7
78
FPDAT0
55
FPDAT1
56
FPDAT2
57
FPDAT3
58
FPDAT4
59
FPDAT560FPDAT6
61
FPDAT7
64
FPDAT8
65
FPDAT9
66
FPDAT10
67
FPDAT11
68
FPDAT12
69
FPDAT13
70
FPDAT14
71
FPDAT15
72
FPDAT16
73
FPDAT17
74
FPFRAME
52
FPLINE
53
FPSHIFT
54
DRDY
48
CVOUT
46
PWMOUT
38
GP0
47
GPIO0
45
GPIO144GPIO2
43
GPIO3
42
GPIO4
41
GPIO5
40
GPIO6
39
TESTEN
86
VSS
14
VSS
25
VSS
36
VSS
50
VSS
62
VSS
75
VSS
100
HIOVDD
16
HIOVDD
26
NIOVDD
37
NIOVDD
49
NIOVDD
63
NIOVDD
76
COREVDD
1
COREVDD
51
R14
330K
R14
330K
C1
0.1uC10.1u
C2
0.1uC20.1u
R15
330K
R15
330K
C3
0.1uC30.1u
R16
330K
R16
330K
R9
15KR915K
C4
0.1uC40.1u
R17
330K
R17
330K
R6
15KR615K
R18
330K
R18
330K
C5
0.1uC50.1u
C6
0.1uC60.1u
C7
0.1uC70.1u
R7
15KR715K
C8
0.1uC80.1u
SW1
SW DIP-10
SW1
SW DIP-10
123456789
201918171615141312
1110
R3
15KR315K
R5
15KR515K
JP1
HEADER 2
JP1
HEADER 2
1
2
R2
15KR215K
R8
15KR815K
R1
15KR115K
R11
330K
R11
330K
Vancouver Design Center
9 Schematics
Figure 9-1: S5U13706P00C100 Schematics (1 of 5)
S1D13706 S5U13706P00C100 Evaluation Board User Manual
X31B-G-021-01 Issue Date: 2009/03/03
Revision 1.1
Page 23
Epson Research and Development Page 23
5
5
4
4
3
3
2
2
1
1
D
D
C
C
B B
A A
+5V
+5V
+3.3V
+3.3V
+3.3V
+3.3V
+3.3V
+3.3V
+3.3V
+5V
+5V
LCDVCC
CLKI 1,4,5
CLKI2
1
BUSCLK1,4,5
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S5U13706P00C100 - Clocks and Power Supplies
B
25Monday, Marc h 05, 2007
For U3
1 2 5.0V LCD Panels
2 3 3.3V LCD Panels
U12
LT1117CM-3 .3
U12
LT1117CM-3 .3
VIN
3
ADJ
1
VOUT
2
JP6
HEADER 3
JP6
HEADER 3
1
2
3
U6
Test SocketU6Test Socket
NC
1
OUT
8
GND
7
VCC
14
U3F
74AHC04
U3F
74AHC04
13 12
14
7
C16
0.1u
C16
0.1u
U5
Test SocketU5Test Socket
NC
1
OUT
8
GND
7
VCC
14
C17
0.1u
C17
0.1u
C13
0.1u
C13
0.1u
C29
0.1u
C29
0.1u
+C30
68u 10V
+C30
68u 10V
U3B
74AHC04
U3B
74AHC04
3 4147
U3C
74AHC04
U3C
74AHC04
5 6147
U3D
74AHC04
U3D
74AHC04
9 8147
U3A
74AHC04
U3A
74AHC04
1 2147
Vancouver Design Center
S5U13706P00C100 Evaluation Board User Manual S1D13706
Issue Date: 2009/03/03 X31B-G-021-01
Figure 9-2: S5U13706P00C100 Schematics (2 of 5)
Revision 1.1
Page 24
Page 24 Epson Research and Development
5
5
4
4
3
3
2
2
1
1
D
D
C
C
B B
A A
FPDAT6
FPDAT0
FPDAT1
FPDAT5
FPDAT4
FPDAT2
FPDAT7
FPDAT3
FPDAT14
FPDAT13
FPDAT15
FPDAT11
FPDAT12
FPDAT9
FPDAT8
FPDAT10
FPDAT16
FPDAT17
BFPDAT[17: 0]FPDAT[17:0]
BFPDAT12
BFPDAT5
BFPDAT15
BFPDAT12
BFPDAT10
BFPDAT3
BFPDAT6
BFPDAT0
BFPDAT15
BFPDAT9
BFPDAT5
BFPDAT10
BFPDAT14
BFPDAT11
BFPDAT7
BFPDAT1
BFPDAT0
BFPDAT2
BFPDAT17
BFPDAT6
BFPDAT14
BFPDAT11
BFPDAT8
BFPDAT4
BFPDAT7
BFPDAT16
BFPDAT2
BFPDAT13
BFPDAT8
BFPDAT1
BFPDAT9
BFPDAT13
BFPDAT3
BFPDAT4
BFPDAT16
BFPDAT17
LCDVCC
LCDVCC
LCDVCC
+12V
LCDVCC
LCDVCC
+3.3V
FPDAT[17:0]
1
GPIO3
1
CVOUT1GPIO41GPIO51GPIO21GPIO11GPIO6
1
GPIO0
1
GPO
1
PWMOUT
1
FPSHIFT1DRDY
1
FPFRAME1
FPLINE
1
Title
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C19
0.1u
C19
0.1u
H1
HEADER 20X2H1HEADER 20X2
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
U7
74HCT244U774HCT244
1A121A2
4
1A3
6
1A4
8
2A1
11
2A2
13
2A3
15
2A4171G
1
2G
19
1Y1
18
1Y2
16
1Y3
14
1Y4
12
2Y1
9
2Y2
7
2Y352Y4
3
VCC
20
GND
10
U9
74HCT244U974HCT244
1A1
2
1A241A3
6
1A4
8
2A1
11
2A2
13
2A3
15
2A4
17
1G
1
2G
19
1Y1
18
1Y2
16
1Y3141Y4
12
2Y1
9
2Y272Y352Y4
3
VCC
20
GND
10
C18
0.1u
C18
0.1u
JP4
HEADER 3
JP4
HEADER 3
123
U10
74HCT244
U10
74HCT244
1A121A2
4
1A3
6
1A4
8
2A1
11
2A2
13
2A3
15
2A4
17
1G
1
2G
19
1Y1
18
1Y2
16
1Y3
14
1Y4
12
2Y1
9
2Y272Y3
5
2Y4
3
VCC
20
GND
10
U8
74HCT244U874HCT244
1A121A2
4
1A3
6
1A4
8
2A1
11
2A2
13
2A3
15
2A4
17
1G
1
2G
19
1Y1181Y2161Y3
14
1Y4122Y1
9
2Y272Y3
5
2Y4
3
VCC
20
GND
10
H2
HEADER 8X2H2HEADER 8X2
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
C20
0.1u
C20
0.1u
U3E
74AHC04
U3E
74AHC04
11 10
14
7
C21
0.1u
C21
0.1u
Vancouver Design Center
Figure 9-3: S5U13706P00C100 Schematics (3 of 5)
S1D13706 S5U13706P00C100 Evaluation Board User Manual
X31B-G-021-01 Issue Date: 2009/03/03
Revision 1.1
Page 25
Epson Research and Development Page 25
5
5
4
4
3
3
2
2
1
1
D
D
C
C
B B
A A
AB[16:0]
DB5
DB[15:0]
DB8
DB4
DB12
DB3
DB11
DB2
DB13
DB1
DB10
DB0
DB9
DB14
DB6 DB7
DB15
AB0
AB2
AB4
AB6
AB8
AB10
AB12
AB14
AB16
AB5
AB7
AB1
AB3
AB11
AB9
AB13
AB15
AD27
AD28
AD21
AD3
AD9
AD6
AD22
AD15
AD13
AD4
AD1
AD23
AD10
AD25
AD11
AD20
AD7
AD0
AD8
AD16
AD18
AD[31:0]
AD30
AD2
AD5
AD12
AD31
AD29
AD14
AD17
AD24
AD19
AD26
+5V +5V
+12V
+12V
+12V
+5V+5V +5V +12V
+12V+5V +5V
AB[16:0]
1,5
RD/WR#
1,5
BUSCLK
1,2,5
BS#
1,5
RD#
1,5
WE0#
1,5
WE1#
1,5
CS#
1,5
M/R#
1,5
WAIT#
1,5
RESET#
1,5
DB[15:0]
1,5
STOP#
5
PAR5
SERR#
5
IDSEL
5
RST#
5
C/BE0#
5
C/BE1#
5
DEVSEL#
5
CLK
5
C/BE2#
5
TRDY#
5
FRAME#
5
AD[31:0]
5
C/BE3#
5
IRDY#5PERR#
5
Title
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Place close to PCIB pin 61 & 62 Plac e close to PCIA pin 2
Place close to PCIB pin 5 & 6
+C36
33u 20V
+C36
33u 20V
PCIB1
PCI-B
PCIB1
PCI-B
-12V
1
TCK
2
GND
3
TDO
4
+5V
5
+5V
6
INTB#
7
INTD#
8
PRSNT#1
9
RESERVED
10
PRSNT#2
11
RESERVED
14
GND
15
CLK
16
GND
17
REQ#
18
+VI/O
19
AD31
20
AD29
21
GND
22
AD27
23
AD25
24
+3.3V
25
C/BE3#
26
AD23
27
GND
28
AD21
29
AD19
30
+3.3V
31
AD17
32
C/BE2#
33
GND
34
IRDY#
35
+3.3V
36
DEVSEL#
37
GND
38
LOCK#
39
PERR#
40
+3.3V
41
SERR#
42
3.3V
43
C/BE1#
44
AD14
45
GND
46
AD1247AD10
48
GND
49
AD8
52
AD7
53
+3.3V
54
AD555AD3
56
GND
57
AD1
58
+VI/O
59
ACK64#
60
+5V
61
+5V
62
PCIA1
PCI-A
PCIA1
PCI-A
TRST#1+12V
2
TMS
3
TDI
4
+5V
5
INTA#6INTC#7+5V
8
RESERVED9+VI/O
10
RESERVED11RESERVED
14
RST#
15
+VI/O16GNT#
17
GND
18
RESERVED19AD30
20
+3.3V
21
AD28
22
AD26
23
GND
24
AD24
25
IDSEL
26
+3.3V
27
AD22
28
AD20
29
GND30AD18
31
AD16
32
+3.3V
33
FRAME#
34
GND
35
TRDY#36GND
37
STOP#38+3.3V39SDONE40SBO#
41
GND
42
PAR43AD1544+3.3V
45
AD13
46
AD1147GND48AD949C/BE0#
52
+3.3V
53
AD654AD4
55
GND
56
AD2
57
AD058+VI/O
59
REQ64#
60
+5V
61
+5V
62
+C33
33u 20V
+C33
33u 20V
+C34
68u 10V
+C34
68u 10V
+C35
68u 10V
+C35
68u 10V
H4
HEADER 17X2H4HEADER 17X2
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
H3
HEADER 17X2H3HEADER 17X2
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
+C37
68u 10V
+C37
68u 10V
Vancouver Design Center
Figure 9-4: S5U13706P00C100 Schematics (4 of 5)
S5U13706P00C100 Evaluation Board User Manual S1D13706
Issue Date: 2009/03/03 X31B-G-021-01
Revision 1.1
Page 26
Page 26 Epson Research and Development
A
A
B
B
C
C
D
D
E
E
4 4
3 3
2 2
1 1
AD13
AD9
AD15
AD16
AD18
AD23
AD10
AD12
AD19
AD24
AD8
AD20
AD22
AD25
AD17
AD11
AD21
AD14
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD27
AD26
AD29
AD28
AD30
AD31
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB2
DB1
DB0
DB6
DB5
DB3
DB4
DB7
DB8
AB15
AB16
AB9
AB[16:0]
AB1
AB0
AB11
AB2
AB12
AB4
AB10
AB6
AB13
AB8
AB5
AB7
AB14
AB3
DCLK
DATAnSTATUS
CONF_DONE
nSTATUS
CONF_DONE
DCLK
DATA
AD[31:0]
DB[15:0]
+5V
+5V
+5V
+5V
+5V
+5V
+5V
+5V
+5V
+5V
+5V
+5V
+5V
+5V
+5V
+3.3V
+3.3V +3.3V +3 .3V +3.3V
+3.3V
TRDY#
4
STOP#
4
PAR
4
IRDY#
4
DEVSEL#
4
PERR#4SERR#
4
AB[16:0]
1,4
M/R#
1,4
WE0#
1,4
DB[15:0]
1,4
BS#
1,4
RD#
1,4
WE1#
1,4
RD/WR#
1,4
CS#
1,4
BUSCLK
1,2,4
RESET#
1,4
C/BE0#
4
IDSEL
4
C/BE3#
4
C/BE1#
4
WAIT#
1,4
FRAME#
4
C/BE2#
4
AD[31:0]
4
RST#
4
CLK
4
nCONFIG
1
Title
Size Document Number Rev
Date:
Sheet of
<Doc>
S5U13706P00C100 - FPGA--6016
B
55Monday, Marc h 05, 2007
Title
Size Document Number Rev
Date:
Sheet of
<Doc>
S5U13706P00C100 - FPGA--6016
B
55Monday, Marc h 05, 2007
Title
Size Document Number Rev
Date:
Sheet of
<Doc>
S5U13706P00C100 - FPGA--6016
B
55Monday, Marc h 05, 2007
FPGA configuration EPROM
Not Populated
U14 EPF6016TC144-2U14 EPF6016TC144-2
IO11IO2
2
IO3
3
nCE
4
GND
5
Vccint
6
Vccio7IO88IO99IO10
10
IO11
11
IO12
12
IO1313IO14
14
IO1515IO16
16
I17
17
GND
18
Vccio
19
I20
20
IO2121IO22
22
IO23
23
IO24
24
IO2525IO26
26
IO2727IO28
28
IO29
29
GND30Vccint31Vccio32MSEL33IO34
34
IO3535IO36
36
IO37
37
IO38
38
IO39
39
IO40
40
IO41
41
IO42
42
IO43
43
IO44
44
IO45
45
IO46
46
IO47
47
IO48
48
IO49
49
IO50
50
IO51
51
IO52
52
nCONFIG
53
GND
54
Vccio
55
nSTATUS
56
IO57
57
IO58
58
IO59
59
IO60
60
IO61
61
IO62
62
IO63
63
IO64
64
IO65
65
IO66
66
IO67
67
IO68
68
IO69
69
IO70
70
IO71
71
IO72
72
IO73
73
IO7474IO75
75
GND
76
Vccint
77
Vccio
78
IO79
79
IO8080IO81
81
IO82
82
IO8383IO84
84
IO8585IO86
86
IO87
87
IO88
88
I89
89
GND
90
Vccio
91
I92
92
IO93
93
IO94
94
IO9595IO96
96
IO9797IO98
98
IO99
99
IO100
100
IO101
101
GND
102
Vccint
103
Vccio
104
CONF_DONE
105
IO106
106
IO107
107
IO108
108
IO109
109
IO110
110
IO111
111
IO112
112
IO113
113
IO114
114
IO115
115
IO116
116
IO117
117
IO118
118
IO119
119
IO120
120
IO121
121
IO122
122
IO123
123
IO124
124
DATA
125
GND
126
Vccio
127
DCLK
128
IO129
129
IO130
130
IO131
131
IO132
132
IO133
133
IO134
134
IO135
135
IO136
136
IO137
137
IO138
138
IO139
139
IO140
140
IO141
141
IO142
142
IO143
143
IO144
144
C38
0.22u
C38
0.22u
R36
15K
R36
15K
R37
15K
R37
15K
R38
15K
R38
15K
R39
15K
R39
15K
R33
15K
R33
15K
U15
EPC1441PC8
U15
EPC1441PC8
DATA
1
DCLK2OE
3
nCS
4
GND
5
nCASC
6
VCC
7
VCC
8
R341KR34
1K
R35
1K
R35
1K
R40
1K
R40
1K
S1
SW DIP-4S1SW DIP-4
123
4
876
5
C40
0.22u
C40
0.22u
C39
0.22u
C39
0.22u
C44
0.22u
C44
0.22u
C42
0.22u
C42
0.22u
C41
0.22u
C41
0.22u
C43
0.22u
C43
0.22u
C46
0.22u
C46
0.22u
C45
0.22u
C45
0.22u
R32
100K
R32
100K
Vancouver Design Center
Figure 9-5: S5U13706P00C100 Schematics (5 of 5)
S1D13706 S5U13706P00C100 Evaluation Board User Manual
X31B-G-021-01 Issue Date: 2009/03/03
Revision 1.1
Page 27
Epson Research and Development Page 27
Vancouver Design Center
10 Board Layout
S5U13706P00C100 Evaluation Board User Manual S1D13706
Issue Date: 2009/03/03 X31B-G-021-01
Figure 10-1: S5U13706P00C100 Board Layout
Revision 1.1
Page 28
Page 28 Epson Research and Development
AMERICA
EPSON ELECTRONIC S AMERICA, INC.
2580 Orchard Parkway
San Jose, CA 95131,USA
Phone: +1-800-228-3964 FAX: +1-408-922-0238
EUROPE
EPSON EUROPE ELECTRON ICS GmbH
Riesstrasse 15, 80992 Munich,
GERMANY
Phone: +49-89-14005-0 FAX: +49-89-14005-110
ASIA
EPSON (CHINA) CO., LTD.
7F, Jinbao Bldg., No.89 Jinbao St.,
Beijing 100005, CHINA
Phone: +86-10-6410-6655 FAX: +86-10-6410-7320
SHANGHAI BRANCH
7F, Block B, High-Tech Bldg., 900, Yishan Road,
Shanghai 200233, CHINA
Phone: +86-21-5423-5522 FAX: +86-21-5423-5512
EPSON HONG KONG LTD.
20/F, Harbour Centre, 25 Harbour Road
Wanchai, Hong Kong
Phone: +852-2585-4600 FAX: +852-2827-4346
Telex: 65542 EPSCO HX
SHENZHEN BRANCH
12F, Dawning Mansion, Keji South 12th Road,
Hi-Tech Park, Shenzhen 518057, CHINA
Phone: +86-755-2699-3828 FAX: +86-755-2699-3838
EPSON TAIWAN TECHNOLOGY & TRADING LTD.
14F, No. 7, Song Ren Road,
Taipei 110, TAIWAN
Phone: +886-2-8786-6688 FAX: +886-2-8786-6660
EPSON SINGAPO RE PT E., LTD.
1 HarbourFront Place,
#03-02 HarbourFront To w er One , Sing apo re 098 633
Phone: +65-6586-5500 FAX: +65-6271-3182
SEIKO EPSON CORP.
KOREA OFFICE
50F, KLI 63 Bldg., 60 Yoido-dong
Youngdeungpo-Ku, Seoul, 150-763, KOREA
Phone: +82-2-784-6027 FAX: +82-2-767-3677
SEIKO EPSON CORP.
SEMICONDUCTOR OPERATIONS DIVISION
IC Sales Dept.
IC International Sales Group
421-8, Hino, Hino-shi, Tokyo 191-8501, JAPAN
Phone: +81-42-587-5814 FAX: +81-42-587-5117
Dongcheng District,
Vancouver Design Center
11 Technical Support
11.1 EPSON LCD Controllers (S1D13706)
S1D13706 S5U13706P00C100 Evaluation Board User Manual
X31B-G-021-01 Issue Date: 2009/03/03
Revision 1.1
Page 29
Epson Research and Development Page 29
Vancouver Design Center
Change Record
X31B-G-021-01 Revision 1.1 - Issued: March 03, 2009
• section 11 - update sales office addresses
X31B-G-021-01 Revision 1.0 - Issued: March 19, 2007
• initial draft
• m inor edits
• added parts list
• added schematics
• updated tech support contact information
S5U13706P00C100 Evaluation Board User Manual S1D13706
Issue Date: 2009/03/03 X31B-G-021-01
Revision 1.1
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