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S5U13700B00C
User Manual
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Epson S5U13700B00C User Manual

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Page 1
S1D13700 Embedded Memory Graphics LCD Controller
S5U13700B00C Rev. 1.0 Evaluation
Board User Manual
Document Number: X42A-G-002-01
Status: Revision 1.0
Issue Date: 2005/07/15
© SEIKO EPSON CORPORATION 2005. All Rights Reserved.
EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.
Revision 1.0
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Vancouver Design Center
S1D13700 S5U13700B00C Rev. 1.0 Evaluation Board User Manual X42A-G-002-01 Issue Date: 2005/07/15
Revision 1.0
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Table of Contents

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3 Installation and Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.1 Configuration DIP Switches . . . . . . . . . . . . . . . . . . . . . . . . . .7
3.2 Configuration Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4 Technical Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.1 Host interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.1.1 Epson PC Card Extender Support . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.1.2 Host Bus Interface Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.2 LCD Panel Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.3 Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5 Parts List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6 Schematic Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7 S5U13700B00C Board Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
8 Connecting the S5U13700B00C to the PC Card Adapter . . . . . . . . . . . . . . 28
9 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
9.1 Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
9.2 Document Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
10 Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
10.1 EPSON Mobile Graphics Engines (S1D13700) . . . . . . . . . . . . . . . . . 30
10.2 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Appendix A Epson PC Card Extender . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
A.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
A.2 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
A.3 Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
A.4 Bus Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
A.5 16-Bit PC Card Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
A.6 Generic #1 / #2 Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
A.7 Epson Evaluation Boards . . . . . . . . . . . . . . . . . . . . . . . . . . 32
A.8 Epson Evaluation Board Header Pin Mapping . . . . . . . . . . . . . . . . . . 32
S5U13700B00C Rev. 1.0 Evaluation Board User Manual S1D13700 Issue Date: 2005/07/15 X42A-G-002-01
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1 Introduction

This manual describes the setup and operation of the S5U13700B00C Rev. 1.0 Evaluation Board. This evaluation board is designed as an evaluation platform for the S1D13700 Embedded Memory Graphics LCD Controller.
The S5U13700B00C is designed for connection to the Epson PC Card Extender (S5UPCMCIAB00C), thus providing an easy connection to a laptop or a desktop computer with a PC Card reader. This module can also be used with other native platforms via the host connectors which provide the appropriate signals to support a variety of CPUs.
This user manual is updated as appropriate. Please check the Epson Research and Devel­opment Website at www.erd.epson.com for the latest revision of this document before beginning any development.
We appreciate your comments on our documentation. Please contact us via email at documentation@erd.epson.com.
S5U13700B00C Rev. 1.0 Evaluation Board User Manual S1D13700 Issue Date: 2005/07/15 X42A-G-002-01
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2 Features

The S5U13700B00C Rev. 1.0 evaluation board includes the following features:
• 64-pin TQFP13 S1D13700F0x Embedded Memory Graphics LCD Controller
• Headers for connecting to various Host Bus Interfaces or to the Epson PC Card Extender
• 0.1x0.1” header with all the LCD interface signals allowing connection to a LCD panel
• On-board 32MHz crystal and option to use an oscillator instead of the crystal
• On-board +3.3V regulator
S1D13700 S5U13700B00C Rev. 1.0 Evaluation Board User Manual X42A-G-002-01 Issue Date: 2005/07/15
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DIP Switch - S1
Top View
Vancouver Design Center

3 Installation and Configuration

The S5U13700B00C evaluation board incorporates a DIP switch and 9 jumpers, which allow configuration of the board.

3.1 Configuration DIP Switches

An 8 position DIP switch (S1) is used to configure the S1D13700 for different Host Bus interfaces and to select the FPSHIFT cycle time. The following figure shows the location of DIP switch S1 on the S5U13700B00C.

Figure 3-1: Configuration DIP Switch (S1) Location

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All S1D13700 configuration inputs (CNF[4:0]) are fully configurable using DIP switch S1 as described below.

Table 3-1: Summary of Configuration Options

SDU13700B00C
S1-[8:1]
Configuration
S1-[8:7] - Not used
S1-[6] AS#
S1-[5] CNF4 Indirect Addressing Mode
S1-[4:3] CNF[3:2]
S1-[2:1] CNF[1:0]
S1D13700
Pin
1 (ON) 0 (OFF)
Generic Bus or M6800 Family Bus Interface M68K Family Bus Interface
Selects the host bus interface as follows:
CNF3 CNF2 Host Bus
00 Generic Bus
01 Reserved
1 0 M6800 Family Bus Interface
1 1 MC68K Family Bus Interface
Selects the FPSHIFT cycle time (FPSHIFT:Clock Input) as follows:
CNF1 CNF0 FPSHIFT Cycle Time
0 0 FPSHIFT Divide 4:1
0 1 FPSHIFT Divide 8:1
1 0 FPSHIFT Divide 16:1
11 Reserved
Configuration State
Direct Addressing Mode
= Required settings when using the PC Card adapter
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3.2 Configuration Jumpers

The S5U13700B00C has 9 jumper blocks which allow the configuration of the board.

Table 3-2: Jumper Summary

Jumper Function Position 1-2 Position 2-3 No Jumper
JP1 HIOVDD
JP2 NIOVDD
JP3 COREVDD
JP4 CLKI Source On Board Oscillator (U2) Host Interface Connector —
JP5 CLKI Input Disable
JP6 Crystal Enable Enable Crystal Output Disable Crystal Output — JP7 HIOVDD Voltage JP8 NIOVDD Voltage +3.3V +5V — JP9 RESET Source Manual Reset Host Interface Reset —
Normal —
Normal —
Normal —
Disable CLKI Input
(CLKI is tied to VSS)
+3.3V +5V —
Disable Crystal Input
(XCG1 is tied to VSS)
HIOVDD current
measurement
NIOVDD current
measurement
COREVDD current
measurement
—
= Required settings when using the PC Card adapter
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Note
Top View
JP1
Normal Operation
HIOVDD current
measurement
Vancouver Design Center
JP1 - HIOVDD
JP1 can be used to measure the current consumption of the S1D13700 host interface. When the jumper is at position 1-2, normal operation is selected. When no jumper is installed, host interface current consumption can be measured across JP1.
The HIOVDD voltage can be selected to be +3.3V or +5V using jumper JP7.

Figure 3-2: Configuration Jumper JP1 Location

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Note
Top View
JP2
Normal Operation
NIOVDD current
measurement
Vancouver Design Center
JP2 - NIOVDD
JP2 can be used to measure the current consumption of the S1D13700 LCD panel interface. When the jumper is at position 1-2, normal operation is selected. When no jumper is installed, panel interface current consumption can be measured across JP2.
The NIOVDD voltage can be selected to be +3.3V or +5V using jumper JP8.

Figure 3-3: Configuration Jumper JP2 Location

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Top View
JP3
Normal Operation
COREVDD current
measurement
Vancouver Design Center
JP3 - COREVDD
JP3 can be used to measure the current consumption of the S1D13700 core. When the jumper is at position 1-2, normal operation is selected. When no jumper is installed, core current consumption can be measured across JP3.

Figure 3-4: Configuration Jumper JP3 Location

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Top View
JP4
On-board oscillator
Host interface
connector
(U2)
Vancouver Design Center
JP4 - CLKI Source
JP4 is used to select the clock source for the S1D13700 CLKI input. When the jumper is at position 1-2, the clock source is the on-board oscillator (U2). When the jumper is at position 2-3, the clock source is from the host interface connector (connector P1, pin 4).

Figure 3-5: Configuration Jumper JP4 Location

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Note
Top View
JP5
Disable CLKI input
Disable XCG1input
Vancouver Design Center
JP5 - CLKI Input Disable
JP5 is used to disable the S1D13700 clock input that is not used by connecting it to ground. When the jumper is at position 1-2, CLKI input is disabled. When the jumper is at position 2-3, XCG1 input is disabled.
When jumper JP5 is at position 1-2, jumper JP6 must also be at position 1-2. When jumper JP5 is at position 2-3, jumper JP6 must also be at position 2-3.

Figure 3-6: Configuration Jumper JP5 Location

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Note
Top View
JP6
Enable XCD1 output
Disable XCD1
output
Vancouver Design Center
JP6 - Crystal Enable
JP6 is used to enable or disable the S1D13700 crystal output (XCD1). When the jumper is at position 1-2, XCD1 output is enabled by connecting it to the crystal. When the jumper is at position 2-3, XCD1 output is disabled by disconnecting it from the crystal.
When jumper JP6 is at position 1-2, jumper JP5 must also be at position 1-2. When jumper JP6 is at position 2-3, jumper JP5 must also be at position 2-3.

Figure 3-7: Configuration Jumper JP6 Location

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Top View
JP7
+3.3V
+5V
Top View
JP8
+3.3V
+5V
Vancouver Design Center
JP7 - HIOVDD Voltage
JP7 is used to select the voltage for HIOVDD. When the jumper is at position 1-2, HIOVDD is +3.3V. When the jumper is at position 2-3, HIOVDD is +5V.

Figure 3-8: Configuration Jumper JP7 Location

JP8 - NIOVDD Voltage
JP8 is used to select the voltage for NIOVDD. When the jumper is at position 1-2, NIOVDD is +3.3V. When the jumper is at position 2-3, NIOVDD is +5V.

Figure 3-9: Configuration Jumper JP8 Location

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Top View
JP9
Manual reset
Host interface reset
Vancouver Design Center
JP9 - RESET# Source
JP9 is used to select the source of the RESET# signal to the S1D13700. When the jumper is at position 1-2, the S1D13700 is reset by the on-board reset button (SW1). When the jumper is at position 2-3, the S1D13700 is reset by the system (connector P1, pin
21).

Figure 3-10: Configuration Jumper JP9 Location

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Note
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4 Technical Description

4.1 Host interface

4.1.1 Epson PC Card Extender Support

The evaluation board is designed to connect to the Epson PC Card Extender (S5UPCMCIAB00C). The extender provides an easy connection to any computer with an available PC Card slot. The S5U13700B00C directly connects to the extender via connectors P1 and P2 (see Section 8, “Connecting the S5U13700B00C to the PC Card Adapter” on page 28).
When using this evaluation board with the Epson PC Card Extender, the maximum cur­rent draw of 750mA provided by the PC Card slot may be exceeded. If the combination of module and LCD panel exceeds this limit, an external 5V power supply may be re­quired. The 5V regulated power supply may be connected to the 5V test point (TP5V1) and the GND test point (TPGND1) to power the on-board regulator. In this case, the 0 Ohm resistor R2 must be removed from the board.

4.1.2 Host Bus Interface Support

The S1D13700 supports several host bus interfaces. All S1D13700 host interface pins are available on connectors P1 and P2 allowing the S5U13700B00C to be used for interfacing to other platforms.
All host interface signals must match HIOVDD of the S1D13700. The default value for HIOVDD on the board is +3.3V, so it will work with the Epson PC Card Extender (S5UPCMCIAB00C). HIOVDD can be selected between +3.3V and +5V using jumper JP7.
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Note
P1 and P2
CPU Bus Connectors
Bottom View
Vancouver Design Center
The following diagram shows the location of the host bus connectors (P1 and P2). Connectors P1 and P2 are 2x2mm headers, 40 pins (20x2) each.
Figure 4-1: CPU Bus Connectors (P1 and P2) Location
For the pinout of connectors P1 and P2, refer to the schematics (see Section 6, “Schematic Diagrams” on page 23).
1. When the board is connected to a PC using the Epson PC Card Extender, the signal AS# is not used and R12 must NOT be populated. AS# input of S1D13700 should be connected to HIOVDD by setting the dip switch (S1) position 6 to ON.
2. When the board is connected to different platforms, the Epson PC Card Extender is not used. If using MC68K Family Bus interface, the signal AS# is used and it can be provided to the P2 connector by populating R12 and the dip switch (S1) position 6 must be set to OFF position to disconnect AS# input from HIOVDD.
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H1
LCD Connector
Top View
Vancouver Design Center

4.2 LCD Panel Interface

All the LCD interface signals are available on connector H1. Connector H1 is a 8x2 header,
0.1x0.1” pitch. The following diagram shows the location of the LCD connector (H1).

4.3 Clock

Figure 4-2: LCD Connector (H1) Location

For the pinout of connector H1, refer to the schematics (see Section 6, “Schematic Diagrams” on page 23).
The S1D13700 accepts a clock signal from an oscillator or from a crystal. If the oscillator is used, the crystal input (XCG1) must be connected to ground and the crystal output (XCD1) must not be connected. If the crystal is used, the clock input (CLKI) must be connected to ground. For details on connecting CLKI or XCG1 to ground, refer to the JP5 description (see “JP6 - Crystal Enable” on page 15).
The default configuration of the S5U13700B00C uses a 32MHz crystal. Jumper JP5 is in position 1-2 to connect the CLKI input to ground because it is not used. Jumper JP6 is in position 1-2 to connect the XCD1 output to the crystal.
The board can use the CLKI input instead of the crystal. To use the CLKI input, JP5 must be moved to position 2-3 to connect the XCG1 input to ground. Also, jumper JP6 must be moved to position 2-3 to disconnect the XCD1 output from the crystal.
The CLKI signal can be provided on the host interface connector or by an on-board oscil­lator. Jumper JP4 is used to select the clock source. In position 1-2, the clock is provided by populating an oscillator into the 14-pin DIP socket U2. In position 2-3, the clock must be provided on pin 4 of the host interface connector P1.
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5 Parts List

Table 5-1: Parts List

Item Qty Reference Part Mfg / PN Notes
15
28
316
4 2 C24,C28 100uF 10V T Kemet T494D107K010AS
5 2 C31,C30 12 pF
6 1 D1 Power Panasonic - SSG LNJ308G8LRA
71 F1
8 1 H1 HEADER 8X2 3M/ESD 2516-6002UB
9 3 JP1,JP2,JP3
10 6
11 2 P1,P2
12 1 R1 22K
13 1 R2 0
14 1 R3 120R,0.1% Panasonic - ECG ERA-3YEB120V Or equivalent
15 1 R4 240R
16 1 R5 200R,0.1% Panasonic - ECG ERA-3YEB200V RES 200 OHM 0.1% SMD 0603
17 1 R6 1M
18 1 R7 100R
19 0 R8,R9,R12 NP
20 2 R10,R11 0
21 1 R13 22k
22 9
23 1 SW1
24 1 S1 CONFIG SW C&K TDA08H0SK1
C1,C12,C13,C20,
C22
C2,C3,C4,C10,
C11,C14,C15,C16
C5,C6,C7,C8,C9, C17,C18,C19,C21, C23,C25,C26,C27,
C29,C32,C33
JP4,JP5,JP6,JP7,
JP8,JP9
SH1,SH2,SH3, SH4,SH5,SH6,
SH7,SH8,SH9
47uF 10V Kemet T494B476M010AS
0.01uF Panasonic - ECG PCC103BQCT
0.1uF
MINISMDC110-
2, 1100mA
.100 in. Jumper
Shunt
SW TACT-
SPST
Yageo America
04022F104Z7B20D
Panasonic - ECG ECJ-
1VC1H120J
Raychem Corp/Polyswitch
Division MINISMDC110-2
Sullins Electronics Corp.
PRPN202PAEN
CTS Corporation 742C163223JTR
Sullins Electronics Corp.
STC02SYAN
ITT Industries KSC241J SWITCH TACT SILVER PLT J-TYPE
CAPACITOR TANT 47UF 10V 20%
SMT
CAPACITOR TANT 100UF 10V 10%
SMT
CAP 12PF 50V CERAMIC 0603 SMD
LED GREEN SS TYPE LOW CUR
SMD
POLYSWITCH 1.1A RESET FUSE
SMD
CONN HEADER VERT 2POS .100
TIN or GENERIC
CONN HEADER VERT 3POS .100
TIN or GENERIC
RES ARRAY 16TRM 8RES SMD
JUMPER SHORTING TIN
SWITCH DIP 8POS HALF PITCH
SMT
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Table 5-1: Parts List
Item Qty Reference Part Mfg / PN Notes
25 3
26 1 U1
27 1 U2
28 1 U3 LT1117CST Linear Technology LT1117CST
29 1 U4 SN74LVC2G17
30 1 U5
31 1 X1
TPGND1,TP5V1,
TPP3.3V1
TP_SMT Keystone 5015 PC TEST POINT MINIATURE SMT
S1D13700_TQ
FP13-64
Oscillator
Socket
14 pin narrow DIP, screw machine
socket
IC LDO REG ADJUSTBL 800MA
SOT223
TPS3801K33D
CKR
Crystal32MHz_
MA306
Texas Instruments
SN74LVC2G17DBVR
Texas Instruments
TPS3801K33DCKR
Epson MA-306 32.0000M-C0
IC BUFFER DUAL SHMT-TRG SOT-
23-6
IC 2.93V SUPPLY MON SOT-323-5
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5
5
4
4
3
3
2
2
1
1
D
D
C
C
B B
A A
D3
D2
CNF0
A12
CNF1
D0
A15
D4
A2A1D7
A14
A0
A5
AS#
D1
A13
A6D5A7
A11A3A8A9A4
D6
A10
FPDAT1
FPLINE
FPDAT0
FPDAT3
FPSHIFT
MOD
FPFRAME
YSCL
FPDAT2
XECL
YDIS
AS#
FPFRAME
YSCL
FPDAT0
MOD
XECL
FPLINE
FPDAT3
FPSHIFT
YDIS
FPDAT2
FPDAT1
CNF4
CNF3
CNF2
NIOVDD
3.3V
HIOVDD
HIOVDD
5V
5V
NIOVDD
NIOVDD
CLKI
2
A[15:0]
3
XCD1
2
XCG1
2
D[7:0]
3
WAIT#
3
RD#3AS#
3
CS#3WE#
3
RESET#
3
Title
Size Document Number Rev
Date:
Sheet of
13700B00C PC Ca rd Module 1.0
S1D13700
B
13Wednesday, Ap ril 06, 2005
Title
Size Document Number Rev
Date:
Sheet of
13700B00C PC Ca rd Module 1.0
S1D13700
B
13Wednesday, Ap ril 06, 2005
Title
Size Document Number Rev
Date:
Sheet of
13700B00C PC Ca rd Module 1.0
S1D13700
B
13Wednesday, Ap ril 06, 2005
Place a 0.01uF an d a 0.1uF cap on each
COREVDD power pin of the S1D13700
Place a 0.01uF an d a 0.1uF cap on each
HIOVDD power pin of the S1D13700
Place a 0.01uF a nd a 0.1uF cap on each
NIOVDD power pin of the S1D13700
SH1
.100 in. Jumper Shunt
SH1
.100 in. Jumper Shunt
C6
0.1uFC60.1uFC1
47uF 10VC147uF 10V
C7
0.1uFC70.1uF
C15
0.01uF
C15
0.01uF
C11
0.01uF
C11
0.01uF
C23
0.1uF
C23
0.1uFC20
47uF 10V
C20
47uF 10V
1 2 3 4 5 6 7 89
1
0
1
1
1
2
1
3
1
4
1
5
1
6
R1
22KR122K
A1562A14
63
A13
64
A122A11
3
A104A95A86A78A69A5
10A411A313A214A115A016
HIOVDD
7
NIOVDD
2
2
VSS
3
3
VSS
2
8
CNF2
58
CNF359CNF4
60
FPDAT3
18
FPDAT2
19
FPDAT1
20
FPDAT0
21
FPSHIFT
23
XECL
24
FPLINE
26
MOD
27
YSCL
29
FPFRAME
30
YDIS
31
RESET#
36
XCD134XCG135CLKI
39
COREVD D
1
2
RD#
41
WR#
42
CS#
43
VSS
1
7
D7
44D645D546D447D349D250D151D052
VS
S
1
WAIT#
54
TSTEN
38
CNF1
57
CNF0
56
COREVD D
2
5
NIOVDD
3
2
COREVDD
4
0
HIOVDD
4
8
HIOVDD
5
5
VSS
5
3
SCANEN
37
AS#
61
U1
S1D13700_TQFP13-64U1S1D13700_TQFP13-64
C16
0.01uF
C16
0.01uF
C9
0.1uFC90.1uF
1
2
JP2
NIOVDD
JP2
NIOVDD
SH2
.100 in. Jumper Shunt
SH2
.100 in. Jumper Shunt
C2
0.01uFC20.01uF
C22
47uF 10V
C22
47uF 10V
C5
0.1uFC50.1uF
SH3
.100 in. Jumper Shunt
SH3
.100 in. Jumper Shunt
C18
0.1uF
C18
0.1uF
C13
47uF 10V
C13
47uF 10V
C8
0.1uFC80.1uF
1 2
JP1
HIOVDD
JP1
HIOVDD
C19
0.1uF
C19
0.1uF
C10
0.01uF
C10
0.01uF
C21
0.1uF
C21
0.1uF
C3
0.01uFC30.01uF
C4
0.01uFC40.01uF
C14
0.01uF
C14
0.01uF
C17
0.1uF
C17
0.1uF
1 2
JP3
COREVDD
JP3
COREVDD
C12
47uF 10V
C12
47uF 10V
1
2
3
4
5
6
7
8
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9
S1
CONFIG SWS1CONFIG SW
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
H1
HEADER 8X2H1HEADER 8X2
Vancouver Design Center

6 Schematic Diagrams

Figure 6-1: S5U13700B00C Schematics (1 of 3)

S5U13700B00C Rev. 1.0 Evaluation Board User Manual S1D13700 Issue Date: 2005/07/15 X42A-G-002-01
Revision 1.0
Page 24
Page 24 Epson Research and Development
5
5
4
4
3
3
2
2
1
1
D
D
C
C
B B
A A
HIOVDD
5V
3.3V
5V
5V_CON_SUPPL Y
3.3V
HIOVDD
5V
NIOVDD
3.3V
5V
3.3V
CLOCK
3
CLKI
1
XCG1
1
XCD1 1
Title
Size Document Number Rev
Date:
Sheet of
13700B00C PC Ca rd Module 1.0
Panel Connector
B
23Thursday, Ap ril 07, 2005
Title
Size Document Number Rev
Date:
Sheet of
13700B00C PC Ca rd Module 1.0
Panel Connector
B
23Thursday, Ap ril 07, 2005
Title
Size Document Number Rev
Date:
Sheet of
13700B00C PC Ca rd Module 1.0
Panel Connector
B
23Thursday, Ap ril 07, 2005
CLKI Select
1-2_Oscillator
2-3_P1_
Connector
Place circuit as
close as possibl e to
S1D13700
Input Disabl e
1-2_Oscillator
2-3_Crystal
Voltage regulator
3.3V @ 800mA
PCB HeatSinked
HIOVDD Select
1-2 3.3V
2-3 5.0V
NIOVDD Selection
1-2 3.3V
2-3 5.0V
Surround crystal with ground island
Clock Trace should be as short as
possible. Isolate Crystal with
ground trace
Crystal
1-2_Enabled
2-3_Disabled
SH7
.100 in. Jumper Shunt
SH7
.100 in. Jumper Shunt
SH6
.100 in. Jumper Shunt
SH6
.100 in. Jumper Shunt
123
JP8
NIO Voltage
JP8
NIO Voltage
SH5
.100 in. Jumper Shunt
SH5
.100 in. Jumper Shunt
R7
100RR7100R
1
TPP3.3V1
TP_SMT
TPP3.3V1
TP_SMT
12
+
C24
100uF 10V T+C24
100uF 10V T
1
1
2
2
F1
MINISMDC110 -2, 1100mAF1MINISMDC110 -2, 1100mA
C29
0.1uF
C29
0.1uF
1
TP5V1
TP_SMT
TP5V1
TP_SMT
C27
0.1uF
C27
0.1uF
SH8
.100 in. Jumper Shunt
SH8
.100 in. Jumper Shunt
1
TPGND1
TP_SMT
TPGND1
TP_SMT
123
JP6
Crystal
JP6
Crystal
NC
1
OUT
8
GND
7
VCC
14
U2
Oscillator SocketU2Oscillator Socket
C26
0.1uF
C26
0.1uF
XIN
1
XOUT
4
NC
2
NC
3
X1
Crystal32MHz_MA306X1Crystal32MHz_MA306
123
JP7
HIO Voltage
JP7
HIO Voltage
D1
PowerD1Power
123
JP4
CLKI Select
JP4
CLKI Select
1 2
R3
120R,0.1%R3120R,0.1%
R6
1MR6 1M
123
JP5
Clock Source
JP5
Clock Source
12
+
C28
100uF 10V T+C28
100uF 10V T
R4
240RR4240R
C30
12 pF
C30
12 pF
1 2
R5
200R,0.1%R5200R,0.1%
R2
0R2 0
C25
0.1uF
C25
0.1uF
SH4
.100 in. Jumper Shunt
SH4
.100 in. Jumper Shunt
C31
12 pF
C31
12 pF
VIN
3
ADJ
1
VOUT
2
VOUT
4
U3
LT1117CSTU3LT1117CST
Vancouver Design Center

Figure 6-2: S5U13700B00C Schematics (2 of 3)

S1D13700 S5U13700B00C Rev. 1.0 Evaluation Board User Manual X42A-G-002-01 Issue Date: 2005/07/15
Revision 1.0
Page 25
Epson Research and Development Page 25
5
5
4
4
3
3
2
2
1
1
D
D
C
C
B B
A A
D2D3D0D1D4D6D5
CON_WE#
CON_RD#
CON_RD#
CON_WE#
D7
A4
A6
A10
A14
A13
A5A7A9
A2A1A0
A12A3A8
A11
A15
RESET_BUS#
RESET_BUS#
5V_CON_SUPPLY
HIOVDD
5V_CON_SUPPLY
HIOVDD
HIOVDD
WAIT#
1
RD#
1
CS#
1
WE#
1
A[15:0]
1
CLOCK
2
D[7:0]
1
AS#
1
RESET#
1
Title
Size Doc ument Number Rev
Date:
Sheet of
13700B00C PC Card Module 1.0
Host Bus Connector
B
33Wednesday, April 06, 2005
Title
Size Doc ument Number Rev
Date:
Sheet of
13700B00C PC Card Module 1.0
Host Bus Connector
B
33Wednesday, April 06, 2005
Title
Size Doc ument Number Rev
Date:
Sheet of
13700B00C PC Card Module 1.0
Host Bus Connector
B
33Wednesday, April 06, 2005
Module CPU Bus Con nectors
Signals on the hea ders that are not used have an X besides it.
P1 and P2 are the CPU bus connector. It was intended to b e as generic as po ssible and also to mate with the
Epson PC Card Adapter board.
PC Card Noise Eliminator on WE# & RD#
The power supply f or the module is pulle d in from P1 conne ctor. It should b e 5V DC regulated.
1-2 Manual Reset
2-3 Host Interface Reset
2A
3
2Y
4
U4B
SN74LVC2G1 7
U4B
SN74LVC2G1 7
R10 0R10 0
R8
NPR8 NP
R9
NPR9 NP
2 4
31
SW1
SW TACT-SPST
SW1
SW TACT-SPST
GND
2
VCC
5
U4C
SN74LVC2G17
U4C
SN74LVC2G17
123
JP9
RESET Selector
JP9
RESET Selector
GND
1
CS8#
2
CS#3M/R#
4
BS#5RD#
6
RD/WR#7WE0#
8
WE1#9GND
10
A2511A24
12
A23
13
A2214A21
15
A20
16
A19
17
A18
18
A1719GND
20
GND
21
A16
22
A1523A1424A1325A1226A11
27
A10
28A929A830
GND
31A732A633A534A435A336A237A138A039
GND
40
P2
HEADER MODULE P2P2HEADER MODULE P2
R11
0R11 0
R12
NPR12 NP
C32
0.1uF
C32
0.1uF
VCC
1
VCC
2
GND3BUSCLK
4
GND5WAIT#6CE2#
7
CE1#
8
REG#
9
INPACK#10WP/IOIS16#11GND12RDY/IREQ#13BVD2/SPKR#14BVD1/STSCHG#15WE#
16
OE#17IOWR#18IORD#19GND
20
RESET#
21
GND
22
D1523D1424D1325D1226D11
27
D10
28D929D830
GND
31D732D633D534D435D336D237D138D039
GND
40
P1
HEADER MOD ULE P1P1HEADER MOD ULE P1
C33
0.1uF
C33
0.1uF
1A
1
1Y
6
U4A
SN74LVC2G1 7
U4A
SN74LVC2G1 7
GND
1
GND2MR#
5
RESET#
3
VDD
4
U5
TPS3801K33D CKRU5TPS3801K33D CKR
R13
22k
R13
22k
SH9
.100 in. Jumper Shunt
SH9
.100 in. Jumper Shunt
Vancouver Design Center

Figure 6-3: S5U13700B00C Schematics (3 of 3)

S5U13700B00C Rev. 1.0 Evaluation Board User Manual S1D13700 Issue Date: 2005/07/15 X42A-G-002-01
Revision 1.0
Page 26
Page 26 Epson Research and Development
Vancouver Design Center

7 S5U13700B00C Board Layout

Figure 7-1: S5U13700B00C Board Layout (Top View)

S1D13700 S5U13700B00C Rev. 1.0 Evaluation Board User Manual X42A-G-002-01 Issue Date: 2005/07/15
Revision 1.0
Page 27
Epson Research and Development Page 27 Vancouver Design Center

Figure 7-2: S5U13700B00C Board Layout (Bottom View)

S5U13700B00C Rev. 1.0 Evaluation Board User Manual S1D13700 Issue Date: 2005/07/15 X42A-G-002-01
Revision 1.0
Page 28
Page 28 Epson Research and Development
S5U13700B00C
PC Card Adapter
Type II PC Card Slot
Vancouver Design Center

8 Connecting the S5U13700B00C to the PC Card Adapter

S1D13700 S5U13700B00C Rev. 1.0 Evaluation Board User Manual X42A-G-002-01 Issue Date: 2005/07/15

Figure 8-1: Connecting the S5U13700B00C to the PC Card Adapter

Revision 1.0
Page 29
Epson Research and Development Page 29 Vancouver Design Center

9 References

9.1 Documents

• Epson Research and Development, Inc., S1D13700F01 Hardware Functional Specifica­tion, document number X42A-A-002-xx.

9.2 Document Sources

• Epson Research and Development Website: http://www.erd.epson.com.
• PC Card Standard, March 1997.
S5U13700B00C Rev. 1.0 Evaluation Board User Manual S1D13700 Issue Date: 2005/07/15 X42A-G-002-01
Revision 1.0
Page 30
Page 30 Epson Research and Development
Japan
Seiko Epson Corporation IC International Sales Group 421-8, Hino, Hino-shi Tokyo 191-8501, Japan Tel: 042-587-5812 Fax: 042-587-5564 http://www.epson.co.jp/
Hong Kong
Epson Hong Kong Ltd. 20/F., Harbour Centre 25 Harbour Road Wanchai, Hong Kong Tel: 2585-4600 Fax: 2827-4346 http://www.epson.com.hk//
Taiwa n
Epson Taiwan Technology & Trading Ltd. 14F, No. 7 Song Ren Road Taipei 100, Taiwan, ROC Tel: 02-8786-6688 Fax: 02-8786-6677 http://www.epson.com.tw/
Singapore
Epson Singapore Pte., Ltd. No. 1 Temasek Avenue #36-00 Millenia Tower Singapore, 039192 Tel: 337-7911 Fax: 334-2716 http://www.epson.com.sg/
Europe
Epson Europe Electronics GmbH Riesstrasse 15 80992 Munich, Germany Tel: 089-14005-0 Fax: 089-14005-110 http://www.epson-electronics.de/
North America
Epson Electronics America, Inc. 150 River Oaks Parkway San Jose, CA 95134, USA Tel: (408) 922-0200 Fax: (408) 922-0238 http://www.eea.epson.com/
Vancouver Design Center

10 Technical Support

10.1 EPSON Mobile Graphics Engines (S1D13700)

10.2 Ordering Information

To order the S5U13700B00C Evaluation Board, contact the Epson sales representative in your area and order part number S5U13700P00C000.
S1D13700 S5U13700B00C Rev. 1.0 Evaluation Board User Manual X42A-G-002-01 Issue Date: 2005/07/15
Revision 1.0
Page 31
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Note
Vancouver Design Center

Appendix A Epson PC Card Extender

This section describes the setup and operation of the PC Card Extender Board Rev 1.0. This board was designed as an evaluation interface for connecting Epson S1D137xx Mobile Graphics Engine Evaluation Boards to the PC Card Bus.

A.1 Features

The PC Card Extender Board Rev 1.0 includes the following features.
• Header Signals for connecting Epson S1D137xx Mobile Graphics Engine Evaluation Boards
• Epson Identification EEPROM
• Current limiting, resettable fuse
• LED power indicators
• Voltage Level shifting to 3.3V

A.2 General

A.3 Power

The PC Card Extender Board is designed to be connected to a laptop supporting a PC Card Type II or Type III slot. The extender board includes an EEPROM containing the identifi­cation to specify it as an EPSON LCD controller. The software driver supplied by Epson will recognize this PC Card as an Epson LCD Controller.
The power supplies from the PC Card host are passed to the evaluation board headers. A resettable PolySwitch fuse (750mA) is placed on Vcc to protect the PC Card bus from excessive current consumption. If necessary, the evaluation board can be connected to an external power supply.
Permanent damage to the host is possible if signals are shorted on the connector. Care must be taken in attaching the modules.
The performance of the Mobile Graphics Engine in this environment is directly propor­tional to the PC Card bus speeds. The maximum data bus transfer speed is 10MHz. The maximum transfer rate is 20M bytes/sec in 16-bit mode and 10M Bytes/sec in 8-bit mode. Note that the PC Card bus itself is 100% asynchronous and has no clock signals.
The PC Card Extender Board requires 5V to be supplied / supported from the PC Card Slot. The extender board will not operate in a 3.3V only PC Card slot.
S5U13700B00C Rev. 1.0 Evaluation Board User Manual S1D13700 Issue Date: 2005/07/15 X42A-G-002-01
Revision 1.0
Page 32
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Note
Vancouver Design Center

A.4 Bus Disable

Switch SW1 is used to disable the bus to the Epson Mobile Graphics Engine evaluation board. When the bus is disabled, the red LED (D2) turns “ON”. For normal operations, the bus should be enabled, with SW1 positioned towards the clock X1 location.
On some systems, the Bus Disable function must be “ON” when the PC Card Extender Board/Evaluation board combination is first plugged into the PC Card host. Once the OS has detected the PC Card, the Bus Disable function can be turned “OFF”.

A.5 16-Bit PC Card Mode

To select 16-bit PC Card mode, switch SW2 must be positioned toward the clock X1 location. The S1D13700 is a 16-bit device and the drivers for the PC Card have been configured for 16-bit devices only. Therefore, 8-bit byte steering logic is not needed from the PC Card and should be placed in the 16-bit position.

A.6 Generic #1 / #2 Bus

Switch SW3 selects the control signals between Generic #1 or Generic #2 bus. The S5U13700B00C Evaluation Board does not require the setting of this switch and it should be positioned towards the clock X1 location.

A.7 Epson Evaluation Boards

The extender card provides a header to interface to Epson Mobile Graphics Engine Evalu­ation Boards. The header contains all the signals necessary for interfacing to the PC Card bus. The signals on the bus have been level shifted from 5V to 3.3V.
Vcc from the PC Card Bus is provided on the header, but considerations to the current draw should be noted. The evaluation board needs to supply it’s own Vcc if the current draw is greater than what the PC Card bus can provide.

A.8 Epson Evaluation Board Header Pin Mapping

The CPU interface uses two female connectors (P1 and P2) which provide all the signals and power connections needed for direct PC Card. Generic #1 and Generic#2 bus control signals have been decoded and are selectable using SW2.
Refer to the schematics for the pinout of P1 and P2.
S1D13700 S5U13700B00C Rev. 1.0 Evaluation Board User Manual X42A-G-002-01 Issue Date: 2005/07/15
Revision 1.0
Page 33
Epson Research and Development Page 33 Vancouver Design Center

Change Record

X42A-G-002-01 Revision 1.0
• released as revision 1.0
X42A-G-002-00 Revision 0.01
• initial draft
• added parts list
• added schematics
• added board layout
S5U13700B00C Rev. 1.0 Evaluation Board User Manual S1D13700 Issue Date: 2005/07/15 X42A-G-002-01
Revision 1.0
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