No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko
Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no representation that this material is applicabl e to products requiring high lev el reliability, such as,
medical products. Moreover, no license to any intellectual property rights is granted by implication or otherwise, and there is
no representation or warranty that anything made in accordance with this material will be free from any patent or copyright
infringement of a third party. This material or portions thereof may contain technology or the subject relating to strategic
products under the control of the Foreign Exchange and Foreign Trade Law of Japan and may require an export license from
the Ministry of International Trade and Industry or other approval from another government agency.
All other product names mentioned herein are trademarks and/or registered trademarks of their respective companies.
4EPSON S5U13515P00C100 Evaluation Board User Manual (Rev 1.1)
Page 5
Chapter 1 Introduction
Chapter 1 Introduction
This manual describes the setup and operation of the S5U13515P00C100 Evaluation Board. The evaluation board
is designed as an evaluation platform for the S2D13515 Display Controller.
The S5U13515P00C100 evaluation board can be used with many native platforms via the host connector which
provides the appropriate signals to support a variety of CPUs. The S5U13515P00C100 evaluation board can also
connect to the S5U13U00P00C1 00 USB Adapter bo ard so that i t can be use d with a laptop or desktop comput er, via
USB 2.0.
This user manual is updated as appropriate. Please check the Epson Research and Development Website at
www.erd.epson.com for the latest revision of this document before beginning any development.
We appreciate your comments on our docu mentation. Please conta ct us via email at documentation@erd. epson.com.
S5U13515P00C100 Evaluation Board User Manual (Rev 1.1) EPSON5
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Chapter 2 Features
Chapter 2 Features
The S5U13515P00C100 Evaluation Board includes the following features:
• 256-pin PBGA S2D13515 Display Controller
• On-board SDRAM, configurable as 32MB (32-bit wide) or 16MB (16-bit wide)
• On-board Serial Flash Memory, 32Mbit
• Headers for connection to various Host Bus Interfaces (includes all S2D13515 Host Bus Interface signals)
• Headers for connection to the S5U13U00P00C100 USB Adapter board
• Headers for connection to various LCD panels (includes all S2D13515 FP1IO and FP2IO interface signals)
• Header for connection to cameras
• Header for I2S outputs
• On-board 3x3 keypad
• On-board 20MHz crystal
• 14-pin DIP socket (if an oscillator for CLKI input is required)
• 3.3V input power
• On-board voltage regulator with 1.8V output
• On-board voltage regulator with adjustable 12~25V output, 60~100mA max., to provide power for LED backlight of LCD panels.
6EPSON S5U13515P00C100 Evaluation Board User Manual (Rev 1.1)
Page 7
Chapter 3 Installation and Configuration
Chapter 3 Installation and Configuration
The S5U13515P00C100 evaluatio n board incor porates a DIP switch, jumper s, and 0 ohm resi stors which all ow it to
be used with a variety of different configurations.
3.1 CNF[7:0] Configuration Inputs
The S2D13515 has 8 configuration inputs (CNF[7:0]), which can be configured through a combination of a DIP
switch and 0 ohm resi stors. CNF[2:0] ar e dedica ted inpu ts and a re configu red usin g DIP sw itch SW1. CNF[ 7:3] ar e
multiplexed with some host interface signals and are configured by 0 ohm resistors.
3.1.1 CNF[2:0]
CNF[2:0] are configured using DIP switch SW1 as described below.
Table 3-1: CNF[2:0] Configuration Settings
CNF[2:0]1 (connected to HIOVDD)0 (connected to VSS)
CNF2CNF[2:1] are used in combination with CNF[7:3] to select the host bus interface. For a
CNF1
CNF0OSCI is the source for Input Clock 1CLKI is the source for Input Clock 1
summary of the possible host bus interfaces, see
Configuration Settings” on page 9.
Section Table 3-3 :, “Host Interf ace
= suggested settings
The following figure shows the location of DIP switch SW1 on the S5U13515P00C100 evaluation board.
S5U13515P00C100 Evaluation Board User Manual (Rev 1.1) EPSON7
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Chapter 3 Installation and Configuration
3.1.2 CNF[7:3]
CNF[7:3] are configured using 0 Ohm resistors as described below.
Table 3-2: CNF[7:3] Configuration Settings
CNFPin1 (connected to HIOVDD)0 (connected to VSS)
CNF3
(see Note)
CNF4BDIP#
CNF5BURST#
CNF6
(see Note)
CNF7AB4
TEA#
BE1#
AB0
AB3
AB0
R100 populated
R107 not populated
R99 populated
R106 not populated
R95 populated
R102 not populated
R96 populated
R103 not populated
R98 populated
R105 not populated
R97 populated
R104 not populated
R99 populated
R106 not populated
R101 populated
R108 not populated
R100 not populated
R107 populated
R99 not populated
R106 popul ated
R95 not populated
R102 popul ated
R96 not populated
R103 popul ated
R98 not populated
R105 popul ated
R97 not populated
R104 popul ated
R99 not populated
R106 popul ated
R101 not populated
R108 popul ated
= default settings, required settings when using S5U13U00P00C100 USB Adapter Board
CNF3 and CNF6 are mapped to different pins depending on the combination of the other CNF inputs.
The following figure shows the location of the 0 Ohm resistors used to configure CNF[7:3].
Figure 3-2: CNF[7:3] 0 Ohm Resistor Locations
8EPSON S5U13515P00C100 Evaluation Board User Manual (Rev 1.1)
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Chapter 3 Installation and Configuration
3.1.3 Host Interface Configuration
The host bus interface used by the S5U13515P00C100 evaluation board is selected using a combination of the
CNF[2:1] pins and unused ho st interfa ce pins. Many host bus interf aces have unus ed pins that can be used as config
uration pins (CNF[7:3]) to select the host bus interface. The following table summarizes the available settings.
= default settings, required settings when using S5U13U00P00C100 USB Adapter Board
X= don’t care
S5U13515P00C100 Evaluation Board User Manual (Rev 1.1) EPSON9
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Chapter 3 Installation and Configuration
3.2 Configuration Jumpers
The S5U13515P00C100 has 16 jumpers which configure various evaluation board settings. The jumper positions
for each function are shown below.
Table 3-4: Configuration Jumper Settings
JumperFunctionPosition 1-2Position 2-3No Jumper
JP1COREVDDNormal—COREVDD current measurement
JP2PLL1VDDNormal—PLL1VDD current measurement
JP3PLL2VDDNormal—PLL2VDD current measurement
JP4OSCVDDNormal—OSCVDD current measu rem en t
JP5PIO1VDDNormal—PIO1VDD current measurement
JP6HIOVDDNormal—HIOVDD curre nt measurement
JP7HIOVDD SourceH4 connector, pin 313.3VDD—
JP8PIO1VDD SourceH9 connector, pin 93.3VDD—
JP9PIO2VDD SourceH9 connector, pin 103.3VDD—
JP10CM1VDDNormal—CM1VDD current measurement
JP11PIO2VDDNormal—PIO2VDD current measurement
JP12CM1DD SourceH9 connector, pin 83.3VDD—
JP13IOVDD SourceH9 connector, pin 73.3VDD—
JP14IOVDDNormal—IOVDD current measurement
JP15SDVDDNormal—SDVDD current measurement
JP16
SDRAM Width Select
(see Note)
32-bit wide SDRAM16-bit wide SDRAM—
= Required settings when using S5U13U00P00C100 USB Adapter board
10EPSON S5U13515P00C100 Evaluation Board User Manual (Rev 1.1)
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Chapter 3 Installation and Configuration
JP1, JP2, JP3, JP4, JP5, JP6, JP10, JP11, JP14, JP15 - Power Supplies for the S2D13515
JP1, JP2, JP3, JP4, JP5, JP6, JP10, JP11, JP14, and JP15 can be used to measure the current consumption of each
S2D13515 power supply.
When the jumper is at position 1-2, normal operation is selected.
When no jumper is installed, the current consumption for each power supply can be measured by connecting an
ammeter to pin 1 and 2 of the jumper.
The jumper associated with each power supply is as follows:
JP1 for COREVDDJP2 for PLL1VDD
JP3 for PLL2VDDJP4 for OSCVDD
JP5 for PIO1VDDJP6 for HIOVDD
JP10 for CM1VDDJP11 for PIO2VDD
JP14 for IOVDDJP15 for SDVDD
S5U13515P00C100 Evaluation Board User Manual (Rev 1.1) EPSON11
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Chapter 3 Installation and Configuration
JP7 - HIOVDD Source
JP7 is used to select the source for the HIOVDD supply voltage.
When the jumper is at position 1-2, the HIOVDD voltage must be provided to pin 31 on the H4 connector.
When the jumper is at position 2-3, the HIOVDD voltage is provided by the 3.3V power supply of the board.
Figure 3-4: Configuration Jumper Location (JP7)
JP8 - PIO1VDD Source
JP8 is used to select the source for the PIO1VDD supply voltage.
When the jumper is at position 1-2, the PIO1VDD voltage must be provided to pin 9 on the H9 connector.
When the jumper is at position 2-3, the PIO1VDD voltage is provided by the 3.3V power supply of the board.
Figure 3-5: Configuration Jumper Location (JP8)
12EPSON S5U13515P00C100 Evaluation Board User Manual (Rev 1.1)
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Chapter 3 Installation and Configuration
JP9 - PIO2VDD Source
JP9 is used to select the source for the PIO2VDD supply voltage.
When the jumper is at position 1-2, the PIO2VDD voltage must be provided to pin 10 on the H9 connector.
When the jumper is at position 2-3, the PIO2VDD voltage is provided by the 3.3V power supply of the board.
Figure 3-6: Configuration Jumper Location (JP9)
JP12 - CM1VDD Source
JP12 is used to select the source for the CM1VDD supply voltage.
When the jumper is at position 1-2, the CM1VDD voltage must be provided to pin 8 on the H9 connector.
When the jumper is at position 2-3, the CM1VDD voltage is provided by the 3.3V power supply of the board.
Figure 3-7: Configuration Jumper Location (JP12)
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Chapter 3 Installation and Configuration
JP13 - IOVDD Source
JP13 is used to select the source for the IOVDD supply voltage.
When the jumper is at position 1-2, the IOVDD voltage must be provided to pin 7 on the H9 connector.
When the jumper is at position 2-3, the IOVDD voltage is provided by the 3.3V power supply of the board.
Figure 3-8: Configuration Jumper Location (JP13)
JP16 - SDRAM Width Select
JP16 is used to select the bus width of the external SDRAM.
When the jumper is at pos it ion 1-2, the externa l SDRAM is 32 bits wide and the memory size is 32M bytes. In this
configuration, the memory consists of 2 chips in parallel, each16M bytes and 16 bits wide.
When the jumper is at pos it ion 2-3, the externa l SDRAM is 16 bits wide and the memory size is 16M bytes. In this
configuration, one memory chip is disabled and only one chip is active (16M bytes and 16 bits wide).
Figure 3-9: Configuration Jumper Location (JP16)
14EPSON S5U13515P00C100 Evaluation Board User Manual (Rev 1.1)
Page 15
Chapter 4 Technical Description
Chapter 4 Technical Description
4.1 Power
4.1.1 Power Requirements
The S5U13515P00C100 evaluation board requires an external regulated power supply (3.3V / 1A). The power is
supplied to the evaluation board through pin 33 of the H4 header, or pin 5 of the P2 header.
The green LED “3.3V Power” is turned on when 3.3V power is applied to the board.
4.1.2 Voltage Regulators
The S5U13515P00C100 evaluation board has an on-board linear regulator to provide the 1.8V power required by
the S2D13515 Display Controller. It also has a step-up switchi ng vol tage regulator to gene ra te adj u st ab le 12~ 25V,
which can be used to power the LED backlight on some LCD panels.
4.1.3 S2D13515 Power
The S2D13515 Display Controller requires 1.8V power and 2.3~2.7V or 3.0~3.6V power.
COREVDD, PLL1VDD, PLL2VDD, and OSCVDD require 1.8V power which is provided by an on-board linear
voltage regulator.
HIOVDD, PIO1VDD, PIO2VDD, CM1VDD, and IOVDD input power may be in the range 2.3V~2.7V or
3.0V~3.6V. When JP7, JP8, JP9, JP12, or JP13 are set to the 2-3 position, the corresponding power input is
connected to 3.3V. If a different voltage is required, set the corresponding jumper to the 1-2 position and connect
the external power supply to the evaluation board as indicated in
page 10.
SDVDD input power may be in the range 2.3V~2.7V or 3.0V~3.6V. On the evaluation board, SDVDD is connected
to 3.3V.
Table 3-4: “Configuration Jumper Settings,” on
4.1.4 LCD Backlight Power
On the evaluation board there is an adjustable 12~25V power supply. At 12V, the maximum current available is
100mA. At 25V, the maximum curren t avai lable i s 60mA. Thi s power suppl y is int ended f or us e to p ower th e LED
backlight on some LCD panels. The voltage is adjusted by the R175 pot.
For LCD panels that use a CCFL backlight, an ext ernal power suppl y must be used to provi de power to the inver ter
for the CCFL backlight. Usually, the inverter current consumption is higher than the maximum 100mA current
available from the on-board voltage regulator.
S5U13515P00C100 Evaluation Board User Manual (Rev 1.1) EPSON15
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Chapter 4 Technical Description
4.2 Clocks
The clock for the S2D13515 Display Con tr oll er i s pr ovi ded by a 20MHz crystal connect ed to the OSCI and OSCO
pins.
Additionally, the S5U1 3515P00C100 evaluati on board can als o use an oscill ator if the DIP14 footprint is populated.
If populated, the oscillator is connected to the CLKI input clock of the S2D13515 Display controller.
For details on the S2D13515 cl ock st ructu re, ref er to the S2D13515 Har dware Func tiona l Speci ficat ion , document
number X83A-A-001-xx.
4.3 Reset
The S2D13515 Display Controller on the S5U13515P00C100 evaluation board can be reset using a push-button
switch (SW2), or via an active low reset signal from the host development platform (pin 30 on the H4 connector).
16EPSON S5U13515P00C100 Evaluation Board User Manual (Rev 1.1)
Figure 4-1: Reset Swit ch (SW2) Location
Page 17
Chapter 4 Technical Description
4.4 Memory
4.4.1 SDRAM
The S5U13515P00C100 evaluation board has 2 SDRAM ICs, each 128Mbit x16-bit, CL=2 in a TSOP54 package.
When the S2D13515 Display Control ler is configured for 32-bit wid e DRAM bus, both SDRAM ICs are used. When
the S2D13515 Display Controller is configured for 16-bit wide DRAM bus, only one of the SDRAM ICs is used
and the other SDRAM I Cs is dis abled by h aving it s chip se lect in put pulle d high to inacti ve state , by putti ng jumper
JP16 in 2-3 position.
4.4.2 Serial Flash Memory with SPI interface
The S2D13515 Display Control ler has a SPI Flas h Memory interface which is connect ed to a 32Mbit Fl ash EPROM.
4.5 Host Interface
4.5.1 Direct Host Bus Interface Support
All S2D13515 host inter face pins are available on con nectors H3 and H4. Thi s allows the S5U13515P00C100 evalu ation board to be connecte d to a variety of de velopmen t platforms . For S2D13515 host interfac e pin mapping, re fer
to the S2D13515 Hardware Functional Specification, document number X83A-A-001-xx.
The following figure shows the location of h ost bus connect ors H3 and H4. H3 is a 0.1” x 0.1” 40-pin hea der (20x2)
and H4 is a 0.1” x 0.1” 34-pin header (17 x 2).
Figure 4-2: Host Bus Connector Location (H3 and H4)
For the pinout of connectors H3 and H4, see Section Chapter 6, “Schematic Diagrams” on page 29.
S5U13515P00C100 Evaluation Board User Manual (Rev 1.1) EPSON17
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Chapter 4 Technical Description
4.5.2 Connecting to the Epson S5U13U00P00C100 USB Adapter Board
The S5U13515P00C100 evaluation board is designed t o connect to a S5U13U00 P00C100 USB Adapter Boar d. The
USB adapter board provides a simple connection to any computer via a USB 2.0 connection. The
S5U13515P00C100 directly connects to the USB adapter board through connectors P1 and P2.
The USB adapter board also supplies the 3.3V power required by the S5U13515P00C100 evaluation board.
HIOVDD should be configured for 3.3V and JP7 should be set to the 2-3 position.
When the S5U13515P00C100 is con nected to the S5U13U 00P00C100 USB Adapter boar d, there are 2 LEDs on the
S5U13515P00C100 which pro vid e a qu ick visual status of the USB adapter. LED1 blinks to indic at e tha t t he USB
adapter board is active. LED2 turns on to indicate that the USB has been enumerated by the PC.
The following diagram shows the location of connectors P1 and P2. P1 and P2 are 2mm x 2mm, 40-pin headers
(20 x 2) located on the underside of the board.
Figure 4-3: USB Adapter Connector Locations (P1 and P2)
For the pinout of connectors P1 and P2, see Section Chapter 6, “Schematic Diagrams” on page 29.
A windows driver must be installed on the PC when the S5U13515P00C100 is used with the S5U13U00P00C100
USB Adapter Board. The S1D13xxxUSB driver is available at www.erd.epson.com.
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Chapter 4 Technical Description
4.6 LCD Interface
The LCD interface uses the FP1 IO[23:0] and FP2IO[27:0] pins. All signals on thes e pins are available on c onnectors
H5, H6, and H7.
Connectors H5, H6, and H7 are 0.1” x 0.1”, 40-pin headers (20 x 2). The following diagram shows the location of
these connectors.
Figure 4-4: FP1IO and FP2IO Connectors Location (H5, H6, H7)
For the pinout of connectors H5, H6, and H7, see Section Chapter 6, “Schematic Diagrams” on page 29.
4.6.1 FP1IO Interface
The FP1IO interface signals have multiplexed functio ns. All FP1IO interface signal s, except FP1IO18 and FP1IO19,
are available on connector H6. FP1IO18 and FP1IO19 signals go through 0 ohm resistors and are available on
connector H7.
The FP1IO interface can be conf igured as a LCD interface , 18-bit RGB input stream int erface, or 8-bit YUV camera
interface and keyboard interface. For S2D13515 FP1IO interface pin mapping, refer to the S2D13515 Hardware Functional Specification, document number X83A-A-001-xx.
4.6.2 FP2IO Interface
All FP2IO interface signals are available on connectors H5 and H7. For S2D13515 FP2IO interface pin mapping,
refer to the S2D13515 Hardware Functional Specification, document number X83A-A-001-xx.
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Chapter 4 Technical Description
4.7 Camera / I2C Interface
The S2D13515 Display Controller has a Camera interface. All the camera interface signals are available on
connector H10. To control t he camera, the S2 D13515 Display Cont roller has an I2C mas ter interface . The SDA and
SCL signals are pulled high to CM1VDD by 2.2 kΩ resistors and are available on connector H10. The reset signal
provided on H10 is active low and is pulled to HIOVDD when inactive.
Connector H10 is a 0.1” x 0.1”, 20-pin header (10 x 2). The following figure shows the location of the connector
H10.
Figure 4-5: Camera Connector Location (H10)
For the pinout of connector H10, see Section Chapter 6, “Schematic Diagrams” on page 29.
20EPSON S5U13515P00C100 Evaluation Board User Manual (Rev 1.1)
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Chapter 4 Technical Description
S2D13515
Zero
Ohms
Zero
Ohms
3x3
M/R#, AB[20:19], AB[16:14]
FP1IO[23:20], FP1IO[16:15]
Keypad
4.8 Keypad Interface
The keyboard is non-operat ion al with th e butt ons SW3- SW11, mo unt ed as th ey ar e on the boar d. In order to make
the keyboard operational, the user must remove the buttons SW3-SW11 from the board and mount them back on
the board, but rotated by 90 degree s or 270 degrees . The buttons will not match the foo tprint on th e PCB, but this i s
how they must be mounted on the board.
The S2D13515 Display Controller can support up to a 5x5 matrix keypad, but the S5U13515P00C100 evaluation
board includes only a 3x3 keypad. The keypad interfa ce can be configur ed to use either the FPIO1 inte rface or Host
interface pins. For S2D13515 pin mapping, refer to the S2D13515 Hardware Functional Specification, document
number X83A-A-001-xx. The keypad interface is configured for either the FPIO1 interface or Host Interface pins
using 0 ohm resistors.
Figure 4-6: Keypad Interface Zero Ohm Resistor Overview Diagram
The keypad can be configured to connect to 1 of 2 source pins on the S2D13515. Depending of the configuration,
the input lines must be pulled high to corresponding power supply. The source connection for the keypad is deter
mined by populating the correct set of zero ohm resistors as described below.
Populate only 1 set of the zero ohm resistors below
Zero Ohm For FP1IOZero Ohm For Host Interface
R181R180
S5U13515P00C100 evaluation board comes configured with the keyboard interface from the Host Interface pins,
so resistors R185 ~ R190 and R180 are populated and R191 ~ R196 and R181 are not populated.
S5U13515P00C100 Evaluation Board User Manual (Rev 1.1) EPSON21
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Chapter 4 Technical Description
4.9 I2S Interface
The S2D13515 Display Controller has an I2S Audio output interface. All of the I2S interface signals are available
on connector H8. The I2C signals, available on the same connector, can be used to program an external I2S Audio
DAC IC.
Connector H8 is a 0.1” x 0.1”, 24-pin header (12x2). The following figure shows the location of the connector H8.
Figure 4-7: I2S Connector Location (H8)
For the pinout of connector H8, see Section Chapter 6, “Schematic Diagrams” on page 29.
22EPSON S5U13515P00C100 Evaluation Board User Manual (Rev 1.1)
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Chapter 4 Technical Description
4.10 PWM Connector
The S2D13515 Display Controller has two PWM outputs which are available on connector H9. The other pins on
connector H9 are used to connec t the external po wer supplies to CM1VDD, IOVDD, PIO1VDD, and PIO2VDD, if
a voltage level different than 3.3V is required. Note that connector H9 is not populated on the S5U13515P00C100
evaluation board.
Connector H9 is a 0.1” x 0.1”, 10-pin header (5x2). The following figure shows the location of the connector H9.
Figure 4-8: PWM Connector Location (H9)
For the pinout of connector H9, see Section Chapter 6, “Schematic Diagrams” on page 29.
S5U13515P00C100 Evaluation Board User Manual (Rev 1.1) EPSON23
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Chapter 4 Technical Description
S2D13515
Zero
Ohms
Zero
Ohms
Zero
Ohms
H2
C33
Debugger
Port
AB[11:7], AB6 or BS#
FP2IO[17, 16, 14, 13, 11, 10]
DB[13:8]
4.11 C33 Debugger Port
The S2D13515 contains an embedded C33 microprocessor core. The debug monitor interface is available on
connector H2 for firmware deb uggi ng us ing C33 Debugge r. I n order to use connector H2, zero ohm re si st ors must
be configured depending on the desired S2D13515 configuration.
The C33 debugger function can be sourced from 2 sets of the host interface pins or from a set of FP2IO pins.
Figure 4-9: C33 Debugger Zero Ohm Resistor Overview Diagram
The connection to the C33 Debugger port is determined by populating the correct set of zero ohm resistors as
described below.
Table 4-2: C33 Debugger Port H7 Zero Ohm Selection
Populate only 1 set of the zero ohm resistors below
C33 Pin Function
PEDST0
PEDST1
PEDST2
PEDCLK
PEDSIO
PEDCPCO
C33 Debugger port
from FP2IO pins
R74 populated
R210 not populated
R73 populated
R211 not populated
R72 populated
R212 not populated
R70 populated
R213 not populated
R71 populated
R215 not populated
R75 populated
R214 not populated
C33 Debugger port from
AB[11:7], AB6 or BS# pins
R65 populated
R202 not populated
R66 populated
R201 not populated
R67 populated
R200 not populated
R69 populated
R199 not populated
R68 populated
R198 not populated
R63 populated (from AB6)
R64, R197 not populated
R64 populated (from BS#)
R63, R209 not populated
C33 Debugger port from
DB[13:8] pins
R80 populated
R208 not populated
R79 populated
R207 not populated
R78 populated
R206 not populated
R76 populated
R205 not populated
R77 populated
R204 not populated
R81 populated
R203 not populated
S5U13515P00C100 board comes configured for the C33 Debu gge r por t f ro m the Host Interface AB[11:6 ] pi ns, so
resistors R63, R65 ~ R69 are populated and R197 ~ R202 are not populated, R203 ~ R215 are populated and R64,
R70 ~ R81 are not populated.
24EPSON S5U13515P00C100 Evaluation Board User Manual (Rev 1.1)
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Chapter 4 Technical Description
Connector H2 is a 0.1” x 0.1”, 10-pin header (5x2). The following figure shows the location of the connector H2.
Figure 4-10: C33 Debugger Connector Location (H2)
For the pinout of connector H2, see Section Chapter 6, “Schematic Diagrams” on page 29.
4.12 JTAG Interface
The S2D13515 Display Controlle r has a JTAG in terface. All the JTAG signa ls are ava ilable on conne ctor H1. Note
that connector H1 is not populated on the S5U13515P00C100 evaluation board.
Connector H1 is a 0.1” x 0.1”, 12-pin header (6x2). The following figure shows the location of the connector H1.
For the pinout of connector H1, see Section Chapter 6, “Schematic Diagrams” on page 29.
S5U13515P00C100 Evaluation Board User Manual (Rev 1.1) EPSON25
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Chapter 8 References
Chapter 8 References
8.1 Documents
• Epson Research and Development, Inc., S2D13515 Hardware Functional Specification, document number
X83A-A-001-xx.
8.2 Document Sources
• Epson Research and Development Website: http://www.erd.epson.com.
36EPSON S5U13515P00C100 Evaluation Board User Manual (Rev 1.1)
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Chapter 8 References
Change Record
X83A-G-001-01 Revision 1.1 - Issued: September 9, 2009
• section 4.8 Keypad Interface - add not e “The keyboa rd is non- operati onal with the buttons SW3- SW11, mounted
as they are on the board...” to start of section
X83A-G-001-01 Revision 1.0 - Issued: January 20, 2009
• Release as Revision 1.0
• section 3.1.2 CNF[7:3] - correct typo in table change “R104” to “R107”