Epson S5U13515P00C100 User Manual

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S2D13515 Display Controller
S5U13515P00C100
Evaluation Board User
Manual
SEIKO EPSON CORPORATION
Rev 1.1
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No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any lia­bility of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or cir­cuit and, further, there is no representation that this material is applicabl e to products requiring high lev el reliability, such as, medical products. Moreover, no license to any intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright infringement of a third party. This material or portions thereof may contain technology or the subject relating to strategic products under the control of the Foreign Exchange and Foreign Trade Law of Japan and may require an export license from the Ministry of International Trade and Industry or other approval from another government agency.
All other product names mentioned herein are trademarks and/or registered trademarks of their respective companies.
©SEIKO EPSON CORPORATION 2008 - 2009, All rights reserved.
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Table of Contents
Chapter 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Chapter 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Chapter 3 Installation and Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.1 CNF[7:0] Configuration Inputs . . . . . . . . . . . . . . . . . . . . . . . . .7
3.1.1 CNF[2:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.1.2 CNF[7:3] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.1.3 Host Interface Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.2 Configuration Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Chapter 4 Technical Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.1 Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.1.1 Power Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.1.2 Voltage Regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.1.3 S2D13515 Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.1.4 LCD Backlight Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.2 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.3 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.4 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.4.1 SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.4.2 Serial Flash Memory with SPI interface . . . . . . . . . . . . . . . . . . . . . . . 17
4.5 Host Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.5.1 Direct Host Bus Interface Support . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.5.2 Connecting to the Epson S5U13U00P00C100 USB Adapter Board . . . . . . . . . 18
4.6 LCD Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.6.1 FP1IO Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.6.2 FP2IO Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.7 Camera / I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.8 Keypad Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.9 I2S Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.10 PWM Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.11 C33 Debugger Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.12 JTAG Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Chapter 5 Parts List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Chapter 6 Schematic Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Chapter 7 Board Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
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Chapter 8 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
8.1 Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
8.2 Document Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
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Chapter 1 Introduction
Chapter 1 Introduction
This manual describes the setup and operation of the S5U13515P00C100 Evaluation Board. The evaluation board is designed as an evaluation platform for the S2D13515 Display Controller.
The S5U13515P00C100 evaluation board can be used with many native platforms via the host connector which provides the appropriate signals to support a variety of CPUs. The S5U13515P00C100 evaluation board can also connect to the S5U13U00P00C1 00 USB Adapter bo ard so that i t can be use d with a laptop or desktop comput er, via USB 2.0.
This user manual is updated as appropriate. Please check the Epson Research and Development Website at www.erd.epson.com for the latest revision of this document before beginning any development.
We appreciate your comments on our docu mentation. Please conta ct us via email at documentation@erd. epson.com.
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Chapter 2 Features
Chapter 2 Features
The S5U13515P00C100 Evaluation Board includes the following features:
• 256-pin PBGA S2D13515 Display Controller
• On-board SDRAM, configurable as 32MB (32-bit wide) or 16MB (16-bit wide)
• On-board Serial Flash Memory, 32Mbit
• Headers for connection to various Host Bus Interfaces (includes all S2D13515 Host Bus Interface signals)
• Headers for connection to the S5U13U00P00C100 USB Adapter board
• Headers for connection to various LCD panels (includes all S2D13515 FP1IO and FP2IO interface signals)
• Header for connection to cameras
• Header for I2S outputs
• On-board 3x3 keypad
• On-board 20MHz crystal
• 14-pin DIP socket (if an oscillator for CLKI input is required)
• 3.3V input power
• On-board voltage regulator with 1.8V output
• On-board voltage regulator with adjustable 12~25V output, 60~100mA max., to provide power for LED back­light of LCD panels.
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Chapter 3 Installation and Configuration
Chapter 3 Installation and Configuration
The S5U13515P00C100 evaluatio n board incor porates a DIP switch, jumper s, and 0 ohm resi stors which all ow it to be used with a variety of different configurations.
3.1 CNF[7:0] Configuration Inputs
The S2D13515 has 8 configuration inputs (CNF[7:0]), which can be configured through a combination of a DIP switch and 0 ohm resi stors. CNF[2:0] ar e dedica ted inpu ts and a re configu red usin g DIP sw itch SW1. CNF[ 7:3] ar e multiplexed with some host interface signals and are configured by 0 ohm resistors.
3.1.1 CNF[2:0]
CNF[2:0] are configured using DIP switch SW1 as described below.
Table 3-1: CNF[2:0] Configuration Settings
CNF[2:0] 1 (connected to HIOVDD) 0 (connected to VSS)
CNF2 CNF[2:1] are used in combination with CNF[7:3] to select the host bus interface. For a CNF1 CNF0 OSCI is the source for Input Clock 1 CLKI is the source for Input Clock 1
summary of the possible host bus interfaces, see Configuration Settings” on page 9.
Section Table 3-3 :, “Host Interf ace
= suggested settings
The following figure shows the location of DIP switch SW1 on the S5U13515P00C100 evaluation board.
Figure 3-1: Configuration DIP Switch (SW1) Location
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Chapter 3 Installation and Configuration
3.1.2 CNF[7:3]
CNF[7:3] are configured using 0 Ohm resistors as described below.
Table 3-2: CNF[7:3] Configuration Settings
CNF Pin 1 (connected to HIOVDD) 0 (connected to VSS)
CNF3
(see Note)
CNF4 BDIP#
CNF5 BURST#
CNF6
(see Note)
CNF7 AB4
TEA#
BE1#
AB0
AB3
AB0
R100 populated
R107 not populated
R99 populated
R106 not populated
R95 populated
R102 not populated
R96 populated
R103 not populated
R98 populated
R105 not populated
R97 populated
R104 not populated
R99 populated
R106 not populated
R101 populated
R108 not populated
R100 not populated
R107 populated
R99 not populated
R106 popul ated
R95 not populated
R102 popul ated
R96 not populated
R103 popul ated
R98 not populated
R105 popul ated
R97 not populated
R104 popul ated
R99 not populated
R106 popul ated
R101 not populated
R108 popul ated
= default settings, required settings when using S5U13U00P00C100 USB Adapter Board
CNF3 and CNF6 are mapped to different pins depending on the combination of the other CNF inputs.
The following figure shows the location of the 0 Ohm resistors used to configure CNF[7:3].
Figure 3-2: CNF[7:3] 0 Ohm Resistor Locations
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Chapter 3 Installation and Configuration
3.1.3 Host Interface Configuration
The host bus interface used by the S5U13515P00C100 evaluation board is selected using a combination of the CNF[2:1] pins and unused ho st interfa ce pins. Many host bus interf aces have unus ed pins that can be used as config uration pins (CNF[7:3]) to select the host bus interface. The following table summarizes the available settings.
Table 3-3 : Host Interface Configuration Settings
CNF1 CNF2 CNF3 CNF4 CNF5 CNF6 CNF7 Host Interface
0 0 0 (TEA#) 0 (BDIP#) 0 (BURST#) 0 (AB3) X Indirect, 8-bit, Intel80 Type1 0 0 0 (TEA#) 0 (BDIP#) 0 (BURST#) 1 (AB3) X Indirect, 8-bit, Intel80 Type2 0 0 0 (TEA#) 0 (BDIP#) 1 (BURST#) 1 (AB3) 0 (AB4) SPI 0 0 0 (TEA#) 0 (BDIP#) 1 (BURST#) 1 (AB3) 1 (AB4) I2C 0 0 0 (TEA#) 1 (BDIP#) 0 (BURST#) 0 (AB3) X Indirect, 8-bit, NEC V850 Type1 0 0 0 (TEA#) 1 (BDIP#) 0 (BURST#) 1 (AB3) X Indirect, 8-bit, NEC V850 Type2 0 0 0 (TEA#) 1 (BDIP#) 1 (BURST#) 0 (AB3) X Indirect, 8-bit, Renesas SH4 0 1 0 (TEA#) 0 (BDIP#) 0 (BURST#) 0 (AB3) X Indirect, 16-bit, Intel80 Type1 0 1 0 (TEA#) 0 (BDIP#) 0 (BURST#) 1 (AB3) X Indirect, 16-bit, Intel80 Type2 0 1 0 (TEA#) 0 (BDIP#) 1 (BURST#) 1 (AB3) 0 (AB4) SPI (2-stream) 0 1 0 (TEA#) 0 (BDIP#) 1 (BURST#) 1 (AB3) 1 (AB4) I2C 0 1 0 (TEA#) 1 (BDIP#) 0 (BURST#) 0 (AB3) X Indirect, 16-bit, NEC V850 Type1 0 1 0 (TEA#) 1 (BDIP#) 0 (BURST#) 1 (AB3) X Indirect, 16-bit, NEC V850 Type2 0 1 0 (TEA#) 1 (BDIP#) 1 (BURST#) 0 (AB3) X Indirect, 16-bit, Renesas SH4 0 0 1 (TEA#) 0 (BDIP#) 0 (BURST#) 0 (BE1#) X Direct, 8-bit, Intel80 Type1 0 0 1 (TEA#) 0 (BDIP#) 0 (BURST#) 1 (BE1#) X Direct, 8-bit, Intel80 Type2 0 0 1 (TEA#) 0 (BDIP#) 1 (BURST#) 1 (BE1#) 0 (AB4) SPI 0 0 1 (TEA#) 0 (BDIP#) 1 (BURST#) 1 (BE1#) 1 (AB4) I2C 0 0 1 (TEA#) 1 (BDIP#) 0 (BURST#) 0 (BE1#) X Direct, 8-bit, NEC V850 Type1 0 0 1 (TEA#) 1 (BDIP#) 0 (BURST#) 1 (BE1#) X Direct, 8-bit, NEC V850 Type2 0 0 1 (TEA#) 1 (BDIP#) 1 (BURST#) 0 (BE1#) X Direct, 8-bit, Renesas SH4 0 1 1 (TEA#) 0 (BDIP#) 0 (BURST#) 0 (AB0) X Direct, 16-bit, Intel80 Type1 0 1 1 (TEA#) 0 (BDIP#) 0 (BURST#) 1 (AB0) X Direct, 16-bit, Intel80 Type2 0 1 1 (TEA#) 0 (BDIP#) 1 (BURST#) 0 (AB0) X Direct, 16-bit, Intel PXA3xxs 0 1 1 (TEA#) 0 (BDIP#) 1 (BURST#) 1 (AB0) 0 (AB4) SPI 0 1 1 (TEA#) 0 (BDIP#) 1 (BURST#) 1 (AB0) 1 (AB4) I2C 0 1 1 (TEA#) 1 (BDIP#) 0 (BURST#) 0 (AB0) X Direct, 16-bit, NEC V850 Type1 0 1 1 (TEA#) 1 (BDIP#) 0 (BURST#) 1 (AB0) X Direct, 16-bit, NEC V850 Type2 0 1 1 (TEA#) 1 (BDIP#) 1 (BURST#) 0 (AB0) X Direct, 16-bit, Renesas SH4 1 0 0 (AB0) X X X X Indirect, 16-bit, TI EBI 1 0 1 (AB0) X X X X Direct, 16-bit, TI EBI 1 1 0 (BE1#) X X X X Indirect, 16-bit, MPC555 1 1 1 (BE1#) X X X X Direct, 16-bit, MPC555
-
= default settings, required settings when using S5U13U00P00C100 USB Adapter Board
X = don’t care
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Chapter 3 Installation and Configuration
3.2 Configuration Jumpers
The S5U13515P00C100 has 16 jumpers which configure various evaluation board settings. The jumper positions for each function are shown below.
Table 3-4: Configuration Jumper Settings
Jumper Function Position 1-2 Position 2-3 No Jumper
JP1 COREVDD Normal COREVDD current measurement JP2 PLL1VDD Normal PLL1VDD current measurement JP3 PLL2VDD Normal PLL2VDD current measurement JP4 OSCVDD Normal OSCVDD current measu rem en t JP5 PIO1VDD Normal PIO1VDD current measurement JP6 HIOVDD Normal HIOVDD curre nt measurement JP7 HIOVDD Source H4 connector, pin 31 3.3VDD — JP8 PIO1VDD Source H9 connector, pin 9 3.3VDD
JP9 PIO2VDD Source H9 connector, pin 10 3.3VDD — JP10 CM1VDD Normal CM1VDD current measurement JP11 PIO2VDD Normal PIO2VDD current measurement JP12 CM1DD Source H9 connector, pin 8 3.3VDD — JP13 IOVDD Source H9 connector, pin 7 3.3VDD — JP14 IOVDD Normal IOVDD current measurement JP15 SDVDD Normal SDVDD current measurement
JP16
SDRAM Width Select
(see Note)
32-bit wide SDRAM 16-bit wide SDRAM
= Required settings when using S5U13U00P00C100 USB Adapter board
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Chapter 3 Installation and Configuration
JP1, JP2, JP3, JP4, JP5, JP6, JP10, JP11, JP14, JP15 - Power Supplies for the S2D13515
JP1, JP2, JP3, JP4, JP5, JP6, JP10, JP11, JP14, and JP15 can be used to measure the current consumption of each S2D13515 power supply. When the jumper is at position 1-2, normal operation is selected. When no jumper is installed, the current consumption for each power supply can be measured by connecting an ammeter to pin 1 and 2 of the jumper.
The jumper associated with each power supply is as follows:
JP1 for COREVDD JP2 for PLL1VDD JP3 for PLL2VDD JP4 for OSCVDD JP5 for PIO1VDD JP6 for HIOVDD JP10 for CM1VDD JP11 for PIO2VDD JP14 for IOVDD JP15 for SDVDD
Figure 3-3: Configuration Jumper Locations (JP1, JP2, JP3, JP4, JP5, JP6, JP10, JP11, JP14, JP15)
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Chapter 3 Installation and Configuration
JP7 - HIOVDD Source
JP7 is used to select the source for the HIOVDD supply voltage. When the jumper is at position 1-2, the HIOVDD voltage must be provided to pin 31 on the H4 connector. When the jumper is at position 2-3, the HIOVDD voltage is provided by the 3.3V power supply of the board.
Figure 3-4: Configuration Jumper Location (JP7)
JP8 - PIO1VDD Source
JP8 is used to select the source for the PIO1VDD supply voltage. When the jumper is at position 1-2, the PIO1VDD voltage must be provided to pin 9 on the H9 connector. When the jumper is at position 2-3, the PIO1VDD voltage is provided by the 3.3V power supply of the board.
Figure 3-5: Configuration Jumper Location (JP8)
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Chapter 3 Installation and Configuration
JP9 - PIO2VDD Source
JP9 is used to select the source for the PIO2VDD supply voltage. When the jumper is at position 1-2, the PIO2VDD voltage must be provided to pin 10 on the H9 connector. When the jumper is at position 2-3, the PIO2VDD voltage is provided by the 3.3V power supply of the board.
Figure 3-6: Configuration Jumper Location (JP9)
JP12 - CM1VDD Source
JP12 is used to select the source for the CM1VDD supply voltage. When the jumper is at position 1-2, the CM1VDD voltage must be provided to pin 8 on the H9 connector. When the jumper is at position 2-3, the CM1VDD voltage is provided by the 3.3V power supply of the board.
Figure 3-7: Configuration Jumper Location (JP12)
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Chapter 3 Installation and Configuration
JP13 - IOVDD Source
JP13 is used to select the source for the IOVDD supply voltage. When the jumper is at position 1-2, the IOVDD voltage must be provided to pin 7 on the H9 connector. When the jumper is at position 2-3, the IOVDD voltage is provided by the 3.3V power supply of the board.
Figure 3-8: Configuration Jumper Location (JP13)
JP16 - SDRAM Width Select
JP16 is used to select the bus width of the external SDRAM. When the jumper is at pos it ion 1-2, the externa l SDRAM is 32 bits wide and the memory size is 32M bytes. In this configuration, the memory consists of 2 chips in parallel, each16M bytes and 16 bits wide. When the jumper is at pos it ion 2-3, the externa l SDRAM is 16 bits wide and the memory size is 16M bytes. In this configuration, one memory chip is disabled and only one chip is active (16M bytes and 16 bits wide).
Figure 3-9: Configuration Jumper Location (JP16)
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Chapter 4 Technical Description
Chapter 4 Technical Description
4.1 Power
4.1.1 Power Requirements
The S5U13515P00C100 evaluation board requires an external regulated power supply (3.3V / 1A). The power is supplied to the evaluation board through pin 33 of the H4 header, or pin 5 of the P2 header.
The green LED “3.3V Power” is turned on when 3.3V power is applied to the board.
4.1.2 Voltage Regulators
The S5U13515P00C100 evaluation board has an on-board linear regulator to provide the 1.8V power required by the S2D13515 Display Controller. It also has a step-up switchi ng vol tage regulator to gene ra te adj u st ab le 12~ 25V, which can be used to power the LED backlight on some LCD panels.
4.1.3 S2D13515 Power
The S2D13515 Display Controller requires 1.8V power and 2.3~2.7V or 3.0~3.6V power.
COREVDD, PLL1VDD, PLL2VDD, and OSCVDD require 1.8V power which is provided by an on-board linear voltage regulator.
HIOVDD, PIO1VDD, PIO2VDD, CM1VDD, and IOVDD input power may be in the range 2.3V~2.7V or
3.0V~3.6V. When JP7, JP8, JP9, JP12, or JP13 are set to the 2-3 position, the corresponding power input is connected to 3.3V. If a different voltage is required, set the corresponding jumper to the 1-2 position and connect the external power supply to the evaluation board as indicated in page 10.
SDVDD input power may be in the range 2.3V~2.7V or 3.0V~3.6V. On the evaluation board, SDVDD is connected to 3.3V.
Table 3-4: “Configuration Jumper Settings,” on
4.1.4 LCD Backlight Power
On the evaluation board there is an adjustable 12~25V power supply. At 12V, the maximum current available is 100mA. At 25V, the maximum curren t avai lable i s 60mA. Thi s power suppl y is int ended f or us e to p ower th e LED backlight on some LCD panels. The voltage is adjusted by the R175 pot.
For LCD panels that use a CCFL backlight, an ext ernal power suppl y must be used to provi de power to the inver ter for the CCFL backlight. Usually, the inverter current consumption is higher than the maximum 100mA current available from the on-board voltage regulator.
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Chapter 4 Technical Description
4.2 Clocks
The clock for the S2D13515 Display Con tr oll er i s pr ovi ded by a 20MHz crystal connect ed to the OSCI and OSCO pins.
Additionally, the S5U1 3515P00C100 evaluati on board can als o use an oscill ator if the DIP14 footprint is populated. If populated, the oscillator is connected to the CLKI input clock of the S2D13515 Display controller.
For details on the S2D13515 cl ock st ructu re, ref er to the S2D13515 Har dware Func tiona l Speci ficat ion , document number X83A-A-001-xx.
4.3 Reset
The S2D13515 Display Controller on the S5U13515P00C100 evaluation board can be reset using a push-button switch (SW2), or via an active low reset signal from the host development platform (pin 30 on the H4 connector).
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Figure 4-1: Reset Swit ch (SW2) Location
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Chapter 4 Technical Description
4.4 Memory
4.4.1 SDRAM
The S5U13515P00C100 evaluation board has 2 SDRAM ICs, each 128Mbit x16-bit, CL=2 in a TSOP54 package. When the S2D13515 Display Control ler is configured for 32-bit wid e DRAM bus, both SDRAM ICs are used. When the S2D13515 Display Controller is configured for 16-bit wide DRAM bus, only one of the SDRAM ICs is used and the other SDRAM I Cs is dis abled by h aving it s chip se lect in put pulle d high to inacti ve state , by putti ng jumper JP16 in 2-3 position.
4.4.2 Serial Flash Memory with SPI interface
The S2D13515 Display Control ler has a SPI Flas h Memory interface which is connect ed to a 32Mbit Fl ash EPROM.
4.5 Host Interface
4.5.1 Direct Host Bus Interface Support
All S2D13515 host inter face pins are available on con nectors H3 and H4. Thi s allows the S5U13515P00C100 evalu ­ation board to be connecte d to a variety of de velopmen t platforms . For S2D13515 host interfac e pin mapping, re fer to the S2D13515 Hardware Functional Specification, document number X83A-A-001-xx.
The following figure shows the location of h ost bus connect ors H3 and H4. H3 is a 0.1” x 0.1” 40-pin hea der (20x2) and H4 is a 0.1” x 0.1” 34-pin header (17 x 2).
Figure 4-2: Host Bus Connector Location (H3 and H4)
For the pinout of connectors H3 and H4, see Section Chapter 6, “Schematic Diagrams” on page 29.
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Chapter 4 Technical Description
4.5.2 Connecting to the Epson S5U13U00P00C100 USB Adapter Board
The S5U13515P00C100 evaluation board is designed t o connect to a S5U13U00 P00C100 USB Adapter Boar d. The USB adapter board provides a simple connection to any computer via a USB 2.0 connection. The S5U13515P00C100 directly connects to the USB adapter board through connectors P1 and P2.
The USB adapter board also supplies the 3.3V power required by the S5U13515P00C100 evaluation board. HIOVDD should be configured for 3.3V and JP7 should be set to the 2-3 position.
When the S5U13515P00C100 is con nected to the S5U13U 00P00C100 USB Adapter boar d, there are 2 LEDs on the S5U13515P00C100 which pro vid e a qu ick visual status of the USB adapter. LED1 blinks to indic at e tha t t he USB adapter board is active. LED2 turns on to indicate that the USB has been enumerated by the PC.
The following diagram shows the location of connectors P1 and P2. P1 and P2 are 2mm x 2mm, 40-pin headers (20 x 2) located on the underside of the board.
Figure 4-3: USB Adapter Connector Locations (P1 and P2)
For the pinout of connectors P1 and P2, see Section Chapter 6, “Schematic Diagrams” on page 29.
A windows driver must be installed on the PC when the S5U13515P00C100 is used with the S5U13U00P00C100 USB Adapter Board. The S1D13xxxUSB driver is available at www.erd.epson.com.
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Chapter 4 Technical Description
4.6 LCD Interface
The LCD interface uses the FP1 IO[23:0] and FP2IO[27:0] pins. All signals on thes e pins are available on c onnectors H5, H6, and H7.
Connectors H5, H6, and H7 are 0.1” x 0.1”, 40-pin headers (20 x 2). The following diagram shows the location of these connectors.
Figure 4-4: FP1IO and FP2IO Connectors Location (H5, H6, H7)
For the pinout of connectors H5, H6, and H7, see Section Chapter 6, “Schematic Diagrams” on page 29.
4.6.1 FP1IO Interface
The FP1IO interface signals have multiplexed functio ns. All FP1IO interface signal s, except FP1IO18 and FP1IO19, are available on connector H6. FP1IO18 and FP1IO19 signals go through 0 ohm resistors and are available on connector H7.
The FP1IO interface can be conf igured as a LCD interface , 18-bit RGB input stream int erface, or 8-bit YUV camera interface and keyboard interface. For S2D13515 FP1IO interface pin mapping, refer to the S2D13515 Hardware Functional Specification, document number X83A-A-001-xx.
4.6.2 FP2IO Interface
All FP2IO interface signals are available on connectors H5 and H7. For S2D13515 FP2IO interface pin mapping, refer to the S2D13515 Hardware Functional Specification, document number X83A-A-001-xx.
S5U13515P00C100 Evaluation Board User Manual (Rev 1.1) EPSON 19
Page 20
Chapter 4 Technical Description
4.7 Camera / I2C Interface
The S2D13515 Display Controller has a Camera interface. All the camera interface signals are available on connector H10. To control t he camera, the S2 D13515 Display Cont roller has an I2C mas ter interface . The SDA and SCL signals are pulled high to CM1VDD by 2.2 kΩ resistors and are available on connector H10. The reset signal provided on H10 is active low and is pulled to HIOVDD when inactive.
Connector H10 is a 0.1” x 0.1”, 20-pin header (10 x 2). The following figure shows the location of the connector H10.
Figure 4-5: Camera Connector Location (H10)
For the pinout of connector H10, see Section Chapter 6, “Schematic Diagrams” on page 29.
20 EPSON S5U13515P00C100 Evaluation Board User Manual (Rev 1.1)
Page 21
Chapter 4 Technical Description
S2D13515
Zero
Ohms
Zero
Ohms
3x3
M/R#, AB[20:19], AB[16:14]
FP1IO[23:20], FP1IO[16:15]
Keypad
4.8 Keypad Interface
The keyboard is non-operat ion al with th e butt ons SW3- SW11, mo unt ed as th ey ar e on the boar d. In order to make the keyboard operational, the user must remove the buttons SW3-SW11 from the board and mount them back on the board, but rotated by 90 degree s or 270 degrees . The buttons will not match the foo tprint on th e PCB, but this i s how they must be mounted on the board.
The S2D13515 Display Controller can support up to a 5x5 matrix keypad, but the S5U13515P00C100 evaluation board includes only a 3x3 keypad. The keypad interfa ce can be configur ed to use either the FPIO1 inte rface or Host interface pins. For S2D13515 pin mapping, refer to the S2D13515 Hardware Functional Specification, document number X83A-A-001-xx. The keypad interface is configured for either the FPIO1 interface or Host Interface pins using 0 ohm resistors.
Figure 4-6: Keypad Interface Zero Ohm Resistor Overview Diagram
The keypad can be configured to connect to 1 of 2 source pins on the S2D13515. Depending of the configuration, the input lines must be pulled high to corresponding power supply. The source connection for the keypad is deter mined by populating the correct set of zero ohm resistors as described below.
Table 4-1: Keypad Zero Ohm Resistor Summary
Keypad Pin Function
KBR0 R191 R185 KBR1 R192 R186 KBR2 R193 R187 KBC0 R194 R188 KBC1 R195 R190 KBC2 R196 R189
Power
(HIOVDD or PIO1VDD)
Populate only 1 set of the zero ohm resistors below
Zero Ohm For FP1IO Zero Ohm For Host Interface
R181 R180
S5U13515P00C100 evaluation board comes configured with the keyboard interface from the Host Interface pins, so resistors R185 ~ R190 and R180 are populated and R191 ~ R196 and R181 are not populated.
S5U13515P00C100 Evaluation Board User Manual (Rev 1.1) EPSON 21
-
Page 22
Chapter 4 Technical Description
4.9 I2S Interface
The S2D13515 Display Controller has an I2S Audio output interface. All of the I2S interface signals are available on connector H8. The I2C signals, available on the same connector, can be used to program an external I2S Audio DAC IC.
Connector H8 is a 0.1” x 0.1”, 24-pin header (12x2). The following figure shows the location of the connector H8.
Figure 4-7: I2S Connector Location (H8)
For the pinout of connector H8, see Section Chapter 6, “Schematic Diagrams” on page 29.
22 EPSON S5U13515P00C100 Evaluation Board User Manual (Rev 1.1)
Page 23
Chapter 4 Technical Description
4.10 PWM Connector
The S2D13515 Display Controller has two PWM outputs which are available on connector H9. The other pins on connector H9 are used to connec t the external po wer supplies to CM1VDD, IOVDD, PIO1VDD, and PIO2VDD, if a voltage level different than 3.3V is required. Note that connector H9 is not populated on the S5U13515P00C100 evaluation board.
Connector H9 is a 0.1” x 0.1”, 10-pin header (5x2). The following figure shows the location of the connector H9.
Figure 4-8: PWM Connector Location (H9)
For the pinout of connector H9, see Section Chapter 6, “Schematic Diagrams” on page 29.
S5U13515P00C100 Evaluation Board User Manual (Rev 1.1) EPSON 23
Page 24
Chapter 4 Technical Description
S2D13515
Zero
Ohms
Zero
Ohms
Zero
Ohms
H2
C33
Debugger
Port
AB[11:7], AB6 or BS#
FP2IO[17, 16, 14, 13, 11, 10]
DB[13:8]
4.11 C33 Debugger Port
The S2D13515 contains an embedded C33 microprocessor core. The debug monitor interface is available on connector H2 for firmware deb uggi ng us ing C33 Debugge r. I n order to use connector H2, zero ohm re si st ors must be configured depending on the desired S2D13515 configuration.
The C33 debugger function can be sourced from 2 sets of the host interface pins or from a set of FP2IO pins.
Figure 4-9: C33 Debugger Zero Ohm Resistor Overview Diagram
The connection to the C33 Debugger port is determined by populating the correct set of zero ohm resistors as described below.
Table 4-2: C33 Debugger Port H7 Zero Ohm Selection
Populate only 1 set of the zero ohm resistors below
C33 Pin Function
PEDST0
PEDST1
PEDST2
PEDCLK
PEDSIO
PEDCPCO
C33 Debugger port
from FP2IO pins
R74 populated
R210 not populated
R73 populated
R211 not populated
R72 populated
R212 not populated
R70 populated
R213 not populated
R71 populated
R215 not populated
R75 populated
R214 not populated
C33 Debugger port from
AB[11:7], AB6 or BS# pins
R65 populated
R202 not populated
R66 populated
R201 not populated
R67 populated
R200 not populated
R69 populated
R199 not populated
R68 populated
R198 not populated
R63 populated (from AB6)
R64, R197 not populated
R64 populated (from BS#)
R63, R209 not populated
C33 Debugger port from
DB[13:8] pins
R80 populated
R208 not populated
R79 populated
R207 not populated
R78 populated
R206 not populated
R76 populated
R205 not populated
R77 populated
R204 not populated
R81 populated
R203 not populated
S5U13515P00C100 board comes configured for the C33 Debu gge r por t f ro m the Host Interface AB[11:6 ] pi ns, so resistors R63, R65 ~ R69 are populated and R197 ~ R202 are not populated, R203 ~ R215 are populated and R64, R70 ~ R81 are not populated.
24 EPSON S5U13515P00C100 Evaluation Board User Manual (Rev 1.1)
Page 25
Chapter 4 Technical Description
Connector H2 is a 0.1” x 0.1”, 10-pin header (5x2). The following figure shows the location of the connector H2.
Figure 4-10: C33 Debugger Connector Location (H2)
For the pinout of connector H2, see Section Chapter 6, “Schematic Diagrams” on page 29.
4.12 JTAG Interface
The S2D13515 Display Controlle r has a JTAG in terface. All the JTAG signa ls are ava ilable on conne ctor H1. Note that connector H1 is not populated on the S5U13515P00C100 evaluation board.
Connector H1 is a 0.1” x 0.1”, 12-pin header (6x2). The following figure shows the location of the connector H1.
For the pinout of connector H1, see Section Chapter 6, “Schematic Diagrams” on page 29.
S5U13515P00C100 Evaluation Board User Manual (Rev 1.1) EPSON 25
Figure 4-11: JTAG Connector Location (H1)
Page 26
Chapter 5 Parts List
Chapter 5 Parts List
Table 5-1 : S5U13515P00C100 Part s List
Item Quantity Reference Part Description
C1,C2,C3,C4,C5,C6,C7,C
8,C17,C20,C24,C25,C26,
C27,C28,C29,C30,C31,C3
9,C40,C41,C42,C43,C49,
1 50
2 43
3 2 C18,C21 1nF Yageo America 04022R102K9B20D, C0402 4 5 C19,C22,C64,C70,C73 10uF Panasonic - ECG ECJ-CV50J106M, C0805 5 2 C65,C66 18pF Panasonic - ECG ECJ-0EC1H180J, C0402
6 1 C102 2.2uF 10V
7 1 C103 10uF 35V 8 1 C104 150pF Panasonic - ECG ECJ-0EC1H151J, C0402
9 1 C105 1uF Panasonic - ECG ECJ-0EB0J105M, C0402
10 3 D1,D2,D3
11 10
12 1 F1 ACH32C-333-T
13 1 F2 ACF451832-222
14 0 H1 JTAG 15 1 H2,H9 Samtec TSW-105-07-G-D, Do not populate H9
16 1 H3 HEADER_20X2 Samtec TSW-120-07-G-D 17 1 H4 HEADER_17X2 Samtec TSW-117-07-G-D 18 3 H5,H6,H7 Samtec TST-120-01-G-D 19 1 H8 I2S PORT Samtec TSW-112-07-G-D 20 1 H10 CAMERA1 Samtec TSW-110-07-G-D
C50,C51,C52,C53,C54,C5
5,C63,C67,C69,C71,C72,
C74,C75,C76,C77,C78,C7
9,C80,C81,C82,C83,C84,
C85,C86,C87,C106
C9,C10,C11,C12,C13,C14
,C15,C16,C23,C32,C33,C 34,C35,C36,C37,C38,C44, C45,C46,C47,C48,C56,C5
7,C58,C59,C60,C61,C62,
C68,C88,C89,C90,C91,C9
2,C93,C94,C95,C96,C97,
C98,C99,C100,C101
D4,D5,D6,D7,D8,D9,D10,
D11,D12,D13
0.1uF Yageo America 04022F104Z7B20D, C0402
0.01uF Yageo America 0402ZRY5V7BB103, C0402
Taiyo Yuden LMK212BJ225KG-T, C0805,
CAP CER 2.2UF 10V X7R 0805
Taiyo Yuden GMK325BJ106KN-T, C1210,
CAP CER 10UF 35V X5R 1210
Panasonic - SSG LNJ308G8LRA, LED0603,
LED GREEN SS TYPE LOW CUR SMD
MBR0540
Micro Commercial Co. MBR0540-TP, SOD-123,
DIODE SCHOTTKY 40V 500MA SOD123
TDK ACH32C-333-T,
FILTR 3TERM 10MHZ TO 300MHZ SMD
TDK ACF451832-222,
FILTER 3-TERM 60MHZ 300MA SMD
Samtec TSW-106-07-G-D
Do not populate
26 EPSON S5U13515P00C100 Evaluation Board User Manual (Rev 1.1)
Page 27
Chapter 5 Parts List
Table 5-1 : S5U13515P00C100 Parts List
Item Quantity Reference Part Description
21 10
22 6
JP1,JP2,JP3,JP4,JP5,JP6
JP10,JP11,JP14,JP15
JP7,JP8,JP9,JP12,JP13,J
P16
23 6 L1,L2,L3,L4,L5,L6 Ferrite
24 1 L7 10uH 25 2 P1,P2 HEADER_20X2 3M 151240-8422-RB, HDR2X20/2MM
R1,R2,R3,R4,R5,R6,R7,R
8,R9,R10,R11,R12,R13,R 14,R15,R16,R17,R18,R19, R20,R21,R22,R23,R24,R2
5,R26,R27,R28,R29,R30,
26 61
R31,R32,R33,R34,R35,R3
33 1% R0402
6,R37,R38,R39,R40,R41,
R42,R43,R44,R45,R46,R4
7,R48,R49,R50,R51,R53,
R54,R55,R57,R58,R59,R6
0,R61,R62,R88
R52,R64,R70,R71,R72,R7
3,R74,R75,R76,R77,R78,
R79,R80,R81,R95,R96,R9
7,R98,R99,R100,R101,R1 04,R106,R108,R134,R135, R136,R137,R138,R139,R1
27 0
40,R141,R142,R143,R144, R145,R146,R147,R148,R1
0_np
49,R150,R151,R161,R163, R165,R167,R169,R170,R1 81,R191,R192,R193,R194, R195,R196,R197,R198,R1 99,R200,R201,R202,R216,
R217,R218,R219
R56,R63,R65,R66,R67,R6
8,R69,R83,R85,R86,R87, R102,R103,R105,R107,R1 09,R110,R111,R113,R114, R115,R116,R117,R118,R1 19,R120,R121,R122,R123, R124,R125,R126,R127,R1
28 68
28,R129,R130,R131,R132,
0 R0402 R152,R153,R154,R155,R1 60,R162,R164,R166,R168, R171,R180,R185,R186,R1 87,R188,R189,R190,R203, R204,R205,R206,R207,R2 08,R209,R210,R211,R212,
R213,R214,R215 29 1 R82 1M R0402 30 1 R84 1k R0402
SIP2 CONN HEADER VERT 2POS .100 TIN or
GENERIC
SIP3 CONN HEADER VERT 3POS .100 TIN or
GENERIC
Steward HZ0603B751R-10, R0603,
FERRITE 200MA 938 OHMS 0603 SMD
Panasonic - ECG ELL-6SH100M, IND_ELL 6,
COIL 10UH 1300MA CHOKE SMD
R0402
Do not populate
S5U13515P00C100 Evaluation Board User Manual (Rev 1.1) EPSON 27
Page 28
Chapter 5 Parts List
Table 5-1 : S5U13515P00C100 Part s List
Item Quantity Reference Part Description
31 10 32 1 R90 150k 1% R0402
33 3 R112,R133,R172 0 R0603 34 3 R157,R158,R159 270 1% R0402 35 1 R173 120k R0402
36 1 R175 200k 37 1 R176 56k R0402
38 1 R177 13.3k 1% R0402 39 2 R178,R179 2.2k R0402
40 16
41 1 SW1 SW4_DIPSW4
42 10
43 2 TPGND1,TP3.3VDD1 TP_SMT 44 1 U1 S2D13515PBGA256 45 1 U2 M25P32-VMF
46 2 U3,U4 128M16 DRAM
47 1 U5 MIC37100-1.8WS
48 1 U6 LM2733Y
49 1 X1 MA-506 20.0000M
50 0 Y1 14-Pin DIP
R89,R91,R92,R93,R94,R1 56,R174,R182,R183,R184
SH1,SH2,SH3,SH4,SH5,S
H6,SH7,SH8,SH9,SH10,S
H11,SH12,SH13,SH14,SH
15,SH16
SW2,SW3,SW4,SW5,SW6
,SW7,SW8,SW9,SW10,S
W11
10k R0402
Panasonic - ECG EVN-5ESX50B25,
POT 200K OHM 3MM CARBON TRIM SMD
.100 in. Jumper
Shunt
Sullins Electronics Corp. STC02SYAN
JUMPER SHORTING TIN
CTS Corp 218-4LPST, DIPSW4,
SWITCH DIP HALF PITCH 4POS
SW TACT-SPST
ITT Industries KSC201JLFS,
SWITCH TACT SILVR 120GF J-LEAD
Keystone 5015, TP_1206,
PC TEST POINT MINIATURE SMT
ST Microelectronics M25P32-VMF6P,
IC SRL FLASH 32MBIT 3V 16-SOIC
Qimonda HYB39S128160FE-7,
IC SDRAM 128MBit 54-TSOP
Micrel MIC37100-1.8WS, SOT-22 3,
Alternate MIC39100-1.8WS
National Semiconductor LM2733YMF/NOPB,
IC CONV BOOST 40V FET SW SOT23-5
Epson MA-506 20.0000M,
CRYSTAL 20.0000MHZ 18PF SMD
AMP 2-641609-1
Do not populate
SOT23-5,
28 EPSON S5U13515P00C100 Evaluation Board User Manual (Rev 1.1)
Page 29
Chapter 6 Schematic Diagrams
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
TDO
TMS
TDI
TCK
FP2IO17
FP2IO27
FP2IO5
FP2IO16
FP2IO4
FP2IO15
FP2IO3
FP2IO26
FP2IO14
FP2IO25
FP2IO13
FP2IO24
FP2IO12
FP2IO23
FP2IO11
FP2IO22
FP2IO10
FP2IO21
FP2IO9
FP2IO20
FP2IO8
FP2IO19
FP2IO7
FP2IO18
FP2IO6
FP2IO2
FP2IO1
FP2IO0
FP1IO9
FP1IO18
FP1IO8
FP1IO17
FP1IO14
FP1IO7
FP1IO11
FP1IO6
FP1IO22
FP1IO5
FP1IO21
FP1IO4
FP1IO20
FP1IO3
FP1IO16
FP1IO2
FP1IO15
FP1IO1
FP1IO13
FP1IO0
FP1IO23
FP1IO12
FP1IO10
FP1IO19
TCK
TMS
TDI
TDO
MEMA2
MEMA1
MEMA12
MEMA0
MEMA11
MEMA8
MEMA10
MEMA6
MEMA9
MEMA5
MEMA4
MEMA7
MEMA3
MEMDQ6
MEMDQ17
MEMDQ27
MEMDQ5
MEMDQ16
MEMDQ26
MEMDQ4
MEMDQ25
MEMDQ3
MEMDQ24
MEMDQ2
MEMDQ23
MEMDQ15
MEMDQ1
MEMDQ12
MEMDQ22
MEMDQ14
MEMDQ10
MEMDQ0
MEMDQ21
MEMDQ13
MEMDQ9
MEMDQ20
MEMDQ8
MEMDQ19
MEMDQ11
MEMDQ7
MEMDQ18
MEMDQ31
MEMDQ30
MEMDQ29
MEMDQ28
AB20
AB19
AB18
AB17
AB16
AB15
AB14
AB13
AB12
AB11
AB10
AB9
AB8
AB7
AB6
AB5
AB4
AB3
AB2
AB1
AB0
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
AB[20:0]
pBS#
pFP2IO17
FP2IO[27:0]
pFP2IO16
pFP2IO10
pFP2IO14
pFP2IO11
pFP2IO13
pAB7
pAB8
pAB9
pAB6
pAB11
pAB10
pDB8
pDB12
pDB9
pDB13
pDB11
pDB10
C33_PEDCLK
C33_PEDST1
C33_PEDST2
C33_PEDSIO
C33_PEDST0
C33_PEDCPCO
pAB6
pAB7
pAB8
pAB9
pAB10
pAB11
pBS#
pDB8
pDB9
pDB10
pDB11
pDB12
pDB13
pFP2IO10
pFP2IO11
pFP2IO13
pFP2IO14
pFP2IO16
pFP2IO17
1.8VDD
CORE
HIOVDD
HIO
PIO1VDD
PIO1
IOVDD
OSC
1.8VDD
PLL2
1.8VDD
3.3VDD
SDVDD
PIO2VDD
PIO2
CM1VDD
CM1
1.8VDD
PLL1
GND3
GND2GND1
IOVDD
IO
HIOVDD_IN
3.3VDD
HIOVDD
PIO1VDD_IN
3.3VDD
PIO1VDD
PIO2VDD_IN
3.3VDD
PIO2VDD
CM1VDD_IN
3.3VDD
CM1VDD
IOVDD_IN
3.3VDD
IOVDD
GND1 GND2 GND3
SDVDDCORE PLL1 PLL2 OSC HIO
PIO1 PIO2
IO CM1
FP2IO[27:0]
4
FP1IO[23:0]
4,5
PWM2
4
PWM1
4
SCL
4,5
SDA
4,5
CM1DAT4
5
CM1CLKOUT
5
CM1FIELD5CM1DAT55CM1VREF5CM1DAT65CM1DAT25CM1DAT15CM1DAT0
5
CM1CLKIN
5
CM1DAT35CM1HREF5
CM1DAT7
5
MEMA[12:0]
2
MEMCLK
2
MEMCKE
2
MEMWE#2MEMCAS#2MEMCS#2MEMRAS#2MEMBA12MEMBA0
2
MEMDQM12MEMDQM22MEMDQM32MEMDQM0
2
MEMDQ[31:0]
2
AB[20:0]
2,3,5
DB[15:0]
3
CS#
3
TEA#
2,3
WAIT#3IRQ
3
M/R#
3,5
RD#
3
RD/WR#
3
BE0#3BE1#
2,3
BS#
3
BURST#
2,3
BDIP#
2,3
RESET#
2,3,5
CNF02CNF12CNF2
2
BUSCLK
3
CLKI2OSCI
2
OSCO
2
SPIDIO
2
SPICS#2SPICLK2WSIO4SCKIO4SDO4MCLKO
4
Title
Size Doc ument Number Rev
Date:
Sheet of
<Doc> 1.0
S2D13515 QFP256
C
15Tuesday, May 27, 2008
Title
Size Doc ument Number Rev
Date: Sheet of
<Doc> 1.0
S2D13515 QFP256
C
15Tuesday, May 27, 2008
Title
Size Doc ument Number Rev
Date: Sheet of
<Doc> 1.0
S2D13515 QFP256
C
15Tuesday, May 27, 2008
Place a 0.01uF and a 0.1uF cap on each
COREVDD power pin of the S2D13515
Place a 0.01uF and a 0.1uF cap on each
HIOVDD power pin of the S2D13515
Place a 0.01uF and a 0.1uF cap on each
PIO1VDD power pin of the S2D13515
Place a 0.01uF and a 0.1uF cap on each
OSCVDD power pin of the S2D13515
Place a 0.01uF and a 0.1uF cap on each
SDVDD power pin of the S2D13515
Place a 0.01uF and a 0.1uF cap on each
PIO2VDD power pin of the S2D13515
Place a 0.01uF and a 0.1uF cap on each
CM1VDD power pin of the S2D13515
Place a 0.01uF and a 0.1uF cap on each
IOVDD power pin of the S2D13515
Board default configuration:
-indirect interface Intel 80, 16-bit
-C33 Debug port from AB[11:6]
-EID signals from FP1IO i nt erf ac e
-Keybord interface on AB[20:12]
Signal traces must be less
than 5cm.
Place these resistors as
close to U1 as possible.
For Indirect
Host
Interface
For REG[001Ch] bit 0 =
1b, C33 debug pins on
FP2IO
For Direct 8-bit
Interface
R23 33 1%R23 33 1%
R212
0R212 0
R27
33 1%R27 33 1%
R11
33 1%R11 33 1%
C7
0.1uFC70.1uF
R57
33 1%R57 33 1%
123
JP7
HIOVDD SOURCE
JP7
HIOVDD SOURCE
R37
33 1%R37 33 1%
C11
0.01uF
C11
0.01uF
R67
0R67 0
C54
0.1uF
C54
0.1uF
R16
33 1%R16 33 1%
R72
0_npR72 0_np
C56
0.01uF
C56
0.01uF
R47
33 1%R47 33 1%
R8 33 1%R8 33 1%
R13
33 1%R13 33 1%
C16
0.01uF
C16
0.01uF
SH7
.100 in. Jumper Shunt
SH7
.100 in. Jumper Shunt
C46
0.01uF
C46
0.01uF
C38
0.01uF
C38
0.01uF
L1
FerriteL1Ferrite
R22
33 1%R22 33 1%
C62
0.01uF
C62
0.01uF
R24
33 1%R24 33 1%
R213
0R213 0
R58
33 1%R58 33 1%
R43
33 1%R43 33 1%
R7
33 1%R7 33 1%
123
JP12
CM1VDD SOURCE
JP12
CM1VDD SOURCE
R66
0R66 0
C20
0.1uF
C20
0.1uF
R18
33 1%R18 33 1%
L6
FerriteL6Ferrite
R48
33 1%R48 33 1%
R71
0_npR71 0_np
C6
0.1uFC60.1uF
R81
0_npR81 0_np
C10
0.01uF
C10
0.01uF
R38
33 1%R38 33 1%
SH12
.100 in. Jumper Shunt
SH12
.100 in. Jumper Shunt
1
2
JP4
OSCVDD1
JP4
OSCVDD1
C53
0.1uF
C53
0.1uF
R60
33 1%R60 33 1%
C15
0.01uF
C15
0.01uF
R9
33 1%R9 33 1%
R14
33 1%R14 33 1%
R17
33 1%R17 33 1%
R29
33 1%R29 33 1%
R15
33 1%R15 33 1%
R52 0_npR52 0_np
R32
33 1%R32 33 1%
C22
10uF
C22
10uF
C31
0.1uF
C31
0.1uF
C37
0.01uF
C37
0.01uF
SH4
.100 in. Jumper Shunt
SH4
.100 in. Jumper Shunt
C52
0.1uF
C52
0.1uF
R65
0R65 0
R59
33 1%R59 33 1%
R80
0_npR80 0_np
R210
0R210 0
C5
0.1uFC50.1uF
L5
FerriteL5Ferrite
R21
33 1%R21 33 1%
C9
0.01uFC90.01uF
R28
33 1%R28 33 1%
R63
0R63 0
C51
0.1uF
C51
0.1uF
R198
0_npR198 0_np
1
2
JP3
PLLVDD2
JP3
PLLVDD2
R1
33 1%R1 33 1%
C24
0.1uF
C24
0.1uF
C14
0.01uF
C14
0.01uF
R214
0R214 0
C36
0.01uF
C36
0.01uF
R33 33 1%R33 33 1%
R10
33 1%R10 33 1% C30
0.1uF
C30
0.1uF
SH3
.100 in. Jumper Shunt
SH3
.100 in. Jumper Shunt
R79
0_npR79 0_np
123
JP13
IOVDD SOURCE
JP13
IOVDD SOURCE
L2
FerriteL2Ferrite
R12 33 1%R12 33 1%
1
2
JP10
CM1VDD
JP10
CM1VDD
C42
0.1uF
C42
0.1uF C50
0.1uF
C50
0.1uF
246810
12
13579
11
H1
JTAGH1JTAG
1
2
JP5
PIO1VDD
JP5
PIO1VDD
1
2
JP2
PLLVDD1
JP2
PLLVDD1
R25
33 1%R25 33 1%
R202
0_npR202 0_np
C28
0.1uF
C28
0.1uF
C4
0.1uFC40.1uF
R3
33 1%R3 33 1%
SH13
.100 in. Jumper Shunt
SH13
.100 in. Jumper Shunt
SH11
.100 in. Jumper Shunt
SH11
.100 in. Jumper Shunt
SH5
.100 in. Jumper Shunt
SH5
.100 in. Jumper Shunt
SH2
.100 in. Jumper Shunt
SH2
.100 in. Jumper Shunt
R45
33 1%R45 33 1%
C57
0.01uF
C57
0.01uF
R49
33 1%R49 33 1%
C13
0.01uF
C13
0.01uF
R39
33 1%R39 33 1%
R215
0R215 0
R78
0_npR78 0_np
C29
0.1uF
C29
0.1uF
C34
0.01uF
C34
0.01uF
R70
0_npR70 0_np
R76
0_npR76 0_np
C49
0.1uF
C49
0.1uF
R203
0R203 0
C41
0.1uF
C41
0.1uF
C18
1nF
C18
1nF
R44
33 1%R44 33 1%
R2
33 1%R2 33 1%
R201
0_npR201 0_np
L3
FerriteL3Ferrite
123
JP8
PIO1VDD SOURCE
JP8
PIO1VDD SOURCE
R34
33 1%R34 33 1%
C58
0.01uF
C58
0.01uF
R204
0R204 0
C3
0.1uFC30.1uF
R40
33 1%R40 33 1%
R205
0R205 0
C23
0.01uF
C23
0.01uF
R206
0R206 0
1
2
JP14
IOVDD
JP14
IOVDD
R207
0R207 0
R61
33 1%R61 33 1%
R77
0_npR77 0_np
246810
13579
H2
C33 DEBUG PORTH2C33 DEBUG PORT
R51
33 1%R51 33 1%
C59
0.01uF
C59
0.01uF
R75
0_npR75 0_np
C21
1nF
C21
1nF
R50
33 1%R50 33 1%
R208
0R208 0
C33
0.01uF
C33
0.01uF
R41
33 1%R41 33 1%
1
2
JP6
HIOVDD
JP6
HIOVDD
C27
0.1uF
C27
0.1uF
C39
0.1uF
C39
0.1uF
R19
33 1%R19 33 1%
123
JP9
PIO2VDD SOURCE
JP9
PIO2VDD SOURCE
SH8
.100 in. Jumper Shunt
SH8
.100 in. Jumper Shunt
R200
0_npR200 0_np
C43
0.1uF
C43
0.1uF
SH14
.100 in. Jumper Shunt
SH14
.100 in. Jumper Shunt
SH6
.100 in. Jumper Shunt
SH6
.100 in. Jumper Shunt
R53
33 1%R53 33 1%
C2
0.1uFC20.1uF
R64
0_npR64 0_np
C17
0.1uF
C17
0.1uF
R30
33 1%R30 33 1%
R4
33 1%R4 33 1%
R35
33 1%R35 33 1%
C60
0.01uF
C60
0.01uF
1
2
JP1
COREVDD
JP1
COREVDD
C40
0.1uF
C40
0.1uF
R20
33 1%R20 33 1%
1
2
JP11
PIO2VDD
JP11
PIO2VDD
R74
0_npR74 0_np
1
2
JP15
SDVDD
JP15
SDVDD
SH9
.100 in. Jumper Shunt
SH9
.100 in. Jumper Shunt
C44
0.01uF
C44
0.01uF
FP2IO16
T11
FP2IO24P9FP2IO22
M9
PIO2VDD
R16
FP2IO25
R9
FP2IO26
K8
FP1IO4P7FP1IO5
R7
COREVDD
M16
FP1IO10
K7
FP1IO23
T5
FP2IO15
P11
PIO2VDD
N9
COREVDD
E1
CLKI
B1
AB0
H6
DB13
H3
VSS
A1
AB17
E5
FP2IO23
T10
DB10
J6
AB8
G6
AB1
H7
AB18
D3
AB7
F2
AB11
F5
DB14
H4
FP1IO19
P3
FP1IO21
N5
FP1IO2
P8
FP2IO21
L9
DB9
J3
FP1IO1
M8
AB19
D4
AB20
C1
VSS
A16
FP1IO9
L7
FP1IO3
R8
SDO
N14
SPICS#
M15
FP1IO8
M7
FP1IO16L6FP1IO15M6FP1IO20
P5
FP1IO13
R5
AB15
D1
AB14
E4
AB13E3AB12
F6
HIOVDD
L5
VSS
E13
COREVDD
L2
AB10
F3
AB6F1AB5
G5
AB4G4AB3G3AB2
G2
HIOVDD
J4
VSS
B12
DB15
H2
DB12H1DB11
J7
MCLKO
N16
SCKIO
N15
FP2IO0
P14
FP2IO1
P16
FP2IO2
P15
VSS
J9
FP2IO3
R15
FP2IO4
R14
FP2IO7
P13
FP2IO8
N12
VSS
J8
PIO2VDD
R11
FP2IO9
P12
FP2IO10
K10
FP2IO11
T13
FP2IO13
L10
FP1IO17R3FP1IO14P4FP1IO11
T3
VSS
E15
PIO1VDD
T8
RESET#
R2
VSS
F4
FP1IO6
T7
FP1IO0
L8
AB16
D2
VSS
K14
IOVDD
M14
PWM1
M13
AB9
G7
FP1IO18
T2
FP1IO22
R4
PIO1VDD
T6
FP1IO12
R6
FP1IO7
N7
VSS
G13
FP2IO27
T9
VSS
H8
FP2IO18
K9
FP2IO20
R10
FP2IO19
P10
PIO1VDD
T4
FP2IO17
N10
VSS
H9
FP2IO14
N11
FP2IO12
R12
FP2IO6
M11
FP2IO5
T15
WSIO
N13
PWM2
M12
COREVDD
D6
SPICLK
L12
PIO2VDD
T14
DB8
J2
VSS
C2
BUSCLK
J1
HIOVDD
E2
DB7J5DB6
K5
DB5K4DB4K3DB3K1DB2K2DB1K6DB0
L1
VSS
C7
COREVDD
E16
HIOVDD
G1
CS#
L3
M/R#
M1
RD#M2RD/WR#M3BE0#M4BE1#
N1
BS#
M5
BURST#
N2
BDIP#N3TEA#P2WAIT#P1IRQ
R1
VSS
D11
SPIDIO
L11
TESTEN
L14
TDO
L15
TCK
K11
TDI
L16
TMS
K12
TRST
K13
VSS
L4
CNF2
K16
CNF1
K15
CNF0
J10
MEMDQM3
J11
MEMDQM2
J12
MEMDQM1
J13
MEMDQM0
J14
MEMCKE
J16
MEMCS#
J15
MEMRAS#
H15
MEMCAS#
H16
VSS
L13
SDVDD
H14
MEMWE#
H13
MEMBA1
H12
MEMBA0
H11
MEMA12
G16
MEMA11
H10
MEMA10
G15
MEMA9
G14
MEMA8
F15
VSS
M10
SDVDD
E11
MEMDQ31
G12
MEMDQ15
G11
MEMDQ30
F14
MEMDQ14
F13
VSS
N4
COREVDD
N6
MEMDQ29
F12
MEMDQ13
G10
MEMDQ28
D13
MEMDQ12
D16
MEMDQ27
E14
VSS
N8
SDVDD
D14
MEMDQ11
C16
MEMDQ26
D15
MEMDQ10
B16
MEMDQ25
C15
MEMDQ9
C14
MEMDQ24
B15
SDVDD
B10
VSS
H5
MEMDQ8
B14
MEMDQ23
A14
MEMDQ7
E12
MEMDQ22
C13
MEMDQ6
B13
MEMDQ21
A13
MEMDQ5
F11
MEMDQ20
D12
SDVDD
A15
COREVDD
T12
VSS
T16
MEMCLK
A12
VSS
T1
MEMDQ4
C11
MEMDQ19
F10
MEMDQ3
G9
MEMDQ18
B11
MEMDQ2
E10
MEMDQ17
F9
MEMDQ1
A11
MEMDQ16
D10
MEMDQ0
C10
VSS
R13
SDVDD
F16
MEMA7
E9
MEMA6
A10
MEMA5D9MEMA4G8MEMA3C9MEMA2F8MEMA1B9MEMA0
A9
SCL
E8
SDA
D8
CM1FIELDC8CM1VREF
B8
CM1HREF
F7
CM1VDD
E7
CM1DAT7
E6
CM1DAT6
D7
CM1DAT5
A8
CM1CLKOUT
A7
VSS
P6
CM1CLKIN
B7
COREVDD
C12
CM1DAT4
D5
CM1DAT3C6CM1DAT2C5CM1DAT1C4CM1DAT0
C3
OSCVSS
B6
OSCO
A6
OSCI
A5
OSCVDD
B5
PLL2VSS
B4
VCP2
A4
PLL2VDD
A3
PLL1VSS
B3
VCP1
A2
PLL1VDD
B2
S2D13515PBGA256
U1
S2D13515PBGA256
U1
SH1
.100 in. Jumper Shunt
SH1
.100 in. Jumper Shunt
C26
0.1uF
C26
0.1uF
R69
0R69 0
R211
0R211 0
C32
0.01uF
C32
0.01uF
L4
FerriteL4Ferrite
R199
0_npR199 0_np
C19
10uF
C19
10uF
SH10
.100 in. Jumper Shunt
SH10
.100 in. Jumper Shunt
R26
33 1%R26 33 1%
C35
0.01uF
C35
0.01uF
R54
33 1%R54 33 1%
R31
33 1%R31 33 1%
R5
33 1%R5 33 1%
C47
0.01uF
C47
0.01uF
SH15
.100 in. Jumper Shunt
SH15
.100 in. Jumper Shunt
C1
0.1uFC10.1uF
C48
0.01uF
C48
0.01uF
R36 33 1%R36 33 1%
C55
0.1uF
C55
0.1uF
C8
0.1uFC80.1uF
R62
33 1%R62 33 1%
R73
0_npR73 0_np
C12
0.01uF
C12
0.01uF
R209
0R209 0
R42
33 1%R42 33 1%
R55
33 1%R55 33 1%
C61
0.01uF
C61
0.01uF
R46
33 1%R46 33 1%
R6
33 1%R6 33 1%
R68
0R68 0
R197
0_npR197 0_np
C25
0.1uF
C25
0.1uF
R56
0R56 0
C45
0.01uF
C45
0.01uF
Chapter 6 Schematic Diagrams
S5U13515P00C100 Evaluation Board User Manual (Rev 1.1) EPSON 29
Figure 6-1: S5U13515P00C100 Schematics (1 of 5)
Page 30
Chapter 6 Schematic Diagrams
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
MEMDQ4
MEMDQ27
MEMDQ21
MEMDQ2
MEMDQ19
MEMDQ7
MEMDQ31
MEMDQ13
MEMDQ3
MEMDQ24
MEMDQ30
MEMDQ22
MEMDQ1
MEMDQ15
MEMDQ11
MEMDQ10
MEMDQ8
MEMDQ23
MEMDQ16
MEMDQ26
MEMDQ14
MEMDQ25
MEMDQ9
MEMDQ0
MEMDQ12
MEMDQ6
MEMDQ5
MEMDQ18
MEMDQ29
MEMDQ28
MEMDQ20
MEMDQ17
MEMA5
MEMA2
MEMA3
MEMA9
MEMA6
MEMA8
MEMA1
MEMA0
MEMA10
MEMA7
MEMA11
MEMA4
MEMA7
MEMA8
MEMA5
MEMA0
MEMA1
MEMA4
MEMA3
MEMA6
MEMA10
MEMA11
MEMA2
MEMA9
MEMBA1
MEMBA0
MEMWE#
MEMCAS#
MEMRAS#
MEMCS#
MEMCKE
MEMCLK
MEMBA0
MEMCAS#
MEMRAS#
MEMCLK
MEMBA1
MEMCKE
MEMWE#
MEMCS#
MEMA12
MEMA12
AB0
AB4
AB3
3.3VDD
3.3VDD
3.3VDD
3.3VDD 3.3VDD
HIOVDD
3.3VDD 1.8VDD
3.3VDD
3.3VDD
HIOVDD
GND3
GND3
HIOVDD
IOVDD
MEMDQ[31:0] 1
MEMDQ[31:0] 1
MEMA[12:0]
1
MEMA[12:0]
1
MEMBA0
1
MEMBA11MEMCS#1MEMWE#1MEMCAS#1MEMRAS#1MEMDQM01MEMDQM1
1
MEMDQM21MEMDQM3
1
MEMCKE1MEMCLK
1
OSCI
1
CLKI
1
OSCO
1
SPICS#
1
SPICLK
1
SPIDIO
1
RESET#
1,3,5
BE1#
1,3
BURST#
1,3
BDIP#
1,3
TEA#
1,3
AB[20:0]
1,3,5
CNF01
CNF11CNF2
1
Title
Size Document Number Rev
Date:
Sheet of
<Doc> 1.0
SDRAM / Flash / Clocks / Reset / 1.8V Supply
B
25Thursday, May 15, 2008
Title
Size Document Number Rev
Date: Sheet of
<Doc> 1.0
SDRAM / Flash / Clocks / Reset / 1.8V Supply
B
25Thursday, May 15, 2008
Title
Size Document Number Rev
Date: Sheet of
<Doc> 1.0
SDRAM / Flash / Clocks / Reset / 1.8V Supply
B
25Thursday, May 15, 2008
SDRAM I/F
1-2 32BIT
2-3 16BIT
Place a 0.01uF and a 0.1uF cap on each
VDD power pin of the two SDRAM chips.
Place a 0.01uF and a 0.1uF cap on each
VDDQ power pin of the two SDRAM chips.
TTL/CMOS Oscillator
This resistor is used to
pull down CLKI input when
oscillator is not used.
If an oscilla tor is used,
then this resistor can be
removed.
CNF3
CNF4 CNF5
CNF6
CNF7
C87
0.1uF
C87
0.1uF
C64
10uF
C64
10uF
2
4 3
1
SW2
SW TACT-SPST
SW2
SW TACT-SPST
1
2
3
4
8
7
6
5
SW1
SW4_DIPSW4
SW1
SW4_DIPSW4
R84
1k
R84
1k
C76
0.1uF
C76
0.1uF
C99
0.01uF
C99
0.01uF
R90
150k 1%
R90
150k 1%
R103
0
R103
0
XIN
1
XOUT
4
NC
2
NC
3
X1
MA-506 20.0000MX1MA-506 20.0000M
C88
0.01uF
C88
0.01uF
C82
0.1uF
C82
0.1uF R107
0
R107
0
R87
0R87 0
C94
0.01uF
C94
0.01uF
C63
0.1uF
C63
0.1uF
R98
0_np
R98
0_np
R95
0_np
R95
0_np
C77
0.1uF
C77
0.1uF
NC
3NC4NC5NC6NC11NC12NC13NC14
CLK
16
CS#
7
DIN
15
DOUT
8
HOLD#
1
VCC
2
VSS
10
W#/VPP
9
U2
M25P32-VMFU2M25P32-VMF
R104
0_np
R104
0_np
C100
0.01uF
C100
0.01uF
R89
10k
R89
10k
C72
0.1uF
C72
0.1uF
TP1TP1
C67
0.1uF
C67
0.1uF
R92
10k
R92
10k
C89
0.01uF
C89
0.01uF
C83
0.1uF
C83
0.1uF
C73
10uF
C73
10uF
C95
0.01uF
C95
0.01uF
A023A124A2
25A326A429A530A631A732A833A934
A10
22
A11
35
BA1
21
BA0
20
VSSQ6VSSQ
12
VSSQ
52
VSS
28
VSS41VSS
54
VSSQ
46
VDD1VDD
14
VDD
27
VDDQ
3
VDDQ9VDDQ43VDDQ
49
D0
2D14D25D37D48
D5
10D611D713D842D944
D1045D1147D1248D1350D1451D15
53
DQML
15
DQMH
39
WE#
16
CAS#17RAS#
18
CS#
19
CLK
38
CKE
37NC40
NC/A12
36
SDRAM 128Mb x 16-bit x 4 banks
U3
128M16 DRAM
SDRAM 128Mb x 16-bit x 4 banks
U3
128M16 DRAM
R105
0
R105
0
C66
18pF
C66
18pF
C78
0.1uF
C78
0.1uF
C69
0.1uF
C69
0.1uF
C101
0.01uF
C101
0.01uF
SH16
.100 in. Jumper Shunt
SH16
.100 in. Jumper Shunt
123
JP16
SDRAM I/F
JP16
SDRAM I/F
C90
0.01uF
C90
0.01uF
C84
0.1uF
C84
0.1uF
R88
33 1%R88 33 1%
IN
1
OUT
3
GND
2
TAB
4
U5
MIC37100-1.8WSU5MIC37100-1.8WS
R99
0_np
R99
0_np
C96
0.01uF
C96
0.01uF
R96
0_np
R96
0_np
R106
0_np
R106
0_np
C70
10uF
C70
10uF
C79
0.1uF
C79
0.1uF
R85
0R85 0
OE
1
OUT
8
GND
7
VDD
14
Y1
14-Pin DIPY114-Pin DIP
C71
0.1uF
C71
0.1uF
R93 10kR93 10k
R91
10k
R91
10k
R83
0R83 0
C91
0.01uF
C91
0.01uF
C85
0.1uF
C85
0.1uF R108
0_np
R108
0_np
C74
0.1uF
C74
0.1uF
C97
0.01uF
C97
0.01uF
C80
0.1uF
C80
0.1uF
R86 0R86 0
R82
1MR82 1M
C92
0.01uF
C92
0.01uF
C86
0.1uF
C86
0.1uF
R101
0_np
R101
0_np
R94
10k
R94
10k
C68
0.01uF
C68
0.01uF
R97
0_np
R97
0_np
C75
0.1uF
C75
0.1uF
A023A124A2
25A326A429A530A631A732A833A934
A1022A11
35
BA1
21
BA0
20
VSSQ
6
VSSQ
12
VSSQ
52
VSS
28
VSS
41
VSS
54
VSSQ
46
VDD
1
VDD
14
VDD
27
VDDQ3VDDQ
9
VDDQ
43
VDDQ
49
D0
2D14D25D37D48
D5
10D611D713D842D944
D1045D1147D1248D1350D1451D15
53
DQML
15
DQMH
39
WE#
16
CAS#
17
RAS#
18
CS#19CLK
38
CKE
37NC40
NC/A12
36
SDRAM 128Mb x 16-bit x 4 banks
U4
128M16 DRAM
SDRAM 128Mb x 16-bit x 4 banks
U4
128M16 DRAM
C98
0.01uF
C98
0.01uF
R100
0_np
R100
0_np
C65
18pF
C65
18pF
C81
0.1uF
C81
0.1uF R102
0
R102
0
C93
0.01uF
C93
0.01uF
Figure 6-2: S5U13515P00C100 Schematics (2 of 5)
30 EPSON S5U13515P00C100 Evaluation Board User Manual (Rev 1.1)
Page 31
Chapter 6 Schematic Diagrams
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
AB19
AB17
AB9
AB15
AB13
AB11 AB12
AB14
AB4
AB6
AB18
AB20
AB3
AB7
AB5
RD/WR#
BE0#
DB12
DB14
DB1
DB3
DB5
DB7
DB8
DB10
DB15
DB13
DB11
DB0
DB9
DB2
DB4
DB6
AB20
AB18
AB16
AB14
AB12
AB10
AB8
AB7
AB5
AB3
AB1
AB17
AB19
AB0
AB2
AB4
AB6
AB9
AB11
AB13
AB15
HEARTBEAT ENUMERATED
HEARTBEAT ENUMERATED
CS# M/R#
DB13
DB15
DB14
BE1#
RD#
DB11
DB8
DB12
DB9
DB10
DB6
DB7
DB3
DB4
DB5
AB1
AB2
DB2
DB1
DB0
AB0
BE1#
RD#
WAIT#
IRQ
AB16
CS#
M/R#
BE0#
RD/WR#
IRQ
WAIT#
AB10
AB8
AB2
AB1
HIOVDD
3.3VDD
3.3VDD
3.3VDD
HIOVDDHIOVDD_IN
RD#
1
BE1#
1,2
BS#
1
DB[15:0]
1
BUSCLK
1
RD/WR#
1
CS#
1
M/R#
1,5
BE0#
1
TEA#
1,2IRQ1
WAIT#
1
BDIP#
1,2
RESET#
1,2,5
AB[20:0]
1,2,5
BURST#
1,2
Title
Size Document Number Rev
Date:
Sheet of
<Doc> 1.0
Host connectors
B
35Tuesday, August 19, 2008
Title
Size Document Number Rev
Date: Sheet of
<Doc> 1.0
Host connectors
B
35Tuesday, August 19, 2008
Title
Size Document Number Rev
Date: Sheet of
<Doc> 1.0
Host connectors
B
35Tuesday, August 19, 2008
This resistor is used to pull
down BUSCLK input when it is
not used. If BUSCLK input is
used, then this resistor can
be removed.
Place these resistors as close as possible
to H3 and H4 headers.
R200 and R201 are not
resistors on PCB. They
are external wires
added to the board.
R202 and R203 are not
resistors on PCB. They
are external wires
added to the board.
R113 0_npR113 0_np
R128
0R128 0
R146
0_npR146 0_np
TP2TP2
R136 0_npR136 0_np
R133
0R133 0
R1200R120
0
D1
LED1D1LED1
AK
R145 0_npR145 0_np
R1310R131
0
R1110R111
0
R157
270 1%
R157
270 1%
R130
0R130 0
R117
0R117 0
R139 0_npR139 0_np
R153
0_npR153 0_np
R152
0_npR152 0_np
R202
0R202 0
R142
0_np
R142
0_np
R114
0R114 0
R122 0R122 0
R119
0R119 0
TPGND1
TP_SMT
TPGND1
TP_SMT
1
R147 0_npR147 0_np
R2030R203
0
H4
HEADER_17X2H4HEADER_17X2
246810121416182022242628303234
13579
1113151719212325272931
33
R159
270 1%
R159
270 1%
R149
0_np
R149
0_np
P2
HEADER_20X2P2HEADER_20X2
2468101214161820222426283032343638
40
13579
111315171921232527293133353739
R138
0_np
R138
0_np
R121
0R121 0
R1250R125
0
R141
0_npR141 0_np
R154 0R154 0
D3
3.3V PowerD33.3V Power
AK
R132 0R132 0
R109
0R109 0
R1150R115
0
R123
0R123 0
R155
0_npR155 0_np
R135
0_npR135 0_np
R144
0_npR144 0_np
R156
10k
R156
10k
R1160R116
0
R148
0_npR148 0_np
R1270R127
0
H3
HEADER_20X2H3HEADER_20X2
2468101214161820222426283032343638
40
13579
111315171921232527293133353739
R134 0_npR134 0_np
TP3.3VDD1
TP_SMT
TP3.3VDD1
TP_SMT
1
R200 0R200 0
R124
0R124 0
R110 0R110 0
R143
0_npR143 0_np
R151
0_np
R151
0_np
R158
270 1%
R158
270 1%
R140
0_np
R140
0_np
R1180R118
0
R112 0R112 0
R201
0R201 0
R126
0R126 0
R1290R129
0
R137
0_npR137 0_np
R150
0_npR150 0_np
D2
LED2D2LED2
AK
P1
HEADER_20X2P1HEADER_20X2
2468101214161820222426283032343638
40
13579
111315171921232527293133353739
Figure 6-3: S5U13515P00C100 Sc hematics (3 of 5)
S5U13515P00C100 Evaluation Board User Manual (Rev 1.1) EPSON 31
Page 32
Chapter 6 Schematic Diagrams
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
FPDAT4FP2IO4
FPDAT2
FP2IO2
FPDAT3
FP2IO3
FPDAT1
FP2IO1
FPDAT0
FP2IO0
FPDAT6
FP2IO6
FPDAT9
FP2IO9
FPDAT5FP2IO5
FPDAT8
FP2IO8
FPDAT7
FP2IO7
FPDAT11
FP2IO11
FPDAT10
FP2IO10
FPDAT14FP2IO14
FPDAT13
FP2IO13
FPDAT12
FP2IO12
FPFRAME
FP2IO25
FPLINE
FP2IO24
FPDAT15
FP2IO15
FPSHIFT
FP2IO27
FPDAT16
FP2IO16
FPDAT17
FP2IO17
FPDAT19
FP2IO19
POLGMA
FPDAT21
FP2IO21
CPV
FPDAT23FP2IO23
DEXR
FPDAT20FP2IO20
FP2IO26
OE
FPDAT22FP2IO22
FPDRDYFP2IO26
FP1IO0
FP1IO1
FP1IO2
FP1IO3
FP1IO5
FP1IO6
FP1IO4
FP1IO7
FP1IO10
FP1IO13
FP1IO8
FP1IO12
FP1IO9
FP1IO15
FP1IO14
FP1IO11
FP1IO23
FP1IO21
FP1IO20
FP1IO22
FP1IO17
FP1IO16
FP2IO25
POLGMA
FP1IO11
DEXR
FP1IO14
CPV
FP1IO17
OE
FP1IO18
LED_DIM_OUT
FP1IO19
PWM1
LED_DIM_OUT
FP2IO18
FP2IO21FPSO
FP2IO24
FP2IO18
FP2IO19
FP2IO20
PWM1
SCKIO
SDO
WSIO
MCLKO
WSIO
SCKIO
SDO
MCLKO
VBACKLIGHT
PIO2VDD
VBACKLIGHT3.3VDD
PIO1VDD
VBACKLIGHT
PIO1VDD_IN PIO2VDD_IN
CM1VDD_IN
IOVDD_IN
IOVDD
FP2IO[27:0]
1
FP1IO[23:0]
1,5
SCKIO
1
PWM2
1
WSIO
1
SDA
1,5
SCL
1,5
PWM1
1
MCLKO
1
SDO
1
Title
Size Document Number Rev
Date:
Sheet of
<Doc> 1.0
LCD, I2S and PWM connectors
B
45Thursday, May 15, 2008
Title
Size Document Number Rev
Date: Sheet of
<Doc> 1.0
LCD, I2S and PWM connectors
B
45Thursday, May 15, 2008
Title
Size Document Number Rev
Date: Sheet of
<Doc> 1.0
LCD, I2S and PWM connectors
B
45Thursday, May 15, 2008
Adjustable Step Up Power Supply
12V@ 100mA to 25V@60mA
Vout=1.23x[1+(R17+ R 20 )/R1 9] (V)
Place these
resistors close to
H8 connector.
Place these
resistors close to
H6 connector.
Place these
resistors close to
H7 connector.
R164
0R164 0
R216
0_npR216 0_np
C103
10uF 35V
C103
10uF 35V
VIN
5
/SHDN
4
GND
2SW1FB3
U6
LM2733YU6LM2733Y
R171
0R171 0
R219
0_np
R219
0_np
1
3
2
R175
200k
R175
200k
R174
10k
R174
10k
R167
0_npR167 0_np
246810
13579
H9
PWM/PWR PORTH9PWM/PWR PORT
R173
120k
R173
120k
R1720R172
0
R168
0R168 0
R169
0_npR169 0_np
R217
0_np
R217
0_np
R177
13.3k 1%
R177
13.3k 1%
R160
0R160 0
246
8
10121416182022
24
13579111315171921
23
H8
I2S PORTH8I2S PORT
2468101214161820222426283032343638
40
13579
111315171921232527293133353739
H5
FP2 LCD ConnectorH5FP2 LCD Connector
C102
2.2uF 10V
C102
2.2uF 10V
R170
0_npR170 0_np
R176
56k
R176
56k
A K
D4
MBR0540D4MBR0540
2468101214161820222426283032343638
40
13579
111315171921232527293133353739
H6
FP1 LCD ConnectorH6FP1 LCD Connector
R162
0R162 0
R163
0_npR163 0_np
R166
0R166 0
2468101214161820222426283032343638
40
13579
111315171921232527293133353739
H7
FP2 Extended LCD ConnectorH7FP2 Extended LCD Connector
1
2
3
F2
ACF451832-222F2ACF451832-222
TP3TP3
R218
0_np
R218
0_np
L7
10uHL710uH
R165 0_npR165 0_np
C104
150pF
C104
150pF
1
2
3
F1
ACH32C-333-TF1ACH32C-333-T
R161
0_npR161 0_np
32 EPSON S5U13515P00C100 Evaluation Board User Manual (Rev 1.1)
Figure 6-4: S5U13515P00C100 Schematics (4 of 5)
Page 33
Chapter 6 Schematic Diagrams
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
KBC0
KBC1
KBC2
KBR0
KBR0
FP1IO16
FP1IO20
FP1IO15
FP1IO22
FP1IO21
FP1IO23
AB20
KBR1
KBR2
KBC0
KBC1
KBC2
AB14
AB15
AB16
AB19
KBR1
KBR2
CM1VDD
CM1VDD
HIOVDD PIO1VDD
CM1VDD
CM1CLKOUT1
SCL
1,4
SDA
1,4
CM1DAT01
CM1DAT21CM1DAT41CM1DAT61CM1CLKIN
1
CM1DAT1
1
CM1DAT31CM1DAT51CM1DAT71CM1VREF1CM1HREF1CM1FIELD
1
RESET#
1,2,3
M/R#
1,3
FP1IO[23:0]
1,4
AB[20:0]
1,2,3
Title
Size Document Number Rev
Date:
Sheet of
<Doc> 1.0
Camera i/f, Keypad
B
55Thursday, May 15, 2008
Title
Size Document Number Rev
Date: Sheet of
<Doc> 1.0
Camera i/f, Keypad
B
55Thursday, May 15, 2008
Title
Size Document Number Rev
Date: Sheet of
<Doc> 1.0
Camera i/f, Keypad
B
55Thursday, May 15, 2008
Place these capacitors close
to pin 15 of the header.
If Kypad i/f from
FP1IO pins, popul ate
this resistor
If Kypad i/f is from M/R#, AB
pins, populate this resistor
Place these
resistors as
close to the
S2D13515 as
possible.
0 5 10
1 6 11
2 7 12
Silkscreen
with Keypad
Matrix Order
A K
D8
MBR0540D8MBR0540
R195
0_np
R195
0_np
A K
D13
MBR0540
D13
MBR0540
2
4 3
1
SW11
SW TACT-SPST
SW11
SW TACT-SPST
2
4 3
1
SW8
SW TACT-SPST
SW8
SW TACT-SPST
2
4 3
1
SW5
SW TACT-SPST
SW5
SW TACT-SPST
R193
0_npR193 0_np
R181
0_npR181 0_np
A K
D10
MBR0540
D10
MBR0540
C105
1uF
C105
1uF
R1860R186
0
R182
10k
R182
10k
C106
0.1uF
C106
0.1uF
R187
0R187 0
A K
D7
MBR0540D7MBR0540
2
4 3
1
SW10
SW TACT-SPST
SW10
SW TACT-SPST
A K
D12
MBR0540
D12
MBR0540
2
4 3
1
SW7
SW TACT-SPST
SW7
SW TACT-SPST
R1880R188
0
R1850R185
0
2
4 3
1
SW4
SW TACT-SPST
SW4
SW TACT-SPST
R1900R190
0
A K
D9
MBR0540D9MBR0540
R184
10k
R184
10k
R1890R189
0
R178
2.2k
R178
2.2k
13579
1113151719
24681012141618
20
H10
CAMERA1
H10
CAMERA1
R180
0R180 0
R183
10k
R183
10k
R192
0_np
R192
0_np
A K
D5
MBR0540D5MBR0540
2
4 3
1
SW9
SW TACT-SPST
SW9
SW TACT-SPST
A K
D6
MBR0540D6MBR0540
2
4 3
1
SW6
SW TACT-SPST
SW6
SW TACT-SPST
R194
0_npR194 0_np
R179
2.2k
R179
2.2k
A K
D11
MBR0540
D11
MBR0540
R196
0_npR196 0_np
2
4 3
1
SW3
SW TACT-SPST
SW3
SW TACT-SPST
R191
0_npR191 0_np
Figure 6-5: S5U13515P00C100 Sc hematics (5 of 5)
S5U13515P00C100 Evaluation Board User Manual (Rev 1.1) EPSON 33
Page 34
Chapter 7 Board Layout
Chapter 7 Board Layout
Figure 7-1: S5U13515P00C100 Boar d Layout - Top View
34 EPSON S5U13515P00C100 Evaluation Board User Manual (Rev 1.1)
Page 35
Chapter 7 Board Layout
Figure 7-2: S5U13515P00C100 Board Layout - Bottom View
S5U13515P00C100 Evaluation Board User Manual (Rev 1.1) EPSON 35
Page 36
Chapter 8 References
Chapter 8 References
8.1 Documents
• Epson Research and Development, Inc., S2D13515 Hardware Functional Specification, document number X83A-A-001-xx.
8.2 Document Sources
• Epson Research and Development Website: http://www.erd.epson.com.
36 EPSON S5U13515P00C100 Evaluation Board User Manual (Rev 1.1)
Page 37
Chapter 8 References
Change Record
X83A-G-001-01 Revision 1.1 - Issued: September 9, 2009
• section 4.8 Keypad Interface - add not e “The keyboa rd is non- operati onal with the buttons SW3- SW11, mounted as they are on the board...” to start of section
X83A-G-001-01 Revision 1.0 - Issued: January 20, 2009
• Release as Revision 1.0
• section 3.1.2 CNF[7:3] - correct typo in table change “R104” to “R107”
• chapter 6 Schematic Diagrams - replace figure 6-3
X83A-G-001-00 Revision 0.03 - Issued: June 3, 2008
• globally add missing Figures
• globally add missing resistor numbers
• chapter 2 Features -in second bullet change “64MB” to “32 MB” and “32MB” to “16MB” respectively
• chapter 5 Parts List - add parts list data
• chapter 6 Schematic Diagrams - update all schematic diagrams
• chapter 7 Board Layout - add figures
X83A-G-001-00 Revision 0.02 - Issued: April 24, 2008
• section 2, changed package from QFP22 to PBGA
• section 2, changed “Headers for connection to cameras” to “Header for connection to cameras”
• section 2, removed “On-board video decoder allowing direct connection of an analog camera ”
• section 2, changed on-board keypad from “5x5” to “3x3”
• section 4.4.1, changed the SDRAM size from 256Mbit to 128Mbit
• section 4.7.1, removed Analog Camera and Video Decoder section
• section 4.8, changed 5x5 keypad to 3x3 keypad and updated keypad diagram
• section 6, updated schematic diagrams
X83A-G-001-00 Revision 0.01 - Issued: February 11, 2008
• initial draft of the user manual
• minor edits and formatting
S5U13515P00C100 Evaluation Board User Manual (Rev 1.1) EPSON 37
Page 38
International Sales Operations
AMERICA
EPSON ELECTRON I CS A MERICA, INC.
2580 Orchard Parkway San Jose, CA 95131,USA Phone: +1-800-228-3964 FAX: +1-408-922-0238
EUROPE
EPSON EUROPE ELECT R O N I CS G m b H
Riesstrasse 15, 80992 Munich, GERMANY Phone: +49-89-14005-0 FAX: +49-89-14005-110
ASIA
EPSON (CHINA) CO., LTD.
7F, Jinbao Bldg., No.89 Jinbao St., Dongcheng District, Beijing 100005, CHINA Phone: +86-10-6410-6655 FAX: +86-10-6410-7320
SHANGHAI BRANCH
7F, Block B, High-Tech Bldg., 900, Yishan Road, Shanghai 200233, CHINA Phone: +86-21-5423-5522 FAX: +86-21-5423-5512
SHENZHEN BRANCH
12F, Dawning Mansion, Keji South 12th Road, Hi-Tech Park, Shenzhen 518057, CHINA Phone: +86-755-2699-3828 FAX: +86-755-2699-3838
EPSON HONG KONG LTD.
20/F, Harbour Centre, 25 Harbour Road Wanchai, Hong Kong Phone: +852-2585-4600 FAX: +852-2827-4346 Telex: 65542 EPSCO HX
EPSON TAIWAN TECHNOLOGY & TRADING LTD.
14F, No. 7, Song Ren Road, Taipei 110, TAIWAN Phone: +886 -2-8786-6688 FAX: +886-2-8786-6660
EPSON SINGAPORE PTE., LTD.
1 HarbourFront Place, #03-02 HarbourFront Tower One, Singapore 098633 Phone: +65-6586-5500 FAX: +65-6271-3182
SEIKO EPSON CORP. KOREA OFFICE
50F, KLI 63 Bldg., 60 Yoido-dong Youngdeungpo-Ku, Seoul, 150-763, KOREA Phone: +82-2-784-6027 FAX: +82-2-767-3677
SEIKO EPSON CORP. SEMICONDUCTOR OPERATIONS DIVISION
IC Sales Dept. IC International Sales Group
421-8, Hino, Hino-shi, Tokyo 191-8501, JAPAN Phone: +81-42-587-5814 FAX: +81-42-587-5117
Document Code: X83A-G-001-01
Issued 2009/01/20
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