Epson S1V30120 User Manual

Page 1
S1V30120 Evaluation Board
User Guide
Rev.2.0
Page 2
NOTICE
No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no representation that this material is applicable to products requiring high level reliability, such as, medical products. Moreover, no license to any intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright infringement of a third party. This material or portions thereof may contain technology or the subject relating to strategic products under the control of the Foreign Exchange and Foreign Trade Law of Japan and may require an export license from the Ministry of Economy, Trade and Industry or other approval from another government agency.
All other product names mentioned herein are trademarks and/or registered trademarks of their respective companies.
©SEIKO EPSON CORPORATION 2007, All rights reserved.
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Table of Contents
1. Introduction....................................................................................................................................... 1
1.1 Scope ......................................................................................................................................... 1
1.2 Document Structure.................................................................................................................... 1
2. System Overview .............................................................................................................................. 2
2.1 System Block Diagram ............................................................................................................... 2
2.2 System Interfaces....................................................................................................................... 3
3. Configuration Options...................................................................................................................... 4
3.1 Configuration Switches............................................................................................................... 4
4. Detailed Interface Descriptions ....................................................................................................... 5
4.1 Power Supply ............................................................................................................................. 5
4.2 Clocks......................................................................................................................................... 5
4.3 Reset .......................................................................................................................................... 5
4.4 SPI Interfaces ............................................................................................................................. 5
4.5 GPIO Buttons ............................................................................................................................. 6
4.6 JTAG........................................................................................................................................... 7
S1V30120 Evaluation Board (FIRECREST) User Guide (Rev 2.0)
EPSON i
Page 4

1. Introduction

1.1 Scope

FIRECREST is the customer evaluation board for the S1V30120 Speech Synthesis IC.
The FIRECREST board provides the necessary clocking, power, configuration and interfaces to
allow evaluation of the S1V30120. It is designed to be used as a daughterboard to the S1V30100
Evaluation Board Nightingale, which provides a USB interface to a PC.
This user manual describes the FIRECREST board in detail.

1.2 Document Structure

The User Guide is structured as follows. Section 2 gives an overview of the FIRECREST board and
the major components and interfaces. Section 3 describes the board configuration options available
on FIRECREST. Section 4 describes each system component and interface in detail.
1. Introduction
S1V30120 Evaluation Board (FIRECREST) EPSON 1 User Guide (Rev 2.0)
Page 5

2. System Overview

A
2. System Overview
FIRECREST provides the required clocks, power, configuration and interface connectors to allow evaluation
of the S1V30120 Silicon.
This section gives an overview of the main blocks and interfaces in the system. Section 2.1 provides an
overview of the major blocks on the FIRECREST board. Section 2.2 summarizes the main interfaces on
FIRECREST.

2.1 System Block Diagram

Figure 1 is a block diagram of the FIRECREST board that illustrates the main system components.
The clocking and system configuration options are also shown on the left-side of the figure.
FIRECREST implements a number of amplifier circuits for converting the S1V30120 headphone
output to a speaker output. Consult the BOM that is delivered with the evaluation kit for details of the
fitted components
SPI M
Power via J5
Oscillator
Regulators
SPI S
Config
S1V30120
GPIO
JTAG
32.768kHz
Reset
3.3V / 1.8V
Switches
Figure 1 FIRECREST Block Diagram
mplifier
Speaker Out
2 EPSON S1V30120 Evaluation Board (FIRECREST)
User Guide (Rev 2.0)
Page 6

2.2 System Interfaces

FIRECREST has a large number of connectors to support all the interfaces available on the
S1V30120. These are summarized below in Table 1. A full description of these interfaces can be
found in Section 4.
Interface Connector Notes
Motherboard Interface J5 Power / Reset / Control Lines
SPI Slave J4 SPI Slave
GPIO A J1 GPIO
JTAG J2 JTAG interface
Dummy NC J6 Dummy connector used for stability in stacking
Speaker Out J3 Speaker Out Jack
2. System Overview
Table 1 Interface Connector Summary
the board with the S1V30100
S1V30120 Evaluation Board (FIRECREST) EPSON 3 User Guide (Rev 2.0)
Page 7

3. Configuration Options

3. Configuration Options
FIRECREST has a number of configuration options. Some options are selected using configuration switches
on the board.

3.1 Configuration Switches

FIRECREST has a DIP switch (SW5) for controlling configuration options. The table below
describes the function of each of this configuration switch, together with its default position.
Table 2 FIRECREST Configuration Switch Summary
Switch Position Default Description
SW5-1[GPIOA0] Open Reserved Closed *** Enter S1V30120 Bootstrap Downloader on Reset.
SW5-2[GPIOA1] Open Closed ***
SW5-3[GPIOA2] Open *** Closed
SW5-4 Open *** Closed
SW5-5 Open *** Closed
SW5-6 Open Closed ***
GPIOA2:A1 select bootstrap option.
Defined values are: 0x00: Reserved 0x01: Boot from SPI interface (slave mode) 0x02: Reserved 0X03: Reserved
GPIOA3: Reserved
GPIOA5: Reserved
UNUSED
4 EPSON S1V30120 Evaluation Board (FIRECREST)
User Guide (Rev 2.0)
Page 8

4. Detailed Interface Descriptions

4.1 Power Supply

FIRECREST receives power from the J5 Connector when connected to the NIGHTINGALE board.
Two yellow LEDs are fitted which indicate whether power is being supplied to the 3.3V and 1.8V –
these are marked as 3.3V (LED1) and 1.8V (LED2) respectively on the board.

4.2 Clocks

FIRECREST requires only a single external clock of 32.768kHz for operation. The clock oscillator
Y1 on the board supplies this signal.

4.3 Reset

Switch SW7 allows the FIRECREST board to be reset. The reset is commoned with SYS_RESET on
the NIGHTINGALE board.
4. Detailed Interface Descriptions

4.4 SPI Interfaces

The S1V30120 has a single SPI Slave Interface. Table 3 shows the pin-out of the SPI Test Connector.
The SPI Slave Interface uses the signals SIN, SOUT, SCLK, SFRM1 for serial data in, serial data out,
serial clock, and slave select respectively.
The SPI test-connectors uses a 6-pin AMP MicroMatch Test connector.
Table 3 SPI Slave Test Connector
J4 – SPI Slave
Pin SPI S Signal
1 GND
2 SOUT
3 SCLK
4 SIN
5 SFRM1
6 GND
S1V30120 Evaluation Board (FIRECREST) EPSON 5 User Guide (Rev 2.0)
Page 9
4. Detailed Interface Descriptions

4.5 GPIO Buttons

The S1V30120 firmware uses two GPIOs to communicate information to/from the host processor to
control STANDBY mode and indicate the availability of a message to be received from the
S1V30120. These can be controlled/observed on the FIRECREST board as shown in Table 4.
Table 4 GPIO Button Functions
Name GPIO Port Description
SW1 Port A Bit 9
SW2 Port A Bit 8
SW3 Port A Bit 7
SW4 Port A Bit 6
SW6 Port A Bit 4 STANDBY_EXIT
SW8 Port A Bit 10
SW9 Port A Bit 11
All the GPIO Port A signals of S1V30120 can be accessed via the 10-pin AMP MicroMatch test
connector (J1). Connector J1 is given below in Table 5.
Table 5 GPIO Connector Mapping
J1 – GPIO PORT A
Pin GPIO A Signal
1 GND
2 GPIOA5
3 GPIOA6
4 GPIOA7
5 GPIOA8
6 GPIOA9
7 GPIOA10
8 GPIOA11
9 SFRM2
10 GND
6 EPSON S1V30120 Evaluation Board (FIRECREST)
User Guide (Rev 2.0)
Page 10

4.6 JTAG

The JTAG Interface provides access to the ARM Processor on the S1V30120.
Table 6 shows the pin-out of the JTAG connector. This is the standard pin-out used for connection to
the ARM Multi-ICE unit.
4. Detailed Interface Descriptions
Table 6 JTAG Connector Pin-out
J2– JTAG Connector
Pin Signal
1 HVDD
2 HVDD
3 NTRST
4 GND
5 TDI
6 GND
7 TMS
8 GND
9 TCK
10 GND
11 GND
12 GND
13 TDO
14 GND
15 SYSRESET
16 GND
17 NC
18 GND
19 NC
20 GND
S1V30120 Evaluation Board (FIRECREST) EPSON 7 User Guide (Rev 2.0)
Page 11
A
J1
LINE OUT/EARPHONE
4 2 3 1
NALOGUE
R37 0R
R35 0R
AGND
HVDD_BOARD
SW8
3 4
SW6
PLLSYSVD D
C46
100nF
PLLSYSGN D
LVDD
C39
100nF
C42
100nF
C44
100nF
C45
100nF
C38
100nF
C34
100nF
C43
100nF
C37
100nF
C40
100nF
C41
100nF
HVDD
C35
100nF
CLOCK
HVDD_BOARD
HVDD_BOARD
Y1
C12
RESET
100nF
SW4 NRESET
L2
22uH
IND_3613C
L1
22uH
IND_3613C
100uF
AGND
+
NJM386 R38 10R
C27
47nF
AGND
R39 0R
C28 220uF
C22 1uF
C25 1uF
R33 0R
AVDD_BOARD
9
OUT_P
7
OUT_N
8
+
C31
R40
15K
U2
754
C29
47uF
AGND
VDDO
C26 1uF
6
VSS#6
5V0
6
-
2
AGND
3
+
8 1
R36 680R
AGND
AGND
NJU8719
+
VDD
VSS#10
U3
IN
NC
MCK
STBYB
AVDD
R32 51K
C24 1uF
R31 51K
AGND
AGND
AVDD_BOAR D
1
10
2 3 4
5
C21
1nF
+
C23
C30
.1uF
10uF
C20
R51 0R
R30 10K
AGND
10nF
R25
GPIOA11
10R
AGND
R24 10R
R23 1K
C32
10nF
1
4
HVDD_BOARD
R20 47K
VIO
VDD
C14
22nF
32.768kH z
GND
OUT
2
3
SYSRE SET
CLKI
HVDD
LVDD
36
CLKI
8
HVDD#8
18
HVDD#18
28
HVDD#28
37
HVDD#37
49
HVDD#49
56
HVDD#56
64
HVDD#64
3
LVDD#3
11
LVDD#11
20
LVDD#20
24
LVDD#24
29
LVDD#29
39
LVDD#39
45
LVDD#45
50
LVDD#50
57
LVDD#57
62
NRESET
63
SCANEN
21
FDA1
22
FDA2
26
HPO
17
HPON
3 4
SW3
3 4
SW1
3 4
10K R26
10K R34
AVDD
6
AGND
27
VSS#6
16
25
AVSS
AVDD
VSS#16
VSS#23
23
32
PLLSYSGN D
35
PLLVSS
VSS#32
VSS#41
VSS#51
VSS#61
41
51
61
SW7
SW9
PLLSYSVD D
33
PLLVDD
EXCKM
38
1 2
1 2
1 2
1 2
VCP
34
GPIOA11
U1
S1V30120
TESTEN
TSTMODE042TSTMODE143TSTMODE2
40
GPIOA9
GPIOA10
44
GPIOA7
GPIOA8
2
GPIOA6
GPIOA947GPIOA8
GPIOA101GPIOA11
J5
1 2 3 4 5 6 7 8
amp_215464-08
J2
1 2 3 4 5 6 7 8 9
10
CON10
SOUT SCLK SIN SFRM1
R43
R42
100K
100K
TCK
1
J4
2 3
SPI S
4
AMP_0188275-06 5 6
R44
100K
1 2 3 4 5 6 7 8 9
J3
10 11
JTAG
12 13 14 15 16 17 18 19 20
NTRST
TDI
TMS
TDO
SYSR ESET
5V0 MSG_R EAD Y STANDBY _EXIT SYSRESET 5V0
GPIOA5 GPIOA6 GPIOA7 GPIOA8 GPIOA9 GPIOA10 GPIOA11 SFRM2
HVDD_BOARD
R41 100K
HVDD_BOARD
R47
R49
STANDBY _EXIT
R50
10K
10K
R45 0R
SW5
GPIOA0 GPIOA1 GPIOA2 GPIOA3MSG_R EAD Y
GPIOA5
SW DI P-6
HVDD_BOARD
STANDBY _EXIT
R14 0R
GPIOA4
46
48
60
55
58
GPIOA0
GPIOA152GPIOA253GPIOA354GPIOA4
SOUT SCLK
SFRM1 SFRM2
SPPDN SPHMT
NTRST
GPIOA5
9 4 5
SIN
7 10
31 30
15 14
TDI
13
TMS
12
TCK
19
TDO
GPIOA659GPIOA7
SW2
10K R12
SFRM2
R46
R48
2K2
5K
10K
POWER SUPPLY
LVDD
C7 1uF
PLLSYSVD D
C15 1uF
HVDD_BOARD
C8 1uF
HVDD
1
J6
2 3
DU MMY_N C
4
AMP_0188275-06
5
HVDD_BOARD
C16 1uF
U4
3.3V AVDD
+
14
5
15
AGND
COMP OUTPUT
COMP INPUT
SHUTDOWN
VIN
GND#11GND#8
8
R21
NERROR
220K
R22 1M
+
C47 22uF
C36 22uF
FEEDBACK
GND#99GND#16
16
R27 0R
ERROR
GND#1313AGND
7
VOUT
SENSE
VREF
VTAP
LP2960
PLLSYSGN D
AGND
12
6
2 3
4
11 10
NERROR
C17 100nF
avx tantd7343
C33 220uF
AGND
AVDD
R29
0R
C19 1uF
AGND
+
AVDD_BOARD
R28
0R
C18 1uF
AGND
FM5
Fiducial
FM4
Fiducial
FM1
1
1
1
1
1
Fiducial
FM3
1
Fiducial
HVDD_BOARD
C13
100nF
SCLK SOUT
8 7 6 5
Vcc RESET C D
M25PE10
U5
S
Q TSL Vss
EEPROM
FM6
1
1
Fiducial
FM2
Fiducial
1
1
MH2
1
MH1
FIX
MH3
1
1
1
FIX
1
FIX
MH4
1
FIX
HVDD_BOARD
R19 22K
1 2 3 4
SFRM2
SIN
SEIKO EPSON CORPORATION
FIRECREST PCB
S1V30120 Evaluation Board Reference Design
6
Rev.
2.0
R17
R3 220R
LED1 3V3
0R
R18 0R
R10
0R
R11
1V8
0R
R56 0R
PLLSYSGND
5V0
R16 220K
C11 100nF
HVDD
R8
120K
R7 100K
+
C51 22uF
NERROR
+
R6 1M
C49 22uF
14
5
15
14
5
15
U6
COMP OUTPUT
COMP INPUT
SHUTDOWN
VIN
GND#11GND#8
8
U9
1.8V LVDD
COMP OUTPUT
COMP INPUT
SHUTDOWN
VIN
GND#11GND#8
8
FEEDBACK
GND#99GND#16
16
FEEDBACK
GND#99GND#16
16
GND#1313AGND
GND#1313AGND
ERROR
7
ERROR
7
VOUT
SENSE
VREF
VTAP
LP2960
3.3V HVDD
VOUT
SENSE
VREF
VTAP
LP2960
NTRST
12
NERROR
6
2 3
4
C10
100nF
11 10
12
6
2 3
4
R1 47K
11 10
SYSRE SET
NERROR
100nF
R2 100K
R15 0R
+
C48 47uF
+
C1
C50 47uF
LED2 1V8
Page 12
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Document Code: 411302600
First Issue October 2007
Printed November 2007 in JAPAN
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