Page 1
Technical Manual
SCSI Interface Controller
S1R72104
MF1529-01
Page 2
NOTICE
No part of this material may be reproduced or duplicated in any form or by any means without the written
permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice.
Seiko Epson does not assume any liability of any kind arising out of any inaccuracies contained in this material
or due to its application or use in any product or circuit and, further, there is no representation that this material
is applicable to products requiring high level reliability, such as, medical products. Moreover, no license to
any intellectual property rights is granted by implication or otherwise, and there is no representation or warranty
that anything made in accordance with this material will be free from any patent or copyright infringement of a
third party. This material or portions thereof may contain technology or the subject relating to strategic
products under the control of the Foreign Exchange and Foreign Trade Law of Japan and may require an export
license from the Ministry of International Trade and Industry or other approval from anther government agency.
©SEIKO EPSON CORPORATION 2002, All rights reserved.
All other product names mentioned herein are trademarks and/or registered trademarks of their respective
companies.
Page 3
Configuration of product number
DEVICES
S1 R 72104 F 00B0 00
Packing specifications
00: Besides tape & reel
0A: TCP BL 2 directions
0B: Tape & reel Back
0C: TCP BR 2 directions
0D: TCP BT 2 directions
0E: TCP BD 2 directions
0F: Tape & reel FRONT
0G: TCP BT 4 directions
0H: TCP BD 4 directions
0J: TCP SL 2 directions
0K: TCP SR 2 directions
0L: Tape & reel LEFT
0M: TCP ST 2 directions
0N: TCP SD 2 directions
0P: TCP ST 4 directions
0Q: TCP SD 4 directions
0R: Tape & reel RIGHT
99: Specs not fixed
Specifications
Shape
(F : QFP)
Model number
Model name
(R : Exclusive use controller, Peripheral)
Product classification
(S1:Semiconductors)
Page 4
Rev.1.1 EPSON
i
CONTENTS
1. DESCRIPTION....................................................................................................................................1
2. FEATURES .........................................................................................................................................1
3. BLOCK DIAGRAM .............................................................................................................................2
4. PIN ASSIGNMENT .............................................................................................................................3
5. PIN DESCRIPTION.............................................................................................................................4
6. FUNCTIONAL DESCRIPTION...........................................................................................................6
6.1 CPU Interface Circuit..................................................................................................................6
6.2 Internal Registers........................................................................................................................6
6.3 Port Interface Circuit...................................................................................................................6
6.4 DMA Control Circuit....................................................................................................................6
6.5 SCSI-2 Interface Circuit..............................................................................................................6
6.6 PLL Circuit (Internal System Clock Generating Section)...........................................................7
7. FUNCTION OF REGISTERS..............................................................................................................8
7.1 List of Registers..........................................................................................................................8
7.2 List of Registers/Bits...................................................................................................................9
7.3 Detailed Description of Each Register......................................................................................10
7.3.1 Main Interrupt Status (MAININT) R/W.......................................................................10
7.3.2 SCSI Interrupt Status 1 (SCSIINT1) R/W..................................................................11
7.3.3 SCSI Interrupt Status 2 (SCSIINT2) R/W..................................................................12
7.3.4 Reset (RESET) W......................................................................................................12
7.3.5 SCSI Mode Select0 (SCSIMODE0) R/W ..................................................................13
7.3.6 SCSI Mode Select1 (SCSIMODE1) R/W ..................................................................14
7.3.7 SCSI Control (SCSICTL) R/W...................................................................................14
7.3.8 SCSI Data (SCSIDATA) R/W.....................................................................................15
7.3.9 Synchronize Transfer Mode (SYNCMODE) R/W......................................................15
7.3.10 SCSI Own ID (OWNID) R/W ...................................................................................16
7.3.11 Source/Destination ID (SDID) R/W..........................................................................16
7.3.12 Selection Timeout Counter (SLTIME) R/W..............................................................16
7.3.13 FIFO Control (FIFOCTL) R/W .................................................................................16
7.3.14 FIFO Data (FIFODATA) R/W...................................................................................17
7.3.15 Non DMA Transfer Size (NDMASIZ) R/W...............................................................17
7.3.16 SCSI Command (COMMAND) R/W........................................................................17
7.3.17 DMA Control (DMACTL) R/W..................................................................................17
7.3.18 DMA Transfer Byte Count 2 (DTBC2) R/W.............................................................17
7.3.19 DMA Transfer Byte Count 1 (DTBC1) R/W.............................................................17
7.3.20 DMA Transfer Byte Count 0 (DTBC0) R/W.............................................................18
7.3.21 CONFIG0 (CONFIG0) R/W .....................................................................................18
7.3.22 CONFIG1 (CONFIG1) R/W .....................................................................................19
7.3.23 Test (TEST) R(/W)...................................................................................................20
7.3.24 Revision Reg. (REVISION) R ..................................................................................20
7.4 SCSI Control Commands .........................................................................................................20
7.4.1 Control Commands and Command Codes..................................................................20
7.4.2 Description of Each Control Command........................................................................21
7.4.3 Command Execution and State Transition ..................................................................28
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Rev.1.1
7.5 Others and Cautions about Operation .....................................................................................29
8. ELECTRICAL CHARACTERISTICS................................................................................................30
8.1 Absolute Maximum Ratings......................................................................................................30
8.2 Recommended operational conditions.....................................................................................30
8.3 DC Characteristics....................................................................................................................30
8.4 AC Characteristics....................................................................................................................33
8.4.1 CPU Interface...............................................................................................................34
8.4.2 SCSI Interface..............................................................................................................36
8.4.3 Port Interface ................................................................................................................49
8.4.4 Others...........................................................................................................................53
9. EXAMPLES OF CONNECTION.......................................................................................................56
10. EXTERNAL DIMENSIONS DRAWING ..........................................................................................57
Page 6
S1R72104 Technical Manual
Rev.1.1 EPSON
1
1. DESCRIPTION
S1R72104 is a SCSI interface control IC compatible with SCAM and FAST20 transfer.
2. FEATURES
«CPU Interface»
Connectable to a general-purpose CPU
«SCSI Interface»
Compatible with SCSI-2 (10Mbps (synchronous), 5Mbps (asynchronous))
Compatible with SCSI-3 FAST20 (20Mbps (synchronous))
Compatible with SCAM Lv.1 (compatible with Lv.2 with firmware)
Automatic processing of phase control
Built-in single end driver
Active negation I/O mounted
«PORT Interface»
Connectable directly to an IDE (ATA) DMA port.
Operational also as a general-purpose port.
«Others»
Built-in oscillation circuit: 20MHz/22.5MHz/40MHz
Built-in PLL circuit
100 pin QFP (0.5 mm pitch)
Supply voltage: 5.0V±10% and 3.3V±0.3V
No anti-radiation design
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S1R72104 Technical Manual
2 EPSON
Rev.1.1
3. BLOCK DIAGRAM
Port interface section
Master mode control
Slave mode control
Bus control
Clock control
section
SCSI-2(3) interface section
XPDREQ
XPDACK
CLKO
2 Multiplying PLL
PD15-0
XPRD
XPWR
Sequence
control
Command
analysis and
execution
Phase
control
Parity
GEN/CHK
FIFO
(16Byte)
DMA control
FIFO control
Asynchro-
nous transfer
control
Synchronous
transfer
SCAM
control
XSRST
XSATN
XSDP
XSBSY
XSIO
XSCD
XSMSG
XSSEL
XSDB7-0
XSREQ
XSACK
Clock distribution
CPU interface
section
Timing control
Interrupt control
Data MPX
DMA control
section
Start-up/stop control
Internal
register
CLKI
XPLLPW
V
C
AD4-0
DB7-0
XCS
XRD
XWR
XINT
XRESET
TEST
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S1R72104 Technical Manual
Rev.1.1 EPSON
3
4. PIN ASSIGNMENT
S1R72104F00B (QFP15-100pin)
VSSNC
XSBSY
HVDDXSACK
VSSXSRST
XSMSG
VSSXSSEL
XSCD
VSSXSREQ
HVDDXSIO
VSSPD7
PD8
PD6
PD9
PD5
PD10
PD4
PD11
LV
DD
75747372717069686766656463626160595857565554535251
HV
DD
76 50
V
SS
XSATN
77 49
PD3
V
SS
78 48
PD12
XSDBP
79 47
PD2
HV
DD
80 46
PD13
XSDB7
81 45
HV
DD
V
SS
82 44
PD1
NC
83 43
PD14
XSDB6
84 42
PD0
HV
DD
85 41
PD15
XSDB5
86 40
PDREQ
V
SS
87 39
XPWR
XSDB4
88 38
XPRD
HV
DD
89 37
XPDACK
XSDB3
90 36
V
SS
V
SS
91 35
XCS
XSDB2
92 34
XINT
NC
93 33
XRESET
HV
DD
94 32
XRD
XSDB1
95 31
XWR
V
SS
96 30
AD4
XSDB0
97 29
AD3
HV
DD
98 28
AD2
NC
99 27
AD1
V
SS
100 26
LV
DD
123456789
101112131415161718192021222324
25
LV
DD
EXCLK
V
SS
OSCIN
OSCOUT
LV
DD
CLKSEL0
CLKSEL1
V
C
XPLLPD
PLLCT0
PLLCT1
TESTMON
TESTEN
DB0
DB1
DB2
DB3
HV
DD
DB4
DB5
DB6
DB7
AD0
V
SS
INDEX
EPSO
TOP View
INDEX
S1R72104
EPSO
TOP View
INDEX
EPSO
TOP View
INDEX
EPSON
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S1R72104 Technical Manual
4 EPSON
Rev.1.1
5. PIN DESCRIPTION
The control signal with “X” at the head of a pin name is LOW-active.
Pin No. Symbol I/O Functional description Remarks
SCSI interface-related matters (18)
97 XSDB0 Is/Otr SCSI data signal (SD0 to SD7) Drive capability 48mA
95 XSDB1
92 XSDB2
90 XSDB3
88 XSDB4
86 XSDB5
84 XSDB6
81 XSDB7
79 XSDBP SCSI data parity signal Drive capability 48mA
77 XSATN I/Ood SCSI ATN signal Drive capability 48mA
73 XSBSY I/Ood SCSI BSY signal Drive capability 48mA
71 XSACK Is/Otr SCSI ACK signal Drive capability 48mA
69 XSRST I/Ood SCSI RST signal Drive capability 48mA
68 XSMSG I/Ood SCSI MSG signal Drive capability 48mA
66 XSSEL I/Ood SCSI SEL signal Drive capability 48mA
65 XSCD I/Ood SCSI C/D signal Drive capability 48mA
63 XSREQ Is/Otr SCSI REQ signal Drive capability 48mA
61 XSIO I/Ood SCSI I/O signal Drive capability 48mA
Port interface-related matters (20)
38 XPRD Is/O Port lead signal Drive capability 3mA
39 XPWR Is/O Port right signal Drive capability 3mA
40 PDREQ Is/O Port DMA request signal (also operable in negative logic) Drive capability 6mA
37 XPDACK Is/O Port DMA ACK signal Drive capability 3mA
42 PD0 I/O Port DMA data bus signal (PD0 to 15) Drive capability 3mA
44 PD1
47 PD2
49 PD3
53 PD4
55 PD5
57 PD6
59 PD7
58 PD8
56 PD9
54 PD10
52 PD11
48 PD12
46 PD13
43 PD14
41 PD15
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S1R72104 Technical Manual
Rev.1.1 EPSON
5
Pin No. Symbol I/O Functional description Remarks
CPU interface-related matters (17)
24 AD0 Ipu Address input pin (AD0 to AD4)
27 AD1
28 AD2
29 AD3
30 AD4
15 DB0 Ipu/O Data pin (DB0 to DB7) Drive capability 3mA
16 DB1
17 DB2
18 DB3
20 DB4
21 DB5
22 DB6
23 DB7
35 XCS Ispu Chip select signal for accessing internal register
34 XINT Otr Interrupt request output signal Drive capability 6mA
32 XRD Ispu Data lead signal
31 XWR Ispu Data write signal
Others (17)
4 OSCIN I Input to built-in oscillation circuit (40MHz, 20MHz or
22.5MHz)
5 OSCOUT O Output from built-in oscillation circuit
13 TESTMON O Monitor output for testing (open “LOW” output usually) Drive capability 2mA
33 XRESET Ipu System reset input signal
14 TESTEN Ipd Pin for testing (connected to LOW (GND) usually)
7 CLKSEL0 I Input clock selection: LOW(GND): OSCIN / HIGH(LVDD):
EXCLK input
8 CLKSEL1 I System clock selection: LOW(GND): PLL output /
HIGH(LV
DD
): Selecting signal of CLKSEL0
11 PLLCT0 I Dependent on PLL operation control pin input clock; input
on 3.3V level
12 PLLCT1 I Dependent on PLL operation control pin input clock; input
on 3.3V level
2 EXCLK I 5V level external clock input pin (connected to LOW (GND)
when not used)
10 XPLLPD I PLL power-down pin
LOW (GND): PLL Power-down mode / HIGH (LV
DD
): PLL
operation
9 VC O Internal VCO control pin
74,83,
93,99
NC
-
Not connected to IC chips (open usually)
HVDD:5V (5)
19,45,62,
72,76,80,
85,89,94,
98
HV
DD
P Power supply for 5V interface
LVDD:3.3V (6)
1,6,26,51 LVDD P Power supply for internal operation
VSS:0V (17)
3,25,36,
50,60,64,
67,70,75,
78,82,87,
91,96,100
V
SS
P GND
Note : I : Input O : Output
Is : Schmitt input Ood : Open drain output
Ipu : Pull-up input Otr : Tristate output
Ispu : Pull-up Schmitt input Ipd : Pull-down input
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S1R72104 Technical Manual
6 EPSON
Rev.1.1
6. FUNCTIONAL DESCRIPTION
6.1 CPU Interface Circuit
This block can be interfaced to a general-purpose CPU. It controls the interface with the CPU generally.
If XCS signal from CPU is LOW, the block can access the internal register. It decodes the address bus AD4 to
AD0 to generate the address of the internal register. At this time, it generates the read/write strobe signal from
XRD/XWR signal, transferring data between the internal register. A wait signal to CPU is not generated
because of no-wait operation.
6.2 Internal Registers
Refer to the section of Register Functions as for the addresses of the internal registers and description of each
bit. The main functions of this block are as follows:
(1) It generates control signals to each block according to the address, write-data and write-strobe signals
generated by the CPU interface circuit.
(2) It stores the status signals from each block, and outputs data according to the address and read-strobe
signals sent from the CPU interface circuit.
6.3 Port Interface Circuit
This is a block controlling the transfer to and from the external DMA port. It has the following functions:
(1) It controls the linkage operation of each functional block according to the control signal and the
stop-operation signal sent from the DMA control circuit.
(2) It control the transfer status of the external port according to PDREQ/XPDACK signals.
(3) It reads/writes the data of the data bus PD15-0 of the port from/to FIFO in SCSI-2 block. If the transfer
becomes impossible because of FIFO’s full/empty state, the block suspends transfer to and from the port
according to the timing specified by the PDREQ/XPDACK signals.
(4) The port allows selection of bit width 8 or 16.
(5) The port interface allows selection of the master or slave function (toward PDREQ/XPDACK/XPRD/XPWR
direction).
6.4 DMA Control Circuit
This is a block which controls the transfer between DMA port and FIFO in SCSI-2 block. It has the following
functions:
(1) It controls the linkage operation of each functional block according to the control signal from the internal
register and the information and stop-operation signals from each block.
(2) It stores the status of each of functional blocks when their linkage operation ends, reporting it to the
internal register at the specified timing.
6.5 SCSI-2 Interface Circuit
This is a block which controls the interfaces conforming to the SCSI-2 standard in general. It has the
following functions:
(1) It performs the SCSI protocol control automatically with hardware.
(2) It has 16-staged off-set counter to control the off-set and transfer rate during synchronous transfer.
(3) In the command phase, it distinguishes automatically the groups of commands received (in Target mode).
(4) It controls the automatic status/message transfer function. It supports the messages 00h/0Ah/0Bh (in
Target mode).
SCAM compatibility
Besides the traditional SCSI, this LSI has some additional functions compatible to SCAM (SCSI Configured
Auto Magnify) as listed below. .
These functions allow a device to operate as a SCAM Lv.1 drive.
(1) It monitors and recognizes SCAM selection and generates interruption.
(2) It responds to the selection response delay of 4ms or more, so it can distinguish SCAM selection from
ordinary selection.
(3) It can operate SCSI bus’s signal line directly because of its actual operation responding to SCAM selection
and sending/receiving data.
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S1R72104 Technical Manual
Rev.1.1 EPSON
7
6.6 PLL Circuit (Internal System Clock Generating Section)
This IC has the function to generate 40MHz required for the internal circuit from the clock generated by the
oscillation circuit or inputted from EXCK pin by using PLL circuit.
The block diagram around the oscillation section is shown below: Internal clock
• The IC allows to structure a oscillation circuit easily by connecting crystal vibrator, ceramic vibrator and
feedback resistance.
(As for the characteristics of the ceramic vibrator, please consult with us separately.)
• It allows oscillation of 20MHz/22.5MHz/40MHz by means of the oscillation circuit mentioned above.
• It allows inputting external clock of 5V level and 2.5MHz/20MHz/22.5MHz/40MHz from the EXCLK pin.
• It allows inputting external clock of 3.3V level and 2.5MHz/20MHz/22.5MHz/40MHz from the OSCIN
pin.
• No PLL circuit is used because the internal clock can get necessary clock if the oscillator section is
oscillated at 40MHz, or if 40MHz clock is input from EXCLK pin.
• If EXCLK pin is used, set OSCIN pin to “LOW”; if OSCIN pin is used, set EXCLK pin to “LOW”.
Make settings as shown below depending on the ways of use (1:LVDD , 0:VSS):
If oscillator circuit is used
If external clock of 3.3V level is
input from OSCIN pin
If external clock of 5V level is
input from EXCLK pin
Oscillation/
input clock
20MHz 22.5MHz 40MHz 2.5MHz 20MHz 22.5MHz 40MHz 2.5MHz 20MHz 22.5MHz 40MHz
CLKSEL0 0 0 0 0 0 0 0 1 1 1 1
XPLLPD 1 1 0 1 1 1 0 1 1 1 0
PLLCNT0 0 1 0 0 0 1 0 0 0 1 0
PLLCNT1 0 1 0 1 0 1 0 1 0 1 0
CLKSEL1 0 0 1 0 0 0 1 0 0 0 1
• PLL circuit specifications Ta=0 to 70°C LV
DD
=3.3V±0.3V
Item Specifications
Lock-up time Within 1ms after oscillation was stabilized
Jitter Within ±2ns
A
B Y
S
PLL
Internal clock
CLKSEL1
XPLLPD
PLLCNT0
PLLCNT1
V
C
6.8k
Ω
100pF
GND
CLKSEL0
OSCOUT
5pF
GND
A
B Y
S
5pF
GND
OSCIN
1M
Ω
EXCLK
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S1R72104 Technical Manual
8 EPSON
Rev.1.1
7. FUNCTION OF REGISTERS
7.1 List of Registers
Address Register name Abridged name
00h Main Interrupt Status MAININT
01h SCSI Interrupt Status 1 SCSIINT1
02h SCSI Interrupt Status 2 SCSIINT2
03h - Reserved -
-
04h - Reserved -
-
05h - Reserved -
-
06h - Reserved -
07h RESET RESET
08h - Reserved -
09h SCSI Mode0 SCSIMODE0
0Ah SCSI Mode1 SCSIMODE1
0Bh SCSI Control SCSICTL
0Ch SCSI DATA SCSIDATA
0Dh SCSI Synchronous data transfer Mode SYNCMODE
0Eh SCSI Own ID OWNID
0Fh SCSI Source/Destination ID SDID
10h SCSI Selection Timeout Counter SELTIME
11h SCSI FIFO Control FIFOCTL
12h SCSI FIFO Data FIFODATA
13h SCSI Non-DMA Transfer Size NDMASIZE
14h SCSI Command COMMAND
15h - Reserved -
16h - Reserved -
17h DMA Control DMACTL
18h - Reserved -
19h Host Transfer Byte Count2 HTBC2
1Ah Host Transfer Byte Count1 HTBC1
1Bh Host Transfer Byte Count0 HTBC0
1Ch Config0 CONFIG0
1Dh Config1 CONFIG1
1Eh Test TEST
1Fh Revision REVISION
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S1R72104 Technical Manual
Rev.1.1 EPSON
9
7.2 List of Registers/Bits
Address Type Register Name Default value Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
00h R/W MAININT 00h GOOD SABT EXEC SCSI1 SCSI2 - DTCMP ASCMP
01h R/W SCSIINT1 00h SPERR IDERR SELTO SATN BFREE ILPHS SCSEL WOATN
02h R/W SCSIINT2 00h - SRST OFERR UNDEF CMDER RESEL SEL LARBT
03h
- -
-
-
-
-
-
-
-
-
-
04h
-
-
-
-
-
-
-
-
-
-
-
05h
-
-
-
-
-
-
-
-
-
-
-
06h
-
-
-
-
-
-
-
-
-
-
-
07h W RESET
-
-
-
-
-
-
-
-
-
08h
-
-
-
-
-
-
-
-
-
-
-
09h R/W SCSIMODE0 80h SINTEN DTCD - ULTRAS AUTO1 AUTO2 AN_C AN_D
0Ah R/W SCSIMODE1 00h STPPE ATNPE STATN AUTO RINH SINH DACS SPCEN
0Bh R/W SCSICTL 00h ACK ATN SEL BSY REQ MSG I/O C/D
0Ch R/W SCSIDATA 00h DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0Dh R/W SYNCMODE 00h RATE3 RATE2 RATE1 RATE0 OFF3 OFF2 OFF1 OFF0
0Eh R/W OWNID 00h -
-
-
-
-
OID2 OID1 OID0
0Fh R/W SDID xxh - SID2 SID1 SID0 - DID2 DID1 DID0
10h R/W SELTIME 00h ST7 ST6 ST5 ST4 ST3 ST2 ST1 ST0
11h R/W FIFOCTL 01h -
-
-
-
-
FCLR FULL EMPTY
12h R/W FIFODATA xxh FD7 FD6 FD5 FD4 FD3 FD2 FD1 FD0
13h R/W NDMASIZE FFh NSZ7 NSZ6 NSZ5 NSZ4 NSZ3 NSZ2 NSZ1 NSZ0
14h R/W COMMAND 00h CMD7 CMD6 CMD5 CMD4 CMD3 CMD2 CMD1 CMD0
15h
-
-
-
-
-
-
-
-
-
-
-
16h
-
-
-
-
-
-
-
-
-
-
-
17h R/W DMACTL 00h -
-
-
-
-
-
FIFO DTGO
18h
-
-
-
-
-
-
-
-
-
-
-
19h R/W DTBC2 00h DBC23 DBC22 DBC21 DBC20 DBC19 DBC18 DBC17 DBC16
1Ah R/W DTBC1 00h DBC15 DBC14 DBC13 DBC12 DBC11 DBC10 DBC9 DBC8
1Bh R/W DTBC0 00h DBC7 DBC6 DBC5 DBC4 DBC3 DBC2 DBC1 DBC0
1Ch R/W CONFIG0 00h ACP INTLV PSLV - PRQLV SWAP ODS BUS8
1Dh R/W CONFIG1 00h NP3 NP2 NP1 NP0 AP3 AP2 AP1 AP0
1Eh R TEST 00h TM2 TM1 TM0 CKOUT - OFST SCBC DMBC
1Fh R REVISION 00h REV7 REV6 REV5 REV4 REV3 REV2 REV1 REV0
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S1R72104 Technical Manual
10 EPSON
Rev.1.1
7.3 Detailed Description of Each Register
7.3.1 Main Interrupt Status (MAININT) R/W
When the IC interrupted CPU, the CPU first reads this register for processing the interruption to get to know
which interrupt status register is the factor.
After reading this register, the CPU reads the interrupt status register corresponding to each bit to find out the
bit that is the source of interrupt, and processes the interruption appropriately. Then it writes the values read to
the interrupt status registers corresponding to each bit, then clearing the bits.
If GOOD, SABT, or DTCMP bit is the interrupt source, the CPU writes the value read to clear the bits. The
register has no need to clear directly any other bits.
7 6 5 4 3 2 1 0
GOOD SABT EXEC SCSI1 SCSI2
-
DTCMP ASCMP
00h
AUTO SEQUENCE COMPLETE
DMA TRANSFER COMPLETE
SCSI INTERRUPT STATUS 2
SCSI INTERRUPT STATUS 1
EXECUTING SCSI COMMAND
ABORTED SCSI COMMAND
SCSI COMMAND NORMAL COMPLETE
BIT7 SCSI COMMAND NORMAL COMPLETE
This bit becomes HIGH if a SCSI control command closed normally.
BIT6 ABORTED SCSI COMMAND
This bit becomes HIGH if a control command was forced to terminate by Abort command issued.
BIT5 EXECUTING SCSI COMMAND
This bit is HIGH while a SCSI control command is under execution. This bit is not a factor causing interrupt to the
CPU, so HIGH of this bit causes no interruption. It is used to monitor the execution of SCSI control command.
BIT4 SCSI INTERRUPT STATUS 1
This bit becomes HIGH if any interrupt factor about the SCSI interface is shown on SCSIINT1 register.
BIT3 SCSI INTERRUPT STATUS 2
This bit becomes HIGH if any interrupt factor about the SCSI interface is shown on SCSIINT2 register.
BIT1 DMA TRANSFER COMPLETE
This bit becomes HIGH when DMA data transfer activated by DMACTL register ends.
It becomes HIGH also when the transfer is forced to terminate by “0” written in DTGO bit of DMACTL register.
It becomes HIGH also if a command is aborted by Abort_SCSI command or if a command under execution is aborted
by ATN assertion after DTGO bit of DMACTL register was set because DMA terminates.
BIT0 AUTO SEQUENCE COMPLETE
This bit becomes HIGH when AUTO1 or AUTO2 bit of SCSIMODE0(09h) is set and the command processing
specified is over.
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S1R72104 Technical Manual
Rev.1.1 EPSON
11
7.3.2 SCSI Interrupt Status 1 (SCSIINT1) R/W
Shows the result of a SCSI control command executed.
The CPU can recognize the interrupt source by reading this register after receiving the interrupt signal. It
clears the bit by writing again the value read.
7 6 5 4 3 2 1 0
SPERR IDERR SELTO SATN BFREE ILPHS
SCSEL WOATN
01h
SELECTED WITHOUT ATTENTION
SCAM SELECTED
ILLEGAL PHASE CHANGE DETECTED
BUS FREE DETECTED
SCSI ATN ASSERTION DETECTED
SELECTION TIME OUT
ID ERROR DETECTED
SCSI DATA PARITY ERROR DETECTED
BIT7 SCSI DATA PARITY ERROR DETECTED
This bit becomes HIGH if a parity error was detected on SCSI data bus.
BIT6 ID ERROR DETECTED
This bit becomes HIGH if an error was detected about ID bit during the selection or reselection phase. The error
about ID bit shows that:
Only one ID bit is asserted. or,
Three or more ID bits are asserted.
BIT5 SELECTION TIME OUT
This bit becomes HIGH if time-out was detected during the selection or reselection phase.
BIT4 SCSI ATN ASSERTION DETECTED
This bit becomes HIGH if SCSI ATN was asserted. It is not set, though, in the sequence where SCSI ATN is asserted
usually, such as the message-out phase subsequent to selection.
BIT3 BUS FREE DETECTED
This bit becomes HIGH if SCSI control command detected the busfree phase during its execution.
BIT2 ILLEGAL PHASE CHANGE DETECTED
This bit becomes HIGH if a SCSI control command detected unexpected phase transition during its execution.
It is valid only in Initiator mode.
BIT1 SCAM SELECTED
This bit becomes HIGH if SCAM selection was responded to.
BIT0 SELECTED WITHOUT ATTENTION
This bit becomes HIGH if the selection which does not assert ATTENTION was responded to.
Even if this bit is set, a SCSI control command continues execution. If a command block remains received, though,
the first byte of SCSI-FIFO has the command code.
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7.3.3 SCSI Interrupt Status 2 (SCSIINT2) R/W
Shows the result of a SCSI control command executed.
The CPU can recognize the interrupt source by reading this register after receiving the interrupt signal. It
clears the bit by writing again the value read.
7 6 5 4 3 2 1 0
-
SRST OFERR UNDEF CMDER RESEL SEL LARBT
02h
LOST ARBITRATION
SELECTED
RESELECTED
COMMAND ERROR
UNDEFIND GROUP COMMAND
OFFSET ERROR IN SYNCHRONOUS TRANSFER
SCSI RST ASSERTION DETECTED
BIT7 RESERVED
BIT6 SCSI RST ASSERTION DETECTED
This bit becomes HIGH if SCSI RST was asserted.
BIT5 OFFSET ERROR IN SYNCHRONOUS TRANSFER
This bit becomes HIGH if an off-set error occurred during synchronous transfer. The off-set error means that the
off-set counter is not reset to “0” when transfer ends, or that the counter overflows/underflows.
BIT4 UNDEFIND GROUP COMMAND
This bit becomes HIGH if SCSI command other than group 0, 1, 2, or 5 was received.
BIT3 COMMAND ERROR
This bit becomes HIGH if an undefined SCSI control command was issued or a control command was issued during
execution of another command.
BIT2 RESELECTED
This bit becomes HIGH if any other device made re-selection during execution of a command other than the SCSI
control command which makes re-selection.
BIT1 SELECTED
This bit becomes HIGH if any other device made selection during execution of a command other than SCSI control
command which makes selection.
BIT0 LOST ARBITRATION
This bit becomes HIGH in the case of defeat in the arbitration phase. If this bit is HIGH and no other device made
selection or re-selection , the IC suspends the operation of the control commands.
7.3.4 Reset (RESET) W
Writing in this register initializes the inside of the circuit. Any value may be entered.
7 6 5 4 3 2 1 0
07h
MSB LSB
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7.3.5 SCSI Mode Select0 (SCSIMODE0) R/W
Makes the operational settings related to SCSI interface.
7 6 5 4 3 2 1 0
SINTEN DTCD
-
ULTRAS AUTO1 AUTO2 AN_C AN_D
09h
ACTIVE NEGATION DATA
ACTIVE NEGATION CONTROL
AUTO2 (s t atus message stop)
AUTO1 (auto status)
ULTRA SCSI
DTCMP DISABLE
SCSI INTERRUPT ENABLE
BIT7 SCSI INTERRUPT ENABLE
If this bit is HIGH, any SCSI interruption but DTCMP is enabled.
[ASCMP may occur if this bit is HIGH. If the IC is used in polling processing, make firmware ignore the ASCMP
interruption.]
BIT6 DTCMP DISABLE
If this bit is HIGH, DTCMP interrupt is disabled.
BIT5 RESERVED
BIT4 ULTRA SCSI
If this bit is HIGH, ULTRA-SCSI transfer is enabled. It is valid only when RATE bit of SYNCMODE register is set
to “0” or “1”.
BIT3 AUTO1 (auto status)
Executes automatically STS_MSG, Busfree, and Wait_SEL_CMD after DMA_DATA_IN/OUT command was
executed.
At the end of execution, ASCMP interrupt occurs. The bit is valid also in FIFO-DMA mode.*AUTO
BIT2 AUTO2 (status message stop)
Executes automatically STS_MSG after DMA_DATA_IN/OUT command was executed.
At the end of execution, ASCMP interrupt occurs. The bit setting is valid also in FIFO-DMA mode.
[When this bit is used, EXECbit is not turned OFF even if ASCMP occurs. Configure the firmware so that it ignores
the status of EXECbit.] *AUTO
*AUTO :
During the execution of AUTO1 or 2, AUTO bit of SCSIMODE1 register is deemed as “1”.
Also, EXEC bit is “1” during the execution of AUTO1 or 2. Because internal sequencer writes the command in
SCSI block for CPU, COMMAND register can read the command value then under execution.
DTCMP interrupt occurs irrespective of the settings of AUTO1or 2. Set DTCD (bit6) of this register to “Hi” to
disable such interruption.
BIT1 ACTIVE NEGATION CONTROL
HIGH of this bit enables the function of active negation of SCSI REQ/ACK signals.
BIT0 ACTIVE NEGATION DATA
HIGH of this bit enables the function of active negation of the SCSI data and parity signals.
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7.3.6 SCSI Mode Select1 (SCSIMODE1) R/W
Makes the operational settings related to SCSI interface.
7 6 5 4 3 2 1 0
STPPE ATNPE STATN AUTO RINH SINH
DIRECT SPCEN
0Ah
SCSI PARITY CHECK ENABLE
SCSI DIRECT ACCESS ENABLE
SELECTION INHIBIT
RESELECTION INHIBIT
AUTO SEND STATUS/MESSAGE
STOP BY ATN ASSERT
ATN ASSERT BY PARITY ERROR
STOP BY PARITY ERROR
BIT7 STOP BY PARITY ERROR
HIGH of this bit suspends a SCSI control command under execution if a parity error was detected on SCSI interface.
BIT6 ATN ASSERT BY PARITY ERROR
HIGH of this bit makes ATN asserted against a target device if a parity error was detected on SCSI interface. Any
setting of this bit is invalid if SCSI parity check is disabled.
This bit is valid only in Initiator mode.
BIT5 STOP BY ATN ASSERT
HIGH of this bit suspends a SCSI control command under execution if ATN asserted was detected.
This bit is valid only in Target mode.
BIT4 AUTO SEND STATUS/MESSAGE
HIGH of this bit puts SCSI control command “Status_Message” into Automatic Transmission mode. In this mode,
FLAG and LINK bits of SCSI command block which have been received are checked; Status 00h(GOOD) and
message 00h(COMMAND COMPLETE), status 10h(INTERMEDIATE GOOD) and message 0Ah(LINKED
COMMAND COMPLETE), and status 10h(INTERMEDIATE GOOD) and message 0Bh(LINKED COMMAND
COMPLETE WITH FLAG) are sent automatically if LINK bit is LOW, LINK bit is HIGH and FLAG bit is LOW, and
LINK and FLAG bits are both HIGH, respectively.
BIT3 RESELECTION INHIBIT
HIGH of this bit disables response to re-selection.
BIT2 SELECTION INHIBIT
HIGH of this bit disables response to selection.
BIT1 SCSI DIRECT ACCESS ENABLE
HIGH of this bit allows direct control of SCSI signal lines from CPU by using SCSI data register and SCSI control
register. Also, it is possible always to monitor the status of the signal lines irrespective of the status of this bit.
BIT0 SCSI PARITY CHECK ENABLE
HIGH of this bit causes parity check of SCSI data bus during the selection phase (when itself is selected) and when
data is input through SCSI.
7.3.7 SCSI Control (SCSICTL) R/W
This register is accessed when CPU controls SCSI signal lines directly.
For such direct control, DIRECT (bit 1) must be set in the mode setting register (0Ah).
The status of each signal is stored as “active HIGH”.
7 6 5 4 3 2 1 0
ACK ATN SEL BSY REQ MSG
I/O C/D
0Bh
SCSI C/D
SCSI I/O
SCSI MSG
SCSI REQ
SCSI BSY
SCSI SEL
SCSI ATN
SCSI ACK
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7.3.8 SCSI Data (SCSIDATA) R/W
The CPU accesses this register when it controls SCSI data bus directly. For such direct control, DIRECT (bit
1) must be set in the mode setting register (0Ah).
The status of each signal is stored as “active HIGH”. DIRECT setting does not decide whether parity bit is
output or not; it is output if it has been output before setting DIRECT, or it is not otherwise.
7 6 5 4 3 2 1 0
DB7
DB6 DB5 DB4 DB3 DB2 DB1 DB0
0Ch
MSB LSB
7.3.9 Synchronize Transfer Mode (SYNCMODE) R/W
Sets transfer rate and off-set for SCSI synchronous transfer.
7 6 5 4 3 2 1 0
RATE3 RATE2 RATE1 RATE0 OFF3 OFF2
OFF1 OFF0
0Dh
SYNCHRONOUS OFFSET
SYNCHRONOUS TRANSFER RATE
RATE3-0 ASSERT NEGATE PERIOD OFF3-0 OFFSET
0000 1T 1T 2T 0000 Asynchronous
0001 2T 1T 3T
Note 1
0001 1
0010 2T 2T 4T 0010 2
0011 3T 2T 5T 0011 3
0100 3T 3T 6T 0100 4
0101 4T 3T 7T 0101 5
0110 4T 4T 8T 0110 6
0111 5T 4T 9T 0111 7
1000 5T 5T 10T 1000 8
1001 6T 5T 11T 1001 9
1010 6T 6T 12T 1010 10
1011 7T 6T 13T 1011 11
1100 7T 7T 14T 1100 12
1101 8T 7T 15T 1101 13
1110 8T 8T 16T 1110 14
1111 9T 8T 17T 1111 15
Note) T has double the cycle of internal clock (40MHz).
Note 1) If ULTRA bit of SCSIMODE0 register is set, T has the same cycle as internal clock (40MHz) only if the value set for
RATE3 to 0 bit is 1 or less.
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7.3.10 SCSI Own ID (OWNID) R/W
Sets the SCSI-ID of this IC itself.
7 6 5 4 3 2 1 0
- -
-
-
-
OID2 OID2 OID0
0Eh
7.3.11 Source/Destination ID (SDID) R/W
Sets both the SCSI-ID of the selector side and the target SCSI-ID when selection is made.
7 6 5 4 3 2 1 0
-
SID2 SID1 SID0
-
DID2 DID1 DID0
0Fh
DESTINATION ID (R)
SOURCE ID (R/W)
In Initiator mode, sets the target SCSI-ID to be selected in DESTINATION ID.
When re-selection is received, the target SCSI-ID which made re-selection is set in SOURCE ID.
In Target mode, sets the initiator SCSI-ID to be re-selected in DESTINATION ID.
When selection is received, the initiator SCSI-ID which made selection is set in SOURCE ID.
7.3.12 Selection Timeout Counter (SLTIME) R/W
Sets time-out delay for selection and re-selection.
7 6 5 4 3 2 1 0
ST7
ST6 ST5 ST4 ST3
ST2 ST1 ST0
10h
The time-out delay value is calculated according to the following formula:
Delay value = count value × 215×T×2
Where, T is internal clock cycle (40MHz).
The IC acts as follows if it detected time-out:
Suspends to output ID bit.
Negates XSSEL 4000×T×2 (about 200µs) after such suspension, and outputs selection time-out interrupt.
No time-out is detected if “0” is set to this register.
7.3.13 FIFO Control (FIFOCTL) R/W
Used for clearing the data of SCSI-FIFO and for checking its status.
7 6 5 4 3 2 1 0
- -
-
- -
FCLR FULL EMPTY
11h
FIFO EMPTY
FIFO FULL
CLEAR FIFO
BIT7,6,5,4,3 RESERVED
BIT2 CLEAR FIFO
HIGH of this bit clears the data stored in SCSI-FIFO.
The bit returns to LOW automatically after such clearing.
BIT1 FULL
HIGH of this bit means that SCSI-FIFO is full. In such a condition, any data written in SCSI-FIFO is ignored.
BIT0 EMPTY
HIGH of this bit means that SCSI-FIFO is empty. In such a condition, any trial to read data from SCSI-FIFO results
in invalid data read out.
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7.3.14 FIFO Data (FIFODATA) R/W
This is a register to access SCSI-FIFO from CPU.
7 6 5 4 3 2 1 0
FD7
FD6 FD5 FD4 FD3
FD2 FD1 FD0
12h
7.3.15 Non DMA Transfer Size (NDMASIZ) R/W
Sets the bytes number of data transferred in Non-DMA mode (the message and command phases).
In Read mode, the register allows to read out the size of data yet to be transferred.
7 6 5 4 3 2 1 0
NSZ7
NSZ6 NSZ5 NSZ4 NSZ3 NSZ2 NSZ1 NSZ0
13h
7.3.16 SCSI Command (COMMAND) R/W
Sets SCSI control commands.
7 6 5 4 3 2 1 0
CMD7
CMD6 CMD5 CMD4 CMD3 CMD2 CMD1 CMD0
14h
Refer to [7.4 SCSI Control Commands] as for the details of each of them.
7.3.17 DMA Control (DMACTL) R/W
7 6 5 4 3 2 1 0
- -
-
- -
-
FIFO DTGO
17h
DMA TRANSFER GO
FIFO CONTROL
BIT7-2 RESERVED
BIT1 FIFO CONTROL
Setting this bit and DTGO to HIGH at the same time causes DMA transfer using FIFO, without using port interface.
CPU must write data in FIFO according to FULL/EMPTY status of FIFO. Alternately, it may first write data in FIFO
and set HIGH in this bit and DTGO, then make control with remaining data and FULL/EMPTY. Though, CPU may
not access FIFO reversely against the direction of transfer.
This bit is used together with SCSI command for DMA Data In/Out. Note that FIFO is cleared when SCSI phase is
switched to the data phase if DMA Data In/Out command was issued without setting this bit.
FIFO is not cleared if DMA Data In/Out command is issued after this bit was set. So it is possible that FIFO has data
written beforehand.
BIT0 DMA TRANSFER GO
Setting this bit to HIGH causes DMA transfer to start. Setting it to HIGH before entering the data phase is allowed,
too.
7.3.18 DMA Transf er Byte Count 2 (DTBC2) R/W
Sets the most significant byte of the byte-length (3 bytes) for DMA transfer.
Setting of DTBC2 to 0 allows the setting of the byte-length up to FFFFFFh.
7 6 5 4 3 2 1 0
DBC23
DBC22 DBC21 DBC20 DBC19 DBC18 DBC17 DBC16
19h
7.3.19 DMA Transf er Byte Count 1 (DTBC1) R/W
Sets the second byte of the byte-length (3 bytes) for DMA transfer.
7 6 5 4 3 2 1 0
DBC15
DBC14 DBC13 DBC12 DBC11 DBC10 DBC9 DBC8
1Ah
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7.3.20 DMA Transf er Byte Count 0 (DTBC0) R/W
Sets the least significant byte of the byte-length (3 bytes) for DMA transfer.
7 6 5 4 3 2 1 0
DBC7
DBC6 DBC5 DBC4 DBC3 DBC2 DBC1 DBC0
1Bh
7.3.21 CONFIG0 (CONFIG0) R/W
Sets the operation mode of the IC.
7 6 5 4 3 2 1 0
ACP INTLV PSLV
-
PRQLV SWAP ODS BUS8
1Ch
PORT INTERFACE 8 BIT BUS
ODD BYTE START
SWAP PORT INTERFACE BUS
PDREQ LEVEL
PORT SLAVE
INTERRUPT LEVEL
ACTIVATE PORT
BIT7 ACTIVATE PORT
After reset, the port interface is in All Pins Input mode. Setting this bit to HIGH activates the port.
BIT6 INTERRUPT LEVEL
Decides the level of the signal interrupting CPU.
0: Active LOW (Output to XINT is 0/Hi-Z)
1: Active HIGH (Output to XINT is 1/0)
BIT5 PORT SLAVE
Decides the operation mode of the port.
0: Master mode (PDREQ = input; XPDACK/XPRD/XPWR = output)
1: Slave mode (PDREQ = output; XPDACK/XPRD/XPWR = input)
BIT3 PDREQ LEVEL
Decides the operation mode of PDREQ signal.
0: Positive logic
1: Negative logic
BIT2 SWAP PORT INTERFACE BUS
Swaps the higher 8 bits with lower ones when the port interface is used with 16-bit width.
0: Lower 8 bits data is transferred first.
1: Higher 8 bits data is transferred first.
BIT1 ODD BYTE START
Setting this bit to HIGH causes the 8 bits data, which should be sent later because of the SWAP setting when the port
interface is used with 16-bit width, to be transferred first.
It is effective only for the first one byte.
BIT0 PORT INTERFACE 8 BIT BUS
Set this bit to HIGH to use the port interface with 8-bit width.
Only the lower 8 bits are valid. Connect the higher 8 bits to GND or HV
DD
externally.
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* Operational settings of the port interface
Shown below is a list of the operational settings made by the bit setting.
1) Switching master/slave of the port by PSLV bit
PDREQ XPDACK XPRD/XPWR Remarks
PSLV=0
(Master)
Input Output Output Data input during XPRD
Data output during XPWR
Setting of STB3 to 0 valid
XPRD/XPWR pulse width:
Assert≥40ns
Negate≥40ns
PSLV=1
(Slave)
Output Input Input Data output during XPRD
Data input during XPWR
Setting of STB3 to 0 invalid
XPRD/XPWR pulse width:
Assert≥30ns
Negate≥30ns
2) Switching operational modes by BUS8/SWAP/ODS bit
BUS8=0 SWAP=0
PD7 to 0 is transferred to and from SCSI block first.
If ODS = 1, PD7 to 0 is discarded when the first one word is transferred,
and only PD15 to 8 is transferred.
PD7 to 0 is used if the last data to be transferred is not a word but a byte.
SWAP=1
PD15 to 8 is transferred to and from SCSI block first.
If ODS = 1, PD15 to 8 is discarded when the first one word is transferred,
and only PD7 to 0 is transferred.
PD15 to 8 is used if the last data to be transferred is not a word but a byte.
BUS8=1 Only PD7-0 is used for transfer.
PD15 to 8 is used for Input mode (connect to GND).
7.3.22 CONFIG1 (CONFIG1) R/W
Sets the operational mode of the IC.
7 6 5 4 3 2 1 0
NP3
NP2 NP1 NP0 AP3
AP2 AP1 AP0
1Dh
BIT7 to 4 NP3 to 0
Sets the negate pulse width of XPRD/XPWR when the port operates in Master mode.
The width is the internal operation clock cycle (40MHz) multiplied by [(NP3 to 0)+2].
ex 0000: 2×25ns=50ns
0001: 3×25ns=75ns
BIT3 to 0 AP3 to 0
Sets the assert pulse width of XPRD/XPWR when the port operates in Master mode.
The width is the internal operation clock cycle (40MHz) multiplied by [(AP3 to 0)+2].
ex 0000: 2×25ns＝50ns
0001: 3×25ns＝75ns
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7.3.23 Test (TEST) R(/W)
Used for testing a LSI. Basically, writing in this register is prohibited.
CKOUTbit is valid, however, even when no test is done. If this bit is used, be sure to set all the other bits to
“0”.
Be cautious not to set “1” to bits other than CKOUTbit, because it will put the IC into Test mode, affecting on
the IC’s basic operation.
7 6 5 4 3 2 1 0
TM2 TM1 TM0 CKOUT
-
OFST SCBC DMBC
1Eh
CLK OUT
BIT4 CLK OUT
Setting HIGH to this bit causes the internal operation clock, 40MHz, output from TESTMON(Pin13) pin.
7.3.24 Revision Reg. (REVISION) R
Shows the revision No. of the IC.
7 6 5 4 3 2 1 0
REV7
REV6 REV5 REV4 REV3 REV2 REV1 REV0
1Fh
7.4 SCSI Control Commands
7.4.1 Control Commands and Command Codes
Code Command names Summary of commands
00h Reserved
01h Abort_SCSI SCSI Abort command
02h Reserved
03h
04h Assert_RST SCSI Bus Clear command
05h Busfree
06h Reserved
07h Assert_ATN
08h SEL_MSG_clear SCAM control commands
09h Select_WithoutATN
0Ah Select_WithATN_Command
0Bh SelectWithoutATN_Command
0Ch Wait_Selection_Command Connection system commands
0Dh Reselection
0Eh Wait_Reselection
0Fh Wait_SCAM_Selection_Command
10h Reserved
11h Negate_ACK
12h Command_Out
13h DMA_Data_Out
14h Non-DMA_Data_Out
15h DMA_Data_In Transfer system commands
16h Non-DMA_Data_In
17h Status_In
18h Message_In
19h Message_Out
1Ah Status_Message
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7.4.2 Description of Each Control Command
Abort_SCSI(01H)
Suspends a SCSI control command under execution. After suspension, this command sets SABT bit of
MAININT register and the status block, causing interruption. This command, if issued in a non-operational
condition, is ignored.
Assert_RST(04H)
Asserts SCSI RST signal (XSRST) for 768×T×2 (about 46µs), and then negates it.
This command releases all the signals it asserts, causing the busfree condition. The inside of the IC is not
initialized.
It sets SCSIINT1 SRST bit after negating RST signal, causing interruption.
If a SCSI control command is under execution, it is forced to terminate. Only RST bit is set, though.
If SCSI DMA command is under execution, status block is set.
Busfree(05H)
Executes busfree.
The command is valid only in Target mode. If issued in Initiator mode, it is ignored.
It is invalid if issued when other SCSI-type command is under execution, causing a command error and the
command error interruption.
Assert_ATN(07H)
Asserts SCSI ATN signal (XSATN).
The command is valid only in Initiator mode. If issued in Target mode, it is ignored.
Also, it is not asserted in the busfree condition, though no error occurs.
It causes no interruption after its execution.
Any other command under execution continues execution.
Negation of ATN occurs in any of the following cases:
When the last byte is ACK-negated after Message_Out command was issued.
If busfree was detected.
If Assert_RST command was executed.
If chip-reset was done.
SEL_MSG_clear(08H)
Negates SCSI SEL/MSG signal (XSSEL/XSMSG).
When SCAM-selection was made by Wait_SCAM_Selection_Command, SCAM protocol is processed in Direct
mode, with .SEL/MSG remaining asserted inside. This command is used to clear it. After issuing this
command, release Direct mode.
It causes no interruption after its execution.
Any other command under execution continues execution.
Select_WithoutATN(09H)
Executes selection without asserting SCSI ATN signal.
This command is valid in either disconnected or connected condition. It causes a command error if issued
when any other command is under execution.
After the command was issued, the IC acts as follows:
Waits until SCSI bus becomes busfree.
Enters arbitration after detecting busfree.
If it wins arbitration, it asserts XSSEL and ID bit to data bus, entering the selection phase.
It terminates selection and operation when its rival asserts XSBSY.
After that, it sets GOOD bit of MAININT register.
It causes interruption.
After that, the IC enters Initiator mode.
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Select_WithATN_Command(0AH)
Asserts SCSI ATN signal, executes selection, and then executes the message-out command phase.
This command is valid in either disconnected or connected condition. It causes a command error if issued
when any other command is under execution.
CPU sets the message byte number in NON-DMA data-size register before issuing this command.
Then, the CPU write message data in FIFO. After transferring the message, it sets the command byte number
in NON-DMA data-size register, writing the command data in FIFO.
The IC acts as follows:
Waits for busfree.
After detecting busfree, enters arbitration.
If it wins arbitration, it asserts XSSEL and ID bit, entering the selection phase. Asserts XSATN at this time.
After selection, it checks message-out at the timing when XSREQ is asserted, transferring messages in FIFO.
Negates XSATN after asserting XSREQ and before asserting XSACK at the last byte of the messages.
After transferring all the messages, it checks the command phase, detects data accumulated in FIFO, and
transfers the command data in FIFO according to the byte number set anew.
After that, it sets GOOD bit of MAININT register.
It causes interruption.
After that, the IC enters Initiator mode.
Caution: Be sure that data is written in FIFO after the number of bytes to be transferred was set.
Select_WithoutATN_Command(0BH)
Executes selection keeping SCSI ATN negated, and then executes the command phase.
This command is valid in either disconnected or connected condition. It causes a command error if issued
when any other command is under execution.
CPU issues this command after setting the command byte number in NON_DMA data-size register.
The command data is written in FIFO.
The IC acts as follows:
Waits for busfree.
Enters arbitration after detecting busfree.
If it wins arbitration, it asserts XSSEL and ID bit, entering the selection phase.
After selection, it checks the command phase at the timing when XSREQ is asserted, transferring command
data from FIFO.
After that, it sets GOOD bit of MAININT register.
It causes interruption.
After those steps are over, the IC enters Initiator mode.
Wait_Select_Command(0CH)
Waits for the selection phase, and executes the command phase after selection.
Valid only when it is not connected.
If issued in the connected condition, it sets SCSIINT2 and CMDER bits, causing interruption. If any other
command is under execution then, it continues execution.
If this command is issued, set STATN(bit5) of SCSIMODE register, and clear it when the command is over.
After the command was issued, the IC acts as follows:
1
Waits for selection phase.
2
If selected, checks XSATN. If it is not asserted, the IC acts as mentioned in 5.
If it is asserted, the IC sets the message-out phase, receiving a message.
3
If the message received is not "Identify", the IC acts as mentioned in 6. (CPU checks the message in FIFO
and responds to it.)
4
If XSATN remains asserted after 1-byte message ("Identify") was received, the IC ends its operation by
setting SATN bit of SCSIINT1 register and causing interruption.
If XSATN is negated,
5
The command phase is set to receive a command.
The IC distinguishes the command groups, deciding the number of bytes received automatically.
6
It sets GOOD bit of MAININT register, causing interruption.
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After the execution, the IC enters Initiator mode.
Reselect(0DH)
Executes the re-selection phase..
Valid only when it is not connected.
If issued in the connected condition, it sets SCSIINT2 and CMDER bits, causing interruption. If any other
command is under execution then, it continues execution.
The IC acts as follows:
Waits for busfree.
Enters arbitration after detecting busfree.
if it wins arbitration, it assets XSSEL, XSIO and ID bits, entering the re-selection phase.
After that, it sets GOOD bit of MAININT register.
It causes interruption.
After the execution, the IC enters Target mode.
Wait_Reselect(0EH)
Waits for the re-selection phase.
Valid only when it is not connected.
If issued in the connected condition, it sets SCSIINT2 and CMDER bits, causing interruption. If any other
command is under execution then, it continues execution.
The IC acts as follows:
Enters the condition waiting for re-selection.
After that, it sets GOOD bit of MAININT register.
It causes interruption.
After that, the IC enters Initiator mode.
Wait_SCAM_Selection_Command(0FH)
Waits for SCAM selection, and causes interruption after the selection is made.
Valid only when it is not connected.
If issued in the connected condition, it sets SCSIINT2 and CMDER bits, causing interruption. If any other
command is under execution then, it continues execution.
If this command is issued, set STATN (bit5) of SCSIMODE register, and clear it when the command is over.
After the command was issued, the IC acts as follows:
Waits for the SCAM/normal selection phase.
Does not respond to, but ignores, SCSI selection with the selection time-out delay less than 4ms.
Responds to SCAM selection, causing interruption.
If no SCAM selection occurs, the IC responds to the selection which continues for 4ms or longer, and acts like
Wait_Select_Command (0Ch) after that.
After that, the IC enters Target mode.
Negate_ACK(11H)
Clears ACK left asserted by the last message transfer in Initiator mode when the LSI stopped operation.
Command_Out(12H)
Executes SCSI command phase.
Valid only in the connected condition. It can be issued in either Target or Initiator mode.
If issued in the disconnected condition, it sets SCSIINT2 and CMDER bits, causing interruption.
In Target mode
The IC acts as follows:
Enters this command into FIFO after setting its command byte number in NON-DMA data-size register.
This control command does not distinguish command groups automatically. It is used when any group
command which has undefined command block length is received or other cases.
After that, it sets GOOD bit of MAININT register.
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It causes interruption.
CPU reads a command from FIFO
In Initiator mode
CPU issues this command after setting the command byte number in NON-DMA data-size register.
Then it writes the command data in FIFO.
The IC acts as follows:
Negates XSACK if it is asserted at the start of execution.
Transfers the command data in FIFO after checking the command phase at the timing of assertion of XSREQ.
Suspends REQ-ACK hand-shake until FIFO becomes full of data, if FIFO was empty.
After that, it sets GOOD bit of MAININT register.
It causes interruption.
If any other phase is found when the command phase is checked:
Sets ILPHS of SCSIINT1, causing interruption.
Caution: Be sure that data is written in FIFO after the number of bytes to be transferred was set.
DMA_Data_Out(13H)
Executes SCSI data-out phase.
Transfers data between port and SCSI usually.
Setting FIFO bit (DMACTL register: bit 1) causes the transfer between CPU and SCSI.
Valid only in the connected condition. It can be issued in either Target or Initiator mode.
If issued in the disconnected condition, it sets SCSIINT2 and CMDER bits, causing interruption.
In Target mode
Combination of this command issued and the AND condition of DTGO bit of DMACTL register starts DMA
transfer.
When transfer of the count value set in DTBC register is over, the command ends, GOOD and DTCMP bits of
MAININT register are set, and interruption is caused.
In Initiator mode
Negates XSACK if it is asserted at the start of execution.
After the data-out phase was checked at the timing of assertion of XSREQ, the AND condition of DTGO bit of
DMACTL register starts actual DMA transfer. When the transfer of the count value set in DTBC register is over,
the command ends, GOOD and DTCMP bits of MAININT register are set, and interruption is caused.
If any other phase is found when the data-out phase is checked, ILPHS of SCSIINT1 is set, and interruption is
caused.
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Non-DMA_Data_Out(14H)
Executes the data-out phase between SCSI and CPU interface.
Valid only in the connected condition. It can be issued in either Target or Initiator mode.
If issued in the disconnected condition, it sets SCSIINT2 and CMDER bits, causing interruption.
In Target mode
Setting data bytes to be transferred in NON-DMA data-size register issues this command.
CPU reads data from inside of FIFO by referring to FIFO status.
The IC acts as follows:
Enters data bytes set into FIFO after setting the data-out phase.
REQ-ACK hand-shake is suspended until FIFO has some space, if FIFO was full.
After that, it sets GOOD bit of MAININT register.
It causes interruption.
In Initiator mode
Setting number of bytes to be transferred in NON-DMA data-size register issues this command.
CPU writes data into FIFO referring to FIFO status.
The IC acts as follows:
Negates XSACK if it is asserted at the start of execution.
Transfers data bytes set from FIFO after checking the data-out phase at the timing when XSREQ is asserted.
Suspends REQ-ACK hand-shake until FIFO becomes full of data, if FIFO was empty
After that, it sets GOOD bit of MAININT register.
It causes interruption.
Caution: Be sure that data is written in FIFO after the number of bytes to be transferred was set.
* Non-DMA_Data_Out can be implemented by setting FIFObit to DMA_Data_Out mentioned above.
Non-DMA_Data_Out can be used only for asynchronous transfer. Se we recommend that the operations
mentioned above be implemented with the combination of DMA_Data_Out and FIFObit.
DMA_Data_In(15H)
Executes SCSI data-in phase.
Transfers data between port and SCSI usually.
Setting FIFO bit (DMACTL register: bit 1) causes the transfer between CPU and SCSI.
Valid only in the connected condition. It can be issued in either Target or Initiator mode.
If issued in the disconnected condition, it sets SCSIINT2 and CMDER bits, causing interruption.
In Target mode
Combination of this command issued and the AND condition of DTGO bit of DMACTL register starts DMA
transfer.
When transfer of the count value set in DTBC register is over, the command ends, GOOD and DTCMP bits of
MAININT register are set, and interruption is caused.
In Initiator mode
Negates XSACK if it is asserted at the start of execution.
After the data-out phase was checked at the timing of assertion of XSREQ, the AND condition of DTGO bit of
DMACTL register starts actual DMA transfer. When the transfer of the count value set in DTBC register is over,
the command ends, GOOD and DTCMP bits of MAININT register are set, and interruption is caused.
If any other phase is found when the data-in phase is checked:
Sets ILPHS of SCSIINT1, causing interruption.
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Non-DMA_Data_In(16H)
Executes the data-in phase between SCSI and CPU interface.
Valid only in the connected condition. It can be issued in either Target or Initiator mode.
If issued in the disconnected condition, it sets SCSIINT2 and CMDER bits, causing interruption.
In Target mode
Setting data bytes to be transferred in NON-DMA data-size register issues this command.
CPU writes data into FIFO by referring to FIFO status.
The IC acts as follows:
Outputs data bytes set from FIFO after setting the data-in phase.
Suspends REQ-ACK hand-shake until FIFO becomes full of data, if FIFO was empty.
After that, it sets GOOD bit of MAININT register.
It causes interruption.
Caution: Be sure that data is written in FIFO after the number of bytes to be transferred was set.
In Initiator mode
Setting data bytes to be transferred in NON-DMA data-size register issues this command.
CPU reads data from inside of FIFO by referring to FIFO status.
The IC acts as follows:
Negates XSACK if it is asserted at the start of execution.
Enters data into FIFO after checking the data-in phase at the timing of assertion of XSREQ.
Suspends REQ-ACK hand-shake until FIFO has some space, if FIFO was full.
If any other phase is found when the data-in phase is checked, the IC sets ILPHS of SCSIINT1, causing
interruption.
* Non-DMA_Data_In can be implemented by setting FIFObit to DMA_Data_In mentioned above.
Non-DMA_Data_In can be used only for asynchronous transfer. Se we recommend that the operations
mentioned above be implemented with the combination of DMA_Data_In and FIFObit.
Status_In(17H)
Executes the status phase.
Valid only in the connected condition. It can be issued in either Target or Initiator mode.
If issued in the disconnected condition, it sets SCSIINT2 and CMDER bits, causing interruption.
In Target mode
CPU issues this command after writing the status byte in SCSI FIFO.
The IC transfers the status in FIFO after setting the status phase.
After that,
It sets GOOD bit of MAININT register.
It causes interruption.
In Initiator mode
Negates XSACK if it is asserted at the start of execution.
Enters 1 byte of status into SCSI FIFO after checking the status phase at the first timing when XSREQ is
asserted.
After that, it sets GOOD bit of MAININT register.
It causes interruption.
CPU checks the interrupt status, and reads status byte from SCSI FIFO if termination is normal.
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Message_In (18H)
Executes the message-in phase.
Valid only in the connected condition. It can be issued in either Target or Initiator mode.
If it is issued in the disconnected condition,
It sets SCSIINT2 and CMDER bits, causing interruption.
In Target mode
CPU sets the message bytes to be sent in NON-DMA data-size register, and issues this command. It writes
messages to be transferred in FIFO.
The IC sets the message phase, and sends the data bytes set in FIFO.
It suspends REQ-ACK hand-shake until FIFO becomes full of data, if FIFO was empty.
After that,
It sets GOOD bit of MAININT register.
It causes interruption.
Caution: Be sure that data is written in FIFO after the number of bytes to be transferred was set.
In Initiator mode
CPU sets the message bytes to be received in NON-DMA data-size register before issuing this command.
The IC acts as follows:
Negates XSACK if it is asserted at the start of execution.
Enters the byte size of message set into FIFO after checking the message-in phase at the timing when REQ is
asserted. REQ-ACK hand-shake is suspended until FIFO has some space, if FIFO was full.
After that, it sets GOOD bit of MAININT register.
It causes interruption.
Usually, the size of message is unknown beforehand. So set “1” as the byte to be transferred when the
command is issued first, and then decide the number of bytes to be received after the second byte by checking
the message code received.
Message_Out(19H)
Executes the message-out phase..
Valid only in the connected condition. It can be issued in either Target or Initiator mode.
If issued in the disconnected condition, it sets SCSIINT2 and CMDER bits, causing interruption.
In Target mode
CPU sets the byte size of message to be received in NON-DMA data-size register before issuing this command.
After setting the message-out phase, the IC enters the byte size of message set into FIFO.
If FIFO becomes full, REQ-ACK hand-shake is suspended until CPU read out message from FIFO to make
some space in it.
After that, it sets GOOD bit of MAININT register.
It causes interruption.
Usually, the size of message is unknown beforehand. So set “1” as the byte to be transferred when the
command is issued first, and then decide the number of bytes to be received after the second byte by checking
the message code received.
In Initiator mode
CPU sets the byte size of message to be sent in NON-DMA data-size register before issuing this command.
CPU writes the message to be transferred in FIFO.
The IC acts as follows:
Asserts XSATN.
Negates XSACK if it is asserted at the start of execution.
Sends data in FIFO after checking the message phase at the timing when XSREQ is asserted.
Suspends REQ-ACK hand-shake until FIFO becomes full of data, if FIFO was empty.
Negates XSATN after sending the bytes to be transferred.
After that, it sets GOOD bit of MAININT register.
It causes interruption.
Caution: Be sure that data is written in FIFO after the number of bytes to be transferred was set.
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Status_Message(1AH)
Executes the message-in phase after executing the status phase.
Valid only in the connected condition. It can be issued in either Target or Initiator mode.
If issued in the disconnected condition, it sets SCSIINT2 and CMDER bits, causing interruption.
In Target mode
Writing the status message to be sent in FIFO issues this command.
It is allowed also to write the status message to be transferred in FIFO after issuing the command.
The IC acts as follows:
Sets the status phase, and transfer one status byte taken out of FIFO.
Sets the message-in phase, and transfer one message byte taken out of FIFO.
Suspends REQ-ACK hand-shake until FIFO becomes full of data, if FIFO was empty.
After that, it sets GOOD bit of MAININT register.
It causes interruption.
In Initiator mode
Issuing this command makes each one byte of status and message taken in FIFO.
CPU reads one status byte, then one message byte, from FIFO.
The IC acts as follows:
Negates XSACK if it is asserted at the start of execution.
Enters status into FIFO after checking the status phase at the timing of assertion of XSREQ.
After receiving status, it enters message into FIFO after checking the message-in phase at the timing of
assertion of XSREQ.
After that, it sets GOOD bit of MAININT register.
It causes interruption.
Note: The message length is fixed at one byte.
7.4.3 Command Execution and State Transition
The IC has the following three state transitions from the viewpoint of execution of SCSI-type commands:
Disconnected condition (D)
Connected condition in Initiator mode (I)
Connected condition in Target mode (T)
The state transition among those conditions are caused by specific commands, as shown in the figure below:
The transition from I to D is done implicitly except by Assert_RST command.
It means that there is no command which causes such transition explicitly. The disconnected condition is
assumed if busfree is found when a next connection-type command is issued, and the command is executed. If
busfree is not found, the disconnected condition is waited for, and the connection-related command is
suspended.
The connection-type command can be executed in the disconnected condition. It may be issued in such
condition.
If it is issued while SCSI control command is under execution, though, a command error will occur.
A transfer-type command can be executed in the connected condition. If it is issued in the disconnected
condition, a command error will occur.
Both connection- and transfer-type commands can be executed when the IC is in the condition where no SCSI
control command is under execution.
If they are issued while SCSI control command is under execution, a command error will occur.
WAIT_SCAM_SELECT_COMMAND
WAIT_SELECT_COMMAND
RESELECT
SELECT***
WAIT_RESELECT
D
T I
BUSFREE
ASSERT_RST
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7.5 Others and Cautions about Operation
Operation responding to the selection without SCSI-1 arbitration phase
The IC operates responding to the selection of only a target ID of SCSI-1 as mentioned below. Note that there
occurs no (automatic) transition to the message or command phase after selection, as in the usual cases after
Wait_selection command.
1
If only an ID is selected after Wait_select_cmd command was issued, IDERR interrupt occurs and the
command ends.
The inside is in the condition where connection is complete, though. So message_out/command_out and
other commands can be issued, as in the usual case the selection is made with an initiator/target ID.
(Except that message_out/command_out is not executed automatically.)
2
If an ID of 3 bits or more is selected, IDERR interrupt occurs. This distinguishes whether selection of 1
bit is completed or IDERR with an ID of 3 bits or more is selected.
If 1 bit is selected, IDERR and SEL interrupts occur. If ATN is not asserted here, WOATN interrupt
occurs, too.
* The firm is asked to check that SCSI-1 selection has occurred by observing SEL interrupt at the same timing
when IDERR interrupt occurs.
Also, issue message_out/command_out manually while observing the condition of WOATN interrupt,
because IDERR terminates Wait_selection command.
Parity error in SCSI data phase, or command stop operation by detection of ATN
Take note of the following points when port interface is used as slave:
If a setting has been made that a parity error or detection of ATN in SCSI data phase stops the operation of a
command (STATN/STPPE/SPCEN bit of SCSIMODE register), occurrence of such factor and subsequent
command stop cause negation of PDREQ being output to port interface at the internal timing of the IC.
Accordingly, use such setting after checking that it causes no problem in hand-shake on the LSI side connected
to the IC.
In such a case, no problem occurs in the internal sequence of the IC if XPDACK or XPRD/XPWR may come
from the port side. Though, data transfer to and from FIFO may be obstructed depending on timing.
(The data may not be written in or read from the FIFO.)
In such a case, the FIFO terminates in uncompleted manner, so it requires clearing before going to the status
phase.
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8. ELECTRICAL CHARACTERISTICS
8.1 Absolute Maximum Ratings
V
SS
= 0[V]
Item Symbol Ratings Unit
Supply voltage HV
DD
-0.3 to +6.0 V
LV
DD
-0.3 to +4.6 V
Input voltage HVIN -0.3 to HV
DD
+ 0.5 V
LVIN -0.3 to LV
DD
+ 0.5 V
Output voltage HV
OUT
-0.3 to HV
DD
+ 0.5 V
LV
OUT
-0.3 to LV
DD
+ 0.5 V
Output current/pins
(SCSI output pins)
I
OUT1
50 mA
Output current/pins
(Other than SCSI output pins)
I
OUT2
±30
mA
Storage temperature T
stg
-65 to +150
°C
8.2 Recommended operational conditions
V
SS
= 0[V]
Item Symbol Min. Typ. Max. Unit
Supply voltage
HV
DD
4.50 5.00 5.50 V
LVDD 3.00 3.30
3.60
Input voltage
HVIN V
SS
-
HVDD V
LVIN V
SS
-
LVDD V
Operating temperature
Topr 0 25
70
°C
Input signal rise time
Normal input
t
ri
-
-
50 ns
Input signal fall time
Normal input
t
fi
-
-
50 ns
Input signal rise time
Schmitt input
t
ri
-
-
5 ms
Input signal fall time
Schmitt input
t
fi
-
-
5 ms
8.3 DC Characteristics
(1) I/O characteristics in the DC condition (Ta = 0 to 70°C, VSS=0V)
Item Symbol Conditions Min. Typ. Max. Unit
Static current HI
DDS
HVDD=5.0V±10%
-
-
80 µA
LI
DDS
LVDD=3.3V±0.3V
-
-
220
Input leak current ILI HVDD=5.0V -1 - 1 µA
Input pins capacitance
C
I
f=1MHz
HV
DD
=0V
-
-
10 pF
Output pins capacitance
C
O
f=1MHz
HV
DD
=0V
-
-
10 pF
Input/output pins capacitance
C
IO
f=1MHz
HV
DD
=0V
-
-
10 pF
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(2) TTL input characteristics (Ta = 0 to70°C, VSS=0V)
Names of signals covered: AD0 to 4,DB0 to 7, PD0 to 15, EXCLK,
XSATN, XSBSY, XSRST, XSMSG, XSSEL, XSCD, XSIO
Item Symbol Conditions Min. Typ. Max. Unit
HIGH level
Input voltage
V
IH
HVDD=5.5V 2.0 -
-
V
LOW level
Input voltage
V
IL
2H HV
DD
=4.5V
-
-
0.8 V
(3) CMOS input characteristics (Ta = 0 to 70°C, V
SS
= 0V)
Names of signals covered: CLKSEL1 to 0, PLLCT1 to 0,XPLLPD, OSCIN
Item Symbol Conditions Min. Typ. Max. Unit
HIGH level
Input voltage
V
IH
IL LV
DD
=3.6V 1.9 -
-
V
LOW level
Input voltage
V
IL
IL LV
DD
=3.0V
-
-
0.8 V
(4) TTL Schmitt input characteristics (Ta = 0 to 70°C, V
SS
= 0V)
Names of signals covered: XSREQ,XSACK, XCS, XRD, XWR, XPRD,XPWR,XPDACK, PDREQ,
XRESET, TESTEN, XSDB0 to 7,XSDBP,
Item Symbol Conditions Min. Typ. Max. Unit
HIGH level trigger
Input voltage
V
T2+
HVDD=5.0V 1.2 - 2.4 V
LOW level trigger
Input voltage
V
T2-
HVDD=5.0V 0.6
-
1.8 V
Hysteresis voltage ∆VH HVDD=5.0V 0.1 -
-
V
(5) Pull-up/down input characteristics (Ta = 0 to 70°C, V
SS
= 0V)
Names of signals covered: AD0 to 4, DB0 to 7, XCS, XRD, XWR, XRESET,TESTEN
Item Symbol Conditions Min. Typ. Max. Unit
Pull-up resistance Rpu
V
I
=0V
HV
DD
=5.0V
50 100 200 kΩ
Pull-down resistance Rpd
V
I
= HVDD
HV
DD
=5.0V
50
100
200 kΩ
(6) Output characteristics (Ta = 0 to 70°C, V
SS
= 0V) (IOL = 2mA)
Names of signals covered: TESTMON
Item Symbol Conditions Min. Typ. Max. Unit
HIGH level
Output voltage
V
OH
LV
DD
=3.0V
I
OH
=-2mA
LV
DD
-0.4
-
-
V
LOW level
Output voltage
V
OL
LV
DD
=Min.
I
OL
=-2mA
-
-
0.4 V
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(7) Output characteristics (Ta = 0 to 70°C, VSS = 0V) (IOL = 3mA)
Names of signals covered: XPDACK, PD0 to 15, DB0 to 7, XPRD, XPWR
Item Symbol Conditions Min. Typ. Max. Unit
HIGH level
Output voltage
V
OH
HV
DD
=5.0V
I
OH
=-1.5mA
HV
DD
-0.4
-
-
V
LOW level
Output voltage
V
OL
HV
DD
=4.5V
I
OL
=3mA
-
-
0.4 V
(8) Output characteristics (Ta = 0 to 70°C, V
SS
= 0V) (IOL = 6mA)
Names of signals covered: XINT, PDREQ
Item Symbol Conditions Min. Typ. Max. Unit
HIGH level
Output voltage
V
OH
HV
DD
=5.0V
I
OH
=-3mA
HV
DD
-0.4
-
-
V
LOW level
Output voltage
V
OL
HV
DD
=4.5V
I
OL
=6mA
-
-
0.4 V
(9) Output characteristics (Ta = 0 to 70°C, V
SS
= 0V) (Open drain IOL = 48mA)
Names of signals covered: XSATN, XSBSY, XSRST, XSMSG, XSSEL, XSCD, XSIO
Item Symbol Conditions Min. Typ. Max. Unit
3-state
Leak current
I
OZ
HVDD=Max. -1 - 1 µA
LOW level
Output voltage
V
OL5
HV
DD
=Min.
I
OL
=48mA
-
-
0.4 V
(10) Output characteristics (Ta = 0 to 70°C, V
SS
= 0V) (IOL = 48mA)
Names of signals covered: XSDB0 to 7, XSDBP, XSREQ, XSACK
Item Symbol Conditions Min. Typ. Max. Unit
HIGH level
Output voltage
V
OH
HV
DD
=Min.
I
OH
=-20mA
1.5
-
-
V *1
LOW level
Output voltage
V
OL
HV
DD
=Min.
I
OL
=48mA
-
-
0.4 V
*1: VOH of the active negation cell meets Active negation Current vs. Voltage defined in American National
Standard X3T10/1071D for Information Systems - SCSI-3 Fast20.
(11) Power consumption (Ta = 0 to 70°C, V
SS
= 0V, HVDD = 5V, LVDD = 3.3V)
Item Symbol Conditions Typ. Max. Unit
HVDD system
Current consumption
I
opH
HVDD=5V±10% 10 25 mA
LVDD system
Current consumption
I
opL
LVDD=3.3V±10% 25 30 mA
Typ.: Only the register access from a CPU of Typ.: HVDD=5.0V, LVDD=3.3V
Max.: Fastest transfer (Fast20) and operation of port and SCSI at Max.: HV
DD
=5.5V, LVDD=3.6V
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8.4 AC Characteristics
Measurement conditions of AC characteristics:
Ta = 0 to 70 HV
DD
= 5V±10% LVDD = 3.3V±0.3V
V
SS
= 0V
DC level to decide input
0.8V to 2.4V
Operating clock
f
oscin
= 40MHz
Loading conditions of output pins except SCSI pins
Drives load capacitance of 50pF and 1TTL.
Load capacitance of SCSI pins
Load capacitance = 100pF, pull-up resistance = 110Ω/pull-down resistance = 165Ω
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8.4.1 CPU Interface
8.4.1.1 Register Read Timing
Symbol Specification Min. Typ. Max. Unit
T
101
XCS fall → XRD fall
AD[4:0] valid → XRD fall
0
-
-
ns
T
102
XRD rise → AD[4:0] invalid
XRD rise → XCS rise
0
-
-
ns
T
103
XRD LOW level pulse width 60
-
-
ns
T
104
XRD HIGH level pulse width 45
-
-
ns
T
105
XRD fall → DB [7:0] output
-
-
60 ns
T
106
XRD rise → DB [7:0] hold 2
-
-
ns
XCS
AD[4:0]
T
105
DB[7:0]
XRD
T
101
T
103
T
102
T
106
T
104
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8.4.1.2 Register Write Timing
Symbol Specification Min. Typ. Max. Unit
T
111
XCS fall → XWR fall
AD [4:0] valid → XWR fall
0
-
-
ns
T
112
XWR rise → AD [4:0] invalid
XWR rise → XCS ris e
0
-
-
ns
T
113
XWR LOW level pulse width 40
-
-
ns
T
114
XWR HIGH level pulse width 45
-
-
ns
T
115
DB [7:0] valid → XWR rise 10
-
-
ns
T
116
XWR rise → DB [7:0] hold 0
-
-
ns
XCS
AD[4:0]
DB[7:0]
XWR
T
111
T
113
T
114
T
115
T
116
T
112
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8.4.2 SCSI Interface
8.4.2.1 Selection Timing
Symbol Specification Min. Typ. Max. Unit
T
201
XSBSY(IN) ↑ -XSBSY(OUT) ↓,
OWNID valid
1600
-
-
ns
T
202
XSBSY(OUT) ↓ -XSSEL ↓ 3000 -
-
ns
T
203
XSSEL ↓ -SELID valid 1500
-
-
ns
T
204
SELID valid -XSBSY(OUT) ↑ 150 -
-
ns
T
205
XSBSY(OUT) ↑ -XSBSY(IN) ↓ 500 -
-
ns
T
206
XSBSY(IN) ↓ -XSSEL ↑ 250 -
-
ns
XSBSY(IN)
XSSEL
XSBSY(OUT)
XSDB0-7,P
XSATN
XSIO
T
201
T
202
T
203
T
204
T
205
T
206
Page 42
S1R72104 Technical Manual
Rev.1.1 EPSON
37
8.4.2.2 Re-selection Timing
Symbol Specification Min. Typ. Max. Unit
T
207
XSBSY(IN) ↑ -XSBSY(OUT) ↓,
OWNID valid
1600
-
-
ns
T
208
XSBSY(OUT) ↓ -XSSEL ↓ 3000 -
-
ns
T
209
XSSEL ↓ -SELID valid,
XSIO ↓
1500
-
-
ns
T
210
SELID valid -XSBSY(OUT) ↑ 150 -
-
ns
T
211
XSBSY(OUT) ↑ -XSBSY(IN) ↓ 500 -
-
ns
T
212
XSBSY(IN) ↓ -XSBSY(OUT) ↓ 100
- -
ns
T
213
XSBSY(OUT) ↓ -XSSEL ↑ 150 -
-
ns
XSBSY(IN)
XSSEL
XSBSY(OUT)
XSDB0-7,P
XSIO
T
207
T
209
T
208
T
210
T
213
T
212
T
211
Page 43
S1R72104 Technical Manual
38 EPSON
Rev.1.1
8.4.2.3 Timing of Being Selected
Symbol Specification Min. Typ. Max. Unit
T
214
SELID valid -XSBSY(IN) ↑ 0 -
-
ns
T
215
XSBSY(IN) ↑ XSBSY(OUT) ↓ 800 -
-
ns
T
216
XSBSY(OUT) ↓ XSSEL ↑ 0 -
-
ns
XSBSY(IN)
XSSEL
XSBSY(OUT)
XSDB0-7,P
T
215
T
216
T
214
Page 44
S1R72104 Technical Manual
Rev.1.1 EPSON
39
8.4.2.4 Timing of Being Selected
Symbol Specification Min. Typ. Max. Unit
T
217
SELID valid -XSBSY(IN) ↑ 0 -
-
ns
T
218
XSBSY(IN) ↑ XSBSY(OUT) ↓ 800
-
-
ns
T
219
XSBSY(OUT) ↑ XSSEL ↑ 0
- -
ns
T
220
XSSEL ↓ -XSBSY(OUT) ↑
-
-
200 ns
XSBSY(IN)
XSSEL
XSBSY(OUT)
XSDB0-7,P
XSIO
T
218
T
217
T
219
T
220
Page 45
S1R72104 Technical Manual
40 EPSON
Rev.1.1
8.4.2.5 XSATN Output Timing
Symbol Specification Min. Typ. Max. Unit
T
221
XSREQ ↓ -XSATN ↑ 25
-
-
ns
T
222
XSATN ↑ -XSACK ↓ 150
-
-
ns
XSATN
XSREQ
XSACK
XSDB0-7,P
XSMSG
XSIO
XSCD
T
221
T
222
LAST MESSAGE
Page 46
S1R72104 Technical Manual
Rev.1.1 EPSON
41
8.4.2.6 Initiator Asynchronous Data-out Timing (Data output)
Symbol Specification Min. Typ. Max. Unit
T
223
XSREQ ↓ -XSACK ↓ 25
-
-
ns
T
224
XSDB valid –XSACK ↓ 100
- -
ns
T
225
XSREQ ↑ -XSACK ↑ 25 - 90
ns
T
226
XSACK ↑ -XSDB invalid 50
-
-
ns
XSDB0-7,P
XSACK
XSREQ
T
224
T
223
T
225
T
226
Page 47
S1R72104 Technical Manual
42 EPSON
Rev.1.1
8.4.2.7 Initiator Asynchronous Data-in Timing (Data input)
Symbol Specification Min. Typ. Max. Unit
T
227
XSDB valid -XSREQ ↓ 30
-
-
ns
T
228
XSREQ ↓ -XSACK ↓ 25
- -
ns
T
229
XSACK ↓ -XSDB invalid 0
- -
ns
T
230
XSREQ ↑ -XSACK ↑ 25
-
90 ns
XSDB0-7,P
XSACK
XSREQ
T
227
T
228
T
229
T
230
Page 48
S1R72104 Technical Manual
Rev.1.1 EPSON
43
8.4.2.8 Initiator Synchronous Data-out Timi ng ( Data out put)
Symbol Specification Min. Typ. Max. Unit
T
231
XSDB valid -XSACK ↓ 25
-
-
ns
T
232
XSACK ↓ -XSDB invalid 25
- -
ns
T
233
XSACK ↓ -XSACK ↑ 25
- -
ns
T
234
XSACK ↑ - (NEXT) XSACK ↓ 25 -
-
ns
Note: Value of when RATE3 to 0bit is “0000”
The timing of switching data is the same as in the case of XSREQ rise.
XSDB0-7,P
XSACK
T
231
T
232
T
233
T
234
Page 49
S1R72104 Technical Manual
44 EPSON
Rev.1.1
8.4.2.9 Initiator Synchronous Data-in Timi ng ( Dat a i nput )
Symbol Specification Min. Typ. Max. Unit
T
235
XSDB0-7, P valid –XSREQ ↓ 6.5
-
-
ns
T
236
XSREQ ↓ -XSDB0-7, P invalid 5
- -
ns
T
237
XSREQ ↓ -XSREQ ↑ 11
- -
ns
T
238
XSREQ ↑ -XSREQ ↓ 11
-
-
ns
XSDB0-7,P
XSREQ
T
235
T
236
T
237
T
238
Page 50
S1R72104 Technical Manual
Rev.1.1 EPSON
45
8.4.2.10 Target Asynchronous Data-in Timing (Data output)
Symbol Specification Min. Typ. Max. Unit
T
239
XSDB valid -XSREQ ↓ 100
-
-
ns
T
240
XSACK ↑ -XSREQ ↑ 25 - 90
ns
T
241
XSREQ ↑ -XSDB invalid 50
- -
ns
T
242a
XSACK ↑ - (NEXT) XSREQ ↓ 25
- -
ns
T
242b
XSREQ ↑ -XSREQ ↓ 150
-
-
ns
XSDB0-7,P
XSREQ
XSACK
T
239
T
241
T
242b
T
242a
T
240
Page 51
S1R72104 Technical Manual
46 EPSON
Rev.1.1
8.4.2.11 Target Asynchronous Data-out Ti m i ng ( Dat a i nput )
Symbol Specification Min. Typ. Max. Unit
T
243
XSDB valid -XSACK ↓ 30
-
-
ns
T
244
XSACK ↓ -XSREQ ↑ 25 - 90
ns
T
245
XSREQ ↑ -XSDB invalid 0
- -
ns
T
246a
XSACK ↑ -XSREQ ↓ 25
- -
ns
T
246b
XSREQ ↑ -XSREQ ↓ 150
-
-
ns
XSDB0-7,P
XSREQ
XSACK
T
243
T
245
T
244
T
246a
T
246b
Page 52
S1R72104 Technical Manual
Rev.1.1 EPSON
47
8.4.2.12 Target Synchronous Data - i n Timing (Data output)
Symbol Specification Min. Typ. Max. Unit
T
247
XSDB valid –XSREQ ↓ 25
-
-
ns
T
248
XSREQ ↓ -XSDB invalid 25
- -
ns
T
249
XSREQ ↓-XSREQ ↑ 25
- -
ns
T
250
XSREQ ↑ -XSREQ ↓ 25
-
-
ns
Note: Value of when RATE3 to 0bit is “0000”
The timing of switching data is the same as in the case of XSREQ rise.
XSDB0-7,P
XSREQ
T
247
T
248
T
249
T
250
Page 53
S1R72104 Technical Manual
48 EPSON
Rev.1.1
8.4.2.13 Target Synchronous Data - out Timing (Data input)
Symbol Specification Min. Typ. Max. Unit
T
251
XSDB valid -XSACK ↓ 6.5
-
-
ns
T
252
XSACK ↓ -XSDB invalid 5
- -
ns
T
253
XSACK ↓-XSACK ↑ 11
- -
ns
T
254
XSACK ↑ -XSACK ↓ 11
-
-
ns
XSDB0-7,P
XSACK
T
251
T
252
T
253
T
254
Page 54
S1R72104 Technical Manual
Rev.1.1 EPSON
49
8.4.3 Port Interface
8.4.3.1 DMA Read (PSLV=1: Slave mode)
Symbol Specification Min. Typ. Max. Unit
T
301
XPWR → XPDACK ↓
XPDACK setup time
5
-
-
ns
T
302
XPDACK ↑ → XPWR
XPDACK hold time
5
- -
ns
T
303
XPRD ↓ → PDREQ negate
PDREQ negate delay time
10
-
40
(35) Note 1
ns
T
304
XPDACK ↓ → XPRD ↓
XPRD setup time
0
- -
ns
T
305
XPRD ↓ → XPRD ↑
XPRD assert pulse width
30
- -
ns
T
306
XPRD ↑ → XPRD ↓
XPRD negate pulse width
30
- -
ns
T
307
XPRD ↑ → XPDACK ↑
XPRD hold time
0
- -
ns
T
308
XPRD ↓ → PD
Data output delay time Note 1
0
-
25
(20) Note 2
ns
T
309
XPRD ↑ → PD(Hi-Z)
Data bus negate time Note 1
6
-
40 ns
Note 1: Data is output to PD only while both XPDACK and XPRD are asserted.
PD is always in Input mode except such time.
Note 2: The value in ( ) is guaranteed by limiting load capacitance, 15pF, and 1TTL to driving.
Direction of data transfer
Prosessor S1R72104 HOST
PDREQ(0)
(PRQLV=1)
XPDACK(I)
XPRD(I)
PD15-0(0)
XPWR(I)
T
304
T
305
T
306
T
303
T
307
T
301
T
308
T
309
T
302
Page 55
S1R72104 Technical Manual
50 EPSON
Rev.1.1
8.4.3.2 DMA Write (PSLV=1: Slave mode)
Symbol Specification Min. Typ. Max. Unit
T
311
XPRD → XPDACK ↓
XPDACK setup time
5
-
-
ns
T
312
XPDACK ↑ → XPRD
XPDACK hold time
5
- -
ns
T
313
XPWR ↓ → PDREQ negate
PDREQ negate delay time
10
-
40
(35) Note 1
ns
T
314
XPDACK ↓ → XPWR ↓
XPWR setup time
0
- -
ns
T
315
XPWR ↓ → XPWR ↑
XPWR assert pulse width
30
- -
ns
T
316
XPWR ↑ → XPWR ↓
XPWR negate pulse width
30
- -
ns
T
317
XPWR ↑ → XPDACK ↑
XPWR hold time
0
- -
ns
T
318
PD → XPWR ↑
Data input delay time
10
- -
ns
T
319
XPWR ↑ → PD
Data hold time
0
-
-
ns
Note 1: The value in ( ) is guaranteed by limiting load capacitance, 15pF, and 1TTL to driving.
PDREQ(0)
(PRQLV=1)
XPDACK(I)
XPWR(I)
PD15-0(I)
XPRD(I)
Direction of data transfer
Prosessor S1R72104 HOST
T
314
T
315
T
316
T
313
T
317
T
318
T
311
T
319
T
312
Page 56
S1R72104 Technical Manual
Rev.1.1 EPSON
51
8.4.3.3 DMA Write (PSLV=0: Master mode)
Symbol Specification Min. Typ. Max. Unit
T
333
XPWR ↓ → PDREQ negate
PDREQ negate delay time
0
-
30 ns
T
334
XPDACK ↓ → XPWR ↓
XPWR setup time
0
-
5
ns
T
335
XPWR ↓ → XPWR ↑
XPWR assert pulse width
-
(AP+2)×25
-
ns
T
336
XPWR ↑ → XPWR ↓
XPWR negate pulse width
-
(NP+2)×25
-
ns
T
337
XPWR ↑ → XPDACK ↑
XPWR hold time
0
-
5
ns
T
338
XPWR ↓ → PD
Data output delay time Note 1
0
-
25
ns
T
339
XPWR ↑ → PD(Hi-Z)
Data bus negate time Note 1
5
-
40
ns
T
33A
PDREQ negate → XPDACK ↑
XPDACK setup time
5
-
-
ns
Note 1: Data is output to PD only while both XPDACK and XPWR are asserted.
PD is always in Input mode except such time.
Direction of data transfer
Prosessor
S1R72104
HOST
PDREQ(I)
XPDACK(0)
XPWR(0)
PD15-0(0)
T
334
T
337
T
336
T
333T33A
T
335
T
338
T
339
Page 57
S1R72104 Technical Manual
52 EPSON
Rev.1.1
8.4.3.4 DMA Read (PSLV=0: Master mode)
Symbol Specification Min. Typ. Max. Unit
T
343
XPRD ↓ → PDREQ negate
PDREQ negate delay time
0
-
30 ns
T
344
XPDACK ↓ → XPRD ↓
XPRD setup time
0
-
5
ns
T
345
XPRD ↓ → XPRD ↑
XPRD assert pulse width
-
(AP+2)×25
-
ns
T
346
XPRD ↑ → XPRD ↓
XPRD negate pulse width
-
(NP+2)×25
-
ns
T
347
XPRD ↑ → XPDACK ↑
XPRD hold time
0
-
5
ns
T
348
PD → XPRD ↑
Data input delay time
10
- -
ns
T
349
XPRD ↑ → PD
Data hold time
0
- -
ns
T
34A
PDREQ negate → XPDACK ↑
XPDACK setup time
5
-
-
ns
Direction of data transfer
Prosessor
S1R72104 HOST
PDREQ(I)
XPDACK(0)
XPRD(0)
PD15-0(I)
T
344
T
345
T
346
T
343T34A
T
347
T
348
T
349
Page 58
S1R72104 Technical Manual
Rev.1.1 EPSON
53
8.4.4 Others
8.4.4.1 OSCIN Input Clock (ex.40MHz) Note: Maximum input voltage: LV
DD
Symbol Specification Min. Typ. Max. Unit
T
400
CLK cycle *1
-
25
(1/f)
-
ns
T
401
CLK HIGH width *1
10
(1/f)×0.4
-
15
(1/f)×0.6
ns
T
402
CLK LOW width *1
10
(1/f)×0.4
-
15
(1/f)×0.6
ns
T
403
CLK rise time
-
-
5
ns
T
404
CLK fall time
-
-
5 ns
*1 T
401+402=T400
*1 Specified in the same rate also in any cases other than CLK input = 40MHz.
T
400
T
401
T
403
T
404
T
402
1.9V
0.9V
Page 59
S1R72104 Technical Manual
54 EPSON
Rev.1.1
8.4.4.2 EXCLK Input Clock (ex.40MHz) Note: Maxim um i nput voltage: HVDD
Symbol Specification Min. Typ. Max. Unit
T
410
CLK cycle *1
-
25
(1/f)
-
ns
T
411
CLK HIGH width *1
10
(1/f)×0.4
-
15
(1/f)×0.6
ns
T
412
CLK LOW width *1
10
(1/f)×0.4
-
15
(1/f)×0.6
ns
T
413
CLK rise time
-
-
5
ns
T
414
CLK fall time
-
-
5 ns
*1 T
411+412=T410
*1 Specified in the same rate also in any cases other than EXCLK input = 40MHz.
T
410
T
411
T
413
T
414
T
412
1.9V
0.9V
Page 60
S1R72104 Technical Manual
Rev.1.1 EPSON
55
8.4.4.3 XRESET Input Pulse Width
Symbol Specification Min. Typ. Max. Unit
T
420
XRESET LOW width 150
-
-
ns
8.4.4.4 TESTMON (CLKOUT = HI G H) O utput Pul se
* When PLL is operated
(When PLL is not used, the waveform inputted is output to CLKINorEXCLK pin.)
* HIGH level is LV
DD
.
Symbol Specification Min. Typ. Max. Unit
T
430
TESTMON cycle *1
-
25
-
ns
T
431
TESTMON HIGH width
(T431
/T
430
)
45
-
55 ns
*1: The accuracy of the output clock depends on the accuracy of the clock oscillated by CLKIN or that
inputted to CLKIN,EXCLK.
T
420
XRESET
T
431
T
430
TESTMON
Page 61
S1R72104 Technical Manual
56 EPSON
Rev.1.1
9. EXAMPLES OF CONNECTION
(When 20MHz OSC oscillation is used)
S1R72104
XCSXCS
XRDXRD
XWRXWR
AD [4:0]AD [4:0]
DB [7:0]DB [7:0]
XINTXINT
∗
CPU Interface (5V type)
PD [15:0]PD [15:0]
PDREQPDREQ
XPDACKXPDACK
XPWRXPWR
XPRDXPRD
∗
PORT Interface (5V type)
EXCLK
XPLLPD
3.3V
PLLCT1
PLLCT0
CLKSEL1
CLKSEL0
V
C
100pF
OSCIN
5pF
OSCOUT
5pF
TESTMONopen
6.8kΩ
1MΩ 20.0MHz
∗
SCSI Interface
active terminator
DB [7:0]XSDB [7:0]
DBPXSDBP
ATNXSATN
BSYXSBSY
ACKXSACK
RSTXSRST
MSGXSMSG
SELXSSEL
C/DXSCD
REQXSREQ
I/OXSIO
XRESETXRESET
HV
DD
5V
LV
DD
3.3V
V
SS
GND
TESTEN
Page 62
S1R72104 Technical Manual
Rev.1.1 EPSON
57
10. EXTERNAL DIMENSIONS DRAWING
Plastic QFP15-100 pin
INDEX
14
±0.1
51
75
76
50
16
±0.4
14
±0.1
26
100
1
25
0.18
-0.05
1.7Max.
0.1
1.4
±0.1
1
0.125
-0.025
0.5
±0.2
10°
0°
+0.1
0.5
+0.05
Unit : mm
16
±0.4
Page 63
International Sales Operations
AMERICA
EPSON ELECTRONICS AMERICA, INC.
HEADQUARTERS
150 River Oaks Parkway
San Jose, CA 95134, U.S.A.
Phone: +1-408-922-0200 FAX: +1-408-922-0238
SALES OFFICES
West
1960 E.Grand Avenue
El Segundo, CA 90245, U.S.A.
Phone: +1-310-955-5300 FAX: +1-310-955-5400
Central
101 Virginia Street, Suite 290
Crystal Lake, IL 60014, U.S.A.
Phone: +1-815-455-7630 FAX: +1-815-455-7633
Northeast
301 Edgewater Place, Suite 120
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Phone: +1-781-246-3600 FAX: +1-781-246-5443
Southeast
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Phone: +1-877-EEA-0020 FAX: +1-770-777-2637
EUROPE
EPSON EUROPE ELECTRONICS GmbH
HEADQUARTERS
Riesstrasse 15
80992 Munich, GERMANY
Phone: +49-(0)89-14005-0 FAX: +49-(0)89-14005-110
DÜSSELDORF BRANCH OFFICE
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51379 Leverkusen, GERMANY
Phone: +49-(0)2171-5045-0 FAX: +49-(0)2171-5045-10
UK & IRELAND BRANCH OFFICE
Unit 2.4, Doncastle House, Doncastle Road
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Phone: +44-(0)1344-381700 FAX: +44-(0)1344-381701
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Phone: +33-(0)1-64862350 FAX: +33-(0)1-64862355
BARCELONA BRANCH OFFICE
Barcelona Design Center
Edificio Testa, Avda. Alcalde Barrils num. 64-68
E-08190 Sant Cugat del Vallès, SPAIN
Phone: +34-93-544-2490 FAX: +34-93-544-2491
Scotland Design Center
Integration House, The Alba Campus
Livingston West Lothian, EH54 7EG, SCOTLAND
Phone: +44-1506-605040 FAX: +44-1506-605041
ASIA
EPSON (CHINA) CO., LTD.
23F, Beijing Silver Tower 2# North RD DongSanHuan
ChaoYang District, Beijing, CHINA
Phone: 64106655 FAX: 64107319
SHANGHAI BRANCH
7F, High-Tech Bldg., 900, Yishan Road,
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Phone: 86-21-5423-5577 FAX: 86-21-5423-4677
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Phone: +852-2585-4600 FAX: +852-2827-4346
Telex: 65542 EPSCO HX
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Taipei
Phone: 02-2717-7360 FAX: 02-2712-9164
Telex: 24444 EPSONTB
HSINCHU OFFICE
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HsinChu 300
Phone: 03-573-9900 FAX: 03-573-9169
EPSON SINGAPORE PTE., LTD.
No. 1 Temasek Avenue, #36-00
Millenia Tower, SINGAPORE 039192
Phone: +65-6337-7911 FAX: +65-6334-2716
SEIKO EPSON CORPORATION
KOREA OFFICE
50F, KLI 63 Bldg., 60 Yoido-dong
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Phone: 02-784-6027 FAX: 02-767-3677
GUMI OFFICE
6F, Good Morning Securities Bldg., 56 Songjeong-Dong,
Gumi-City, Seoul, 730-090, KOREA
Phone: 054-454-6027 FAX: 054-454-6093
- JAPAN -
SEIKO EPSON CORPORATION
ELECTRONIC DEVICES MARKETING DIVISION
IC Marketing Department
IC Marketing & Engineering Group
421-8, Hino, Hino-shi, Tokyo 191-8501, JAPAN
Phone: +81-(0)42-587-5816 FAX: +81-(0)42-587-5624
ED International Marketing Department
421-8, Hino, Hino-shi, Tokyo 191-8501, JAPAN
Phone: +81-(0)42-587-5814 FAX: +81-(0)42-587-5117
Page 64
In pursuit of “Saving” Technology, Epson electronic devices.
Our lineup of semiconductors, displays and quartz devices
assists in creating the products of our customers’ dreams.
Epson IS energy savings.
Page 65
First issue October, 2002
Printed in Japan
H
A
EPSON Electronic Devices Website
ELECTRONIC DEVICES MARKETING DIVISION
SEIKO EPSON CORPORATION
http://www.epsondevice.com/
S1R72104
Technical Manual
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