EPSON S1D13742 User Guide

S1D13742 Mobile Graphics Engine

S5U13742P00C100 Evaluation Board

User Manual

Document Number: X63A-G-002-01

Status: Revision 1.0

Issue Date: 2007/08/15

Information in this document is subject to change without notice. You may download and use this document, but only for your own use in evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any representation that the contents of this document are accurate or current. The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws.

EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.

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S1D13742 S5U13742P00C100 Evaluation Board User Manual X63A-G-002-01 Issue Date: 2007/08/15

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1 Introduction

This manual describes the setup and operation of the S5U13742P00C100 Evaluation Board. The evaluation board is designed as an evaluation platform for the S1D13742 Mobile Graphics Engine.

The S5U13742P00C100 evaluation boar d can be used with many native platfor ms vi a the host connector which provides the appropriate signals to support a variety of CPUs. The S5U13742P00C100 evaluation board can also connect to the S5U13U00P00C100 USB Adapter board so that it can be used with a laptop or desktop computer, via USB 2.0.

This user manual is updated as appropriate. Please check the Epson Research and Development Website at www.erd.epson.com for the latest revision of this document before beginning any development.

We appreciate your comments on our documentation. Please contact us via email at documentation@erd.epson.com.

S5U13742P00C100 Evaluation Board User Manual S1D13742 Issue Date: 2007/08/15 X63A-G-002-01

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2 Features

The S5U13742P00C100 Evaluation Board includes the following features:

• 121-pin FCBGA S1D13742 Mobile Graphics Engine

• Header with all S1D13742 Host Bus Interface signals

• Headers for connection to the S5U13U00P00C100 USB Adapter board

• Headers for connecting to LCD panels

• Header for S1D13742 GPIO pins (optional)

• On-board 4MHz oscillator

• 14-pin DIP socket (if a clock other than 4MHz must be used)

• 3.3V input power

• On-board voltage regulator with 1.5V output

• On-board voltage regulator with adjustable 6~24V output, 40mA max., to provide power for LED backlight of LCD panels.

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3 Installation and Configuration

The S5U13742P00C100 evaluation board incorporates a DIP switch, jumpers, and 0 ohm resistors which allow it to be used with a variety of different configurations.

3.1 Configuration DIP Switch

The S1D13742 has 3 configuration inputs (CNF[2:0]). A DIP switch (SW1) is used to configure CNF[2:0] as described below.

Table 3-1: Summary of Power-On/Reset Options

SDU13742P00C100

SW1-[4:1] Config

SW1-[1] CNF0 SW1-[2] CNF1 Host Data is 16-bit Host data is 8-bit SW1-[3] CNF2 PIOVDD output current = 6.5mA PIOVDD output current = 2.5mA SW1-[4] - not used

S1D13742

CNF[2:0] Config

1 (ON) 0 (OFF)

Host Data lines are normal Host data lines are swapped

Power-On/Reset State

DIP Switch

SW1

= Required settings when using S5U13U00P00C100 USB Adapter board

The following figure shows the location of DIP switch SW1 on the S5U13742P00C100 board.

Figure 3-1: Configuration DIP Switch (SW1) Location

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3.2 Configuration Jumpers

The S5U13742P00C100 has 6 jumpers whi ch configure various board settings. The jumper positions for each function are shown below.

Jumper Function Position 1-2 Position 2-3 No Jumper

JP1 COREVDD Normal —

JP2 PLLVDD Normal —

JP3 IOVDD Normal — JP4 IOVDD Source H1 connector, pin 32 JP5 PIOVDD Normal — JP6 PIOVDD Source H4 connector, pin 8

= Required settings when using S5U13U00P00C100 USB Adapter board

3.3VDD —

COREVDD current

measurement

PLLVDD current

measurement

IOVDD current

measurement

PIOVDD current

measurement

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JP1, JP2, JP3, JP5 - Power Supplies for the S1D13742

JP1, JP2, JP3, JP5 can be used to measure the current consumption of each S1D13742 power supply. When the jumper is at position 1-2, normal operation is selected. When no jumper is installed, the current consumption for each power supply can be measured by connecting an ammeter to pin 1 and 2 of the jumper.

The jumper associated with each power supply is as follows:

JP1 for COREVDD JP2 for PLLVDD JP3 for IOVDD JP5 for PIOVDD

JP3 JP5 JP1 JP2

Figure 3-2: Configuration Jumper Locations (JP1, JP2, JP3, JP5)

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JP4 - IOVDD Source

JP4 is used to select the source for the IOVDD supply voltage. When the jumper is at position 1-2, the IOVDD voltage must be provided to the H1 connector, pin 32. When the jumper is at position 2-3, the IOVDD voltage is provided by the 3.3V power supply of the board.

JP4

Figure 3-3: Configuration Jumper Location (JP4)

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JP6 - SIOVDD Source

JP6 is used to select the source for the PIOVDD supply voltage. When the jumper is at position 1-2, the PIOVDD voltage must be provided to the H4 connector, pin 8. When the jumper is at position 2-3, the PIOVDD voltage is provided by the 3.3V power supply of the board.

JP6

Figure 3-4: Configuration Jumper Location (JP6)

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4 Technical Description

4.1 Power

4.1.1 Power Requirements

The S5U13742P00C100 evaluation board requires an external regulated power supply (3.3V / 0.5A). The power is supplied to the evaluation board through pin 34 of the H1 header, or pin 5 of the P2 header.

The green LED ‘3.3V Power’ is turned on when 3.3V power is applied to the board.

4.1.2 Voltage Regulators

The S5U13742P00C100 evaluation board has an on-board linear regulator to provide the

1.5V power required by the S1D13742 Mobile Graphics Engine. It also has a step-up

switching voltage regul ator t o genera te ad justa ble 6~24 V, which can be us ed to power the LED backlight on some LCD panels.

4.1.3 S1D13742 Power

The S1D13742 Mobile Graphics Engine requires 1.5V and 1.65~3.6V power supplies.

1.5V power for COREVDD and PLLVDD is provided by an on-board linear voltage

regulator.

IOVDD can be in the range of 1.65~3.6V. When JP4 is set to the 2-3 position, IOVDD is connected to 3.3V. If a di fferent voltage is required f or IOVDD, set JP4 to the 1-2 p osition and connect the external power supply to pin 32 of connector H1.

Note

If the IOVDD voltage is less than 3.0V, an oscillator working at the selected IOVDD voltage must be used.

PIOVDD is the power used by the LCD interface and can be in the range of 1.65~3.6V. When JP6 is set to the 2-3 posit ion, PIOVDD is con nected to 3.3 V. If a diffe rent volt age is needed for PIOVDD because of the LCD panel requirements, set JP6 to the 1-2 position and connect the external power supply to pin 8 of connector H4.

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4.2 Clocks

The clock for the S1D13742 Mobile Graphics Engine is provided by a 4MHz oscillator.

The S5U13742P00C100 evaluation board has a DIP14 footprint for an optional second oscillator, Y2. This is provided for cases requiring a different clock frequency for the S1D13742 Mobile Graphics Engine. To use Y2, an oscillat or must b e populated in the Y2 footprint and the following board modifications must be made.

1. Remove R10 (33 ohm resistor, size 0402) to cut the output of Y1.

2. Populate R13 with a 33 ohm resistor, size 0402, to connect the output of Y2 to the CLKI input of the S1D13742 Mobile Graphics Engine.

Note

If the board is configured for an IOVDD voltage below 3.0V, an oscillator working at the selected IOVDD voltage must be used at Y2. The on-board 4MHz oscillator is not specified to work below a 3.0V supply voltage.

The S1D13742 MGE can output the input cl ock on the CLKOUT pin depending on the state of the CLKOUTEN input. Both these signals ar e available on the H4 connec tor: CLKOUT on pin 1 and CLKOUTEN on pin 4. On the board the CLKOUTEN pin is pulled down which disables the CLKOUT signal. Note that connector H4 is not populated on the S5U13742P00C100 evaluation board.

4.3 Reset

4.4 Power Save

The S1D13742 Mobile Graphics Engine on the S5U13742P00C100 evaluation board can be reset using a push-button (SW2), or via an active low reset signal from the host development platform (pin 33 on the H1 connector).

The S1D13742 chip has an input called PWRSVE that will enable (when high) or disable (when low) the power save mode. This signal is avail able on pin 5 of the H4 connector. On the board the PWRSVE pin is pulled down which means power save mode is controlled only by the S1D13742 register setting. Note that connector H4 is not populated on the S5U13742P00C100 evaluation board.

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4.5 Host Interface

4.5.1 Direct Host Bus Interface Support

All S1D13742 host interface pins are available on connector H1 which allows the S5U13742P00C100 evaluation board to be connected to a variety of development platforms. For detailed S1D13742 pin mapping, refer to the S1D13742 Hardware Functional Specification, document number X63A-A-001-xx.

The following figure shows the location of host bus connector H1. H1 is a 0.1x0.1” 34-pin header (17x2).

H1

Figure 4-1: Host Bus Connector Location (H1)

For the pinout of connector H1, see “Schematic Diagrams” on page 21.

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4.5.2 Connecting to the Epson S5U13U00P00C100 USB Adapter Board

The S5U13742P00C100 evaluatio n bo ard i s designed to connec t to a S 5U13U00P00 C100 USB Adapter Board. The USB adapter board provides a simple connection to any computer via a USB 2.0 connection. The S5U13742P00C100 directly connects to the USB adapter board through connectors P1 and P2.

The USB adapter board also supplies the 3.3V power requir ed by the S5U13742P00C1 00. IOVDD should be selected for 3.3V and JP4 should be set to the 2-3 position.

When the S5U13742P00C100 is connected to the S5U13U00P00C100 USB Adapter board, there are 2 LEDs on S5U1374 2P00C100 which provide a quick visual status of the USB adapter. LED1 blinks to i ndicate that the USB adapter board is active. LED2 turns on to indicate that the USB has been enumerated by the PC.

The following diagram shows the location of connectors P1 and P2. P1 and P2 are 40-pin headers (20x2).

P1

P2

Figure 4-2: USB Adapter Connector Locations (P1 and P2)

For the pinout of connectors P1 and P2, see “Schematic Diagrams” on page 21.

Note

A windows driver must be installed on the PC when the S5U13742P00C100 is used with the S5U13U00P00C100 USB Adapter Board. The S1D13xxxUSB driver is available at www.erd.epson.com.

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4.6 LCD Panel Interface

The LCD interface signals are available on connectors H2 and H3. For S1D13742 LCD interface pin mapping, refer to the S1D13742 Hardware Functional Specification, document number X63A-A-001-xx.

Connector H2 is 0.1x0.1” 2 0-pin header (10x2) and con nector H3 is 0.1x0.1” 40-pi n header (20x2). For the pinout of connectors H2 and H3, see “Schematic Diagrams” on page 21.

On the evaluation board there is an adjustable 6~24V, 40mA max. power supply. This voltage is provided only on connector H3 (it is not used elsewhere on the board). It is intended for use to power t he LED backlig ht on some LCD panels . The voltage is adjust ed by the R24 pot.

Note

For LCD panels that use a CCFL backlight, an external power supply must be used to provide power to the inverter for the CCFL backlight. Usually, the inverter current consumption is higher than the maximum 40mA current available from the on-board voltage regulator.

H2

The following diagram shows the location of the LCD panel connectors H2 and H3.

H3

Figure 4-3: LCD Panel Connectors Location (H2, H3)

For the pinout of connectors H2 and H3, see “Schematic Diagrams” on page 21.

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4.7 GPIO Connections

The S1D13742 Mobile Graphics Engine has 8 GPIO pins . All the GPIO pi ns are rou ted to the H4 connector. Note that connector H4 is not populated on the S5U13742P00C100 evaluation board.

The following figure shows the location of the GPIO connector, H4.

H4

Figure 4-4: GPIO Connector Location (H4)

For the pinout of connector H4, see “Schematic Diagrams” on page 21.

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5 Parts List

Table 5-1: Parts List

Item Qty Reference Part Description Mfg / Mfg PN / Notes

C1, C2, C3, C4, C9, C12,

116

212

3 1 C10 1nF C0402

4 1 C11 10uF C0805 5 1 C29 100uF 4V T C3528 Kemet T494B107M004AS 6 2 C31, C33 0.01uF C0402 7 1 C34 4.7uF 10V T C3528 Kemet T491B475K010AS 8 1 C35 10pF C0402 9 1 C36 1uF 50V C1206 TDK C3216X7R1 H105 K

10 3 D1, D2, D3 LED0603

11 1 D4 MBR0530 SOD-123

12 2 F1, F2 ACF451832-222

13 1 H1 HEADER_1 7X2 AMP 1-87215-7 14 1 H2 Extended LCD Connector Samtec TST-110-01-G-D 15 1 H3 LCD Connector Samtec TST-120-01-G-D 16 0 H4 HEADER 8X2 Samtec TSW-108-07-G-D

17 4 JP1, JP2, JP3, JP5 SIP2

18 2 JP4, JP6 SIP3

19 2 L1, L2 Ferrite R0603

C13, C14, C18, C19, C20, C21, C26, C27, C28, C30,

C32

C5, C6, C7, C8, C15, C16, C17, C22, C23, C24, C25,

0.1uF C0402

0.01uF C0402

Yageo America

04022F104Z7B20D

Yageo America

0402ZRY5V7BB103

Yageo America

04022R102K9B20D

Panasonic - ECG ECJ-CV50J106M

Kemet

C0402C103K4RACTU

Panasonic - ECG

ECJ-0EC1H100D

Panasonic - SSG

LNJ308G8LRA

LED GREEN SS TYPE

LOW CUR SMD

Micro Comm ercial Co.

MBR0530-TP

TDK ACF451 832-222

FILTER 3-TERM 60MHZ

300MA SMD

CONN HEADER VERT

2POS .100 TIN or

GENERIC

CONN HEADER VERT

3POS .100 TIN or

GENERIC

Steward

HZ0603B751R-10

FERRITE 200MA 938

OHMS 0603 SMD

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Table 5-1: Parts List

Item Qty Reference Part Description Mfg / Mfg PN / Notes

Panasonic - ECG

ELL-6SH100M

20 1 L3 10uH IND_ELL6

COIL 10UH 1300MA

CHOKE SMD 21 2 P1, P2 HEADER_20X2 HDR2X20/2MM 3M 151240-8422-RB 22 3 R1, R2, R3 10k R0402 23 3 R4, R7, R19 0 R0603 24 1 R5 150k 1% R0402 25 5 R6, R8, R9, R11, R20 0 R0402 26 1 R10 33 1% R0402 27 0 R12, R13 NP R0402 28 3 R14, R15, R16 270 1% R0402 29 3 R17, R18, R23 47k R0402 30 1 R21 887k 1% RC0603 31 1 R22 22k R0402

32 1 R24 200k

33 6

SH1, SH2, SH3, SH4,

SH5, SH6

.100 in. Jumper Shunt Not Applicable

34 1 SW1 SW4_DIPSW4 DIPSW4

35 1 SW2 SW TACT-SPST SW_EVQQW

36 2 TPGND1, TP3.3VDD1 TP_SMT TP_1206

37 0 TP1, TP2, TP3, TP4 T POINT F SIP1 38 1 U1 S1D13742

Panasonic - ECG

EVN-5ESX50B25

Sullins Electronics Corp.

STC02SYAN

JUMPER SHORTING TIN

CTS Corp 218-4LPST

SWITCH DIP HALF

PITCH 4POS

ITT Industries

KSC241GLFS

SWITCH TACT SILVER

PLT GULLWING

Keystone 5015

PC TEST POINT

MINIATURE SMT

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Table 5-1: Parts List

Item Qty Reference Part Description Mfg / Mfg PN / Notes

Texas Instruments

TPS76915DBVT

39 1 U2 TPS76915DBVT SOT23-5

IC 1.5V 100MA LDO REG

SOT-23-5

TI TPS61040DVBR

40 1 U3 TPS61040 SOT23-5

41 1 Y1 4M OSC

42 0 Y2 14-Pin DIP AMP 2-641609-1

IC CONV DC/DC BOOST

LP SOT-23-5

Connor-Winfield

CWX823-4.0M

OSC 4.0000MHz 3.3V

50ppm SMD

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6 Schematic Diagrams

D

C8

C4

0.1uFC40.1uF

0.01uFC80.01uF

C3

C7

0.01uFC70.01uF

0.1uFC30.1uF

C2

1

1.5VDD

2

JP1

SH1

.100 in. Jum p er Shunt

SH1

.100 in. Jum p er Shunt

2

C5

C1

1

COREVDD

0.01uFC50.01uF

0.1uFC10.1uF

3

C6

0.01uFC60.01uF

0.1uFC20.1uF

CORE

PLL

L1

1.5VDD

Place a 0.01uF a nd a 0.1uF cap on each COREVDD

power pin of the S1D1374 2/S1D743

JP2

SH2

.100 in. Jum p er Shunt

SH2

.100 in. Jum p er Shunt

C

C21

C25

0.1uF

C21

0.1uF

0.01uF

C25

C11

10uF

C11

10uF

1nF

C10

1nF

C10

FerriteL1Ferrite

0.1uFC90.1uF

C9

1

2

PLLVDD

IO

L2

FerriteL2Ferrite

IOVDD

2

JP3

SH3

.100 in. Jum p er Shunt

SH3

.100 in. Jum p er Shunt

C17

0.01uF

C17

C14

C13

C12

1

IOVDD

0.01uF

0.1uF

C16

0.01uF

C16

0.01uF

0.1uF

C15

0.01uF

C15

0.01uF

0.1uF

Place a 0.01uF a nd a 0.1uF cap on ea ch IOVDD

power pins of the S1D137 42 /S1 D13 74 3

IOVDD_IN

3.3VDD

IOVDD

123

JP4

IOVDD SOURCE

.100 in. Jumper Shunt

SH4

.100 in. Jumper Shunt

SH4

C20

C19

PIO

C18

PIOVDD

1

2

PIOVDD

JP5

PIOVDD

JP5

.100 in. Jum p er Shunt

SH5

.100 in. Jum p er Shunt

SH5

0.01uF

C24

0.01uF

C24

0.01uF

0.1uF

0.01uF

C23

0.01uF

0.1uF

C23

0.01uF

C22

0.01uF

0.1uF

C22

power pins of the S1D137 42 /S1 D13 74 3

Place a 0.01uF a nd a 0.1uF cap on ea ch PIOVDD

PIOVDD_IN

3.3VDD

PIOVDD

123

JP6

PIOVDD SOURCE

.100 in. Jumper Shunt

SH6

.100 in. Jumper Shunt

SH6

13Saturday, Ju ne 09, 2007

1

Sheet of

<Doc> 1.0

S1D13742/S1 D13 74 3 PF BG A 121

<Doc> 1.0

S1D13742/S1 D13 74 3 PF BG A 121

<Doc> 1.0

S1D13742/S1 D13 74 3 PF BG A 121

B

Title

Size Document Number Rev

Date:

Title

Size Document Number Rev

Date:

Title

Size Document Number Rev

Date:

2

VD[35:0]

VD0

VD4

VD2

VD3

VD1

L9

L7

VD1L8VD2

VD3L6VD4L5VD5

VD0

3

PLLVDD

D4

PIOVDD

H7

PIOVDD

H5

PIOVDD

G4

PIOVDD

E8

PIOIO PLL

CORE

4

5

IOVDD

H4

IOVDD

D8

IOVDD

C4

CoreVDD

H6

CoreVDD

G7

CoreVDD

E4

CoreVDD

D7

MD0C1MD1C3MD2B2MD3

S1D13742 (S1D13 743)

D

A5

MD2

MD3

MD1

MD0

MD4

MD[15:0]

2

VD12

VD7

VD9

VD5

VD8

VD10

VD6MD6

L4

L3

K10

K9

K8

K7

K6

K5

VD6

VD9

VD7

VD8

VD11

VD10

MD6A8MD7

MD9B9MD10

MD11

MD4A6MD5

MD8

A7

A9

B8

B3

C2

B10

MD12

MD10

MD8

MD9

MD11 VD11

MD5

MD7

VD20

VD13

VD15

VD16

VD22

VD18

VD17

VD23

VD21

VD14

VD19

VD24

VD25

VD26

VD27

VD28

K4

J11

J10

J9

J8

J7

J5

J4

H11

H10

H9

G11

G10

VD13

VD15

VD16

VD18

VD12

MD12

MD13

B5

MD13

VD21

VD14

VD17

VD19J6VD20

VD22

VD23

VD25 (NC)H8VD26 (NC)

VD27 (NC)

VD24 (NC)

VD28 (NC)G9VD29 (NC)G8VD30 (NC)

E#

CS#C7D/C#

W

C8

2TE2

C

RESET#

TED2GPIO_INT

RD#

C9

D3

D1

C10

CS#2RD#2WE#

D/C#

RESET#

GPIO_IN T

2

MD14

MD15

B6

B7

MD14

MD15

3HS3

3

GPIO7

PCLK3DE

GPIO63GPIO53GPIO43GPIO33GPIO23GPIO13GPIO0

VS

VD29

VD30

VD31

VD32

VD33

VD34

VD35

F11

F10

F9

F8

E11

E10VSD10HSD9

D11DEC11

PCLK

VD33 (NC)

VD35 (NC)

VD31 (NC)

VD32 (NC)

VD34 (NC)

CNF0

CLKOUTEN

CNF2H3CNF1

CLKOUT

CLKI

F3

A4

A3

B4

E3

G3

CLKI2

CLKOUT

CLKOUTEN 3

3

123

4

SW1

SW4_DIPSW4

876

5

IOVDD

B B

G1

G2

H1

K3

GPIO2

GPIO0

GPIO1

GPIO3H2GPIO4J1GPIO5J2GPIO6K2GPIO7

VSS

C5

VSS

C6

VSS

E5

VSS

E6

VSS

E7

VSS

F4

VSS

F5

VSS

F6

VSS

F7

VSS

G5

VSS

G6

PLLVSS

D6

NC

L11

NC

L10

NC

L2

NC

L1

NC

K11

NC

K1

NC

E9

NC

B11

NC

B1

NC

A11

NC

A10

NC

A2

NC

The pin names enclosed in brac kets applies to S1D13743 only.

TEST2

PWRSVE

TEST1E1TEST0

TESTEN

J3

F1

E2

PWRSVE3

10kR310k

R3

10kR210k

R2

10kR110k

R1

A1

VCP

SCANEN

U1

F2

D5

A A

3

4

5

Figure 6-1: S5U13742P00C100 Schematics (1 of 3)

S5U13742P00C100 Evaluation Board User Manual S1D13742 Issue Date: 2007/08/15 X63A-G-002-01

Revision 1.0

Page 22 Epson Research and Development

Vancouver Design Center

D

1

IOVDD

1

RESET#

C26

R5R5

0.1uF

C26

150k 1%

1

2

4 3

SW2

2

1

MD[15:0]

MD9

MD11

MD5

MD7

MD13

MD3

1113151719212325272931

MD4

MD6

MD2

MD8

MD15

MD12

MD14

MD10

CS#

1

MD1

3

246810121416182022242628303234

H1

13579

MD0

C

1

1.5VDD

C29

100uF 4V T+C29

100uF 4V T

+

12

TP1TP1

C28

0.1uF

C28

0.1uF

5

4

Vout

NC/FB

GND

Vin

/EN

U2

SW TACT-SPS T

3.3VDD

IOVDD_IN

3.3VDD

33

GPIO_INT

WE#

D/C#

RD#

WE#

D/C#

RD#

RESET#

GPIO_INT

1

1TE1

1

TPS76915DB VTU2TPS76915DB VT

1

2

3

0R60

R6

C27

0.1uF

C27

0.1uF

HEADER_17X2H1HEADER_17X2

3.3VDD

CLKI

TP2TP2

33 1%R10 33 1%

R10

1

3

OE

OUT

VDD

GND

Y1

4M OSCY14M OSC

2

4

C31

0.01uF

C31

0.01uF

0

C30

0.1uF

C30

R90R9

0.1uF

R13 NPR13 NP

1

8

OE

OUT

GND

VDD

R12 NPR12 NP

Y2

14-Pin DIPY214-Pin DIP

Oscillator

TTL/CMOS

7

14

C33

0.01uF

C33

0.01uF

IOVDD

C32

0.1uF

C32

0.1uF

TP3TP3

TPGND1

TP_SMT

TPGND1

TP_SMT

1

23Saturday, June 09, 2007

1

Sheet of

<Doc> 1.0

Host connectors / 1.5V power / clock / reset

<Doc> 1.0

Host connectors / 1.5V power / clock / reset

<Doc> 1.0

Host connectors / 1.5V power / clock / reset

B

Title

Size Document Numbe r Rev

Date:

Title

Size Document Numbe r Rev

Date:

Title

Size Document Numbe r Rev

Date:

2

3

4

MD12

MD14

MD1

MD3

MD5

MD7

MD8

MD10

WE#

2468101214161820222426283032343638

P1

13579

111315171921232527293133353739

MD15

RD#

GPIO_INT

5

D

R4 0R4 0

IOVDD

40

MD13

MD11

MD0

MD9

MD2

MD4

MD6

C

2468101214161820222426283032343638

HEADER_20X2P1HEADER_20X2

P2

13579

111315171921232527293133353739

R7 0R7 0

R8 0R8 0

HEARTBEAT ENUMERATED

CS#

3.3VDD

TP3.3VDD1

TP_SMT

TP3.3VDD1

TP_SMT

1

40

0R11 0

R11

D/C#

B B

3.3VDD

HEADER_20X2P2HEADER_20X2

HEARTBEAT ENUMERATED

3.3V PowerD33.3V Power

D3

AK

R16

270 1%

LED2D2LED2

D2

AK

R15

270 1%

D1

LED1D1LED1

AK

R14

270 1%

A A

4

5

Figure 6-2: S5U13742P00C100 Schematics (2 of 3)

S1D13742 S5U13742P00C100 Evaluation Board User Manual X63A-G-002-01 Issue Date: 2007/08/15

Revision 1.0

Epson Research and Development Page 23 Vancouver Design Center

D

1

2

3

C

1

CLKOUTEN

2468101214

H4

13579

IOVDD

CLKOUT

1

PWRSVE

1

33Saturday, June 09, 2007

1

Sheet of

R18

47k

R18

47k

1

<Doc> 1.0

LCD Connectors/ GPIO connector

<Doc> 1.0

LCD Connectors/ GPIO connector

<Doc> 1.0

PIOVDD_IN

GPIO5

GPIO11GPIO3

LCD Connectors/ GPIO connector

B

Title

Size Document Numbe r Rev

Date:

Title

Size Document Numbe r Rev

Date:

Title

Size Document Numbe r Rev

Date:

16

HEADER 8X2H4HEADER 8X2

GPIO0

1

111315

GPIO21GPIO41GPIO6

R17

1GPIO71

47k

TP4TP4

R22

22k

R22

22k

12VDD3.3VDD

2

3

2

C36

1uF 50V

C36

12VDD

PIOVDD

VD27

VD29

VD31

VD33

VD19

24681012141618

4

5

H2

13579

VD18

VD20 VD21

VD35

VD23

VD25

20

1113151719

VD22

VD24

VD26

Extended LCD ConnectorH2Extended LCD Connector

VD30

VD32

VD34

VD28

VD1

VD0

2468101214161820222426283032343638

H3

13579

111315171921232527293133353739

VD10

VD15

VD11

VD16

VD17

VD5

VD9

VD4

VD[35:0]

1

40

LCD ConnectorH3LCD Connector

VD14

VD3

VD12

VD13

VD6

VD7

VD8

VD2

PCLK1DE

HS

1VS1

1

F2

D4

MBR0530D4MBR0530

L3

Internal Step Up 6 to 24V

Power Supply

Typical 12V @ 40mA

F1

1uF 50V

ACF451832-22 2F2ACF451832-22 2

1

10pF

C35

10pF

C35

2

13

R21

R23

R21

887k 1%

A K

R24

200k

R24

47k

200k

4

2SW1FB3

2

U3

+

C34

VIN5EN

R200R20

0

4.7uF 10V T

GND

TPS61040U3TPS61040

4

Vout=1.233x[1+R103/(R105+R106)] (V)

5

10uHL310uH

12

3

ACF451832-222F1ACF451832-222

1

0

R19

D

C

B B

A A

Figure 6-3: S5U13742P00C100 Schematics (3 of 3)

S5U13742P00C100 Evaluation Board User Manual S1D13742 Issue Date: 2007/08/15 X63A-G-002-01

Revision 1.0

Page 24 Epson Research and Development

Vancouver Design Center

7 Board Layout

Figure 7-1: S5U13742P00C100 Board Layout - Top View

S1D13742 S5U13742P00C100 Evaluation Board User Manual X63A-G-002-01 Issue Date: 2007/08/15

Revision 1.0

Epson Research and Development Page 25 Vancouver Design Center

Figure 7-2: S5U13742P00C100 Board Layout - Bottom View

S5U13742P00C100 Evaluation Board User Manual S1D13742 Issue Date: 2007/08/15 X63A-G-002-01

Revision 1.0

Page 26 Epson Research and Development

Vancouver Design Center

8 References

8.1 Documents

• Epson Research and Developme nt, Inc., S1D1374 2 Hardware Funct ional Speci ficati on, document number X63A-A-001-xx.

8.2 Document Sources

• Epson Research and Development Website: http://www.erd.epson.com.

S1D13742 S5U13742P00C100 Evaluation Board User Manual X63A-G-002-01 Issue Date: 2007/08/15

Revision 1.0

Epson Research and Development Page 27 Vancouver Design Center

9 Technical Support

9.1 EPSON Display Controllers (S1D13742)

Japan

Seiko Epson Corporation IC International Sales Group 421-8, Hino, Hino-shi Tokyo 191-8501, Japan Tel: 042-587-5812 Fax: 042-587-5564 http://www.epson.co.jp/

Hong Kong

Epson Hong Kong Ltd. 20/F., Harbour Centre 25 Harbour Road Wanchai, Hong Kong Tel: 2585-4600 Fax: 2827-4346 http://www.epson.com.hk/

9.2 Ordering Information

To order the S5U13742P00C100 Eva luation Board , contact t he Epson sal es represe ntative in your area and order part number S5U13742P00C100.

North America

Epson Electronics America, Inc. 2580 Orchard Parkway San Jose, CA 95131, USA Tel: (408) 922-0200 Fax: (408) 922-0238 http://www.eea.epson.com/

Europe

Epson Europe Electronics GmbH Riesstrasse 15 80992 Munich, Germany Tel: 089-14005-0 Fax: 089-14005-110 http://www.epson-electronics.de/

Taiwan

Epson Taiwan Technology & Trading Ltd. 14F, No. 7 Song Ren Road Taipei 110, Taiwan, ROC Tel: 02-8786-6688 Fax: 02-8786-6677 http://www.epson.com.tw/

Singapore

Epson Singapore Pte Ltd 1 HarbourFront Place #03-02 HarbourFront Tower O ne Singapore, 098633 Tel: (65) 6586-5500 Fax: (65) 6271-3182 http://www.epson.com.sg/

S5U13742P00C100 Evaluation Board User Manual S1D13742 Issue Date: 2007/08/15 X63A-G-002-01

Revision 1.0

Page 28 Epson Research and Development

Vancouver Design Center

Change Record

X63A-G-002-01 Revision 1.0 - Issued: August 15, 2007

• section 5, changed C26 from 0.01uF part to 0.1uF part (changed from item 2 to item 1)

• section 5, changed item 24 (R5) from 1.5k 1% to 150k 1%

• section 6, updated schematic 2 of 3 with updated values for C26 and R5

X63A-G-002-00 Revision 0.02 - Issued: June 26, 2007

• removed section 4.5.3

X63A-G-002-00 Revision 0.01 - Issued: June 25, 2007

• minor editing

• section 5, added parts list

• section 6, added schematics

• section 7, added board layout

S1D13742 S5U13742P00C100 Evaluation Board User Manual X63A-G-002-01 Issue Date: 2007/08/15

Revision 1.0

EPSON S1D13742 User Guide

Specifications and Main Features

Frequently Asked Questions

User Manual

Table of Contents

1 Introduction

2 Features

3 Installation and Configuration

3.1 Configuration DIP Switch

Table 3-1: Summary of Power-On/Reset Options

Figure 3-1: Configuration DIP Switch (SW1) Location

3.2 Configuration Jumpers

Figure 3-2: Configuration Jumper Locations (JP1, JP2, JP3, JP5)

Figure 3-3: Configuration Jumper Location (JP4)

Figure 3-4: Configuration Jumper Location (JP6)

4 Technical Description

4.1 Power

4.1.1 Power Requirements

4.1.2 Voltage Regulators

4.1.3 S1D13742 Power

4.2 Clocks

4.3 Reset

4.4 Power Save

4.5 Host Interface

4.5.1 Direct Host Bus Interface Support

Figure 4-1: Host Bus Connector Location (H1)

4.5.2 Connecting to the Epson S5U13U00P00C100 USB Adapter Board

Figure 4-2: USB Adapter Connector Locations (P1 and P2)

4.6 LCD Panel Interface

Figure 4-3: LCD Panel Connectors Location (H2, H3)

4.7 GPIO Connections

Figure 4-4: GPIO Connector Location (H4)

5 Parts List

Table 5-1: Parts List

6 Schematic Diagrams

Figure 6-1: S5U13742P00C100 Schematics (1 of 3)

Figure 6-2: S5U13742P00C100 Schematics (2 of 3)

Figure 6-3: S5U13742P00C100 Schematics (3 of 3)

7 Board Layout

Figure 7-1: S5U13742P00C100 Board Layout - Top View

Figure 7-2: S5U13742P00C100 Board Layout - Bottom View

8 References

8.1 Documents

8.2 Document Sources

9 Technical Support

9.1 EPSON Display Controllers (S1D13742)

9.2 Ordering Information

Change Record