EPSON S1D13706 service manual

S1D13706

S1D13706 Embedded Memory LCD Controller

Hardware Functional Specification

Document Number: X31B-A-001-09

Copyright © 1999, 2004 Epson Research and Development, Inc. All Rights Reserved.

Information in this document is subject to change without notice. You may download and use this document, but only for your own use in evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any representation that the contents of this document are accurate or current. The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws.

EPSON is a registered trademark of Seiko Epson Corporation. All other Trademarks are the property of their respective owners

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S1D13706	Hardware Functional Specification
X31B-A-001-09	Issue Date: 2004/02/09

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Table of Contents

1	Introduction . . . . . . . . . . . . . . . . .		. . . . . . . . . . . . . . . . . . .	. .	.	11
	1.1	Scope . . . . . . . . . . . . . . .	. . . . . . . . . . . . . . . .	. .	.	11
	1.2	Overview Description . . . . . . . .	. . . . . . . . . . . . . . . .	. .	.	11
2	Features . . . . . . . . . . . . . . . . . . .		. . . . . . . . . . . . . . . . . . .	. .	.	12
	2.1	Integrated Frame Buffer . . . . . . .	. . . . . . . . . . . . . . . .	. .	.	12
	2.2	CPU Interface . . . . . . . . . . .	. . . . . . . . . . . . . . . .	. .	.	12
	2.3	Display Support . . . . . . . . . . .	. . . . . . . . . . . . . . . .	. .	.	12
	2.4	Display Modes . . . . . . . . . . .	. . . . . . . . . . . . . . . .	. .	.	13
	2.5	Display Features . . . . . . . . . .	. . . . . . . . . . . . . . . .	. .	.	13
	2.6	Clock Source . . . . . . . . . . . .	. . . . . . . . . . . . . . . .	. .	.	13
	2.7	Miscellaneous . . . . . . . . . . .	. . . . . . . . . . . . . . . .	. .	.	13
3	Typical System Implementation Diagrams		. . . . . . . . . . . . . . . . . . .	. .	.	14
4	Pins . . . . . . . . . . . . . . . . . . . . .		. . . . . . . . . . . . . . . . . . .	. .	.	18
	4.1	Pinout Diagram - TQFP15 - 100pin . . .	. . . . . . . . . . . . . . . .	. .	.	18
	4.2	Pinout Diagram - Die Form . . . . . .	. . . . . . . . . . . . . . . .	. .	.	19
	4.3	Pin Descriptions . . . . . . . . . .	. . . . . . . . . . . . . . . .	. .	.	21
		4.3.1 Host Interface . . . . . . . . . . . .	. . . . . . . . . . . . . . . . . . . . .	. .	. .	21

4.3.2LCD Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

4.3.3 Clock Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

4.3.4Miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

		4.3.5 Power And Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	27
	4.4	Summary of Configuration Options . . . . . . . . . . . . . . . . . . . . . .	28
	4.5	Host Bus Interface Pin Mapping . . . . . . . . . . . . . . . . . . . . . . .	29
	4.6	LCD Interface Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . .	30
5	D.C. Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		31
6	A.C. Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		32
	6.1	Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	32

6.1.1Input Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

6.1.2	Internal Clocks . . . . . . .	. . . . . . . . . . . . . . . . . . . . . . . . . . . . .	34
6.2 CPU Interface Timing . . . . .		. . . . . . . . . . . . . . . . . . . . . .	35
6.2.1	Generic #1 Interface Timing	. . . . . . . . . . . . . . . . . . . . . . . . . . . . .	35

6.2.2Generic #2 Interface Timing (e.g. ISA) . . . . . . . . . . . . . . . . . . . . . . . . 37

6.2.3	Hitachi SH-4 Interface Timing	. . . . . . . . . . . . . . . . . . . . . . . . . . . .	39
6.2.4	Hitachi SH-3 Interface Timing	. . . . . . . . . . . . . . . . . . . . . . . . . . . .	41

6.2.5Motorola MC68K #1 Interface Timing (e.g. MC68000) . . . . . . . . . . . . . . . 43

6.2.6Motorola MC68K #2 Interface Timing (e.g. MC68030) . . . . . . . . . . . . . . . 45

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6.2.7 Motorola REDCAP2 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . 47

6.2.8Motorola DragonBall Interface Timing with DTACK (e.g. MC68EZ328/MC68VZ328) 49

6.2.9Motorola DragonBall Interface Timing w/o DTACK (e.g. MC68EZ328/MC68VZ328) 51

6.3 LCD Power Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . .54

6.3.1Passive/TFT Power-On Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

6.3.2Passive/TFT Power-Off Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

6.4 Display Interface . . . . . . . . . . . . . .		. . . . . . . . . . . . . . .	.56
6.4.1	Generic STN Panel Timing . . . . . . . . .	. . . . . . . . . . . . . . . . . . . . . 58
6.4.2	Single Monochrome 4-Bit Panel Timing . .	. . . . . . . . . . . . . . . . . . . . . 60
6.4.3	Single Monochrome 8-Bit Panel Timing . .	. . . . . . . . . . . . . . . . . . . . . 62
6.4.4	Single Color 4-Bit Panel Timing . . . . . .	. . . . . . . . . . . . . . . . . . . . . 64
6.4.5 Single Color 8-Bit Panel Timing (Format 1)		. . . . . . . . . . . . . . . . . . . . . 66
6.4.6 Single Color 8-Bit Panel Timing (Format 2)		. . . . . . . . . . . . . . . . . . . . .	68

6.4.7Single Color 16-Bit Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

6.4.8	Generic TFT Panel Timing . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . .	72
6.4.9	9/12/18-Bit TFT Panel Timing . . . . . . . . . . . . . . . . . . . .	. . . . . . . .	73
6.4.10	160x160 Sharp ‘Direct’ HR-TFT Panel Timing (e.g. LQ031B1DDxx)	. . . . . . .	76

6.4.11320x240 Sharp ‘Direct’ HR-TFT Panel Timing (e.g. LQ039Q2DS01) . . . . . . . . 80

6.4.12160x240 Epson D-TFD Panel Timing (e.g. LF26SCR) . . . . . . . . . . . . . . . . 82

6.4.13320x240 Epson D-TFD Panel Timing (e.g. LF37SQR) . . . . . . . . . . . . . . . . 86

7 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90

7.1 Clock Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . .	.90
7.1.1 BCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	90

7.1.2MCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

7.1.3 PCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

7.1.4PWMCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

7.2	Clock Selection . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . .93
7.3	Clocks versus Functions . . . . . . . . . . . . . . . . . . . . . . .	. . . .94
8 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. . . .95
8.1	Register Mapping . . . . . . . . . . . . . . . . . . . . . . . . .	. . . .95
8.2	Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . .95
8.3	Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . .	. . . .96

8.3.1Read-Only Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 96

8.3.2	Clock Configuration Registers	. . . . . . . . . . . . . . . . . . . . . . . . . . . .	97
8.3.3	Look-Up Table Registers . .	. . . . . . . . . . . . . . . . . . . . . . . . . . . . .	99

8.3.4Panel Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101

8.3.5Display Mode Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109

8.3.6 Picture-in-Picture Plus (PIP+) Registers . . . . . . . . . . . . . . . . . . . . . . .115

8.3.7Miscellaneous Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120

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8.3.8General IO Pins Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

8.3.9Pulse Width Modulation (PWM) Clock and Contrast Voltage (CV) Pulse Configuration Registers 126

9	Frame Rate Calculation . . .		. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
10	Display Data Formats . . . .		. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
11	Look-Up Table Architecture .		. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
	11.1	Monochrome Modes . . .	. . . . . . . . . . . . . . .	. . . . . .	. . . . 132
	11.2	Color Modes . . . . . .	. . . . . . . . . . . . . . .	. . . . . .	. . . . 134
12	SwivelView™ . . . . . . . . .		. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
	12.1	Concept . . . . . . . .	. . . . . . . . . . . . . . .	. . . . . .	. . . . 138
	12.2	90° SwivelView™ . . .	. . . . . . . . . . . . . . .	. . . . . .	. . . . 138
	12.2.1 Register Programming		. . . . . . . . . . . . . . . . . . .	. . . . . . . .	. . . . . 139
	12.3	180° SwivelView™ . . .	. . . . . . . . . . . . . . .	. . . . . .	. . . . 140
	12.3.1 Register Programming		. . . . . . . . . . . . . . . . . . .	. . . . . . . .	. . . . . 140
	12.4	270° SwivelView™ . . .	. . . . . . . . . . . . . . .	. . . . . .	. . . . 141
	12.4.1 Register Programming		. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
13	Picture-in-Picture Plus (PIP+)		. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
	13.1	Concept . . . . . . . .	. . . . . . . . . . . . . . .	. . . . . .	. . . . 143
	13.2	With SwivelView Enabled	. . . . . . . . . . . . . . .	. . . . . .	. . . . 144

13.2.1SwivelView 90° . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

13.2.2SwivelView 180° . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

13.2.3SwivelView 270° . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

14	Big-Endian Bus Interface . . .	. . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
	14.1 Byte Swapping Bus Data . . .	. . . . . . . . . . . . . . . . . . . . . . . 146
	14.1.1 16 Bpp Color Depth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
	14.1.2 1/2/4/8 Bpp Color Depth	. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
15	Power Save Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
16	Mechanical Data . . . . . . . .	. . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
17	References . . . . . . . . . . .	. . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
18	Sales and Technical Support .	. . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

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	List of Tables
Table 4-1:	Pinout Assignments - Die Form (S1D13706D00A) . . . . . . . . . . . . . . . . . . . .	20
Table 4-2:	Host Interface Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	21
Table 4-3:	LCD Interface Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	25
Table 4-4:	Clock Input Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	27
Table 4-5:	Miscellaneous Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	27
Table 4-6:	Power And Ground Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . .	27
Table 4-7:	Summary of Power-On/Reset Options . . . . . . . . . . . . . . . . . . . . . . . . . . .	28
Table 4-8:	Host Bus Interface Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	29
Table 4-9:	LCD Interface Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	30
Table 5-1:	Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	31
Table 5-2:	Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . .	31
Table 5-3:	Electrical Characteristics for VDD = 3.3V typical. . . . . . . . . . . . . . . . . . . . .	31
Table 6-1:	Clock Input Requirements for CLKI when CLKI to BCLK divide > 1 . . . . . . . . . .	32
Table 6-2:	Clock Input Requirements for CLKI when CLKI to BCLK divide = 1 . . . . . . . . . .	33
Table 6-3:	Clock Input Requirements for CLKI2 . . . . . . . . . . . . . . . . . . . . . . . . . . .	33
Table 6-4:	Internal Clock Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	34
Table 6-5:	Generic #1 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	36
Table 6-6:	Generic #2 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	38
Table 6-7:	Hitachi SH-4 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	40
Table 6-8:	Hitachi SH-3 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	42
Table 6-9: Motorola MC68K #1 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . .		44
Table 6-10: Motorola MC68K #2 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . .		46
Table 6-11: Motorola REDCAP2 Interface Timing. . . . . . . . . . . . . . . . . . . . . . . . . . .		48
Table 6-12: Motorola DragonBall Interface with DTACK Timing . . . . . . . . . . . . . . . . . . .		50
Table 6-13: Motorola DragonBall Interface without DTACK Timing . . . . . . . . . . . . . . . . .		52
Table 6-14: Passive/TFT Power-On Sequence Timing . . . . . . . . . . . . . . . . . . . . . . . . .		54
Table 6-15: Passive/TFT Power-Off Sequence Timing. . . . . . . . . . . . . . . . . . . . . . . . .		55
Table 6-16: Panel Timing Parameter Definition and Register Summary . . . . . . . . . . . . . . . .		57
Table 6-17: Single Monochrome 4-Bit Panel A.C. Timing . . . . . . . . . . . . . . . . . . . . . . .		61
Table 6-18: Single Monochrome 8-Bit Panel A.C. Timing . . . . . . . . . . . . . . . . . . . . . . .		63
Table 6-19: Single Color 4-Bit Panel A.C. Timing . . . . . . . . . . . . . . . . . . . . . . . . . . .		65
Table 6-20: Single Color 8-Bit Panel A.C. Timing (Format 1) . . . . . . . . . . . . . . . . . . . . .		67
Table 6-21: Single Color 8-Bit Panel A.C. Timing (Format 2) . . . . . . . . . . . . . . . . . . . . .		69
Table 6-22: Single Color 16-Bit Panel A.C. Timing . . . . . . . . . . . . . . . . . . . . . . . . . .		71
Table 6-23: TFT A.C. Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		75
Table 6-24:	160x160 Sharp ‘Direct’ HR-TFT Horizontal Timing . . . . . . . . . . . . . . . . . . .	77
Table 6-25:	160x160 Sharp ‘Direct’ HR-TFT Panel Vertical Timing . . . . . . . . . . . . . . . . .	79

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Table 6-26:	320x240	Sharp ‘Direct’ HR-TFT Panel Horizontal Timing . . . . . . . . . . . . . . . .		81
Table 6-27:	320x240	Sharp ‘Direct’ HR-TFT Panel Vertical Timing . . . . . . . . . . . . . . . . .		81
Table 6-28:	160x240	Epson D-TFD Panel Horizontal Timing . . . . . . . . . . . . . . . . . . . . .		83
Table 6-29:	160x240	Epson D-TFD Panel GCP Horizontal Timing . . . . . . . . . . . . . . . . . .		84
Table 6-30:	160x240	Epson D-TFD Panel Vertical Timing . . . . . . . . . . . . . . . . . . . . . .		85
Table 6-31:	320x240	Epson D-TFD Panel Horizontal Timing . . . . . . . . . . . . . . . . . . . . .		87
Table 6-32:	320x240	Epson D-TFD Panel GCP Horizontal Timing . . . . . . . . . . . . . . . . . .		88
Table 6-33:	320x240	Epson D-TFD Panel Vertical Timing . . . . . . . . . . . . . . . . . . . . . .		89
Table 7-1:	BCLK Clock Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Table 7-2:	MCLK Clock Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Table 7-3:	PCLK Clock Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Table 7-4:	Relationship between MCLK and PCLK. . . . . . . . . . . . . . . . . . . . . . . . . .			92
Table 7-5:	PWMCLK Clock Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Table 7-6:	S1D13706 Internal Clock Requirements . . . . . . . . . . . . . . . . . . . . . . . . . .			94
Table 8-1:	S1D13706 Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Table 8-2:	MCLK Divide Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Table 8-3:	PCLK Divide Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Table 8-4:	PCLK Source Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Table 8-5:	Panel Data Width Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102
Table 8-6:	Active Panel Resolution Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102
Table 8-7:	LCD Panel Type Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102
Table 8-8:	Inverse Video Mode Select Options . . . . . . . . . . . . . . . . . . . . . . . . . . . .110
Table 8-9:	LCD Bit-per-pixel Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111
Table 8-10:	SwivelViewTM Mode Select Options . . . . . . . . . . . . . . . . . . . . . . . . . . .112
Table 8-11:	32-bit Address Increments for Color Depth		. . . . . . . . . . . . . . . . . . . . . . . .116
Table 8-12:	32-bit Address Increments for Color Depth		. . . . . . . . . . . . . . . . . . . . . . . .117
Table 8-13:	32-bit Address Increments for Color Depth		. . . . . . . . . . . . . . . . . . . . . . . .118
Table 8-14:	32-bit Address Increments for Color Depth		. . . . . . . . . . . . . . . . . . . . . . . .119
Table 8-15:	PWM Clock Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126
Table 8-16:	CV Pulse Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127
Table 8-17:	PWM Clock Divide Select Options . . . . . . . . . . . . . . . . . . . . . . . . . . . .128
Table 8-18:	CV Pulse Divide Select Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128
Table 8-19:	PWMOUT Duty Cycle Select Options . . . . . . . . . . . . . . . . . . . . . . . . . . .129
Table 15-1:	Power Save Mode Function Summary . . . . . . . . . . . . . . . . . . . . . . . . . . .149

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	List of Figures
Figure 3-1:	Typical System Diagram (Generic #1 Bus)	. . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 3-2:	Typical System Diagram (Generic #2 Bus)	. . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 3-3:	Typical System Diagram (Hitachi SH-4 Bus)		. . . . . . . . . . . . . . . . . . . . . . . 15
Figure 3-4:	Typical System Diagram (Hitachi SH-3 Bus)		. . . . . . . . . . . . . . . . . . . . . . . 15
Figure 3-5:	Typical System Diagram (MC68K # 1, Motorola 16-Bit 68000) . . . . . . . . . . . . . 16
Figure 3-6:	Typical System Diagram (MC68K #2, Motorola 32-Bit 68030) . . . . . . . . . . . . . . 16
Figure 3-7:	Typical System Diagram (Motorola REDCAP2 Bus) . . . . . . . . . . . . . . . . . . . 17
Figure 3-8:	Typical System Diagram (Motorola MC68EZ328/MC68VZ328 “DragonBall” Bus) . . . 17
Figure 4-1:	Pinout Diagram - TQFP15 - 100pin (S1D13706F00A) . . . . . . . . . . . . . . . . . . 18
Figure 4-2:	Pinout Diagram - Die Form (S1D13706D00A) . . . . . . . . . . . . . . . . . . . . . . 19
Figure 6-1:	Clock Input Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 6-2:	Generic #1 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 6-3:	Generic #2 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 6-4:	Hitachi SH-4 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 6-5:	Hitachi SH-3 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 6-6:	Motorola MC68K #1 Interface Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 6-7:	Motorola MC68K #2 Interface Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 6-8:	Motorola REDCAP2 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 6-9:	Motorola DragonBall Interface with DTACK Timing . . . . . . . . . . . . . . . . . . . 49
Figure 6-10:	Motorola DragonBall Interface without DTACK# Timing . . . . . . . . . . . . . . . . 51
Figure 6-11:	Passive/TFT Power-On Sequence Timing . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 6-12:	Passive/TFT Power-Off Sequence Timing . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 6-13:	Panel Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 6-14:	Generic STN Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 6-15:	Single Monochrome 4-Bit Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Figure 6-16:	Single Monochrome 4-Bit Panel A.C. Timing . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 6-17:	Single Monochrome 8-Bit Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Figure 6-18:	Single Monochrome 8-Bit Panel A.C. Timing . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 6-19:	Single Color 4-Bit Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Figure 6-20:	Single Color 4-Bit Panel A.C. Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Figure 6-21:	Single Color 8-Bit Panel Timing (Format 1) . . . . . . . . . . . . . . . . . . . . . . . . 66
Figure 6-22:	Single Color 8-Bit Panel A.C. Timing (Format 1) . . . . . . . . . . . . . . . . . . . . . 67
Figure 6-23:	Single Color 8-Bit Panel Timing (Format 2) . . . . . . . . . . . . . . . . . . . . . . . . 68
Figure 6-24:	Single Color 8-Bit Panel A.C. Timing (Format 2) . . . . . . . . . . . . . . . . . . . . . 69
Figure 6-25:	Single Color 16-Bit Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Figure 6-26:	Single Color 16-Bit Panel A.C. Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Figure 6-27:	Generic TFT Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

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Figure 6-28:	18-Bit TFT Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
Figure 6-29:	TFT A.C. Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
Figure 6-30:	160x160		Sharp ‘Direct’ HR-TFT Panel Horizontal Timing . . . . . . . . . . . . . . . .76
Figure 6-31:	160x160		Sharp ‘Direct’ HR-TFT Panel Vertical Timing. . . . . . . . . . . . . . . . . .78
Figure 6-32:	320x240		Sharp ‘Direct’ HR-TFT Panel Horizontal Timing . . . . . . . . . . . . . . . .80
Figure 6-33:	320x240		Sharp ‘Direct’ HR-TFT Panel Vertical Timing. . . . . . . . . . . . . . . . . .81
Figure 6-34:	160x240		Epson D-TFD Panel Horizontal Timing . . . . . . . . . . . . . . . . . . . . .82
Figure 6-35:	160x240		Epson D-TFD Panel GCP Horizontal Timing . . . . . . . . . . . . . . . . . .84
Figure 6-36:	160x240		Epson D-TFD Panel Vertical Timing . . . . . . . . . . . . . . . . . . . . . . .85
Figure 6-37:	320x240		Epson D-TFD Panel Horizontal Timing . . . . . . . . . . . . . . . . . . . . .86
Figure 6-38:	320x240		Epson D-TFD Panel GCP Horizontal Timing . . . . . . . . . . . . . . . . . .88
Figure 6-39:	320x240		Epson D-TFD Panel Vertical Timing . . . . . . . . . . . . . . . . . . . . . . .89
Figure 7-1:	Clock Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
Figure 8-1:	Display Data Byte/Word Swap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Figure 8-2:	PWM Clock/CV Pulse Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Figure 10-1:	4/8/16 Bit-Per-Pixel Display Data Memory Organization . . . . . . . . . . . . . . . . 131
Figure 11-1:	1	Bit-per-pixel Monochrome Mode Data Output Path . . . . . . . . . . . . . . . . . . 132
Figure 11-2:	2	Bit-per-pixel Monochrome Mode Data Output Path . . . . . . . . . . . . . . . . . . 132
Figure 11-3:	4	Bit-per-pixel Monochrome Mode Data Output Path . . . . . . . . . . . . . . . . . . 133
Figure 11-4:	8	Bit-per-pixel Monochrome Mode Data Output Path . . . . . . . . . . . . . . . . . . 133
Figure 11-5:	1	Bit-Per-Pixel Color Mode Data Output Path . . . . . . . . . . . . . . . . . . . . . . 134
Figure 11-6:	2	Bit-Per-Pixel Color Mode Data Output Path . . . . . . . . . . . . . . . . . . . . . . 135
Figure 11-7:	4	Bit-Per-Pixel Color Mode Data Output Path . . . . . . . . . . . . . . . . . . . . . . 136

Figure 11-8: 8 Bit-per-pixel Color Mode Data Output Path . . . . . . . . . . . . . . . . . . . . . . 137 Figure 12-1: Relationship Between The Screen Image and the Image Refreshed in 90× SwivelView. 138 Figure 12-2: Relationship Between The Screen Image and the Image Refreshed in 180× SwivelView.140 Figure 12-3: Relationship Between The Screen Image and the Image Refreshed in 270× SwivelView.141 Figure 13-1: Picture-in-Picture Plus with SwivelView disabled . . . . . . . . . . . . . . . . . . . . 143 Figure 13-2: Picture-in-Picture Plus with SwivelView 90° enabled . . . . . . . . . . . . . . . . . . 144

Figure 13-3:	Picture-in-Picture Plus with SwivelView 180° enabled	. . . . . . . . .	. . . .	. .	.	. 144
Figure 13-4:	Picture-in-Picture Plus with SwivelView 270° enabled	. . . . . . . . .	. . . .	. .	.	. 145

Figure 14-1: Byte-swapping for 16 Bpp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 Figure 14-2: Byte-swapping for 1/2/4/8 Bpp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 Figure 16-1: Mechanical Data 100pin TQFP15 (S1D13706F00A) . . . . . . . . . . . . . . . . . . 150

S1D13706	Hardware Functional Specification
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1 Introduction

1.1 Scope

This is the Hardware Functional Specification for the S1D13706 Embedded Memory LCD Controller. Included in this document are timing diagrams, AC and DC characteristics, register descriptions, and power management descriptions. This document is intended for two audiences: Video Subsystem Designers and Software Developers.

For additional documentation related to the S1D13706 see Section 17, “References” on page 151.

This document is updated as appropriate. Please check the Epson Research and Development Website at www.erd.epson.com for the latest revision of this document before beginning any development.

We appreciate your comments on our documentation. Please contact us via email at [e-mail].

1.2 Overview Description

The S1D13706 is a color/monochrome LCD graphics controller with an embedded 80K byte SRAM display buffer. While supporting all other panel types, the S1D13706 is the only LCD controller to directly interface to both the Epson D-TFD and the Sharp HR-TFT family of products thus removing the requirement of an external Timing Control IC. This high level of integration provides a low cost, low power, single chip solution to meet the demands of embedded markets such as Mobile Communications devices and Palm-size PCs, where board size and battery life are major concerns.

The S1D13706 utilizes a guaranteed low-latency CPU architecture providing support for microprocessors without READY/WAIT# handshaking signals. The 32-bit internal data path provides high performance bandwidth into display memory allowing for fast screen updates.

Products requiring a rotated display image can take advantage of the SwivelView TM feature which provides hardware rotation of the display memory transparent to the software application. The S1D13706 also provides support for “Picture-in-Picture Plus” (a variable size Overlay window).

The S1D13706 provides impressive support for Palm OS handhelds, however its impartiality to CPU type or operating system makes it an ideal display solution for a wide variety of applications.

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2 Features

2.1Integrated Frame Buffer

•Embedded 80K byte SRAM display buffer.

2.2CPU Interface

•Direct support of the following interfaces: Generic MPU bus interface using WAIT# signal. Hitachi SH-3.

Hitachi SH-4. Motorola M68K.

Motorola MC68EZ328/MC68VZ328 DragonBall. Motorola “REDCAP2” - no WAIT# signal.

•8-bit processor support with “glue logic”.

•“Fixed” low-latency CPU access times.

•Registers are memory-mapped - M/R# input selects between memory and register address space.

•The complete 80K byte display buffer is directly and contiguously available through the 17-bit address bus.

•Single level CPU write buffer.

2.3Display Support

•Single-panel, single-drive passive displays.

•4/8-bit monochrome LCD interface.

•4/8/16-bit color LCD interface.

•Active Matrix TFT interface.

•9/12/18-bit interface.

•‘Direct’ support for 18-bit Epson D-TFD interface.

•‘Direct’ support for 18-bit Sharp HR-TFT interface.

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2.4Display Modes

•1/2/4/8/16 bit-per-pixel (bpp) color depths.

•Up to 64 gray shades using Frame Rate Modulation (FRM) and dithering on monochrome passive LCD panels.

•Up to 64K colors on passive STN panels.

•Up to 64K colors on active matrix LCD panels.

•Example resolutions:

320x240 at a color depth of 8 bpp

160x160 at a color depth of 16 bpp

160x240 at a color depth of 16 bpp

2.5Display Features

•SwivelView™: 90°, 180°, 270° counter-clockwise hardware rotation of display image.

•“Picture-in-Picture Plus”: displays a variable size window overlaid over background image.

•Double Buffering/Multi-pages: provides smooth animation and instantaneous screen updates.

2.6Clock Source

•Two clock inputs: CLKI and CLKI2. It is possible to use one clock input only.

•Bus clock is derived from CLKI and can be internally divided by 2, 3, or 4.

•Memory clock is derived from bus clock. It can be internally divided by 2, 3, or 4.

•Pixel clock can be derived from CLKI, CLKI2, bus clock, or memory clock. It can be internally divided by 2, 3, 4, or 8.

2.7Miscellaneous

•Hardware/Software Video Invert.

•Software Power Save mode.

•General Purpose Input/Output pins are available.

•100-pin TQFP15 package.

•104-pin CFLGA package.

•Die form available.

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3 Typical System Implementation Diagrams

				.
				Oscillator
	Generic #1
	BUS	HIOVDD		CLKI2
			BS#			16-bit
	A[27:17]	Decoder	M/R#	FPDAT[15:0]	D[15:0]	Single
				FPFRAME	FPFRAME	LCD
	CSn#		CS#			Display
				FPLINE	FPLINE	Power
	A[16:1]		AB[16:1]	FPSHIFT	FPSHIFT
	D[15:0]		DB[15:0]	DRDY	MOD	Bias
	WE0#			S1D13706
			WE0#
	WE1#		WE1#	GPO
	RD0#		RD#
	RD1#		RD/WR#
	WAIT#		WAIT#
	BUSCLK		CLKI
	RESET#		RESET#
			AB0
		VSS

Figure 3-1: Typical System Diagram (Generic #1 Bus)

				.
				Oscillator
	Generic #2
	BUS		VDD
				CLKI2
			BS#			9-bit
			RD/WR#
				FPDAT[8:0]	D[8:0]
						TFT
	A[27:17]		M/R#
		Decoder		FPFRAME	FPFRAME Display
	CSn#		CS#	FPLINE	FPLINE	Power
	A[16:0]		AB[16:0]	FPSHIFT	FPSHIFT
	D[15:0]		DB[15:0]	DRDY	DRDY	Bias
	WE#			S1D13706
			WE0#
	BHE#		WE1#	GPO
	RD#		RD#
	WAIT#		WAIT#
	BUSCLK		CLKI
	RESET#		RESET#

Figure 3-2: Typical System Diagram (Generic #2 Bus)

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			.
			Oscillator
SH-4
BUS
A[25:17]	Decoder	M/R#	CLKI2	FPDAT15	D11	12-bit
				FPDAT12	D10	TFT
						Display
CSn#		CS#		FPDAT[9:0]	D[9:0]
A[16:1]		AB[16:1]		FPFRAME	FPFRAME
				FPLINE	FPLINE
D[15:0]		DB[15:0]				Power
				FPSHIFT
WE0#		WE0#			FPSHIFT
WE1#		WE1#	S1D13706	DRDY	DRDY	Bias
BS#		BS#
RD/WR#		RD/WR#		GPO
RD#		RD#
RDY#		WAIT#
CKIO		CLKI
RESET#		RESET#
		AB0
		VSS

Figure 3-3: Typical System Diagram (Hitachi SH-4 Bus)

			.
			Oscillator
SH-3
BUS
A[25:17]	Decoder	M/R#	CLKI2		18-bit
				D[17:0]	TFT
			FPDAT[17:0]
CSn#		CS#	FPFRAME	FPFRAME Display
A[16:1]		AB[16:1]	FPLINE	FPLINE	Power
D[15:0]		DB[15:0]
			FPSHIFT
WE0#		WE0#		FPSHIFT
			DRDY	DRDY	Bias
WE1#		WE1#
BS#		BS#	S1D13706
RD/WR#		RD/WR#	GPO
RD#		RD#
WAIT#		WAIT#
CKIO		CLKI
RESET#		RESET#
		AB0
		VSS

Figure 3-4: Typical System Diagram (Hitachi SH-3 Bus)

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			.
			Oscillator
MC68K #1
BUS	HIOVDD
			CLKI2
		RD#		FPDAT[17:0]	D[17:0]	18-bit
		WE0#
				FPFRAME	SPS	HR-TFT
A[23:17]
	Decoder	M/R#		FPLINE	LP	Display
FC0, FC1
				FPSHIFT	CLK
	Decoder	CS#		GPIO0	PS	Power
A[16:1]		AB[16:1]		GPIO1	CLS
				GPIO2	REV
D[15:0]		DB[15:0]				Bias
			S1D13706	GPIO3	SPL
LDS#		AB0
UDS#		WE1#		GPO
AS#		BS#
R/W#		RD/WR#
DTACK#		WAIT#
CLK		CLKI
RESET#		RESET#
	Figure 3-5: Typical System Diagram (MC68K # 1, Motorola 16-Bit 68000)

			.
			Oscillator
MC68K #2
BUS
A[31:17]	Decoder	M/R#	CLKI2	FPDAT[17:0]	D[17:0]	18-bit
FC0, FC1
				FPFRAME	DY
						D-TFD
	Decoder	CS#		FPLINE	LP	Display
				FPSHIFT	XSCL
A[16:0]		AB[16:0]
				DRDY	GCP
D[31:16]		DB[15:0]
				GPIO0	XINH
DS#		WE1#		GPIO1	YSCL
				GPIO2	FR	Power)
AS#
		BS#	S1D13706	GPIO3	FRS
R/W#		RD/WR#		GPIO4	RES
SIZ1		RD#		GPIO5	DD_P1	(Bias
				GPIO6	YSCLD
SIZ0		WE0#				XSET
DSACK1#		WAIT#
CLK		CLKI		GPO
RESET#		RESET#
	Figure 3-6: Typical System Diagram (MC68K #2, Motorola 32-Bit 68030)

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			.
			Oscillator
REDCAP2
BUS	HIOVDD		CLKI2
		BS#					4-bit
A[21:17]	Decoder	M/R#
				FPDAT[7:4]			Single
					D[3:0]
CSn		CS#		FPSHIFT	FPSHIFT		LCD
						Display
A[16:1]		AB[16:1]
							Power
D[15:0]		DB[15:0]		FPFRAME	FPFRAME
				FPLINE	FPLINE
				DRDY	MOD		Bias
			S1D13706
R/W		RD/WR#		GPO
OE		RD#
EB1		WE0#
EB0		WE1#
CLK		CLKI
RESET_OUT		RESET#
		AB0
	VSS
*Note: CSn# can be any of CS0-CS4

Figure 3-7: Typical System Diagram (Motorola REDCAP2 Bus)

				.
				Oscillator
	MC68EZ328/
	MC68VZ328
	DragonBall	HIOVDD		CLKI2
			BS#			8-bit
	BUS
						Single
			RD/WR#	FPDAT[7:0]	D[7:0]
	A[25:17]	Decoder	M/R#	FPSHIFT	FPSHIFT	LCD
						Display
	CSX		CS#	FPFRAME	FPFRAME	Power
	A[16:1]		AB[16:1]	FPLINE	FPLINE
				DRDY	MOD	Bias
	D[15:0]		DB[15:0]
				S1D13706
	LWE		WE0#	GPO
	UWE		WE1#
	OE		RD#
	DTACK		WAIT#
	CLKO		CLKI
	RESET		RESET#
			AB0
		VSS

Figure 3-8: Typical System Diagram (Motorola MC68EZ328/MC68VZ328 “DragonBall” Bus)

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4 Pins

4.1 Pinout Diagram - TQFP15 - 100pin

					75
				VSS
	76		NIOVDD
		77
			CLKI2
	78
			CNF7
		79
			CNF6
		80
			CNF5
	81
			CNF4
	82
			CNF3
	83
			CNF2
	84
			CNF1
	85
			CNF0
	86
			TESTEN
	87
			AB16
	88
			AB15
	89
			AB14
	90
			AB13
	91
			AB12
	92
			AB11
	93
			AB10
	94
			AB9
	95
			AB8
	96
			AB7
	97
			AB6
	98
			AB5
	99
			AB4	COREVDD
	100
			VSS
					1

		74		73		72			71		70		69
FPDAT17		FPDAT16			FPDAT15		FPDAT14		FPDAT13			FPDAT12

AB3		AB2		AB1		AB0		CS#		M/R#
			3		4		5		6		7
	2

68

FPDAT11

BS#

8

67

FPDAT10

RD#

9

	66			65		64		63			62		61		60		59
FPDAT9		FPDAT8		FPDAT7			NIOVDD		VSS		FPDAT6			FPDAT5		FPDAT4

S1D13706

WE0#		WE1#		RD/WR#		RESET#		VSS		CLKI		HIOVDD		WAIT#
			11		12		13		14		15		16		17
	10

58

FPDAT3

18 DB15

	57		56
FPDAT2		FPDAT1

DB14		DB13
			20
	19

55

FPDAT0

21 DB12

	54		53
FPSHIFT		FPLINE

DB11		DB10
			23
	22

	52			51
FPFRAME		COREVDD		VSS
		NIOVDD
				DRDY
				GPO
			CVOUT
				GPIO0
				GPIO1
				GPIO2
				GPIO3
				GPIO4
				GPIO5
				GPIO6
	PWMOUT
		NIOVDD
				VSS
				DB0
				DB1
				DB2
				DB3
				DB4
				DB5
				DB6
				DB7
				DB8
		HIOVDD
DB9		VSS
				25
	24

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

Figure 4-1: Pinout Diagram - TQFP15 - 100pin (S1D13706F00A)

Note

Package type: 100 pin surface mount TQFP15

S1D13706	Hardware Functional Specification
X31B-A-001-09	Issue Date: 2004/02/09

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4.2 Pinout Diagram - Die Form

	170	165	160	155	150	145	140	135	130	125	120
175
DIE No. X5534D										Unusable Pad
180											115
185											110
190											105
195						Y					100
200											95
205											90
								X
210											85
						(0,0)
215											80
220											75
225											70
230											65
235											60
Unusable Pad
1	5	10	15	20	25	30	35	40	45	50	55

Figure 4-2: Pinout Diagram - Die Form (S1D13706D00A)

Chip Size: 5.88 x 6.55 mm

PAD size: 68 x 68 m

Hardware Functional Specification	S1D13706
Issue Date: 2004/02/09	X31B-A-001-09

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Table 4-1: Pinout Assignments - Die Form (S1D13706D00A)

	Pin No.		Pad No.		Pin Name		X ( m)		Y ( m)		Pin No.		Pad No.		Pin Name		X ( m)		Y ( m)
	1		1		LVDD		-2331		-3149		51		119		LVDD		2813		2667
	2		3		AB3		-2100		-3149		52		122		FPFRAME		2100		3149
	3		5		AB2		-1932		-3149		53		124		FPLINE		1932		3149
	4		8		AB1		-1680		-3149		54		127		FPSHIFT		1680		3149
	5		10		AB0		-1512		-3149		55		129		FPDAT0		1512		3149
	6		12		CS#		-1344		-3149		56		131		FPDAT1		1344		3149
	7		15		M/R#		-1092		-3149		57		134		FPDAT2		1092		3149
	8		17		BS#		-924		-3149		58		136		FPDAT3		924		3149
	9		20		RD#		-672		-3149		59		139		FPDAT4		672		3149
	10		22		WE0#		-504		-3149		60		141		FPDAT5		504		3149
	11		24		WE1#		-336		-3149		61		143		FPDAT6		336		3149
	12		27		RD/WR#		-84		-3149		62		146		VSS		84		3149
	13		29		RESET#		84		-3149		63		148		HVDD		-84		3149
	14		31		VSS		252		-3149		64		150		FPDAT7		-252		3149
	15		34		CLKI		504		-3149		65		153		FPDAT8		-504		3149
	16		36		HVDD		672		-3149		66		155		FPDAT9		-672		3149
	17		39		WAIT#		924		-3149		67		158		FPDAT10		-924		3149
	18		41		DB15		1092		-3149		68		160		FPDAT11		-1092		3149
	19		43		DB14		1260		-3149		69		162		FPDAT12		-1260		3149
	20		46		DB13		1512		-3149		70		165		FPDAT13		-1512		3149
	21		48		DB12		1680		-3149		71		167		FPDAT14		-1680		3149
	22		50		DB11		1848		-3149		72		169		FPDAT15		-1848		3149
	23		53		DB10		2100		-3149		73		172		FPDAT16		-2100		3149
	24		55		DB9		2331		-3149		74		174		FPDAT17		-2331		3149
	25		58		VSS		2813		-2478		75		177		VSS		-2813		2478
	26		60		HVDD		2813		-2310		76		179		HVDD		-2813		2310
	27		62		DB8		2813		-2142		77		181		CLKI2		-2813		2142
	28		65		DB7		2813		-1890		78		184		CNF7		-2813		1890
	29		67		DB6		2813		-1722		79		186		CNF6		-2813		1722
	30		70		DB5		2813		-1470		80		189		CNF5		-2813		1470
	31		72		DB4		2813		-1302		81		191		CNF4		-2813		1302
	32		74		DB3		2813		-1134		82		193		CNF3		-2813		1134
	33		77		DB2		2813		-882		83		196		CNF2		-2813		882
	34		79		DB1		2813		-714		84		198		CNF1		-2813		714
	35		81		DB0		2813		-546		85		200		CNF0		-2813		546
	36		84		VSS		2813		-294		86		203		TESTEN		-2813		294
	37		86		HVDD		2813		-126		87		205		AB16		-2813		126
	38		89		PWMOUT		2813		126		88		208		AB15		-2813		-126
	39		91		GPIO6		2813		294		89		210		AB14		-2813		-294
	40		93		GPIO5		2813		462		90		212		AB13		-2813		-462
	41		96		GPIO4		2813		714		91		215		AB12		-2813		-714
	42		98		GPIO3		2813		882		92		217		AB11		-2813		-882
	43		100		GPIO2		2813		1050		93		219		AB10		-2813		-1050
	44		103		GPIO1		2813		1302		94		222		AB9		-2813		-1302
	45		105		GPIO0		2813		1470		95		224		AB8		-2813		-1470
	46		108		CVOUT		2813		1722		96		227		AB7		-2813		-1722
	47		110		GPO		2813		1890		97		229		AB6		-2813		-1890
	48		112		DRDY		2813		2058		98		231		AB5		-2813		-2058
	49		115		HVDD		2813		2310		99		234		AB4		-2813		-2310
	50		117		VSS		2813		2478		100		236		VSS		-2813		-2478

S1D13706	Hardware Functional Specification
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4.3 Pin Descriptions

Key:

I	=	Input
O	=	Output
IO	=	Bi-Directional (Input/Output)
P	=	Power pin
LIS	=	LVTTLa Schmitt input
LI	=	LVTTL input
LB2A	= LVTTL IO buffer (6mA/-6mA@3.3V)
LB3P	= Low noise LVTTL IO buffer (12mA/-12mA@3.3V)
LO3	= Low noise LVTTL Output buffer (12mA/-12mA@3.3V)
LB3M	= Low noise LVTTL IO buffer with input mask (12mA/-12mA@3.3V)
T1	=	Test mode control input with pull-down resistor (typical value of 50Ω at 3.3V)
Hi-Z	=	High Impedance

a LVTTL is Low Voltage TTL (see Section 5, “D.C. Characteristics” on page 31).

4.3.1 Host Interface

Table 4-2: Host Interface Pin Descriptions

	Pin Name	Type	Pin #	Cell	IO	RESET#	Description
					Voltage	State
							This input pin has multiple functions.
							• For Generic #1, this pin is not used and should be connected
							to VSS.
							• For Generic #2, this pin inputs system address bit 0 (A0).
							• For SH-3/SH-4, this pin is not used and should be connected
							to VSS.
	AB0	I	5	LIS	HIOVDD	0	• For MC68K #1, this pin inputs the lower data strobe (LDS#).
							• For MC68K #2, this pin inputs system address bit 0 (A0).
							• For REDCAP2, this pin is not used and should be connected
							to VSS.
							• For DragonBall, this pin is not used and should be connected
							to VSS.
							See Table 4-8: “Host Bus Interface Pin Mapping,” on page 29 for
							summary.
	AB[16:1]	I	87-99,	LI	HIOVDD	0	System address bus bits 16-1.
			2-4

Hardware Functional Specification	S1D13706
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Table 4-2: Host Interface Pin Descriptions

	Pin Name	Type	Pin #	Cell	IO	RESET#	Description
					Voltage	State
							Input data from the system data bus.
							• For Generic #1, these pins are connected to D[15:0].
							• For Generic #2, these pins are connected to D[15:0].
							• For SH-3/SH-4, these pins are connected to D[15:0].
			18-24,				• For MC68K #1, these pins are connected to D[15:0].
	DB[15:0]	IO		LB2A	HIOVDD	Hi-Z	• For MC68K #2, these pins are connected to D[31:16] for a 32-
			27-35				bit device (e.g. MC68030) or D[15:0] for a 16-bit device (e.g.
							MC68340).
							• For REDCAP2, these pins are connected to D[15:0].
							• For DragonBall, these pins are connected to D[15:0].
							See Table 4-8: “Host Bus Interface Pin Mapping,” on page 29 for
							summary.
							This input pin has multiple functions.
							• For Generic #1, this pin inputs the write enable signal for the
							lower data byte (WE0#).
							• For Generic #2, this pin inputs the write enable signal (WE#)
							• For SH-3/SH-4, this pin inputs the write enable signal for data
							byte 0 (WE0#).
	WE0#	I	10	LIS	HIOVDD	1	• For MC68K #1, this pin must be tied to HIO VDD
							• For MC68K #2, this pin inputs the bus size bit 0 (SIZ0).
							• For REDCAP2, this pin inputs the byte enable signal for the
							D[7:0] data byte (EB1).
							• For DragonBall, this pin inputs the byte enable signal for the
							D[7:0] data byte (LWE).
							See Table 4-8: “Host Bus Interface Pin Mapping,” on page 29 for
							summary.
							This input pin has multiple functions.
							• For Generic #1, this pin inputs the write enable signal for the
							upper data byte (WE1#).
							• For Generic #2, this pin inputs the byte enable signal for the
							high data byte (BHE#).
							• For SH-3/SH-4, this pin inputs the write enable signal for data
							byte 1 (WE1#).
	WE1#	I	11	LIS	HIOVDD	1	• For MC68K #1, this pin inputs the upper data strobe (UDS#).
							• For MC68K #2, this pin inputs the data strobe (DS#).
							• For REDCAP2, this pin inputs the byte enable signal for the
							D[15:8] data byte (EB0).
							• For DragonBall, this pin inputs the byte enable signal for the
							D[15:8] data byte (UWE).
							See Table 4-8: “Host Bus Interface Pin Mapping,” on page 29 for
							summary.
	CS#	I	6	LI	HIOVDD	1	Chip select input. See Table 4-8: “Host Bus Interface Pin Mapping,”
							on page 29 for summary.
							This input pin is used to select between the display buffer and
							register address spaces of the S1D13706. M/R# is set high to
	M/R#	I	7	LIS	HIOVDD	0	access the display buffer and low to access the registers. See
							Table 4-8: “Host Bus Interface Pin Mapping,” on page 29 for
							summary.

S1D13706	Hardware Functional Specification
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Table 4-2: Host Interface Pin Descriptions

Pin Name

Type

Pin #

Cell

IO

RESET#

Description

Voltage

State

This input pin has multiple functions.

• For Generic #1, this pin must be tied to HIO VDD.

• For Generic #2, this pin must be tied to HIO VDD.

• For SH-3/SH-4, this pin inputs the bus start signal (BS#).

BS#

I

8

LIS

HIOVDD

1

• For MC68K #1, this pin inputs the address strobe (AS#).

• For MC68K #2, this pin inputs the address strobe (AS#).

• For REDCAP2, this pin must be tied to HIO VDD.

• For DragonBall, this pin must be tied to HIO VDD.

See Table 4-8: “Host Bus Interface Pin Mapping,” on page 29 for

summary.

This input pin has multiple functions.

• For Generic #1, this pin inputs the read command for the

upper data byte (RD1#).

• For Generic #2, this pin must be tied to HIO VDD.

• For SH-3/SH-4, this pin inputs the RD/WR# signal. The

RD/WR#

I

12

LIS

HIOVDD

1

S1D13706 needs this signal for early decode of the bus cycle.

• For MC68K #1, this pin inputs the R/W# signal.

• For MC68K #2, this pin inputs the R/W# signal.

• For REDCAP2, this pin inputs the R/W

signal.

• For DragonBall, this pin must be tied to HIO VDD.

See Table 4-8: “Host Bus Interface Pin Mapping,” on page 29 for

summary.

This input pin has multiple functions.

• For Generic #1, this pin inputs the read command for the

lower data byte (RD0#).

• For Generic #2, this pin inputs the read command (RD#).

• For SH-3/SH-4, this pin inputs the read signal (RD#).

RD#

I

9

LIS

HIOVDD

1

• For MC68K #1, this pin must be tied to HIO VDD.

• For MC68K #2, this pin inputs the bus size bit 1 (SIZ1).

• For REDCAP2, this pin inputs the output enable

(OE)

.

• For DragonBall, this pin inputs the output enable

(OE)

.

See Table 4-8: “Host Bus Interface Pin Mapping,” on page 29 for

summary.

Hardware Functional Specification	S1D13706
Issue Date: 2004/02/09	X31B-A-001-09

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Table 4-2: Host Interface Pin Descriptions

	Pin Name	Type	Pin #	Cell	IO	RESET#	Description
					Voltage	State
							During a data transfer, this output pin is driven active to force the
							system to insert wait states. It is driven inactive to indicate the
							completion of a data transfer. WAIT# is released to the high
							impedance state after the data transfer is complete. Its active
							polarity is configurable. See Table 4-7: “Summary of Power-
							On/Reset Options,” on page 28.
							• For Generic #1, this pin outputs the wait signal (WAIT#).
							• For Generic #2, this pin outputs the wait signal (WAIT#).
							• For SH-3 mode, this pin outputs the wait request signal
							(WAIT#).
	WAIT#	O	17	LB2A	HIOVDD	Hi-Z	• For SH-4 mode, this pin outputs the device ready signal
							(RDY#).
							• For MC68K #1, this pin outputs the data transfer acknowledge
							signal (DTACK#).
							• For MC68K #2, this pin outputs the data transfer and size
							acknowledge bit 1 (DSACK1#).
							• For REDCAP2, this pin is unused (Hi-Z).
							• For DragonBall, this pin outputs the data transfer
							acknowledge signal (DTACK).
							See Table 4-8: “Host Bus Interface Pin Mapping,” on page 29 for
							summary.
	RESET#	I	13	LIS	HIOVDD	0	Active low input to set all internal registers to the default state and
							to force all signals to their inactive states.

S1D13706	Hardware Functional Specification
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4.3.2 LCD Interface

Table 4-3: LCD Interface Pin Descriptions

	Pin Name	Type	Pin #	Cell	IO	RESET#		Description
					Voltage	State
	FPDAT[17:0]	O	74-64,	LB3P	NIOVDD	0	Panel Data bits 17-0.
			61-55
							This output pin has multiple functions.
							•	Frame Pulse
	FPFRAME	O	52	LB3P	NIOVDD	0	•	SPS for Sharp HR-TFT
							•	DY for Epson D-TFD
							See Table 4-9: “LCD Interface Pin Mapping,” on page 30 for
							summary.
							This output pin has multiple functions.
							•	Line Pulse
	FPLINE	O	53	LB3P	NIOVDD	0	•	LP for Sharp HR-TFT
							•	LP for Epson D-TFD
							See Table 4-9: “LCD Interface Pin Mapping,” on page 30 for
							summary.
							This output pin has multiple functions.
							•	Shift Clock
	FPSHIFT	O	54	LB3P	NIOVDD	0	•	CLK for Sharp HR-TFT
							•	XSCL for Epson D-TFD
							See Table 4-9: “LCD Interface Pin Mapping,” on page 30 for
							summary.
							This output pin has multiple functions.
							•	Display enable (DRDY) for TFT panels
							• 2nd shift clock (FPSHIFT2) for passive LCD with Format 1
	DRDY	O	48	LO3	NIOVDD	0		interface
							•	GCP for Epson D-TFD
							•	LCD backplane bias signal (MOD) for all other LCD panels
							See Table 4-9: “LCD Interface Pin Mapping,” on page 30 for
							summary.
							This pin has multiple functions.
							•	PS for Sharp HR-TFT
							•	XINH for Epson D-TFD
	GPIO0	IO	45	LB3M	NIOVDD	0	•	General purpose IO pin 0 (GPIO0)
							•	Hardware Video Invert
							See Table 4-9: “LCD Interface Pin Mapping,” on page 30 for
							summary.
							This pin has multiple functions.
							•	CLS for Sharp HR-TFT
	GPIO1	IO	44	LB3M	NIOVDD	0	•	YSCL for Epson D-TFD
							•	General purpose IO pin 1 (GPIO1)
							See Table 4-9: “LCD Interface Pin Mapping,” on page 30 for
							summary.

Hardware Functional Specification	S1D13706
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Table 4-3: LCD Interface Pin Descriptions

	Pin Name	Type	Pin #	Cell	IO	RESET#		Description
					Voltage	State
							This pin has multiple functions.
							•	REV for Sharp HR-TFT
	GPIO2	IO	43	LB3M	NIOVDD	0	•	FR for Epson D-TFD
							•	General purpose IO pin 2 (GPIO2)
							See Table 4-9: “LCD Interface Pin Mapping,” on page 30 for
							summary.
							This pin has multiple functions.
							•	SPL for Sharp HR-TFT
	GPIO3	IO	42	LB3M	NIOVDD	0	•	FRS for Epson D-TFD
							•	General purpose IO pin 3 (GPIO3)
							See Table 4-9: “LCD Interface Pin Mapping,” on page 30 for
							summary.
							This pin has multiple functions.
							•	RES for Epson D-TFD
	GPIO4	IO	41	LB3M	NIOVDD	0	•	General purpose IO pin 4 (GPIO4)
							See Table 4-9: “LCD Interface Pin Mapping,” on page 30 for
							summary.
							This pin has multiple functions.
							• DD_P1 for Epson D-TFD
	GPIO5	IO	40	LB3M	NIOVDD	0	•	General purpose IO pin 5 (GPIO5)
							See Table 4-9: “LCD Interface Pin Mapping,” on page 30 for
							summary.
							This pin has multiple functions.
							•	YSCLD for Epson D-TFD
	GPIO6	IO	39	LB3M	NIOVDD	0	•	General purpose IO pin 6 (GPIO6)
							See Table 4-9: “LCD Interface Pin Mapping,” on page 30 for
							summary.
							This output pin has multiple functions.
	PWMOUT	O	38	LB3P	NIOVDD	0	• PWM Clock output
							•	General purpose output
							This output pin has multiple functions.
	CVOUT	O	46	LB3P	NIOVDD	0	• CV Pulse Output
							•	General purpose output

S1D13706	Hardware Functional Specification
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	4.3.3 Clock Input
					Table 4-4: Clock Input Pin Descriptions
	Pin Name	Type	Pin #	Cell	IO	RESET#	Description
					Voltage	State
	CLKI	I	15	LI	NIOVDD	—	Typically used as input clock source for bus clock and memory
							clock
	CLKI2	I	77	LI	NIOVDD	—	Typically used as input clock source for pixel clock

4.3.4 Miscellaneous

Table 4-5: Miscellaneous Pin Descriptions

	Pin Name	Type	Pin #	Cell	IO	RESET#	Description
					Voltage	State
							These inputs are used to configure the S1D13706 - see Table 4-7:
	CNF[7:0]	I	78-85	LI	NIOVDD	—	“Summary of Power-On/Reset Options,” on page 28.
							Note: These pins are used for configuration of the S1D13706
							and must be connected directly to IO VDD or VSS.
							General Purpose Output (possibly used for controlling the LCD
	GPO	O	47	LO3	NIOVDD	0	power). It may also be used for the MOD control signal of the Sharp
							HR-TFT panel.
	TESTEN	I	86	T1	NIOVDD	0	Test Enable input used for production test only (has type 1 pull-
							down resistor with a typical value of 50Ω at 3.3V).

4.3.5 Power And Ground

Table 4-6: Power And Ground Pin Descriptions

	Pin Name	Type	Pin #	Cell	IO	RESET#	Description
					Voltage	State
	HIOVDD	P	16, 26	P	—	—	IO VDD pins associated with the host interface pins as described in
							Section 4.3.1, “Host Interface” on page 21.
							IO VDD pins associated with the non-host interface pins as
	NIOVDD	P	37, 49,	P	—	—	described in Section 4.3.2, “LCD Interface” on page 25, Section
			63, 76				4.3.3, “Clock Input” on page 27, and Section 4.3.4, “Miscellaneous”
							on page 27.
	COREVDD	P	1, 51	P	—	—	2 Core VDD. pins.
			14, 25,
	VSS	P	36, 50,	P	—	—	7 VSS pins.
			62, 75,
			100

Hardware Functional Specification	S1D13706
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4.4 Summary of Configuration Options

These pins are used for configuration of the S1D13706 and must be connected directly to NIOVDD or VSS. The state of CNF[6:0] is latched on the rising edge of RESET#. Changing state at any other time has no effect.

Table 4-7: Summary of Power-On/Reset Options

S1D13706				Power-On/Reset State
Configuration	1 (connected to NIOVDD)					0 (Connected to VSS)
Input
	Select host bus interface as follows:
	CNF4	CNF2	CNF1	CNF0		Host Bus
	1	0	0	0		SH-4/SH-3 interface, Big Endian
	0	0	0	0		SH-4/SH-3 interface, Little Endian
	1	0	0	1		MC68K #1, Big Endian
	0	0	0	1		Reserved
	1	0	1	0		MC68K #2, Big Endian
	0	0	1	0		Reserved
	1	0	1	1		Generic #1, Big Endian
CNF4,CNF[2:0]	0	0	1	1		Generic #1, Little Endian
	1	1	0	0		Reserved
	0	1	0	0		Generic #2, Little Endian
	1	1	0	1		REDCAP2, Big Endian
	0	1	0	1		Reserved
	1	1	1	0		DragonBall (MC68EZ328/MC68VZ328), Big Endian
	0	1	1	0		Reserved
	X	1	1	1		Reserved
	Note: The host bus interface is 16-bit only.
CNF3	Configure GPIO pins as inputs at power-on					Configure GPIO pins as outputs at power-on (for use
						by HR-TFT/D-TFD when selected)
CNF5	WAIT# is active high					WAIT# is active low
	CLKI to BCLK divide select:
	CNF7	CNF6			CLKI to BCLK Divide Ratio
CNF[7:6]	0	0			1 : 1
	0	1			2 : 1
	1	0			3 : 1
	1	1			4 : 1

S1D13706	Hardware Functional Specification
X31B-A-001-09	Issue Date: 2004/02/09

Epson Research and Development	Page 29
Vancouver Design Center

4.5 Host Bus Interface Pin Mapping

Table 4-8: Host Bus Interface Pin Mapping

Motorola

S1D13706

Generic #1

Generic #2

Hitachi

Motorola

Motorola

Motorola

MC68EZ328/

Pin Name

SH-3 /SH-4

MC68K #1

MC68K #2

REDCAP2

MC68VZ328

DragonBall

AB[16:1]

A[16:1]

A[16:1]

A[16:1]

A[16:1]

A[16:1]

A[16:1]

A[16:1]

AB0

A01

A0

A01

LDS#

A0

A01

A01

DB[15:0]

D[15:0]

D[15:0]

D[15:0]

D[15:0]

D[15:0]2

D[15:0]

D[15:0]

CS#

External Decode

CSn#

External Decode

CSn

CSX

M/R#

External Decode

CLKI

BUSCLK

BUSCLK

CKIO

CLK

CLK

CLK

CLKO

BS#

Connected to VDD

BS#

AS#

AS#

Connected to VDD

Connected to

Connected to

RD/WR#

RD1#

RD/WR#

R/W#

R/W#

R/W

VDD

VDD

Connected to

RD#

RD0#

RD#

RD#

SIZ1

OE

OE

VDD

Connected to

WE0#

WE0#

WE#

WE0#

SIZ0

EB1

LWE

VDD

WE1#

WE1#

BHE#

WE1#

UDS#

DS#

EB0

UWE

WAIT#/

WAIT#

WAIT#

WAIT#

DTACK#

DSACK1#

N/A

DTACK

RDY#

RESET#

RESET#

RESET#

RESET#

RESET#

RESET#

RESET_OUT

RESET

Note

1A0 for these busses is not used internally by the S1D13706 and should be connected to VSS.

2If the target MC68K bus is 32-bit, then these signals should be connected to D[31:16].

Hardware Functional Specification	S1D13706
Issue Date: 2004/02/09	X31B-A-001-09

Page 30	Epson Research and Development
	Vancouver Design Center

4.6 LCD Interface Pin Mapping

Table 4-9: LCD Interface Pin Mapping

Monochrome Passive

Color Passive Panel

Color TFT Panel

Panel

Pin Name

Single

Single

Others

Sharp HR-

Epson

TFT1

D-TFD1

4-bit

Format 1

Format 2

16-Bit

4-bit

8-bit

8-bit

8-bit

9-bit

12-bit

18-bit

18-bit

18-bit

FPFRAME

FPFRAME

SPS

DY

FPLINE

FPLINE

LP

LP

FPSHIFT

FPSHIFT

DCLK

XSCL

DRDY

MOD

FPSHIFT2

MOD

DRDY

no connect

GCP

FPDAT0

driven 0

D0

driven 0

D0 (B5)2

D0 (G3)2

D0 (R6)2

R2

R3

R5

R5

R5

FPDAT1

driven 0

D1

driven 0

D1 (R5)2

D1 (R3)2

D1 (G5)2

R1

R2

R4

R4

R4

FPDAT2

driven 0

D2

driven 0

D2 (G4)2

D2 (B2)2

D2 (B4)2

R0

R1

R3

R3

R3

FPDAT3

driven 0

D3

driven 0

D3 (B3)2

D3 (G2)2

D3 (R4)2

G2

G3

G5

G5

G5

FPDAT4

D0

D4

D0 (R2)2

D4 (R3)2

D4 (R2)2

D8 (B5)2

G1

G2

G4

G4

G4

FPDAT5

D1

D5

D1 (B1)2

D5 (G2)2

D5 (B1)2

D9 (R5)2

G0

G1

G3

G3

G3

FPDAT6

D2

D6

D2 (G1)2

D6 (B1)2

D6 (G1)2

D10 (G4)2

B2

B3

B5

B5

B5

FPDAT7

D3

D7

D3 (R1)2

D7 (R1)2

D7 (R1)2

D11 (B3)2

B1

B2

B4

B4

B4

FPDAT8

driven 0

driven 0

driven 0

driven 0

driven 0

D4 (G3)2

B0

B1

B3

B3

B3

FPDAT9

driven 0

driven 0

driven 0

driven 0

driven 0

D5 (B2)2

driven 0

R0

R2

R2

R2

FPDAT10

driven 0

driven 0

driven 0

driven 0

driven 0

D6 (R2)2

driven 0

driven 0

R1

R1

R1

FPDAT11

driven 0

driven 0

driven 0

driven 0

driven 0

D7 (G1)2

driven 0

driven 0

R0

R0

R0

FPDAT12

driven 0

driven 0

driven 0

driven 0

driven 0

D12 (R3)2

driven 0

G0

G2

G2

G2

FPDAT13

driven 0

driven 0

driven 0

driven 0

driven 0

D13 (G2)2

driven 0

driven 0

G1

G1

G1

FPDAT14

driven 0

driven 0

driven 0

driven 0

driven 0

D14 (B1)2

driven 0

driven 0

G0

G0

G0

FPDAT15

driven 0

driven 0

driven 0

driven 0

driven 0

D15 (R1)2

driven 0

B0

B2

B2

B2

FPDAT16

driven 0

driven 0

driven 0

driven 0

driven 0

driven 0

driven 0

driven 0

B1

B1

B1

FPDAT17

driven 0

driven 0

driven 0

driven 0

driven 0

driven 0

driven 0

driven 0

B0

B0

B0

GPIO0

GPIO0

GPIO0

GPIO0

GPIO0

GPIO0

GPIO0

GPIO0

GPIO0

GPIO0

PS

XINH

GPIO1

GPIO1

GPIO1

GPIO1

GPIO1

GPIO1

GPIO1

GPIO1

GPIO1

GPIO1

CLS

YSCL

GPIO2

GPIO2

GPIO2

GPIO2

GPIO2

GPIO2

GPIO2

GPIO2

GPIO2

GPIO2

REV

FR

GPIO3

GPIO3

GPIO3

GPIO3

GPIO3

GPIO3

GPIO3

GPIO3

GPIO3

GPIO3

SPL

FRS

GPIO4

GPIO4

GPIO4

GPIO4

GPIO4

GPIO4

GPIO4

GPIO4

GPIO4

GPIO4

GPIO4

RES

(output only)

GPIO5

GPIO5

GPIO5

GPIO5

GPIO5

GPIO5

GPIO5

GPIO5

GPIO5

GPIO5

GPIO5

DD_P1

(output only)

GPIO6

GPIO6

GPIO6

GPIO6

GPIO6

GPIO6

GPIO6

GPIO6

GPIO6

GPIO6

GPIO6

YSCLD

(output only)

GPO

GPO (General Purpose Output)

MOD3

GPO

CVOUT

CVOUT

PWMOUT

PWMOUT

Note

1GPIO pins must be configured as outputs (CNF3 = 0 at RESET#) when the HR-TFT or D-TFD interface is selected.

2These pin mappings use signal names commonly used for each panel type, however signal names may differ between panel manufacturers. The values shown in brackets represent the color components as mapped to the corresponding FPDATxx signals at the first valid edge of FPSHIFT. For further FPDATxx to LCD interface mapping, see Section 6.4, “Display Interface” on page 56.

3When the HR-TFT interface is selected (REG[10h] bits 1-0 = 10), this GPO can be used to control the HR-TFT MOD signal. Note this is not the same signal as the S1D13706 DRDY(MOD) signal used for passive panels.

S1D13706	Hardware Functional Specification
X31B-A-001-09	Issue Date: 2004/02/09