Epson S1D13704 Technical Manual

Page 1

S1D13704 Embedded Memory Color LCD Controller

S1D13704

TECHNICAL MANUAL

Issue Date: 01/02/12 Document Number: X26A-Q-001-04

Information in this document is subject to change without notice. You may download and use this document, but only for your own use in evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any representation that the contents of this document are accurate or current. The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent law s .

EPSON is a registered trademark of Seiko Epson Corporation. All other Trademarks are the property of their respective owners

Page 2

Page 2 Epson Research and Development

Vancouver Design Center

THIS PAGE LEFT BLANK

S1D13704 TECHNICAL MANUAL X26A-Q-001-04 Issue Date: 01/02/12

Page 3

Epson Research and Development Page 3

Vancouver Design Center

Customer Support Information

Comprehensive Support Tools

Seiko Epson Corp. provides to the system designer and computer OEM manufacturer a complete set of resources and tools for the development of graphics systems.

Evaluation / Demonstration Board

• Assembled and fully tested graphics evaluation board with installation guide and schematics.

• To borrow an evaluation board, pl ease cont act your local Seiko Epson Corp. sales representative.

Chip Documentation

• Technical manual includes Data Sheet, Application Notes, and Programmer’s Reference.

Software

• OEM Utilities.

• User Utilities.

• Evaluation Software.

• To obtain these programs, contact Applicat ion Engineering Support.

Application Engineering Support

Engineering and Sales Support is provided by:

Japan

Seiko Epson Corporation Electronic Devices Marketing Division 421-8, Hino, Hino-shi Tokyo 191-8501, Japan Tel: 042-587-5812 Fax: 042-587-5564 http://www.epson.co.jp

Hong Kong

Epson Hong Kong Ltd. 20/F., Harbour Centre 25 Harbour Road Wanchai, Hong Kong Tel: 2585-4600 Fax: 2827-4346

North America

Epson Electronics America, Inc. 150 River Oaks Parkway San Jose, CA 95134, USA Tel: (408) 922-0200 Fax: (408) 922-0238 http://www.eea.epson.com

Europe

Epson Europe Electronics GmbH Riesstrasse 15 80992 Munich, Germany Tel: 089-14005-0 Fax: 089-14005-110

Taiwan, R.O.C.

Epson Taiwan Technology & Trading Ltd. 10F, No. 287 Nanking East Road Sec. 3, Taipei, Taiwan, R.O.C. Tel: 02-2717-7360 Fax: 02-2712-9164

Singapore

Epson Singapore Pte., Ltd. No. 1 Temasek Avenue #36-00 Millenia Tower Singapore, 039192 Tel: 337-7911 Fax: 334-2716

TECHNICAL MANUAL S1D13704 Issue Date: 01/02/12 X26A-Q-001-04

Page 4

Page 4 Epson Research and Development

Vancouver Design Center

THIS PAGE LEFT BLANK

S1D13704 TECHNICAL MANUAL X26A-Q-001-04 Issue Date: 01/02/12

Page 5

Epson Research and Development Page 5

Vancouver Design Center

INTRODUCTION

S1D13704 Embedded Memory Color LCD Controller Product Brief

SPECIFICATION

S1D13704 Hardware Functiona l Specification

PROGRAMMER’S REFERENCE

S1D13704 Programming Notes and Examples S1D13704 Register Summary

UTILITIES

13704CFG.EXE File Configuration Program 13704SHOW Demonstration Program 13704SPLT Display Utility 13704VIRT Display Utility 13704PLAY Diagnostic Utility 13704BMP Demonstration Program 13704PWR Power Save Utility

DRIVERS

S1D13704 Windows® CE Display Drivers

EVALUATION

S5U13704B00C Rev. 1 ISA Bus Evaluation Board User Manual

APPLICATION NOTES

Interfacing to the Toshiba MIPS TX3912 Processor Power Consumption Interfacing to the Mo tor ola MC68328 Microprocessor Interfacing to the NEC VR4102 Micr opr ocessor Interfacing the S1D13704 to the PC Card Bus Interfacing to the Mo tor ola MPC821 Microprocessor Interfacing to the Mo tor ola MCF5307 Microprocessor Interfacing to the Philips MIPS PR31500/PR31700 Processor S5U13704/5-TMPR3912/22U CPU Module Interfacing to an 8-Bi t Processor

TECHNICAL MANUAL S1D13704 Issue Date: 01/02/12 X26A-Q-001-04

Page 6

Page 6 Epson Research and Development

Vancouver Design Center

THIS PAGE LEFT BLANK

S1D13704 TECHNICAL MANUAL X26A-Q-001-04 Issue Date: 01/02/12

Page 7

ENERGY

SAVING

EPSON

GRAPHICS

S1D13704

February 2001

S1D13704 EMBEDDED MEMORY COLOR LCD CONTROLLER

■

DESCRIPTION

The S1D13704 is a color/monochrome LCD graphics controller with an embedded 40K Byte SRAM display buffer. The high integration of the S1D13704 provides a low cost, low power, single chip solution to meet the requirements of embedded markets such as Office Automation equipment, Mobile Communications devices, and Palmsize PCs where board size and battery life are major concerns.

Products requiring a “Portrait” display can take advantage of the Hardware Portrait Mode feature of the S1D13704. Virtual and Split Screen are just some of the display modes supported. The above features, combined with the Operating System independence of the S1D13704, make it the ideal s olution for a wide variety of applications .

■

FEATURES

Memory Interface

Embedded 40K byte SR AM dis pl ay bu ffer .

•

CPU Interface

Direct support of the following interfaces:

•

Hitachi SH-3. Hitachi SH-4. Motorola M68K. MPU bus interface with programmable READY.

Direct memory mapping of internal registers.

•

CPU write buffer.

•

Display Support

4/8-bit monochrome LCD interface.

•

4/8-bit color LCD interface.

•

Single-panel, single-drive passive displays.

•

Dual-panel, dual-drive passive displays.

•

Active Matrix TFT / TFD in terface.

•

Example resolu tio ns :

•

640x480 at a color depth of 1 bpp 640x240 at a color depth of 2 bpp 320x240 at a color depth of 4 bpp 240x160 at a color depth of 8 bpp

Po wer Down Modes

Hardware and software Suspend modes.

•

LCD power-down sequencing.

•

Display Modes

Hardware Portrait Mode: direct ha rdware rotation

•

of display image for portrait mode display. 1/2/4 bit-per-pixel (bpp), 2/4/16-level grayscale

•

display.

1/2/4/8 bit-per-pixel, 2/4/16/256-level color display.

•

Up to 16 shades of gray by FRM on monochrome

•

passive LCD panels. 256 simultaneous of 4096 colors on color passive

•

and active matrix LCD panels.

Split screen display for all panel modes allows two

•

different images to be simultaneously displayed.

Virtual display support (displays images larger

•

than the panel size through the use of panning).

Clock Source

Single clock input f or bo th pix e l and memory clocks.

•

The S1D13704 clock source can be internally

•

divided down for a higher frequency clock input.

Dynamic switching of memory clocks in portrait

•

mode.

General Purpose IO Pins

Five General Purpose Input / Output pins available.

•

Operating Voltage

2.7 volts to 5.5 volts.

•

Package

80-pin QFP14 surface mount package.

•

X26A-C-001-07 1

Page 8

GRAPHICS

S1D13704

■

SYSTEM BLOCK DIAGRAM

CPU

Data and

Control Signals

S1D13704

CONTACT YOUR SALES REPRESENTATIVE FOR THESE COMPREHENSIVE DESIGN TOOLS:

• S1D13704 Technical Manual

• S5U13704 Evaluation Boards

• Windows



CE Display Driver

• CPU Independent Software Utilities

Japan

Seiko Epson Corporation Electronic Devices Marketing Division 421-8, Hino, Hino-shi Tokyo 191-8501, Japan Tel: 042-587-5812 Fax: 042-587-5564 http://www.epson.co.jp

North America

Epson Electronics America, Inc. 150 River Oaks Parkway San Jose, CA 95134, USA Tel: (408) 922-0200 Fax: (408) 922-0238 http://www.eea.epson.com

Digital Out

Flat Panel

Actual Size

FOR SYSTEM INT EGRATION SERVICES FOR WINDOWS® CE CONTACT:

Epson Research & Development, Inc. Suite #320 - 11120 Horseshoe Way Richmond, B.C., Canada V7A 5H7 Tel: (604) 275-5151 Fax: (604) 275-2167 Email: wince@erd.epson.com http://www.erd.epson.com

Taiwan, R.O.C.

Epson Taiwan Technology & Trading Ltd. 10F, No. 287 Nanking East Road Sec. 3, Taipei, Taiwan, R.O.C. Tel: 02-2717-7360 Fax: 02-2712-9164

Hong Kong

Epson Hong Kong Ltd. 20/F., Harbour Centre 25 Harbour Road Wanchai, Hong Kong Tel: 2585-4600 Fax: 2827-4346

Copyright ©1998, 2001 Epson Research and Development, Inc. All rights reserved. VDC Information in this document is subject to change without notice. You may download and use this document, but only for your own use in evaluati ng Seiko Epson/EPSON products. You may not mod ify the docume nt. Epson Rese arch and Deve lopment, Inc. d isclaims an y representati on that the content s of this do cument are accurate or current. The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trade mark of Seiko Epso n Corpor ation. Microsoft, W indows, and the Wi ndo ws CE Logo are re gistered t rademarks of Micr osoft Corporation.

Europe

Epson Europe Electronics GmbH Riesstrasse 15 80992 Munich, Germany Tel: 089-14005-0 Fax: 089-14005-110

Singapore

Epson Singapore Pte., Ltd. No. 1 Temasek Avenue #36-00 Millenia Tower Singapore, 039192 Tel: 337-7911 Fax: 334-2716

X26A-C-001-07 2

Page 9

S1D13704 Embedded Memory LCD Controller

Hardware Functional Specification

Document Number: X26A-A-001-04

EPSON is a registered trademark of Seiko Epson Corporation. All other Trademarks are the property of their respective owners

Page 10

Page 2 Epson Research and Development

Vancouver Design Center

THIS PAGE LEFT BLANK

S1D13704 Hardware Functional Specification X26A-A-001-04 Issue Date: 01/02/08

Page 11

Epson Research and Development Page 3

Vancouver Design Center

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

1.1 Scope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

1.2 Overview Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.1 Integrated Frame Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.2 CPU Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.3 Display Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.4 Display Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.5 Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.6 Miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.7 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

3 Typical System Implementation Diagrams . . . . . . . . . . . . . . . . . . . . . . 12

4 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

4.1 Functional Block Descriptions . . . . . . . . . . . . . . . . . . . . . . . . 15

4.1.1 Host Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

4.1.2 Memory Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

4.1.3 Sequence Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

4.1.4 Look-Up Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

4.1.5 LCD Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

4.1.6 Power Save . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

5 Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

5.1 Pinout Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

5.2 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

5.2.1 Host Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

5.2.2 LCD Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

5.2.3 Clock Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

5.2.4 Miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

5.2.5 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

5.3 Summary of Configuration Options . . . . . . . . . . . . . . . . . . . . . . 22

5.4 Host Bus Interface Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . 22

5.5 LCD Interface Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . . 23

6 D.C. Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

7 A.C. Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

7.1 Bus Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

7.1.1 SH-4 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

7.1.2 SH-3 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

7.1.3 Motorola M68K #1 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . 30

Hardware Functional Specification S1D13704 Issue Date: 01/02/08 X26A-A-001-04

Page 12

Page 4 Epson Research and Development

Vancouver Design Center

7.1.4 M otorola M68K #2 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . 31

7.1.5 Generic #1 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

7.1.6 Generic #2 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

7.2 Clock Input Requirements . . . . . . . . . . . . . . . . . . . . . . . . . .34

7.3 Display Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

7.3.1 Power On/Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

7.3.2 Power Down/Up Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

7.3.3 Single Monochrome 4-Bit Panel Timing . . . . . . . . . . . . . . . . . . . . . . . 37

7.3.4 Single Monochrome 8-Bit Panel Timing . . . . . . . . . . . . . . . . . . . . . . . 39

7.3.5 Single Color 4-Bit Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

7.3.6 Single Color 8-Bit Panel Timing (Format 1) . . . . . . . . . . . . . . . . . . . . . 43

7.3.7 Single Color 8-Bit Panel Timing (Format 2) . . . . . . . . . . . . . . . . . . . . . 45

7.3.8 Dual Monochrome 8-Bit Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . 47

7.3.9 Dual Color 8-Bit Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

7.3.10 9/12-Bit TFT/D-TFD Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 51

8 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54

8.1 Register Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

8.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . .54

9 Frame Rate Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70

10 Display Data Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71

11 Look-Up Table Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72

11.1 Gray Shade Display Modes . . . . . . . . . . . . . . . . . . . . . . . . . . 72

11.2 Color Display Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . .75

12 SwivelView™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79

12.1 Default SwivelView Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 79

12.1.1 How to Set Up Default SwivelView Mode . . . . . . . . . . . . . . . . . . . . . . 80

12.2 Alternate SwivelView Mode . . . . . . . . . . . . . . . . . . . . . . . . .81

12.2.1 How to Set Up Alternate SwivelView Mode . . . . . . . . . . . . . . . . . . . . . 82

12.3 Comparison Between Default and Alternate SwivelView Modes . . . . . . . . . . .83

12.4 SwivelView Mode Limitations . . . . . . . . . . . . . . . . . . . . . . . .83

13 Power Save Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84

13.1 Software Power Save Mode . . . . . . . . . . . . . . . . . . . . . . . . .84

13.2 Hardware Power Save Mode . . . . . . . . . . . . . . . . . . . . . . . . .84

13.3 Power Save Mode Function Summary . . . . . . . . . . . . . . . . . . . . .85

13.4 Panel Power Up/Down Sequence . . . . . . . . . . . . . . . . . . . . . . .85

13.5 Turning Off BCLK Between Accesses . . . . . . . . . . . . . . . . . . . . .86

13.6 Clock Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . .87

14 Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88

S1D13704 Hardware Functional Specification X26A-A-001-04 Issue Date: 01/02/08

Page 13

Epson Research and Development Page 5

Vancouver Design Center

List of Tables

Table 5-1: Summary of Power On/Reset Options . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 5-2: Host Bus Interface Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 5-3: LCD Interface Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Table 6-1: Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 6-2: Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 6-3: Input Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 6-4: Output Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 7-1: SH-4 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 7-2: SH-3 Bus Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 7-3: M68K #1 Bus Timing (MC68000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 7-4: M68K #2 Timing (MC68030) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 7-5: Generic #1 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 7-6: Generic #2 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 7-7: Clock Input Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 7-8: Power Down/Up Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 8-1: Panel Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Table 8-2: Gray Shade/Color Mode Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Table 8-3: High Performance Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Table 8-4: Inverse Video Mode Select Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Table 8-5: Hardware Power Save/GPIO0 Operation . . . . . . . . . . . . . . . . . . . . . . . . . 58

Table 8-6: Software Power Save Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 8

Table 8-7: Look-Up Table Access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Table 8-8: Selection of SwivelView Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Table 8-9: Selection of PCLK and MCLK in SwivelView Mode. . . . . . . . . . . . . . . . . . . 69

Table 11-1: Look-Up Table Configurations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Table 12-1: Default and Alternate SwivelView Mode Comparison . . . . . . . . . . . . . . . . . . 83

Table 13-1: Power Save Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Table 13-2: Software Power Save Mode Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Table 13-3: Hardware Power Save Mode Summary . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Table 13-4: Power Save Mode Function Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Table 13-5: S1D13704 Internal Cloc k Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . 87

Hardware Functional Specification S1D13704 Issue Date: 01/02/08 X26A-A-001-04

Page 14

Page 6 Epson Research and Development

Vancouver Design Center

THIS PAGE LEFT BLANK

S1D13704 Hardware Functional Specification X26A-A-001-04 Issue Date: 01/02/08

Page 15

Epson Research and Development Page 7

Vancouver Design Center

List of Figures

Figure 3-1: Typical System Diagram (SH-4 Bus). . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 3-2: Typical System Diagram (SH-3 Bus). . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 3-3: Typical System Diagram (M68K #1 Bus) . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 3-4: Typical System Diagram (M68K #2 Bus) . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 3-5: Typical System Diagram (Generic #1 Bus) . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 3-6: Typical System Diagram (Generic #2 Bus - e.g. ISA Bus). . . . . . . . . . . . . . . . . 14

Figure 4-1: System Block Diagram Showing Data Paths . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 5-1: Pinout Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 7-1: SH-4 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 7-2: SH-3 Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 7-3: M68K #1 Bus Timing (MC68000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 7-4: M68K #2 Timing (MC68030) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

Figure 7-5: Generic #1 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Figure 7-6: Generic #2 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 7-7: Clock Input Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 7-8: LCD Panel Power On/Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 7-9: Power Down/Up Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 7-10: Single Monochrome 4-Bit Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 7-11: Single Monochrome 4-Bit Panel A.C. Timing . . . . . . . . . . . . . . . . . . . . . . . 38

Figure 7-12: Single Monochrome 8-Bit Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Figure 7-13: Single Monochrome 8-Bit Panel A.C. Timing . . . . . . . . . . . . . . . . . . . . . . . 40

Figure 7-14: Single Color 4-Bit Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Figure 7-15: Single Color 4-Bit Panel A.C. Timing . . . . . . . . . . . . . . . . . . . . . . . . . . .42

Figure 7-16: Single Color 8-Bit Panel Timing (Format 1) . . . . . . . . . . . . . . . . . . . . . . . . 43

Figure 7-17: Single Color 8-Bit Panel A.C. Timing (Format 1) . . . . . . . . . . . . . . . . . . . . . 44

Figure 7-18: Single Color 8-Bit Panel Timing (Format 2) . . . . . . . . . . . . . . . . . . . . . . . . 45

Figure 7-19: Single Color 8-Bit Panel A.C. Timing (Format 2) . . . . . . . . . . . . . . . . . . . . . 46

Figure 7-20: Dual Monochrome 8-Bit Panel Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Figure 7-21: Dual Monochrome 8-Bit Panel A.C. Timing. . . . . . . . . . . . . . . . . . . . . . . . 48

Figure 7-22: Dual Color 8-Bit Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Figure 7-23: Dual Color 8-Bit Panel A.C. Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . .50

Figure 7-24: 12-Bit TFT/D-TFD Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51

Figure 7-25: TFT/D-TFD A.C. Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Figure 8-1: Screen-Register Relationship, Split Screen. . . . . . . . . . . . . . . . . . . . . . . . . 64

Figure 10-1: 1/2/4/8 Bit-Per-Pixel Display Data Memory Organization. . . . . . . . . . . . . . . . . 71

Figure 11-1: 2-Level Gray-Shade Mode Look-Up Table Architecture . . . . . . . . . . . . . . . . . 72

Figure 11-2: 4-Level Gray-Shade Mode Look-Up Table Architecture . . . . . . . . . . . . . . . . . 73

Hardware Functional Specification S1D13704 Issue Date: 01/02/08 X26A-A-001-04

Page 16

Page 8 Epson Research and Development

Vancouver Design Center

Figure 11-3: 16-Level Gray-Shade Mode Look-Up Table Architecture . . . . . . . . . . . . . . . . . 73

Figure 11-4: Look-Up Table Bypas s Mode Arc hitectur e. . . . . . . . . . . . . . . . . . . . . . . . . 74

Figure 11-5: 2-Level Color Look-Up Table Architecture . . . . . . . . . . . . . . . . . . . . . . . . 75

Figure 11-6: 4-Level Color Mode Look-Up Table Architecture . . . . . . . . . . . . . . . . . . . . . 76

Figure 11-7: 16-Level Color Mode Look-Up Table Architecture . . . . . . . . . . . . . . . . . . . .77

Figure 11-8: 256-Level Color Mode Look-Up Table Architecture. . . . . . . . . . . . . . . . . . . . 78

Figure 12-1: Relationship Between The Screen Image and the Image Refreshed by S1D13704 . . . .79

Figure 12-2: Relationship Between The Screen Image and the Image Refreshed by S1D13704 . . . .81

Figure 13-1: Panel On/Off Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Figure 14-1: Mechanical Drawing QFP14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

S1D13704 Hardware Functional Specification X26A-A-001-04 Issue Date: 01/02/08

Page 17

Epson Research and Development Page 9

Vancouver Design Center

1 Introduction

1.1 Scope

This is the Functiona l Specification f or the S1D13704 Embed ded Memory LCD Controlle r Chip. Included in this document are timing diagrams, AC and DC characteristics, register descriptions, and power management descriptions. This document is intended for two audiences: Video Subsystem Designers and Software Developers.

Please check the Epson Electronics America website at http://www.eea.epson.com for the latest revision of this document before beginning any development.

We appreciate your commen ts on our documentation. Please contact us via email at techpubs@erd.epson.com.

1.2 Overview Description

The S1D13704 is a color / monochrome LCD graphics controller with an embedded 40K Byte SRAM display buffer. The hig h integration of the S1D137 04 provides a low cost, low power, single chip solution to meet the requirements of embedded markets such as Office Automation equipment, Mobile Communic at ions devices, and Hand-Held PCs where board size and battery life are major concerns.

Products requiring a “Portrait” display can take advantage of the Swivelview™ (90° Hardware Rotate) feature of the S 1D13704. Virtual and Split Screen are just some of the display modes supported. The above features, combined with the Operating System independence of the S1D13704, make it the ideal solution for a wide variety of applications.

Hardware Functional Specification S1D13704 Issue Date: 01/02/08 X26A-A-001-04

Page 18

Page 10 Epson Research and Development

Vancouver Design Center

2 Features

2.1 Integrated Frame Buffer

• Embedded 40K byte SRAM display buffer.

2.2 CPU Interface

• Direct support of the following interfaces: Hitachi SH-3. Hitachi SH-4. Motorola M68 K . MPU bus interface using WAIT# signal.

• Direct memory mapping of internal registers.

• Single level CPU write buffer.

• Registers a re mapped into upper 32 bytes of 64K byte address space.

• The complete 40K byte fr ame bu ffer is directly and contiguously available through the 16-bit address bus.

2.3 Display Support

• 4/8-bit monochrome LCD interface.

• 4/8-bit color LCD interface.

• Single-panel, single-drive passive displays.

• Dual-panel, dual-drive passive displays.

• Active Matrix TFT / D-TFD interface

• Register level support for EL panels.

• Example resolutions:

640x480 at a color depth of 1 bpp 640x240 at a color depth of 2 bpp 320x240 at a color depth of 4 bpp 240x160 at a color depth of 8 bpp

S1D13704 Hardware Functional Specification X26A-A-001-04 Issue Date: 01/02/08

Page 19

Epson Research and Development Page 11

Vancouver Design Center

2.4 Display Modes

• SwivelView™: direct 90° hardware rotation of display image for portrait mode display.

• 1/2/4 bit-p er-pixel (bpp), 2/ 4/16-level grayshade d i s play.

• 1/2/4/8 bit-per-pixel, 2/4/16/256-level color display.

• Up to 16 shades of gray by FRM on monochrome passive LCD panels; a 16x4 LookUp-Table is used to map 1/2/4-bpp modes into these shades.

• 256 simultaneous of 4096 colors on color passive and active matrix LCD panels; three 16x4 Look-Up Tables are used to map 1/2/4/8-bpp modes into these colors.

• Split screen display for all landscape panel modes allows two different images to be simultaneously displayed.

• Virtual display support (displays images larger than the panel size through the use of panning).

2.5 Clock Source

• Maximum operating clock (CLK) frequency of 25MHz.

• Operating clock (CLK) is derived from CLKI input.

• Pixel Clock (PCLK) and Memory Clock (MCLK) are derived from CLK.

2.6 Miscellaneous

• Hardware/Software Video Invert.

• Software Power Save mode.

• Hardware Power Save mode.

• LCD power-down sequencing.

• 5 General Purpose Input/Out put pins are available.

• IO Operates from 3.0 volts to 5.5 volts

CLK = CLKI

CLK = CLKI/2

• GPIO0 is available if Hardware Power Save is not required.

• GPIO[4:1] are available if upper LCD data pins (FPDAT[11:8]) are not required for

TFT/D-TFD support or Hardware Video Inve rt.

• Core opera t e s from 3.0 volts to 3.6 volts.

2.7 Package

• 80 pin QFP14 package.

Hardware Functional Specification S1D13704 Issue Date: 01/02/08 X26A-A-001-04

Page 20

Page 12 Epson Research and Development

Vancouver Design Center

3 Typical System Implementation Diagrams

Oscillator

SH-4 BUS

SH-3 BUS

CSn#

A[15:0] D[15:0]

WE1#

BS#

RD/WR#

RD# WE0# RDY#

CKIO

RESET#

CSn#

A[15:0] D[15:0]

WE1#

BS#

RD/WR#

RD# WE0#

WAIT#

CKIO

RESET#

CLKI

CS# AB[15:0]

DB[15:0]

WE1# BS#

RD/WR#

RD# WE0# WAIT#

BCLK

RESET#

S1D13704

FPDAT[7:0]

FPSHIFT

FPFRAME

FPLINE

DRDY

LCDPWR

Figure 3-1: Typical System Diagram (SH-4 Bus)

Oscillator

CLKI

CS# AB[15:0]

DB[15:0]

WE1# BS#

RD/WR#

RD# WE0# WAIT#

BCLK

RESET#

S1D13704

FPDAT[3:0]

FPSHIFT

FPFRAME

FPLINE

DRDY

LCDPWR

D[7:0] FPSHIFT

FPFRAME FPLINE MOD

D[3:0] FPSHIFT

FPFRAME FPLINE MOD

8-bit LCD

Display

4-bit

LCD

Display

Figure 3-2: Typical System Diagram (SH-3 Bus)

S1D13704 Hardware Functional Specification X26A-A-001-04 Issue Date: 01/02/08

Page 21

Epson Research and Development Page 13

Vancouver Design Center

Oscillator

MC68000 BUS

A[23:16]

FC0, FC1, FC2

Decoder

CS#

CLKI

MC68030

BUS

A[31:16]

FC0, FC1, FC2

D[31:16]

DSACK1#

RESET#

A[15:1] D[15:0]

LDS#

UDS#

AS#

R/W#

DTACK#

CLK

RESET#

A[15:0]

DS# AS#

R/W#

SIZ1 SIZ0

CLK

AB[15:1] DB[15:0]

AB0# WE1# BS# RD/WR# WAIT#

BCLK RESET#

S1D13704

FPDAT[3:0]

FPSHIFT

FPFRAME

FPLINE

LCDPWR

Figure 3-3: Typical System Diagram (M68K #1 Bus)

Oscillator

Decoder

CS#

AB[15:0] DB[15:0]

WE1# BS#

RD/WR#

RD# WE0# WAIT#

BCLK RESET#

S1D13704

CLKI

FPDAT[7:0]

FPSHIFT

FPFRAME

FPLINE

DRDY

LCDPWR

DRDY

D[3:0] FPSHIFT

FPFRAME FPLINE MOD

D[7:0] FPSHIFT

FPFRAME FPLINE MOD

4-bit

LCD

Display

8-bit

LCD

Display

Figure 3-4: Typical System Diagram (M68K #2 Bus)

Hardware Functional Specification S1D13704 Issue Date: 01/02/08 X26A-A-001-04

Page 22

Page 14 Epson Research and Development

Vancouver Design Center

Oscillator

GENERIC #1 BUS

ISA BUS

CSn#

A[15:0] D[15:0]

WE0# WE1#

RD0# RD1#

WAIT#

BCLK

RESET#

REFRESH

SA[19:16]

SA[15:0] SD[15:0]

SMEMW#

SMEMR#

SBHE#

IOCHRDY

BCLK

RESET

BS#

CS# AB[15:0]

DB[15:0]

WE0# WE1#

RD RD/WR# WAIT#

BCLK RESET#

S1D13704

CLKI

FPDAT[11:0]

FPSHIFT

FPFRAME

FPLINE

LCDPWR

Figure 3-5: Typical System Diagram (Generic #1 Bus)

Oscillator

Decoder

BS#

CS#

AB[15:0] DB[15:0]

WE0# RD#

WE1#

WAIT#

BCLK RESET#

S1D13704

CLKI

FPDAT[8:0]

FPSHIFT

FPFRAME

FPLINE

LCDPWR

DRDY

D[11:0] FPSHIFT

FPFRAME FPLINE DRDY

D[8:0] FPSHIFT

FPFRAME

FPLINE DRDY

12-bit

TFT

Display

9-bit

TFT

Display

Figure 3-6: Typical System Diagram (Generic #2 Bus - e.g. ISA Bus)

S1D13704 Hardware Functional Specification X26A-A-001-04 Issue Date: 01/02/08

Page 23

Epson Research and Development Page 15

Vancouver Design Center

4 Functional Block Diagram

20k x 16-bit SRAM

Memory Controller

Generic MPU MC68K SH-3 SH-4

Host

I/F

Bus Clock Memory Clock Pixel Clock

Figure 4-1: System Block Diagram Showing Data Paths

4.1 Functional Block Descriptions

Power Save

Clocks

Look-Up Table

Sequence Controller

LCD

I/F

LCD

4.1.1 Host Interface

The Host Interface provides the means for the CPU/MPU to communicate with the display memory and internal re gisters.

4.1.2 Memory Controller

The Memory Controller arbitrates between CPU accesses and display refresh accesses. It also generates the necessary signals to control the SRAM frame buffer.

4.1.3 Sequence Controller

The Sequence Controller controls data flow from the Memory Controller throug h the LookUp Table and to the LCD Interf ace. It als o generate s memory addr esses for display re fresh accesses.

Hardware Functional Specification S1D13704 Issue Date: 01/02/08 X26A-A-001-04

Page 24

Page 16 Epson Research and Development

Vancouver Design Center

4.1.4 Look-Up Table

The Look-Up Table c ontain s thr ee 16x 4 Look- Up Table s or palet tes, one fo r each p rimary color. In monochrome mode only one of these Look-Up Tables is used.

4.1.5 LCD Interface

The LCD Interface perfo rms fra me rate modulation for passive LCD panels. It also generates the correct data format and timing control signa ls for various LCD and TFT/D-TFD panels.

4.1.6 Power Save

Power Save contains the power save mode circuitry.

S1D13704 Hardware Functional Specification X26A-A-001-04 Issue Date: 01/02/08

Page 25

Epson Research and Development Page 17

Vancouver Design Center

5 Pins

5.1 Pinout Diagram

60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41

AB11

AB9

AB10

VSS

AB12

AB13

AB14

AB15

VSS

CLKI

IOVDD

CNF1

CNF0

CNF2

CNF3

CNF4

TESTEN

DRDY

COREVDD

LCDPWR

61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80

COREVDD AB8 AB7 AB6

AB5 AB4 AB3 AB2 AB1 AB0 BCLK VSS RESET# CS# BS# RD# WE0# WE1# RD/WR# VSS

S1D13704

COREVDD

WAIT#

DB15

1234567891011121314151617181920

DB14

DB13

DB12

DB11

DB10

IOVDD

DB9

DB6

DB5

DB4

DB3

DB8

DB7

DB2

VSS

DB0

DB1

VSS

FPFRAME

FPLINE

FPDAT0 FPDAT1 FPDAT2 FPDAT3 FPDAT4 FPDAT5 FPDAT6

FPDAT7

IOVDD

FPSHIFT

VSS FPDAT8 FPDAT9

FPDAT10 FPDAT11

GPIO0

COREVDD

40 39 38

37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21

Figure 5-1: Pinout Diagram

Note

Package type: 80 pin surface mount QFP14

Hardware Functional Specification S1D13704 Issue Date: 01/02/08 X26A-A-001-04

Page 26

Page 18 Epson Research and Development

Vancouver Design Center

5.2 Pin Description

Key:

I=Input O=Output I/O = Bi-Directional (Input/Out put) P=Power pin C = CMOS level input CD = CMOS level input with pull down resistor (typical values of 100KΩ/180ΚΩ at 5V/3.3V respectively) CS = CMOS level Schmitt input COx = CMOS output driver, x denotes driver type (1=3/-1.5mA, 2=6/-3mA, 3=12/-6mA) TSx = Tri-state CMOS output driver, x denotes driver type (1=3/-1.5mA, 2=6/-3mA, 3=12/-6mA) TSxD = Tri-state CMOS output driver with pull down resistor (typical values of 100KΩ/180ΚΩ at 5V/3.3V

respectively), x denotes driver type (1=3/-1.5mA, 2=6/-3mA, 3=12/-6mA)

CNx = CMOS low-noise output driver, x denotes driver type (1=3/-1.5mA, 2=6/-3mA, 3=12/-6mA)

5.2.1 Host Interface

Pin Names Type Pin # Cell

AB0 I 70 CS Input

53, 54, 55, 56, 57, 58,

AB[15:1] I

DB[15:0] I/O

59, 62, 63, 64, 65, 66,

67, 68, 69

3, 4, 5, 6, 7, 8, 9, 11, 12,

13, 14, 15, 16, 17, 18,

C Input

C/TS2

RESET#

State

High

Impedance

Description

This pin has multiple functions.

• For SH-3/SH-4 mode, this pin in puts system address bi t 0 (A0).

• For MC68K #1, this pin inputs the lower data strobe (LDS#).

• For MC68K #2, this pin input s s ys tem address bit 0 (A0).

• For Generic #1, this pin inputs system add ress bit 0 (A0).

• For Generic #2, this pin inputs system add ress bit 0 (A0).

See “Host Bus Interface Pin Mapping” for summary.

These pins input the syste m add res s bits 15 through 1 (A[15:1]).

These pins have multiple fun cti ons .

• For SH-3/SH-4 mode, these pi ns are connected to [D15:0].

• For MC68K #1, these pins are connected to D[15:0].

• For MC68K #2, these pins are connected to D[31:16] for a 32-bit device (e.g. MC68030) or D[15:0] for a 16-bit device (e.g. MC68340).

• For Generic #1, these pins are connected to D[15:0].

• For Generic #2, these pins are connected to D[15:0].

See “Host Bus Interface Pin Mapping” for summary.

S1D13704 Hardware Functional Specification X26A-A-001-04 Issue Date: 01/02/08

Page 27

Epson Research and Development Page 19

Vancouver Design Center

Pin NamesType Pin #Cell

RESET#

State

Description

This pin has multi ple functions.

• For SH-3/SH-4 mode, this pin inputs the write enable signal for the lower data byte (WE0#).

• For MC68K #1, this pin must be tied to IO V

WE0# I 77 CS Input

• For MC68K #2, this pin inputs the bus size bit 0 (SIZ0).

• For Generic #1, this pi n inpu ts the write ena b le si gnal for the lower data b yte (WE0 #).

• For Generic #2, this pin inputs the write enable signal (WE#)

See “Host Bus Interface Pin Mapping” for summary. This pin has multi ple functions.

• For SH-3/SH-4 mode, this pin inputs the write enable signal for the upper data byte (WE1#).

• For MC68K #1, this pin inputs the upper data strobe (UDS#).

WE1# I 78 CS Input

• For MC68K #2, this pin inputs the data strobe (DS#).

• For Generic #1, this pi n inpu ts the write ena b le si gnal for the upper data byte (WE1#).

• For Generic #2, this pin in puts the byte enable signal for the high data byte (BHE#).

See “Host Bus Interface Pin Mapping” for summary.

CS# I 74 C Input This pin inputs the ch ip sel ec t sign al.

BCLK I 71 C Input This pin inputs the system bus clock.

This pin has multi ple functions.

• For SH-3/SH-4 mode, this pin inputs the bus start si gnal (BS#).

• For MC68K #1, this pin inputs the address strobe (AS#).

BS# I 75 CS Input

• For MC68K #2, this pin inputs the address strobe (AS#).

• For Generic #1, this pin must be tied to V

• For Generic #2, this pin must be tied to IO VDD.

See “Host Bus Interface Pin Mapping” for summary. This pin has multi ple functions.

• For SH-3/SH-4 mode, this pin inputs the RD/WR# signal. The S1D13704 needs this signal for early decode of the bus cycl e.

• For MC68K #1, this pin inputs the R/W# signal.

RD/WR# I 79 CS Input

• For MC68K #2, this pin inputs the R/W# signal.

• For Generic #1, this pin inpu ts the read comm and f or the upper data byte (RD1#).

• For Generic #2, this pin must be tied to IO V

See “Host Bus Interface Pin Mapping” for summary.

Hardware Functional Specification S1D13704 Issue Date: 01/02/08 X26A-A-001-04

Page 28

Page 20 Epson Research and Development

Vancouver Design Center

Pin Names Type Pin # Cell

RESET#

RD# I 76 CS Input

WAIT# O 2 TS2

Impedance

RESET# I 73 CS 0

State

High

Description

This pin has multiple functions.

• For SH-3/SH-4 mode, this pin in put s the read si gna l (RD#).

• For MC68K #1, this pin must be tied to IO V

• For MC68K #2, this pin inputs the bus size bit 1 (SIZ1).

• For Generic #1, this pin inputs the read c ommand f or the lower data byte (RD0#).

• For Generic #2, this pi n input s th e read command (RD#).

See “Host Bus Interface Pin Mapping” for summary. This pin has multiple functions.

• For SH-3 mode, this pin outputs the wait request signal (WAIT#).

• For SH-4 mode, this pin outputs the device ready signal (RDY#).

• For MC68K #1, this pin outputs the data transf e r acknowledge signal (DTACK#).

• For MC68K #2, this pin outputs the data transf e r an d size acknowledge bit 1 (DSACK1#).

• For Generic #1, this pin outputs the wait signal (WAIT#).

• For Generic #2, this pin outputs the wait signal (WAIT#).

See “Host Bus Interface Pin Mapping” for summary. Active low input to set all interna l reg isters to the defau lt state

and to force all signals to their inactive states.

5.2.2 LCD Interface

Pin Name T ype Pin # Cell

30, 31, 32,

FPDAT[7:0] O

33, 34, 35,

CN3 0 Panel Data

36, 37

FPDAT[10:8]

FPDAT11

I/O

24, 25, 26 CN3 Input

23 CN3 Input

FPFRAME O 39 CN3 0 Frame Pulse

RESET#

State

These pins have multiple functions.

• Panel Data bits [10:8] for TFT/D-TFD panels.

• General Purpose Input/Output pins GPIO[3:1].

These pins should be connected to IO V See “LCD Interface Pin Mapping” for summary.

This pin has multi ple functions.

• Panel Data bit 11 for TFT/D-TFD panels.

• Gen eral Purpose Input/Output pin GPIO4.

• Inverse Video select pin.

This pin should be connected to IO V “LCD Interface Pin Mappi ng” for summary.

Description

when unused.

when unused. See

S1D13704 Hardware Functional Specification X26A-A-001-04 Issue Date: 01/02/08

Page 29

Epson Research and Development Page 21

Vancouver Design Center

Pin Name Type Pin # Cell

RESET#

State

FPLINE O 38 CN3 0 Line Pulse

FPSHIFT O 28 CN3 0 Shift Clock

LCDPWR O 43 CO1

0 if CNF4 = 1 1 if CNF4 = 0

LCD Power Control This pin has multiple functions.

DRDY O 42 CN3 0

See “LCD Interface Pin Mapping” for summary.

5.2.3 Clock Input

Pin Name Type Pin # Driver Description

CLKI I 51 C Input Clock

5.2.4 Miscellaneous

Pin Name Type Pin # Cell

45, 46, 47,

48, 49

CS/

TS1

CNF[4:0] I

GPIO0

I/O,

TESTEN I 44 CD

RESET#

State

As set by hardware

Input

High

Impedance

These inputs are used to configure the S1D13704 - see “Summary of Configu rati on Options”.

Must be connected directly to IO V This pin has multiple functions - see REG[03h] bit 2.

Test Enable input. This input must be connected to V

Description

• TFT/D-TFD Display Enable (DRDY).

• LCD Backplane Bias (MOD).

• Second Shift Clock (FPSHIFT2).

Description

or VSS.

• General Purpose Input/Output pin.

• Hardware Po wer Save.

5.2.5 Power Supply

Pin Name Type Pin # Driver Description

COREVDD P

1, 21, 41,

PCore V

IOVDD P 10, 29 , 52 P IO V

20, 27, 40,

VSS P

50, 60, 72,

P Comm on V

Hardware Functional Specification S1D13704 Issue Date: 01/02/08 X26A-A-001-04

Page 30

Page 22 Epson Research and Development

Vancouver Design Center

5.3 Summary of Configuration Options

Table 5-1: Summary of Power On/Reset Options

Configuration

CNF4 Active high (On) LCDPWR polarity Active low (On) LCDPWR polarity CNF3 Big Endian Little Endian

Select host bus interface as follows:

CNF2 CNF1 CNF0 BS# Host Bus

0 0 0 X SH-4 interface 0 0 1 X SH-3 interface 010Xreserved

CNF[2:0]

0 1 1 X MC68K #1, 16-bit 1 0 0 X reserved 1 0 1 X MC68K #2, 16-bit 1100reserved 1101reserved 1110Generic #1, 16-bit 1111Generic #2, 16-bit

Power On/Reset State

5.4 Host Bus Interface Pin Mapping

Table 5-2: Host Bus Interface Pin Mapping

S1D13704

Pin Names

AB[15:1] A[15:1] A[15:1] A[15:1] A[15:1] A[15:1] A[15:1]

AB0 A0 A0 LDS# A0 A0 A0

DB[15:0] D[15:0] D[15:0] D[15:0] D[31:16] D[15:0] D[15:0]

WE1# WE1# WE1# UDS# DS# WE1# BHE#

CS# CSn# CSn# External Decode External Decode External Decode External Decode

BCLK CKIO CKIO CLK CLK BCLK BCLK

BS# BS# BS# AS# AS# connect to V

RD/WR# RD/WR# RD/WR# R/W# R/W# RD1# connect to IO V

RD# RD# RD# connect to IO V

WE0# WE0# WE0# connect to IO V

WAIT# WAIT# RDY# DTACK# DSACK1# WAIT# WAIT#

SH-3 SH-4 MC68K #1 MC68K #2 Generic #1 Generic #2

connect to IO V

SIZ1 RD0# RD# SIZ0 WE0# WE#

RESET# RESET# RESET# RESET# RESET# RESET# RESET#

S1D13704 Hardware Functional Specification X26A-A-001-04 Issue Date: 01/02/08

Page 31

Epson Research and Development Page 23

Vancouver Design Center

5.5 LCD Interface Pin Mapping

Table 5-3: LCD Interface Pin Mapping

Monochrome Passive Panel Color Passive Panel Color TFT/D-TFD

S1D13704

Pin Name

FPFRAME FPFRAME

FPLINE FPLINE

FPSHIFT FPSHIFT

DRDY MOD MOD MOD MOD FPSHIFT2 MOD MOD DRDY FPDAT0 driven 0 D0 LD0 driven 0 D0 D0 LD0 R2 R3 FPDAT1 driven 0 D1 LD1 driven 0 D1 D1 LD1 R1 R2 FPDAT2 driven 0 D2 LD2 driven 0 D2 D2 LD2 R0 R1 FPDAT3 driven 0 D3 LD3 driven 0 D3 D3 LD3 G2 G3 FPDAT4 D0 D4 UD0 D0 D4 D4 UD0 G1 G2 FPDAT5 D1 D5 UD1 D1 D5 D5 UD1 G0 G1 FPDAT6 D2 D6 UD2 D2 D6 D6 UD2 B2 B3 FPDAT7 D3 D7 UD3 D3 D7 D7 UD3 B1 B2 FPDAT8 GPIO1 GPIO1 GPIO1 GPIO1 GPIO1 GPIO1 GPIO1 B0 B1 FPDAT9 GPIO2 GPIO2 GPIO2 GPIO2 GPIO2 GPIO2 GPIO2 GPIO2 R0

FPDAT10 GPIO3 GPIO3 GPIO3 GPIO3 GPIO3 GPIO3 GPIO3 GPIO3 G0

FPDAT11

4-bit

Single

GPIO4/

HW Video

Invert

8-bit

Single

GPIO4/

HW Video

Invert

8-bit Dual

GPIO4/

HW Video

Invert

4-bit

Single

GPIO4/

HW Video

Invert

8-bit

Single

Format 1

GPIO4/

HW Video

Invert

8-bit

Single

Format 2

GPIO4/

HW Video

Invert

8-bit Dual 9-bit 12-bit

GPIO4/

HW Video

Invert

GPIO4 B0

Note

1. Unused GPIO pins must be connected to IO VDD.

2. Hardware Video Invert is enabled on FPDAT11 by REG[02h] bit 1.

Hardware Functional Specification S1D13704 Issue Date: 01/02/08 X26A-A-001-04

Page 32

Page 24 Epson Research and Development

Vancouver Design Center

6 D.C. Characteristics

Table 6-1: Absolute Maximum Ratings

Symbol Parameter Rating Units

Core V

IO V

OUT

STG

SOL

Symbol Parameter Condition Min Typ Max Units

Core V

IO V

OPR

Supply Voltage VSS - 0.3 to 4.6 V Supply Voltage VSS - 0.3 to 6.0 V Input Voltage VSS - 0.3 to IO VDD + 0.5 V Output Voltage VSS - 0.3 to IO VDD + 0.5 V Storage Temperature -65 to 150 ° C Solder Temperature/Time 260 for 10 sec. max at lead ° C

Table 6-2: Recommended Operating Conditions

Supply Voltage VSS = 0 V 3.0 3.3 3.6 V Supply Voltage VSS = 0 V 3.0 3.3/5.0 5.5 V Input Voltage V

Operating Temperature -40 25 85 ° C

IO V

Table 6-3: Input Specifications

Symbol Parameter Condition Min Typ Max Units

C HR

T+

T-

Low Level Input Voltage

CMOS inputs

High Level Input Voltage

CMOS inputs

Positive-going Threshold

CMOS Schmitt inputs

Negative-going Threshold

CMOS Schmitt inputs

Input Leakage Current

Input Pin Capacitance 10 pF Pull Down Resistance VI = V

IO VDD = 3.3

5.0

IO VDD = 3.3

5.0

IO VDD = 3.3

5.0

IO VDD = 3.3

5.0

= Max

= V

0.8

1.0

2.0

3.5

1.1

2.0

0.6

0.8

2.4

4.0

1.8

3.1

-1 1 µA

50 100 300 kΩ

V V

S1D13704 Hardware Functional Specification X26A-A-001-04 Issue Date: 01/02/08

Page 33

Epson Research and Development Page 25

Vancouver Design Center

Table 6-4: Output Specifications

Symbol Parameter Condition Min Typ Max Units

Low Level Output Voltage

C C

OUT BID

Type 1 - TS1, CO1 Type 2- TS2, CO2 Type 3 - TS3, CO3

High Level Output Volt ag e Type 1 - TS1, CO1 Type 2- TS2, CO2 Type 3 - TS3, CO3

Output Leakage Curren t

Output Pin Capacitanc e 10 pF Bidirectional Pin Capaci tanc e 10 pF

= 3mA

= 6mA

= 12mA

= -1.5 mA

= -3 mA

= -6 mA

= MAX

= V

0.4 V

IO VDD - 0.4 V

-1 1 µA

Hardware Functional Specification S1D13704 Issue Date: 01/02/08 X26A-A-001-04

Page 34

Page 26 Epson Research and Development

Vancouver Design Center

7 A.C. Characteristics

Conditions: IO VDD = 3.3V ± 10% or IO VDD = 5V ± 10%

= -40° C to 85° C

and T

rise

= 60pF (Bus/MPU Interface)

= 60pF (LCD Panel Interface)

7.1 Bus Interface Timing

7.1.1 SH-4 Interface Timing

CKIO

t2 t3

for all inputs must be < 5 nsec (10% ~ 90%)

fall

A[16:0]

RD/WR#

BS#

CSn#

WEn#

RD#

RDY#

D[15:0]

(write)

D[15:0]

(read)

t6 t7

t11

t12

t14

t16

VALID

t15

t10

t13

t17

Figure 7-1: SH-4 Timing

Note

The SH-4 Wait State Control Register for the area in which the S1D13704 resides must be set to a non-zero value. The SH-4 read-to-write cycle transition must be set to a non-zero value (with reference to BUSCLK).

S1D13704 Hardware Functional Specification X26A-A-001-04 Issue Date: 01/02/08

Page 35

Epson Research and Development Page 27

Vancouver Design Center

Table 7-1: SH-4 Timing

Symbol Parameter Min Max Units

CKIO

t10 t11 t12 t13 t14 t15 t16 t17

Bus Clock frequency

Bus Clock period t2 t3 t4 t5 t6 t7 t8 t9

Clock pulse wid th high

Clock pulse wid th lo w

A[15:0], RD/WR# setup to CKIO

A[15:0], RD/WR# hold from CS#

BS# setup

BS# hold

CSn# setup

Falling edge RD# to DB[15:0] driven

Rising edge CSn# to RDY# high impedance

Falling edge CSn# to RDY# drive n

CKIO to RDY# low

Rising edge CSn# to RDY# high

DB[15:0] setup to 2

CKIO after BS# (write cycle) DB[15:0] hold (write cycle) DB[15:0] valid to RDY# fallin g edge setup ti me (read c ycle) Rising edge RD# to DB[15: 0] high impedance (read cycle)

050MHz

1/f

CKIO

17 ns 16 ns

0ns 0ns 5ns 5ns 0ns

25 ns

t1 ns 20 ns 20 ns 20 ns

0ns 0ns 0ns

10 ns

Note

CKIO may be turned off (held low) between accesses - see Section 13.5, “Turning Off BCLK Between Accesses” on page 86

Hardware Functional Specification S1D13704 Issue Date: 01/02/08 X26A-A-001-04

Page 36

Page 28 Epson Research and Development

Vancouver Design Center

7.1.2 SH-3 Interface Timing

CKIO

A[16:0], M/R#

RD/WR#

BS#

CSn#

t2 t3

t6 t7

WEn#

RD#

WAIT#

D[15:0]

(write)

D[15:0]

(read)

t10

Hi-Z

t14

Hi-Z

t16

Hi-Z

t11

t12

t13

t15

VALID

Figure 7-2: SH-3 Bus Timing

Note

The SH-3 Wait State Control Register for the area in which the S1D13704 resides must be set to a non-zero value.

S1D13704 Hardware Functional Specification X26A-A-001-04 Issue Date: 01/02/08

Page 37

Epson Research and Development Page 29

Vancouver Design Center

Table 7-2: SH-3 Bus Timing

Symbol Parameter Min Max

CKIO

t10 t11 t12 t13 t14 t15 t16

Bus Clock frequency Bus Clock perio d

t2 t3 t4 t5 t6 t7 t8 t9

Clock pulse wid th high Clock pulse wid th lo w A[15:0], RD/WR# setup to CKIO A[15:0], RD/WR# hold from CS# BS# setup BS# hold CSn# setup Falling edge RD# to DB[15:0] driven Rising edge CSn# to WAIT# high impedance Falling edge CSn# to WAIT# dri ve n CKIO to WAIT# delay

DB[15:0] setup to 2

CKIO after BS# (write cycle) DB[15:0] hold from rising edge of WEn# (write cycle) DB[15:0] valid to RDY# fallin g edge s etup ti me (read cycle) Rising edge RD# to DB[15: 0] high impedance (read cycle)

One Software WAIT State Required

050MHz

1/f

CKIO

17 ns 16 ns

0ns 0ns 5ns 5ns 0ns

0ns 0ns 0ns

Units

25 ns 10 ns 15 ns 20 ns

10 ns

Note

CKIO may be turned off (held low) between accesses - see Section 13.5, “Turning Off BCLK Between Accesses” on page 86

Hardware Functional Specification S1D13704 Issue Date: 01/02/08 X26A-A-001-04

Page 38

Page 30 Epson Research and Development

Vancouver Design Center

7.1.3 Motorola M68K #1 Interface Timing

CLK

A[15:1]

CS#

R/W#

AS#

UDS#, LDS#

DTACK#

D[15:0]

(write

D[15:0]

(read)

INVALID

Hi-Z

VALID

t10

VALID

t11

Hi-Z

Figure 7-3: M68K #1 Bus Timing (MC68000)

Table 7-3: M68K #1 Bus Timing (MC68000)

Symbol Parameter Min Max Units

CLK

t1 A[15:1], CS# valid before AS# falling ed ge 0 ns t2 A[15:1], CS# hold from AS# rising edge 0 ns t3 AS# low to DTACK# driven high 16 ns t4 CLK to DTACK# low 15 ns t5 AS# high to DTACK# high 20 ns t6 AS# high to DTACK# high impedance T t7 UDS#, LDS# falling edge to D[15:0] valid (write cycle) T t8 D[15:0] hold from AS# rising edge (write cycle) 0 ns

t9 UDS#, LDS# falling edge to D[15:0] driven (read cycle) 15 ns t10 D[15:0] valid to DTACK# falling edge (read cycle) 0 ns t11 UDS#, LDS# rising edge to D[15:0] high impedance 10 ns

Bus Clock Frequency 0 33 MHz Bus Clock period 1/f

CLK

CLK CLK

Note

CLK may be turned off (held low) between accesses - see Section 13.5, “Turning Off BCLK Between Accesses” on page 86

S1D13704 Hardware Functional Specification X26A-A-001-04 Issue Date: 01/02/08

Page 39

Epson Research and Development Page 31

Vancouver Design Center

7.1.4 Motorola M68K #2 Interface Timing

CLK

A[15:0]

CS#

SIZ0, SIZ1

R/W#

AS#

DS#

DSACK1#

D[31:16]

(write)

D[31:16]

(read)

Hi-Z

VALID

t10

Hi-Z

Figure 7-4: M68K #2 Timing (MC68030)

Table 7-4: M68K #2 Timing (MC68030)

Symbol Parameter Min Max Units

CLK

Bus Clock frequency 0 33 MHz Bus Clock period 1/f

CLK

t1 A[15:0], CS#, SIZ0, SIZ1 valid before AS# falling edge 0 ns t2 A[15:0], CS#, SIZ0, SIZ1 hold from AS#, DS# rising edge 0 ns t3 AS# low to DSACK1# driven high 22 ns t4 CLK to DSACK1# low 18 ns t5 AS# high to DSACK1# high 26 ns t6 AS# high to DSACK1# high impedance T t7 DS# falling edge to D[31:16] valid (write cycle) T

CLK

/ 2 t8 AS#, DS# rising edge to D[31:16] invalid (write cycle) 0 ns t9 D[31:16] valid to DSACK1# low (read cycle) 0 ns

t10 AS#, DS# rising edge to D[31:16] high impedance 20 ns

Note

CLK may be turned off (held low) be tween accesses - see Section 13.5, “Turning Off BCLK Between Accesses” on page 86

Hardware Functional Specification S1D13704 Issue Date: 01/02/08 X26A-A-001-04

Page 40

Page 32 Epson Research and Development

Vancouver Design Center

7.1.5 Generic #1 Interfac e Timing

BCLK

A[15:0]

CS#

WE0#,WE1# RD0#, RD1#

D[15:0]

(write)

D[15:0]

(read)

WAIT#

Hi-Z

VALID

Hi-Z

t10

Hi-Z

Figure 7-5: Generic #1 Timing

Table 7-5: Generic #1 Timin g

Symbol Parameter Min Max Units

BCLK

t2 t3 WE0#, WE1# low to D[15:0] valid (write cycle) T

Bus Clock frequency 0 50 MHz Bus Clock pe riod 1/f A[15:0], CS# valid to WE0#, WE1# low (write cyc le) or RD0#, RD1# low (read cycle) WE0#, WE1# high (write cycle) or RD0#, R D1# high (r e ad cy cl e) to A[15 :0], CS# invalid

BCLK

0ns

BCLK

MHz

t4 RD0#, RD1# low to D[15:0] driven (read cycle) 17 ns t5 WE0#, WE1# high to D[15:0] invalid (write cycle) 0 ns t6 D[15:0] valid to WAIT# high (read cycle) 0 ns t7 RD0#, RD1# high to D[15:0] high impedance (read cycle) 10 ns

WE0#, WE1# low (write cycle) or RD0#, RD1# low (read cy c le) to WAIT# driven low

16 ns

t9 BCLK to WAIT# high 16 ns

t10

WE0#, WE1# high (write cycle) or RD0#, RD1# high (read cycl e) to WAIT# high impedance

11 ns

Note

BCLK may be turned off (held low) between accesses - see Section 13.5, “Turning Off BCLK Between Accesses” on page 86

S1D13704 Hardware Functional Specification X26A-A-001-04 Issue Date: 01/02/08

Page 41

Epson Research and Development Page 33

Vancouver Design Center

7.1.6 Generic #2 Interface Timing

BCLK

A[15:0]

BHE#

CS#

WE#,RD#

D[15:0]

(write)

D[15:0]

(read)

WAIT#

Hi-Z

VALID

Hi-Z

t10

Hi-Z

Figure 7-6: Generic #2 Timing

Table 7-6: Generic #2 Timing

Symbol Parameter Min Max Units

BCLK

Bus Clock frequency 0 50 MHz Bus Clock period 1/f

BCLK

t1 A[15:0], BHE#, CS# valid to WE#, RD# low 0 ns t2 WE#, RD# high to A[15:0], BHE#, t3 WE# low to D[15:0] valid (write cycle) T

CS# invalid 0 ns

BCLK

t4 WE# high to D[15:0] invalid (write cy cl e) 0 ns t5 RD# low to D[15:0] driven (read cycle) 16 ns t6 D[15:0] valid to WAIT# high (read cycle) 0 ns t7 RD# high to D[15:0] high impedance (read cycle) 10 ns t8 WE#, RD# low to WAIT# driven low 14 ns t9 BCLK to WAIT# high 16 ns

t10 WE#, RD# high to WAIT# high impedance 11 ns

Note

BCLK may be turned off (held low) between accesses - see Section 13.5, “Turning Off BCLK Between Accesses” on page 86

Hardware Functional Specification S1D13704 Issue Date: 01/02/08 X26A-A-001-04

Page 42

Page 34 Epson Research and Development

Vancouver Design Center

7.2 Clock Input Requirements

Clock Input Waveform

PWL

90%

10%

PWH

IH IL

CLKI

Figure 7-7: Clock Input Requirements

Table 7-7: Clock Input Requirements

Symbol Parameter Min Max Units

CLKI

PWH

PWL

Input Clock Frequency (CLKI) 0 50 MHz Input Clock period (CLKI) 1/f

CLKI

Input Clock Pulse Width High (CLKI) 8 ns Input Clock Pulse Width Low (CLKI) 8 ns Input Clock Fall Time (10% - 90%) 5 ns Input Clock Rise Time (10% - 90%) 5 ns

Note

When CLKI is > 25MHz it must be divided by 2 (REG[02h] bit 4 = 1).

S1D13704 Hardware Functional Specification X26A-A-001-04 Issue Date: 01/02/08

Page 43

Epson Research and Development Page 35

Vancouver Design Center

7.3 Display Interface

7.3.1 Power On/Reset Timing

RESET#

REG[03h] bits [1:0]

LCDPWR

(CNF4 = 1)

LCDPWR

(CNF4 = 0)

FPLINE

FPSHIFT

FPDAT

FPFRAME

DRDY

00 11

ACTIVE

Figure 7-8: LCD Panel Power On/Reset Timing

Symbol Parameter Min Typ Max Units

REG[03h] to FPLINE, FPFRAME, FPSHIFT, FPDAT, DRDY active FPLINE, FPFRAME, FPSHIFT, FPDAT, DRDY active to LCDPWR

FPFRAME

0Frames

Note

Where T

FPFRAME

is the period of FPFRAME and T

is the period of the pixel clock.

PCLK

Hardware Functional Specification S1D13704 Issue Date: 01/02/08 X26A-A-001-04

Page 44

Page 36 Epson Research and Development

Vancouver Design Center

7.3.2 Power Down/Up Timing

LCDPWR Override

(REG[03h] bit 3)

HW Power Save

Software Power Save

REG[03h] bits [1:0]

11 00 11 00 11

FP Signals

LCDPWR

(polarity set by CNF4)

Active Inactive Active Inactive Active

Active Active ActiveInactive Inactive

Figure 7-9: Power Down/Up Timing

Table 7-8: Power Down/Up Timing

Symbol Parameter Min Typ Max Units

HW Power Save active to FPLINE, FPFRAME, FPSHIFT, FPDAT, DRDY

inactive - LCDPWR Override = 1 HW Power Save inactive to FPLINE, FPFRAME, FPSHIFT, FPDAT, DRDY

active - LCDPWR Override = 1 HW Power Save active to FPLINE, FPFRAME, FPSHIFT, FPDAT, DRDY

inactive - LCDPWR Override = 0 LCDPWR low to FPLINE, FPFRAME, FPSHIFT, FPDAT, DRDY inactive

- LCDPWR Override = 0 HW Power Save inactive to FPLINE, FPFRAME, FPSHIFT, FPDAT, DRDY,

LCDPWR active - LCDPWR Override = 0

127 Frame

0Frame

t6 LCDPWR Override active (1) to LCDPWR inactive 1 Frame t7 LCDPWR Override inactive (1) to LCDPWR active 1 Frame

1Frame

S1D13704 Hardware Functional Specification X26A-A-001-04 Issue Date: 01/02/08

Page 45

Epson Research and Development Page 37

Vancouver Design Center

7.3.3 Single Monochrome 4-Bit P a nel Timing

FPFRAME

FPLINE

DRDY (MOD)

FPDAT[7:4]

LINE1 LINE2 LINE3 LINE4 LINE239 LINE240

FPLINE

DRDY (MOD)

FPSHIFT

FPDAT7 FPDAT6

FPDAT5 FPDAT4

* Diagram drawn with 2 FPLINE vertical blank period Example timing for a 320x240 panel For this timing diag ram Mask FPSHIFT, REG[01h] bit 3, is set to 1

1-1 1-5

1-2 1-6 1-318 1-3

1-7

1-4 1-8

VDP

HDP HNDP

VNDP

1-317

1-319 1-320

LINE1 LINE2

Figure 7-10: Single Monoch rome 4-Bi t Panel Timing

VDP = V er ti cal Di splay Period = (REG[06h] bits 1-0, REG [05h] bits 7-0) + 1 Lines VNDP = Vertical Non-Display Period = REG[0Ah] bits 5-0 Lines HDP = Horizontal Displa y Period = ((REG[04h] bits 6-0) + 1) x 8Ts HNDP = Horizonta l Non-Dis pl ay P er iod = (REG[08h] + 4) x 8Ts

Hardware Functional Specification S1D13704 Issue Date: 01/02/08 X26A-A-001-04

Page 46

Page 38 Epson Research and Development

Vancouver Design Center

Sync Timing

Frame Pulse

Line Pulse

DRDY (MOD)

Data Timing

Line Pulse

Shift Pu l se

FPDAT[7:4]

Note: For this timing diagram Mask FPSHIFT, REG[01h] bit 3, is set to 1

t8 t9

t14 t10t11

t12 t13

Figure 7-11: Single Monoc hrome 4-Bit Panel A.C. Timing

Symbol Parameter Min Typ Max Units

t1 Frame Pulse setup to Line Pulse fallin g edge note 2 (note 1) t2 Frame Pulse hold from Line Pulse falling edge 9 Ts t3 Line Pulse period note 3 t4 Line Pulse pulse width 9 Ts t5 MOD delay from Line Pulse rising edg e 1 Ts t6 Shift Pulse falling edge to Line Pulse rising edge note 4 t7 Shift Pulse falling edge to Line Pulse falling edge note 5 t8 Line Pulse falling edge to Shift Pulse falling edge t14 + 2 Ts

t9 Shift Pulse period 4 Ts t10 Shift Pulse pulse width low 2 Ts t11 Shift Pulse pulse width high 2 Ts t12 FPDAT[7:4] setup to Shift Pulse falling edge 2 Ts t13 FPDAT[7:4] hold to Shift Pulse falling edge 2 Ts t14 Line Pulse falling edge to Shift Pulse rising edge 23 Ts

1. Ts = pixel clock period

2. t1

3. t3

4. t6

5. t7

= t3

min

= [((REG[04h] bits 6-0)+1) x 8 + ((REG[0 8h] bits 4-0) + 4) x 8]Ts

min

= [(REG[08h] bits 4-0) x 8 + 2]Ts

min

= [(REG[08h] bits 4-0) x 8 + 11]Ts

min

- 9Ts

S1D13704 Hardware Functional Specification X26A-A-001-04 Issue Date: 01/02/08

Page 47

Epson Research and Development Page 39

Vancouver Design Center

7.3.4 Single Monochrome 8-Bit P a nel Timing

FPFRAME

FPLINE

DRDY (MOD)

FPDAT[7:0]

FPLINE

DRDY (MOD)

FPSHIFT

FPDAT7 FPDAT6 FPDAT5

FPDAT4 FPDAT3

FPDAT2 FPDAT1

FPDAT0

VDP

LINE1 LINE2 LINE3 LINE4 LINE479 LINE480

HDP

1-1 1-9

1-2 1 -1 0 1-634 1-3

1-11 1-4 1-1 2 1-5 1-13

1-6 1-14 1-7 1-15 1-639 1-8 1-16

VNDP

1-633

1-635 1-636 1-637 1-638

1-640

LINE1 LINE2

HNDP

* Diagram drawn with 2 FPLINE vertical blank period Example timing for a 640x480 panel For this t iming diagram Mask FPSH IFT, REG[01h] bit 3, is set to 1

Figure 7-12: Single Monoch rome 8-Bi t Panel Timing

Hardware Functional Specification S1D13704 Issue Date: 01/02/08 X26A-A-001-04

Page 48

Page 40 Epson Research and Development

Vancouver Design Center

Sync Timing

Frame Pulse

Line Pulse

MOD

Data Timing

Line Pulse

Shift Pulse

FPDAT[7:0]

Note: For this timing diagram Mask FPSHIFT, REG[01h] bit 3, is set to 1

t8 t9

t14

t12 t13

t10t11

Figure 7-13: Single Monoc hrome 8-Bit Panel A.C. Timing

Symbol Parameter Min Typ Max Units

t1 Frame Pulse setup to Line Pulse falling edge note 2 (note 1) t2 Frame Pulse hold from Line Pulse fall ing ed ge 9 Ts t3 Line Pulse period note 3 t4 Line Pulse pulse width 9 Ts t5 MOD delay from Line Pulse risin g edge 1 Ts t6 Shift Pulse falling edge to Line Pulse risin g edge note 4 t7 Shift Pulse falling edge to Line Pulse fallin g edge note 5 t8 Line Pulse falling edge to Shift Pul se fal lin g edge t14 + 4 Ts

t9 Shift Pulse period 8 Ts t10 Shift Pulse puls e width low 4 Ts t11 Shift Pulse puls e width high 4 Ts t12 FPDAT[7:0] setup to Shift Pulse falling edge 4 Ts t13 FPDAT[7:0] hold to Shift Pulse falling edge 4 Ts t14 Line Pulse fal lin g edge to Shift Pulse rising edge 23 Ts

1. Ts = pixel clock period

2. t1

3. t3

4. t6

5. t7

= t3

min

= [((REG[04h] bits 6-0)+1) x 8 + ((REG[0 8h] bits 4-0) + 4) x 8]Ts

min

= [(REG[08h] bits 4-0) x 8 + 4]Ts

min

=[(REG[08h] bits 4-0) x 8 + 13]Ts

min

- 9Ts

S1D13704 Hardware Functional Specification X26A-A-001-04 Issue Date: 01/02/08

Page 49

Epson Research and Development Page 41

Vancouver Design Center

7.3.5 Single Color 4-Bit Panel Timing

FPFRAME

FPLINE

DRDY (MOD)

FPDAT[7:4]

FPLINE

DRDY (MOD)

FPSHIFT

FPDAT7 FPDAT6 FPDAT5 FPDAT4

* Diagram d rawn with 2 FPLINE vertical blank period Example timing for a 640x480 pane l

1-R1 1-G1 1-B1 1-R2

VDP

LINE1 LINE2 LINE3 LINE4

1-G2

1-B3

1-B2

1-R4

1-R3

1-G4

1-G3

1-B4

HDP

LINE479 LINE480

VNDP

LINE1 LINE2

HNDP

1-B319 1-R320 1-G320

1-B320

Figure 7-14: Single Color 4-Bit Panel Timing

Hardware Functional Specification S1D13704 Issue Date: 01/02/08 X26A-A-001-04

Page 50

Page 42 Epson Research and Development

Vancouver Design Center

Sync Timing

Data Timing

Frame Pulse

Line Pulse

DRDY (MOD)

Line Pulse

Shift Pulse

FPDAT[7:4]

t8 t9

t14

t12 t13

t10t11

Figure 7-15: Single Color 4-Bit Panel A.C. Timing

Symbol Parameter Min Typ Max Units

t1 Frame Puls e setup to Line Pulse falling edge note 2 (note 1) t2 Frame Pulse hold from Line Pulse falling edge 9 Ts t3 Line Pulse period note 3 t4 Line Pulse pulse width 9 Ts t5 MOD delay from Line Pulse rising edge 1 Ts t6 Shift Pulse falling edge to Line Pulse rising edge note 4 t7 Shift Pulse falling edge to Line Pulse falling edge note 5 t8 Line Pulse falling edge to Shift Pulse falling edge t14 + 0.5 Ts t9 Shift Pulse period 1 Ts

t10 Shift Pulse pulse width low 0.5 Ts t11 Shift Pulse pulse width high 0.5 Ts t12 FPDAT[7:4] setup to Shift Pulse falling edge 0.5 Ts t13 FPDAT[7:4] hold to Shift Pulse falling edge 0.5 Ts t14 Line Pulse falling edge to Shift Pulse rising edge 23 Ts

1. Ts = pixel clock period

2. t1

3. t3

4. t6

5. t7

= t3

min

= [((REG[04h] bits 6-0)+1) x 8 + ((REG[0 8h] bits 4-0) + 4) x 8]Ts

min

= [(REG[08h] bits 4-0) x 8 + 0.5]Ts

min

= [(REG[08h] bits 4-0) x 8 + 9.5]Ts

min

- 9Ts

S1D13704 Hardware Functional Specification X26A-A-001-04 Issue Date: 01/02/08

Page 51

Epson Research and Development Page 43

Vancouver Design Center

7.3.6 Single Color 8-Bit Panel Timing (Format 1)

FPFRAME

FPLINE

FPDAT[7:0]

FPLINE

FPSHIFT

FPSHIFT 2

FPDAT7 FPDAT6 FPDAT5 FPDAT4 FPDAT3 FPDAT2 FPDAT1 FPDAT0

LINE1 LINE2 LINE3 LINE4

1-R1

1-G1

1-G6

1-B6

1-B1

1-R2

1-R7

1-G7

1-G2

1-B2

1-B7

1-R8

1-R3

1-G3

1-G8

1-B8

1-B3

1-R4

1-R9

1-G9

1-G4

1-B4

1-B9

1-R10

1-R5

1-G5

1-G10

1-B10

1-B5

1-R6

1-R11

1-G11

1-B11 1-G12 1-R13

1-B13 1-G14 1-R15 1-B15 1-G16

VDP

HDP

1-R12 1-B12 1-G13

1-R14 1-B14 1-G15 1-R16 1-B16

LINE479 LINE480

VNDP

LINE1 LINE2

HNDP

1-R636 1-B636 1-G637

1-R638

1-B638

1-G639 1-R640 1-B640

* Diagram drawn with 2 FPLINE vertical blank period Example timing for a 640x480 panel

Figure 7-16: Single Color 8-Bit Panel Timing (Format 1)

Hardware Functional Specification S1D13704 Issue Date: 01/02/08 X26A-A-001-04

Page 52

Page 44 Epson Research and Development

Vancouver Design Center

Sync Timing

Data Timing

Frame Pulse

Line Pulse

t6a

t6b

t7a

Shift Pulse 2

t7b

Shift Pulse

FPDAT[7:0]

t8 t9

t14

t12

t13

t12 t13

Figure 7-17: Single Color 8-Bit Panel A.C. Timing (Format 1)

t10t11

Symbol Parameter Min Typ Max Units

t1 Frame Pulse setup to Line Pulse falling edge note 2 (note 1) t2 Frame Pulse hold from Line Pulse falling edge 9 Ts t3 Line Pulse period note 3

t4 Line Pulse pulse width 9 Ts t6a Shift Pulse falling edge to Line Pulse rising edge note 4 t6b Shift Pulse 2 falling edge to Line Pulse rising edge note 5 t7a Shift Pulse 2 fa lling edge to Line Pulse falling edge note 6 t7b Shift Pulse falling edge to Line Pulse falling edge note 7

t8 Line Pulse falling edge to Shift Pulse rising, Shift Puls e 2 falling edge t14 + 2 Ts

t9 Shift Pulse 2, Shift Pulse period 4 Ts t10 Shift Pulse 2, Shift Pulse pulse width low 2 Ts t11 Shift Pulse 2, Shift Pulse pulse width high 2 Ts t12 FPDAT[7:0] setup to Shift Pulse 2, Shift Pulse falling edge 1 Ts t13 FPDAT[7:0] hold to Shift Pulse 2, Shift Pulse falling edge 1 Ts t14 Line Pulse falling edge to Shift Pulse rising edge 23 Ts

1. Ts = pixel clock period

2. t1

3. t3

4. t6a

5. t6b

6. t7a

7. t7b

= t3

min

= [((REG[04h] bits 6-0)+1) x 8 + ((REG[0 8h] bits 4-0) + 4) x 8]Ts

min

= [(REG[08h] bits 4-0) x 8 + t13 - t10]Ts

min

= [(REG[08h] bits 4-0) x 8 + t13]Ts

min

= [(REG[08h] bits 4-0) x 8 + 11]Ts

min

= [(REG[08h] bits 4-0) x 8 + 11] - t10]Ts

min

- 9Ts

S1D13704 Hardware Functional Specification X26A-A-001-04 Issue Date: 01/02/08

Page 53

Epson Research and Development Page 45

Vancouver Design Center

7.3.7 Single Color 8-Bit Panel Timing (Format 2)

FPFRAME

FPLINE

DRDY (MOD)

FPDAT[7:0]

FPLINE

DRDY (MOD)

FPSHIFT

FPDAT7 FPDAT6 FPDAT5 FPDAT4 FPDAT3 FPDAT2 FPDAT1 FPDAT0

VDP

LINE1 LINE2 LINE3 LINE4 LINE479 LINE480

HDP

1-R1

1-B3

1-G6

1-G1

1-R4

1-B6

1-B1

1-G 4

1-R7

1-R2

1-B4

1-G7

1-G2

1-R5

1-B7

1-B2

1-G 5

1-R8

1-R3

1-B5

1-G8

1-G3

1-R6

1-B8

VNDP

LINE1 LINE2

HNDP

1-G638 1-B638 1-R639

1-G639 1-B639

1-R640 1-G640 1-B640

* Diagram drawn with 2 FPLINE vertical blank period Example timing for a 640x480 panel

Figure 7-18: Single Color 8-Bit Panel Ti ming (Format 2)

Hardware Functional Specification S1D13704 Issue Date: 01/02/08 X26A-A-001-04

Page 54

Page 46 Epson Research and Development

Vancouver Design Center

Sync Timing

Data Timing

Frame Pulse

Line Pulse

DRDY (MOD)

Line Pulse

Shift Pulse

FPDAT[7:0]

t8 t9

t14 t10t11

t12 t13

Figure 7-19: Single Color 8-Bit Panel A.C. Timing (Format 2)

Symbol Parameter Min Typ Max Units

t1 Frame Pulse setup to Line Pulse falling edge note 2 (note 1) t2 Frame Pulse hold from Line Pulse fal lin g edge 9 Ts t3 Line Pulse period note 3 t4 Line Pulse pulse width 9 Ts t5 MOD delay from Line Pulse rising edge 1 Ts t6 Shift Pulse falling edge to Line Pulse rising edge note 4 t7 Shift Pulse falling edge to Line Pulse falling edge note 5 t8 Line Pulse falling edge to Shift Pulse falling edge t14 + 2 Ts

t9 Shift Pulse period 2 Ts t10 Shift Pulse pulse width low 1 Ts t11 Shift Pulse pulse width high 1 Ts t12 FPDAT[7:0] setup to Shift Pulse falling edge 1 Ts t13 FPDAT[7:0] hold to Shift Pulse falling edge 1 Ts t14 Line Pulse falling edge to Shift Pulse rising edge 23 Ts

1. Ts = pixel clock period

2. t1

3. t3

4. t6

5. t7

= t3

min

= [((REG[04h] bits 6-0)+1) x 8 + ((REG[0 8h] bits 4-0) + 4) x 8]Ts

min

= [(REG[08h] bits 4-0) x 8 + 1]Ts

min

= [(REG[08h] bits 4-0) x 8 + 10]Ts

min

- 9Ts

S1D13704 Hardware Functional Specification X26A-A-001-04 Issue Date: 01/02/08

Page 55

Epson Research and Development Page 47

Vancouver Design Center

7.3.8 Dual Monochrome 8-Bit Panel Timing

FPFRAME

FPLINE

DRDY (MOD)

FPDAT[7:0]

FPLINE

DRDY (MOD)

FPSHIFT

FPDAT7 FPDAT6 FPDAT5 FPDAT4 FPDAT3 FPDAT2 FPDAT1 FPDAT0

VDP

LINE 1/241 LINE 2/242 LINE 3/243 LINE 4/244 LINE 239/479 LINE 240/480 LINE 1/241 LINE 2/242

HDP

1-1 1-5

1-2 1-6 1-638

1-3

1-7

1-4 1-8

241-1 241-5

241-2 241-6

241-3 241-7

241-4 241-8

VNDP

HNDP

1-637

1-639

1-640

241-637

241-638

241-639

241-640

* Diagram drawn with 2 FPLINE verti cal blank period

Example timing for a 640x480 panel

Figure 7-20: Dual Monochrome 8-Bit Panel Timing

Hardware Functional Specification S1D13704 Issue Date: 01/02/08 X26A-A-001-04

Page 56

Page 48 Epson Research and Development

Vancouver Design Center

Sync Timing

Data Timing

Frame Pulse

Line Pulse

DRDY (MOD)

Line Pulse

Shift Pulse

FPDAT[7:0]

Figure 7-21: Dual Monochrome 8-Bit Panel A.C. Timing

t1 t2

t8 t9

t14 t10t11

t12 t13

Symbol Parameter Min Typ Max Units

t1 Frame Pulse setup to Line Pulse falling edge note 2 (note 1) t2 Frame Pulse hold from Line Pulse falling edge 9 Ts t3 Line Pulse period note 3 t4 Line Pulse pulse width 9 Ts t5 MOD delay from Line Pulse fall ing edge 1 Ts t6 Shift Pulse falling edge to Line Pulse rising edge note 5 t7 Shift Pulse falling edge to Lin e Pulse falling edge note 6 t8 Line Pulse falling edge to Shi ft Pulse falling edge t14 + 4 Ts

t9 Shift Pulse period 8 Ts t10 S hift Pul se pul se w idt h low 4 Ts t11 S hift Pul se pul se w idt h high 4 Ts t12 FPDAT[7:0] setup to Shift Pulse falling edge 4 Ts t13 FPDAT[7 :0] hold to Shift Pulse falling edge 4 Ts t14 Lin e Pulse fal li ng edge to Shift Pulse rising edge 39 Ts

1. Ts = pixel clock period

2. t1

3. t3

5. t6

6. t7

= t3

min

= [(((REG[04h] bits 6-0)+1) x 8 + ((REG[08h] bits 4-0) + 4) x 8) x 2]Ts

min

= [((REG[08h] bits 4-0) x 2)x 8 + 20]Ts

min

= [((REG[08h] bits 4-0) x 2)x 8 + 29]Ts

min

- 9Ts

S1D13704 Hardware Functional Specification X26A-A-001-04 Issue Date: 01/02/08

Page 57

Epson Research and Development Page 49

Vancouver Design Center

7.3.9 Dual Color 8-Bit Panel Timing

FPFRAME

FPLINE

DRDY (MOD)

FPDAT[7:0]

FPLINE

DRDY (MOD)

FPSHIFT

FPDAT7 FPDAT6 FPDAT5 FPDAT4 FPDAT3 FPDAT2 FPDAT1 FPDAT0

VDP

LINE 1/241 LINE 2/242 LINE 239/479 LINE 240/480 LINE 1/241

VNDP

HDP

1-R1

1-G1

1-B1

1-R2

241-R1

241-G1

241-B1

241-R2

1-G2

1-B2

1-R3

1-G3

241-G2

241-B2

241-R3

241-G3

1-B3

1-R4

1-G4

1-B4

241-B3

241-R4

241-G4

241-B4

1-R5

1-G5

1-B5

1-R6

241-R5

241-G5

241-B5

241-R6

1-G6

1-B6

1-R7

1-G7

241-G6

241-B6

241-R7

241-G7

1-B7

1-R8

1-G8

1-B8

241-B7

241-R8

241-G8

241-B8

1-B639

1-R640

1-G640

1-B640

241B639

241R640

241-

G640

241-

B640

HNDP

* Diagram drawn with 2 FPLINE verti cal blank period Example timing for a 640x480 panel

Figure 7-22: Dual Color 8-Bit Panel Timing

Hardware Functional Specification S1D13704 Issue Date: 01/02/08 X26A-A-001-04

Page 58

Page 50 Epson Research and Development

Vancouver Design Center

Sync Timing

Data Timing

Frame Pulse

Line Pulse

DRDY (MOD)

Line Pulse

Shift Pulse

FPDAT[7:0]

Figure 7-23: Dual Color 8-Bit Panel A.C. Timing

t1 t2

t8 t9

t14 t10t11

t12 t13

Symbol Parameter Min Typ Max Units

t1 Frame Pulse setup to Line Pulse fallin g edge note 2 (note 1) t2 Frame Pulse hold from Line Pulse falling edge 9 Ts t3 Line Pulse period note 3 t4 Line Pulse pulse width 9 Ts t5 MOD delay from Line Pulse falling ed ge 1 Ts t6 Shift Pulse falling edge to Line Pulse rising edge note 5 t7 Shift Pulse falling edge to Line Pulse falling edge note 6 t8 Line Pulse falling edge to Shift Pulse falling edge t14 + 1 Ts

1. Ts = pixel clock period

2. t1

3. t3

5. t6

6. t7

= t3

min

= [(((REG[04h] bits 6-0)+1) x 8 + ((REG[08h] bits 4-0) + 4) x 8) x 2]Ts

min

= [((REG[08h] bits 4-0) x 2)x 8 + 17]Ts

min

= [((REG[08h] bits 4-0) x 2)x 8 + 26]Ts

min

- 9Ts

S1D13704 Hardware Functional Specification X26A-A-001-04 Issue Date: 01/02/08

Page 59

Epson Research and Development Page 51

Vancouver Design Center

7.3.10 9/12-Bit TFT/D-TFD Panel Timing

FPFRAME

FPLINE

FPDAT[11:0]

DRDY

FPLINE

FPSHIFT

DRDY

FPDAT[9]

FPDAT[2:0]

FPDAT[10]

FPDAT[4:3]

FPDAT[11]

FPDAT[8:6]

LINE480

HNDP

VNDP

1-1

1-2

1-1

1-2

1-1

1-2

VDP

LINE1 LINE480

HDP

1-640

HNDP

VNDP

Note: DRDY is used to indi cate the firs t pixel Example Timing for 640x480 pane l

Figure 7-24: 12-Bit TFT/D-TFD Panel Timing

VDP = V er ti cal Di splay Period = (REG[06h] bits 1-0, REG [05h] bits 7-0) + 1 Lines VNDP = Vertical Non-Display Period = VNDP1 + VNDP2 = (REG [0A h] b its 5- 0) Lines VNDP1 = Vertical Non-Display Period 1 = REG[09h] bits 5-0 Lines VNDP2 = Vertical Non-Display Period 2 = ( REG[0Ah] bits 5-0) - (REG[09Ah] bits 5-0) Lines HDP = Horizontal Display Period = ((REG[04h] bits 6-0) + 1) x 8Ts HNDP = Horizontal Non-Display Period = HNDP1 + HNDP2 = (REG[08h] + 4) x 8Ts HNDP1= Horizontal Non-Display Period 1 = ((REG[07h] bits4-0) x 8) +16Ts HNDP2= Horizontal Non-Display Period 2 = (((REG[08h ] bits4-0) - (REG[07h] bits 4-0)) x 8) +16Ts

Hardware Functional Specification S1D13704 Issue Date: 01/02/08 X26A-A-001-04

Page 60

Page 52 Epson Research and Development

Vancouver Design Center

Frame Pulse

t12

Line Pulse

DRDY

t11

Shift Pulse

FPDAT[11:0]

Note: DRDY is used to indicate the first pixel

t17

Figure 7-25: TFT/D-TFD A.C. Timing

t13

t14

21639

t10

t15

t16

640

S1D13704 Hardware Functional Specification X26A-A-001-04 Issue Date: 01/02/08

Page 61

Epson Research and Development Page 53

Vancouver Design Center

Symbol Parameter Min Typ Max Units

t1 t2 t3 t4 t5 t6 t7

t8 Frame Pulse cycle time note 3

t9 Frame Pulse pulse width low 2t6 t10 Horizontal display period note 4 t11 Line Pulse setup to Shift Pulse falling edge 0.5 Ts

t12 t13 DRDY to Shift Pulse falling edge setup time 0.5 Ts

t14 DRDY pulse width note 5 t15 DRDY falling edge to Line Pulse falling edge note 6 t16 DRDY hold from Shift Pulse falling edge 0.5 Ts t17 Line Pulse Falling edge to DRDY active note 7 250

Shift Pulse period 1 (note 1) Shift Pulse pulse width high 0.5 Ts Shift Pulse pulse width low 0.5 Ts Data setup to Shift Pulse fallin g edge 0.5 Ts Data hold from Shift Pulse falling edge 0.5 Ts Line Pulse cycle time note 2 Line Pulse pulse width low 9 Ts

Frame Pulse falling edge to Lin e Pulse falling edge phase differenc e

t6 - 18Ts

1. Ts = pixel clock period

2. t6min = [((REG[04h] bits 6-0)+1) x 8 + ((REG[08h] bits 4-0)+4) x 8] Ts

3. t8 min = [((REG[06h] bits 1-0, REG[05h] bits 7-0)+1) + (REG[0Ah] bits 6-0)] Lines

4. t10min = [((REG[04h] bits 6-0)+1) x 8] Ts

5. t14min = [((REG[04h] bits 6-0)+1) x 8] Ts

6. t15min = [(REG[07h] bits 4-0) x 8 + 16] Ts

7. t17min = [(REG[08h] bits 4-0) - (REG[07]) x 8 + 16] Ts

Hardware Functional Specification S1D13704 Issue Date: 01/02/08 X26A-A-001-04

Page 62

Page 54 Epson Research and Development

Vancouver Design Center

8 Registers

8.1 Register Mapping

The S1D13704 registers are located in the upper 32 bytes of the 64K byte S1D13704 address range. The registers are accessible when CS# = 0 and AB[15:0] are in the range FFE0h through FFFFh.

8.2 Register Descriptions

Unless specified otherwise, all register bits are reset to 0 during power up.

REG[00h] Revision Code Register

Address = FFE0h Read Only

Product Code

Bit 5

Product Code

Bit 4

Product Code

Bit 3

Product Code

Bit 2

Product Code

Bit 1

Product Code

Bit 0

Revision

Code Bit 1

Revision

Code Bit 0

bits 7-2 Product Code

This is a read-only register that indicates the product code of the chi p. The pro duct co de i s

000110.

bits 1-0 Revision Code

This is a read-only regis ter that indic ates the re vision code of the chip. The re vision code is

00.

REG[01h] Mode Register 0

Address = FFE1h Read/Write.

TFT/STN Dual/Single Color/Mono

FPLine

Polarity

FPFrame

Polarity

Mask

FPSHIFT

Data Width

Bit 1

Data Width

Bit 0

bit 7 TFT/STN

When this bit = 0, STN (passive) panel mode is selected. When this bit = 1, TFT/D-TFD panel mode is selected. If TFT/D- TFD panel mode is s elected , Dual/Si ngle ( REG[01h] bit

6) and Color/Mono (REG[01h] bit5) are ignored. See Table 8-1: “Panel Data Format” below.

bit 6 Dual/Single

When this bit = 0, Single LCD pane l drive is selected. When this bit = 1, Dual LCD panel drive is selected. See Table 8-1: “Panel Data Format” below.

bit 5 Color/Mono

When this bit = 0, Monochrome LCD panel drive is selected. When this bit = 1, Color LCD panel drive is selected. See Table 8-1: “Panel Data Format” below.

S1D13704 Hardware Functional Specification X26A-A-001-04 Issue Date: 01/02/08

Page 63

Epson Research and Development Page 55

Vancouver Design Center

bit 4 FPLINE Polarity

This bit controls the polarity of FPLINE in TFT/D-TFD mode (no effect in passive panel mode). When this bit = 0, FPLINE is ac tive low. When this bit = 1, FPLINE is active high.

bit 3 FPFRAME Polarity

This bit controls the polarity of FPFRAME in TFT/D-TF D mode (no effect in passive panel mode). When this bit = 0, FPFRAME is active low. When this bit = 1, FPFRAME is activ e high.

bit 2 Mask FPSHIFT

FPSHIFT is masked during non-display periods if either of the following two criteria is met:

1. Color passive panel is selected (REG[01h] bit 5 = 1)

2. This bit (REG[01h] bit 2) = 1

bits 1-0 Data Width Bits [1:0]

These bits select the display data format. See Table 8-1: “Panel Data Format” below.

Table 8-1: Panel Data Format

TFT/STN

REG[01h] bit 7

1 X (don’t care)

Color/Mono

REG[01h] bit 5

Dual/Single

REG[01h] bit 6

Data Width

Bit 1

REG[01h] bit 1

Data Width

Bit 0

REG[01h] bit 0

0 Mono Sing le 4-bi t pass iv e LCD 1 Mono Sing le 8-bi t pass iv e LCD 0 reserved 1 reserved 0 reserved 1 Mono Dual 8-bit passive LCD 0 reserved 1 reserved 0 Color Single 4-bit passive LCD 1 Color Single 8-bit passive LCD format 1 0 reserved 1 Color Single 8-bit passive LCD format 2 0 reserved 1 Color Dual 8-bit passive LCD 0 reserved 1 reserved 0 9-bit TFT/D-TFD panel 1 12-bit TFT/D-TFD panel

Function

Hardware Functional Specification S1D13704 Issue Date: 01/02/08 X26A-A-001-04

Page 64

Page 56 Epson Research and Development

Vancouver Design Center

REG[02h] Mode Register 1

Address = FFE2h Read/Write.

Bit-Per-Pixel

Bit 1

Bit-Per-Pixel

Bit 0

High

Performance

Input Clock

divide

(CLKI/2)

Display Blank

Frame

Repeat

Hardware

Video Invert

Enable

Software

Video Invert

bits 7-6 Bit-Per-Pixel Bits [1:0]

These bits select the color or gray-shade depth (Display Mode).

Table 8-2: Gray Shade/Color Mode Selection

Color/Mono

REG[01h] bi t 6

Bit-Per -Pix el Bit 1

REG[02h] bi t 7

Bit-Per-Pixel Bit 0

REG[02h] bit 6

bit 5 High Performance (Landscape Modes Only)

When this bit = 0, the internal Memory clock (MCLK) is a divided-down version of the Pixel clock (PCLK). The denominator is dependent on the bit-per-pixel mode - see the table below.

Table 8-3: High Performance Selection

High Performance BPP Bit 1 BPP Bit 0 Display Modes

1XXMClk = PClk

Display Mode

0 2 Gray shade 1 bit-per-pixel 1 4 Gray shade 2 bit-per-pixel 0 16 Gray shade 4 bit-per-pixel 1 reserved 0 2 Colors 1 bit-per-pixel 1 4 Colors 2 bit-per-pixel 0 16 Colors 4 bit-per-pixel 1 256 Colors 8 bit-per-pixel

0 MClk = PClk/ 8 1 bit-per-pix el 1 MClk = PClk/ 4 2 bit-per-pix el 0 MClk = PClk/ 2 4 bit-per-pix el 1 MClk = PClk 8 bit-per-pixel

When this bit = 1, MCLK is fix ed to the same frequency as PCLK for all bit-per-pixel modes. This pro vides a f aster s creen u pdate per formance in 1 , 2, 4 bit-pe r- pixel modes , b ut also increases power consumption. This bit can be set to 1 just before a major screen update, then set back to 0 to save power after the update. This bit has no effect in SwivelView mode. Refer to REG[1Bh] SwivelView Mode Register on page 68 for SwivelView mode clock selection.

S1D13704 Hardware Functional Specification X26A-A-001-04 Issue Date: 01/02/08

Page 65

Epson Research and Development Page 57

Vancouver Design Center

bit 4 Input Clock Divide

When this bit = 0, the operating clock(CLK) is same as the input clock (CLKI). When this bit = 1, CLK = CLKI/2.

In landscape mode PCLK=CLK and MCLK is selected as per Table 8-3: “High Performance Selection”.

In SwivelView mode MCLK and PCLK are derived from CLK as shown in Table 8-9: “Selection of PCLK and MCLK in SwivelView Mode,” on page 69.

bit 3 Display Blank

This bit blanks the display image. When this bit = 1, the display is blanked (FPDAT lines to the panel ar e driven low). When this bit = 0, the display is enabled.

bit 2 Frame Repeat (EL support)

This feature is used to improve Frame Rate Modulation of EL panels. When this bit = 1, an internal fram e counter runs from 0 to 3FFFFh. When the frame counter rolls over, the modulated image pattern is repeated (every 1 hour when the frame rate is 72Hz). When this bit = 0, the modulated image pattern is never repeated.

bit 1 Hardware Video Invert Ena ble

In passive panel modes (REG[01h] bit 7 = 0) FPDAT11 is available as either GPIO4 or hardware video invert. When this bit = 1, Hardware Video Invert is enabled via the FPDAT11 pin. When this bit = 0, FPDAT11 operates as GPIO4. See Table 8-4: “Inverse Video Mode Select Options” below.

Note

Video data is inverted after the Look-Up Table.

bit 0 Software Video Invert

When this bit = 1, Inverse video mode is selected. When this bit = 0, standard video mode is selected. See Table 8-4: “Inverse Video Mode Select Opt ions” below .

Note

Video data is inverted after the Look-Up Table.

Table 8-4: Inverse Video Mode Select Options

Hardware Video

Invert Enable

00XNormal 0 1 X Inverse 1X0Normal 1 X 1 Inverse

Software Video

Invert

(Passive and

Active Panels)

FPDAT11

(Passive Panels

Only)

Video Data

Hardware Functional Specification S1D13704 Issue Date: 01/02/08 X26A-A-001-04

Page 66

Page 58 Epson Research and Development

Vancouver Design Center

REG[03h] Mode Register 2

Address = FFE3h Read/Write

Look-Up

Table Bypass

n/a n/a n/a

LCDPWR

Override

Hardware

Power Save

Enable

Software

Power Save

Bit 1

Software

Power Save

Bit 0

bit 7 Look-Up Table Bypass

When the Look-Up Table Bypass bit = 0, the Green Look-Up Table is used for display data output in gray shade modes. When this bit = 1, the Look -Up Table is bypassed for display data output in gray shade modes (for power save purposes). See “Look-Up Table Architecture” on pag e72.

There is no effect on changi ng this bit in color mo des. In color display mode the Look-Up Table cannot be bypassed.

bit 3 LCDPWR Override

This bit is used to o v erride t he panel on /of f seque ncing logi c. When this bi t = 0, LCDPWR and the panel interface signals are controlled by the sequencing logic. When this bit 1, LCDPWR is forced to of f and t he pan el inte rf ace si gnals a re fo rced l ow immediately upon entering power save mode. See Section 7.3.2, “Power Down/Up Timing” on page 36 for further information.

bit 2 Hardware Power Save Enable

When this bit = 1 GPIO0 i s us ed a s t he Ha rd ware Power Save input pin. When this bit = 0 GPIO0 operates normally.

Table 8-5: Hardware Power Save/GPIO0 Operation

RESET#

State

0X X X 1 0 0 reads pin status 1 0 1 0 GPIO0 Output = 0

1 0 1 1 GPIO0 Output = 1 11 X X

Hardware Power

Save Enable

REG[03h] bit 2

bits 1-0 So ftware Power Save Bits [1: 0]

These bits select the Power Save Mode as shown in the fol lowing table.

Table 8-6: Software Power Save Mode Selection

Bit 1 Bit 0 Mode

0 0 Software Power Save 0 1 reserved 1 0 reserved 1 1 Normal Operation

GPIO0 Config

REG[18h] bit 0

GPIO0

Status/Control

REG[19h] bit 0

GPIO0 Operation

GPIO0 Input

(high impedance)

Hardware Power Save

Input (active high)

S1D13704 Hardware Functional Specification X26A-A-001-04 Issue Date: 01/02/08

Page 67

Epson Research and Development Page 59

Vancouver Design Center

Refer to Power Save Modes on page 84 for a complete description.

REG[04h] Horizontal Panel Size Register

Address = FFE4h Read/Write

n/a

Horizontal

Panel Size Bit

Horizontal

Panel Size Bit

Horizontal

Panel Size Bit

Horizontal

Panel Size Bit

Horizontal

Panel Size Bit

Horizontal

Panel Size Bit

Horizontal

Panel Size Bit

bits 6-0 Horizontal Panel Size Bits [6: 0]

This register determines the horizontal resolution of the panel. This register must be programmed w ith a value calculated as follows:

HorizontalPanelResolution pixels()

HorizontalPanelSizeRegister



----------------------------------------------------------------------------------------------



1–=

This register must not be set to a value le ss than 03h.

REG[05h] Vertical Panel Size Register (LSB)

Address = FFE5h Read/Write

Vertical Panel

Size

Bit 7

Vertical Panel

Size Bit 6

Vertical Panel

Size Bit 5

Vertical Panel

Size

Bit 4

Vertical Panel

Size Bit 3

Vertical Panel

Size

Bit 2

Vertical Panel

Size Bit 1

Vertical Panel

Size Bit 0

REG[06h] Vertical Panel Size Register (MSB)

Address = FFE6h Read/Write

n/a n/a n/a n/a n/a n/a

Vertical Panel

Size Bit 9

Vertical Panel

Size Bit 8

REG[05h] bits 7-0 Ve rt i c al Panel Size Bits [9 :0] REG[06h] bits 1-0 This 10-bit register determines the vertical resolution of the panel. This regist er must be

programmed with a value cal cul at ed as fol lows:

VerticalPanelSizeRegist er VerticalPanelResolution lines()1–=

3FFh is the maximum value of this regi ster for a vertical re solution of 1024 lines.

Hardware Functional Specification S1D13704 Issue Date: 01/02/08 X26A-A-001-04

Page 68

Page 60 Epson Research and Development

Vancouver Design Center

REG[07h] FPLINE Start Position

Address = FFE7h Read/Write

n/a n/a n/a

FPLINE Start Position Bit 4

FPLINE Start Position Bit 3

FPLINE Start Position Bit 2

FPLINE Start Position Bit 1

FPLINE Start Position Bit 0

bits 4-0 FPLINE Start Position

These bits are used in TFT/D-TFD mode to specify the position of the FPLINE pulse. These bits specify the delay, in 8-pixel resolution, from the end of a line of di splay data (FPDAT) to the leading edge of FPLINE. This register is effective in TFT/D-TFD mode only (REG[01h] bit 7 = 1). This register is programmed as follows:

FPLINEposition pixels()REG 07h[]2+()8×=

The following constraint must be satisfied:

REG 07h[]REG 08h[]≤

REG[08h] Horizontal Non-Display Period

Address = FFE8h Read/Write

n/a n/a n/a

Horizontal

Non-Display

Period Bit 4

Horizontal

Non-Display

Period Bit 3

Horizontal

Non-Display

Period Bit 2

Horizontal

Non-Display

Period Bit 1

Horizontal

Non-Display

Period Bit 0

bits 4-0 Horizontal Non-Display Period

These bits specify the horizontal non-display period in 8-pixel resolution.

HorizontalNonDisplayPeriod pixels()REG 08 h[]4+()8×=

REG[09h] FPFRAME Start Position

Address = FFE9h Read/Write

n/a n/a

FPFRAME

Start Position

Bit 5

FPFRAME

Start Position

Bit 4

FPFRAME

Start Position

Bit 3

FPFRAME

Start Position

Bit 2

FPFRAME

Start Position

Bit 1

FPFRAME

Start Position

Bit 0

bits 5-0 FPFRAME Start Position

These bits are used in TFT/D-TFD mode to specify the position of the FPFRAME pulse. These bits specify the number of lines between the last line of display data (FPDAT) and the leading edge of FPFRAME. This reg ister is effective in TFT/D-TFD mode only (REG[01h] bit 7 = 1).

FPFRAMEposition lines()REG 09h[]=

The contents of this re giste r must be great er than zero and less t han or equal to the Vertical Non-Display Period Regis te r, i.e.

1REG09h[]REG 0Ah[]≤≤

S1D13704 Hardware Functional Specification X26A-A-001-04 Issue Date: 01/02/08

Page 69

Epson Research and Development Page 61

Vancouver Design Center

REG[0Ah] Vertical Non-Display Period

Address = FFEAh Read/Write

Vertical Non-

Display

Status

n/a

Vertical Non-

Display

Period Bit 5

Vertical Non-

Display

Period Bit 4

Vertical Non-

Display

Period Bit 3

Vertical Non-

Display

Period Bit 2

Vertical Non-

Display

Period Bit 1

Vertical Non-

Display

Period Bit 0

bit 7 Vertical Non-Display Status

This bit =1 during the Vertical Non-Display period.

bits 5-0 Vertical Non-Display Period

These bits specify the vertic al non-displa y period.

VerticalNonDisplayPeriod lines()REG 0Ah[]=

Note

This register should be set only once, on power-up during initialization.

REG[0Bh] MOD Rate Register

Address = FFEBh Read/Write

n/a n/a

MOD Rate

Bit 5

MOD Rate

Bit 4

MOD Rate

Bit 3

MOD Rate

Bit 2

MOD Rate

Bit 1

MOD Rate

Bit 0

bits 5-0 MOD Rate Bits [5:0]

When the valu e of this register is 0, the MOD output signal toggles every FPFRAME. For a non-zero value, the value in this register + 1 specifies the number of FPLINEs between toggles of the MOD output sig nal. These bits are for passi ve LCD panels only.

REG[0Ch] Screen 1 Start Address Register (LSB)

Address = FFECh Read/Write

Screen 1 Start

Address

Bit 7

Screen 1 Start

Address

Bit 6

Screen 1 Start

Address

Bit 5

Screen 1 Start

Address

Bit 4

Screen 1 Start

Address

Bit 3

Screen 1 Start

Address

Bit 2

Screen 1 Start

Address

Bit 1

Screen 1 Start

Address

Bit 0

REG[0Dh] Screen 1 Start Address Register (MSB)

Address = FFEDh Read/Write

Screen 1 Start

Address

Bit 15

Screen 1 Start

Address

Bit 14

Screen 1 Start

Address

Bit 13

Screen 1 Start

Address

Bit 12

Screen 1 Start

Address

Bit 11

Screen 1 Start

Address

Bit 10

Screen 1 Start

Address

Bit 9

Screen 1 Start

Address

Bit 8

REG[0Dh] bit 6-0 Screen 1 Start Address Bits [14:0] REG[0Ch] bit 7-0 These bits determine the word address of the start of Screen 1 in landscape modes or the

byte address of the start of Screen 1 in SwivelView modes.

REG[0Dh] bit 7 Screen 1 Start Address Bit 15

This bit is for SwivelView mode only and has no effec t in Landscape mode.

Hardware Functional Specification S1D13704 Issue Date: 01/02/08 X26A-A-001-04

Page 70

Page 62 Epson Research and Development

Vancouver Design Center

REG[0Fh] Screen 2 St art Ad dress Register (LSB)

Address = FFEFh Read/Write

Screen 2 Start

Address

Bit 7

Screen 2 Start

Address

Bit 6

Screen 2 Start

Address

Bit 5

Screen 2 Start

Address

Bit 4

Screen 2 Start

Address

Bit 3

Screen 2 Start

Address

Bit 2

Screen 2 Start

Address

Bit 1

Screen 2 Start

Address

Bit 0

REG[10h] Screen 2 Start Address Register (MSB)

Address = FFF0h Read/Write

Screen 2 Start

Address

Bit 15

Screen 2 Start

Address

Bit 14

Screen 2 Start

Address

Bit 13

Screen 2 Start

Address

Bit 12

Screen 2 Start

Address

Bit 11

Screen 2 Start

Address

Bit 10

Screen 2 Start

Address

Bit 9

Screen 2 Start

Address

Bit 8

REG[10h] bit 6-0 Screen 2 Start Address Bits [14:0] REG[0Fh] bit 7-0 These bits determine the word address of the start of Screen 2 in landscape modes or the

byte address of the start of Screen 2 in SwivelView modes.

REG[10h] bit 7 Screen 2 Start Address Bit 15

This bit is for SwivelVi ew mode only and has no effect in Landscape mode.

REG[12h] Memory Address Offset Register

Address = FFF2h Read/Write

Memory Address

Offset Bit 7

bits 7-0

Memory Address

Offset Bit 6

Memory Address Offset

Memory Address

Offset Bit 5

Memory Address

Offset Bit 4

Memory

Address

Offset Bit 3

Memory Address

Offset Bit 2

Bits [7:0] (Landscape Modes Only)

Memory Address

Offset Bit 1

Memory Address

Offset Bit 0

This registe r is used to creat e a virtual imag e by setting a word offset be tw een the last address of one line and the f irs t addr ess of the fo ll o wing l ine. I f thi s register is not equal to zero, then a virtual image is formed. The displayed image is a window into the larger virtual image. See Figure 8-1: “Screen-Register Relationship, Split Screen,” on page 64.

This register has no effect in SwivelView modes. See “REG[1Ch] Line Byte Count Register for SwivelView Mode” on page69.

S1D13704 Hardware Functional Specification X26A-A-001-04 Issue Date: 01/02/08

Page 71

Epson Research and Development Page 63

Vancouver Design Center

REG[13h] Screen 1 Vertical Size Register (LSB)

Address = FFF3h Read/Write

Screen 1

Vertical Size

Bit 7

Screen 1

Vertical Size

Bit 6

Screen 1

Vertical Size

Bit 5

Screen 1

Vertical Size

Bit 4

Screen 1

Vertical Size

Bit 3

Screen 1

Vertical Size

Bit 2

Screen 1

Vertical Size

Bit 1

Screen 1

Vertical Size

Bit 0

REG[14h] Screen 1 Vertical Size Register (MSB)

Address = FFF4h Read/Write

Screen 1

n/an/an/an/an/an/a

Vertical Size

Bit 9

Screen 1

Vertical Size

Bit 8

REG[14h] bits 1-0 Screen 1 Vertical Size Bits [9:0] REG[13h] bits 7-0 This register is use d to implement the Split Screen feature of the S1D13704. These bits

determine the height (in lines) of Screen 1. On reset this register is set to 0h. In landscape modes, if this r e gis ter i s progr ammed with a value, n, where n is less than the

Vertical Panel Si ze (REG[06 h], REG[05h] ), then l ines 0 to n of the panel con tain Scr een 1 and lines n+1 to REG[06h], REG[05h] of the panel contain Screen 2. See Figure 8-1: “Screen-Register Relationship, Split Screen,” on page 64. If Split Screen is not desired, this register must be programmed greater than, or equal to the Vertical Panel Size, REG[06h] and REG[05h].

In Swivel View modes this regi ster must be programmed gr eater than, or equal to the Vertical Panel Size, REG[06h] and REG[05h]. See “Swivel View™” on page 79.

Hardware Functional Specification S1D13704 Issue Date: 01/02/08 X26A-A-001-04

Page 72

Page 64 Epson Research and Development

Vancouver Design Center

(REG[0Dh], REG[0Ch]) Words

Image 1

Image 2

Where: (REG[0Dh], REG[0Ch]) is the Screen 1 Start Word Address BPP is Bits-per-Pixel as set by REG[02h] bits 7:6 REG[12h] is the Address Pitch Adjustment in Words (REG[10h], REG[0Fh]) is the Screen 2 Start Word Address (REG[14h], REG[13h]) is the Screen 1 Vertical Size (REG[06h], REG[05h]) is the Vertical Panel Size

Line 0 Last Pixel Address + REG[12h] Words

Line 0

Line 1

Line=(REG[14h], REG[13h])

(REG[10h], REG[0Fh]) Words

8(REG[04h]+1) Pixels

Figure 8-1: Screen-Register Relationship, Split Screen

Virtual Image

Line 0 Last Pixel Address=((REG[0Dh], REG[0Ch]) +

REG[12h] Words

(8(REG[04h]+1) Words

((REG[06h], REG[05])+1) Lines

BPP/16))

Consider an example wher e REG[14h], REG[13h]= 0CEh for a 320x240 display system. The upper 207 lines (CEh + 1) of the panel show an image from the Screen 1 Start Word Address. The remaining 33 lines show an image from the Screen 2 Start Word Address.

S1D13704 Hardware Functional Specification X26A-A-001-04 Issue Date: 01/02/08

Page 73

Epson Research and Development Page 65

Vancouver Design Center

REG[15h] Look-Up Table Address Register

Address = FFF5h Read/Write

n/a n/a

RGB Index

Bit 1

RGB Index

Bit 0

Look-Up

Table

Address

Bit 3

Look-Up

Table

Address

Bit 2

Look-Up

Table

Address

Bit 1

Look-Up

Table

Address

Bit 0

The S1D13704 has three 16-p osition, 4 -bit wi de Look- Up Tables, one each for re d, green , and blue. Refer to “Look-Up Table Architecture” for details. This register selects which Look-Up Table position is read/ write ac cessible through t he Look-Up Table Data Register (REG[17h]).

bits 5-4 RGB Index Bits [1:0]

These bits select between the Red, Green, and Blue Look-Up Tables, and Auto-Increment mode. The Green Look-Up Table is used in monochrome mode with these bits set to 10b. See Note below.

bits 3-0 Look-Up Table Address Bits [3:0]

These 4 bits select one of the 16 positions in the selected Look-Up Table. These bits are automatically changed as the Look-Up Table Data Register is accessed. See Note below.

Note

Accesses to the Look-Up Table Data Register automatically increment a pointer into the RGB Look-Up Tables. The pointer sequence varies as shown in the table below.

Table 8-7: Look-Up Table Access

REG[01h] REG[15h]

bit 5 bit 5 bit 4

010 1 0 0 Auto-Increment R[n], G[n], B[n], R[n+1], G[n+1],...

1 0 1 Red Look-Up Ta ble R[n], R[n+1], R[n+2],... 110 1 1 1 Blue Look-Up Table B[n], B[n+1], B[n+2],...

Look-Up Table

Selected

Green/Gray Look-Up

Table

Green/Gray Look-Up

Table

Pointer Sequence

G[n], G[n+1], G[n+2],...

In Auto-Increment mode, writing the Look-Up Table Address Register automatically sets the pointer to the Red Look-Up Table. For exam ple, writing a value 03 into the Look-Up Table Address Register selects Auto-Increment mode and sets the pointer to R[3]. Subsequent accesses to the Look-Up Table Data Register move the point er onto G[3], B[3], R[4], etc.

Hardware Functional Specification S1D13704 Issue Date: 01/02/08 X26A-A-001-04

Page 74

Page 66 Epson Research and Development

Vancouver Design Center

REG[16h] Look-Up Table Bank Select Register

Address = FFF6h Read/Write

n/a n/a

Red Bank

Select

Bit 1

Red Bank

Select

Bit 0

Green Bank

Select

Bit 1

Green Bank

Select

Bit 0

Blue Bank

Select

Bit 1

Blue Bank

Select

Bit 0

bits 7-6 n/ a bits 5-4 Red Bank Select B its [1:0]

In 1 bit-per-pixel (bpp) color mode the lowe r 8 positions of the Red Look-Up T a ble is arranged into four banks, each with two positions. These two bits select which bank is used for display data.

In 2 bpp color mode the 16 position Red Look-Up Table is arranged into four banks, each with four positions. These two bits select which bank is used for display data.

These bits hav e no effect in 4 bpp color/gray modes. In 8 bpp color mode the 16 positio n, Red Look-Up Table is arranged into two banks, each

with eight positions. R ed Bank Select bit 0 selects which bank is used for display data.

bits 3-2 Green Bank Select Bits [1:0]

In 1 bit-per-pi xel ( bpp) color /gray mode th e lo wer 8 posit ions of t he Green Look-Up Table is arranged into four banks, each with two positions. These two bits select which bank is used for display data.

In 2 bpp color/gray mode, the 16 position Green Look-Up Table is arranged into four banks, each with four positions. These two bits select which bank is used for display data.

These bits hav e no effect in 4 bpp color/gray modes. In 8 bpp color mode, the 16 position Green Look-Up Table is arranged into two banks,

each with eight positions. Green Bank Select bit 0 selects which bank is used for display data.

bit 1-0 Blue Bank Select Bits [1:0]

In 1 bit-per-pixel (bpp) color mode the lower 8 positions of the Blue Look-Up Table is arranged into four banks, each with two positions. These two bits select which bank is used for display data.

In 2 bpp color mode, the 1 6 posi tion Blue Look- Up Table is arranged i nto four banks, eac h with four positions. These two bits select which bank is used for display data.

These bits hav e no effect in 4 bpp color/gray modes. In 8 bpp color mode, the 1 6 posi tion Blue Look- Up Table is arranged i nto four banks, eac h

with four positions. These two bits select which bank is used for display data.

S1D13704 Hardware Functional Specification X26A-A-001-04 Issue Date: 01/02/08

Page 75

Epson Research and Development Page 67

Vancouver Design Center

REG[17h] Look-Up Table Data Register

Address = FFF7h Read/Write

Look-Up

n/an/an/an/a

Table Data

Bit 3

Look-Up

Table Data

Bit 2

Look-Up

Table Data

Bit 1

Look-Up

Table Data

Bit 0

bits 3-0 Look-Up Table Data Bits [3:0]

This register is used to read/write the RGB Look-Up Tables. This register is an apert ure into the three 16-position Look-Up Tables. The Look-Up Table Address Register (REG[16h]) selects whi ch Look- Up Table position is accessible. See REG[16h] Look-Up Table Bank Select Register on page 66.

REG[18h] GPIO Configuration Control Register

Address = FFF8h Read/Write

n/a n/a n/a

GPIO4 Pin IO Configuration

GPIO3 Pin IO

Configuration

GPIO2 Pin IO Configuration

GPIO1 Pin IO

Configuration

GPIO0 Pin IO

Configuration

bits 4-0 GPIO[4:0] Pin IO Configuration

These bits determine the direction of the GPIO[4:0] pins. When GPIOn Pin IO Conf iguration bit = 0, the corresponding GPIOn pi n is configured as an input. The input can be read at the GPIOn Status/Control Register bit. See REG[19h] below.

When GPIOn Pin IO Conf iguration bit = 1, the corresponding GPIOn pi n is configured as an output. The output can be controlled by writing the GPIOn Status/Control Register bit.

Note

These bits have no effect when the GPIOn pin is configured for a specific function (i.e. as FPDAT[11:8] for TFT/D-TFD operation). All unused GPIO pins must be tied to

GPIO4 Pin IO

Status

GPIO3 Pin IO

Status

GPIO2 Pin IO

Status

GPIO1 Pin IO

Status

GPIO0 Pin IO

Status

IO V

REG[19h] GPIO Status/Control Register

Address = FFF9h Read/Write

n/a n/a n/a

bits 4-0 GPIO[4:0] Status

When the GPIOn pin is conf i gur ed as an input, the corresponding GPIO Status bit is us ed to read the pin input. See REG[18h] above.

When the GPIOn pin is c onf igured as an output , the corr esponding GPIO Status bit is us ed to control the pin output.

Hardware Functional Specification S1D13704 Issue Date: 01/02/08 X26A-A-001-04

Page 76

Page 68 Epson Research and Development

Vancouver Design Center

REG[1Ah] Scratch Pad Register

Address = FFFAh Read/Write

Scratch bit 7 Scratch bit 6 Scratch bit 5 Scratch bit 4 Scratch bit 3 Scratch bit 2 Scratch bi t 1 Scratch bit 0

bits 7-0 Scratch Pad Register

This register contains general use read/write bits. These bits have no effect on hardware.

REG[1Bh] SwivelView Mode Register

Address = FFFBh Read/Write

SwivelView

Mode Enable

SwivelView

Mode Select

n/a n/a n/a reserved

SwivelView

Mode Pixel

Clock Select

Bit 1

SwivelView Mode Pixel

Clock Select

Bit 0

bit 7 SwivelView Mode Enable

When this bit = 1, SwivelView Mode is enabled. Whe n this bit = 0, Landscape Mode is enabled.

bit 6 SwivelView Mode Select

When this bit = 0, Default SwivelView Mode is selected. When this bit = 1, Alternate SwivelView Mode is selected. See Section 12, “SwivelView™” on page 79 for further information on SwivelView Mode.

The following table shows the selection of SwivelView Mode.

Table 8-8: Selection of SwivelView Mode

SwivelView

Mode Enable

(REG[1Bh] bit 7)

0 X Landscape 1 0 Default SwivelView 1 1 Alternate SwivelView

SwivelView

Mode Select

(REG[1Bh] bit 6)

bit 2 reserved

reserved bits must be set to 0.

bits 1-0 SwivelView Mode Pixel Clock Select Bits [1:0]

These two bits select the Pixel Clock (PCLK) source in SwivelView Mode - these bi ts have no effect in Landscape Mode. The following table shows the selection of PCLK and MCLK in SwivelView Mode - see Section 12, “SwivelView™” on page 79 for details.

Mode

S1D13704 Hardware Functional Specification X26A-A-001-04 Issue Date: 01/02/08

Page 77

Epson Research and Development Page 69

Vancouver Design Center

Table 8-9: Selection of PCLK and MCLK in SwivelView Mode

SwivelView

Mode Enable

(REG[1Bh] bit 7)

0 X X X CLK See Reg[02h] bit 5 1000CLK CLK 1001CLK/2CLK/2 1010CLK/4CLK/4 1011CLK/8CLK/8 1100CLK/2CLK 1101CLK/2CLK 1110CLK/4CLK/2 1111CLK/8CLK/4

SwivelView

Mode Select

(REG[1Bh] bit 6)

Pixel Clock (PCLK) Select

(REG[1Bh] bits [1:0]

Bit 1 Bit 0

Where CLK is CLKI (REG[02h] bit 4 = 0) or CLKI/2 (REG[02h] bit 4 = 1)

PCLK = MCLK =

REG[1Ch] Line Byte Count Register for SwivelView Mode

Address = FFFCh Read/Write

Line Byte

Count bit 7

Line Byte

Count bit 6

Line Byte

Count bit 5

Line Byte

Count bit 4

Line Byte

Count bit 3

Line Byte

Count bit 2

Line Byte

Count bit

Line Byte

Count bit

bits 7-0 Line Byte Count Bits [7:0]

This register is the byte count from the beginning of one line to the beginning of the next consecutiv e line (common ly called “stride ” by programmers). This re gister may be used to create a virtual image in SwivelView mode.

REG[1Eh] and REG[1Fh]

REG[1Eh] and REG[1Fh] are reserved for factory S1D13704 testing and should not be written. Any value wri tten to t hese regis ters may r esult i n damage to t he S1D1 3704 and/o r any panel connected to the S1D13704.

Hardware Functional Specification S1D13704 Issue Date: 01/02/08 X26A-A-001-04

Page 78

Page 70 Epson Research and Development

Vancouver Design Center

9 Frame Rate Calculat ion

The following formulae are used to calculate the display frame rate.

TFT/D-TFD and Passive Single-Panel modes

FrameRat e

---------------------------------------------------------------------------------------- -=

HDP HNDP+()VDP VNDP+()×

PCLK

Where: f

PCLK

= PClk frequency (Hz) HDP = Horizontal Display Period = ((REG[04h] bits 6-0) + 1) x 8 Pixels HNDP = Horizontal Non-Display Period = ((REG[08h] bits 4-0) + 4) x 8 Pixels VDP = Vertical Display Period = ((REG[06h] bits 1-0, REG[05h] bits 7-0) + 1) Lines VNDP = Vertical Non-Display Period = (REG[0Ah] bits 5-0) Lines

Passive Dual-Panel mode

FrameRate

Where: f

PCLK

---------------------------------------------------------------------------------------------------= 2 HDP HNDP+()×

= PClk frequency (Hz) HDP = Horizontal Display Period = ((REG[04h] bits 6-0) + 1) x 8 Pixels HNDP = Horizontal Non-Display Period = ((REG[08h] bits 4-0) + 4) x 8 Pixels VDP = Vertical Display Period = ((REG[06 h] bits 1-0, REG[ 05h] bits 7-0) + 1) Lines VNDP = Vertical Non-Display Period = (REG[0Ah] bits 5-0) Lines

PCLK

VDP



----------- - V N D P+



S1D13704 Hardware Functional Specification X26A-A-001-04 Issue Date: 01/02/08

Page 79

Epson Research and Development Page 71

Vancouver Design Center

10 Display Data Formats

1-bpp:

Byte 0

Host Address

2-bpp:

Byte 0 Byte 1

Host Address

4-bpp:

Byte 0 Byte 1 Byte 2

bit 7 bit 0

A0A1A2A3A4A5A6A

Display Memory

bit 7 bit 0

A0B0A1B1A2B2A3B A4B4A5B5A6B6A7B

Display Memory

bit 7 bit 0

A0B0C0D0A1B1C1D A2B2C2D2A3B3C3D A4B4C4D4A5B5C5D

P1P

P5P

Pn = (An)

Panel Display

P1P

P5P

= (An, Bn)

Panel Display

P1P

= (An, Bn, Cn, Dn)

P5P

Panel Display

Host Address

8-bpp:

Byte 0 Byte 1

Byte 2

bit 7 bit 0

Display Memory

3-3-2 RGB

P1P

= (R

P5P

2-0

, B

1-0

)

, Gn

Panel Display

Host Address

Display Memory

Figure 10-1: 1/2/4/8 Bit-Per-Pi xe l Displ ay Data Me mory Organization

Hardware Functional Specification S1D13704 Issue Date: 01/02/08 X26A-A-001-04

Page 80

Page 72 Epson Research and Development

Vancouver Design Center

11 Look-Up Table Architecture

Table 11-1: Look-Up Table Configurations

Display Mode 4-bit wide Look-Up Table

RED GREEN BLUE 2-level gray 4-level gray 4 banks of 4

16-level gray 1 bank of 16

2 color 4 bank of 2 4 bank of 2 4 bank of 2 4 color 4 banks of 4 4 banks of 4 4 banks of 4

16 color 1 bank of 16 1 bank of 16 1 bank of 16

256 color 2 banks of 8 2 banks of 8 4 banks of 4

Indicates the Lo ok-Up Table is not used for that display mode

The following figures are inte nded to show the display data output path only. The CPU R/W access to the individual Look-Up Tables is not affected by the vari ous ‘banking’ configurations.

4 banks of 2

11.1 Gray Shade Display Modes

2-Level Gray Shade Mode

Green Look-Up Table

1-bit pixel data

Green Bank Select

REG[16h] bits [3:2]

0 1

2 3

4 5

6 7

Bank Select Logic

2 Gray Data Format:

76543210

A0 A1 A2 A3 A4 A5 A6 A7

See Section 10

4-bit display data output

Figure 11-1: 2-Level Gray-Shade Mode Look-Up Table Architecture

S1D13704 Hardware Functional Specification X26A-A-001-04 Issue Date: 01/02/08

Page 81

Epson Research and Development Page 73

Vancouver Design Center

4-Level Gray Shade Mode

4 Gray Data Format:

76543210

A0 B0 A1 B1 A2 B2 A3 B3

See Section 10

2-bit pixel data

Green Bank Select

REG[16h] bits [3:2]

Green Look-Up Table

Bank 0

0 1 2 3

Bank 1

0 1 2 3

Bank 2

0 1 2 3

Bank 3

0 1 2 3

Bank Select Logic

4-bit display data output

Figure 11-2: 4-Level Gray-Shade Mode Look-Up Table Architecture

16-Level Gray Shade Mode

16 Gray Data Format:

76543210

A0 B0 C0 D0 A1 B1 C1 D1

See Section 10

4-bit pixel data

Figure 11-3: 16-Level Gray-Shade Mode Look-Up Table Architecture

Green Look-Up Table 16x4

0 1 2 3

C D E F

4-bit display data output

Hardware Functional Specification S1D13704 Issue Date: 01/02/08 X26A-A-001-04

Page 82

Page 74 Epson Research and Development

Vancouver Design Center

Look-Up Table Bypass Mode

Look-Up Tables

1 bit pixel data (An) 2 bit pixel data (An, Bn) 4 bit pixel data (A

, Bn, Cn, Dn)

Figure 11-4: Look-Up Table Bypass Mode Architecture

Note

In 1 bit-per-pixel display mode, Look-Up Table Bypass mode will turn off the FRM circuitry and place the S1D13704 in Black-and-Whi te mode.

In 2 bit-per-pixel mode the Display Data Output values are 0, 5, A, and F (in hex).

1 bit display data output (A 4 bit display data output (A 4 bit display data output (A

)

, Bn, An, Bn)

, Bn, Cn, Dn)

S1D13704 Hardware Functional Specification X26A-A-001-04 Issue Date: 01/02/08

Page 83

Epson Research and Development Page 75

Vancouver Design Center

11.2 Color Display Modes

2-Level Color Mode

2 Color Data Format:

76543210

A0 A1 A2 A3 A4 A5 A6 A7

See Section 10

1-bit pixel data

Red Bank Select

REG[16h] bits [5:4]

Red Look-Up Table

0 1

2 3

4 5

6 7

Green Look-Up Table

0 1

Bank Select Logic

4-bit ‘Red’ display data output

Green Bank Select

REG[16h] bits [3:2]

Blue Bank Select

REG[16h] bits [1:0]

2 3

4 5

6 7

Blue Look-Up Table

0 1

2 3

4 5

6 7

Bank Select Logic

4-bit ‘Green’ display data output

4-bit ‘Blue’ display data output

Figure 11-5: 2-Level Color Look-Up Table Architectur e

Hardware Functional Specification S1D13704 Issue Date: 01/02/08 X26A-A-001-04

Page 84

Page 76 Epson Research and Development

Vancouver Design Center

4-Level Color Mode

4 Color Data Format:

76543210

A0 B0 A1 B1 A2 B2 A3 B3

See Section 10

2-bit pixel data

Red Bank Select

REG[16h] bits [5:4 ]

Green Bank Select

REG[16h] bits [3:2]

Red Look-Up Table

Bank 0

0 1 2 3

Bank 1

0 1 2 3

Bank 2

0 1 2 3

Bank 3

0 1 2 3

Green Look-Up Table

Bank 0

0 1 2 3

Bank 1

0 1 2 3

Bank 2

0 1 2 3

Bank 3

0 1 2 3

Bank Select Logic

Select Logic

4-bit ‘Red’ display data output

4-bit ‘Green’ display data outputBank

Blue Look-Up Table

Bank 0

0 1 2 3

Bank 1

Blue Bank Select

REG[16h] bits [1:0]

1 2 3

Bank 2

0 1 2 3

Bank 3

0 1 2 3

Bank Select Logic

4-bit ‘Blue’ display data output

Figure 11-6: 4-Level Color Mode Look-Up Table Architectur e

S1D13704 Hardware Functional Specification X26A-A-001-04 Issue Date: 01/02/08

Page 85

Epson Research and Development Page 77

Vancouver Design Center

16-Level Color Mode

16 Color Data Format:

76543210

A0 B0 C0 D0 A1 B1 C1 D1

See Section 10

4-bit pixel data 4-bit ‘Red’ display data output

Red Look-Up Table 16x4

0 1 2 3

C D E F

Green Look-Up Table 16x4

0 1 2 3

C D E F

Blue Look-Up Table 16x4

0 1 2 3

4-bit ‘Green’ display data output

4-bit ‘Blue’ display data output

C D E F

Figure 11-7: 16-Level Color Mode Look-Up Tabl e Archi te cture

Hardware Functional Specification S1D13704 Issue Date: 01/02/08 X26A-A-001-04

Page 86

Page 78 Epson Research and Development

Vancouver Design Center

256-Level Color Mode

256 Color Data Format:

76543210

R2 R1 R0 G2 G1 G0 B1 B0

See Section 10

3-bit pixel data

Red Bank Select REG[16h] bit 4

3-bit pixel data

Green Bank Select REG[16h] bit 2

2-bit pixel data

Blue Bank Select REG[16h] bits [1:0]

Red Look-Up Table

Bank 0

0 1 2 3 4 5 6 7

Bank 1

0 1 2 3 4 5 6 7

Green Look-Up Table

Bank 0

0 1 2 3 4 5 6 7

Bank 1

0 1 2 3 4 5 6 7

Blue Look-Up Table

Bank 0

0 1 2 3

Bank 1

0 1 2 3

Bank 2

0 1 2 3

Bank 3

0 1 2 3

Bank Select Logic

Figure 11-8: 256-Level Colo r Mode Look-Up Table Architectu re

S1D13704 Hardware Functional Specification X26A-A-001-04 Issue Date: 01/02/08

Page 87

Epson Research and Development Page 79

Vancouver Design Center

12 SwivelView™

Many of todays applications use the LCD panel in a portrait orientation. In this case it becomes necessary to “ rot at e” the displayed image. This rotation can be done by software at the expense of performance or, as with the S1D13704, it can be done by hardware with no CPU penalty.

There are tw o SwivelView modes: Default SwivelView and Alter nate SwivelView.

12.1 Default SwivelView Mode

Default SwivelView Mode requir es the po rtra it image width be a power of tw o, e.g. a 240line panel requires a minimum virtual image width of 256. This mode should be used whenever the required virtual image can be contained within the integrated display buffer (i.e. virtual image size ≤ 40k bytes), as it consumes less power than th e Alternate SwivelView mode.

physical memory

start

address

For example, the panel size is 320 x240 and the display mode is 4 bit-per- pixel. The vi rtual image size is 320x256 which can be contained within the 40k Byte display buffer.

Default SwivelView Mode also requi res memory clock (MCLK) ≥ pixel clock (PCLK).

The following figure sho ws how the programmer sees a 240x320 image and how the image is displayed. The application image is written to the S1D13704 in the following sense: A–B–C–D. The display is refreshed by the S1D13704 in the following sense: B-D-A-C.

256

SwivelView

320

window

240

display

start

address

window

SwivelView

320

256

240

image seen by programmer

= image in display buffer

image refreshed by S1D13704

Figure 12-1: Relationship Between The Screen Image and the Image Refreshed by S1D13704

Hardware Functional Specification S1D13704 Issue Date: 01/02/08 X26A-A-001-04

Page 88

Page 80 Epson Research and Development

Vancouver Design Center

12.1.1 How to Set Up Default SwivelView Mode

The following describes the register settings needed to set up Default SwivelView Mode for a 240x320x4 bpp image:

• Select Default SwivelView Mode: REG[1Bh] bit 7 = 1 and bit 6 = 0

• The display refresh circuitry starts at pixel “B”, therefore the Screen 1 Start Address register must be programmed with the address of pixel “B”, i.e.

REG 0Dh[]REG 0Ch[]AddressOfPixelB=,

AddressOfPixelA ByteOffset+()=

240pixels 4bpp×

AddressOfPixelA

AddressOfPixelA 77h+=

Where bpp is bits- per-p ixel and bpb is bits-per-byte.

• The Line Byte Count Register for SwivelView Mode must be set to the virtual-image width in bytes, i.e.

REG 1Ch[]

256

----------------------------------------- -

8bpb()4bpp()÷

256

-------- - 128 80h==== 2



--------------------------------------------



8bpb

1–+=

Where bpb is bits-per-b yte an d bpp is bits -pe r-pi xe l.

• Panning is achieved by changing the Screen 1 Start Address register:

• Increment the register by 1 to pan horizontally by one byte, e.g. two pixels in 4 bpp mode

• Increment the register by twice the value in the Line Byte Count register to pan vertically by two lines, e.g. add 100h to pan by two lines in the example above.

Note

Vertical panning by a single line is not supported in Default SwivelView Mode.

S1D13704 Hardware Functional Specification X26A-A-001-04 Issue Date: 01/02/08

Page 89

Epson Research and Development Page 81

Vancouver Design Center

12.2 Alternate SwivelView Mode

Alternate SwivelView Mode may be used when the virtual image size of Default SwivelView Mode cannot be contained in the 40kByte integrated frame buffer. For example, the panel size is 240x160 and the display mode is 8 bit-per-pixel. The minimum virtual image size for Default SwivelView Mode would be 240x256 which requires 60K bytes. Alternate Swive lView Mode requir es a panel si ze of only 240x1 60 which needs only 38,400 bytes.

Alternate SwivelView Mode requires the memory clock (MCLK) to be at least twice the frequency of the pixel cl ock (PCLK), i.e. MCLK ≥ 2 x PCLK. Because of this, the power consumption in Altern at e SwivelView Mode is higher than in De fault SwivelView Mode.

The following figure sho ws how the programmer sees a 240x160 image and how the image is being displayed. The appl ic ation image is written to the S1D13704 in the following sense: A–B–C–D. The display is refreshed by the S1D13704 in the following sense: B-DA-C.

physical memory

start

address

SwivelView

240

window

160

image seen by programmer = image in display buffer

display

start

address

window

image refreshed by S1D13704

SwivelView

240

160

Figure 12-2: Relationship Between The Screen Image and the Image Refreshed by S1D13704

Hardware Functional Specification S1D13704 Issue Date: 01/02/08 X26A-A-001-04

Page 90

Page 82 Epson Research and Development

Vancouver Design Center

12.2.1 How to Set Up Alternate SwivelView Mode

The following descri bes the regi ster sett ings needed to set up Alter nate Swivel View Mode for a 160x240x8 bpp image.

• Select Alternate SwivelView Mode: REG[1Bh] bit 7 = 1 and bit 6 = 1

• The display refresh circuitry starts at pixel “B”, therefore the Screen 1 Start Address register must be programmed with the address of pixel “B”, or

REG 0Dh[]REG 0Ch[]AddressOfPixelB=,

AddressOfPixelA ByteOffset+()=

160pixels 8bpp×

AddressOfPixelA

AddressOfPixelA 9Fh+=

Where bpp is bits-per-pixel and bpb is bi ts-p er-by te .

• The Line Byte Count Register for SwivelView Mode must be set to the image width in bytes, i.e.

REG 1 Ch[]

160

----------------------------------------- -

8bpb()8bpp()÷

160

-------- -160A0h==== 1



--------------------------------------------



8bpb

1–+=

Where bpb is bits-per-b yte an d bpp is bits-per-pixel.

• Panning is achieved by changing the Screen 1 Start Address register:

• Increment the register by 1 to pan horizontally by one byte, e.g. one pixel in 8 bpp mode

• Increment the regist er by the value in the Line Byte Count regi ster to pan ve rticall y by one line, e.g. add A0h to pan by one line in the example above

S1D13704 Hardware Functional Specification X26A-A-001-04 Issue Date: 01/02/08

Page 91

Epson Research and Development Page 83

Vancouver Design Center

12.3 Comparison Between Default and Alternate SwivelView Modes

Table 12-1: Default and Alternate SwivelView Mode Comparison

Item Default SwivelView Mode Alternate SwivelView Mode

The width of the rotated image must be a power of 2. In most cases, a virtual image is required where the right-hand side of the virtual image is unused and memory is wasted. For exam ple, a

Memory Requirements

Clock Requirements

Power Consumption Lowest power consumption. Higher than Default Mode. Panning Vertical panning in 2 line increments. Vertical panning in 1 line increments. Performance Nominal pe rform an ce. Higher performance th an De fau lt Mod e.

160x240x8bpp image would normally require only 38,400 bytes - possible within the 40K byte addres s s pa ce, but the virtual image is 256x240x8bpp which needs 61,440 bytes - not possible.

CLK need only be as fast as the required PCLK.

Does not require a virtual imag e.

MCLK, and hence CLK, need to be 2x PCLK. For example, if the panel requires a 3MHz PCLK, then CLK must be 6MHz. Note that 25MHz is the maximum CLK, so PCLK cannot be higher than 12.5MHz in this mode.

12.4 SwivelView Mode Limitations

The only limitation to using SwivelView mode on the S1D13705. is that split screen operation is not supported.

Hardware Functional Specification S1D13704 Issue Date: 01/02/08 X26A-A-001-04

Page 92

Page 84 Epson Research and Development

Vancouver Design Center

13 Power Save Modes

Two Power Save Modes have been incorporated into the S1D13704 to accommodate the need for power reduction in the hand-held devices market. These modes are enabled as follows:

Table 13-1: Power Save Mode Select ion

Hardware Power

Save

Not Configured or 0 0 0 Software Power Save Mode Not Configured or 0 0 1 reserved Not Configured or 0 1 0 reserved Not Configured or 0 1 1 Normal Operation

Configured and 1 X X Hardware P ower Save Mode

Software Power

13.1 Software Power Save Mode

Software Power Save Mode sav es power by powering down the pa nel and stopping dis play refresh accesses to the display buffer.

Table 13-2: Software Power Save Mode Summary

• Registers read/write accessib le

• Memory read/write accessible

• LCD outputs are forced low

13.2 Hardware Power Save Mode

Save Bit 1

Software Power

Save Bit 0

Mode

Hardware Power Save Mode saves power by powering down the panel, stopping accesses to the display buffer and registers, and disabling the Host Bus Interface.

Table 13-3: Hardware Power Save Mode Summary

• Host Interface not accessible

• Memory read/write not accessible

• LCD outputs are forced low

S1D13704 Hardware Functional Specification X26A-A-001-04 Issue Date: 01/02/08

Page 93

Epson Research and Development Page 85

Vancouver Design Center

13.3 Power Save Mode Function Summary

Table 13-4: Power Save Mode Function Summary

IO Access Possible? No Yes Yes

Memory Access Possible? No Yes Yes

Sequence Controller Ru nni ng? No No Yes

Display Active? No No Yes

LCDPWR Inactive Inactive Active

FPDAT[11:0], FPSHIFT (see note ) Forced Low Forced Low Active

FPLINE, FPFRAME, DRDY Forced Low Forced Low Active

Note

When FPDAT[11:8] are designated as GPIO outputs, the output state prior to enabling the Power Save Mode is maintained. When FPDAT[11:8] are designated as GPIO inputs, unused inputs must be tied to either IO V face Pin Mapping,” on page 23.

13.4 Panel Power Up/Down Sequence

After chip re s et or when ent ering/exitin g a power save mode, the Panel Interface sign als follow a power o n/off sequenc e shown belo w. This sequenc e is essent ial to prev ent damage to the LCD panel.

Hardware

Power Save

Software

Power Save

or GND - see Table 5-3: “LCD Inter-

Normal

Hardware Functional Specification S1D13704 Issue Date: 01/02/08 X26A-A-001-04

Page 94

Page 86 Epson Research and Development

RESET#

Vancouver Design Center

Software Power Save

REG[03h] bits [1:0]

Hardware Power Save

LCDPWR

(CNF4 = Low)

LCDPWR

(CNF4 = Hi)

Panel Interface

Output Signals

(except LCDPWR)

00 11 00 11

Power Save Mode

0 frame 127 frames 0 frame

power-down p ower-uppower-up

Figure 13-1: Panel On/Off Sequence

After chip reset, LCDPWR is inactive and the rest of the panel interface output signals are held ‘low’. Software initializes the chip (i.e. programs the registers) and then - as a last step set - programs REG[03h] bits [1:0] to 11. This starts t he power-up sequence as sh own. The power-up/power-down sequence delay is 127 frames.

The power-up/power-down sequence also occurs when exiting/entering Software Power Save Mode.

13.5 Turning Off BCLK Between Accesses

BCLK may be turned off (held low) betwee n acces ses if the following rules are obser ved:

1. BCLK must be turned off/on in a glitch free manner

2. BCLK must continue for a period equal to [8T

BCLK

+ 12T

access (RDY# asserted or WAIT# deas serted).

3. BCLK must be present for at least one T

S1D13704 Hardware Functional Specification X26A-A-001-04 Issue Date: 01/02/08

before the start of an access.

BCLK

] after the end of the

MCLK

Page 95

Epson Research and Development Page 87

Vancouver Design Center

13.6 Clock Requirements

The following table shows what clock is required for which function in the S1D13704.

Table 13-5: S1D13704 Internal Clock Requirements

Function BCLK CLKI

Is required during register acc esse s. BCLK can be shut down between accesses: allow eight BCLK pulses plus 12 MCLK pulses

Memory Read/Write

Software Power Save Required

Hardware Power Save Not Required

(8T

BCLK

+ 12T

) after the last access

MCLK

before shutting BCLK off. Allow one BCLK pulse after starting up BCLK before the next access

Is required during memory ac ce sses. BCLK can be shut down between accesses: allow eight BCLK pulses plus 12 MCLK pulses (8T

BCLK

+ 12T

) after the last access

MCLK

before shutting BCLK off. Allow one BCLK pulse after starting up BCLK before the next access

Not Required

Required

Can be stopped after 128 frames from entering Software Power Save, i.e. after REG[03h] bits 1-0 = 11

Can be stopped after 128 frames from entering Hardware Power Save

Hardware Functional Specification S1D13704 Issue Date: 01/02/08 X26A-A-001-04

Page 96

Page 88 Epson Research and Development

Vancouver Design Center

14 Mechanical Data

QFP14 - 80 pin

± 0.4

14.0

± 0.1

12.0

60 41

Index

Unit: mm

± 0.1

± 0.4

14.0

12.0

+ 0.05

- 0.025

0.125

120

0.5

± 0.1

0.18

+ 0.1

- 0.05

1.4

± 0.2

0.1

0.5

0~10°

1.0

Figure 14-1: Mechanical Drawing QFP14

S1D13704 Hardware Functional Specification X26A-A-001-04 Issue Date: 01/02/08

Page 97

S1D13704 Embedded Memory Color LCD Controller

Programming Notes and Examples

EPSON is a registered trademark of Seiko Epson Corporation. All other Trademarks are the property of their respective owners

Page 98

Page 2 Epson Research and Development

Vancouver Design Center

THIS PAGE LEFT BLANK

S1D13704 Programming Notes and Examples X26A-G-002-03 Issue Date: 01/02/12

Page 99

Epson Research and Development Page 3

Vancouver Design Center

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.1 Frame Rate Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3 Memory Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

3.1 Display Buffer Location . . . . . . . . . . . . . . . . . . . . . . . . . . 11

3.1.1 1 Bit-Per-Pixel (2 Colors/Gray Shades) . . . . . . . . . . . . . . . . . . . . . . . . 11

3.1.2 2 Bit-Per-Pixel (4 Colors/Gray Shades) . . . . . . . . . . . . . . . . . . . . . . . . 12

3.1.3 4 Bit-Per-Pixel (16 Colors/Gray Shades) . . . . . . . . . . . . . . . . . . . . . . . 12

3.1.4 Eight Bit-Per-Pixel (256 Colors) . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

4 Look-Up Table (LUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

4.1 Look-Up Table Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 14

4.2 Look-Up Table (LUT) Organization . . . . . . . . . . . . . . . . . . . . . . 19

5 Advanced Techniques . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

5.1 Virtual Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

5.1.1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

5.1.2 Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

5.2 Panning and Scrolling . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

5.2.1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

5.2.2 Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

5.3 Split Screen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

5.3.1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

5.3.2 Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

6 LCD Power Sequencing and Power Save Modes . . . . . . . . . . . . . . . . . . . 34

6.1 LCD Power Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . 34

6.2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

6.3 LCD Enable/Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

7 SwivelView™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

7.1 Introduction To SwivelView . . . . . . . . . . . . . . . . . . . . . . . . . 36

7.2 Default SwivelView Mode . . . . . . . . . . . . . . . . . . . . . . . . . 36

7.3 Alternate SwivelView Mode . . . . . . . . . . . . . . . . . . . . . . . . . 37

7.4 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

7.5 Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

7.6 Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

8 Identifying the S1D13704 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

9 Hardware Abstraction Layer (HAL) . . . . . . . . . . . . . . . . . . . . . . . . . . 47

9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Programming Notes and Examples S1D13704 Issue Date: 01/02/12 X26A-G-002-03

Page 100

Page 4 Epson Research and Development

Vancouver Design Center

9.2 API for 13704HAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47

9.2.1 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

9.2.2 M iscellaneous HAL Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

9.2.3 Advanced HAL Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

9.2.4 Register / Memory Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

9.2.5 Power Save . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

9.2.6 Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

9.2.7 LUT Manipulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

10 Sample Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61

10.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

10.1.1 Sample code using the S1D13704 HAL API . . . . . . . . . . . . . . . . . . . . . 61

10.1.2 Sample code without using the S1D13704 HAL API . . . . . . . . . . . . . . . . . 64

10.1.3 Header Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

S1D13704 Programming Notes and Examples X26A-G-002-03 Issue Date: 01/02/12

Epson S1D13704 Technical Manual

Customer Support Information

Comprehensive Support Tools

Evaluation / Demonstration Board

Chip Documentation

Software

Application Engineering Support

Table of Contents

S1D13704 EMBEDDED MEMORY COLOR LCD CONTROLLER

DESCRIPTION

FEATURES

Memory Interface

CPU Interface

Display Support

Po wer Down Modes

Display Modes

Clock Source

General Purpose IO Pins

Operating Voltage

Package

SYSTEM BLOCK DIAGRAM

Hardware Functional Specification

Table of Contents

List of Tables

List of Figures

1 Introduction

1.1 Scope

1.2 Overview Description

2 Features

2.1 Integrated Frame Buffer

2.2 CPU Interface

2.3 Display Support

2.4 Display Modes

2.5 Clock Source

2.6 Miscellaneous

2.7 Package

3 Typical System Implementation Diagrams

4 Functional Block Diagram

4.1 Functional Block Descriptions

4.1.1 Host Interface

4.1.2 Memory Controller

4.1.3 Sequence Controller

4.1.4 Look-Up Table

4.1.5 LCD Interface

4.1.6 Power Save

5 Pins

5.1 Pinout Diagram

5.2 Pin Description

Key:

5.2.1 Host Interface

5.2.2 LCD Interface

5.2.3 Clock Input

5.2.4 Miscellaneous

5.2.5 Power Supply

5.3 Summary of Configuration Options

5.4 Host Bus Interface Pin Mapping

5.5 LCD Interface Pin Mapping

6 D.C. Characteristics

7 A.C. Characteristics

7.1 Bus Interface Timing

7.1.1 SH-4 Interface Timing

7.1.2 SH-3 Interface Timing

7.1.3 Motorola M68K #1 Interface Timing

7.1.4 Motorola M68K #2 Interface Timing

7.1.5 Generic #1 Interfac e Timing

7.1.6 Generic #2 Interface Timing

7.2 Clock Input Requirements

7.3 Display Interface

7.3.1 Power On/Reset Timing

7.3.2 Power Down/Up Timing

7.3.3 Single Monochrome 4-Bit P a nel Timing

7.3.4 Single Monochrome 8-Bit P a nel Timing

7.3.5 Single Color 4-Bit Panel Timing

7.3.6 Single Color 8-Bit Panel Timing (Format 1)

7.3.7 Single Color 8-Bit Panel Timing (Format 2)

7.3.8 Dual Monochrome 8-Bit Panel Timing

7.3.9 Dual Color 8-Bit Panel Timing

7.3.10 9/12-Bit TFT/D-TFD Panel Timing

8 Registers

8.1 Register Mapping