Epson S1D13504 User Manual
S1D13504 Color Graphics LCD/CRT Controller
S1D13504
TECHNICAL MANUAL
Document Number: X19A-Q-002-14
Copyright © 1997, 2001 Epson Research and Development, Inc. All Rights Reserved.
Information in this document is subject to change without notice. You may download and use this document, but only for your own use in
evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Resear ch and Development, Inc. disclaims any
representation that the contents of this document are accurate or current. The Programs/Technologies described in this document may contain
material protected under U.S. and/or International Patent laws.
EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.
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S1D13504 TECHNICAL MANUAL
X19A-Q-002-14 Issue Date: 01/04/18
Epson Research and Development Page 3
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Customer Support Information
Comprehensive Support T ools
Seiko Epson Corp. provides to the system designer and computer OEM manufacturer a complete set
of resources and tools for the development of graphics systems.
Evaluation / Demonstration Board
• Assembled and fully tested graphics evaluation board with installation guide and schematics.
• To borrow an evaluation board, pleas e c ontact your local Seik o Epson Corp. sales repres entative.
Chip Documentation
• Technical manual includes Data Sheet, Application Notes, and Programmer’s Reference.
Software
• OEM Utilities.
• User Utilities.
• Evaluation Software.
• To obtain these programs, contact Application Engineering Support.
Application Engineering Support
Engineering and Sales Support is provided by:
Japan
Seiko Epson Corporation
Electronic Devices Marketing Division
421-8, Hino, Hino-shi
Tokyo 191-8501, Japan
Tel: 042-587-5812
Fax: 042-587-5564
http://www.epson.co.jp
Hong Kong
Epson Hong Kong Ltd.
20/F., Harbour Centre
25 Harbour Road
Wanchai, Hong Kong
Tel: 2585-4600
Fax: 2827-4346
North America
Epson Electronics America, Inc.
150 River Oaks Parkway
San Jose, CA 95134, USA
Tel: (408) 922-0200
Fax: (408) 922-0238
http://www.eea.epson.com
Europe
Epson Europe Electronics GmbH
Riesstrasse 15
80992 Munich, Germany
Tel: 089-14005-0
Fax: 089-14005-110
Taiwan
Epson Taiwan Technology
& Trading Ltd.
10F, No. 287
Nanking East Road
Sec. 3, Taipei, Taiwan
Tel: 02-2717-7360
Fax: 02-2712-9164
Singapore
Epson Singapore Pte., Ltd.
No. 1
Temasek Avenue #36-00
Millenia Tower
Singapore, 039192
Tel: 337-7911
Fax: 334-2716
TECHNICAL MANUAL S1D13504
Issue Date: 01/04/18 X19A-Q-002-14
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S1D13504 TECHNICAL MANUAL
X19A-Q-002-14 Issue Date: 01/04/18
ENERGY
SAVING
EPSON
GRAPHICS
S1D13504
S1D13504 COLOR GRAPHICS LCD/CRT CONTROLLER
■
DESCRIPTION
The S1D13504 is a low cost, low power, color/monochrome LCD/CRT controller interfacing to a wide range of CPUs
and LCDs. The S1D13504 architecture is de si gned to meet the requirements of embedded markets such as Office
Automation equipment, Mobile Communi ca tions devices and Hand-Held PCs where Wi ndow s CE may serve as a
primary o perat ing system.
The S1D13504 supports LCD interfaces with data widths up to 16-bits. Using Frame Rate Modulation (FRM), it can
display 16 shades of gray on monochrome LCD panels, up to 4096 colors on passive color LCD, and 64K colors on
active matrix TFT LCD panels. CRT support is handled through the use of an external RAMDAC interface allowing
simultaneous display of both the CRT and LCD panel. A 16-bit memory interface supports up to 2M bytes of FPMDRAM or EDO-DRAM. Supports flexible operating voltages from 2.7V to 5.5V.
■ FEATURES
Memory Interface
16-bit EDO-DRAM or FPM- DRAM in ter face.
•
Memory size options:
•
512K bytes using one 256K×16 device.
2M bytes using one 1M×16 device.
Addressable as a single linear address space.
•
CPU Interface
Suppor ts the following inter faces:
•
Hitachi SH-3.
Motorola M68K.
ISA bus.
MPU bus interface with programmable READY.
i386/486 bus.
Philips MIPS PR31500/ 31700.
NEC MIPS V
CPU write buffer.
•
Display Support
4/8-bit monochrome passive LCD interface.
•
4/8/16-bit color passive LCD interface.
•
Single-panel, single-drive displays.
•
Dual-panel, dual- drive displays.
•
Direct support for 9/12-bit TFT; 18-bit TFT is sup-
•
ported up to 64K color depth (16-bit data).
External RAMDAC support using the upper byte of
•
the LCD data bus for the RAMDAC pixel data bus.
Simultaneous display of CRT and 4/8-bit passive
•
or 9-bit TFT panels, regardless of resolution.
Maximum resolution of 800x600 pixels at a color
•
depth of 16 bpp.
R
4102.
Display Modes
1/2/4/8/16 bit-per-pixel (bpp) support on LCD.
•
1/2/4/8 bit-per-pixel (bpp) on CRT.
•
Up to 16 shades of gray using FRM on
•
monochrome passive LCD panels.
Up to 4096 colors on passive LCD panels.
•
Up to 64K colors on active matrix TFT LCD in
•
16 bpp modes.
Split Screen Display: allows two different images to
•
be simultaneously displayed.
Virtual Display Support: displays images larger
•
than the panel size through the use of panning.
Double Buffering/multi-pages: provides smooth ani-
•
mation and instantaneous screen update.
Acceleration of screen upd ates by allocati ng ful l
•
display buffer bandwidth to CPU.
Clock Source
Single clock input for both pixel and memory clocks.
•
Memory clock can be input clock or (input clock/2),
•
providing flexibility to use CPU bus clock as input.
Pixel clock can be memory clock or (memory clock/
•
2), (memory clock/3) or (memory clock/4).
Power Down Modes
Two pow er do wn modes: one softw are / one hardware.
•
LCD Power Sequencing.
•
General Purpose IO pins
Up to 12 General Purpose IO pins are available.
•
Operating Voltage
2.7 volts to 5.5 volts.
•
Package
128-pin QFP15 surface mount package
•
144-pin QFP20 surface mount package
•
February 2001
X19A-C-002-11 1
GRAPHICS
S1D13504
■
SYSTEM BLOCK DIAGRAM
RAMDAC
EDO-DRAM
FPM-DRAM
CPU
Control
Clock
S1D13504
Digital Out
CONTACT YOUR SALES REPRESENTATIVE FOR THESE
COMPREHENSIVE DESIGN TOOLS:
• S1D13504 Technical Manual
• S5U13504 Evaluation Boards
• Windows
CE Display Driver
• CPU Independent Software Utilities
Japan
Seiko Epson Corporation
Electronic Devices Marketing Division
421-8, Hino, Hino-shi
Tokyo 191-8501, Japan
Tel: 042-587-5812
Fax: 042-587-5564
http://www.epson.co.jp
North America
Epson Electronics America, Inc.
150 River Oaks Parkway
San Jose, CA 95134, USA
Tel: (408) 922-0200
Fax: (408) 922-0238
http://www.eea.epson.com.com
Analog Out
CRT
Flat Panel
FOR SYSTEM INT EGRATION SERVICES
FOR WINDOWS® CE CONTACT:
Epson Research & Development, Inc.
Suite #320 - 11120 Horseshoe Way
Richmond, B.C., Canada V7A 5H7
Tel: (604) 275-5151
Fax: (604) 275-2167
Email: wince@erd.epson.com
http://www.erd.epson.com
Taiwan, R.O.C.
Epson Taiwan Technology
& Trading Ltd.
10F, No. 287
Nanking East Road
Sec. 3, Taipei, Taiwan, R.O.C.
Tel: 02-2717-7360
Fax: 02-2712-9164
Hong Kong
Epson Hong Kong Ltd.
20/F., Harbour Centre
25 Harbour Road
Wanchai, Hong Kong
Tel: 2585-4600
Fax: 2827-4346
Copyright ©1997, 2001 Epson Research and Development, Inc. All rights reserved. VDC
Information in this document is subject to change without notice. You may download and use this documen t, but only for your own use in evaluatin g Seiko Epson/
EPSON products. You may not modify the document. Epson Research and Developm ent, Inc. disclaims any re presentation that the content s of this document are
accurate or current. The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws.
EPSON is a registered trademark of Seiko Epson Corporation. Microsoft, Windows, and the Windo ws CE Logo are registered trademarks of Microsoft Corporation.
Europe
Epson Europe Electronics GmbH
Riesstrasse 15
80992 Munich, Germany
Tel: 089-14005-0
Fax: 089-14005-110
Singapore
Epson Singapore Pte., Ltd.
No. 1
Temasek Avenue #36-00
Millenia Tower
Singapore, 039192
Tel: 337-7911
Fax: 334-2716
X19A-C-002-11 2
S1D13504 Color Graphics LCD/CRT Controller
Hardware Functional Specification
Document Number: X19A-A-002-18
Copyright © 1997, 2001 Epson Research and Development, Inc. All Rights Reserved.
Information in this document is subject to change without notice. You may download and use this document, but only for your own use in
evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Resear ch and Development, Inc. disclaims any
representation that the contents of this document are accurate or current. The Programs/Technologies described in this document may contain
material protected under U.S. and/or International Patent laws.
EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.
Page 2 Epson Research and Development
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S1D13504 Hardware Functional Specification
X19A-A-002-18 Issue Date: 01/01/30
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Table of Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.1 Scope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.2 Overview Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.1 Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.2 CPU Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.3 Display Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.4 Display Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.5 Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.6 Miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.7 Package and Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3 Typical System Implementation Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4 Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.1 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.2 Functional Block Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.2.1 Host Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.2.2 Memory Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.2.3 Display FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.2.4 Look-Up Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.2.5 LCD Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.2.6 Power Save . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5 Pin Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.1 Pinout Diagram for S1D13504F00A . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.2 Pinout Diagram for S1D13504F01A . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.3 Pinout Diagram for S1D13504F02A . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.4 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.4.1 Host Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.4.2 Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.4.3 LCD Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.4.4 Clock Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.4.5 CRT and External RAMDAC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.4.6 Miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.4.7 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.5 Summary of Configuration Options . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.6 Multiple Function Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
6 D.C. Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
7 A.C. Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7.1 CPU Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7.1.1 SH-3 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
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7.1.2 MC68K Bus 1 Interface Timing (e.g. MC68000) . . . . . . . . . . . . . . . . . . . . . . . .38
7.1.3 MC68K Bus 2 Interface Timing (e.g. MC68030) . . . . . . . . . . . . . . . . . . . . . . . .40
7.1.4 Generic MPU Interface Synchronous Timing . . . . . . . . . . . . . . . . . . . . . . . . . .42
7.1.5 Generic MPU Interface Asynchronous Timing . . . . . . . . . . . . . . . . . . . . . . . . .44
7.2 Clock Input Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
7.3 Memory Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
7.3.1 EDO-DRAM Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
7.3.2 EDO-DRAM Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
7.3.3 EDO-DRAM Read-Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
7.3.4 EDO-DRAM CAS Before RAS Refresh Timing . . . . . . . . . . . . . . . . . . . . . . . .53
7.3.5 EDO-DRAM Self-Refresh Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
7.3.6 FPM-DRAM Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
7.3.7 FPM-DRAM Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
7.3.8 FPM-DRAM Read-Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
7.3.9 FPM-DRAM CAS# Before RAS# Refresh Timing . . . . . . . . . . . . . . . . . . . . . . .6 1
7.3.10 FPM-DRAM Se lf-Refresh Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
7.4 Display Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
7.4.1 Power-On/Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
7.4.2 Suspend Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
7.4.3 Single Monochrome 4-Bit Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
7.4.4 Single Monochrome 8-Bit Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
7.4.5 Single Color 4-Bit Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
7.4.6 Single Color 8-Bit Panel Timing (Format 1) . . . . . . . . . . . . . . . . . . . . . . . . . . .71
7.4.7 Single Color 8-Bit Panel Timing (Format 2) . . . . . . . . . . . . . . . . . . . . . . . . . . .73
7.4.8 Single Color 16-Bit Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
7.4.9 Dual Monochrome 8-Bit Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
7.4.10 Dual Color 8-Bit Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
7.4.11 Dual Color 16-Bit Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
7.4.12 16-Bit TFT Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
7.4.13 CRT Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
7.4.14 External RAMDAC Read / Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
8 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
8.1 Register Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
8.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
8.2.1 Revision Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
8.2.2 Memory Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
8.2.3 Panel/Monitor Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
8.2.4 Display Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
8.2.5 Clock Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
8.2.6 Power Save Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
8.2.7 Miscellaneous Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
8.2.8 Look-Up Table Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
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8.2.9 External RAMDAC Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
9 Display Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
9.1 Image Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
9.2 Half Frame Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
10 Display Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
10.1 Display Mode Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116
10.2 Image Manipulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118
11 Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119
11.1 Maximum MCLK: PCLK Ratios . . . . . . . . . . . . . . . . . . . . . . . . . . .119
11.2 Frame Rate Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120
12 Look-Up Table Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122
12.1 Gray Shade Display Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122
12.2 Color Display Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124
13 Power Save Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
13.1 Hardware Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128
13.2 Software Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128
13.3 Power Save Mode Function Summary . . . . . . . . . . . . . . . . . . . . . . . . .129
13.4 Pin States in Power Save Modes . . . . . . . . . . . . . . . . . . . . . . . . . . .129
14 Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130
14.1 QFP15-128 (S1D13504F00A) . . . . . . . . . . . . . . . . . . . . . . . . . . . .130
14.2 TQFP15-128 (S1D13504F01A) . . . . . . . . . . . . . . . . . . . . . . . . . . .131
14.3 QFP20-144 (S1D13504F02A) . . . . . . . . . . . . . . . . . . . . . . . . . . . .132
Hardware Functional Specification S1D13504
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List of Tables
Table 2-1: S1D13504 Series Package list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 5-1: Host Interface Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 5-2: Memory Interface Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 5-3: LCD Interface Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 5-4: Clock Input Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 5-5: CRT and RAMDAC Interface Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 5-6: Miscellaneous Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 5-7: Power Supply Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 5-8: Summary of Power On / Reset Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 5-9: Host Bus Interface Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 5-10: Memory Interface Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 5-11: LCD, CRT, RAMDAC Interface Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 6-1: Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 6-2: Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 6-3: Input Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 6-4: Output Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 7-1: SH-3 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 7-2: MC68K Bus 1 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 7-3: MC68K Bus 2 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 7-4: Generic MPU Interface Synchronous Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 7-5: Generic MPU Interface Asynchronous Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 7-6: Clock Input Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 7-7: EDO DRAM Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 7-8: EDO DRAM Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 7-9: EDO DRAM Read-Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 7-10: EDO-DRAM CAS Before RAS Refresh Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 7-11: EDO-DRAM Self-Refresh Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 7-12: FPM DRAM Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 7-13: FPM-DRAM Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 7-14: FPM-DRAM Read-Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 7-15: FPM-DRAM CAS# Before RAS# Refresh Timing . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 7-16: FPM-DRAM CBR Self-Refresh Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 7-17: LCD Panel Power-On/Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 7-18: LCD Panel Suspend Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 7-19: Single Monochrome 4-Bit Panel A.C. Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Table 7-20: Single Monochrome 8-Bit Panel A.C. Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 7-21: Single Color 4-Bit Panel A.C. Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Table 7-22: Single Color 8-Bit Panel A.C. Timing (Format 1) . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Table 7-23: Single Color 8-Bit Panel A.C. Timing (Format 2) . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Table 7-24: Single Color 16-Bit Panel A.C. Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
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Table 7-25: Dual Monochrome 8-Bit Panel A.C. Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
Table 7-26: Dual Color 8-Bit Panel A.C. Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
Table 7-27: Dual Color 16-Bit Panel A.C. Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
Table 7-28: TFT A.C. Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
Table 7-29: CRT A.C. Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
Table 7-30: Generic Bus RAMDAC Read / Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
Table 8-1: S1D13504 Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
Table 8-2: DRAM Refresh Rate Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
Table 8-3: Panel Data Width Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
Table 8-4: FPLINE Polarity Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Table 8-5: FPFRAME Polarity Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
Table 8-6: Simultaneous Display Option Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
Table 8-7: Number of Bits-Per-Pixel Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
Table 8-8: Pixel Panning Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Table 8-9: PCLK Divide Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Table 8-10: Suspend Refresh Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Table 8-11: Minimum Memory Timing Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Table 8-12: RAS-to-CAS Delay Timing Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Table 8-13: RAS Precharge Timing Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Table 8-14: Optimal NRC, NRP, and NRCD Values at Maximum MCLK Frequency . . . . . . . . . . . . . 109
Table 8-15: RGB Index Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Table 9-1: S1D13504 Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Table 11-1: Maximum PCLK Frequency with EDO-DRAM . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Table 11-2: Maximum PCLK Frequency with FPM-DRAM . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Table 11-3: Example Frame Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Table 12-1: Look-Up Table Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Table 13-1: Power Save Mode Function Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Table 13-2: P in States in Power Save Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
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List of Figures
Figure 3-1: Typical System Diagram – SH-3 Bus, 1Mx16 FPM/EDO-DRAM . . . . . . . . . . . . . . . . . 14
Figure 3-2: Typical System Diagram – MC68K Bus 1, 1Mx16 FPM/EDO-DRAM (16-Bit MC68000) . . . . 15
Figure 3-3: Typical System Diagram – MC68K Bus 2, 256Kx16 FPM/EDO-DRAM (32-Bit MC68030) . . 15
Figure 3-4: Typical System Diagram – Generic Bus, 1Mx16 FPM/EDO-DRAM . . . . . . . . . . . . . . . 16
Figure 4-1: System Block Diagram Showing Datapaths . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 5-1: Pinout Diagram of F00A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 5-2: Pinout Diagram of F01A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 5-3: Pinout Diagram of F02A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 7-1: SH-3 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 7-2: MC68K Bus 1 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 7-3: MC68K Bus 2 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 7-4: Generic MPU Interface Synchronous Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 7-5: Generic MPU Interface Asynchronous Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 7-6: Clock Input Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 7-7: EDO-DRAM Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 7-8: EDO-DRAM Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 7-9: EDO-DRAM Read-Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 7-10: EDO-DRAM CAS Before RAS Refresh Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 7-11: EDO-DRAM Self-Refresh Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 7-12: FPM-DRAM Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 7-13: FPM-DRAM Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Figure 7-14: FPM-DRAM Read-Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 7-15: FPM-DRAM CAS# Before RAS# Refresh Timing . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 7-16: FPM-DRAM CBR Self-Refresh Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Figure 7-17: LCD Panel Power-On/Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 7-18: LCD Panel Suspend Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Figure 7-19: Single Monochrome 4-Bit Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Figure 7-20: Single Monochrome 4-Bit Panel A.C. Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Figure 7-21: Single Monochrome 8-Bit Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Figure 7-22: Single Monochrome 8-Bit Panel A.C. Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Figure 7-23: Single Color 4-Bit Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Figure 7-24: Single Color 4-Bit Panel A.C. Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Figure 7-25: Single Color 8-Bit Panel Timing (Format 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Figure 7-26: Single Color 8-Bit Panel A.C. Timing (Format 1) . . . . . . . . . . . . . . . . . . . . . . . . . 72
Figure 7-27: Single Color 8-Bit Panel Timing (Format 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Figure 7-28: Single Color 8-Bit Panel A.C. Timing (Format 2) . . . . . . . . . . . . . . . . . . . . . . . . . 74
Figure 7-29: Single Color 16-Bit Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Figure 7-30: Single Color 16-Bit Panel A.C. Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Figure 7-31: Dual Monochrome 8-Bit Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Figure 7-32: Dual Monochrome 8-Bit Panel A.C. Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
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Figure 7-33: Dual Color 8-Bit Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Figure 7-34: Dual Color 8-Bit Panel A.C. Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Figure 7-35: Dual Color 16-Bit Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Figure 7-36: Dual Color 16-Bit Panel A.C. Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Figure 7-37: 16-Bit TFT Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Figure 7-38: TFT A.C. Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Figure 7-39: CRT Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Figure 7-40: CRT A.C. Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Figure 7-41: Generic Bus RAMDAC Read / Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
Figure 9-1: Display Buffer Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Figure 10-1: 1/2/4/8 Bit-Per-Pixel Format Memory Organization . . . . . . . . . . . . . . . . . . . . . . . 116
Figure 10-2: 15/16 Bit-Per-Pixel Format Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . 117
Figure 10-3: Image Manipulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Figure 12-1: 1 Bit-Per-Pixel – 2-Level Gray-Shade Mode Look-Up Table Architecture . . . . . . . . . . . . 122
Figure 12-2: 2 Bit-Per-Pixel – 4-Level Gray-Shade Mode Look-Up Table Architecture . . . . . . . . . . . . 123
Figure 12-3: 4 Bit-Per-Pixel – 16-Level Gray-Shade Mode Look-Up Table Architecture . . . . . . . . . . . 123
Figure 12-4: 1 Bit-Per-Pixel – 2-Level Color Look-Up Table Architecture . . . . . . . . . . . . . . . . . . 124
Figure 12-5: 2 Bit-Per-Pixel – 4-Level Color Mode Look-Up Table Architecture . . . . . . . . . . . . . . . 125
Figure 12-6: 4 Bit-Per-Pixel – 16-Level Color Mode Look-Up Table Architecture . . . . . . . . . . . . . . 126
Figure 12-7: 8 Bit-Per-Pixel – 256-Level Color Mode Look-Up Table Architecture . . . . . . . . . . . . . . 127
Figure 14-1: Mechanical Drawing QFP15-128 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Figure 14-2: Mechanical Drawing TQFP15-128 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Figure 14-3: Mechanical Drawing QFP20-144 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
S1D13504 Hardware Functional Specification
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1 Introduction
1.1 Scope
This is the Functional Specification for the S1D13504 Series Color Graphics LCD/CRT Controller
Chip. Included in this document are timing diagrams, AC and DC characteristics, register descriptions, and power management descriptions. This document is intended for two audiences: Video
Subsystem Designers and Software Developers.
1.2 Overview Description
The S1D13504 is a low cost, low power color/monochrome LCD/CRT controller interfacing to a
wide range of CPUs and LCDs. The S1D13504 architecture is designed to meet the requ irements of
embedded markets such as Office Automation equipment, Mobile Communications devices and
Hand-Held PCs where Windows CE may serve as a primary operating system.
The S1D13504 supports LCD interfaces with data widths up to 16 bits. Using Frame Rate
Modulation (FRM), it can displa y 16 shades of gray on mo nochrome LCD panels, up t o 4096 colors
on passive color LCDs, and 64K colors on active matrix TFT LCD panels. CRT support is handled
through the use of an external RAMDAC interface allowing simultaneous display of both the CRT
and LCD panel. A 16-bit memory interface supports up to 2M bytes of FPM-DRAM or EDODRAM. Flexible operating voltages from 2.7V to 5.5V provide for very low power consumption.
Hardware Functional Specification S1D13504
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2 Features
2.1 Memory Interface
• 16-bit DRAM interface:
• EDO-DRAM up to 40MHz data rate (80M bytes per second).
• FPM-DRAM up to 25MHz data rate (50M bytes per second).
• Memory size options:
• 512K bytes using one 256K×16 device.
• 2M bytes using one 1M×16 device.
• A configuration register can be programmed to enhance performance by tailoring the memory
control output timing to the DRAM device.
2.2 CPU Interface
• Supports the following interfaces:
2.3 Display Support
• 8/16-bit Hitachi SH-3 bus interface.
• 16-bit interface to 16/32-bit Motorola MC68K microprocessors/microcontrollers.
• Philips MIPS PR31500 / PR31700.
•NEC MIPS V
R
4102.
• 8/16-bit generic interface bus.
• One-Stage write buffer for minimum wait-state CPU writes.
• Registers are memory-mapped; M/R# pin selects between memory and register address space.
• The complete 2M byte display buffer address space is directly and contiguously available
through the 21-bit address bus .
• 4/8-bit monochrome or 4/8/16-bit color passive LCD interface for single-panel, single-drive
displays.
• 8-bit monochrome or 8/16-bit color passive LCD interface for dual-panel, dual-drive displays.
• Direct support for 9/12-bit TFT, 18/24-bi t TFT are suppor ted up to 64 K color depth (16-bi t data).
• External RAMDAC support using the upper byte of the LCD data bus for the RAMDAC pixel
data bus.
• Simultaneous disp lay of CRT and 4/8-bit passive panel or 9-bit TFT panel:
• Normal mode for cases where LCD and CRT image sizes are identical.
• Line-Doubling mode for simultaneous display of 240-line images on 240-line LCD and 480-
line CRT.
• Even-Scan and interlace modes fo r si multaneous display of 480-line images on 240-line LCD
and 480-line CRT.
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2.4 Display Modes
• 1/2/4/8/16 bit-per-pixel modes supported on LCD.
• 1/2/4/8 bit-per-pixel modes supported on CRT.
• Up to 16 shades of gray by FRM on monochrome passive LCD panels; a 16x4 Look-Up Table is
used to map 1/2/4 bit-per-pixel modes into these shades.
• Up to 4096 colors on color passive LCD panels; three 16x4 Look-Up Tables are used to map
1/2/4/8 bit-per-pixel mode s int o thes e col or s, 1 6 bit-per-pixel mode is mapped directly using the
4 most significant bits of the red, green and blue colors.
• Up to 64K colors in 16 bit-per-pixel mode on TFT panel s .
• Split screen mode – allows two different images to be simultaneously displayed.
• Virtual display mode – displays images lar ger than the panel size through the use of panning and
scrolling.
• Double buffering / multi-pages – for smooth animation and instantaneous screen update.
• Fast-Update feature – accelerates screen update by allocating full display buffer bandwidth to
CPU (see REG[23h] bit 7).
2.5 Clock Source
• Single clock input for both pixel and memory clocks.
• Memory clock can be input clock or (input clock)/2 – this provides flexibility to use CPU bus
• Pixel clock can be memory clock, (memory clock)/2, (memory clock)/3 or (memory clock)/4.
2.6 Miscellaneous
• The memory data bus MD[15:0], is used to configure the chip at power-on.
• Up to 12 General Purpose Input/Output pins are available:
• Suspend power save mode is initiated by hardware or software.
• The SUSPEND# pin is used either as an input to initiate Suspend mode, or as a General Purpose
2.7 Package and Pin
clock as input clock.
• GPIO0 is always available.
• GPIO[3:1] are available if upper Memory Address pins are not required for DRAM support.
• GPIO[11:4] are available if there is no external RAMDAC.
Output that can be used to control the LCD backlight – its power-on polarity is selected by an
MD configuration pin.
Table 2-1: S1D13504 Series Package list
Name Package Pin
S1D13504F00A QFP15 128
S1D13504F01A TQFP15 128
S1D13504F02A QFP20 144
Hardware Functional Specification S1D13504
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3 Typical System Implementation Diagrams
SH-3
BUS
A21
CSn#
A[20:0]
D[15:0]
WE1#
BS#
RD/WR#
RD#
WE0#
WAIT#
CKIO
RESET#
M/R#
CS#
AB[20:0]
DB[15:0]
WE1#
BS#
RD/WR#
RD#
WE0#
WAIT#
BUSCLK
RESET#
Power
Management
SUSPEND#
S1D13504
Oscillator
CLKI
RAS#
WE#
MD[15:0]
WE#
D[15:0]
1Mx16
RAS#
LCAS#
LCAS#
MA[11:0]
A[11:0]
FPM/EDO-DRAM
FPDAT[15:8]
FPDAT[7:0]
FPSHIFT
FPFRAME
FPLINE
DRDY
LCDPWR
UCAS#
UCAS#
Figure 3-1: Typical System Diagram – SH-3 Bus, 1Mx16 FPM/EDO-DRAM
UD[7:0]
LD[7:0]
FPSHIFT
FPFRAME
FPLINE
MOD
4/8/16-bit
LCD
Display
S1D13504 Hardware Functional Specification
X19A-A-002-18 Issue Date: 01/01/30
Epson Research and Development Page 15
Vancouver Design Center
.
MC68000
BUS
A[23:21]
FC0, FC1
A[20:1]
D[15:0]
LDS#
UDS#
AS#
R/W#
DTACK#
BCLK
RESET#
Decoder
Decoder
M/R#
CS#
AB[20:1]
DB[15:0]
AB0#
WE1#
BS#
RD/WR#
WAIT#
BUSCLK
RESET#
Power
Management
SUSPEND#
S1D13504
Oscillator
CLKI
RAS#
WE#
MD[15:0]
WE#
D[15:0]
1Mx16
RAS#
LCAS#
LCAS#
MA[11:0]
A[11:0]
FPM/EDO-DRAM
UCAS#
UCAS#
FPDAT[15:8]
FPDAT[7:0]
FPSHIFT
FPFRAME
FPLINE
DRDY
LCDPWR
UD[7:0]
LD[7:0]
FPSHIFT
FPFRAME
FPLINE
MOD
Figure 3-2: Typical System Diagram – MC68K Bus 1, 1Mx16 FPM/EDO-DRAM (16-Bit MC68000)
4/8/16-bit
LCD
Display
MC68030
BUS
A[31:21]
FC0, FC1
D[31:16]
DSACK1#
RESET#
A[20:0]
DS#
AS#
R/W#
SIZ1
SIZ0
BCLK
Decoder
Decoder
M/R#
CS#
AB[20:0]
DB[15:0]
WE1#
BS#
RD/WR#
RD#
WE0#
WAIT#
BUSCLK
RESET#
Power
Management
SUSPEND#
S1D13504
Oscillator
CLKI
RAS#
WE#
MD[15:0]
WE#
RAS#
D[15:0]
256Kx16
LCAS#
LCAS#
MA[8:0]
A[8:0]
FPM/EDO-DRAM
FPDAT[15:8]
FPDAT[7:0]
FPSHIFT
FPFRAME
FPLINE
DRDY
LCDPWR
UCAS#
UCAS#
Figure 3-3: Typical System Diagram – MC68K Bus 2, 256Kx16 FPM/EDO-DRA M (32-Bit MC68030)
UD[7:0]
LD[7:0]
FPSHIFT
FPFRAME
FPLINE
MOD
4/8/16-bit
LCD
Display
Hardware Functional Specification S1D13504
Issue Date: 01/01/30 X19A-A-002-18
Page 16 Epson Research and Development
Vancouver Design Center
.
GENERIC
BUS
RESET#
A21
CSn#
A[20:0]
D[15:0]
WE0#
WE1#
RD0#
RD1#
WAIT#
BCLK
M/R#
CS#
AB[20:0]
DB[15:0]
WE0#
WE1#
RD#
RD/WR#
WAIT#
BUSCLK
RESET#
Power
Management
SUSPEND#
S1D13504
Oscillator
CLKI
RAS#
WE#
MD[15:0]
WE#
D[15:0]
1Mx16
RAS#
LCAS#
LCAS#
MA[11:0]
A[11:0]
FPM/EDO-DRAM
FPDAT[15:8]
FPDAT[7:0]
FPSHIFT
FPFRAME
FPLINE
DRDY
LCDPWR
UCAS#
UCAS#
Figure 3-4: Typical System Diagram – Generic Bus, 1Mx16 FPM/EDO-DRAM
UD[7:0]
LD[7:0]
FPSHIFT
FPFRAME
FPLINE
MOD
4/8/16-bit
LCD
Display
S1D13504 Hardware Functional Specification
X19A-A-002-18 Issue Date: 01/01/30
Epson Research and Development Page 17
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4 Block Description
4.1 Functional Block Diagram
16-bit FPM/EDO
DRAM
Register
CPU
R/W
Host
CPU / MPU
I/F
Bus Clock Memory Clock Pixel Clock
Figure 4-1: System Block Diagram Showing Datapaths
4.2 Functional Block Descriptions
Memory
Controller
Display
FIFO
Power Save
Clocks
Look-Up
Table
CRTC
LCD
I/F
LCD
DAC
Data
DAC
Control
4.2.1 Host Interface
The Host Interface block provides the means for the CPU/MPU to communicate with the display
buffer and internal registers, via one of the supported bus interfaces.
4.2.2 Memory Controller
The Memory Controller block arbitrates between CPU accesses and display refresh accesses as well
as generates the necessary signals to interface to one of th e supported 16-bit memory d evices (FPMDRAM or EDO-DRAM).
4.2.3 Display FIFO
The Display FIFO block fetches display data from the Memory Controller for display refresh.
Hardware Functional Specification S1D13504
Issue Date: 01/01/30 X19A-A-002-18
Page 18 Epson Research and Development
Vancouver Design Center
4.2.4 Look-Up Table
The Look-Up Table block contains three 16x4 Look-Up Tables, one for each primary color. In
monochrome mode only one of these Look-Up Tables is selected and used.
4.2.5 LCD Interface
The LCD Interface block performs frame rate modulation for passiv e LCD panels. It also g enerates
the correct data format and timing control signals for various LCD and TFT panels.
4.2.6 Power Save
The Power Save block contains the power save mode circuitry.
S1D13504 Hardware Functional Specification
X19A-A-002-18 Issue Date: 01/01/30
Epson Research and Development Page 19
Vancouver Design Center
5 Pin Out
5.1 Pinout Diagram for S1D13504F00A
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
COREVDD
DACP0
DACWR#
DACRS0
DACRS1
HRTC
VRTC
VSS
CLKI
SUSPEND#
TESTEN
BUSCLK
VSS
IOVDD
AB20
AB19
AB18
AB17
AB16
AB15
AB14
AB13
AB12
AB11
AB10
AB9
AB8
AB7
AB6
AB5
AB4
AB3
96 95 94 93 92 91 90 89 88 87 86 85 84 83 7475 73 72 71 70 69 68 67 66 6582 81 80 79 78 77 76
VSS
FPDAT13
FPDAT15
FPDAT14
FPDAT10
FPDAT12
FPDAT9
FPDAT11
FPDAT8
VSS
DACCLK
BLANK#
DACRD#
IOVDD
FPDAT7
FPDAT6
FPDAT5
FPDAT4
FPDAT3
FPDAT2
S1D13504F00A
RD/WR#
RESET#
WAIT#
IOVDD
AB2
AB1
BS#
RD#
WE0#
M/R#
CS#
AB0
WE1#
GPIO0
VSS
DB15
DB14
DB12
DB13
DB11
FPDAT1
DB10
FPDAT0
DB9
VSS
DB8
FPSHIFT
DB7
DRDY
DB6
LCDPWR
DB5
FPLINE
DB4
FPFRAME
DB3
VSS
DB2
MD15
DB1
MD0
DB0
MD14
VSS
MD1
MD13
MD2
MD12
MD3
MD11
MD4
MD10
MD5
MD9
MD6
MD8
MD7
VSS
LCAS#
UCAS#
WE#
RAS#
IOVDD
MA9
MA11
MA8
MA10
MA7
MA0
MA6
MA1
MA5
MA2
MA4
MA3
COREVDD
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
1234567891011121314151617181920212223242526272829303132
Figure 5-1: Pinout Diagr am of F 00 A
Package type: 128 pin surface mount QFP15
Hardware Functional Specification S1D13504
Issue Date: 01/01/30 X19A-A-002-18
Page 20 Epson Research and Development
Vancouver Design Center
5.2 Pinout Diagram for S1D13504F01A
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
COREVDD
DACP0
DACWR#
DACRS0
DACRS1
HRTC
VRTC
VSS
CLKI
SUSPEND#
TESTEN
BUSCLK
VSS
IOVDD
AB20
AB19
AB18
AB17
AB16
AB15
AB14
AB13
AB12
AB11
AB10
AB9
AB8
AB7
AB6
AB5
AB4
AB3
96 95 94 93 92 91 90 89 88 87 86 85 84 83 7475 73 72 71 70 69 68 67 66 6582 81 80 79 78 77 76
VSS
FPDAT13
FPDAT15
FPDAT14
FPDAT10
FPDAT12
FPDAT9
FPDAT11
FPDAT8
VSS
DACCLK
BLANK#
DACRD#
IOVDD
FPDAT7
FPDAT6
FPDAT5
FPDAT4
FPDAT3
FPDAT2
S1D13504F01A
RD/WR#
RESET#
WAIT#
IOVDD
AB2
AB1
BS#
RD#
WE0#
M/R#
CS#
AB0
WE1#
GPIO0
VSS
DB15
DB14
DB12
DB13
DB11
FPDAT1
DB10
FPDAT0
DB9
VSS
DB8
FPSHIFT
DB7
DRDY
DB6
LCDPWR
DB5
FPLINE
DB4
FPFRAME
DB3
VSS
DB2
MD15
DB1
MD0
DB0
MD14
VSS
MD1
MD13
MD2
MD12
MD3
MD11
MD4
MD10
MD5
MD9
MD6
MD8
MD7
VSS
LCAS#
UCAS#
WE#
RAS#
IOVDD
MA9
MA11
MA8
MA10
MA7
MA0
MA6
MA1
MA5
MA2
MA4
MA3
COREVDD
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
1234567891011121314151617181920212223242526272829303132
Figure 5-2: Pinout Diagram of F01A
Package type: 128 pin surface mount TQFP15
S1D13504 Hardware Functional Specification
X19A-A-002-18 Issue Date: 01/01/30
Epson Research and Development Page 21
Vancouver Design Center
5.3 Pinout Diagram for S1D13504F02A
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
108107106105104103102101100
FPDAT15
VSS
NC
NC
NC
NC
COREVDD
DACP0
DACWR#
DACRS0
DACRS1
HRTC
VRTC
VSS
CLKI
SUSPEND#
TESTEN
BUSCLK
VSS
IOVDD
AB20
AB19
AB18
AB17
AB16
AB15
AB14
AB13
AB12
AB11
AB10
AB9
AB8
AB7
AB6
AB5
AB4
AB3
NC
NC
AB2
NC
NC
9998 97 96 95 94 93 92 91 90 89 88 878685 84 8382 81 80 79 78 77 76 75 7473
FPDAT13
FPDAT14
FPDAT10
FPDAT12
FPDAT9
FPDAT11
DACCLK
VSS
FPDAT8
IOVDD
FPDAT7
DACRD#
BLANK#
FPDAT6
S1D13504F02A
RD/WR#
M/R#
CS#
AB0
AB1
WE0#
RD#
BS#
RESET#
WE1#
IOVDD
WAIT#
GPIO0
VSS
FPDAT3
FPDAT2
FPDAT4
FPDAT5
DB15
DB14
DB12
DB13
VSS
FPSHIFT
DRDY
LCDPWR
FPLINE
FPFRAME
VSS
MD15
MD14
FPDAT0
FPDAT1
DB10
DB11
DB8
DB9
DB5
DB7
DB4
DB6
MD0
NC
NC
72
NC
71
NC
MD1
70
MD13
69
68
MD2
67
MD12
66
MD3
65
MD11
64
MD4
63
MD10
62
MD5
61
MD9
60
MD6
59
MD8
58
MD7
57
VSS
56
LCAS#
55
UCAS#
54
WE#
53
RAS#
52
IOVDD
51
MA9
50
MA11
49
MA8
48
MA10
47
MA7
46
MA0
45
MA6
44
MA1
43
MA5
42
MA2
41
MA4
40
MA3
NC
NC
39
38
37
COREVDD
DB3
DB2
VSS
DB1
DB0
NC
NC
1 2 3 4 5 6 7 8 9 101112 131415 16 171819 20 21 22 23 24 25 2627 28 293031 32 33 34 35 36
Figure 5-3: Pinout Diagr am of F 02 A
Package type: 144 pin surface mount QFP20
Hardware Functional Specification S1D13504
Issue Date: 01/01/30 X19A-A-002-18
Page 22 Epson Research and Development
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5.4 Pin Description
Key:
I = Input
O = Output
IO = Bi-Directional (Input/Output)
P=Power pin
C = CMOS level input
CD = CMOS level input with pull-down resistor (typical values of 100KΩ/180KΩ at 5V/3.3V respectively)
CS = CMOS level Schmitt input
COx = CMOS output driver, x denotes driver type (1=3/-1.5mA, 2=6/-3mA, 3=12/-6mA)
TSx = Tri-state CMOS output driver, x denotes driver type (1=3/-1.5mA, 2=6/-3mA, 3=12/-6mA)
TSxD =
CNx = CMOS lo w-noi se output driver, x denotes driver type (1=3/-1. 5m A, 2=6/-3 mA, 3=12/-6m A)
Tri-state CMOS output driver with pull-down resistor (typical values of 100KΩ/180KΩ at 5V/3.3V
respectively), x denotes driver type (1=3/-1.5mA, 2=6/-3mA, 3=12/-6mA)
5.4.1 Host Interface
Table 5-1: Host Interface Pin Descriptions
Pin #
Pin Name Type
AB0 I 3 5 CS Hi-Z
AB[20:1] I
DB[15:0] IO 16-31 18-33 C/TS2 Hi-Z
F00A
F01A
111-128
1, 2
F02A
125-142
3,4
Driver
C Hi-Z System address bus bits [20:1].
Reset =
0 Value
Description
This pin has multiple functions.
• F or SH-3 m ode, this pin inputs system address bit 0 (A0).
• For MC68K Bus 1, this pin inputs the lower data strobe (LDS#).
• For MC68K Bus 2, this pin inputs system address bit 0 (A0).
• For Generic Bus, this pin inputs system address bit 0 (A0).
See Table 5-9: “Host Bus Interface Pin Mapping,” on page 32 for
summary.
System data bus. Unused data pins should be connected to IO
V
.
DD
• For SH-3 mode, these pins are connected to D[15:0].
• For MC68K Bus 1, these pins are connected to D[15:0].
• F or MC68K Bus 2, these pins are c onnected to D[31:16] for 32bit devices (e.g. MC68030) or D[15:0] for 16-bit devices (e.g.
MC68340).
• F or Gen eric Bu s , these pi n s are connected to D[15:0].
See Table 5-9: “Host Bus Interface Pin Mapping,” on page 32
summary.
for
S1D13504 Hardware Functional Specification
X19A-A-002-18 Issue Date: 01/01/30
Epson Research and Development Page 23
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Table 5-1: Host Inter face Pin Descriptions (Continued )
Pin Name Type
F00A
F01A
Pin #
F02A
Driver
Reset =
0 Value
Description
This pin has multiple functions.
• For SH-3 mode, this pin inputs the write enable signal for the
upper data byte (WE1#).
• For MC68K Bus 1, this pin inputs the upper data strobe
WE1# I 9 11 CS Hi-Z
(UDS#).
• For MC68K Bus 2, this pin inputs the data strobe (DS#).
• For Generic Bus, this pin inputs the write enable signal for the
upper data byte (WE1#).
See Table 5-9: “Host Bus Interfa ce Pin Ma ppi ng,” on page 32.
This input pin is used to select between the memory and register
address spaces of the S1D13504. M/R# is set high to access the
M/R# I 5 7 C Hi-Z
memory and low to access the registers. See Section 8.1,
“Register Mapping”
on page 90
.
See Table 5-9: “Host Bus Interfa ce Pin Ma ppi ng,” on page 32.
CS# I 4 6 C Hi-Z
BUSCLK I 108 122 C Hi-Z
Chip select input. See Table 5-9: “Host Bus Interface Pin
Mapping,” on page 32.
System bus clock. See Table 5-9: “Host Bus Interface Pin
Mapping,” on page 32.
This pin has multiple functions.
• For SH-3 mode, this pin inputs the bus start signal (BS#).
BS# I 6 8 CS Hi-Z
• For MC68K Bus 1, this pin inputs the address strobe (AS#).
• For MC68K Bus 2, this pin inputs the address strobe (AS#).
• For Generic Bus, this pin must be tied to IO V
DD
.
See Table 5-9: “Host Bus Interfa ce Pin Ma ppi ng,” on page 32.
This pin has multiple functions.
• For SH-3 mode, this pin inputs the RD/WR# signal. The
S1D13504 needs this si gnal for early decode of the bus cycle.
RD/WR# I 10 12 CS Hi-Z
• For MC68K Bus 1, this pin inputs the R/W# signal.
• For MC68K Bus 2, this pin inputs the R/W# signal.
• For Generic Bus, this pin inputs the read command for the
upper data byte (RD1# ).
See Table 5-9: “Host Bus Interfa ce Pin Ma ppi ng,” on page 32.
This pin has multiple functions.
• For SH-3 mode, this pin inputs the read signal (RD#).
• For MC68K Bus 1, this pin must be tied to IO V
RD#I79CSHi-Z
• For MC68K Bus 2, this pin inputs the bus size bit 1 (SIZ1).
DD
.
• For Generic Bus, this pin inputs the read command for the
lower data byte (RD0#).
See Table 5-9: “Host Bus Interfa ce Pin Ma ppi ng,” on page 32.
Hardware Functional Specification S1D13504
Issue Date: 01/01/30 X19A-A-002-18
Page 24 Epson Research and Development
Vancouver Design Center
Table 5-1: Host Interface Pin Descriptions (Continued)
Pin Name Type
F00A
F01A
Pin #
F02A
Driver
Reset =
0 Value
Description
This pin has multiple functions.
• For SH-3 mode, this pin inputs the write enable signal for the
lower data byte (WE0#).
WE0# I 8 10 CS Hi-Z
• For MC68K Bus 1, this pin must be tied to IO V
• For MC68K Bus 2, this pin inputs the bus size bit 0 (SIZ0).
DD.
• For Generic Bus, this pin inputs the write enable signal for the
lower data byte (WE0#).
See Table 5-9: “Host Bus Interface Pin Mapping,” on page 32.
The active polarity of the WAIT# out put is configurable on the
rising edge of RESET# - see Section 5.5,
Configuration Opti ons”
on page 31.
“Summary of
This pin has multiple functions.
• F or SH-3 m ode, this pin outputs the wait reques t sign al
(WAIT#); MD5 must be pulled low during reset by the internal
pull-down resistor.
WAIT# O 13 15 TS2 Hi-Z
• For MC68K Bus 1, this pin outputs the data transfer
acknowle dge signal (DTACK#); MD5 m u st be pull ed high
during reset by an external pull-up resistor.
• For MC68K Bus 2, this pin outputs the data transfer and size
acknowle dge bit 1 (DSACK1#); MD5 must be pulled high
during reset by an external pull-up resistor.
• F or Generic Bus , thi s pin ou tputs th e wai t signa l (WAIT#); MD5
must be pulled low du ring res et by the internal pull-down
resistor.
See Table 5-9: “Host Bus Interface Pin Mapping,” on page 32.
RESET# I 11 13 CS Input 0
Active low input to clear all internal registers and to force all
signals to their inacti ve states.
S1D13504 Hardware Functional Specification
X19A-A-002-18 Issue Date: 01/01/30
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