EPSON S1D13305 service manual
MF1167-02
查询S1D13503F00A供应商
LCD Controller ICs
S1D13305 Series
Technical Manual
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Seiko Epson does not assume any liability of any kind arising out of any inaccuracies contained in this
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approval from another government agency.
✽ In this manual, Zilog's Z80-CPU or its equivalent shall be called Z80, Intel's 8085A or its equivalent shall
be called 8085 and Motorola's MC6809 and MC6802 or their equivalents shall be called 6809 and 6802,
respectively.
® stands for registered trade mark.
All other product names mentioned herein are trademarks and/or registered trademarks of their respective owners.
© Seiko Epson Corporation 2001 All rights reserved.
The information of the product number change
Starting April 1, 2001, the product number will be changed as listed below. To order from April 1,
2001 please use the new product number. For further information, please contact Epson sales
representative.
Configuration of product number
Devices
S1 D 13706 F 00A0 00
Packing specification
Specification
Package (B: CSP, F: QFP)
Corresponding model number
Model name (D: driver, digital products)
Product classification (S1: semiconductor)
Evaluation Board
S5U 13705 P00C
Specification
Corresponding model number (13705: for S1D13705)
Product classification (S5U: development tool for semiconductor)
Comparison table between new and previous number
• S1D13305 Series • S1D1370x Series
Previous No.
SED1335 Series
SED1335D0A
SED1335F0A
SED1335F0B
• S1D1350x Series
Previous No.
SED135x Series
SED1353D0A
SED1353F0A
SED1353F1A
SED1354F0A
SED1354F1A
SED1354F2A
SED1355F0A
SED1356F0A
New No.
S1D13305 Series
S1D13305D00A
S1D13305F00A
S1D13305F00B
New No.
S1D1350x Series
S1D13503D00A
S1D13503F00A
S1D13503F01A
S1D13504F00A
S1D13504F01A
S1D13504F02A
S1D13505F00A
S1D13506F00A
Previous No.
SED137x Series
SED1374F0A
SED1375F0A
SED1376B0A
SED1376F0A
SED1378 Series
• S1D13A0x Series
Previous No.
SED13Ax Series
SED13A3F0A
SED13A3B0B
SED13A4B0B
New No.
S1D1370x Series
S1D13704F00A
S1D13705F00A
S1D13706B00A
S1D13706F00A
S1D13708 Series
New No.
S1D13A0x Series
S1D13A03F00A
S1D13A03B00B
S1D13A04B00B
• S1D1380x Series
Previous No.
SED138x Series
SED1386F0A
S1D1380x Series
S1D13806F00A
New No.
Comparison table between new and previous number of Evaluation Boards
• S1D1350x Series
Previous No.
SDU1353#0C
SDU1354#0C
SDU1355#0C
SDU1356#0C
New No. Previous No.
S5U13503P00C
S5U13504P00C
S5U13505P00C
S5U13506P00C
• S1D1370x Series • S1D1380x Series
New No. Previous No.
SDU1374#0C
SDU1375#0C
SDU1376#0C
SDU1376BVR
SDU1378#0C
S5U13704P00C
S5U13705P00C
S5U13706P00C
S5U13706B32R
S5U13708P00C
SDU1386#0C S5U13806P00C
• S1D13A0x Series
Previous No.
SDU13A3#0C
SDU13A4#0C
New No.
S5U13A03P00C
S5U13A04P00C
New No.
CONTENTS
CONTENTS
1. OVERVIEW ................................................................................................................................................................. 1
2. FEATURES ................................................................................................................................................................. 1
3. BLOCK DIAGRAM....................................................................................................................................................... 2
4. PINOUTS..................................................................................................................................................................... 3
5. PIN DESCRIPTION ..................................................................................................................................................... 4
5.1. S1D13305F00A/00B Pin Summary ................................................................................................................... 4
5.2. Pin Functions ..................................................................................................................................................... 5
5.2.1. Power supply ......................................................................................................................................... 5
5.2.2. Oscillator ................................................................................................................................................ 5
5.2.3. Microprocessor interface........................................................................................................................ 5
5.2.4. Display memory control ......................................................................................................................... 6
5.2.5. LCD drive signals................................................................................................................................... 7
6. SPECIFICATIONS ....................................................................................................................................................... 7
6.1. Absolute Maximum Ratings ............................................................................................................................... 7
6.2. S1D13305 .......................................................................................................................................................... 8
6.3. S1D13305F Timing Diagrams.......................................................................................................................... 10
6.3.1. 8080 family interface timing ................................................................................................................. 10
6.3.2. 6800 family interface timing ................................................................................................................. 11
6.3.3. Display memory read timing ................................................................................................................ 12
6.3.4. Display memory write timing ................................................................................................................ 13
6.3.5. SLEEP IN command timing ................................................................................................................. 15
6.3.6. External oscillator signal timing............................................................................................................ 16
6.3.7. LCD output timing ................................................................................................................................ 17
7. PACKAGE DIMENSIONS ......................................................................................................................................... 19
7.1. S1D13305F00A ............................................................................................................................................... 19
7.2. S1D13305F00B ............................................................................................................................................... 19
8. INSTRUCTION SET .................................................................................................................................................. 20
8.1. The Command Set ........................................................................................................................................... 20
8.2. System Control Commands ............................................................................................................................. 21
8.2.1. SYSTEM SET ...................................................................................................................................... 21
8.2.1.1. C ........................................................................................................................................... 21
8.2.1.2. M0 ......................................................................................................................................... 21
8.2.1.3. M1 ......................................................................................................................................... 21
8.2.1.4. M2 ......................................................................................................................................... 22
8.2.1.5. W/S ....................................................................................................................................... 22
8.2.1.6. IV .......................................................................................................................................... 23
8.2.1.7. FX ......................................................................................................................................... 24
8.2.1.8. WF ........................................................................................................................................ 25
8.2.1.9. FY ......................................................................................................................................... 25
8.2.1.10. C/R ....................................................................................................................................... 25
8.2.1.11. TC/R ..................................................................................................................................... 26
8.2.1.12. L/F ........................................................................................................................................ 26
8.2.1.13. AP ......................................................................................................................................... 27
8.2.2. SLEEP IN ............................................................................................................................................. 27
8.3. Display Control Commands ............................................................................................................................. 28
8.3.1. DISP ON/OFF ...................................................................................................................................... 28
8.3.1.1. D ........................................................................................................................................... 28
8.3.1.2. FC ......................................................................................................................................... 28
8.3.1.3. FP ......................................................................................................................................... 28
8.3.2. SCROLL............................................................................................................................................... 29
8.3.2.1. C ........................................................................................................................................... 29
8.3.2.2. SL1, SL2 ............................................................................................................................... 30
S1D13305 Series EPSON i
Technical Manual
CONTENTS
8.3.3. CSRFORM ........................................................................................................................................... 34
8.3.3.1. CRX ...................................................................................................................................... 34
8.3.3.2. CRY ...................................................................................................................................... 34
8.3.3.3. CM ........................................................................................................................................ 34
8.3.4. CSRDIR ............................................................................................................................................... 34
8.3.5. OVLAY ................................................................................................................................................. 35
8.3.5.1. MX0, MX1 ............................................................................................................................. 35
8.3.5.2. DM1, DM2 ............................................................................................................................ 36
8.3.5.3. OV ........................................................................................................................................ 36
8.3.6. CGRAM ADR ....................................................................................................................................... 36
8.3.7. HDOT SCR .......................................................................................................................................... 37
8.3.7.1. D0 to D2 ............................................................................................................................... 37
8.4. Drawing Control Commands ............................................................................................................................ 37
8.4.1. CSRW .................................................................................................................................................. 37
8.4.2. CSRR ................................................................................................................................................... 38
8.5. Memory Control Commands ............................................................................................................................ 38
8.5.1. MWRITE .............................................................................................................................................. 38
8.5.2 MREAD ................................................................................................................................................ 39
9. DISPLAY CONTROL FUNCTIONS ........................................................................................................................... 40
9.1. Character Configuration................................................................................................................................... 40
9.2. Screen Configuration ....................................................................................................................................... 42
9.2.1. Screen configuration ............................................................................................................................ 42
9.2.2. Display address scanning .................................................................................................................... 42
9.2.3. Display scan timing .............................................................................................................................. 45
9.3. Cursor Control.................................................................................................................................................. 46
9.3.1. Cursor register function........................................................................................................................ 46
9.3.2. Cursor movement ................................................................................................................................ 46
9.3.3. Cursor display layers ........................................................................................................................... 46
9.4. Memory to Display Relationship ...................................................................................................................... 48
9.5. Scrolling ........................................................................................................................................................... 51
9.5.1. On-page scrolling ................................................................................................................................. 51
9.5.2. Inter-page scrolling .............................................................................................................................. 51
9.5.3. Horizontal scrolling............................................................................................................................... 52
9.5.4. Bidirectional scrolling ........................................................................................................................... 53
9.5.5. Scroll units ........................................................................................................................................... 53
10. CHARACTER GENERATOR .................................................................................................................................... 54
10.1. CG Characteristics ........................................................................................................................................... 54
10.1.1. Internal character generator................................................................................................................. 54
10.1.2. External character generator ROM ...................................................................................................... 54
10.1.3. Character generator RAM .................................................................................................................... 54
10.2. CG Memory Allocation ..................................................................................................................................... 55
10.3. Setting the Character Generator Address ........................................................................................................ 56
10.3.1. M1 = 1 .................................................................................................................................................. 56
10.3.2. CG RAM addressing example ............................................................................................................. 57
10.4. Character Codes .............................................................................................................................................. 58
11. MICROPROCESSOR INTERFACE .......................................................................................................................... 59
11.1. System Bus Interface ....................................................................................................................................... 59
11.1.1. 8080 series .......................................................................................................................................... 59
11.1.2. 6800 series .......................................................................................................................................... 59
11.2. Microprocessor Synchronization ...................................................................................................................... 59
11.2.1. Display status indication output ........................................................................................................... 59
11.2.2. Internal register access ........................................................................................................................ 59
11.2.3. Display memory access ....................................................................................................................... 59
11.3. Interface Examples .......................................................................................................................................... 61
11.3.1. Z80 to S1D13305 series interface ....................................................................................................... 61
11.3.2. 6802 to S1D13305 series interface...................................................................................................... 61
ii EPSON S1D13305 Series
Technical Manual
CONTENTS
12. DISPLAY MEMORY INTERFACE ............................................................................................................................. 62
12.1. Static RAM ....................................................................................................................................................... 62
12.2. Supply Current during Display Memory Access ............................................................................................... 63
13. OSCILLATOR CIRCUIT ............................................................................................................................................ 63
14. STATUS FLAG .......................................................................................................................................................... 63
15. RESET....................................................................................................................................................................... 65
16. APPLICATION NOTES ............................................................................................................................................. 65
16.1. Initialization Parameters ................................................................................................................................... 65
16.1.1. SYSTEM SET instruction and parameters........................................................................................... 65
16.1.2. Initialization example............................................................................................................................ 66
16.1.3. Display mode setting example 1: combining text and graphics .......................................................... 72
16.1.4. Display mode setting example 2: combining graphics and graphics .................................................. 73
16.1.5. Display mode setting example 3: combining three graphics layers .................................................... 75
16.2. System Overview ............................................................................................................................................. 76
16.3 System Interconnection ................................................................................................................................... 77
16.3.1. S1D13305F .......................................................................................................................................... 77
16.4. Smooth Horizontal Scrolling ............................................................................................................................. 79
16.5. Layered Display Attributes ............................................................................................................................... 80
16.5.1. Inverse display ..................................................................................................................................... 80
16.5.2. Half-tone display .................................................................................................................................. 80
16.5.2.1. Menu pad display ................................................................................................................. 80
16.5.2.2. Graph display ....................................................................................................................... 81
16.5.3. Flashing areas ..................................................................................................................................... 81
16.5.3.1. Small area ............................................................................................................................ 81
16.5.3.2. Large area ............................................................................................................................ 81
16.6. 16 × 16-dot Graphic Display............................................................................................................................. 81
16.6.1. Command usage.................................................................................................................................. 81
16.6.2. Kanji character display ......................................................................................................................... 81
17. INTERNAL CHARACTER GENERATOR FONT ....................................................................................................... 84
18. GLOSSARY OF TERMS ........................................................................................................................................... 85
Request for Information on S1D13305 Series ................................................................................................................. 86
S1D13305 Series EPSON iii
Technical Manual
OVERVIEW/FEATURES
1. OVERVIEW
The S1D13305 series is a controller IC that can display
text and graphics on LCD panel.
The S1D13305 series can display layered text and graphics, scroll the display in any direction and partition the
display into multiple screens.
The S1D13305 series stores text, character codes and bitmapped graphics data in external frame buffer memory.
Display controller functions include transferring data
from the controlling microprocessor to the buffer memory,
reading memory data, converting data to display pixels
and generating timing signals for the buffer memory,
LCD panel.
The S1D13305 series has an internal character generator
with 160, 5 × 7 pixel characters in internal mask ROM.
The character generators support up to 64, 8 × 16 pixel
characters in external character generator RAM and up to
256, 8 × 16 pixel characters in external character generator ROM.
2. FEATURES
• Text, graphics and combined text/graphics display
modes
• Three overlapping screens in graphics mode
• Up to 640 × 256 pixel LCD panel display resolution
• Programmable cursor control
• Smooth horizontal and vertical scrolling of all or part
of the display
• 1/2-duty to 1/256-duty LCD drive
• Up to 640 × 256 pixel LCD panel display resolution
memory
• 160, 5 × 7 pixel characters in internal mask-programmed character generator ROM
• Up to 64, 8 × 16 pixel characters in external character
generator RAM
• Up to 256, 8 × 16 pixel characters in external character
generator ROM
• 6800 and 8080 family microprocessor interfaces
• Low power consumption—3.5 mA operating current
DD = 3.5V), 0.05 µA standby current
(V
• Package
line-up Package
S1D13305F00A QFP5-60 pin
S1D13305F00B QFP6-60 pin
• 2.7 to 5.5 V (S1D13305F)
S1D13305 Series EPSON 1
Technical Manual
BLOCK DIAGRAM
3. BLOCK DIAGRAM
Cursor
Address
Controller
Video RAM
VCE
VA0 to VA15
Character
Generator RAM
VRD, VWR (S1D13305F)
Display
Address
Controller
Microprocessor Interface
RES
SEL0
SEL1
Refresh
Counter
RD, WR
A0, CS
Character
Generator ROM
Input/Output
Register
Dot Counter
D0 to D7
VD0 to VD7
Character
Generator
ROM
LCD
LP, WF
YSCL, YD, YDIS
LCD ControllerVideo RAM Interface
Layered
Controller
Oscillator
XG
XSCL
XD0 to XD3
XD
2 EPSON S1D13305 Series
Technical Manual
4. PINOUTS
◊
S1D13305F00A
XG
SEL1
SEL2WRRDNCNC
RES
VRD
VCE
VWR
VA0
VA1
VA2
VA3
VA4
VA5
VA6
VA7
◊
S1D13305F00B
VD4
VD5
VD6
VD7
YSCLYDYDISWFLP
VSSXSCL
XECL
PINOUTS
XD0
XD1
XD2
RES
NCNCRD
3145
WR
VD3
VD2
VD1
VD0
VA15
VA14
VA13
VA12
VA11
VA10
VA9
VA8
VA7
VA6
NC
VD3
VA8
VA9
VA10
VA11
VA12
VA13
NC
VA14
VA15
VD0
VD1
VD2
XD
CS
A0
DD
V
D0
D1
D2
D3
D4
D5
D6
60
1
5
6
Index
D7
XD3
XD2
S1D13305F00A
SS
V
XD1
XD0
XECL
XSCL
404550
30
29
201510
LP
YD
WF
VD7
VD6
VD5
YSCL
VD4
YDIS
46
S1D13305F00B
Index
60
115
VA5
VA4
VA3
VA2
VA1
VA0
VCE
VRD
VWR
30
16
SEL 2
XD3
D7
D6
D5
D4
D3
D2
D1
D0
DD
V
A0
CS
XD
XG
SEL1
S1D13305 Series EPSON 3
Technical Manual
PIN DESCRIPTION
5. PIN DESCRIPTION
5.1. S1D13305F00A/00B Pin Summary
Name
VA0 to VA15
VWR 44 7 Output VRAM write signal
VCE 45 8 Output Memory control signal
VRD 46 9 Output VRAM read signal
RES 47 10 Input Reset
NC 28, 48, 49 11, 12, 60 — No connection
RD 50 13 Input
WR 51 14 Input
SEL2 52 15 Input
SEL1 53 16 Input
XG 54 17 Input Oscillator connection
XD 55 18 Output Oscillator connection
CS 56 19 Input Chip select
A0 57 20 Input Data type select
DD 58 21 Supply 2.7 to 5.5V supply
V
D0 to D7
XD0 to XD3 7 to 10 30 to 33 Output X-driver data
XECL 11 34 Output X-driver enable chain clock
XSCL 12 35 Output X-driver data shift clock
SS 13 36 Supply Ground
V
LP 14 37 Output Latch pulse
WF 15 38 Output Frame signal
YDIS 16 39 Output
YD 17 40 Output Scan start pulse
YSCL 18 41 Output Y-driver shift clock
VD0 to VD7 19 to 26 42 to 49 Input/output VRAM data bus
S1D13305F00A S1D13305F00B
27 to 28 1 to 6
30 to 43 50 to 59
59 to 60
1 to 6
Number
Type Description
Output VRAM address bus
8080 family: Read signal
6800 family: Enable clock (E)
8080 family: Write signal
6800 family: R/W signal
8080 or 6800 family interface
select
8080 or 6800 family interface
select
22 to 29 Input/output Data bus
Power-down signal when display is
blanked
4 EPSON S1D13305 Series
Technical Manual
PIN DESCRIPTION
5.2. Pin Functions
5.2.1. Power supply
Pin Name Function
DD
V
SS
V
Note: The peak supply current drawn by the S1D13305 series may be up to ten times the average supply current. The power
supply impedance must be kept as low as possible by ensuring that supply lines are sufficiently wide and by placing 0.47 µF
decoupling capacitors that have good high-frequency response near the device’s supply pins.
5.2.2. Oscillator
Pin Name Function
XG
XD
5.2.3. Microprocessor interface
Pin Name Function
D0 to D7 Tristate input/output pins. Connect these pins to an 8- or 16-bit microprocessor bus.
SEL1, SEL2
2.7 to 5.5V supply.
This may be the same supply as the controlling microprocessor.
Ground
Crystal connection for internal oscillator (See section 13). This pin can be driven by an external
clock source that satisfies the timing specifications of the EXT φ0 signal (See section 6.3.6).
Crystal connection for internal oscillator. Leave this pin open when using an external clock
source.
Microprocessor interface select pin. The S1D13305 series supports both 8080 family
processors (such as the 8085 and Z80®) and 6800 family processors (such as the 6802
and 6809).
SEL1 SEL2* Interface A0 RD WR CS
0 0 8080 family A0 RD WR CS
1 0 6800 family A0 E R/W CS
Note: SEL1 should be tied directly to VDD or VSS to prevent noise. If noise does appear on SEL1, decouple it to ground using a
capacitor placed as close to the pin as possible.
S1D13305 Series EPSON 5
Technical Manual
PIN DESCRIPTION
Pin Name Function
8080 family interface
A0 RD WR Function
0 0 1 Status flag read
1 0 1 Display data and cursor address read
0 1 0 Display data and parameter write
A0
RD or E
WR or R/W
CS
RES
1 1 0 Command write
6800 family interface
A0 R/W E Function
0 1 1 Status flag read
1 1 1 Display data and cursor address read
0 0 1 Display data and parameter write
1 0 1 Command write
When the 8080 family interface is selected, this signal acts as the active-LOW read strobe. The
S1D13305 series output buffers are enabled when this signal is active.
When the 6800 family interface is selected, this signal acts as the active-HIGH enable clock.
Data is read from or written to the S1D13305 series when this clock goes HIGH.
When the 8080 family interface is selected, this signal acts as the active-LOW write strobe. The
bus data is latched on the rising edge of this signal.
When the 6800 family interface is selected, this signal acts as the read/write control signal. Data
is read from the S1D13305 series if this signal is HIGH, and written to the S1D13305 series if
it is LOW.
Chip select. This active-LOW input enables the S1D13305 series. It is usually connected
to the output of an address decoder device that maps the S1D13305 series into the memory
space of the controlling microprocessor.
This active-LOW input performs a hardware reset on the S1D13305 series. It is a
Schmitt-trigger input for enhanced noise immunity; however, care should be taken to ensure
that it is not triggered if the supply voltage is lowered.
5.2.4. Display memory control
The S1D13305 series can directly access static RAM and
PROM. The designer may use a mixture of these two
Pin Name Function
VA0 to VA15
16-bit display memory address. When accessing character generator RAM or ROM, VA0 to
VA3, reflect the lower 4 bits of the S1D13305 series’s row counter.
VD0 to VD7 8-bit tristate display memory data bus. These pins are enabled when VR/W is LOW.
VWR Active-LOW display memory write control output.
VRD Active-LOW display memory read control output.
VCE Active-LOW static memory standby control signal. VCE can be used with CS.
6 EPSON S1D13305 Series
types of memory to achieve an optimum trade-off between low cost and low power consumption.
Technical Manual
5.2.5. LCD drive signals
In order to provide effective low-power drive for LCD
matrixes, the S1D13305 series can directly control both
the X- and Y-drivers using an enable chain.
Pin Name Function
XD0 to XD3
XSCL
XECL
LP
WF
YSCL
YD
YDIS
4-bit X-driver (column drive) data outputs. Connect these outputs to the inputs of the X-driver
chips.
The falling edge of XSCL latches the data on XD0 to XD3 into the input shift registers of the
X-drivers. To conserve power, this clock halts between LP and the start of the following display
line (See section 6.3.7).
The falling edge of XECL triggers the enable chain cascade for the X-drivers.
Every 16th clock pulse is output to the next X-driver.
LP latches the signal in the X-driver shift registers into the output data latches. LP is a fallingedge triggered signal, and pulses once every display line.
Connect LP to the Y-driver shift clock on modules.
LCD panel AC drive output. The WF period is selected to be one of two values with SYSTEM
SET command.
The falling edge of YSCL latches the data on YD into the input shift registers of the
Y-drivers. YSCL is not used with driver ICs which use LP as the Y-driver shift clock.
YD is the data pulse output for the Y drivers. It is active during the last line of each frame, and
is shifted through the Y drivers one by one (by YSCL), to scan the display’s common
connections.
Power-down output signal. YDIS is HIGH while the display drive outputs are active.
YDIS goes LOW one or two frames after the sleep command is written to the S1D13305
series. All Y-driver outputs are forced to an intermediate level (de-selecting the display
segments) to blank the display. In order to implement power-down operation in the LCD unit,
the LCD power drive supplies must also be disabled when the display is disabled by YDIS.
PIN DESCRIPTION/SPECIFICATIONS
6. SPECIFICATIONS
6.1. Absolute Maximum Ratings
Parameter Symbol Rating Unit
Supply voltage range V
Input voltage range V
Power dissipation P
Operating temperature range T
Storage temperature range T
Soldering temperature (10 seconds). See note 1. T
Notes:
1. The humidity resistance of the flat package may be reduced if the package is immersed in solder. Use a soldering technique
that does not heatstress the package.
2. If the power supply has a high impedance, a large voltage differential can occur between the input and supply voltages. Take
appropriate care with the power supply and the layout of the supply lines. (See section 6.2.)
SS
3. All supply voltages are referenced to V
S1D13305 Series EPSON 7
Technical Manual
= 0V.
DD
IN
D
opg
stg
solder
–0.3 to 7.0
–0.3 to VDD + 0.3 V
300 mW
–20 to 75 °C
–65 to 150 °C
260 °C
V
SPECIFICATIONS
6.2. S1D13305
VDD = 4.5 to 5.5V, VSS = 0V, Ta = –20 to 75°C
Parameter Symbol Condition
Supply voltage V
Register data retention voltage V
Input leakage current I
Output leakage current I
Operating supply current I
Quiescent supply current I
Oscillator frequency f
OSC
External clock frequency f
Oscillator feedback resistance R
DD
OH
LI
VI = VDD. See note 5. — 0.05 2.0 µA
LO
VI = VSS. See note 5. — 0.10 5.0 µA
opr
See note 4. — 11 15 mA
Sleep mode,
Q
= VCS = VRD = V
V
OSC1
Measured at crystal,
CL
f
47.5% duty cycle.
See note 6.
Min. Typ. Max.
4.5 5.0 5.5 V
2.0 — 6.0 V
DD
1.0 — 10.0 MHz
1.0 — 10.0 MHz
0.5 1.0 3.0 MΩ
TTL
HIGH-level input voltage V
LOW-level input voltage V
HIGH-level output voltage V
LOW-level output voltage V
IHT
See note 1. 0.5V
ILT
See note 1. V
IOH = –5.0 mA.
OHT
See note 1.
OLT
IOL = 5.0 mA. See note 1. — — VSS + 0.4 V
2.4 — — V
CMOS
HIGH-level input voltage V
LOW-level input voltage V
HIGH-level output voltage V
LOW-level output voltage V
IHC
See note 2. 0.8V
ILC
See note 2. V
OHC
IOH = –2.0 mA. See note 2.
OLC
IOH = 1.6 mA. See note 2.
VDD – 0.4 — — V
Open-drain
LOW-level output voltage V
OLN
IOL = 6.0 mA.
Schmitt-trigger
Rising-edge threshold voltage V
Falling-edge threshold voltage V
Notes:
1. D0 to D7, A0, CS, RD, WR, VD0 to VD7, VA0 to VA15, VRD, VWR and VCE are TTL-level inputs.
2. SEL1 is CMOS-level inputs. YD, XD0 to XD3, XSCL, LP, WF, YDIS are CMOS-level outputs.
3. RES is a Schmitt-trigger input. The pulsewidth on RES must be at least 200 µs. Note that pulses of more than a few seconds
will cause DC voltages to be applied to the LCD panel.
4. f
OSC
= 10 MHz, no load (no display memory), internal character generator, 256 × 200 pixel display. The operating
supply current can be reduced by approximately 1 mA by setting both CLO and the display OFF.
5. VD0 to VD7 and D0 to D7 have internal feedback circuits so that if the inputs become high-impedance, the input
state immediately prior to that is held. Because of the feedback circuit, input current flow occurs when the
inputs are in an intermediate state.
6. Because the oscillator circuit input bias current is in the order of µA, design the printed circuit board so as to
reduce leakage currents.
T+
See note 3. 0.5V
T–
See note 3. 0.2V
Rating
— 0.05 20.0 µA
DD
—VDDV
SS
SS
——V
——V
— 0.2V
DD
—VDDV
— 0.2V
DD
0.7V
DD
DD
0.3V
DD
DD
DD
SS
+ 0.4 V
SS
+ 0.4 V
0.8V
DD
0.5V
DD
Unit
V
V
V
V
8 EPSON S1D13305 Series
Technical Manual
VDD = 2.7 to 4.5 V, VSS = 0 V, Ta = –20 to 75˚C unless otherwise noted
SPECIFICATIONS
Parameter Symbol Condition
Supply voltage VDD 2.7 3.5 4.5 V
Register data retention voltage VOH 2.0 — 6.0 V
Input leakage current ILI VI = VDD. See note 5. — 0.05 2.0 µA
Output leakage current ILO VI = VSS. See note 5. — 0.10 5.0 µA
DD = 3.5 V. See note 4. — 3.5 —
Operating supply current Iopr
Quiescent supply current I
Oscillator frequency fOSC
External clock frequency fCL 47.5% duty cycle. 1.0 — 8.0 MHz
Oscillator feedback resistance Rf
TTL
HIGH-level input voltage VIHT See note 1. 0.5 VDD —VDD V
LOW-level input voltage VILT See note 1. VSS — 0.2 VDD V
HIGH-level output voltage VOHT
LOW-level output voltage VOLT IOL = 3.0 mA. See note 1. — — VSS + 0.4 V
CMOS
HIGH-level input voltage VIHC See note 2. 0.8 VDD —VDD V
LOW-level input voltage VILC See note 2. VSS — 0.2 VDD V
HIGH-level output voltage VOHC
LOW-level output voltage VOLC IOH = 1.6 mA. See note 2. — — VSS + 0.4 V
Open-drain
LOW-level output voltage VOLN IOL = 6.0 mA. — — VSS + 0.4 V
Schmitt-trigger
Rising-edge threshold voltage VT+ See note 3. 0.5 VDD 0.7 VDD 0.8 VDD V
Falling-edge threshold voltage V
Q
T– See note 3. 0.2 VDD 0.3 VDD 0.5 VDD V
V
See note 4. — — 7.0
Sleep mode,
VOSC1 = VCS = VRD = VDD
Measured at crystal,
See note 6.
IOH = –3.0 mA. See note 1.
IOH = –2.0 mA. See note 2.
Min. Typ. Max.
— 0.05 20.0 µA
1.0 — 8.0 MHz
0.7 — 3.0 MΩ
2.4 — — V
VDD – 0.4 — — V
Rating
Unit
mA
Notes
1. D0 to D7, A0, CS, RD, WR, VD0 to VD7, VA0 to VA15, VRD, VWR and VCE are TTL-level inputs.
2. SEL1 is CMOS-level inputs. YD, XD0 to XD3, XSCL, LP, WF, YDIS are CMOS-level outputs.
3. RES is a Schmitt-trigger input. The pulsewidth on RES must be at least 200 µs. Note that pulses of more than a few seconds will
cause DC voltages to be applied to the LCD panel.
4.
fOSC = 10 MHz, no load (no display memory), internal character generator, 256 × 200 pixel display. The operating supply current can
be reduced by approximately 1 mA by setting both CLO and the display OFF.
5. VD0 to VD7 and D0 to D7 have internal feedback circuits so that if the inputs become high-impedance, the input state immediately
prior to that is held. Because of the feedback circuit, input current flow occurs when the inputs are in an intermediate state.
6. Because the oscillator circuit input bias current is in the order of µA, design the printed circuit board so as to reduce leakage currents.
S1D13305 Series EPSON 9
Technical Manual
SPECIFICATIONS
6.3. S1D13305F Timing Diagrams
6.3.1. 8080 family interface timing
AO, CS
t
AW8
WR, RD
t
D0 to D7
(Write)
t
CC
DS8
t
CYC8
t
AH8
t
DH8
t
ACC8
D0 to D7
(Read)
Ta = –20 to 75°C
Signal Symbol Parameter
t
A0, CS
WR, RD
D0 to D7
Note: For memory control and system control commands:
AH8
t
AW8
t
CYC8
t
t
DS8
DH8
t
t
ACC8
t
OH8
t
CYC8
For all other commands:
t
CYC8
Address hold time 10 — 10 — ns
Address setup time 0 — 0 — ns
System cycle time
CC
Strobe pulsewidth 120 — 150 — ns
Data setup time 120 — 120 — ns
Data hold time 5 — 5 — ns
RD access time — 50 — 80 ns
Output disable time 10 50 10 55 ns
= 2tC + tCC + t
= 4tC + tCC + 30
CEA
+ 75 > t
ACV
+ 245
t
OH8
DD
= 4.5 to 5.5V VDD = 2.7 to 4.5V
V
Min. Max. Min. Max.
See note.
—
See note.
Unit Condition
—ns
CL = 100pF
10 EPSON S1D13305 Series
Technical Manual
6.3.2. 6800 family interface timing
E
R/W
A0, CS
D0 to D7
(Write)
D0 to D7
(Read)
Note: t
CYC6
indicates the interval during which CS is LOW and E is HIGH.
SPECIFICATIONS
t
CYC6
t
AW6
t
ACC6
t
EW
t
AH6
t
t
DS6
DH6
t
OH6
Ta = –20 to 75°C
DD
= 4.5 to 5.5V VDD = 2.7 to 4.5V
Signal Symbol Parameter
t
A0,
CS,
R/W
D0 to D7
CYC6
t
AW6
t
AH6
t
DS6
t
DH6
t
OH6
t
ACC6
System cycle time
Address setup time 0 — 10 — ns
Address hold time 0 — 0 — ns
Data setup time 100 — 120 — ns
Data hold time 0 — 0 — ns
Output disable time 10 50 10 75 ns
Access time — 85 — 130 ns
V
Min. Max. Min. Max.
See note.
—
See note.
—ns
EtEWEnable pulsewidth 120 — 150 — ns
Note: For memory control and system control commands:
= 2tC + tEW + t
t
CYC6
For all other commands:
= 4tC + tEW + 30
t
CYC6
CEA
+ 75 > t
ACV
+ 245
Unit Condition
CL =
100 pF
S1D13305 Series EPSON 11
Technical Manual
SPECIFICATIONS
6.3.3. Display memory read timing
EXTΦ0
VCE
VA0 to VA15
VR/W
VD0 to VD7
t
C
t
W
t
ASC
t
RCS
t
CEA
t
ACV
t
CYR
t
t
CE
AHC
t
W
t
RCH
t
CE3
t
OH2
Ta = –20 to 75°C
DD
= 4.5 to 5.5V VDD = 2.7 to 4.5V
Signal Symbol Parameter
V
Min. Max. Min. Max.
EXT φ0tCClock period 100 — 125 — ns
VCE HIGH-level
VCE
VA0 to
VA15
VRD
VD0 to
VD7
t
t
CE
t
CYR
ASC
t
AHC
t
t
RCS
RCH
t
ACV
t
t
CEA
t
OH2
t
CE3
W
pulsewidth
VCE LOW-level
pulsewidth
Read cycle time 3t
Address setup time to
falling edge of VCE
Address hold time from
falling edge of VCE
Read cycle setup time to
falling edge of VCE
Read cycle hold time
from rising edge of VCE
Address access time — 3tC – 100 — 3tC – 115 ns
VCE access time — 2tC – 80 — 2tC – 90 ns
Output data hold time 0 — 0 — ns
VCE to data off time 0 — 0 — ns
C
– 50 — tC – 50 — ns
t
– 30 — 2tC – 30 — ns
2t
C
C
C
– 70 — tC – 100 — ns
t
– 30 — 2tC – 40 — ns
2t
C
t
C
– 45 — tC – 60 — ns
0.5t
—3tC—ns
C
— 0.5t
C
—ns
Unit Condition
CL = 100
pF
12 EPSON S1D13305 Series
Technical Manual
6.3.4. Display memory write timing
t
C
EXTφO
SPECIFICATIONS
VCE
VA0 to VA15
VR/W
VD0 to VD7
t
W
t
ASC
t
t
WSC
AS
t
DSC
t
CE
t
AHC
t
WHC
t
DHC
t
t
AH2
DH2
t
CA
S1D13305 Series EPSON 13
Technical Manual
SPECIFICATIONS
Ta = –20 to 75°C
DD
= 4.5 to 5.5V VDD = 2.7 to 4.5V
Signal Symbol Parameter
V
Min. Max. Min. Max.
EXT φ0tCClock period 100 — 125 — ns
VCE HIGH-level
W
t
VCE
t
CYW
t
AHC
t
ASC
t
VA0 to
VA15
t
t
t
t
WSC
VWR
t
WHC
t
DSC
VD0 to
VD7 from falling edge of VCE
Note: VD0 to VD7 are latching input/outputs. While the bus is high impedance, VD0 to VD7 retain the write data until the data read
DHC
t
t
DH2
from the memory is placed on the bus.
pulsewidth
VCE LOW-level
CE
pulsewidth
Write cycle time 3t
Address hold time from
falling edge of VCE
Address setup time to
falling edge of VCE
Address hold time from
CA
rising edge of VCE
Address setup time to
AS
falling edge of VWR
Address hold time from
AH2
rising edge of VWR
Write setup time to
falling edge of VCE
Write hold time from
falling edge of VCE
Data input setup time to
falling edge of VCE
Data input hold time
Data hold time from
rising edge of VWR
C
– 50 — tC – 50 — ns
t
2t
C
– 30 — 2tC – 30 — ns
C
C
– 30 — 2tC – 40 — ns
2t
– 70 — tC – 110 — ns
t
C
—3tC—ns
0—0—ns
0—0—ns
10 — 10 — ns
C
– 80 — tC – 115 — ns
t
– 20 — 2tC – 20 — ns
2t
C
C
– 85 — tC – 125 — ns
t
– 30 — 2tC – 30 — ns
2t
C
550550ns
Unit Condition
CL = 100
pF
14 EPSON S1D13305 Series
Technical Manual
6.3.5. SLEEP IN command timing
SPECIFICATIONS
VCE
WR
(Command input)
YDIS
Ta = –20 to 75°C
Signal Symbol Parameter
VCE falling-edge delay
time
YDIS falling-edge delay
time
OSS
+ 40 (t
is the time delay from the sleep state until stable operation)
OSS
WR
Notes:
1. t
2. t
WRD
t
t
WRL
= 18tC + t
WRD
= 36tC × [TC/R] × [L/F] + 70
WRL
t
WRL
SYSTEM SET writeSLEEP IN write
DD
= 4.5 to 5.5V VDD = 2.7 to 4.5V
V
Min. Max. Min. Max.
See note 1.
—
See note 2.
—
See note 1.
—
t
WRD
Unit Condition
—ns
See note 2.
ns
CL = 100
pF
S1D13305 Series EPSON 15
Technical Manual
SPECIFICATIONS
6.3.6. External oscillator signal timing
EXTφ0
Ta = –20 to 75°C
Signal Symbol Parameter
t
EXT φ0
Notes:
1.
2.
RCL
t
FCL
t
t
C
– t
RCL
– t
(t
C
– t
RCL
– t
(t
External clock rise time — 15 — 15 ns
External clock fall time — 15 — 15 ns
External clock
WH
HIGH-level pulsewidth
External clock
WL
LOW-level pulsewidth
C
External clock period 100 — 125 — ns
t
475
FCL
) ×
< tWH, t
FCL
) ×
1000
525
1000
> tWH, t
WL
WL
t
RCL
t
WL
DD
V
t
= 4.5 to 5.5V VDD = 2.7 to 4.5V
t
C
WH
t
FCL
Min. Max. Min. Max
See note 1. See note 2.See note 1. See note 2.
See note 1. See note 2.See note 1. See note 2.
Unit Condition
ns
ns
16 EPSON S1D13305 Series
Technical Manual
6.3.7. LCD output timing
The following characteristics are for a 1/64 duty cycle.
62 63 64 1 2 3 4 60 61 62 63 64
Row
LP
YD
WF
WF
SPECIFICATIONS
1 frame time
1 line time
Row 64 Row 1
LP
XSCL
XD0 to XD3
(14) (15) (16) (1) (15) (15)(16) (16)(1) (3) (1)(2)
r
t
t
WX
XSCL
t
DS
XD0 to XD3
t
WL
t
LD
LP
WF(B)
YD
Row 2
t
f
t
t
DH
t
LS
t
DHY
t
DF
CX
S1D13305 Series EPSON 17
Technical Manual
SPECIFICATIONS
Ta = –20 to 75°C
Signal Symbol Parameter
t
r
Rise time — 30 — 40 ns
f
Fall time — 30 — 40 ns
t
t
CX
XSCL
XD0 to
XD3
LP t
WF t
YD t
t
t
t
t
t
DHY
Shift clock cycle time 4t
WX
XSCL clock pulsewidth 2tC – 60 — 2tC – 60 — ns
DH
X data hold time 2tC – 50 — 2tC – 50 — ns
DS
X data setup time 2tC – 100 — 2tC – 105 — ns
LS
Latch data setup time 2tC – 50 — 2tC – 50 — ns
WL
LP pulsewidth 4tC – 80 — 4tC – 120 — ns
LD
LP delay time from XSCL 0 — 0 — ns
DF
Permitted WF delay — 50 — 50 ns
Y data hold time 2tC – 20 — 2tC – 20 — ns
DD
= 4.5 to 5.5V VDD = 2.7 to 4.5V
V
Min. Max. Min. Max
C
—4tC—ns
Unit Condition
CL =
100 pF
18 EPSON S1D13305 Series
Technical Manual
7. PACKAGE DIMENSIONS
Unit: mm
PACKAGE DIMENSIONS
7.1. S1D13305F00A
◊
QFP5-60 pin
0.4
25.6 ±
0.1
20.0 ±
Index
623
0.1
1.0 ±
0.35 ±
55
60
0.05
±
0.15
54
1
5
0.1
±
2.7
7.2. S1D13305F00B
◊
QFP6-60 pin
0.4
17.6 ±
0.2
36
35
0.4
0.1
30
±
±
29
19.6
14.0
24
0.1
46
60
0.1
0.05
±
0.15
1.5 ±
0 to 12°
0.3
2.8
14.0 ±
45
31
30
0.2
±
Index
14.0
16
115
0.35 ±
0.15
0.15
0.8 ±
±
2.7
0.8 ±
0.3
1.8
0.4
±
17.6
0 to 12°
S1D13305 Series EPSON 19
Technical Manual
INSTRUCTION SET
8. INSTRUCTION SET
8.1. The Command Set
Table 1. Command set
Code Read
Class Command Hex Command Description
RD WR A0 D7 D6 D5 D4 D3 D2 D1 D0
System
control
Display
control
Drawing
control
Memory
control
Notes:
SYSTEM SET 1010100000040
SLEEP IN 1010101001153Enter standby mode 0 8.2.2
DISP ON/OFF 1010101100D
SCROLL 1010100010044
CSRFORM 101010111015DSet cursor type 2 8.3.3
CGRAM ADR 101010111005C
CSRDIR 101010011
HDOT SCR 101010110105A
OVLAY 101010110115B
CSRW 1010100011046Set cursor address 2 8.4.1
CSRR 1010100011147Read cursor address 2 8.4.2
MWRITE 1010100001042Write to display memory — 8.5.1
MREAD 1010100001143
1. In general, the internal registers of the S1D13305 series are modified as each command parameter is input. However,
the microprocessor does not have to set all the parameters of a command and may send a new command before all parameters
have been input. The internal registers for the parameters that have been input will have been changed but the remaining
parameter registers are unchanged.
2-byte parameters (where two bytes are treated as 1 data item) are handled as follows:
a. CSRW, CSRR: Each byte is processed individually. The microprocessor may read or write just the low byte of the cursor
address.
b. SYSTEM SET, SCROLL, CGRAM ADR: Both parameter bytes are processed together. If the command is changed after
half of the parameter has been input, the single byte is ignored.
2. APL and APH are 2-byte parameters, but are treated as two 1-byte parameters.
CD CD
10tomovement
Initialize device and
display
58, Enable and disable dis59 play and display flashing
Set display start address
and display regions
Set start address of character generator RAM
4C
Set direction of cursor
4F
Set horizontal scroll
position
Set display overlay
format
Read from display
memory
Command
Parameters
No. of SecBytes tion
8 8.2.1
1 8.3.1
10 8.3.2
2 8.3.6
0 8.3.4
1 8.3.7
1 8.3.5
— 8.5.2
20 EPSON S1D13305 Series
Technical Manual
8.2. System Control Commands
8.2.1. SYSTEM SET
Initializes the device, sets the window sizes, and selects
the LCD interface format. Since this command sets the
basic operating parameters of the S1D13305 series, an
INSTRUCTION SET
incorrect SYSTEM SET command may cause other
commands to operate incorrectly.
D7 D6 D5 D4 D3 D2 D1 D0 A0 WR RD
C 01000000 1 0 1
P1 0 0 IV 1 W/S M2 M1 M0 0 0 1
P2 WF0000 FX 0 0 1
P3 0000 FY 0 0 1
P4 C/R 0 0 1
P5 TC/R 0 0 1
P6 L/F 0 0 1
P7 APL 0 0 1
P8 APH 0 0 1
LSBMSB
Figure 1. SYSTEM SET instruction
8.2.1.1. C
This control byte performs the following:
1. Resets the internal timing generator
2. Disables the display
3. Cancels sleep mode
Parameters following P1 are not needed if only canceling sleep mode.
Note that if the CG ROM address space overlaps the
display memory address space, that portion of the display
memory cannot be written to.
8.2.1.3. M1
Selects the memory configuration for user-definable characters. The CG RAM codes select one of the 64 codes
8.2.1.2. M0
Selects the internal or external character generator ROM.
The internal character generator ROM contains 160, 5 ×
7 pixel characters, as shown in figure 70. These characters are fixed at fabrication by the metallization mask.
The external character generator ROM, on the other
hand, can contain up to 256 user-defined characters.
M0 = 0: Internal CG ROM
M0 = 1: External CG ROM
S1D13305 Series EPSON 21
Technical Manual
shown in figure 46.
M1 = 0: No D6 correction.
The CG RAM1 and CG RAM2 address spaces are not
contiguous, the CG RAM1 address space is treated as
character generator RAM, and the CG RAM2 address
space is treated as character generator ROM.
M1 = 1: D6 correction.
The CG RAM1 and CG RAM2 address spaces are
contiguout and are both treated as character generator
RAM.
INSTRUCTION SET
8.2.1.4. M2
Selects the height of the character bitmaps. Characters
more than 16 pixels high can be displayed by creating a
bitmap for each portion of each character and using the
S1D13305 series graphics mode to reposition them.
M2 = 0: 8-pixel character height (2716 or equivalent
ROM)
M2 = 1: 16-pixel character height (2732 or equivalent
ROM)
EI
YD
Y driver
Figure 2. Single-panel display
8.2.1.5. W/S
Selects the LCD drive method.
W/S = 0: Single-panel drive
W/S = 1: Dual-panel drive
X driver X driver
LCD
YD
Y driver
EI
X driver X driver
Upper Panel
Lower Panel
X driver X driver
Figure 3. Above and below two-panel display
22 EPSON S1D13305 Series
Technical Manual
INSTRUCTION SET
EI
YD
Y driver
X driver X driver X driver X driver
Right PanelLeft Panel
Figure 4. Left-and-right two-panel display
Note
There are no Seiko Epson LCD units in the configuration shown in Figure 4.
Table 2. LCD parameters
Parameter
IV = 1 IV = 0 IV = 1 IV = 0
W/S = 0 W/S = 1
C/R C/R C/R C/R C/R
TC/R TC/R TC/R (See note 1.) TC/R TC/R
L/F L/F L/F L/F L/F
SL1 00H to L/F
SL2 00H to L/F
00H to L/F + 1
(See note 2.)
00H to L/F + 1
(See note 2.)
(L/F) / 2 (L/F) / 2
(L/F) / 2 (L/F) / 2
SAD1 First screen block First screen block First screen block First screen block
SAD2 Second screen block Second screen block Second screen block Second screen block
SAD3 Third screen block Third screen block Third screen block Third screen block
SAD4 Invalid Invalid Fourth screen block Fourth screen block
Cursor move-
ment range continuous movement over whole screen
Notes:
1. See table 26 for further details on setting the C/R and TC/R parameters when using the HDOT SCR command.
2. The value of SL when IV = 0 is equal to the value of SL when IV = 1, plus one.
Continuous movement over whole screen
Above-and-below configuration:
8.2.1.6. IV
Screen origin compensation for inverse display. IV is
usually set to 1.
The best way of displaying inverted characters is to
Exclusive-OR the text layer with the graphics back-
left of the screen are difficult to read as the character
origin is at the top-left of its bitmap and there are no
background pixels either above or to the left of these
characters.
ground layer. However, inverted characters at the top or
S1D13305 Series EPSON 23
Technical Manual
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