Epson S1C88650 User Manual

CMOS 8-BIT SINGLE CHIP MICROCOMPUTER

S1C88650

Technical Manual

S1C88650 Technical Hardware

NOTICE

No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no representation that this material is applicable to products requiring high level reliability, such as medical products. Moreover, no license to any intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright infringement of a third party. This material or portions thereof may contain technology or the subject relating to strategic products under the control of the Foreign Exchange and Foreign Trade Law of Japan and may require an export license from the Ministry of International Trade and Industry or other approval from another government agency.

Configuration of product number

Devices

S1 C 88104 F 0A01

Packing specifications

 00 : Besides tape & reel  0A : TCP BL 2 directions  0B : Tape & reel BACK  0C: TCP BR 2 directions  0D: TCP BT 2 directions  0E : TCP BD 2 directions  0F : Tape & reel FRONT  0G: TCP BT 4 directions  0H: TCP BD 4 directions  0J : TCP SL 2 directions  0K : TCP SR 2 directions  0L : Tape & reel LEFT  0M: TCP ST 2 directions  0N: TCP SD 2 directions  0P : TCP ST 4 directions  0Q: TCP SD 4 directions  0R: Tape & reel RIGHT  99 : Specs not fixed

Specification Package

 D: die form; F: QFP

Model number Model name

 C: microcomputer, digital products

Product classification

 S1: semiconductor

Development tools

S5U1 C 88348 D1 1

Packing specifications

 00: standard packing Version

 1: Version 1

Tool type

 Hx : ICE  Ex : EVA board  Px : Peripheral board  Wx: Flash ROM writer for the microcomputer  Xx : ROM writer peripheral board

 Cx : C compiler package  Ax : Assembler package  Dx : Utility tool by the model  Qx : Soft simulator

Corresponding model number

 88348: for S1C88348

Tool classification

 C: microcomputer use

Product classification

 S5U1: development tool for semiconductor products

CONTENTS

Contents

1 INTRODUCTION .............................................................................................. 1

1.1 Features .............................................................................................................................1

1.2 Block Diagram ...................................................................................................................2

1.3 Pins ....................................................................................................................................3

1.3.1 Pin layout diagram................................................................................................................... 3

1.3.2 Pin description .........................................................................................................................4

1.4 Mask Option.......................................................................................................................5

2 POWER SUPPLY............................................................................................... 7

2.1 Operating Voltage..............................................................................................................7

2.2 Internal Power Supply Circuit ...........................................................................................7

3 CPU AND BUS CONFIGURATION ................................................................ 8

3.1 CPU ...................................................................................................................................8

3.2 Internal Memory ................................................................................................................8

3.2.1 Program ROM.......................................................................................................................... 8

3.2.2 RAM.......................................................................................................................................... 8

3.2.3 I/O memory............................................................................................................................... 8

3.2.4 Display memory........................................................................................................................8

3.2.5 Kanji font ROM ........................................................................................................................8

3.3 Exception Processing Vectors ...........................................................................................9

3.4 CC (Customized Condition Flag) ......................................................................................9

3.5 Chip Mode..........................................................................................................................9

3.5.1 MCU mode and MPU mode .....................................................................................................9

3.5.2 Bus mode .................................................................................................................................10

3.5.3 CPU mode ...............................................................................................................................11

3.6 External Bus......................................................................................................................11

3.6.1 Data bus ..................................................................................................................................11

3.6.2 Address bus .............................................................................................................................12

3.6.3 Read (RD)/write (WR) signals.................................................................................................12

3.6.4 Chip enable (CE) signal ..........................................................................................................12

3.6.5 WAIT control ........................................................................................................................... 13

3.6.6 Bus authority release state ...................................................................................................... 14

4 INITIAL RESET ............................................................................................... 15

4.1 Initial Reset Factors..........................................................................................................15

4.1.1 RESET terminal....................................................................................................................... 15

4.1.2 Simultaneous LOW level input at input port terminals K00–K03........................................... 16

4.1.3 Initial reset sequence............................................................................................................... 16

4.2 Initial Settings After Initial Reset......................................................................................17

5 PERIPHERAL CIRCUITS AND THEIR OPERATION................................ 18

5.1 I/O Memory Map ..............................................................................................................18

5.2 System Controller and Bus Control ..................................................................................34

5.2.1 Bus mode and CPU mode settings ..........................................................................................34

5.2.2 Address decoder (CE output) settings .....................................................................................34

5.2.3 WAIT state settings.................................................................................................................. 35

5.2.4 Setting the bus authority release request signal......................................................................35

5.2.5 Stack page setting.................................................................................................................... 35

5.2.6 Control of system controller.................................................................................................... 36

5.2.7 Programming notes ................................................................................................................. 38

S1C88650 TECHNICAL MANUAL EPSON i

CONTENTS

5.3 Watchdog Timer................................................................................................................39

5.3.1 Configuration of watchdog timer ............................................................................................ 39

5.3.2 Interrupt function ....................................................................................................................39

5.3.3 Control of watchdog timer ......................................................................................................40

5.3.4 Programming notes ................................................................................................................. 40

5.4 Oscillation Circuits...........................................................................................................41

5.4.1 Configuration of oscillation circuits .......................................................................................41

5.4.2 Mask option ............................................................................................................................. 41

5.4.3 OSC1 oscillation circuit .......................................................................................................... 41

5.4.4 OSC3 oscillation circuit .......................................................................................................... 42

5.4.5 Switching the CPU clocks .......................................................................................................42

5.4.6 Control of oscillation circuit ................................................................................................... 43

5.4.7 Programming notes ................................................................................................................. 43

5.5 Input Ports (K ports).........................................................................................................44

5.5.1 Configuration of input ports....................................................................................................44

5.5.2 Mask option ............................................................................................................................. 44

5.5.3 Pull-up control ........................................................................................................................45

5.5.4 Interrupt function and input comparison register................................................................... 45

5.5.5 Control of input ports .............................................................................................................. 47

5.5.6 Programming notes ................................................................................................................. 50

5.6 Output Ports (R ports) ......................................................................................................51

5.6.1 Configuration of output ports..................................................................................................51

5.6.2 High impedance control .......................................................................................................... 51

5.6.3 DC output ................................................................................................................................ 51

5.6.4 Control of output ports ............................................................................................................52

5.7 I/O Ports (P ports) ............................................................................................................54

5.7.1 Configuration of I/O ports.......................................................................................................54

5.7.2 Mask option ............................................................................................................................. 54

5.7.3 I/O control registers and I/O mode ......................................................................................... 54

5.7.4 Pull-up control ........................................................................................................................55

5.7.5 Special output ..........................................................................................................................55

5.7.6 Control of I/O ports................................................................................................................. 57

5.7.7 Programming notes ................................................................................................................. 60

5.8 Serial Interface .................................................................................................................61

5.8.1 Configuration of serial interface............................................................................................. 61

5.8.2 Switching of terminal functions............................................................................................... 61

5.8.3 Transfer modes ........................................................................................................................62

5.8.4 Clock source ............................................................................................................................63

5.8.5 Transmit-receive control ......................................................................................................... 64

5.8.6 Operation of clock synchronous transfer ................................................................................ 65

5.8.7 Operation of asynchronous transfer .......................................................................................69

5.8.8 Interrupt function ....................................................................................................................73

5.8.9 Control of serial interface ....................................................................................................... 75

5.8.10 Programming notes ............................................................................................................... 80

5.9 Clock Timer.......................................................................................................................81

5.9.1 Configuration of clock timer ...................................................................................................81

5.9.2 Interrupt function ....................................................................................................................81

5.9.3 Control of clock timer .............................................................................................................83

5.9.4 Programming notes ................................................................................................................. 85

5.10 Programmable Timer........................................................................................................86

5.10.1 Configuration of programmable timer.................................................................................. 86

5.10.2 Operation mode..................................................................................................................... 87

5.10.3 Setting of input clock ............................................................................................................. 89

5.10.4 Operation and control of timer .............................................................................................89

5.10.5 Interrupt function ..................................................................................................................91

5.10.6 Setting of TOUT output .........................................................................................................93

5.10.7 Transfer rate setting of serial interface.................................................................................94

ii EPSON S1C88650 TECHNICAL MANUAL

CONTENTS

5.10.8 Setting frame frequency for LCD driver ...............................................................................94

5.10.9 Control of programmable timer ............................................................................................95

5.10.10 Programming notes ............................................................................................................ 107

5.11 LCD Driver ......................................................................................................................108

5.11.1 Configuration of LCD driver................................................................................................108

5.11.2 LCD power supply................................................................................................................ 108

5.11.3 Frame frequency .................................................................................................................. 109

5.11.4 Switching drive duty ............................................................................................................. 109

5.11.5 Display memory....................................................................................................................113

5.11.6 Display control ..................................................................................................................... 120

5.11.7 Control of LCD driver.......................................................................................................... 121

5.11.8 Programming notes .............................................................................................................. 123

5.12 Supply Voltage Detection (SVD) Circuit .........................................................................124

5.12.1 Configuration of SVD circuit ...............................................................................................124

5.12.2 SVD operation ...................................................................................................................... 124

5.12.3 Control of SVD circuit..........................................................................................................125

5.12.4 Programming notes .............................................................................................................. 125

5.13 Heavy Load Protection Function.....................................................................................126

5.13.1 Outline of heavy load protection function............................................................................ 126

5.13.2 Control of heavy load protection function ...........................................................................126

5.13.3 Programming note................................................................................................................126

5.14 Interrupt and Standby Status ...........................................................................................127

5.14.1 Interrupt generation conditions ...........................................................................................127

5.14.2 Interrupt factor flag.............................................................................................................. 129

5.14.3 Interrupt enable register ......................................................................................................130

5.14.4 Interrupt priority register and interrupt priority level......................................................... 131

5.14.5 Exception processing vectors ............................................................................................... 132

5.14.6 Control of interrupt ..............................................................................................................133

5.14.7 Programming notes .............................................................................................................. 135

6 SUMMARY OF NOTES .................................................................................. 136

6.1 Notes for Low Current Consumption...............................................................................136

6.2 Precautions on Mounting.................................................................................................137

7 BASIC EXTERNAL WIRING DIAGRAM..................................................... 139

8 ELECTRICAL CHARACTERISTICS............................................................ 140

8.1 Absolute Maximum Rating...............................................................................................140

8.2 Recommended Operating Conditions ..............................................................................140

8.3 DC Characteristics ..........................................................................................................141

8.4 Analog Circuit Characteristics ........................................................................................142

8.5 Power Current Consumption ...........................................................................................143

8.6 AC Characteristics...........................................................................................................144

8.7 Oscillation Characteristics ..............................................................................................149

8.8 Characteristics Curves (reference value) ........................................................................150

9 PACKAGE ........................................................................................................ 159

9.1 Plastic Package................................................................................................................159

9.2 Ceramic Package for Test Samples .................................................................................160

10 PAD LAYOUT .................................................................................................. 161

10.1 Diagram of Pad Layout ...................................................................................................161

10.2 Pad Coordinates ..............................................................................................................162

S1C88650 TECHNICAL MANUAL EPSON iii

CONTENTS

APPENDIX A S5U1C88000P1&S5U1C88649P2 MANUAL

(Peripheral Circuit Board for S1C88650) ...................................... 163

A.1 Names and Functions of Each Part .................................................................................163

A.2 Precautions ......................................................................................................................165

A.2.1 Precaution for operation .......................................................................................................165

A.2.2 Differences from actual IC ....................................................................................................165

A.3 Connecting to the Target System .....................................................................................168

A.4 Product Specifications .....................................................................................................171

APPENDIX B USING KANJI FONT ..................................................................... 172

iv EPSON S1C88650 TECHNICAL MANUAL

1 INTRODUCTION

The S1C88650 is an 8-bit microcomputer for portable equipment with an LCD display that has a built-in LCD controller/driver and a character generator (kanji) ROM. This microcomputer features low-voltage (1.8 V) and high-speed (8.2 MHz) operations as well as low-current consumption (2.5 µA during standby). The LCD controller/driver contains an LCD drive power supply circuit and can drive an maximum of 126 × 32-dot LCD panel in low-power consumption. The S1C88650 has a built-in 11 × 12-dot kanji font

other characters and user-defined characters, this makes it possible to display kanji characters without any external kanji font ROM (refer to Appendix B, "USING KANJI FONT"). This 8-bit CPU has up to 16MB accessible address space allowing easy implementation of a large data processing application. The S1C88650 is suitable for display modules, portable CD/MD, solid audio players, PDA, data bank and other applications that required an exclusive LCD driver in conventional systems.

ROM that contains JIS level-1 and level-2 kanji sets,

1.1 Features

Table 1.1.1 lists the features of the S1C88650.

Table 1.1.1 Main features

Core CPU Main

(OSC3)

Sub Instruction set Min. instruction execution time Internal ROM capacity

Internal RAM capacity Bus line

Input port Output port

I/O port

Serial interface Timer

LCD driver

Watchdog timer Supply voltage detection (SVD) circuit Interrupt

Supply voltage Current consumption

Supply form

S1C88650 TECHNICAL MANUAL EPSON 1

oscillation circuit

(OSC1)

oscillation circuit

∗ The current consumption with LCD ON listed above is the value under the conditions of LCDCx = "11 (all on)", LCx = "0FH" and

"No panel load". Current consumption increases according to the display contents and panel load.

S1C88 (MODEL3) CMOS 8-bit core CPU Crystal oscillation circuit/ceramic oscillation circuit 8.2 MHz (Max.), or CR oscillation circuit 2.2 MHz (Max.) Crystal oscillation circuit 32.768 kHz (Typ.), or CR oscillation circuit 200 kHz (Max.) 608 types (usable for multiplication and division instructions)

0.244 µsec/8.2 MHz (2 clock) 48K bytes/program ROM 896K bytes/kanji font ROM (can be used for a program and data ROM when no font data is stored.) 8K bytes/RAM 768 bytes/display memory Address bus: Data bus: CE signal: WR signal: RD signal: 8 bits (4 bits can be used as the source clock inputs for PWM timers and 1 bit as a bus request signal input) 0–3 bits (when the external bus is used) 26 bits (when the external bus is not used) 8 bits (when the external bus is used) 16 bits (when the external bus is not used) 1 ch (optional clock synchronous system or asynchronous system) Programmable timer: Clock timer: Dot matrix type (supports 16 × 16/5 × 8 or 12 × 12 dot font) 126 segments × 32, 16 or 8 commons (1/5 bias) Built-in LCD power supply circuit (booster type, 5 potentials) Built-in (1–8 second cycles) 13 value programmable (1.8–2.7 V)

External interrupt: Internal interrupt:

1.8–3.6 V SLEEP mode: 1 µA(Typ.) HALT mode: 2.5 µA(Typ.) 32 kHz crystal, LCD OFF

Run state: 9 µA(Typ.) 32 kHz crystal, LCD OFF

QFP22-256pin or chip

20 bits (also usable as general output ports when not used for the bus) 8 bits (also usable as general I/O ports when not used for the bus) 3 bits 1 bit

(also usable as general output ports when not used for the bus)

1 bit

(1 bit can be configured for the bus acknowledge signal output)

(shard with serial interface, FOUT and TOUT terminals)

16 bits (8 bits × 2) 4 ch (with PWM function) 1 ch

Input interrupt Timer interrupt Serial interface interrupt

10 µA(Typ.) 32 kHz CR, LCD OFF

7.6 µA(Typ.) 32 kHz crystal, LCD ON*, V

15 µA(Typ.) 32 kHz CR, LCD OFF 1700 µA(Typ.) 8 MHz ceramic, LCD OFF 600 µA(Typ.) 2 MHz CR, LCD OFF 14 µA(Typ.) 32 kHz crystal, LCD ON*, V 19 µA(Typ.) 32 kHz crystal, LCD ON*, V 14 µA(Typ.) 32 kHz crystal, SVD ON

1 system (8 types) 2 systems (16 types) 1 system (3 types)

DD = 2.5–3.6 V

DD = 2.5–3.6 V DD = 1.8–2.5 V, Power voltage booster ON

1 INTRODUCTION

1.2 Block Diagram

Core CPU S1C88

OSC1, 2 OSC3, 4

MCU/MPU BREQ (K03) BACK (R33)

RESET

TEST

EXCL0–EXCL3 (K04–K07)

TOUT0–TOUT3 (P14, P15)

TOUT2/TOUT3 (P17)

V V

VC1–V

CA–CG

Oscillator

System Controller Input Port

Reset/Test

Watchdog Timer

Programmable Timer

/Event Counter

Clock Timer

DD SS

D1 D2 C5

Power Generator

RAM

8K bytes

Interrupt Controller

I/O Port

Serial Interface

External

Memory Interface

Output Port

LCD Driver

Supply Voltage Detector

ROM

48K bytes+896K bytes

K00–K02 K03 (BREQ) K04–K07

P10 (SIN) P11 (SOUT) P12 (SCLK) P13 (SRDY) P14 (TOUT0/TOUT1) P15 (TOUT2/TOUT3) P16 (FOUT) P17 (TOUT2/TOUT3) P00–P07 (D0–D7) R00–R07, R10–R17, R20–R23

(A0–A7, A8–A15, A16–A19) R24, R25 (RD, WR)

R30–R32 (CE0–CE2) R33 (BACK)

SEG0–SEG125

COM0–COM31

Fig. 1.2.1 S1C88650 block diagram

2 EPSON S1C88650 TECHNICAL MANUAL

1 INTRODUCTION

1.3 Pins

1.3.1 Pin layout diagram

QFP22-256pin

193

INDEX

256

Pin No. Pin name

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52

N.C. N.C.

TEST SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 SEG57 SEG58 SEG59 SEG60 SEG61 SEG62 SEG63 SEG64 SEG65 SEG66 SEG67 SEG68 SEG69 SEG70 SEG71 SEG72 SEG73 SEG74 SEG75 SEG76 SEG77 SEG78 SEG79 SEG80 SEG81 SEG82 SEG83 SEG84 SEG85 SEG86 SEG87

Pin No. Pin name

53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98

99 100 101 102 103 104

SEG88 SEG89 SEG90 SEG91 SEG92 SEG93 SEG94 SEG95 SEG96

N.C. N.C. N.C. N.C. N.C.

V SEG97 SEG98 SEG99

SEG100 SEG101 SEG102 SEG103 SEG104 SEG105 SEG106 SEG107 SEG108 SEG109 SEG110 SEG111 SEG112 SEG113 SEG114 SEG115 SEG116 SEG117 SEG118 SEG119 SEG120 SEG121 SEG122 SEG123 SEG124 SEG125 COM31 COM30 COM29 COM28 COM27 COM26 COM25 COM24

Pin No. Pin name

105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156

COM23 COM22 COM21 COM20 COM19 COM18 COM17 COM16

CG CF CE CD CC CB CA

N.C. N.C. N.C. N.C. N.C. V

OSC3 OSC4

OSC1 OSC2 TEST

RESET

MCU/MPU K07/EXCL3 K06/EXCL2 K05/EXCL1 K04/EXCL0

K03/BREQ

K02 K01 K00

P17/TOUT2/TOUT3

P16/FOUT P15/TOUT2/TOUT3 P14/TOUT0/TOUT1

P13/SRDY P12/SCLK P11/SOUT

P10/SIN

Fig. 1.3.1.1 S1C88650 pin layout

S1C88650 TECHNICAL MANUAL EPSON 3

129192

128

641

Pin No. Pin name

157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208

P07/D7 P06/D6 P05/D5 P04/D4 P03/D3 P02/D2 P01/D1 P00/D0 R00/A0 R01/A1 R02/A2 R03/A3 R04/A4 R05/A5 R06/A6 R07/A7 R10/A8

R11/A9 R12/A10 R13/A11 R14/A12 R15/A13 R16/A14 R17/A15 R20/A16 R21/A17 R22/A18 R23/A19

R24/RD R25/WR R30/CE0 R31/CE1

N.C. N.C. N.C. N.C. N.C.

R32/CE2

R33/BACK

COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9

COM10

Pin No. Pin name

209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256

– – – –

COM11 COM12 COM13 COM14 COM15

SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8

SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38

V N.C. N.C. N.C.

– – – –

1 INTRODUCTION

1.3.2 Pin description

Table 1.3.2.1 S1C88650 pin description

Pin name In/Out Function

VSS VD1 VD2 VC1–VC5 CA–CG OSC1 OSC2 OSC3 OSC4 MCU/MPU K00–K02 K03/BREQ K04/EXCL0 K05/EXCL1 K06/EXCL2 K07/EXCL3 R00–R07/A0–A7 R10–R17/A8–A15 R20–R23/A16–A19 R24/RD R25/WR R30–R32/CE0–CE2 R33 (BACK) P00–P07/D0–D7 P10/SIN P11/SOUT P12/SCLK P13/SRDY P14/TOUT0/TOUT1

P15/TOUT2/TOUT3

P16/FOUT P17/TOUT2/TOUT3

COM0–COM31 SEG0–SEG125

RESET TEST TEST

Pin No.

131, 189

67, 134, 195, 253

135

113 125–121 120–114

136

137

132

133

140 148–146

145

144

143

142

141 165–172 173–180 181–184

185

186

187, 188, 196

197 164–157

156

155

154

153

152

151

150

149

198–213, 112–97

214–252, 4–61,

68–96

139

138

–

Power supply (+) terminal

–

Power supply (GND) terminal

–

Internal logic system and oscillation system voltage regulator output terminals

–

LCD circuit power voltage booster output terminal

–

LCD drive voltage output terminals

–

LCD and power voltage booster capacitor connection terminals

OSC1 oscillation input terminal (select crystal/CR oscillation by mask option)

OSC1 oscillation output terminal

OSC3 oscillation input terminal (select crystal/ceramic/CR oscillation by mask option)

OSC3 oscillation output terminal

MCU/MPU mode setup terminal

Input terminals (K00–K02)

Input terminal (K03) or bus request signal input terminal (BREQ)

Input terminal (K04) or programmable timer external clock input terminal (EXCL0)

Input terminal (K05) or programmable timer external clock input terminal (EXCL1)

Input terminal (K06) or programmable timer external clock input terminal (EXCL2)

Input terminal (K07) or programmable timer external clock input terminal (EXCL3)

Output terminals (R00–R07) or address bus (A0–A7)

Output terminals (R10–R17) or address bus (A8–A15)

Output terminals (R20–R23) or address bus (A16–A19)

Output terminal (R24) or read signal output terminal (RD)

Output terminal (R25) or write signal output terminal (WR)

Output terminals (R30–R32) or chip enable signal output terminals (CE0–CE2)

Output terminal (R33) or bus acknowledge signal output terminal (BACK)

I/O

I/O terminals (P00–P07) or data bus (D0–D7)

I/O

I/O terminal (P10) or serial I/F data input terminal (SIN)

I/O

I/O terminal (P11) or serial I/F data output terminal (SOUT)

I/O

I/O terminal (P12) or serial I/F clock I/O terminal (SCLK)

I/O

I/O terminal (P13) or serial I/F ready signal output terminal (SRDY)

I/O

I/O terminal (P14) or programmable timer underflow signal output terminal (TOUT0/TOUT1)

I/O

I/O terminal (P15) or programmable timer underflow signal output terminal (TOUT2/TOUT3)

I/O

I/O terminal (P16) or clock output terminal (FOUT)

I/O

I/O terminal (P17) or programmable timer underflow inverted signal output terminal (TOUT2/TOUT3)

LCD common output terminals

LCD segment output terminals

Initial reset input terminal

Test input terminal

–

Test terminal (open during normal operation)

4 EPSON S1C88650 TECHNICAL MANUAL

1 INTRODUCTION

1.4 Mask Option

Mask options shown below are provided for the S1C88650. Several hardware specifications are prepared in each mask option, and one of them can be selected according to the application. Multiple specifications are available in each option item as indicated in the

Select the specifications that meet the target system and check the appropriate box. The option selection is done interactively on the screen during function option generator winfog execution, using this option list as reference. Mask pattern of the IC is finally generated based on the data created by the winfog. Refer to the "S5U1C88000C Manual II" for details on the winfog.

Option List.

PERIPHERAL CIRCUIT BOARD option list

The following shows the options for configuring the Peripheral Circuit Board (S5U1C88000P1 with S5U1C88649P2) installed in the ICE (S5U1C88000H5). The selections do not affect the IC's mask option.

A OSC1 SYSTEM CLOCK

■■ 1. Internal Clock

■■ 2. User Clock

B OSC3 SYSTEM CLOCK

■■ 1. Internal Clock

■■ 2. User Clock

When User Clock is selected, input a clock to the OSC1 terminal. When Internal Clock is selected, the clock frequency is changed according to the oscillation circuit selected by the IC's mask option.

When User Clock is selected, input a clock to the OSC3 terminal. When Internal Clock is selected, the clock frequency is changed according to the oscillation circuit

selected by the IC's mask option.

S1C88650 mask option list

The following shows the option list for generating the IC's mask pattern. Note that the Peripheral Circuit Board installed in the ICE does not support some options.

1 OSC1 SYSTEM CLOCK

■■ 1. Crystal

■■ 2. CR

2 OSC3 SYSTEM CLOCK

■■ 1. Crystal

■■ 2. Ceramic

■■ 3. CR

3 MULTIPLE KEY ENTRY RESET

• Combination ..■■ 1. Not Use

■■ 2. Use K00, K01

■■ 3. Use K00, K01, K02

■■ 4. Use K00, K01, K02, K03

4 INPUT PORT PULL UP RESISTOR

• K00...................■■ 1. With Resistor ■■ 2. Gate Direct

• K01...................■■ 1. With Resistor ■■ 2. Gate Direct

• K02...................■■ 1. With Resistor ■■ 2. Gate Direct

• K03...................■■ 1. With Resistor ■■ 2. Gate Direct

• K04...................■■ 1. With Resistor ■■ 2. Gate Direct

• K05...................■■ 1. With Resistor ■■ 2. Gate Direct

• K06...................■■ 1. With Resistor ■■ 2. Gate Direct

• K07...................■■ 1. With Resistor ■■ 2. Gate Direct

• MCU/MPU .... ■■ 1. With Resistor ■■ 2. Gate Direct

• RESET .............■■ 1. With Resistor ■■ 2. Gate Direct

______

________

The specification of the OSC1 oscillation circuit can be selected from among two types: "Crystal oscillation" and "CR oscillation". Refer to Section 5.4.3, "OSC1 oscillation circuit", for details.

The specification of the OSC3 oscillation circuit can be selected from among three types: "Crystal oscillation", "Ceramic oscillation" and "CR oscillation". Refer to Section 5.4.4, "OSC3 oscillation circuit", for details.

This mask option can select whether the multiple key entry reset function is used or not. When the function is used, a combination of the input ports (K00–K03), which are connected to the keys, can be selected. Refer to Section 4.1.2, "Simultaneous LOW level input at input port terminals K00–K03", for details.

This mask option can select whether the pull-up resistor for the input (K) port terminal is used or not. It is possible to select for each bit of the input ports. Refer to Section 5.5, "Input Ports (K ports)", for details. Furthermore, a pull-up option is also provided for the

______ ________

MCU/MPU and RESET terminals.

S1C88650 TECHNICAL MANUAL EPSON 5

1 INTRODUCTION

5 I/O PORT PULL UP RESISTOR

• P00 ......... ■■ 1. With Resistor ■■ 2. Gate Direct

• P01 ......... ■■ 1. With Resistor ■■ 2. Gate Direct

• P02 ......... ■■ 1. With Resistor ■■ 2. Gate Direct

• P03 ......... ■■ 1. With Resistor ■■ 2. Gate Direct

• P04 ......... ■■ 1. With Resistor ■■ 2. Gate Direct

• P05 ......... ■■ 1. With Resistor ■■ 2. Gate Direct

• P06 ......... ■■ 1. With Resistor ■■ 2. Gate Direct

• P07 ......... ■■ 1. With Resistor ■■ 2. Gate Direct

• P10 ......... ■■ 1. With Resistor ■■ 2. Gate Direct

• P11 ......... ■■ 1. With Resistor ■■ 2. Gate Direct

• P12 ......... ■■ 1. With Resistor ■■ 2. Gate Direct

• P13 ......... ■■ 1. With Resistor ■■ 2. Gate Direct

• P14 ......... ■■ 1. With Resistor ■■ 2. Gate Direct

• P15 ......... ■■ 1. With Resistor ■■ 2. Gate Direct

• P16 ......... ■■ 1. With Resistor ■■ 2. Gate Direct

• P17 ......... ■■ 1. With Resistor ■■ 2. Gate Direct

6 INPUT PORT INPUT I/F LEVEL

• K00......... ■■ 1. CMOS Level ■■ 2. CMOS Schmitt

• K01......... ■■ 1. CMOS Level ■■ 2. CMOS Schmitt

• K02......... ■■ 1. CMOS Level ■■ 2. CMOS Schmitt

• K03......... ■■ 1. CMOS Level ■■ 2. CMOS Schmitt

• K04......... ■■ 1. CMOS Level ■■ 2. CMOS Schmitt

• K05......... ■■ 1. CMOS Level ■■ 2. CMOS Schmitt

• K06......... ■■ 1. CMOS Level ■■ 2. CMOS Schmitt

• K07......... ■■ 1. CMOS Level ■■ 2. CMOS Schmitt

This mask option can select whether the pull-up resistor for the I/O port terminal (it works during input mode) is used or not. It is possible to select for each bit of the I/O ports. Refer to Section 5.7, "I/O Ports (P ports)", for details.

This mask option can select the interface level of the input (K) port from either the CMOS level or CMOS Schmitt level. It is possible to select for each bit of the input ports. Refer to Section 5.5, "Input Ports (K ports)", for details. The input port on the ICE (with the Peripheral Circuit Board installed) is fixed to the CMOS level interface regardless of this option selection.

7 I/O PORT INPUT I/F LEVEL

• P10 ......... ■■ 1. CMOS Level ■■ 2. CMOS Schmitt

• P11 ......... ■■ 1. CMOS Level ■■ 2. CMOS Schmitt

• P12 ......... ■■ 1. CMOS Level ■■ 2. CMOS Schmitt

• P13 ......... ■■ 1. CMOS Level ■■ 2. CMOS Schmitt

• P14 ......... ■■ 1. CMOS Level ■■ 2. CMOS Schmitt

• P15 ......... ■■ 1. CMOS Level ■■ 2. CMOS Schmitt

• P16 ......... ■■ 1. CMOS Level ■■ 2. CMOS Schmitt

• P17 ......... ■■ 1. CMOS Level ■■ 2. CMOS Schmitt

WATCHDOG TIMER NMI GENERATION CYCLE

■■ 1. 32768/fOSC1

■■ 2. 65536/fOSC1

■■ 3. 131072/fOSC1

■■ 4. 262144/fOSC1

______

(0.75–1-sec cycle when f

OSC1

= 32 kHz)

(1.5–2-sec cycle when fOSC1 = 32 kHz)

(3–4-sec cycle when fOSC1 = 32 kHz)

(6–8-sec cycle when fOSC1 = 32 kHz)

This mask option can select the interface level of the I/O (P) port from either the CMOS level or CMOS Schmitt level. It is possible to select for each bit of the I/O ports. Refer to Section 5.7, "I/O Ports (P ports)", for details. The input port on the ICE (with the Peripheral Circuit Board installed) is fixed to the CMOS level interface regardless of this option selection.

This mask option can select the NMI generation cycle of

______

the watchdog timer. Refer to Section 5.3.1, "Configuration of watchdog timer", for details.

6 EPSON S1C88650 TECHNICAL MANUAL

2POWER SUPPLY

In this section, we will explain the operating voltage and the configuration of the internal power

supply circuit of the S1C88650.

2 POWER SUPPLY

2.1 Operating V oltage

The S1C88650 operating power voltage is as follows:

1.8 V to 3.6 V

2.2 Internal Power Supply Circuit

The S1C88650 incorporates the power supply circuit shown in Figure 2.2.1. When voltage within the range described above is supplied to VDD (+) and VSS (GND), all the voltages needed for the internal circuit are generated internally in the IC.

Roughly speaking, the power supply circuit is divided into three sections.

Table 2.2.1 Power supply circuit

Circuit

Oscillation circuits, Internal circuits LCD system voltage regulator LCD driver

The internal logic voltage regulator generates the operating voltage <VD1> for driving the internal logic circuits and the oscillation circuit. The VD1 voltage value is fixed at 1.8 V (Typ.).

The power voltage booster generates the operating voltage <V

D2> for the LCD system voltage

regulator.

External power supply

Power supply circuit

Internal logic voltage regulator Power voltage booster LCD system voltage regulator

VDD

VD1

Output voltage

VD1

VDD or VD2

VC1–VC5

Internal logic

voltage regulator

Either <V

DD> or <VD2> can be selected as the

power source for the LCD system voltage regulator according to the <VDD> power supply voltage level.

Table 2.2.2 Power source for LCD system

voltage regulator

Supply voltage

VDD

1.8–2.5 V

2.5–3.6 V

Power source for

LCD system voltage regulator

VD2 VDD

The VD2 voltage is about double the VDD voltage level. Refer to Chapter 8, "ELECTRICAL CHARACTERISTICS", for details.

The LCD system voltage regulator generates the 1/ 5-bias LCD drive voltages <VC1>, <VC2>, <VC3>, <VC4> and <VC5>. See Chapter 8, "ELECTRICAL CHARACTERISTICS" for the voltage values.

In the S1C88650, the LCD drive voltage is supplied to the built-in LCD driver which drives the LCD panel connected to the SEG and COM terminals.

Notes: • Under no circumstances should VD1,VD2,

VC1, VC2, VC3, VC4 and VC5, terminal output be used to drive external circuit.

• If VDD is used as the power source for the LCD system voltage regulator when VDD is

2.5 V or less, the VC1 to VC5 voltages cannot be generated within specifications.

OSC1, OSC2 OSC3, OSC4

VD1

Oscillation circuit

Internal circuit

VD2

V VC2 VC3 VC4 VC5

CC CD

CA CB

Power

voltage

booster

VD2

LCD system

voltage regulator

VC1–VC5

LCD driver

COM0–COM31 SEG0–SEG125

Fig. 2.2.1 Configuration of power supply circuit

S1C88650 TECHNICAL MANUAL EPSON 7

3 CPU AND BUS CONFIGURATION

In this section, we will explain the CPU, operating mode and bus configuration.

3.1 CPU

The S1C88650 utilize the S1C88 8-bit core CPU whose resistor configuration, command set, etc. are virtually identical to other units in the family of processors incorporating the S1C88.

See the "S1C88 Core CPU Manual" for the S1C88. Specifically, the S1C88650 employ the Model 3

S1C88 CPU which has a maximum address space of 1M bytes × 3.

3.2 Internal Memory

The S1C88650 is equipped with internal ROM and RAM as shown in Figure 3.2.1. Small scale applications can be handled by one chip. It is also possible to utilize internal memory in combination with external memory. Furthermore, internal ROM can be disconnected from the bus and the resulting space released for external applications.

0EFFFFH

Kanji font ROM

010000H 00FFFFH 00FF00H 00FD7FH 00F800H 00F7FFH 00D800H 00D7FFH

: 00C000H 00BFFFH

000000H

Fig. 3.2.1 Internal memory map

3.2.1 Program ROM

The S1C88650 has a built-in 48K-byte program ROM. The ROM is allocated to 000000H–00BFFFH. This ROM areas shown above can be released to external memory depending on the setting of the

_______

MCU/MPU terminal. (See "3.5 Chip Mode".)

(896K bytes)

I/O memory

Display memory

RAM (8K bytes)

Unused

area

ROM

(48K bytes)

3.2.2 RAM

The internal RAM capacity is 8K bytes and is allocated to 00D800H–00F7FFH. Even when external memory which overlaps the internal RAM area is expanded, the RAM area is not released to external memory. Access to this area is via internal RAM.

3.2.3 I/O memory

A memory mapped I/O method is employed in the S1C88650 for interfacing with internal peripheral circuit. Peripheral circuit control bits and data register are arranged in data memory space. Control and data exchange are conducted via normal memory access. I/O memory is arranged in page 0: 00FF00H–00FFFFH area. See Section 5.1, "I/O Memory Map", for details of the I/O memory. Even when external memory which overlaps the I/ O memory area is expanded, the I/O memory area is not released to external memory. Access to this area is via I/O memory.

3.2.4 Display memory

The S1C88650 is equipped with an internal display memory which stores a display data for LCD driver. Display memory is arranged in page 0: 00Fx00H– 00Fx7FH (x = 8–DH) in the data memory area. See Section 5.11, "LCD Driver", for details of the display memory. Like the I/O memory, display memory cannot be released to external memory.

3.2.5 Kanji font ROM

The S1C88650 has a built-in kanji font ROM that can be used to store JIS level-1 and level-2 kanji sets, alphanumeric characters and music shift-JIS characters. The kanji font ROM capacity is 896K bytes and is allocated to 010000H–0EFFFFH. When the kanji font is not used the remaining area or the entire area can be used for a program and data storage area (see the "S5U1C88xxxRx Manual" for use of font data). This ROM areas shown above can be released to external memory depending on the setting of the

_______

MCU/MPU terminal. (See "3.5 Chip Mode".)

8 EPSON S1C88650 TECHNICAL MANUAL

3 CPU AND BUS CONFIGURATION

3.3 Exception Processing Vectors

000000H–00004BH in the program area of the S1C88650 is assigned as exception processing vectors. Furthermore, from 00004EH to 0000FFH, software interrupt vectors are assignable to any two bytes which begin with an even address. Table 3.3.1 lists the vector addresses and the exception processing factors to which they correspond.

Table 3.3.1 Exception processing vector table

Vector

address

000000H 000002H 000004H 000006H

000008H 00000AH 00000CH

00000EH

000010H

000012H

000014H

000016H

000018H 00001AH 00001CH

00001EH

000020H

000022H

000024H

000026H

000028H 00002AH 00002CH

00002EH

000030H

000032H

000034H

000036H

000038H 00003AH 00003CH

00003EH

000040H

000042H

000044H

000046H

000048H 00004AH 00004CH

00004EH

0000FEH

Exception processing factor

Reset Zero division Watchdog timer (NMI) K07 input interrupt K06 input interrupt K05 input interrupt K04 input interrupt K03 input interrupt K02 input interrupt K01 input interrupt K00 input interrupt PTM 0 underflow interrupt PTM 0 compare match interrupt PTM 1 underflow interrupt PTM 1 compare match interrupt PTM 2 underflow interrupt PTM 2 compare match interrupt PTM 3 underflow interrupt PTM 3 compare match interrupt System reserved (cannot be used) Serial I/F error interrupt Serial I/F receiving complete interrupt Serial I/F transmitting complete interrupt System reserved (cannot be used) System reserved (cannot be used) System reserved (cannot be used) Clock timer 32 Hz interrupt Clock timer 8 Hz interrupt Clock timer 2 Hz interrupt Clock timer 1 Hz interrupt PTM 4 underflow interrupt PTM 4 compare match interrupt PTM 5 underflow interrupt PTM 5 compare match interrupt PTM 6 underflow interrupt PTM 6 compare match interrupt PTM 7 underflow interrupt PTM 7 compare match interrupt System reserved (cannot be used)

Software interrupt

For each vector address and the address after it, the start address of the exception processing routine is written into the subordinate and super ordinate sequence. When an exception processing factor is generated, the exception processing routine is executed starting from the recorded address.

Priority

High

↑

↓

Low

priority

rating

When multiple exception processing factors are generated at the same time, execution starts with the highest priority item. The priority sequence shown in Table 3.3.1 assumes that the interrupt priority levels are all the same. The interrupt priority levels can be set by software in each system. (See Section 5.14, "Interrupt and Standby Status".)

Note: For exception processing other than reset,

SC (system condition flag) and PC (program counter) are evacuated to the stack and branches to the exception processing routines. Consequently, when returning to the main routine from exception processing routines, please use the RETE instruction.

See the "S1C88 Core CPU Manual" for information on CPU operations when an exception processing factor is generated.

3.4 CC (Customized Condition Flag)

The S1C88650 does not use the customized condition flag (CC) in the core CPU. Accordingly, it cannot be used as a branching condition for the conditional branching instruction (JRS, CARS).

3.5 Chip Mode

3.5.1 MCU mode and MPU mode

The chip operating mode can be set to one of two settings using the MCU/MPU terminal.

■

MCU mode...Set the MCU/MPU terminal to HIGH

Switch to this setting when using internal ROM. With respect to areas other than internal memory, external memory can even be expanded. See Section 3.5.2, "Bus mode", for the memory map.

In the MCU mode, during initial reset, only systems in internal memory are activated. Internal program ROM is normally fixed as the top portion of the program memory from the common area (logical space 0000H–7FFFH). Exception processing vectors are assigned in internal program ROM. Furthermore, the application initialization routines that start with reset exception processing must likewise be written to internal program ROM. Since bus and other settings which correlate with external expanded memory can be executed in software, this processing is executed in the initialization routine written to internal program ROM. Once these bus mode settings are made, external memory can be accessed.

_______

S1C88650 TECHNICAL MANUAL EPSON 9

3 CPU AND BUS CONFIGURATION

0EFFFFH

010000H 00FFFFH 00FF00H 00FD7FH 00F800H 00F7FFH 00D800H 00D7FFH

: 00C000H 00BFFFH

000000H

- MCU mode -

Kanji font ROM

(896K bytes)

I/O memory

Display memory

Internal RAM

Unused area

Internal ROM

When accessing internal memory in this mode,

____ ____ _____

the chip enable (CE) and read (RD)/write (WR) signals are not output to external memory, and the data bus (D0–D7) goes into high impedance status (or pull-up status). Consequently, in cases where addresses overlap in external and internal memory, the areas in external memory will be unavailable.

■

MPU mode...Set the MCU/MPU terminal to LOW

_______

Internal ROM area is released to an external device source. Internal ROM then becomes unusable and when this area is accessed, chip

____ ____ _____

enable (CE) and read (RD)/write (WR) signals are output to external memory and the data bus (D0–D7) become active. These signals are not output to an external source when other areas of internal memory are accessed.

In the MPU mode, the system is activated by external memory. When employing this mode, the exception processing vectors and initialization routine must be assigned within the common area (000000H–007FFFH).

You can select whether to use the built-in pull-up

_______

resistor of the MCU/MPU terminal by the mask option.

3.5.2 Bus mode

In order to set bus specifications to match the configuration of external expanded memory, two different bus modes described below are selectable in software.

■ Single chip mode

Iput port pull-up resistor

_______

MCU/MPU ..... ■■ With resistor ■■ Gate direct

Notes: •

Setting of MCU/MPU terminal is latched at the rising edge of a reset signal input from the RESET terminal. Therefore, if the setting is to be changed, the RESET terminal must be set to LOW level once again.

•

The data bus while the CPU accesses to the internal memory can be select into highimpedance status or pulled up to high using the pull-up control register and mask option. See Section 5.7, "I/O Ports (P ports)", for details.

Fig. 3.5.2.1 Memory map for the single chip mode

The single chip mode setting applies when the S1C88650 is used as a single chip microcomputer without external expanded memory. Since this mode employs internal ROM, the system can only be operated in the MCU mode discussed in Section 3.5.1. In the MPU mode, the system cannot be set to the single chip mode. Since there is no need for an external bus line in this mode, terminals normally set for bus use can be used as general purpose output ports or I/O ports.

■ Expansion mode

The expansion mode setting applies when the S1C88650 is used with less than 1M bytes × 3 of external expanded memory. This mode is usable regardless of the MCU/MPU mode setting.

Because internal ROM is being used in the MCU mode, external memory in this model can be assigned to the area from 100000H to 3FFFFFH. Since the internal ROM area is released in the MPU mode, external memory in this model can be assigned to the area from 000000H to 2FFFFFH. However, the area from 00C000H to 00FFFFH is assigned to internal memory and cannot be used to access an external device.

10 EPSON S1C88650 TECHNICAL MANUAL

3 CPU AND BUS CONFIGURATION

- MCU mode -

3FFFFFH

External

memory area

100000H

0F0000H 0EFFFFH

010000H 00FFFFH 00D800H 00D7FFH

00C000H 00BFFFH

000000H

Unused area

Internal memory

Unused area

Internal memory

See Figure 3.2.1 for the internal memory

- MPU mode -

2FFFFFH

External memory area

Internal memory

External memory area

Fig. 3.5.2.2 Memory map for the expansion mode

There is an explanation on how all these settings are actually made in "5.2 System Controller and Bus Control" of this Manual.

3.5.3 CPU mode

The CPU allows software to select its operating mode from two types shown below according to the programming area size.

■ Minimum mode

The program area is configured within 64K bytes in any one-bank. However, the bank to be used must be specified in the CB register and cannot be changed after an initialization. This mode does not push the CB register contents onto the stack when a subroutine is called. It makes it possible to economize on stack area usage. This mode is suitable for small- to midscale program memory and large-scale data memory systems.

■ Maximum mode

The program area can be configured exceeding 64K bytes. However the CB register must be setup when the program exceeds a bank boundary every 64K bytes. This mode pushes the CB register contents when a subroutine is called. This mode is suitable for large-scale program and data memory systems.

3.6 External Bus

The S1C88650 has bus terminals that can address a maximum of 1M × 3 bytes and memory (and other) devices can be externally expanded according to the range of each bus mode described in the previous section.

Address bus (A0–A19)

Data bus (D0–D7)

S1C88650

BREQ

External

device

BACK

RD WR CE0 CE1 CE2

Fig. 3.6.1 External bus lines

Below is an explanation of external bus terminals. For information on control methods, see Section 5.2, "System Controller and Bus Control".

3.6.1 Data bus

The S1C88650 possesses an 8-bit external data bus (D0–D7). The terminals and I/O circuits of data bus D0–D7 are shared with I/O ports P00–P07, switching between these functions being determined by the bus mode setting. In the single chip mode, the 8-bit terminals are all set as I/O ports P00–P07 and in the expansion mode, they are set as data bus (D0–D7). When set as data bus, the data register and I/O control register of each I/O port are detached from the I/O circuits and usable as a general purpose data register with read/write capabilities.

The data bus can be pulled up to high during input mode using the built-in pull-up resistor. This pullup resistor is enabled or disabled using the pull-up control register and mask option. See "5.7 I/O Ports" for details.

I/O

port

P00 P01 P02

Single

chip

Fig. 3.6.1.1 Correspondence between data bus

P03 P04 P05 P06 P07

and I/O ports

Data

bus

D0 D1 D2 D3 D4 D5 D6 D7

External

device

Bus modeBus mode

Expansion

External

device

S1C88650 TECHNICAL MANUAL EPSON 11

3 CPU AND BUS CONFIGURATION

3.6.2 Address bus

The S1C88650 possesses a 20-bit external address bus A0–A19. The terminals and output circuits of address bus A0–A19 are shared with output ports R00–R07 (=A0–A7), R10–R17 (=A8–A15) and R20– R23 (=A16–A19), switching between these functions being determined by the bus mode setting. In the single chip mode, the 20-bit terminals are all set as output ports R00–R07, R10–R17 and R20–R23. In the expansion mode, all of the 20-bit terminals are set as the address bus (A0–A19). When set as an address bus, the data register and high impedance control register of each output port are detached from the output circuit and used as a general purpose data register with read/write capabilities.

Single

chip

Output

port

R00 R01 R02 R03 R04 R05 R06 R07 R10 R11 R12 R13 R14 R15 R16 R17 R20 R21 R22 R23

Address

bus

A0 A1 A2 A3 A4 A5 A6 A7 A8

A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19

Bus modeBus mode

Expansion

Fig. 3.6.2.1 Correspondence between address bus

and output ports

_____ ______

3.6.3 Read (RD)/write (WR) signals

The output terminals and output circuits for the

____ _____

read (RD)/write (WR) signals directed to external devices are shared respectively with output ports R24 and R25, switching between these functions being determined by the bus mode setting. In the single chip mode, both of these terminals are set as output port terminals and in the expansion mode, they are set as read (RD)/write (WR) signal output terminals.

____ _____

When set as read (RD)/write (WR) signal output

____ _____

terminal, the data register and high impedance control register for each output port (R24, R25) are detached from the output circuit and is usable as a general purpose data register with read/write capabilities. See Section 3.6.5, "WAIT control", for the output timing of the signal.

Output

port

Bus mode

Single

chip

Fig. 3.6.3.1 Correspondence between read (RD)/

R24

R25

_____

RD/WR

signal

Bus mode

Expansion

____

write (WR) signal and output ports

_____

3.6.4 Chip enable (CE) signal

The S1C88650 is equipped with address decoders which can output three different chip enable (CE) signals. Consequently, three devices equipped with a chip

_____ _____

enable (CE) or chip select (CS) terminal can be directly connected without setting the address decoder to an external device.

_____ _____

The three chip enable (CE0–CE2) signal output terminals and output circuits are shared with output ports R30–R32 and in the expansion mode,

____

either the chip enable (CE) output or general output can be selected in software for each of the three bits.

____

When set for chip enable (CE) output, the data register and high impedance control register for each output port are detached from the output circuit and is usable as general purpose data register with read/write capabilities. In the single chip mode, these terminals are set as output ports R30–R32.

us mode

Single

chip

Output

port

R30 R31 R32

signal

CE0 CE1 CE2

Bus mode

Expansion

Fig. 3.6.4.1 Correspondence between CE signals

and output ports

Table 3.6.4.1 shows the address ranges which are

____

assigned to the chip enable (CE) signal in the expansion mode.

____

12 EPSON S1C88650 TECHNICAL MANUAL

Table 3.6.4.1 CE0–CE2 address settings

_____ _____

CE signal

CE0 CE1 CE2

MCU mode MPU mode

300000H–3FFFFFH 100000H–1FFFFFH 200000H–2FFFFFH

Address range (expansion mode)

_____

When accessing the internal memory area, the CE signal is not output. Care should be taken here because the address range for these portions of memory involves irregular settings. The arrangement of memory space for external devices does not necessarily have to be continuous from a subordinate address and any of the chip enable signals can be used to assign areas in memory.

Note:

____

The CE signals will be inactive status when the chip enters the standby mode (HALT mode or SLEEP mode).

See Section 3.6.5, "WAIT control", for the output timing of signal.

3.6.5 WAIT control

In order to insure accessing of external low speed devices during high speed operations, the S1C88650 is equipped with a WAIT function which prolongs access time. (See the "S1C88 Core CPU Manual" for details of the WAIT function.)

The WAIT state numbers to be inserted can be selected in software from a series of 8 as shown in Table 3.6.5.1.

3 CPU AND BUS CONFIGURATION

000000H–00D7FFH, 010000H–0FFFFFH

100000H–1FFFFFH 200000H–2FFFFFH

Table 3.6.5.1 Selectable WAIT state numbers

Selection No. Insert states1022344658610712814

* One state is a 1/2 cycle of the clock in length.

The WAIT states set in software are inserted between bus cycle states T3–T4. Note, however, that WAIT states cannot be inserted when an internal register and internal memory are being accessed and when operating with the OSC1 oscillation circuit (see "5.4 Oscillation Circuits"). Consequently, WAIT state settings are meaningless in the single chip mode.

Figure 3.6.5.1 shows the memory read/write timing charts.

CLK

A0–A19

CE0

CE1

T2 T3 T4

Address

T2 T3 T4

Address

D0–D7

Read data

Read cycle

Write data

Write cycle

(1) No WAIT

WAIT (4 states inserted) WAIT (4 states inserted)

CLK

A0–A19

CE0

CE1

D0–D7

T2 T3 T4

Tw2 Tw2Tw1 Tw1 Tw2 Tw2Tw1 Tw1

Address

Read data

Read cycle

T2 T3 T4

Address

Write data

Write cycle

(2) WAIT state insertion

Fig. 3.6.5.1 Memory read/write cycle

S1C88650 TECHNICAL MANUAL EPSON 13

3 CPU AND BUS CONFIGURATION

3.6.6 Bus authority release state

The S1C88650 is equipped with a bus authority release function on request from an external device so that DMA (Direct Memory Access) transfer can be conducted between external devices. The internal memory cannot be accessed by this function.

There are two terminals used for this function: the bus authority release request signal (BREQ) input terminal and the bus authority release acknowledge signal (BACK) output terminal. The BREQ input terminal is shared with input port

________

terminal K03 and the BACK output terminal with output port terminal R33, use with setting to

________ ________

BREQ/BACK terminals done in software. In the single chip mode, or when using a system which does not require bus authority release, set respective terminals as input and output ports.

________

When the bus authority release request (BREQ =

________

LOW) is received from an external device, the S1C88650 switches the address bus, data bus, RD/

_____ ____

WR signal, and CE signal lines to a high impedance

________

____

state, outputs a LOW level from the BACK terminal and releases bus authority.

________

As soon as a LOW level is output from the BACK terminal, the external device can use the external bus. When DMA is completed, the external device

________

returns the BREQ terminal to HIGH and releases bus authority. Figure 3.6.6.2 shows the bus authority release sequence.

During bus authority release state, internal memory cannot be accessed from the external device. In cases where external memory has areas which overlap areas in internal memory, the external memory areas can be accessed accordance with the

____

CE signal output by the external device.

CLK

A0–A19

D0–D7

BREQ

BACK

Input

port K03

Output

port R33

_______

BREQ

input

BACK

output

_______

Fig. 3.6.6.1 BREQ/BACK terminals

Note: Be careful with the system, such that an

external device does not become the bus master, other than during the bus release status. After setting the BREQ terminal to LOW level, hold the BREQ terminal at LOW level until the BACK terminal becomes LOW level.

_______

If the BREQ terminal is returned to HIGH

_______

level, before the BACK terminal becomes LOW level, the shift to the bus authorization release status will become indefinite.

Tw2 T4 T1 T2 T3 Tw1 Tw2 T4 Tz1 Tz2 Tz1 Tz2 Tz1 Tz2 Tz1 Tz2 T1 T2 T3

(IX)

Program exection status

(IX)

LLLLH

Bus authority release status

PCHL

ANY

Program exection

status

LD [HL],[IX]

Fig. 3.6.6.2 Bus authority release sequence

14 EPSON S1C88650 TECHNICAL MANUAL

4 INITIAL RESET

Initial reset in the S1C88650 is required in order to initialize circuits. This section of the Manual

contains a description of initial reset factors and the initial settings for internal registers, etc.

____________

4.1 Initial Reset Factors

There are two initial reset factors for the S1C88650 as shown below.

External initial reset by the RESET terminal

(1) (2) External initial reset by the simultaneous LOW

level input at input port terminals K00–K03 (mask option)

Figure 4.1.1 shows the configuration of the initial reset circuit. The CPU and peripheral circuits are initialized by means of initial reset factors. When the factor is canceled, the CPU commences reset exception processing. (See the "S1C88 Core CPU Manual".) When this occurs, the reset exception processing vector, Bank 0, 000000H–000001H from program memory is read out and the program (initialization routine) which begins at the readout address is executed.

_________

4.1.1 RESET terminal

Initial reset can be done by externally inputting a LOW level to the RESET terminal. Be sure to maintain the RESET terminal at LOW level for the regulation time after the power on to assure the initial reset. (See Section 8.6, "AC Characteristics".) In addition, be sure to use the RESET terminal for the first initial reset after the power is turned on.

_________

The RESET terminal is equipped with a pull-up resistor. You can select whether or not to use by mask option.

Input port pull-up resistor

_________

RESET............■■ With resistor ■■ Gate direct

_________

4 INITIAL RESET

OSC3 OSC4

OSC1 OSC2

K00

K01

K02

K03

RESET

OSC3

oscillation

circuit

OSC1

oscillation

circuit

Input port K00

Input port K01

Input port K03

SLEEP status

Oscillation stability

waiting signal

Operating clock status

OSC3

Divider

Mask option

/1,024 Hz

OSC1

/256 Hz

Time

authorize

circuit

Reset signal

Fig. 4.1.1 Configuration of initial reset circuit

Selector

Reset release clock

Internal initial reset

S1C88650 TECHNICAL MANUAL EPSON 15

4 INITIAL RESET

4.1.2 Simultaneous LOW level input at input port terminals K00–K03

Another way of executing initial reset externally is to input a LOW level simultaneously to the input ports (K00–K03) selected by mask option. Since there is a built-in time authorize circuit, be sure to maintain the designated input port terminal at LOW level for 65536/fOSC1 seconds (two seconds when the oscillation frequency is fOSC1 = 32.768 kHz) or more to perform the initial reset by means of this function. However, the time authorize circuit is bypassed during the SLEEP (standby) status and oscillation stabilization waiting period, and initial reset is executed immediately after the simultaneous LOW level input to the designated input ports. The combination of input ports (K00–K03) that can be selected by mask option are as follows:

Multiple key entry reset

■■ Not use

■■ K00 & K01

■■ K00 & K01 & K02

■■ K00 & K01 & K02 & K03

For instance, let's say that mask option "K00 & K01 & K02 & K03" is selected, when the input level at input ports K00–K03 is simultaneously LOW, initial reset will take place.

When using this function, make sure that the designated input ports do not simultaneously switch to LOW level while the system is in normal operation.

4.1.3 Initial reset sequence

After cancellation of the LOW level input to the

_________

RESET terminal, when the power is turned on, the start-up of the CPU is held back until the oscillation stabilization waiting time (512/fOSC3 sec.) have elapsed. Figure 4.1.3.1 shows the operating sequence following initial reset release. The CPU starts operating in synchronization with the OSC3 clock after reset status is released.

Also, when using the initial reset by simultaneous LOW level input into the input port, you should be careful of the following points.

(1) During SLEEP status, since the time authoriza-

tion circuit is bypassed, an initial reset is triggered immediately after a LOW level simultaneous input value. In this case, the CPU starts after waiting the oscillation stabilization time, following cancellation of the LOW level simultaneous input.

(2) Other than during SLEEP status, an initial reset

will be triggered 65536/f LOW level simultaneous input. In this case, since a reset differential pulse (64/fOSC1 seconds) is generated within the S1C88650, the CPU will start even if the LOW level simultaneous input status is not canceled.

Note: The oscillation stabilization time described in

this section does not include oscillation start time. Therefore the time interval until the CPU starts executing instructions after power is turned on or SLEEP status is cancelled may be longer than that indicated in the figure below.

OSC3 seconds after a

OSC3

Reset signal

Reset release clock

Internal initial reset

Internal address bus

Internal data bus

Internal read signal

Reset release

Internal initial reset release

PC PC PC 00-0000

Dummy Dummy

512/f

OSC3

[sec] Oscillation stable waiting time Dummy cycle Reset exception processing ∗ Reset status is maintained

during this period.

VECL

Fig. 4.1.3.1 Initial reset sequence

16 EPSON S1C88650 TECHNICAL MANUAL

4.2

Initial Settings After Initial Reset

The CPU internal registers are initialized as follows during initial reset.

Table 4.2.1 Initial settings

Data register A Data register B Index (data) register L Index (data) register H Index register IX Index register IY Program counter Stack pointer Base register Zero flag Carry flag Overflow flag Negative flag Decimal flag Unpack flag Interrupt flag 0 Interrupt flag 1 New code bank register Code bank register Expand page register Expand page register for IX Expand page register for IY

Code Setting value

Bit length

A B

H IX IY

PC SP BR

Z C V N D U I0 I1

NB CB EP XP YP

16 16 16 16

Undefined

Undefined Undefined Undefined Undefined Undefined

8 1 1 1 1 1 1 1 1 8 8 8 8 8

0 0 0 0 0 0 1 1

01H

Undefined

00H 00H 00H

* Reset exception processing loads the preset

values stored in 0 bank, 0000H–0001H into the PC. At the same time, 01H of the NB initial value is loaded into CB.

Initialize the registers which are not initialized at initial reset using software.

Since the internal RAM and display memory are not initialized at initial reset, be sure to initialize using software.

The respectively stipulated initializations are done for internal peripheral circuits. If necessary, the initialization should be done using software. For initial value at initial reset, see the sections on the I/O memory map and peripheral circuit descriptions in the following chapter of this manual.

4 INITIAL RESET

S1C88650 TECHNICAL MANUAL EPSON 17

5 PERIPHERAL CIRCUITS AND THEIR OPERATION (I/O Memory Map)

5 PERIPHERAL CIRCUITS AND

THEIR OPERATION

The peripheral circuits of the S1C88650 is interfaced with the CPU by means of the memory mapped I/O method. For this reason, just as with other memory access operations, peripheral circuits can be controlled by manipulating I/O memory. Below is a description of the operation and control method for each individual peripheral circuit.

5.1 I/O Memory Map

Table 5.1.1(a) I/O Memory map (00FF00H–00FF03H)

SR R/W10Address Bit Name Function Comment

00FF00

(MCU)D7D6

D5 D4 D3 D2 D1 D0

00FF00

(MPU)D7D6

D5 D4 D3 D2 D1 D0

00FF01 D7

D6 D5 D4 D3 D2 D1 D0

00FF02 D7

D3 D2 D1 D0

00FF03 D7

D6 D5 D4 D3 D2 D1 D0

Note:

All the interrupts including NMI are disabled, until you write the optional value into both the "00FF00H" and

BUSMOD CPUMOD – – – CE2 CE1 CE0 BUSMOD CPUMOD – – – CE2 CE1 CE0 SPP7 SPP6 SPP5 SPP4 SPP3 SPP2 SPP1 SPP0 EBR

WT2

WT1

WT0

CLKCHG SOSC3 – – – – – – – – VDSEL DBON

Bus mode CPU mode R/W register R/W register R/W register CE2 (R32) CE1 (R31) CE0 (R30)

CE signal output Enable/Disable

CE signal output

Enable:

DC (R3x) output

Disable: Bus mode CPU mode R/W register R/W register R/W register CE2 (R32) CE1 (R31) CE0 (R30)

CE signal output Enable/Disable

Enable:

CE signal output

Disable:

DC (R3x) output

Stack pointer page address

< SP page allocatable address >

• Single chip mode:

• Expansion mode:

only 0 page 0–27H page

Bus release enable register (K03 and R33 terminal specification) Wait control register

WT2

WT1 1 1 1 1 0 0 0 0

1 1 0 0 1 1 0 0

WT0

Number

of state 1 0 1 0

14 12 10

1 0 1 0

No wait

CPU operating clock switch OSC3 oscillation On/Off control R/W register R/W register – – – – – – Power source select for LCD voltage regulator Power voltage booster On/Off control

____

(MSB)

(LSB)

K03 R33

8 6 4 2

Expansion Maximum

1 1

1 CE2 enable CE1 enable CE0 enable

Expansion Maximum

1 CE2 enable CE1 enable CE0 enable

BREQ

BACK

OSC3

–

Single chip

Minimum

CE2 disable CE1 disable CE0 disable

Minimum

CE2 disable CE1 disable CE0 disable

Input port

Output port

OSC1

Off

"00FF01H" addresses.

18 EPSON S1C88650 TECHNICAL MANUAL

R/W

0 0 0 1

–

0 0

0 0 1 0

1 1 0

0 –

–

– –

–

00R/W

Reserved register

R/W R/W

In Single chip mode,

R/W

these setting are fixed

R/W

at DC output.

R/W

Expansion mode only

R/W

Reserved register

R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

R/W

R/W R/W

Reserved register

R/W R/W

Constantly "0" when being read

R/W

00FF10 D7

D6 D5 D4 D3 D2 D1

00FF11 D7

D6 D5

D3 D2 D1 D0

00FF12 D7

D6 D5 D4

D3 D2 D1 D0

00FF14 D7

D3 D2

HLMOD SEGREV – – – DTFNT LDUTY1

LDUTY0

FRMCS DSPAR LCDC1

LCDC0

LC3 LC2 LC1 LC0

– – SVDDT SVDON

SVDS3 SVDS2 SVDS1 SVDS0

PRPRT1 PST12

PST11

PST10

PRPRT0 PST02

PST01

PST00

5 PERIPHERAL CIRCUITS AND THEIR OPERATION (I/O Memory Map)

Table 5.1.1(b) I/O Memory map (00FF10H–00FF14H)

Heavy load protection mode Reverse SEG assignment R/W register R/W register R/W register LCD dot font selection LCD drive duty selection

LDUTY1

1 1 0 0

LDUTY0

1 0 1 0

Duty

Not allowed

1/16 1/32

1/8

LCD frame signal source clock selection LCD display memory area selection LCD display control

LCDC1

1 1 0 0

LCDC0

1 0 1 0

LCD display

All LCDs lit All LCDs out Normal display Drive off

LCD contrast adjustment

LC3

LC2

LC1

LC0

Contrast

1 0

Dark

Light

– – SVD detection data SVD circuit On/Off SVD criteria voltage setting

SVDS3

SVDS2

SVDS1

SVDS0

1 1 1

Voltage (V)

1 0 1 : 1

Programmable timer 1 clock control Programmable timer 1 division ratio

PST12

PST11

PST10

(OSC3)

OSC3

/ 4096 / 1024 / 256 / 64 / 32 / 8 / 2 / 1

(OSC1)

OSC1

/ 128 / 64 / 32 / 16 / 8 / 4 / 2 / 1

Programmable timer 0 clock control Programmable timer 0 division ratio

PST02

PST01

PST00

(OSC3)

OSC3

/ 4096 / 1024 / 256 / 64 / 32 / 8 / 2 / 1

(OSC1)

OSC1

/ 128 / 64 / 32 / 16 / 8 / 4 / 2 / 1

2.7

2.6

2.5 :

1.8

Reverse

1 1 1

12×12

PTM f

Display area 1 Display area 0

– –

Low

Off

Normal

0 0 0

16×16/5×8

OSC1

– –

Normal

Off

SR R/WAddress Bit Name Function Comment10

0 0 0 0 0 0 1

0 0 0

0 0 0 0

– – 0 0

0 0 0 0

0 0

R/W R/W R/W

Reserved register

R/W R/W R/W R/W

R/W

R/W R/W

These bits are reset

R/W

to (0, 0) when SLP instruction is executed.

R/W

R/W R/W R/W R/W

Constantly "0" when being read

R/W R/W

R/W R/W R/W

R/W R/W

R/W

R/W R/W

R/W

S1C88650 TECHNICAL MANUAL EPSON 19

5 PERIPHERAL CIRCUITS AND THEIR OPERATION (I/O Memory Map)

Table 5.1.1(c) I/O Memory map (00FF15H–00FF18H)

00FF15 D7

00FF17 D7

00FF18 D7

D3 D2

D6 D5 D4 D3 D2 D1 D0

D3 D2

PRPRT3 PST32

PST31

PST30

PRPRT2 PST22

PST21

PST20

– – – – PRTF3 PRTF2 PRTF1 PRTF0 PRPRT5 PST52

PST51

PST50

PRPRT4 PST42

PST41

PST40

Programmable timer 3 clock control Programmable timer 3 division ratio

PST32

PST31

PST30

(OSC3)

OSC3

/ 4096 / 1024 / 256 / 64 / 32 / 8 / 2 / 1

(OSC1)

OSC1

f f

OSC1 OSC1

OSC1

/ 128 / 64 / 32 / 16 / 8 / 4 / 2 / 1

Programmable timer 2 clock control Programmable timer 2 division ratio

PST22

PST21

PST20

(OSC3)

OSC3

/ 4096 / 1024 / 256 / 64 / 32 / 8 / 2 / 1

(OSC1)

OSC1

/ 128 / 64 / 32 / 16 / 8 / 4 / 2 / 1

– – – R/W register Programmable timer 3 source clock selection Programmable timer 2 source clock selection Programmable timer 1 source clock selection Programmable timer 0 source clock selection

Programmable timer 5 clock control Programmable timer 5 division ratio

PST52

PST51

PST50

(OSC3)

OSC3

/ 4096 / 1024 / 256 / 64 / 32 / 8 / 2 / 1

(OSC1)

OSC1

/ 128 / 64 / 32 / 16 / 8 / 4 / 2 / 1

Programmable timer 4 clock control Programmable timer 4 division ratio

PST42

PST41

PST40

(OSC3)

OSC3

/ 4096 / 1024 / 256 / 64 / 32 / 8 / 2 / 1

(OSC1)

OSC1

/ 128 / 64 / 32 / 16 / 8 / 4 / 2 / 1

f f f f

OSC1

SR R/WAddress Bit Name Function Comment10

Off

– – – 1

OSC3

f f

OSC3

– – – 0

Off

R/W

– –

Constantly "0" when being read

– 0

R/W

Reserved register

R/W

20 EPSON S1C88650 TECHNICAL MANUAL

00FF19 D7

D3 D2

00FF1B D7

D6 D5 D4 D3 D2 D1 D0

00FF20 D7

D6 D5 D4 D3 D2 D1

00FF21 D7

D6 D5 D4 D3 D2 D1 D0

00FF22 D7

D6 D5 D4 D3 D2 D1 D0

PRPRT7 PST72

PST71

PST70

PRPRT6 PST62

PST61

PST60

– – – – PRTF7 PRTF6 PRTF5 PRTF4 PK01 PK00 PSIF1 PSIF0 – – PTM1

PTM0

– – PPT3 PPT2 PPT1 PPT0 – – – – – – ETM32 ETM8 ETM2 ETM1

5 PERIPHERAL CIRCUITS AND THEIR OPERATION (I/O Memory Map)

Table 5.1.1(d) I/O Memory map (00FF19H–00FF22H)

Programmable timer 7 clock control Programmable timer 7 division ratio

PST72

PST71

PST70

(OSC3)

OSC3

/ 4096 / 1024 / 256 / 64 / 32 / 8 / 2 / 1

(OSC1)

OSC1

f f

OSC1 OSC1

OSC1

f f

OSC1

/ 128 / 64 / 32 / 16 / 8 / 4 / 2 / 1

Programmable timer 6 clock control Programmable timer 6 division ratio

PST62

PST61

PST60

(OSC3)

OSC3

/ 4096 / 1024 / 256 / 64 / 32 / 8 / 2 / 1

(OSC1)

OSC1

f f

OSC1 OSC1

OSC1

f f

OSC1

/ 128 / 64 / 32 / 16 / 8 / 4 / 2 / 1

– – – – Programmable timer 7 source clock selection Programmable timer 6 source clock selection Programmable timer 5 source clock selection Programmable timer 4 source clock selection K00–K07 interrupt priority register

Serial interface interrupt priority register

– – Clock timer interrupt priority register

– – Programmable timer 3–2 interrupt priority register Programmable timer 1–0 interrupt priority register – – – – – – Clock timer 32 Hz interrupt enable register Clock timer 8 Hz interrupt enable register Clock timer 2 Hz interrupt enable register Clock timer 1 Hz interrupt enable register

OSC1

f f

OSC1

PK01

PSIF1

1 1 0 0

PTM1

1 1 0 0

PPT3 PPT1

1 1 0 0

Interrupt

enable

– – – –

– –

– – – – – –

PK00

PSIF0

1 0 1 0

PTM0

1 0 1 0

PPT2 PPT0

1 0 1 0

Off

– – – –

OSC3

f f

OSC3

Priority

level Level 3 Level 2 Level 1 Level 0

– –

Priority level

Level 3 Level 2 Level 1 Level 0

– –

Priority

level Level 3 Level 2 Level 1

–

Level 0

– – – – – –

Interrupt

disable

SR R/WAddress Bit Name Function Comment10

0 0

– – – – 0 0 0 0 0

– – 0

– – 00R/W

– – – – – –

0 R/W

R/W R/W

R/W

R/W R/W

R/W

Constantly "0" when being read

R/W R/W R/W R/W R/W

R/W

Constantly "0" when being read

R/W

Constantly "0" when being read

R/W

Constantly "0" when being read Constantly "0" when being read

S1C88650 TECHNICAL MANUAL EPSON 21

5 PERIPHERAL CIRCUITS AND THEIR OPERATION (I/O Memory Map)

Table 5.1.1(e) I/O Memory map (00FF23H–00FF28H)

Address Bit Name SR R/WFunction Comment10

00FF23 –

00FF24 EK07

00FF25 D7

00FF26 D7

00FF27 D7

00FF28 FK07

D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0

D6 D5 D4 D3 D2 D1 D0

D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0

– – – – ESERR ESREC ESTRA

EK06 EK05 EK04 EK03 EK02 EK01 EK00 ETC3 ETU3 ETC2 ETU2 ETC1 ETU1 ETC0 ETU0 – – – – FTM32 FTM8 FTM2 FTM1 – – – – – FSERR FSREC FSTRA

FK06 FK05 FK04 FK03 FK02 FK01 FK00

– – – – – Serial I/F (error) interrupt enable register Serial I/F (receiving) interrupt enable register Serial I/F (transmitting) interrupt enable register K07 interrupt enable K06 interrupt enable K05 interrupt enable K04 interrupt enable K03 interrupt enable K02 interrupt enable K01 interrupt enable K00 interrupt enable PTM3 compare match interrupt enable PTM3 underflow interrupt enable PTM2 compare match interrupt enable PTM2 underflow interrupt enable PTM1 compare match interrupt enable PTM1 underflow interrupt enable PTM0 compare match interrupt enable PTM0 underflow interrupt enable – – – – Clock timer 32 Hz interrupt factor flag Clock timer 8 Hz interrupt factor flag Clock timer 2 Hz interrupt factor flag Clock timer 1 Hz interrupt factor flag – – – – – Serial I/F (error) interrupt factor flag Serial I/F (receiving) interrupt factor flag Serial I/F (transmitting) interrupt factor flag K07 interrupt factor flag K06 interrupt factor flag K05 interrupt factor flag K04 interrupt factor flag K03 interrupt factor flag K02 interrupt factor flag K01 interrupt factor flag K00 interrupt factor flag

– – – – –

Interrupt

enable

Interrupt

enable

Interrupt

enable

– – – –

(R)

Generated

(W)

Reset

– – – – –

(R)

Generated

(W)

Reset

(R)

Interrupt

factor is

generated

(W)

Reset

– – – – –

Interrupt

disable

Interrupt

disable

Interrupt

disable

– – – –

(R)

Not generated

(W)

No operation

– – – – –

(R)

Not generated

(W)

No operation

(R)

No interrupt

factor is

generated

(W)

No operation

– – – – –

R/W

0 R/W

– – – –

0 R/W

– – – – –

0 R/W

R/W

Constantly "0" when being read

22 EPSON S1C88650 TECHNICAL MANUAL

+ 152 hidden pages

Epson S1C88650 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

1 INTRODUCTION

1.1 Features

1.2 Block Diagram

1.3 Pins

1.3.1 Pin layout diagram

1.3.2 Pin description

1.4 Mask Option

2 POWER SUPPLY

2.1 Operating V oltage

2.2 Internal Power Supply Circuit

3 CPU AND BUS CONFIGURATION

3.1 CPU

3.2 Internal Memory

3.2.1 Program ROM

3.2.2 RAM

3.2.3 I/O memory

3.2.4 Display memory

3.2.5 Kanji font ROM

3.3 Exception Processing Vectors

3.4 CC (Customized Condition Flag)

3.5 Chip Mode

3.5.1 MCU mode and MPU mode

3.5.2 Bus mode

3.5.3 CPU mode

3.6 External Bus

3.6.1 Data bus

3.6.2 Address bus

3.6.3 Read (RD)/write (WR) signals

3.6.4 Chip enable (CE) signal

3.6.5 WAIT control

3.6.6 Bus authority release state

4.1 Initial Reset Factors

4.1.1 RESET terminal

4 INITIAL RESET

4.1.3 Initial reset sequence

Initial Settings After Initial Reset

5.1 I/O Memory Map