Epson S1C88650 User Manual

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CMOS 8-BIT SINGLE CHIP MICROCOMPUTER

S1C88650

Technical Manual

S1C88650 Technical Hardware

NOTICE

No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no representation that this material is applicable to products requiring high level reliability, such as medical products. Moreover, no license to any intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright infringement of a third party. This material or portions thereof may contain technology or the subject relating to strategic products under the control of the Foreign Exchange and Foreign Trade Law of Japan and may require an export license from the Ministry of International Trade and Industry or other approval from another government agency.

Configuration of product number

Devices

S1 C 88104 F 0A01

Packing specifications

 00 : Besides tape & reel  0A : TCP BL 2 directions  0B : Tape & reel BACK  0C: TCP BR 2 directions  0D: TCP BT 2 directions  0E : TCP BD 2 directions  0F : Tape & reel FRONT  0G: TCP BT 4 directions  0H: TCP BD 4 directions  0J : TCP SL 2 directions  0K : TCP SR 2 directions  0L : Tape & reel LEFT  0M: TCP ST 2 directions  0N: TCP SD 2 directions  0P : TCP ST 4 directions  0Q: TCP SD 4 directions  0R: Tape & reel RIGHT  99 : Specs not fixed

Specification Package

 D: die form; F: QFP

Model number Model name

 C: microcomputer, digital products

Product classification

 S1: semiconductor

Development tools

S5U1 C 88348 D1 1

Packing specifications

 00: standard packing Version

 1: Version 1

Tool type

 Hx : ICE  Ex : EVA board  Px : Peripheral board  Wx: Flash ROM writer for the microcomputer  Xx : ROM writer peripheral board

 Cx : C compiler package  Ax : Assembler package  Dx : Utility tool by the model  Qx : Soft simulator

Corresponding model number

 88348: for S1C88348

Tool classification

 C: microcomputer use

Product classification

 S5U1: development tool for semiconductor products

CONTENTS

Contents

1 INTRODUCTION .............................................................................................. 1

1.1 Features .............................................................................................................................1

1.2 Block Diagram ...................................................................................................................2

1.3 Pins ....................................................................................................................................3

1.3.1 Pin layout diagram................................................................................................................... 3

1.3.2 Pin description .........................................................................................................................4

1.4 Mask Option.......................................................................................................................5

2 POWER SUPPLY............................................................................................... 7

2.1 Operating Voltage..............................................................................................................7

2.2 Internal Power Supply Circuit ...........................................................................................7

3 CPU AND BUS CONFIGURATION ................................................................ 8

3.1 CPU ...................................................................................................................................8

3.2 Internal Memory ................................................................................................................8

3.2.1 Program ROM.......................................................................................................................... 8

3.2.2 RAM.......................................................................................................................................... 8

3.2.3 I/O memory............................................................................................................................... 8

3.2.4 Display memory........................................................................................................................8

3.2.5 Kanji font ROM ........................................................................................................................8

3.3 Exception Processing Vectors ...........................................................................................9

3.4 CC (Customized Condition Flag) ......................................................................................9

3.5 Chip Mode..........................................................................................................................9

3.5.1 MCU mode and MPU mode .....................................................................................................9

3.5.2 Bus mode .................................................................................................................................10

3.5.3 CPU mode ...............................................................................................................................11

3.6 External Bus......................................................................................................................11

3.6.1 Data bus ..................................................................................................................................11

3.6.2 Address bus .............................................................................................................................12

3.6.3 Read (RD)/write (WR) signals.................................................................................................12

3.6.4 Chip enable (CE) signal ..........................................................................................................12

3.6.5 WAIT control ........................................................................................................................... 13

3.6.6 Bus authority release state ...................................................................................................... 14

4 INITIAL RESET ............................................................................................... 15

4.1 Initial Reset Factors..........................................................................................................15

4.1.1 RESET terminal....................................................................................................................... 15

4.1.2 Simultaneous LOW level input at input port terminals K00–K03........................................... 16

4.1.3 Initial reset sequence............................................................................................................... 16

4.2 Initial Settings After Initial Reset......................................................................................17

5 PERIPHERAL CIRCUITS AND THEIR OPERATION................................ 18

5.1 I/O Memory Map ..............................................................................................................18

5.2 System Controller and Bus Control ..................................................................................34

5.2.1 Bus mode and CPU mode settings ..........................................................................................34

5.2.2 Address decoder (CE output) settings .....................................................................................34

5.2.3 WAIT state settings.................................................................................................................. 35

5.2.4 Setting the bus authority release request signal......................................................................35

5.2.5 Stack page setting.................................................................................................................... 35

5.2.6 Control of system controller.................................................................................................... 36

5.2.7 Programming notes ................................................................................................................. 38

S1C88650 TECHNICAL MANUAL EPSON i

CONTENTS

5.3 Watchdog Timer................................................................................................................39

5.3.1 Configuration of watchdog timer ............................................................................................ 39

5.3.2 Interrupt function ....................................................................................................................39

5.3.3 Control of watchdog timer ......................................................................................................40

5.3.4 Programming notes ................................................................................................................. 40

5.4 Oscillation Circuits...........................................................................................................41

5.4.1 Configuration of oscillation circuits .......................................................................................41

5.4.2 Mask option ............................................................................................................................. 41

5.4.3 OSC1 oscillation circuit .......................................................................................................... 41

5.4.4 OSC3 oscillation circuit .......................................................................................................... 42

5.4.5 Switching the CPU clocks .......................................................................................................42

5.4.6 Control of oscillation circuit ................................................................................................... 43

5.4.7 Programming notes ................................................................................................................. 43

5.5 Input Ports (K ports).........................................................................................................44

5.5.1 Configuration of input ports....................................................................................................44

5.5.2 Mask option ............................................................................................................................. 44

5.5.3 Pull-up control ........................................................................................................................45

5.5.4 Interrupt function and input comparison register................................................................... 45

5.5.5 Control of input ports .............................................................................................................. 47

5.5.6 Programming notes ................................................................................................................. 50

5.6 Output Ports (R ports) ......................................................................................................51

5.6.1 Configuration of output ports..................................................................................................51

5.6.2 High impedance control .......................................................................................................... 51

5.6.3 DC output ................................................................................................................................ 51

5.6.4 Control of output ports ............................................................................................................52

5.7 I/O Ports (P ports) ............................................................................................................54

5.7.1 Configuration of I/O ports.......................................................................................................54

5.7.2 Mask option ............................................................................................................................. 54

5.7.3 I/O control registers and I/O mode ......................................................................................... 54

5.7.4 Pull-up control ........................................................................................................................55

5.7.5 Special output ..........................................................................................................................55

5.7.6 Control of I/O ports................................................................................................................. 57

5.7.7 Programming notes ................................................................................................................. 60

5.8 Serial Interface .................................................................................................................61

5.8.1 Configuration of serial interface............................................................................................. 61

5.8.2 Switching of terminal functions............................................................................................... 61

5.8.3 Transfer modes ........................................................................................................................62

5.8.4 Clock source ............................................................................................................................63

5.8.5 Transmit-receive control ......................................................................................................... 64

5.8.6 Operation of clock synchronous transfer ................................................................................ 65

5.8.7 Operation of asynchronous transfer .......................................................................................69

5.8.8 Interrupt function ....................................................................................................................73

5.8.9 Control of serial interface ....................................................................................................... 75

5.8.10 Programming notes ............................................................................................................... 80

5.9 Clock Timer.......................................................................................................................81

5.9.1 Configuration of clock timer ...................................................................................................81

5.9.2 Interrupt function ....................................................................................................................81

5.9.3 Control of clock timer .............................................................................................................83

5.9.4 Programming notes ................................................................................................................. 85

5.10 Programmable Timer........................................................................................................86

5.10.1 Configuration of programmable timer.................................................................................. 86

5.10.2 Operation mode..................................................................................................................... 87

5.10.3 Setting of input clock ............................................................................................................. 89

5.10.4 Operation and control of timer .............................................................................................89

5.10.5 Interrupt function ..................................................................................................................91

5.10.6 Setting of TOUT output .........................................................................................................93

5.10.7 Transfer rate setting of serial interface.................................................................................94

ii EPSON S1C88650 TECHNICAL MANUAL

CONTENTS

5.10.8 Setting frame frequency for LCD driver ...............................................................................94

5.10.9 Control of programmable timer ............................................................................................95

5.10.10 Programming notes ............................................................................................................ 107

5.11 LCD Driver ......................................................................................................................108

5.11.1 Configuration of LCD driver................................................................................................108

5.11.2 LCD power supply................................................................................................................ 108

5.11.3 Frame frequency .................................................................................................................. 109

5.11.4 Switching drive duty ............................................................................................................. 109

5.11.5 Display memory....................................................................................................................113

5.11.6 Display control ..................................................................................................................... 120

5.11.7 Control of LCD driver.......................................................................................................... 121

5.11.8 Programming notes .............................................................................................................. 123

5.12 Supply Voltage Detection (SVD) Circuit .........................................................................124

5.12.1 Configuration of SVD circuit ...............................................................................................124

5.12.2 SVD operation ...................................................................................................................... 124

5.12.3 Control of SVD circuit..........................................................................................................125

5.12.4 Programming notes .............................................................................................................. 125

5.13 Heavy Load Protection Function.....................................................................................126

5.13.1 Outline of heavy load protection function............................................................................ 126

5.13.2 Control of heavy load protection function ...........................................................................126

5.13.3 Programming note................................................................................................................126

5.14 Interrupt and Standby Status ...........................................................................................127

5.14.1 Interrupt generation conditions ...........................................................................................127

5.14.2 Interrupt factor flag.............................................................................................................. 129

5.14.3 Interrupt enable register ......................................................................................................130

5.14.4 Interrupt priority register and interrupt priority level......................................................... 131

5.14.5 Exception processing vectors ............................................................................................... 132

5.14.6 Control of interrupt ..............................................................................................................133

5.14.7 Programming notes .............................................................................................................. 135

6 SUMMARY OF NOTES .................................................................................. 136

6.1 Notes for Low Current Consumption...............................................................................136

6.2 Precautions on Mounting.................................................................................................137

7 BASIC EXTERNAL WIRING DIAGRAM..................................................... 139

8 ELECTRICAL CHARACTERISTICS............................................................ 140

8.1 Absolute Maximum Rating...............................................................................................140

8.2 Recommended Operating Conditions ..............................................................................140

8.3 DC Characteristics ..........................................................................................................141

8.4 Analog Circuit Characteristics ........................................................................................142

8.5 Power Current Consumption ...........................................................................................143

8.6 AC Characteristics...........................................................................................................144

8.7 Oscillation Characteristics ..............................................................................................149

8.8 Characteristics Curves (reference value) ........................................................................150

9 PACKAGE ........................................................................................................ 159

9.1 Plastic Package................................................................................................................159

9.2 Ceramic Package for Test Samples .................................................................................160

10 PAD LAYOUT .................................................................................................. 161

10.1 Diagram of Pad Layout ...................................................................................................161

10.2 Pad Coordinates ..............................................................................................................162

S1C88650 TECHNICAL MANUAL EPSON iii

CONTENTS

APPENDIX A S5U1C88000P1&S5U1C88649P2 MANUAL

(Peripheral Circuit Board for S1C88650) ...................................... 163

A.1 Names and Functions of Each Part .................................................................................163

A.2 Precautions ......................................................................................................................165

A.2.1 Precaution for operation .......................................................................................................165

A.2.2 Differences from actual IC ....................................................................................................165

A.3 Connecting to the Target System .....................................................................................168

A.4 Product Specifications .....................................................................................................171

APPENDIX B USING KANJI FONT ..................................................................... 172

iv EPSON S1C88650 TECHNICAL MANUAL

1 INTRODUCTION

The S1C88650 is an 8-bit microcomputer for portable equipment with an LCD display that has a built-in LCD controller/driver and a character generator (kanji) ROM. This microcomputer features low-voltage (1.8 V) and high-speed (8.2 MHz) operations as well as low-current consumption (2.5 µA during standby). The LCD controller/driver contains an LCD drive power supply circuit and can drive an maximum of 126 × 32-dot LCD panel in low-power consumption. The S1C88650 has a built-in 11 × 12-dot kanji font

other characters and user-defined characters, this makes it possible to display kanji characters without any external kanji font ROM (refer to Appendix B, "USING KANJI FONT"). This 8-bit CPU has up to 16MB accessible address space allowing easy implementation of a large data processing application. The S1C88650 is suitable for display modules, portable CD/MD, solid audio players, PDA, data bank and other applications that required an exclusive LCD driver in conventional systems.

ROM that contains JIS level-1 and level-2 kanji sets,

1.1 Features

Table 1.1.1 lists the features of the S1C88650.

Table 1.1.1 Main features

Core CPU Main

(OSC3)

Sub Instruction set Min. instruction execution time Internal ROM capacity

Internal RAM capacity Bus line

Input port Output port

I/O port

Serial interface Timer

LCD driver

Watchdog timer Supply voltage detection (SVD) circuit Interrupt

Supply voltage Current consumption

Supply form

S1C88650 TECHNICAL MANUAL EPSON 1

oscillation circuit

(OSC1)

oscillation circuit

∗ The current consumption with LCD ON listed above is the value under the conditions of LCDCx = "11 (all on)", LCx = "0FH" and

"No panel load". Current consumption increases according to the display contents and panel load.

S1C88 (MODEL3) CMOS 8-bit core CPU Crystal oscillation circuit/ceramic oscillation circuit 8.2 MHz (Max.), or CR oscillation circuit 2.2 MHz (Max.) Crystal oscillation circuit 32.768 kHz (Typ.), or CR oscillation circuit 200 kHz (Max.) 608 types (usable for multiplication and division instructions)

0.244 µsec/8.2 MHz (2 clock) 48K bytes/program ROM 896K bytes/kanji font ROM (can be used for a program and data ROM when no font data is stored.) 8K bytes/RAM 768 bytes/display memory Address bus: Data bus: CE signal: WR signal: RD signal: 8 bits (4 bits can be used as the source clock inputs for PWM timers and 1 bit as a bus request signal input) 0–3 bits (when the external bus is used) 26 bits (when the external bus is not used) 8 bits (when the external bus is used) 16 bits (when the external bus is not used) 1 ch (optional clock synchronous system or asynchronous system) Programmable timer: Clock timer: Dot matrix type (supports 16 × 16/5 × 8 or 12 × 12 dot font) 126 segments × 32, 16 or 8 commons (1/5 bias) Built-in LCD power supply circuit (booster type, 5 potentials) Built-in (1–8 second cycles) 13 value programmable (1.8–2.7 V)

External interrupt: Internal interrupt:

1.8–3.6 V SLEEP mode: 1 µA(Typ.) HALT mode: 2.5 µA(Typ.) 32 kHz crystal, LCD OFF

Run state: 9 µA(Typ.) 32 kHz crystal, LCD OFF

QFP22-256pin or chip

20 bits (also usable as general output ports when not used for the bus) 8 bits (also usable as general I/O ports when not used for the bus) 3 bits 1 bit

(also usable as general output ports when not used for the bus)

1 bit

(1 bit can be configured for the bus acknowledge signal output)

(shard with serial interface, FOUT and TOUT terminals)

16 bits (8 bits × 2) 4 ch (with PWM function) 1 ch

Input interrupt Timer interrupt Serial interface interrupt

10 µA(Typ.) 32 kHz CR, LCD OFF

7.6 µA(Typ.) 32 kHz crystal, LCD ON*, V

15 µA(Typ.) 32 kHz CR, LCD OFF 1700 µA(Typ.) 8 MHz ceramic, LCD OFF 600 µA(Typ.) 2 MHz CR, LCD OFF 14 µA(Typ.) 32 kHz crystal, LCD ON*, V 19 µA(Typ.) 32 kHz crystal, LCD ON*, V 14 µA(Typ.) 32 kHz crystal, SVD ON

1 system (8 types) 2 systems (16 types) 1 system (3 types)

DD = 2.5–3.6 V

DD = 2.5–3.6 V DD = 1.8–2.5 V, Power voltage booster ON

1 INTRODUCTION

1.2 Block Diagram

Core CPU S1C88

OSC1, 2 OSC3, 4

MCU/MPU BREQ (K03) BACK (R33)

RESET

TEST

EXCL0–EXCL3 (K04–K07)

TOUT0–TOUT3 (P14, P15)

TOUT2/TOUT3 (P17)

V V

VC1–V

CA–CG

Oscillator

System Controller Input Port

Reset/Test

Watchdog Timer

Programmable Timer

/Event Counter

Clock Timer

DD SS

D1 D2 C5

Power Generator

RAM

8K bytes

Interrupt Controller

I/O Port

Serial Interface

External

Memory Interface

Output Port

LCD Driver

Supply Voltage Detector

ROM

48K bytes+896K bytes

K00–K02 K03 (BREQ) K04–K07

P10 (SIN) P11 (SOUT) P12 (SCLK) P13 (SRDY) P14 (TOUT0/TOUT1) P15 (TOUT2/TOUT3) P16 (FOUT) P17 (TOUT2/TOUT3) P00–P07 (D0–D7) R00–R07, R10–R17, R20–R23

(A0–A7, A8–A15, A16–A19) R24, R25 (RD, WR)

R30–R32 (CE0–CE2) R33 (BACK)

SEG0–SEG125

COM0–COM31

Fig. 1.2.1 S1C88650 block diagram

2 EPSON S1C88650 TECHNICAL MANUAL

1 INTRODUCTION

1.3 Pins

1.3.1 Pin layout diagram

QFP22-256pin

193

INDEX

256

Pin No. Pin name

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52

N.C. N.C.

TEST SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 SEG57 SEG58 SEG59 SEG60 SEG61 SEG62 SEG63 SEG64 SEG65 SEG66 SEG67 SEG68 SEG69 SEG70 SEG71 SEG72 SEG73 SEG74 SEG75 SEG76 SEG77 SEG78 SEG79 SEG80 SEG81 SEG82 SEG83 SEG84 SEG85 SEG86 SEG87

Pin No. Pin name

53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98

99 100 101 102 103 104

SEG88 SEG89 SEG90 SEG91 SEG92 SEG93 SEG94 SEG95 SEG96

N.C. N.C. N.C. N.C. N.C.

V SEG97 SEG98 SEG99

SEG100 SEG101 SEG102 SEG103 SEG104 SEG105 SEG106 SEG107 SEG108 SEG109 SEG110 SEG111 SEG112 SEG113 SEG114 SEG115 SEG116 SEG117 SEG118 SEG119 SEG120 SEG121 SEG122 SEG123 SEG124 SEG125 COM31 COM30 COM29 COM28 COM27 COM26 COM25 COM24

Pin No. Pin name

105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156

COM23 COM22 COM21 COM20 COM19 COM18 COM17 COM16

CG CF CE CD CC CB CA

N.C. N.C. N.C. N.C. N.C. V

OSC3 OSC4

OSC1 OSC2 TEST

RESET

MCU/MPU K07/EXCL3 K06/EXCL2 K05/EXCL1 K04/EXCL0

K03/BREQ

K02 K01 K00

P17/TOUT2/TOUT3

P16/FOUT P15/TOUT2/TOUT3 P14/TOUT0/TOUT1

P13/SRDY P12/SCLK P11/SOUT

P10/SIN

Fig. 1.3.1.1 S1C88650 pin layout

S1C88650 TECHNICAL MANUAL EPSON 3

129192

128

641

Pin No. Pin name

157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208

P07/D7 P06/D6 P05/D5 P04/D4 P03/D3 P02/D2 P01/D1 P00/D0 R00/A0 R01/A1 R02/A2 R03/A3 R04/A4 R05/A5 R06/A6 R07/A7 R10/A8

R11/A9 R12/A10 R13/A11 R14/A12 R15/A13 R16/A14 R17/A15 R20/A16 R21/A17 R22/A18 R23/A19

R24/RD R25/WR R30/CE0 R31/CE1

N.C. N.C. N.C. N.C. N.C.

R32/CE2

R33/BACK

COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9

COM10

Pin No. Pin name

209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256

– – – –

COM11 COM12 COM13 COM14 COM15

SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8

SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38

V N.C. N.C. N.C.

– – – –

1 INTRODUCTION

1.3.2 Pin description

Table 1.3.2.1 S1C88650 pin description

Pin name In/Out Function

VSS VD1 VD2 VC1–VC5 CA–CG OSC1 OSC2 OSC3 OSC4 MCU/MPU K00–K02 K03/BREQ K04/EXCL0 K05/EXCL1 K06/EXCL2 K07/EXCL3 R00–R07/A0–A7 R10–R17/A8–A15 R20–R23/A16–A19 R24/RD R25/WR R30–R32/CE0–CE2 R33 (BACK) P00–P07/D0–D7 P10/SIN P11/SOUT P12/SCLK P13/SRDY P14/TOUT0/TOUT1

P15/TOUT2/TOUT3

P16/FOUT P17/TOUT2/TOUT3

COM0–COM31 SEG0–SEG125

RESET TEST TEST

Pin No.

131, 189

67, 134, 195, 253

135

113 125–121 120–114

136

137

132

133

140 148–146

145

144

143

142

141 165–172 173–180 181–184

185

186

187, 188, 196

197 164–157

156

155

154

153

152

151

150

149

198–213, 112–97

214–252, 4–61,

68–96

139

138

–

Power supply (+) terminal

–

Power supply (GND) terminal

–

Internal logic system and oscillation system voltage regulator output terminals

–

LCD circuit power voltage booster output terminal

–

LCD drive voltage output terminals

–

LCD and power voltage booster capacitor connection terminals

OSC1 oscillation input terminal (select crystal/CR oscillation by mask option)

OSC1 oscillation output terminal

OSC3 oscillation input terminal (select crystal/ceramic/CR oscillation by mask option)

OSC3 oscillation output terminal

MCU/MPU mode setup terminal

Input terminals (K00–K02)

Input terminal (K03) or bus request signal input terminal (BREQ)

Input terminal (K04) or programmable timer external clock input terminal (EXCL0)

Input terminal (K05) or programmable timer external clock input terminal (EXCL1)

Input terminal (K06) or programmable timer external clock input terminal (EXCL2)

Input terminal (K07) or programmable timer external clock input terminal (EXCL3)

Output terminals (R00–R07) or address bus (A0–A7)

Output terminals (R10–R17) or address bus (A8–A15)

Output terminals (R20–R23) or address bus (A16–A19)

Output terminal (R24) or read signal output terminal (RD)

Output terminal (R25) or write signal output terminal (WR)

Output terminals (R30–R32) or chip enable signal output terminals (CE0–CE2)

Output terminal (R33) or bus acknowledge signal output terminal (BACK)

I/O

I/O terminals (P00–P07) or data bus (D0–D7)

I/O

I/O terminal (P10) or serial I/F data input terminal (SIN)

I/O

I/O terminal (P11) or serial I/F data output terminal (SOUT)

I/O

I/O terminal (P12) or serial I/F clock I/O terminal (SCLK)

I/O

I/O terminal (P13) or serial I/F ready signal output terminal (SRDY)

I/O

I/O terminal (P14) or programmable timer underflow signal output terminal (TOUT0/TOUT1)

I/O

I/O terminal (P15) or programmable timer underflow signal output terminal (TOUT2/TOUT3)

I/O

I/O terminal (P16) or clock output terminal (FOUT)

I/O

I/O terminal (P17) or programmable timer underflow inverted signal output terminal (TOUT2/TOUT3)

LCD common output terminals

LCD segment output terminals

Initial reset input terminal

Test input terminal

–

Test terminal (open during normal operation)

4 EPSON S1C88650 TECHNICAL MANUAL

1 INTRODUCTION

1.4 Mask Option

Mask options shown below are provided for the S1C88650. Several hardware specifications are prepared in each mask option, and one of them can be selected according to the application. Multiple specifications are available in each option item as indicated in the

Select the specifications that meet the target system and check the appropriate box. The option selection is done interactively on the screen during function option generator winfog execution, using this option list as reference. Mask pattern of the IC is finally generated based on the data created by the winfog. Refer to the "S5U1C88000C Manual II" for details on the winfog.

Option List.

PERIPHERAL CIRCUIT BOARD option list

The following shows the options for configuring the Peripheral Circuit Board (S5U1C88000P1 with S5U1C88649P2) installed in the ICE (S5U1C88000H5). The selections do not affect the IC's mask option.

A OSC1 SYSTEM CLOCK

■■ 1. Internal Clock

■■ 2. User Clock

B OSC3 SYSTEM CLOCK

■■ 1. Internal Clock

■■ 2. User Clock

When User Clock is selected, input a clock to the OSC1 terminal. When Internal Clock is selected, the clock frequency is changed according to the oscillation circuit selected by the IC's mask option.

When User Clock is selected, input a clock to the OSC3 terminal. When Internal Clock is selected, the clock frequency is changed according to the oscillation circuit

selected by the IC's mask option.

S1C88650 mask option list

The following shows the option list for generating the IC's mask pattern. Note that the Peripheral Circuit Board installed in the ICE does not support some options.

1 OSC1 SYSTEM CLOCK

■■ 1. Crystal

■■ 2. CR

2 OSC3 SYSTEM CLOCK

■■ 1. Crystal

■■ 2. Ceramic

■■ 3. CR

3 MULTIPLE KEY ENTRY RESET

• Combination ..■■ 1. Not Use

■■ 2. Use K00, K01

■■ 3. Use K00, K01, K02

■■ 4. Use K00, K01, K02, K03

4 INPUT PORT PULL UP RESISTOR

• K00...................■■ 1. With Resistor ■■ 2. Gate Direct

• K01...................■■ 1. With Resistor ■■ 2. Gate Direct

• K02...................■■ 1. With Resistor ■■ 2. Gate Direct

• K03...................■■ 1. With Resistor ■■ 2. Gate Direct

• K04...................■■ 1. With Resistor ■■ 2. Gate Direct

• K05...................■■ 1. With Resistor ■■ 2. Gate Direct

• K06...................■■ 1. With Resistor ■■ 2. Gate Direct

• K07...................■■ 1. With Resistor ■■ 2. Gate Direct

• MCU/MPU .... ■■ 1. With Resistor ■■ 2. Gate Direct

• RESET .............■■ 1. With Resistor ■■ 2. Gate Direct

______

________

The specification of the OSC1 oscillation circuit can be selected from among two types: "Crystal oscillation" and "CR oscillation". Refer to Section 5.4.3, "OSC1 oscillation circuit", for details.

The specification of the OSC3 oscillation circuit can be selected from among three types: "Crystal oscillation", "Ceramic oscillation" and "CR oscillation". Refer to Section 5.4.4, "OSC3 oscillation circuit", for details.

This mask option can select whether the multiple key entry reset function is used or not. When the function is used, a combination of the input ports (K00–K03), which are connected to the keys, can be selected. Refer to Section 4.1.2, "Simultaneous LOW level input at input port terminals K00–K03", for details.

This mask option can select whether the pull-up resistor for the input (K) port terminal is used or not. It is possible to select for each bit of the input ports. Refer to Section 5.5, "Input Ports (K ports)", for details. Furthermore, a pull-up option is also provided for the

______ ________

MCU/MPU and RESET terminals.

S1C88650 TECHNICAL MANUAL EPSON 5

1 INTRODUCTION

5 I/O PORT PULL UP RESISTOR

• P00 ......... ■■ 1. With Resistor ■■ 2. Gate Direct

• P01 ......... ■■ 1. With Resistor ■■ 2. Gate Direct

• P02 ......... ■■ 1. With Resistor ■■ 2. Gate Direct

• P03 ......... ■■ 1. With Resistor ■■ 2. Gate Direct

• P04 ......... ■■ 1. With Resistor ■■ 2. Gate Direct

• P05 ......... ■■ 1. With Resistor ■■ 2. Gate Direct

• P06 ......... ■■ 1. With Resistor ■■ 2. Gate Direct

• P07 ......... ■■ 1. With Resistor ■■ 2. Gate Direct

• P10 ......... ■■ 1. With Resistor ■■ 2. Gate Direct

• P11 ......... ■■ 1. With Resistor ■■ 2. Gate Direct

• P12 ......... ■■ 1. With Resistor ■■ 2. Gate Direct

• P13 ......... ■■ 1. With Resistor ■■ 2. Gate Direct

• P14 ......... ■■ 1. With Resistor ■■ 2. Gate Direct

• P15 ......... ■■ 1. With Resistor ■■ 2. Gate Direct

• P16 ......... ■■ 1. With Resistor ■■ 2. Gate Direct

• P17 ......... ■■ 1. With Resistor ■■ 2. Gate Direct

6 INPUT PORT INPUT I/F LEVEL

• K00......... ■■ 1. CMOS Level ■■ 2. CMOS Schmitt

• K01......... ■■ 1. CMOS Level ■■ 2. CMOS Schmitt

• K02......... ■■ 1. CMOS Level ■■ 2. CMOS Schmitt

• K03......... ■■ 1. CMOS Level ■■ 2. CMOS Schmitt

• K04......... ■■ 1. CMOS Level ■■ 2. CMOS Schmitt

• K05......... ■■ 1. CMOS Level ■■ 2. CMOS Schmitt

• K06......... ■■ 1. CMOS Level ■■ 2. CMOS Schmitt

• K07......... ■■ 1. CMOS Level ■■ 2. CMOS Schmitt

This mask option can select whether the pull-up resistor for the I/O port terminal (it works during input mode) is used or not. It is possible to select for each bit of the I/O ports. Refer to Section 5.7, "I/O Ports (P ports)", for details.

This mask option can select the interface level of the input (K) port from either the CMOS level or CMOS Schmitt level. It is possible to select for each bit of the input ports. Refer to Section 5.5, "Input Ports (K ports)", for details. The input port on the ICE (with the Peripheral Circuit Board installed) is fixed to the CMOS level interface regardless of this option selection.

7 I/O PORT INPUT I/F LEVEL

• P10 ......... ■■ 1. CMOS Level ■■ 2. CMOS Schmitt

• P11 ......... ■■ 1. CMOS Level ■■ 2. CMOS Schmitt

• P12 ......... ■■ 1. CMOS Level ■■ 2. CMOS Schmitt

• P13 ......... ■■ 1. CMOS Level ■■ 2. CMOS Schmitt

• P14 ......... ■■ 1. CMOS Level ■■ 2. CMOS Schmitt

• P15 ......... ■■ 1. CMOS Level ■■ 2. CMOS Schmitt

• P16 ......... ■■ 1. CMOS Level ■■ 2. CMOS Schmitt

• P17 ......... ■■ 1. CMOS Level ■■ 2. CMOS Schmitt

WATCHDOG TIMER NMI GENERATION CYCLE

■■ 1. 32768/fOSC1

■■ 2. 65536/fOSC1

■■ 3. 131072/fOSC1

■■ 4. 262144/fOSC1

______

(0.75–1-sec cycle when f

OSC1

= 32 kHz)

(1.5–2-sec cycle when fOSC1 = 32 kHz)

(3–4-sec cycle when fOSC1 = 32 kHz)

(6–8-sec cycle when fOSC1 = 32 kHz)

This mask option can select the interface level of the I/O (P) port from either the CMOS level or CMOS Schmitt level. It is possible to select for each bit of the I/O ports. Refer to Section 5.7, "I/O Ports (P ports)", for details. The input port on the ICE (with the Peripheral Circuit Board installed) is fixed to the CMOS level interface regardless of this option selection.

This mask option can select the NMI generation cycle of

______

the watchdog timer. Refer to Section 5.3.1, "Configuration of watchdog timer", for details.

6 EPSON S1C88650 TECHNICAL MANUAL

2POWER SUPPLY

In this section, we will explain the operating voltage and the configuration of the internal power

supply circuit of the S1C88650.

2 POWER SUPPLY

2.1 Operating V oltage

The S1C88650 operating power voltage is as follows:

1.8 V to 3.6 V

2.2 Internal Power Supply Circuit

The S1C88650 incorporates the power supply circuit shown in Figure 2.2.1. When voltage within the range described above is supplied to VDD (+) and VSS (GND), all the voltages needed for the internal circuit are generated internally in the IC.

Roughly speaking, the power supply circuit is divided into three sections.

Table 2.2.1 Power supply circuit

Circuit

Oscillation circuits, Internal circuits LCD system voltage regulator LCD driver

The internal logic voltage regulator generates the operating voltage <VD1> for driving the internal logic circuits and the oscillation circuit. The VD1 voltage value is fixed at 1.8 V (Typ.).

The power voltage booster generates the operating voltage <V

D2> for the LCD system voltage

regulator.

External power supply

Power supply circuit

Internal logic voltage regulator Power voltage booster LCD system voltage regulator

VDD

VD1

Output voltage

VD1

VDD or VD2

VC1–VC5

Internal logic

voltage regulator

Either <V

DD> or <VD2> can be selected as the

power source for the LCD system voltage regulator according to the <VDD> power supply voltage level.

Table 2.2.2 Power source for LCD system

voltage regulator

Supply voltage

VDD

1.8–2.5 V

2.5–3.6 V

Power source for

LCD system voltage regulator

VD2 VDD

The VD2 voltage is about double the VDD voltage level. Refer to Chapter 8, "ELECTRICAL CHARACTERISTICS", for details.

The LCD system voltage regulator generates the 1/ 5-bias LCD drive voltages <VC1>, <VC2>, <VC3>, <VC4> and <VC5>. See Chapter 8, "ELECTRICAL CHARACTERISTICS" for the voltage values.

In the S1C88650, the LCD drive voltage is supplied to the built-in LCD driver which drives the LCD panel connected to the SEG and COM terminals.

Notes: • Under no circumstances should VD1,VD2,

VC1, VC2, VC3, VC4 and VC5, terminal output be used to drive external circuit.

• If VDD is used as the power source for the LCD system voltage regulator when VDD is

2.5 V or less, the VC1 to VC5 voltages cannot be generated within specifications.

OSC1, OSC2 OSC3, OSC4

VD1

Oscillation circuit

Internal circuit

VD2

V VC2 VC3 VC4 VC5

CC CD

CA CB

Power

voltage

booster

VD2

LCD system

voltage regulator

VC1–VC5

LCD driver

COM0–COM31 SEG0–SEG125

Fig. 2.2.1 Configuration of power supply circuit

S1C88650 TECHNICAL MANUAL EPSON 7

3 CPU AND BUS CONFIGURATION

In this section, we will explain the CPU, operating mode and bus configuration.

3.1 CPU

The S1C88650 utilize the S1C88 8-bit core CPU whose resistor configuration, command set, etc. are virtually identical to other units in the family of processors incorporating the S1C88.

See the "S1C88 Core CPU Manual" for the S1C88. Specifically, the S1C88650 employ the Model 3

S1C88 CPU which has a maximum address space of 1M bytes × 3.

3.2 Internal Memory

The S1C88650 is equipped with internal ROM and RAM as shown in Figure 3.2.1. Small scale applications can be handled by one chip. It is also possible to utilize internal memory in combination with external memory. Furthermore, internal ROM can be disconnected from the bus and the resulting space released for external applications.

0EFFFFH

Kanji font ROM

010000H 00FFFFH 00FF00H 00FD7FH 00F800H 00F7FFH 00D800H 00D7FFH

: 00C000H 00BFFFH

000000H

Fig. 3.2.1 Internal memory map

3.2.1 Program ROM

The S1C88650 has a built-in 48K-byte program ROM. The ROM is allocated to 000000H–00BFFFH. This ROM areas shown above can be released to external memory depending on the setting of the

_______

MCU/MPU terminal. (See "3.5 Chip Mode".)

(896K bytes)

I/O memory

Display memory

RAM (8K bytes)

Unused

area

ROM

(48K bytes)

3.2.2 RAM

The internal RAM capacity is 8K bytes and is allocated to 00D800H–00F7FFH. Even when external memory which overlaps the internal RAM area is expanded, the RAM area is not released to external memory. Access to this area is via internal RAM.

3.2.3 I/O memory

A memory mapped I/O method is employed in the S1C88650 for interfacing with internal peripheral circuit. Peripheral circuit control bits and data register are arranged in data memory space. Control and data exchange are conducted via normal memory access. I/O memory is arranged in page 0: 00FF00H–00FFFFH area. See Section 5.1, "I/O Memory Map", for details of the I/O memory. Even when external memory which overlaps the I/ O memory area is expanded, the I/O memory area is not released to external memory. Access to this area is via I/O memory.

3.2.4 Display memory

The S1C88650 is equipped with an internal display memory which stores a display data for LCD driver. Display memory is arranged in page 0: 00Fx00H– 00Fx7FH (x = 8–DH) in the data memory area. See Section 5.11, "LCD Driver", for details of the display memory. Like the I/O memory, display memory cannot be released to external memory.

3.2.5 Kanji font ROM

The S1C88650 has a built-in kanji font ROM that can be used to store JIS level-1 and level-2 kanji sets, alphanumeric characters and music shift-JIS characters. The kanji font ROM capacity is 896K bytes and is allocated to 010000H–0EFFFFH. When the kanji font is not used the remaining area or the entire area can be used for a program and data storage area (see the "S5U1C88xxxRx Manual" for use of font data). This ROM areas shown above can be released to external memory depending on the setting of the

_______

MCU/MPU terminal. (See "3.5 Chip Mode".)

8 EPSON S1C88650 TECHNICAL MANUAL

3 CPU AND BUS CONFIGURATION

3.3 Exception Processing Vectors

000000H–00004BH in the program area of the S1C88650 is assigned as exception processing vectors. Furthermore, from 00004EH to 0000FFH, software interrupt vectors are assignable to any two bytes which begin with an even address. Table 3.3.1 lists the vector addresses and the exception processing factors to which they correspond.

Table 3.3.1 Exception processing vector table

Vector

address

000000H 000002H 000004H 000006H

000008H 00000AH 00000CH

00000EH

000010H

000012H

000014H

000016H

000018H 00001AH 00001CH

00001EH

000020H

000022H

000024H

000026H

000028H 00002AH 00002CH

00002EH

000030H

000032H

000034H

000036H

000038H 00003AH 00003CH

00003EH

000040H

000042H

000044H

000046H

000048H 00004AH 00004CH

00004EH

0000FEH

Exception processing factor

Reset Zero division Watchdog timer (NMI) K07 input interrupt K06 input interrupt K05 input interrupt K04 input interrupt K03 input interrupt K02 input interrupt K01 input interrupt K00 input interrupt PTM 0 underflow interrupt PTM 0 compare match interrupt PTM 1 underflow interrupt PTM 1 compare match interrupt PTM 2 underflow interrupt PTM 2 compare match interrupt PTM 3 underflow interrupt PTM 3 compare match interrupt System reserved (cannot be used) Serial I/F error interrupt Serial I/F receiving complete interrupt Serial I/F transmitting complete interrupt System reserved (cannot be used) System reserved (cannot be used) System reserved (cannot be used) Clock timer 32 Hz interrupt Clock timer 8 Hz interrupt Clock timer 2 Hz interrupt Clock timer 1 Hz interrupt PTM 4 underflow interrupt PTM 4 compare match interrupt PTM 5 underflow interrupt PTM 5 compare match interrupt PTM 6 underflow interrupt PTM 6 compare match interrupt PTM 7 underflow interrupt PTM 7 compare match interrupt System reserved (cannot be used)

Software interrupt

For each vector address and the address after it, the start address of the exception processing routine is written into the subordinate and super ordinate sequence. When an exception processing factor is generated, the exception processing routine is executed starting from the recorded address.

Priority

High

↑

↓

Low

priority

rating

When multiple exception processing factors are generated at the same time, execution starts with the highest priority item. The priority sequence shown in Table 3.3.1 assumes that the interrupt priority levels are all the same. The interrupt priority levels can be set by software in each system. (See Section 5.14, "Interrupt and Standby Status".)

Note: For exception processing other than reset,

SC (system condition flag) and PC (program counter) are evacuated to the stack and branches to the exception processing routines. Consequently, when returning to the main routine from exception processing routines, please use the RETE instruction.

See the "S1C88 Core CPU Manual" for information on CPU operations when an exception processing factor is generated.

3.4 CC (Customized Condition Flag)

The S1C88650 does not use the customized condition flag (CC) in the core CPU. Accordingly, it cannot be used as a branching condition for the conditional branching instruction (JRS, CARS).

3.5 Chip Mode

3.5.1 MCU mode and MPU mode

The chip operating mode can be set to one of two settings using the MCU/MPU terminal.

■

MCU mode...Set the MCU/MPU terminal to HIGH

Switch to this setting when using internal ROM. With respect to areas other than internal memory, external memory can even be expanded. See Section 3.5.2, "Bus mode", for the memory map.

In the MCU mode, during initial reset, only systems in internal memory are activated. Internal program ROM is normally fixed as the top portion of the program memory from the common area (logical space 0000H–7FFFH). Exception processing vectors are assigned in internal program ROM. Furthermore, the application initialization routines that start with reset exception processing must likewise be written to internal program ROM. Since bus and other settings which correlate with external expanded memory can be executed in software, this processing is executed in the initialization routine written to internal program ROM. Once these bus mode settings are made, external memory can be accessed.

_______

S1C88650 TECHNICAL MANUAL EPSON 9

3 CPU AND BUS CONFIGURATION

0EFFFFH

010000H 00FFFFH 00FF00H 00FD7FH 00F800H 00F7FFH 00D800H 00D7FFH

: 00C000H 00BFFFH

000000H

- MCU mode -

Kanji font ROM

(896K bytes)

I/O memory

Display memory

Internal RAM

Unused area

Internal ROM

When accessing internal memory in this mode,

____ ____ _____

the chip enable (CE) and read (RD)/write (WR) signals are not output to external memory, and the data bus (D0–D7) goes into high impedance status (or pull-up status). Consequently, in cases where addresses overlap in external and internal memory, the areas in external memory will be unavailable.

■

MPU mode...Set the MCU/MPU terminal to LOW

_______

Internal ROM area is released to an external device source. Internal ROM then becomes unusable and when this area is accessed, chip

____ ____ _____

enable (CE) and read (RD)/write (WR) signals are output to external memory and the data bus (D0–D7) become active. These signals are not output to an external source when other areas of internal memory are accessed.

In the MPU mode, the system is activated by external memory. When employing this mode, the exception processing vectors and initialization routine must be assigned within the common area (000000H–007FFFH).

You can select whether to use the built-in pull-up

_______

resistor of the MCU/MPU terminal by the mask option.

3.5.2 Bus mode

In order to set bus specifications to match the configuration of external expanded memory, two different bus modes described below are selectable in software.

■ Single chip mode

Iput port pull-up resistor

_______

MCU/MPU ..... ■■ With resistor ■■ Gate direct

Notes: •

Setting of MCU/MPU terminal is latched at the rising edge of a reset signal input from the RESET terminal. Therefore, if the setting is to be changed, the RESET terminal must be set to LOW level once again.

•

The data bus while the CPU accesses to the internal memory can be select into highimpedance status or pulled up to high using the pull-up control register and mask option. See Section 5.7, "I/O Ports (P ports)", for details.

Fig. 3.5.2.1 Memory map for the single chip mode

The single chip mode setting applies when the S1C88650 is used as a single chip microcomputer without external expanded memory. Since this mode employs internal ROM, the system can only be operated in the MCU mode discussed in Section 3.5.1. In the MPU mode, the system cannot be set to the single chip mode. Since there is no need for an external bus line in this mode, terminals normally set for bus use can be used as general purpose output ports or I/O ports.

■ Expansion mode

The expansion mode setting applies when the S1C88650 is used with less than 1M bytes × 3 of external expanded memory. This mode is usable regardless of the MCU/MPU mode setting.

Because internal ROM is being used in the MCU mode, external memory in this model can be assigned to the area from 100000H to 3FFFFFH. Since the internal ROM area is released in the MPU mode, external memory in this model can be assigned to the area from 000000H to 2FFFFFH. However, the area from 00C000H to 00FFFFH is assigned to internal memory and cannot be used to access an external device.

10 EPSON S1C88650 TECHNICAL MANUAL

3 CPU AND BUS CONFIGURATION

- MCU mode -

3FFFFFH

External

memory area

100000H

0F0000H 0EFFFFH

010000H 00FFFFH 00D800H 00D7FFH

00C000H 00BFFFH

000000H

Unused area

Internal memory

Unused area

Internal memory

See Figure 3.2.1 for the internal memory

- MPU mode -

2FFFFFH

External memory area

Internal memory

External memory area

Fig. 3.5.2.2 Memory map for the expansion mode

There is an explanation on how all these settings are actually made in "5.2 System Controller and Bus Control" of this Manual.

3.5.3 CPU mode

The CPU allows software to select its operating mode from two types shown below according to the programming area size.

■ Minimum mode

The program area is configured within 64K bytes in any one-bank. However, the bank to be used must be specified in the CB register and cannot be changed after an initialization. This mode does not push the CB register contents onto the stack when a subroutine is called. It makes it possible to economize on stack area usage. This mode is suitable for small- to midscale program memory and large-scale data memory systems.

■ Maximum mode

The program area can be configured exceeding 64K bytes. However the CB register must be setup when the program exceeds a bank boundary every 64K bytes. This mode pushes the CB register contents when a subroutine is called. This mode is suitable for large-scale program and data memory systems.

3.6 External Bus

The S1C88650 has bus terminals that can address a maximum of 1M × 3 bytes and memory (and other) devices can be externally expanded according to the range of each bus mode described in the previous section.

Address bus (A0–A19)

Data bus (D0–D7)

S1C88650

BREQ

External

device

BACK

RD WR CE0 CE1 CE2

Fig. 3.6.1 External bus lines

Below is an explanation of external bus terminals. For information on control methods, see Section 5.2, "System Controller and Bus Control".

3.6.1 Data bus

The S1C88650 possesses an 8-bit external data bus (D0–D7). The terminals and I/O circuits of data bus D0–D7 are shared with I/O ports P00–P07, switching between these functions being determined by the bus mode setting. In the single chip mode, the 8-bit terminals are all set as I/O ports P00–P07 and in the expansion mode, they are set as data bus (D0–D7). When set as data bus, the data register and I/O control register of each I/O port are detached from the I/O circuits and usable as a general purpose data register with read/write capabilities.

The data bus can be pulled up to high during input mode using the built-in pull-up resistor. This pullup resistor is enabled or disabled using the pull-up control register and mask option. See "5.7 I/O Ports" for details.

I/O

port

P00 P01 P02

Single

chip

Fig. 3.6.1.1 Correspondence between data bus

P03 P04 P05 P06 P07

and I/O ports

Data

bus

D0 D1 D2 D3 D4 D5 D6 D7

External

device

Bus modeBus mode

Expansion

External

device

S1C88650 TECHNICAL MANUAL EPSON 11

3 CPU AND BUS CONFIGURATION

3.6.2 Address bus

The S1C88650 possesses a 20-bit external address bus A0–A19. The terminals and output circuits of address bus A0–A19 are shared with output ports R00–R07 (=A0–A7), R10–R17 (=A8–A15) and R20– R23 (=A16–A19), switching between these functions being determined by the bus mode setting. In the single chip mode, the 20-bit terminals are all set as output ports R00–R07, R10–R17 and R20–R23. In the expansion mode, all of the 20-bit terminals are set as the address bus (A0–A19). When set as an address bus, the data register and high impedance control register of each output port are detached from the output circuit and used as a general purpose data register with read/write capabilities.

Single

chip

Output

port

R00 R01 R02 R03 R04 R05 R06 R07 R10 R11 R12 R13 R14 R15 R16 R17 R20 R21 R22 R23

Address

bus

A0 A1 A2 A3 A4 A5 A6 A7 A8

A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19

Bus modeBus mode

Expansion

Fig. 3.6.2.1 Correspondence between address bus

and output ports

_____ ______

3.6.3 Read (RD)/write (WR) signals

The output terminals and output circuits for the

____ _____

read (RD)/write (WR) signals directed to external devices are shared respectively with output ports R24 and R25, switching between these functions being determined by the bus mode setting. In the single chip mode, both of these terminals are set as output port terminals and in the expansion mode, they are set as read (RD)/write (WR) signal output terminals.

____ _____

When set as read (RD)/write (WR) signal output

____ _____

terminal, the data register and high impedance control register for each output port (R24, R25) are detached from the output circuit and is usable as a general purpose data register with read/write capabilities. See Section 3.6.5, "WAIT control", for the output timing of the signal.

Output

port

Bus mode

Single

chip

Fig. 3.6.3.1 Correspondence between read (RD)/

R24

R25

_____

RD/WR

signal

Bus mode

Expansion

____

write (WR) signal and output ports

_____

3.6.4 Chip enable (CE) signal

The S1C88650 is equipped with address decoders which can output three different chip enable (CE) signals. Consequently, three devices equipped with a chip

_____ _____

enable (CE) or chip select (CS) terminal can be directly connected without setting the address decoder to an external device.

_____ _____

The three chip enable (CE0–CE2) signal output terminals and output circuits are shared with output ports R30–R32 and in the expansion mode,

____

either the chip enable (CE) output or general output can be selected in software for each of the three bits.

____

When set for chip enable (CE) output, the data register and high impedance control register for each output port are detached from the output circuit and is usable as general purpose data register with read/write capabilities. In the single chip mode, these terminals are set as output ports R30–R32.

us mode

Single

chip

Output

port

R30 R31 R32

signal

CE0 CE1 CE2

Bus mode

Expansion

Fig. 3.6.4.1 Correspondence between CE signals

and output ports

Table 3.6.4.1 shows the address ranges which are

____

assigned to the chip enable (CE) signal in the expansion mode.

____

12 EPSON S1C88650 TECHNICAL MANUAL

Table 3.6.4.1 CE0–CE2 address settings

_____ _____

CE signal

CE0 CE1 CE2

MCU mode MPU mode

300000H–3FFFFFH 100000H–1FFFFFH 200000H–2FFFFFH

Address range (expansion mode)

_____

When accessing the internal memory area, the CE signal is not output. Care should be taken here because the address range for these portions of memory involves irregular settings. The arrangement of memory space for external devices does not necessarily have to be continuous from a subordinate address and any of the chip enable signals can be used to assign areas in memory.

Note:

____

The CE signals will be inactive status when the chip enters the standby mode (HALT mode or SLEEP mode).

See Section 3.6.5, "WAIT control", for the output timing of signal.

3.6.5 WAIT control

In order to insure accessing of external low speed devices during high speed operations, the S1C88650 is equipped with a WAIT function which prolongs access time. (See the "S1C88 Core CPU Manual" for details of the WAIT function.)

The WAIT state numbers to be inserted can be selected in software from a series of 8 as shown in Table 3.6.5.1.

3 CPU AND BUS CONFIGURATION

000000H–00D7FFH, 010000H–0FFFFFH

100000H–1FFFFFH 200000H–2FFFFFH

Table 3.6.5.1 Selectable WAIT state numbers

Selection No. Insert states1022344658610712814

* One state is a 1/2 cycle of the clock in length.

The WAIT states set in software are inserted between bus cycle states T3–T4. Note, however, that WAIT states cannot be inserted when an internal register and internal memory are being accessed and when operating with the OSC1 oscillation circuit (see "5.4 Oscillation Circuits"). Consequently, WAIT state settings are meaningless in the single chip mode.

Figure 3.6.5.1 shows the memory read/write timing charts.

CLK

A0–A19

CE0

CE1

T2 T3 T4

Address

T2 T3 T4

Address

D0–D7

Read data

Read cycle

Write data

Write cycle

(1) No WAIT

WAIT (4 states inserted) WAIT (4 states inserted)

CLK

A0–A19

CE0

CE1

D0–D7

T2 T3 T4

Tw2 Tw2Tw1 Tw1 Tw2 Tw2Tw1 Tw1

Address

Read data

Read cycle

T2 T3 T4

Address

Write data

Write cycle

(2) WAIT state insertion

Fig. 3.6.5.1 Memory read/write cycle

S1C88650 TECHNICAL MANUAL EPSON 13

3 CPU AND BUS CONFIGURATION

3.6.6 Bus authority release state

The S1C88650 is equipped with a bus authority release function on request from an external device so that DMA (Direct Memory Access) transfer can be conducted between external devices. The internal memory cannot be accessed by this function.

There are two terminals used for this function: the bus authority release request signal (BREQ) input terminal and the bus authority release acknowledge signal (BACK) output terminal. The BREQ input terminal is shared with input port

________

terminal K03 and the BACK output terminal with output port terminal R33, use with setting to

________ ________

BREQ/BACK terminals done in software. In the single chip mode, or when using a system which does not require bus authority release, set respective terminals as input and output ports.

________

When the bus authority release request (BREQ =

________

LOW) is received from an external device, the S1C88650 switches the address bus, data bus, RD/

_____ ____

WR signal, and CE signal lines to a high impedance

________

____

state, outputs a LOW level from the BACK terminal and releases bus authority.

________

As soon as a LOW level is output from the BACK terminal, the external device can use the external bus. When DMA is completed, the external device

________

returns the BREQ terminal to HIGH and releases bus authority. Figure 3.6.6.2 shows the bus authority release sequence.

During bus authority release state, internal memory cannot be accessed from the external device. In cases where external memory has areas which overlap areas in internal memory, the external memory areas can be accessed accordance with the

____

CE signal output by the external device.

CLK

A0–A19

D0–D7

BREQ

BACK

Input

port K03

Output

port R33

_______

BREQ

input

BACK

output

_______

Fig. 3.6.6.1 BREQ/BACK terminals

Note: Be careful with the system, such that an

external device does not become the bus master, other than during the bus release status. After setting the BREQ terminal to LOW level, hold the BREQ terminal at LOW level until the BACK terminal becomes LOW level.

_______

If the BREQ terminal is returned to HIGH

_______

level, before the BACK terminal becomes LOW level, the shift to the bus authorization release status will become indefinite.

Tw2 T4 T1 T2 T3 Tw1 Tw2 T4 Tz1 Tz2 Tz1 Tz2 Tz1 Tz2 Tz1 Tz2 T1 T2 T3

(IX)

Program exection status

(IX)

LLLLH

Bus authority release status

PCHL

ANY

Program exection

status

LD [HL],[IX]

Fig. 3.6.6.2 Bus authority release sequence

14 EPSON S1C88650 TECHNICAL MANUAL

4 INITIAL RESET

Initial reset in the S1C88650 is required in order to initialize circuits. This section of the Manual

contains a description of initial reset factors and the initial settings for internal registers, etc.

____________

4.1 Initial Reset Factors

There are two initial reset factors for the S1C88650 as shown below.

External initial reset by the RESET terminal

(1) (2) External initial reset by the simultaneous LOW

level input at input port terminals K00–K03 (mask option)

Figure 4.1.1 shows the configuration of the initial reset circuit. The CPU and peripheral circuits are initialized by means of initial reset factors. When the factor is canceled, the CPU commences reset exception processing. (See the "S1C88 Core CPU Manual".) When this occurs, the reset exception processing vector, Bank 0, 000000H–000001H from program memory is read out and the program (initialization routine) which begins at the readout address is executed.

_________

4.1.1 RESET terminal

Initial reset can be done by externally inputting a LOW level to the RESET terminal. Be sure to maintain the RESET terminal at LOW level for the regulation time after the power on to assure the initial reset. (See Section 8.6, "AC Characteristics".) In addition, be sure to use the RESET terminal for the first initial reset after the power is turned on.

_________

The RESET terminal is equipped with a pull-up resistor. You can select whether or not to use by mask option.

Input port pull-up resistor

_________

RESET............■■ With resistor ■■ Gate direct

_________

4 INITIAL RESET

OSC3 OSC4

OSC1 OSC2

K00

K01

K02

K03

RESET

OSC3

oscillation

circuit

OSC1

oscillation

circuit

Input port K00

Input port K01

Input port K03

SLEEP status

Oscillation stability

waiting signal

Operating clock status

OSC3

Divider

Mask option

/1,024 Hz

OSC1

/256 Hz

Time

authorize

circuit

Reset signal

Fig. 4.1.1 Configuration of initial reset circuit

Selector

Reset release clock

Internal initial reset

S1C88650 TECHNICAL MANUAL EPSON 15

4 INITIAL RESET

4.1.2 Simultaneous LOW level input at input port terminals K00–K03

Another way of executing initial reset externally is to input a LOW level simultaneously to the input ports (K00–K03) selected by mask option. Since there is a built-in time authorize circuit, be sure to maintain the designated input port terminal at LOW level for 65536/fOSC1 seconds (two seconds when the oscillation frequency is fOSC1 = 32.768 kHz) or more to perform the initial reset by means of this function. However, the time authorize circuit is bypassed during the SLEEP (standby) status and oscillation stabilization waiting period, and initial reset is executed immediately after the simultaneous LOW level input to the designated input ports. The combination of input ports (K00–K03) that can be selected by mask option are as follows:

Multiple key entry reset

■■ Not use

■■ K00 & K01

■■ K00 & K01 & K02

■■ K00 & K01 & K02 & K03

For instance, let's say that mask option "K00 & K01 & K02 & K03" is selected, when the input level at input ports K00–K03 is simultaneously LOW, initial reset will take place.

When using this function, make sure that the designated input ports do not simultaneously switch to LOW level while the system is in normal operation.

4.1.3 Initial reset sequence

After cancellation of the LOW level input to the

_________

RESET terminal, when the power is turned on, the start-up of the CPU is held back until the oscillation stabilization waiting time (512/fOSC3 sec.) have elapsed. Figure 4.1.3.1 shows the operating sequence following initial reset release. The CPU starts operating in synchronization with the OSC3 clock after reset status is released.

Also, when using the initial reset by simultaneous LOW level input into the input port, you should be careful of the following points.

(1) During SLEEP status, since the time authoriza-

tion circuit is bypassed, an initial reset is triggered immediately after a LOW level simultaneous input value. In this case, the CPU starts after waiting the oscillation stabilization time, following cancellation of the LOW level simultaneous input.

(2) Other than during SLEEP status, an initial reset

will be triggered 65536/f LOW level simultaneous input. In this case, since a reset differential pulse (64/fOSC1 seconds) is generated within the S1C88650, the CPU will start even if the LOW level simultaneous input status is not canceled.

Note: The oscillation stabilization time described in

this section does not include oscillation start time. Therefore the time interval until the CPU starts executing instructions after power is turned on or SLEEP status is cancelled may be longer than that indicated in the figure below.

OSC3 seconds after a

OSC3

Reset signal

Reset release clock

Internal initial reset

Internal address bus

Internal data bus

Internal read signal

Reset release

Internal initial reset release

PC PC PC 00-0000

Dummy Dummy

512/f

OSC3

[sec] Oscillation stable waiting time Dummy cycle Reset exception processing ∗ Reset status is maintained

during this period.

VECL

Fig. 4.1.3.1 Initial reset sequence

16 EPSON S1C88650 TECHNICAL MANUAL

4.2

Initial Settings After Initial Reset

The CPU internal registers are initialized as follows during initial reset.

Table 4.2.1 Initial settings

Data register A Data register B Index (data) register L Index (data) register H Index register IX Index register IY Program counter Stack pointer Base register Zero flag Carry flag Overflow flag Negative flag Decimal flag Unpack flag Interrupt flag 0 Interrupt flag 1 New code bank register Code bank register Expand page register Expand page register for IX Expand page register for IY

Code Setting value

Bit length

A B

H IX IY

PC SP BR

Z C V N D U I0 I1

NB CB EP XP YP

16 16 16 16

Undefined

Undefined Undefined Undefined Undefined Undefined

8 1 1 1 1 1 1 1 1 8 8 8 8 8

0 0 0 0 0 0 1 1

01H

Undefined

00H 00H 00H

* Reset exception processing loads the preset

values stored in 0 bank, 0000H–0001H into the PC. At the same time, 01H of the NB initial value is loaded into CB.

Initialize the registers which are not initialized at initial reset using software.

Since the internal RAM and display memory are not initialized at initial reset, be sure to initialize using software.

The respectively stipulated initializations are done for internal peripheral circuits. If necessary, the initialization should be done using software. For initial value at initial reset, see the sections on the I/O memory map and peripheral circuit descriptions in the following chapter of this manual.

4 INITIAL RESET

S1C88650 TECHNICAL MANUAL EPSON 17

5 PERIPHERAL CIRCUITS AND THEIR OPERATION (I/O Memory Map)

5 PERIPHERAL CIRCUITS AND

THEIR OPERATION

The peripheral circuits of the S1C88650 is interfaced with the CPU by means of the memory mapped I/O method. For this reason, just as with other memory access operations, peripheral circuits can be controlled by manipulating I/O memory. Below is a description of the operation and control method for each individual peripheral circuit.

5.1 I/O Memory Map

Table 5.1.1(a) I/O Memory map (00FF00H–00FF03H)

SR R/W10Address Bit Name Function Comment

00FF00

(MCU)D7D6

D5 D4 D3 D2 D1 D0

00FF00

(MPU)D7D6

D5 D4 D3 D2 D1 D0

00FF01 D7

D6 D5 D4 D3 D2 D1 D0

00FF02 D7

D3 D2 D1 D0

00FF03 D7

D6 D5 D4 D3 D2 D1 D0

Note:

All the interrupts including NMI are disabled, until you write the optional value into both the "00FF00H" and

BUSMOD CPUMOD – – – CE2 CE1 CE0 BUSMOD CPUMOD – – – CE2 CE1 CE0 SPP7 SPP6 SPP5 SPP4 SPP3 SPP2 SPP1 SPP0 EBR

WT2

WT1

WT0

CLKCHG SOSC3 – – – – – – – – VDSEL DBON

Bus mode CPU mode R/W register R/W register R/W register CE2 (R32) CE1 (R31) CE0 (R30)

CE signal output Enable/Disable

CE signal output

Enable:

DC (R3x) output

Disable: Bus mode CPU mode R/W register R/W register R/W register CE2 (R32) CE1 (R31) CE0 (R30)

CE signal output Enable/Disable

Enable:

CE signal output

Disable:

DC (R3x) output

Stack pointer page address

< SP page allocatable address >

• Single chip mode:

• Expansion mode:

only 0 page 0–27H page

Bus release enable register (K03 and R33 terminal specification) Wait control register

WT2

WT1 1 1 1 1 0 0 0 0

1 1 0 0 1 1 0 0

WT0

Number

of state 1 0 1 0

14 12 10

1 0 1 0

No wait

CPU operating clock switch OSC3 oscillation On/Off control R/W register R/W register – – – – – – Power source select for LCD voltage regulator Power voltage booster On/Off control

____

(MSB)

(LSB)

K03 R33

8 6 4 2

Expansion Maximum

1 1

1 CE2 enable CE1 enable CE0 enable

Expansion Maximum

1 CE2 enable CE1 enable CE0 enable

BREQ

BACK

OSC3

–

Single chip

Minimum

CE2 disable CE1 disable CE0 disable

Minimum

CE2 disable CE1 disable CE0 disable

Input port

Output port

OSC1

Off

"00FF01H" addresses.

18 EPSON S1C88650 TECHNICAL MANUAL

R/W

0 0 0 1

–

0 0

0 0 1 0

1 1 0

0 –

–

– –

–

00R/W

Reserved register

R/W R/W

In Single chip mode,

R/W

these setting are fixed

R/W

at DC output.

R/W

Expansion mode only

R/W

Reserved register

R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

R/W

R/W R/W

Reserved register

R/W R/W

Constantly "0" when being read

R/W

00FF10 D7

D6 D5 D4 D3 D2 D1

00FF11 D7

D6 D5

D3 D2 D1 D0

00FF12 D7

D6 D5 D4

D3 D2 D1 D0

00FF14 D7

D3 D2

HLMOD SEGREV – – – DTFNT LDUTY1

LDUTY0

FRMCS DSPAR LCDC1

LCDC0

LC3 LC2 LC1 LC0

– – SVDDT SVDON

SVDS3 SVDS2 SVDS1 SVDS0

PRPRT1 PST12

PST11

PST10

PRPRT0 PST02

PST01

PST00

5 PERIPHERAL CIRCUITS AND THEIR OPERATION (I/O Memory Map)

Table 5.1.1(b) I/O Memory map (00FF10H–00FF14H)

Heavy load protection mode Reverse SEG assignment R/W register R/W register R/W register LCD dot font selection LCD drive duty selection

LDUTY1

1 1 0 0

LDUTY0

1 0 1 0

Duty

Not allowed

1/16 1/32

1/8

LCD frame signal source clock selection LCD display memory area selection LCD display control

LCDC1

1 1 0 0

LCDC0

1 0 1 0

LCD display

All LCDs lit All LCDs out Normal display Drive off

LCD contrast adjustment

LC3

LC2

LC1

LC0

Contrast

1 0

Dark

Light

– – SVD detection data SVD circuit On/Off SVD criteria voltage setting

SVDS3

SVDS2

SVDS1

SVDS0

1 1 1

Voltage (V)

1 0 1 : 1

Programmable timer 1 clock control Programmable timer 1 division ratio

PST12

PST11

PST10

(OSC3)

OSC3

/ 4096 / 1024 / 256 / 64 / 32 / 8 / 2 / 1

(OSC1)

OSC1

/ 128 / 64 / 32 / 16 / 8 / 4 / 2 / 1

Programmable timer 0 clock control Programmable timer 0 division ratio

PST02

PST01

PST00

(OSC3)

OSC3

/ 4096 / 1024 / 256 / 64 / 32 / 8 / 2 / 1

(OSC1)

OSC1

/ 128 / 64 / 32 / 16 / 8 / 4 / 2 / 1

2.7

2.6

2.5 :

1.8

Reverse

1 1 1

12×12

PTM f

Display area 1 Display area 0

– –

Low

Off

Normal

0 0 0

16×16/5×8

OSC1

– –

Normal

Off

SR R/WAddress Bit Name Function Comment10

0 0 0 0 0 0 1

0 0 0

0 0 0 0

– – 0 0

0 0 0 0

0 0

R/W R/W R/W

Reserved register

R/W R/W R/W R/W

R/W

R/W R/W

These bits are reset

R/W

to (0, 0) when SLP instruction is executed.

R/W

R/W R/W R/W R/W

Constantly "0" when being read

R/W R/W

R/W R/W R/W

R/W R/W

R/W

R/W R/W

R/W

S1C88650 TECHNICAL MANUAL EPSON 19

5 PERIPHERAL CIRCUITS AND THEIR OPERATION (I/O Memory Map)

Table 5.1.1(c) I/O Memory map (00FF15H–00FF18H)

00FF15 D7

00FF17 D7

00FF18 D7

D3 D2

D6 D5 D4 D3 D2 D1 D0

D3 D2

PRPRT3 PST32

PST31

PST30

PRPRT2 PST22

PST21

PST20

– – – – PRTF3 PRTF2 PRTF1 PRTF0 PRPRT5 PST52

PST51

PST50

PRPRT4 PST42

PST41

PST40

Programmable timer 3 clock control Programmable timer 3 division ratio

PST32

PST31

PST30

(OSC3)

OSC3

/ 4096 / 1024 / 256 / 64 / 32 / 8 / 2 / 1

(OSC1)

OSC1

f f

OSC1 OSC1

OSC1

/ 128 / 64 / 32 / 16 / 8 / 4 / 2 / 1

Programmable timer 2 clock control Programmable timer 2 division ratio

PST22

PST21

PST20

(OSC3)

OSC3

/ 4096 / 1024 / 256 / 64 / 32 / 8 / 2 / 1

(OSC1)

OSC1

/ 128 / 64 / 32 / 16 / 8 / 4 / 2 / 1

– – – R/W register Programmable timer 3 source clock selection Programmable timer 2 source clock selection Programmable timer 1 source clock selection Programmable timer 0 source clock selection

Programmable timer 5 clock control Programmable timer 5 division ratio

PST52

PST51

PST50

(OSC3)

OSC3

/ 4096 / 1024 / 256 / 64 / 32 / 8 / 2 / 1

(OSC1)

OSC1

/ 128 / 64 / 32 / 16 / 8 / 4 / 2 / 1

Programmable timer 4 clock control Programmable timer 4 division ratio

PST42

PST41

PST40

(OSC3)

OSC3

/ 4096 / 1024 / 256 / 64 / 32 / 8 / 2 / 1

(OSC1)

OSC1

/ 128 / 64 / 32 / 16 / 8 / 4 / 2 / 1

f f f f

OSC1

SR R/WAddress Bit Name Function Comment10

Off

– – – 1

OSC3

f f

OSC3

– – – 0

Off

R/W

– –

Constantly "0" when being read

– 0

R/W

Reserved register

R/W

20 EPSON S1C88650 TECHNICAL MANUAL

00FF19 D7

D3 D2

00FF1B D7

D6 D5 D4 D3 D2 D1 D0

00FF20 D7

D6 D5 D4 D3 D2 D1

00FF21 D7

D6 D5 D4 D3 D2 D1 D0

00FF22 D7

D6 D5 D4 D3 D2 D1 D0

PRPRT7 PST72

PST71

PST70

PRPRT6 PST62

PST61

PST60

– – – – PRTF7 PRTF6 PRTF5 PRTF4 PK01 PK00 PSIF1 PSIF0 – – PTM1

PTM0

– – PPT3 PPT2 PPT1 PPT0 – – – – – – ETM32 ETM8 ETM2 ETM1

5 PERIPHERAL CIRCUITS AND THEIR OPERATION (I/O Memory Map)

Table 5.1.1(d) I/O Memory map (00FF19H–00FF22H)

Programmable timer 7 clock control Programmable timer 7 division ratio

PST72

PST71

PST70

(OSC3)

OSC3

/ 4096 / 1024 / 256 / 64 / 32 / 8 / 2 / 1

(OSC1)

OSC1

f f

OSC1 OSC1

OSC1

f f

OSC1

/ 128 / 64 / 32 / 16 / 8 / 4 / 2 / 1

Programmable timer 6 clock control Programmable timer 6 division ratio

PST62

PST61

PST60

(OSC3)

OSC3

/ 4096 / 1024 / 256 / 64 / 32 / 8 / 2 / 1

(OSC1)

OSC1

f f

OSC1 OSC1

OSC1

f f

OSC1

/ 128 / 64 / 32 / 16 / 8 / 4 / 2 / 1

– – – – Programmable timer 7 source clock selection Programmable timer 6 source clock selection Programmable timer 5 source clock selection Programmable timer 4 source clock selection K00–K07 interrupt priority register

Serial interface interrupt priority register

– – Clock timer interrupt priority register

– – Programmable timer 3–2 interrupt priority register Programmable timer 1–0 interrupt priority register – – – – – – Clock timer 32 Hz interrupt enable register Clock timer 8 Hz interrupt enable register Clock timer 2 Hz interrupt enable register Clock timer 1 Hz interrupt enable register

OSC1

f f

OSC1

PK01

PSIF1

1 1 0 0

PTM1

1 1 0 0

PPT3 PPT1

1 1 0 0

Interrupt

enable

– – – –

– –

– – – – – –

PK00

PSIF0

1 0 1 0

PTM0

1 0 1 0

PPT2 PPT0

1 0 1 0

Off

– – – –

OSC3

f f

OSC3

Priority

level Level 3 Level 2 Level 1 Level 0

– –

Priority level

Level 3 Level 2 Level 1 Level 0

– –

Priority

level Level 3 Level 2 Level 1

–

Level 0

– – – – – –

Interrupt

disable

SR R/WAddress Bit Name Function Comment10

0 0

– – – – 0 0 0 0 0

– – 0

– – 00R/W

– – – – – –

0 R/W

R/W R/W

R/W

R/W R/W

R/W

Constantly "0" when being read

R/W R/W R/W R/W R/W

R/W

Constantly "0" when being read

R/W

Constantly "0" when being read

R/W

Constantly "0" when being read Constantly "0" when being read

S1C88650 TECHNICAL MANUAL EPSON 21

5 PERIPHERAL CIRCUITS AND THEIR OPERATION (I/O Memory Map)

Table 5.1.1(e) I/O Memory map (00FF23H–00FF28H)

Address Bit Name SR R/WFunction Comment10

00FF23 –

00FF24 EK07

00FF25 D7

00FF26 D7

00FF27 D7

00FF28 FK07

D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0

D6 D5 D4 D3 D2 D1 D0

D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0

– – – – ESERR ESREC ESTRA

EK06 EK05 EK04 EK03 EK02 EK01 EK00 ETC3 ETU3 ETC2 ETU2 ETC1 ETU1 ETC0 ETU0 – – – – FTM32 FTM8 FTM2 FTM1 – – – – – FSERR FSREC FSTRA

FK06 FK05 FK04 FK03 FK02 FK01 FK00

– – – – – Serial I/F (error) interrupt enable register Serial I/F (receiving) interrupt enable register Serial I/F (transmitting) interrupt enable register K07 interrupt enable K06 interrupt enable K05 interrupt enable K04 interrupt enable K03 interrupt enable K02 interrupt enable K01 interrupt enable K00 interrupt enable PTM3 compare match interrupt enable PTM3 underflow interrupt enable PTM2 compare match interrupt enable PTM2 underflow interrupt enable PTM1 compare match interrupt enable PTM1 underflow interrupt enable PTM0 compare match interrupt enable PTM0 underflow interrupt enable – – – – Clock timer 32 Hz interrupt factor flag Clock timer 8 Hz interrupt factor flag Clock timer 2 Hz interrupt factor flag Clock timer 1 Hz interrupt factor flag – – – – – Serial I/F (error) interrupt factor flag Serial I/F (receiving) interrupt factor flag Serial I/F (transmitting) interrupt factor flag K07 interrupt factor flag K06 interrupt factor flag K05 interrupt factor flag K04 interrupt factor flag K03 interrupt factor flag K02 interrupt factor flag K01 interrupt factor flag K00 interrupt factor flag

– – – – –

Interrupt

enable

Interrupt

enable

Interrupt

enable

– – – –

(R)

Generated

(W)

Reset

– – – – –

(R)

Generated

(W)

Reset

(R)

Interrupt

factor is

generated

(W)

Reset

– – – – –

Interrupt

disable

Interrupt

disable

Interrupt

disable

– – – –

(R)

Not generated

(W)

No operation

– – – – –

(R)

Not generated

(W)

No operation

(R)

No interrupt

factor is

generated

(W)

No operation

– – – – –

R/W

0 R/W

– – – –

0 R/W

– – – – –

0 R/W

R/W

Constantly "0" when being read

22 EPSON S1C88650 TECHNICAL MANUAL

00FF29 D7

D6 D5 D4 D3 D2 D1 D0

00FF2A D7

D6 D5 D4 D3 D2 D1 D0

00FF2C

D7 D6 D5 D4 D3 D2 D1 D0

00FF2E D7

D6 D5 D4 D3 D2 D1 D0

00FF30

D7 D6 D5 D4 D3 D2 D1 D0

00FF31 D7

D6 D5 D4 D3 D2 D1 D0

FTC3 FTU3 FTC2 FTU2 FTC1 FTU1 FTC0 FTU0 – – – – PPT7 PPT6 PPT5 PPT4 ETC7 ETU7 ETC6 ETU6 ETC5 ETU5 ETC4 ETU4 FTC7 FTU7 FTC6 FTU6 FTC5 FTU5 FTC4 FTU4 MODE16_A PTNREN_A – – PTOUT0 PTRUN0 PSET0 CKSEL0 – – – – PTOUT1 PTRUN1 PSET1 CKSEL1

5 PERIPHERAL CIRCUITS AND THEIR OPERATION (I/O Memory Map)

Table 5.1.1(f) I/O Memory map (00FF29H–00FF31H)

PTM3 compare match interrupt factor flag PTM3 underflow interrupt factor flag PTM2 compare match interrupt factor flag PTM2 underflow interrupt factor flag PTM1 compare match interrupt factor flag PTM1 underflow interrupt factor flag PTM0 compare match interrupt factor flag PTM0 underflow interrupt factor flag – – – – Programmable timer 7–6 interrupt priority register Programmable timer 5–4 interrupt priority register PTM7 compare match interrupt enable PTM7 underflow interrupt enable PTM6 compare match interrupt enable PTM6 underflow interrupt enable PTM5 compare match interrupt enable PTM5 underflow interrupt enable PTM4 compare match interrupt enable PTM4 underflow interrupt enable PTM7 compare match interrupt factor flag PTM7 underflow interrupt factor flag PTM6 compare match interrupt factor flag PTM6 underflow interrupt factor flag PTM5 compare match interrupt factor flag PTM5 underflow interrupt factor flag PTM4 compare match interrupt factor flag PTM4 underflow interrupt factor flag PTM0–1 8/16-bit mode selection External clock 0 noise rejecter selection – R/W register PTM0 clock output control PTM0 Run/Stop control PTM0 preset PTM0 input clock selection – – – R/W register PTM1 clock output control PTM1 Run/Stop control PTM1 preset PTM1 input clock selection

(R) Interrupt factor is

generated

(W)

Reset

– – – –

PPT7 PPT5

1 1 0 0

Interrupt

enable

(R) Interrupt factor is

generated

(W)

Reset

16-bit x 1

Enable

– 1

Run

Preset

External clock

– – – 1

Run

Preset

External clock

No interrupt

No operation

PPT6 PPT4

1 0 1 0

No interrupt

No operation

Internal clock

No operation

Internal clock

(R)

factor is

generated

(W)

– – – –

Priority

level Level 3 Level 2 Level 1 Level 0

Interrupt

disable

(R)

factor is

generated

(W)

-bit x 2

Disable

– 0

Off

Stop

– – – 0

Off

Stop

SR R/WAddress Bit Name Function Comment10

0 R/W

– – – – 00R/W

0 R/W

0 0 – 0 0 0 0 0 – – – 0 0 0 0 0

Constantly "0" when being read

R/W

R/W R/W

"0" when being read

R/W

Reserved register

R/W R/W

"0" when being read

R/W

Constantly "0" when being read

R/W

Reserved register

R/W R/W

"0" when being read

R/W

S1C88650 TECHNICAL MANUAL EPSON 23

5 PERIPHERAL CIRCUITS AND THEIR OPERATION (I/O Memory Map)

Table 5.1.1(g) I/O Memory map (00FF32H–00FF37H)

00FF32

00FF33

00FF34

00FF35

00FF36

00FF37

D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0

RDR07 RDR06 RDR05 RDR04 RDR03 RDR02 RDR01 RDR00 RDR17 RDR16 RDR15 RDR14 RDR13 RDR12 RDR11 RDR10 CDR07 CDR06 CDR05 CDR04 CDR03 CDR02 CDR01 CDR00 CDR17 CDR16 CDR15 CDR14 CDR13 CDR12 CDR11 CDR10 PTM07 PTM06 PTM05 PTM04 PTM03 PTM02 PTM01 PTM00 PTM17 PTM16 PTM15 PTM14 PTM13 PTM12 PTM11 PTM10

PTM0 reload data D7 (MSB) PTM0 reload data D6 PTM0 reload data D5 PTM0 reload data D4 PTM0 reload data D3 PTM0 reload data D2 PTM0 reload data D1 PTM0 reload data D0 (LSB) PTM1 reload data D7 (MSB) PTM1 reload data D6 PTM1 reload data D5 PTM1 reload data D4 PTM1 reload data D3 PTM1 reload data D2 PTM1 reload data D1 PTM1 reload data D0 (LSB) PTM0 compare data D7 (MSB) PTM0 compare data D6 PTM0 compare data D5 PTM0 compare data D4 PTM0 compare data D3 PTM0 compare data D2 PTM0 compare data D1 PTM0 compare data D0 (LSB) PTM1 compare data D7 (MSB) PTM1 compare data D6 PTM1 compare data D5 PTM1 compare data D4 PTM1 compare data D3 PTM1 compare data D2 PTM1 compare data D1 PTM1 compare data D0 (LSB) PTM0 data D7 (MSB) PTM0 data D6 PTM0 data D5 PTM0 data D4 PTM0 data D3 PTM0 data D2 PTM0 data D1 PTM0 data D0 (LSB) PTM1 data D7 (MSB) PTM1 data D6 PTM1 data D5 PTM1 data D4 PTM1 data D3 PTM1 data D2 PTM1 data D1 PTM1 data D0 (LSB)

High Low

SR R/WAddress Bit Name Function Comment10

1 R/W

0 R/W

24 EPSON S1C88650 TECHNICAL MANUAL

00FF38

D7 D6 D5 D4 D3 D2 D1 D0

00FF39 D7

D6 D5 D4 D3 D2 D1 D0

00FF3A

D7 D6 D5 D4 D3 D2 D1 D0

00FF3B

D7 D6 D5 D4 D3 D2 D1 D0

00FF3C

D7 D6 D5 D4 D3 D2 D1 D0

00FF3D

D7 D6 D5 D4 D3 D2 D1 D0

MODE16_B PTNREN_B – RPTOUT2 PTOUT2 PTRUN2 PSET2 CKSEL2 – – – RPTOUT3 PTOUT3 PTRUN3 PSET3 CKSEL3 RDR27 RDR26 RDR25 RDR24 RDR23 RDR22 RDR21 RDR20 RDR37 RDR36 RDR35 RDR34 RDR33 RDR32 RDR31 RDR30 CDR27 CDR26 CDR25 CDR24 CDR23 CDR22 CDR21 CDR20 CDR37 CDR36 CDR35 CDR34 CDR33 CDR32 CDR31 CDR30

5 PERIPHERAL CIRCUITS AND THEIR OPERATION (I/O Memory Map)

Table 5.1.1(h) I/O Memory map (00FF38H–00FF3DH)

PTM2–3 8/16-bit mode selection External clock 1 noise rejecter selection – PTM2 inverted clock output control PTM2 clock output control PTM2 Run/Stop control PTM2 preset PTM2 input clock selection – – – PTM3 inverted clock output control PTM3 clock output control PTM3 Run/Stop control PTM3 preset PTM3 input clock selection PTM2 reload data D7 (MSB) PTM2 reload data D6 PTM2 reload data D5 PTM2 reload data D4 PTM2 reload data D3 PTM2 reload data D2 PTM2 reload data D1 PTM2 reload data D0 (LSB) PTM3 reload data D7 (MSB) PTM3 reload data D6 PTM3 reload data D5 PTM3 reload data D4 PTM3 reload data D3 PTM3 reload data D2 PTM3 reload data D1 PTM3 reload data D0 (LSB) PTM2 compare data D7 (MSB) PTM2 compare data D6 PTM2 compare data D5 PTM2 compare data D4 PTM2 compare data D3 PTM2 compare data D2 PTM2 compare data D1 PTM2 compare data D0 (LSB) PTM3 compare data D7 (MSB) PTM3 compare data D6 PTM3 compare data D5 PTM3 compare data D4 PTM3 compare data D3 PTM3 compare data D2 PTM3 compare data D1 PTM3 compare data D0 (LSB)

16-bit x 1

Enable

– On On

Run

Preset

External clock

–

– On On

Run

Preset

External clock

High Low

bit x 2

Disable

– Off Off

Stop

No operation

Internal clock

–

– Off Off

Stop

No operation

Internal clock

SR R/WAddress Bit Name Function Comment10

0 0 – 0 0 0 0 0 – – – 0 0 0 0 0

1 R/W

0 R/W

R/W R/W

"0" when being read

R/W R/W R/W

"0" when being read

R/W

Constantly "0" when being read

R/W R/W R/W

"0" when being read

R/W

S1C88650 TECHNICAL MANUAL EPSON 25

5 PERIPHERAL CIRCUITS AND THEIR OPERATION (I/O Memory Map)

Table 5.1.1(i) I/O Memory map (00FF3EH–00FF41H)

00FF3E

D6 D5 D4 D3 D2 D1 D0

00FF3F

D7 D6 D5 D4 D3 D2 D1 D0

00FF40 D7

D3 D2 D1 D0

00FF41 D7

D6 D5 D4 D3 D2 D1 D0

PTM27 PTM26 PTM25 PTM24 PTM23 PTM22 PTM21 PTM20 PTM37 PTM36 PTM35 PTM34 PTM33 PTM32 PTM31 PTM30 WDEN FOUT2

FOUT1

FOUT0

FOUTON WDRST TMRST TMRUN TMD7 TMD6 TMD5 TMD4 TMD3 TMD2 TMD1 TMD0

PTM2 data D7 (MSB) PTM2 data D6 PTM2 data D5 PTM2 data D4 PTM2 data D3 PTM2 data D2 PTM2 data D1 PTM2 data D0 (LSB) PTM3 data D7 (MSB) PTM3 data D6 PTM3 data D5 PTM3 data D4 PTM3 data D3 PTM3 data D2 PTM3 data D1 PTM3 data D0 (LSB) Watchdog timer enable FOUT frequency selection

FOUT2

FOUT1

FOUT0

FOUT output control Watchdog timer reset Clock timer reset Clock timer Run/Stop control Clock timer data Clock timer data Clock timer data Clock timer data Clock timer data Clock timer data Clock timer data Clock timer data

1 Hz 2 Hz 4 Hz

8 Hz 16 Hz 32 Hz 64 Hz

128 Hz

Frequency

OSC3

/ 8

OSC3

/ 4

OSC3

/ 2

f f

OSC3

/ 1

OSC1

/ 8

f f

OSC1

/ 4

OSC1

/ 2

f f

OSC1

/ 1

High Low

Enable Disable

On Reset Reset

Run

High Low

Off No operation No operation

Stop

SR R/WAddress Bit Name Function Comment10

R/W

–

R/W

Constantly "0" when being read

26 EPSON S1C88650 TECHNICAL MANUAL

00FF48 D7

D6 D5 D4

00FF49 D7

D2 D1

00FF4A D7

D6 D5 D4 D3 D2 D1 D0

00FF4B D7

D6 D5 D4 D3 D2 D1 D0

– EPR PMD SCS1

SCS0

SMD1

SMD0

ESIF – FER

PER

OER

RXTRG

RXEN TXTRG

TXEN TRXD7 TRXD6 TRXD5 TRXD4 TRXD3 TRXD2 TRXD1 TRXD0 – – – – – – STPB SDP

5 PERIPHERAL CIRCUITS AND THEIR OPERATION (I/O Memory Map)

Table 5.1.1(j) I/O Memory map (00FF48H–00FF4BH)

SR R/WAddress Bit Name Function Comment10

–– Parity enable register Parity mode selection Clock source selection

SCS1

SCS0

Clock source Programmable timer fOSC3 / 4 fOSC3 / 8 fOSC3 / 16

Serial I/F mode selection

SMD1

SMD0

Asynchronous 8-bit

Asynchronous 7-bit

Clock synchronous slave

Clock synchronous master

Mode

Serial I/F enable register – "0" when being read Serial I/F framing error flag

Serial I/F parity error flag

Serial I/F overrun error flag

Serial I/F receive trigger/status

Serial I/F receive enable Serial I/F transmit trigger/status

Serial I/F transmit enable Serial I/F transmit/Receive data D7 (MSB) Serial I/F transmit/Receive data D6 Serial I/F transmit/Receive data D5 Serial I/F transmit/Receive data D4 Serial I/F transmit/Receive data D3 Serial I/F transmit/Receive data D2 Serial I/F transmit/Receive data D1 Serial I/F transmit/Receive data D0 (LSB) – – – – – – Serial I/F stop bit selection Serial I/F data input/output permutation selection

R W R W R W R W

R W

– –

With parity

Odd

Serial I/F

– –

Error

Reset (0)

Error

Reset (0)

Error

Reset (0)

Run Trigger Enable

– – – – – –

2 bits

MSB first

Non parity

Even

I/O port

No error

No operation

No error

No operation

No error

No operation

Stop

No operation

Disable

Stop

No operation

Disable

– – – – – –

1 bit

LSB first

R/W

R/W – 0

R/W

R/W 0

R/W

X R/WHigh Low

– – – – – – 00R/W

R/W

"0" when being read Only for

asynchronous mode

In the clock synchronous slave mode, external clock is selected.

Only for

asynchronous mode

Constantly "0" when being read

S1C88650 TECHNICAL MANUAL EPSON 27

5 PERIPHERAL CIRCUITS AND THEIR OPERATION (I/O Memory Map)

Table 5.1.1(k) I/O Memory map (00FF52H–00FF60H)

00FF52 D7

00FF54 D7

00FF56 D7

00FF58 D7

00FF60 D7

D6 D5 D4 D3 D2 D1 D0

D3 D2

D6 D5 D4 D3 D2 D1 D0

KCP07 KCP06 KCP05 KCP04 KCP03 KCP02 KCP01 KCP00 K07D K06D K05D K04D K03D K02D K01D K00D PULK07 PULK06 PULK05 PULK04 PULK03 PULK02 PULK01 PULK00 – CTK02H

CTK01H

CTK00H

– CTK02L

CTK01L

CTK00L

IOC07 IOC06 IOC05 IOC04 IOC03 IOC02 IOC01 IOC00

K07 input comparison register K06 input comparison register K05 input comparison register K04 input comparison register K03 input comparison register K02 input comparison register K01 input comparison register K00 input comparison register K07 input port data K06 input port data K05 input port data K04 input port data K03 input port data K02 input port data K01 input port data K00 input port data K07 pull-up control register K06 pull-up control register K05 pull-up control register K04 pull-up control register K03 pull-up control register K02 pull-up control register K01 pull-up control register K00 pull-up control register – K04–K07 port chattering-eliminate setup

(Input level check time)

CTK02H

1 1 1 1 0 0 0 0

CTK01H

1 1 0 0 1 1 0 0

CTK00H

1 0 1 0 1 0 1 0

Check time

[sec]

OSC3

4/f 2/f

OSC3

1/f

OSC3

4096/f 2048/f

512/f

OSC1

128/f

OSC1

None – K00–K03 port chattering-eliminate setup

(Input level check time)

CTK02L

1 1 1 1 0 0 0 0

CTK01L

1 1 0 0 1 1 0 0

CTK00L

1 0 1 0 1 0 1 0

Check time

[sec]

4/f

OSC3

2/f

OSC3

1/f

OSC3

4096/f 2048/f

512/f

OSC1

128/f

OSC1

None P07 I/O control register P06 I/O control register P05 I/O control register P04 I/O control register P03 I/O control register P02 I/O control register P01 I/O control register P00 I/O control register

Interrupt

generated

at falling

edge

High level

input

On Off

OSC1 OSC1

Output Input

SR R/WAddress Bit Name Function Comment10

Interrupt

generated

at rising

edge

Low level

input

1 R/W

–R

1 R/W

–

"0" when being read

R/W

"0" when being read

R/W

0 R/W

28 EPSON S1C88650 TECHNICAL MANUAL

00FF61 D7

D6 D5 D4 D3 D2 D1 D0

00FF62 D7

D6 D5 D4 D3 D2 D1 D0

00FF63 D7

D6 D5 D4 D3 D2 D1 D0

00FF64 D7

D6 D5 D4 D3 D2 D1 D0

00FF65 D7

D6 D5 D4 D3 D2 D1 D0

00FF70 D7

D6 D5 D4 D3 D2 D1 D0

IOC17 IOC16 IOC15 IOC14 IOC13 IOC12 IOC11 IOC10 P07D P06D P05D P04D P03D P02D P01D P00D P17D P16D P15D P14D P13D P12D P11D P10D PULP07 PULP06 PULP05 PULP04 PULP03 PULP02 PULP01 PULP00 PULP17 PULP16 PULP15 PULP14 PULP13 PULP12 PULP11 PULP10 – – – – HZR1H HZR1L HZR0H HZR0L

5 PERIPHERAL CIRCUITS AND THEIR OPERATION (I/O Memory Map)

Table 5.1.1(l) I/O Memory map (00FF61H–00FF70H)

P17 I/O control register P16 I/O control register P15 I/O control register P14 I/O control register P13 I/O control register P12 I/O control register P11 I/O control register P10 I/O control register P07 I/O port data P06 I/O port data P05 I/O port data P04 I/O port data P03 I/O port data P02 I/O port data P01 I/O port data P00 I/O port data P17 I/O port data P16 I/O port data P15 I/O port data P14 I/O port data P13 I/O port data P12 I/O port data P11 I/O port data P10 I/O port data P07 pull-up control register P06 pull-up control register P05 pull-up control register P04 pull-up control register P03 pull-up control register P02 pull-up control register P01 pull-up control register P00 pull-up control register P17 pull-up control register P16 pull-up control register P15 pull-up control register P14 pull-up control register P13 pull-up control register P12 pull-up control register P11 pull-up control register P10 pull-up control register R/W register R/W register R/W register R/W register R14–R17 high impedance control R10–R13 high impedance control R04–R07 high impedance control R00–R03 high impedance control

Output Input

High Low

On Off

1 1 1 1

High

impedance

0 0 0 0

Complementary

SR R/WAddress Bit Name Function Comment10

0 R/W

1 R/W

0 0 0 0

Reserved register

R/W R/W R/W R/W

R/W

S1C88650 TECHNICAL MANUAL EPSON 29

5 PERIPHERAL CIRCUITS AND THEIR OPERATION (I/O Memory Map)

Table 5.1.1(m) I/O Memory map (00FF71H–00FF76H)

D6 D5 D4 D3 D2 D1 D0

00FF72 –

D7 D6 D5 D4 D3 D2 D1 D0

00FF73 D7

D6 D5 D4 D3 D2 D1 D0

00FF74 D7

D6 D5 D4 D3 D2 D1 D0

00FF75 D7

D6 D5 D4 D3 D2 D1 D0

00FF76 D7

D6 D5 D4 D3 D2 D1 D0

– – HZR25 HZR24 HZR23 HZR22 HZR21 HZR20

– – – HZR33 HZR32 HZR31 HZR30 R07D R06D R05D R04D R03D R02D R01D R00D R17D R16D R15D R14D R13D R12D R11D R10D – – R25D R24D R23D R22D R21D R20D – – – – R33D R32D R31D R30D

R/W register R/W register R25 high impedance control R24 high impedance control R23 high impedance control R22 high impedance control R21 high impedance control R20 high impedance control R/W register R/W register R/W register R/W register R33 high impedance control R32 high impedance control R31 high impedance control R30 high impedance control R07 output port data R06 output port data R05 output port data R04 output port data R03 output port data R02 output port data R01 output port data R00 output port data R17 output port data R16 output port data R15 output port data R14 output port data R13 output port data R12 output port data R11 output port data R10 output port data

R/W register R25 output port data R24 output port data R23 output port data R22 output port data R21 output port data R20 output port data R/W register R/W register R/W register R/W register R33 output port data R32 output port data R31 output port data R30 output port data

High

impedance

High

impedance

High Low

High

SR R/WAddress Bit Name Function Comment10

R/W R/W

R/W

R/W R/W R/W R/W

R/W

Reserved register00FF71 D7

Reserved register0

1 1

Comple-

mentary

1 1 1 1

Comple-

mentary

1 R/W

1 R/WHigh Low

R/W R/W

R/W

R/W R/W R/W R/W

R/W

Reserved registerR/W register

Reserved register0

1 1

Low

1 1 1 1

Low

30 EPSON S1C88650 TECHNICAL MANUAL

00FFB0

D7 D6 D5 D4 D3 D2 D1 D0

00FFB1 D7

D6 D5 D4 D3 D2 D1 D0

00FFB2

D7 D6 D5 D4 D3 D2 D1 D0

00FFB3

D7 D6 D5 D4 D3 D2 D1 D0

00FFB4

D7 D6 D5 D4 D3 D2 D1 D0

00FFB5

D7 D6 D5 D4 D3 D2 D1 D0

MODE16_C PTNREN_C – – – PTRUN4 PSET4 CKSEL4 – – – – – PTRUN5 PSET5 CKSEL5 RDR47 RDR46 RDR45 RDR44 RDR43 RDR42 RDR41 RDR40 RDR57 RDR56 RDR55 RDR54 RDR53 RDR52 RDR51 RDR50 CDR47 CDR46 CDR45 CDR44 CDR43 CDR42 CDR41 CDR40 CDR57 CDR56 CDR55 CDR54 CDR53 CDR52 CDR51 CDR50

PTM4–5 8/16-bit mode selection External clock 2 noise rejecter selection – R/W register R/W register PTM4 Run/Stop control PTM4 preset PTM4 input clock selection – – – R/W register R/W register PTM5 Run/Stop control PTM5 preset PTM5 input clock selection PTM4 reload data D7 (MSB) PTM4 reload data D6 PTM4 reload data D5 PTM4 reload data D4 PTM4 reload data D3 PTM4 reload data D2 PTM4 reload data D1 PTM4 reload data D0 (LSB) PTM5 reload data D7 (MSB) PTM5 reload data D6 PTM5 reload data D5 PTM5 reload data D4 PTM5 reload data D3 PTM5 reload data D2 PTM5 reload data D1 PTM5 reload data D0 (LSB) PTM4 compare data D7 (MSB) PTM4 compare data D6 PTM4 compare data D5 PTM4 compare data D4 PTM4 compare data D3 PTM4 compare data D2 PTM4 compare data D1 PTM4 compare data D0 (LSB) PTM5 compare data D7 (MSB) PTM5 compare data D6 PTM5 compare data D5 PTM5 compare data D4 PTM5 compare data D3 PTM5 compare data D2 PTM5 compare data D1 PTM5 compare data D0 (LSB)

5 PERIPHERAL CIRCUITS AND THEIR OPERATION (I/O Memory Map)

Table 5.1.1(n) I/O Memory map (00FFB0H–00FFB5H)

16-bit x 1

Enable

– 1 1

Run

Preset

External clock

– – – 1 1

Run

Preset

External clock

High Low

bit x 2

Disable

– 0 0

Stop

No operation

Internal clock

– – – 0 0

Stop

No operation

Internal clock

SR R/WAddress Bit Name Function Comment10

0 0 – 0 0 0 0 0 – – – 0 0 0 0 0

1 R/W

0 R/W

R/W R/W

"0" when being read

R/W

Reserved register

R/W R/W

"0" when being read

R/W

Constantly "0" when being read

R/W

Reserved register

R/W R/W

"0" when being read

R/W

S1C88650 TECHNICAL MANUAL EPSON 31

5 PERIPHERAL CIRCUITS AND THEIR OPERATION (I/O Memory Map)

Table 5.1.1(o) I/O Memory map (00FFB6H–00FFBBH)

00FFB6

D6 D5 D4 D3 D2 D1 D0

00FFB7

D7 D6 D5 D4 D3 D2 D1 D0

00FFB8

D7 D6 D5 D4 D3 D2 D1 D0

00FFB9 D7

D6 D5 D4 D3 D2 D1 D0

00FFBA

D7 D6 D5 D4 D3 D2 D1 D0

00FFBB

D7 D6 D5 D4 D3 D2 D1 D0

PTM47 PTM46 PTM45 PTM44 PTM43 PTM42 PTM41 PTM40 PTM57 PTM56 PTM55 PTM54 PTM53 PTM52 PTM51 PTM50 MODE16_D PTNREN_D – – – PTRUN6 PSET6 CKSEL6 – – – – – PTRUN7 PSET7 CKSEL7 RDR67 RDR66 RDR65 RDR64 RDR63 RDR62 RDR61 RDR60 RDR77 RDR76 RDR75 RDR74 RDR73 RDR72 RDR71 RDR70

PTM4 data D7 (MSB) PTM4 data D6 PTM4 data D5 PTM4 data D4 PTM4 data D3 PTM4 data D2 PTM4 data D1 PTM4 data D0 (LSB) PTM5 data D7 (MSB) PTM5 data D6 PTM5 data D5 PTM5 data D4 PTM5 data D3 PTM5 data D2 PTM5 data D1 PTM5 data D0 (LSB) PTM6–7 8/16-bit mode selection External clock 3 noise rejecter selection – R/W register R/W register PTM6 Run/Stop control PTM6 preset PTM6 input clock selection – – – R/W register R/W register PTM7 Run/Stop control PTM7 preset PTM7 input clock selection PTM6 reload data D7 (MSB) PTM6 reload data D6 PTM6 reload data D5 PTM6 reload data D4 PTM6 reload data D3 PTM6 reload data D2 PTM6 reload data D1 PTM6 reload data D0 (LSB) PTM7 reload data D7 (MSB) PTM7 reload data D6 PTM7 reload data D5 PTM7 reload data D4 PTM7 reload data D3 PTM7 reload data D2 PTM7 reload data D1 PTM7 reload data D0 (LSB)

High Low

16-bit x 1

Enable

Run

Preset

External clock

Run

Preset

External clock

High Low

– 1 1

– – – 1 1

bit x 2

Disable

– 0 0

Stop

No operation

Internal clock

– – – 0 0

Stop

No operation

Internal clock

SR R/WAddress Bit Name Function Comment10

R/W

R/W – 0

R/W 0

R/W – – – 0

R/W 0

R/W

1 R/W

"0" when being read Reserved register

"0" when being read

Constantly "0" when being read

Reserved register

"0" when being read

32 EPSON S1C88650 TECHNICAL MANUAL

00FFBC

00FFBD

00FFBE

00FFBF

D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0

CDR67 CDR66 CDR65 CDR64 CDR63 CDR62 CDR61 CDR60 CDR77 CDR76 CDR75 CDR74 CDR73 CDR72 CDR71 CDR70 PTM67 PTM66 PTM65 PTM64 PTM63 PTM62 PTM61 PTM60 PTM77 PTM76 PTM75 PTM74 PTM73 PTM72 PTM71 PTM70

5 PERIPHERAL CIRCUITS AND THEIR OPERATION (I/O Memory Map)

Table 5.1.1(p) I/O Memory map (00FFBCH–00FFBFH)

PTM6 compare data D7 (MSB) PTM6 compare data D6 PTM6 compare data D5 PTM6 compare data D4 PTM6 compare data D3 PTM6 compare data D2 PTM6 compare data D1 PTM6 compare data D0 (LSB) PTM7 compare data D7 (MSB) PTM7 compare data D6 PTM7 compare data D5 PTM7 compare data D4 PTM7 compare data D3 PTM7 compare data D2 PTM7 compare data D1 PTM7 compare data D0 (LSB) PTM6 data D7 (MSB) PTM6 data D6 PTM6 data D5 PTM6 data D4 PTM6 data D3 PTM6 data D2 PTM6 data D1 PTM6 data D0 (LSB) PTM7 data D7 (MSB) PTM7 data D6 PTM7 data D5 PTM7 data D4 PTM7 data D3 PTM7 data D2 PTM7 data D1 PTM7 data D0 (LSB)

SR R/WAddress Bit Name Function Comment10

0R/WHigh Low

1RHigh Low

S1C88650 TECHNICAL MANUAL EPSON 33

5 PERIPHERAL CIRCUITS AND THEIR OPERATION (System Controller and Bus Control)

5.2

System Controller and Bus Control

The system controller is a management unit which sets such items as the bus mode in accordance with memory system configuration factors. For the purposes of controlling the system, the following settings can be performed in software:

(1) Bus and CPU mode settings (2)

Chip enable (CE) signal output settings

____

(3) WAIT state settings for external memory (4) Page address setting of the stack pointer

Table 5.2.1.1 Bus and CPU mode settings

MCU/MPU

terminal

1 (MCU mode)

0 (MPU mode)

Setting value

BUSMOD

1 1 0 0 1 1 0 0

CPUMOD

1 0 1 0 1 0 1 0

Bus mode

Expansion

Single chip

Expansion

Table 5.2.1.2 I/O terminal settings

Terminal

R00 R01 R02 R03 R04 R05 R06 R07 R10 R11 R12 R13 R14 R15 R16 R17 R20 R21 R22 R23 R24 R25 P00 P01 P02 P03 P04 P05 P06 P07

Single chip

Output port R00 Output port R01 Output port R02 Output port R03 Output port R04 Output port R05 Output port R06 Output port R07 Output port R10 Output port R11 Output port R12 Output port R13 Output port R14 Output port R15 Output port R16 Output port R17 Output port R20 Output port R21 Output port R22 Output port R23 Output port R24 Output port R25

I/O port P00 I/O port P01 I/O port P02 I/O port P03 I/O port P04 I/O port P05 I/O port P06 I/O port P07

Bus mode

Expansion

Address bus A0 Address bus A1 Address bus A2 Address bus A3 Address bus A4 Address bus A5 Address bus A6 Address bus A7 Address bus A8

Address bus A9 Address bus A10 Address bus A11 Address bus A12 Address bus A13 Address bus A14 Address bus A15 Address bus A16 Address bus A17 Address bus A18 Address bus A19

RD signal

WR signal Data bus D0 Data bus D1 Data bus D2 Data bus D3 Data bus D4 Data bus D5 Data bus D6 Data bus D7

Below is a description of the how these settings are to be made.

5.2.1 Bus mode and CPU mode settings

The S1C88650 has two bus modes and two CPU modes and the software must select appropriate modes according to the external memory size connected to the S1C88650.

As shown in Table 5.2.1.1, these modes are specified usng the registers BUSMOD and CPUMOD.

CPU mode

Maximum Minimum Maximum Minimum Maximum Minimum Maximum Minimum

Configuration of external memory

ROM+RAM>64K bytes (Program≥64K bytes) ROM+RAM>64K bytes (Program<64K bytes) None (Program≥64K bytes) None (Program<64K bytes) ROM+RAM>64K bytes (Program≥64K bytes) ROM+RAM>64K bytes (Program<64K bytes) ROM+RAM>64K bytes (Program≥64K bytes) ROM+RAM>64K bytes (Program<64K bytes)

The function of I/O terminals is set as shown in Table 5.2.1.2 in accordance with mode selection. At initial reset, the bus mode (CPU mode) is set as explained below.

• In MCU mode:

At initial reset, the S1C88650 is set in single chip mode (minimum). Accordingly, in MCU mode, even if a memory has been externally expanded, the system is activated by the program written to internal ROM. In the system with externally expanded memory, perform the applicable bus mode settings during the initialization routine originating in internal ROM.

• In MPU mode:

At initial reset, the S1C88650 is set in expansion mode (minimum). Therefore, the internal ROM will be disabled.

_____

5.2.2 Address decoder (CE output) settings

As explained in Section 3.6.4, the S1C88650 is equipped with address decoders that can output a maximum of three chip enable signals (CE0–CE2) to external devices.

_____ _____

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5 PERIPHERAL CIRCUITS AND THEIR OPERATION (System Controller and Bus Control)

Table 5.2.2.1 Address settings of CE0–CE2

CE signal

CE0 CE1 CE2

The output terminals and output circuits for CE0–

_____

MCU mode MPU mode

300000H–3FFFFFH 100000H–1FFFFFH 200000H–2FFFFFH

Address range (expansion mode)

_____

CE2 are shared with output ports R30–R32. At initial reset, they are set as output port terminals. For this reason, when operating in expansion mode,

_____

the ports to be used as CE signal output terminals must be set as such. This setting is performed through software which writes "1" to registers CE0–CE2 corresponding the

____

CE signals to be used. Table 5.2.2.1 shows the address range assigned to

____

the three chip enable (CE) signals. The arrangement of memory space for external devices does not necessarily have to be continuous from a subordinate address and any of the chip enable signals can be used to assign areas in memory. However, in the MPU mode, program memory must be assigned to CE0.

____

_____

The CE signals are only output when the appointed external memory area is accessed and are not output when internal memory is accessed.

5.2.3 WAIT state settings

In order to insure accessing of external low speed devices during high speed operations, the S1C88650 is equipped with a WAIT function which prolongs access time. The number of wait states inserted can be selected from a choice of eight as shown in Table 5.2.3.1 by means of registers WT0–WT2.

Table 5.2.3.1 Setting the number of WAIT states

WT2 Number of inserted states

* The length of one state is a 1/2 clock cycle.

WAIT states set in software are inserted between bus cycle states T3–T4. Note, however, that WAIT states cannot be inserted when an internal register and internal memory are being accessed and when operating with the OSC1 oscillation circuit (see "5.4 Oscillation Circuits").

WT1

1 1 1 1 0 0 0 0

WT0

1 1 0 0 1 1 0 0

1 0 1 0 1 0 1 0

14 12 10

8 6 4 2

No wait

_____ _____

000000H–00D7FFH, 010000H–0FFFFFH

100000H–1FFFFFH 200000H–2FFFFFH

Consequently, WAIT state settings in single chip mode are meaningless. With regard to WAIT insertion timing, see Section

3.6.5, "WAIT control".

5.2.4 Setting the bus authority release request signal

With systems performing DMA transfer, the bus authority release request signal (BREQ) input terminal and acknowledge signal (BACK) output terminal have to be set.

________

The BREQ input terminal is shared with input port

________

terminal K03 and the BACK output terminal with output port terminal R33. At initial reset, these terminal facilities are set as input port terminal and output port terminal, respectively. The terminals can be altered to function as BREQ/BACK terminals by writing a "1" to register EBR.

For details on bus authority release, see "3.6.6 Bus authority release state" and "S1C88 Core CPU Manual".

________

________ ________

5.2.5 Stack page setting

Although the stack area used to evacuate registers during subroutine calls can be arbitrarily moved to any area in data RAM using the stack pointer SP, its page address is set in registers SPP0–SPP7 in I/O memory. At initial reset, SPP0–SPP7 are set to "00H" (page 0).

Since the internal RAM is arranged on page 0 (00D800H–00F7FFH), the stack area in single chip mode is inevitably located in page 0. In order to place the stack area at the final address in internal RAM, the stack pointer SP is placed at an initial setting of "F800H". (SP is pre-decremented.)

In the expansion mode, to place the stack in external expanded RAM, set a corresponding page to SPP0–SPP7. The page addresses to which SPP0– SPP7 can be set are 00H–27H and must be within a RAM area.

* A page is each recurrent 64K division of data

memory beginning at address zero.

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5 PERIPHERAL CIRCUITS AND THEIR OPERATION (System Controller and Bus Control)

5.2.6 Control of system controller

Table 5.2.6.1 shows the control bits for the system controller.

Table 5.2.6.1 System controller control bits

SR R/W10Address Bit Name Function Comment

00FF00

(MCU)D7D6

D5 D4 D3 D2 D1 D0

00FF00

(MPU)D7D6

D5 D4 D3 D2 D1 D0

00FF01 D7

D6 D5 D4 D3 D2 D1 D0

00FF02 D7

D3 D2 D1 D0

Note:

All the interrupts including NMI are disabled, until you write the optional value into both the "00FF00H" and "00FF01H" addresses.

BUSMOD CPUMOD – – – CE2 CE1 CE0 BUSMOD CPUMOD – – – CE2 CE1 CE0 SPP7 SPP6 SPP5 SPP4 SPP3 SPP2 SPP1 SPP0 EBR

WT2

WT1

WT0

CLKCHG SOSC3 – –

Bus mode CPU mode R/W register R/W register R/W register CE2 (R32) CE1 (R31) CE0 (R30)

CE signal output Enable/Disable

CE signal output

Enable:

DC (R3x) output

Disable: Bus mode CPU mode R/W register R/W register R/W register CE2 (R32) CE1 (R31) CE0 (R30)

CE signal output Enable/Disable

Enable:

CE signal output

Disable:

DC (R3x) output

Stack pointer page address

< SP page allocatable address >

• Single chip mode:

• Expansion mode:

only 0 page 0–27H page

Bus release enable register (K03 and R33 terminal specification) Wait control register

WT2

WT1 1 1 1 1 0 0 0 0

WT0 1 1 0 0 1 1 0 0

1 0 1 0 1 0 1 0

CPU operating clock switch OSC3 oscillation On/Off control R/W register R/W register

____

(MSB)

(LSB)

K03 R33

Number

of state

14 12 10

8 6 4 2

No wait

Expansion Maximum

1 1

1 CE2 enable CE1 enable CE0 enable

Expansion Maximum

1 CE2 enable CE1 enable CE0 enable

BREQ BACK

OSC3

Single chip

Minimum

CE2 disable CE1 disable CE0 disable

Minimum

CE2 disable CE1 disable CE0 disable

Input port

Output port

OSC1

Off

0 0 0

0 0 0 1

–

0 0

0 0 1 0

0 0

1 1

R/W R/W

Reserved register

R/W R/W R/W

In Single chip mode,

R/W

these setting are fixed

R/W

at DC output.

R/W

Expansion mode only

R/W R/W

Reserved register

R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

R/W

R/W R/W

Reserved register

R/W R/W

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5 PERIPHERAL CIRCUITS AND THEIR OPERATION (System Controller and Bus Control)

BUSMOD, CPUMOD: 00FF00H•D7, D6

Bus mode and CPU mode are set as shown in Table

5.2.6.2.

Table 5.2.6.2 Bus mode and CPU mode settings

Setting valueMCU/MPU

terminal

1 (MCU mode)

0 (MPU mode)

BUSMOD

1 1 0 0 1 1 0 0

CPUMOD

The single chip mode configuration is only possible when this IC is used in the MCU mode. The single chip mode setting is incompatible with the MPU mode, since this mode does not utilize internal ROM. At initial reset, in the MCU mode the unit is set to single chip (minimum) mode and in the MPU mode the expansion (minimum) mode is used to select the applicable mode.

CE0–CE2: 00FF00H•D0–D2

_____

Sets the CE output terminals being used.

When "1" is written: When "0" is written: Reading: Valid

____

CE output is enabled when a "1" is written to registers CE0–CE2 which correspond to the CE output being used. A "0" written to any of the

____

registers disables CE signal output from that terminal and it reverts to its alternate function as an output port terminal (R30–R32). At initial reset, register CE0 is set to "0" in the MCU mode and in the MPU mode, "1" is set in the register. Registers CE1–CE2 are always set to "0" regardless of the MCU/MPU mode setting.

Note: To avoid a malfunction from an interrupt

generated before the bus configuration is initialized, all interrupts including NMI are masked until you write an optional value into address "00FF00H".

Bus mode

Expansion

1 0

Single

chip

Expansion

1 0 1 0

_____

CE output enable

_____

CPU mode

CE output disable

_____

Maximum Minimum Maximum Minimum Maximum Minimum Maximum Minimum

____

Since a carry and borrow from/to the stack pointer SP is not reflected in register SPP, the upper limit on continuous use of the stack area is 64K bytes. At initial reset, this register is set to "00H" (page 0).

Note: To avoid a malfunction from an interrupt

generated before the bus configuration is

_____

initialized, all interrupts including NMI are disabled, until you write an optional value into "00FF01H" address. Furthermore, to avoid generating an interrupt while the stack

_____

area is being set, all interrupts including NMI are disabled in one instruction execution period after writing to address "00FF01H".

WT0–WT2: 00FF02H•D4–D6

How WAIT state settings are performed. The number of WAIT states to be inserted based on register settings is as shown in Table 5.2.6.3.

Table 5.2.6.3 Setting WAIT states

WT2 Number of inserted states

* The length of one state is a 1/2 clock cycle.

At initial reset, this register is set to "0" (no wait).

EBR: 00FF02H•D7

Sets the BREQ/BACK terminals function.

When "1" is written: When "0" is written: Reading: Valid

How BREQ and BACK terminal functions are set. Writing "1" to EBR enables BREQ/BACK input/ output. Writing "0" sets the BREQ terminal as input port terminal K03 and the BACK terminal as output port terminal R33. At initial reset, EBR is set to "0" (BREQ/BACK disabled).

WT1

1 1 1 1 0 0 0 0

________ ________

1 1 0 0 1 1 0 0

________ ________

WT0

1 0 1 0 1 0 1 0

________ ________

BREQ/BACK enabled

________ ________

No wait

BREQ/BACK disabled

________ ________

________

________ ________

14 12 10

8 6 4 2

SPP0–SPP7: 00FF01H

Sets the page address of stack area. In single chip mode, set page address to "00H". In expansion mode, it can be set to any value within the range "00H"–"27H".

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5 PERIPHERAL CIRCUITS AND THEIR OPERATION (System Controller and Bus Control)

5.2.7 Programming notes

(1)

All the interrupts including NMI are masked,

______

until you write the optional value into both the "00FF00H" and "00FF01H" addresses. Consequently, even if you do not change the content of this address (You use the initial value, as is.), you should still be sure to perform the writing operation using the initialization routine.

(2) When setting stack fields, including page

addresses as well, you should write them in the order of the register SPP ("00FF01H") and the stack pointer SP.

Example: When setting the "178000H" address

LD EP, #00H LD HL, #0FF01H LD [HL], #17H LD SP, #8000H

During this period the interrupts (including

_______

NMI) are masked.

38 EPSON S1C88650 TECHNICAL MANUAL

5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Watchdog Timer)

5.3 Watchdog Timer

5.3.1 Configuration of watchdog timer

The S1C88650 is equipped with a watchdog timer driven by OSC1 as source oscillation. The watchdog timer must be reset periodically by software, and if reset does not take place within the selected period, a non-maskable interrupt signal is generated and output to the CPU. The watchdog timer starts operating after initial reset, however, it can be stopped by the software.

_______

The NMI generation cycle by the watchdog timer can be selected by mask option.

Watchdog timer NMI generation cycle

■■ 32768/fOSC1

(0.75–1-sec cycle when fOSC1 = 32 kHz)

■■ 65536/fOSC1

(1.5–2-sec cycle when fOSC1 = 32 kHz)

■■ 131072/fOSC1

(3–4-sec cycle when fOSC1 = 32 kHz)

■■ 262144/fOSC1

(6–8-sec cycle when fOSC1 = 32 kHz)

Figure 5.3.1.1 is a block diagram of the watchdog timer.

By running watchdog timer reset during the main routine of the program, it is possible to detect program runaway as if watchdog timer processing had not been applied.

_____

Normally, this routine is integrated at points that are regularly being processed.

The watchdog timer continues to operate during HALT and when HALT state is continuous for longer than the selected period, the CPU starts exception processing. During SLEEP, the watchdog timer is stopped.

Note: The NMI generation cycles in the watchdog

timer mask option list represent maximum values. A maximum minus (<selected optional cycle> / 4) seconds of error occurs depending on the watchdog timer reset timing. For example, when 131072/f

OSC1

is selected by mask option, the actual NMI generation cycle is within the range of 98304/f

OSC1

to 131072/f

OSC1

seconds.

5.3.2 Interrupt function

In cases where the watchdog timer is not periodically reset in software, the watchdog timer outputs an interrupt signal to the CPU's NMI (level 4) input. Unmaskable and taking priority over other interrupts, this interrupt triggers the generation of exception processing. See the "S1C88 Core CPU Manual" for more details on NMI exception processing. This exception processing vector is set at 000004H.

______

OSC1 oscillation circuit

OSC1

WDEN

WDRST

Mask option

1/16384

Divider

1/32768 1/65536

1/131072

Watchdog timer enable signal

Watchdog timer reset signal

Fig. 5.3.1.1 Block diagram of watchdog timer

Watchdog timer

1/4

Non-maskable interrupt (NMI)

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5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Watchdog Timer)

5.3.3 Control of watchdog timer

Table 5.3.3.1 shows the control bits for the watchdog timer.

Table 5.3.3.1 Watchdog timer control bits

00FF40 D7

D3 D2 D1 D0

WDEN FOUT2

FOUT1

FOUT0

FOUTON WDRST TMRST TMRUN

Watchdog timer enable FOUT frequency selection

FOUT2

FOUT1

FOUT0

FOUT output control Watchdog timer reset Clock timer reset Clock timer Run/Stop control

Enable

Frequency

fOSC1 / 1 fOSC1 / 2 fOSC1 / 4 fOSC1 / 8 fOSC3 / 1 fOSC3 / 2 fOSC3 / 4 fOSC3 / 8

On Reset Reset

Run

Disable

Off No operation No operation

Stop

SR R/WAddress Bit Name Function Comment10

1 0

0 – – 0

R/W R/W

R/W

Constantly "0" when

W W

being read

R/W

WDEN: 00FF40H•D7

Selects whether the watchdog timer is used (enabled) or not (disabled).

When "1" is written: Enabled When "0" is written: Disabled Reading: Valid

When "1" is written to the WDEN register, the watchdog timer starts count operation. When "0" is written, the watchdog timer does not count and

______

does not generate the interrupt (NMI). At initial reset, this register is set to "1".

WDRST: 00FF40H•D2

Resets the watchdog timer.

When "1" is written: Watchdog timer is reset When "0" is written: No operation Reading: Constantly "0"

By writing "1" to WDRST, the watchdog timer is reset, after which it is immediately restarted. Writing "0" will mean no operation. Since WDRST is for writing only, it is constantly set to "0" during readout.

5.3.4 Programming notes

(1) When the watchdog timer is being used, the

software must reset it within the cycles selected by mask option.

(2) Do not execute the SLP instruction for 2 msec

(3) Because the watchdog timer is set in operation

(4)

______

after a NMI interrupt has occurred (when fOSC1 is 32.768 kHz).

state by initial reset, set the watchdog timer to disabled state (not used) before generating an interrupt (NMI) if it is not used.

______

The NMI generation cycles in the watchdog timer mask option list represent maximum values. A maximum minus (<selected optional cycle> / 4) seconds of error occurs depending on the watchdog timer reset timing. For example, when 131072/fOSC1 is selected by

______

mask option, the actual NMI generation cycle is within the range of 98304/fOSC1 to 131072/fOSC1 seconds.

40 EPSON S1C88650 TECHNICAL MANUAL

5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Oscillation Circuits)

5.4 Oscillation Circuits

5.4.1 Configuration of oscillation circuits

The S1C88650 is twin clock system with two internal oscillation circuits (OSC1 and OSC3). The OSC3 oscillation circuit generates the mainclock (Max. 8.2 MHz) to run the CPU and some peripheral circuits in high speed, and the OSC1 oscillation circuit generates the sub-clock (Typ.

32.768 kHz) for low-power operation. Figure 5.4.1.1 shows the configuration of the oscillation circuit.

OSC1

oscillation circuit

OSC3

oscillation circuit

SLEEP

status

SOSC3

Fig. 5.4.1.1 Configuration of oscillation circuits

At initial reset, OSC3 oscillation circuit is selected for the CPU operating clock. ON/OFF switching of the OSC3 oscillation circuit and switching of the system clock between OSC3 and OSC1 are controlled in software. OSC3 circuit is utilized when high speed operation of the CPU and some peripheral circuits become necessary. Otherwise, OSC1 should be used to generate the operating clock and OSC3 circuit placed in a stopped state in order to reduce current consumption.

5.4.2 Mask option

OSC1 oscillation circuit

■■ Crystal oscillation circuit

■■ CR oscillation circuit

OSC3 oscillation circuit

■■ Crystal oscillation circuit

■■ Ceramic oscillation circuit

■■ CR oscillation circuit

In terms of the oscillation circuit types for OSC1, either crystal oscillation or CR oscillation can be selected with the mask option. In terms of the oscillation circuit types for OSC3, either crystal oscillation, ceramic oscillation or CR oscillation can be selected with the mask option, in the same way as OSC1.

OSC1

OSC3

Oscillation circuit control signal

)

Prescaler

Clock

switch

)

CLKCHG

To peripheral circuit

To CPU (CLK) To some peripheral

circuit

CPU clock selection signal

5.4.3 OSC1 oscillation circuit

The OSC1 oscillation circuit generates the 32.768 kHz (Typ.) system clock which is utilized during low speed operation (low power mode) of the CPU and peripheral circuits. Furthermore, even when OSC3 is utilized as the system clock, OSC1 continues to generate the source clock for the clock timer and stopwatch timer. This oscillation circuit stops when the SLP instruction is executed. In terms of the oscillation circuit types, either crystal oscillation or CR oscillation can be selected with the mask option. Figure 5.4.3.1 shows the configuration of the OSC1 oscillation circuit.

SLEEP status

OSC1

X'tal1

OSC2

(1) Crystal oscillation circuit

OSC1

RCR1

OSC2

(2) CR oscillation circuit

Fig. 5.4.3.1 OSC1 oscillation circuit

When crystal oscillation is selected, a crystal oscillation circuit can be easily formed by connecting a crystal oscillator X'tal1 (Typ. 32.768 kHz) between the OSC1 and OSC2 terminals along with a trimmer capacitor CG1 (5–25 pF) between the OSC1 terminal and VSS. When CR oscillation is selected, the CR oscillation circuit (Max. 200 kHz) is formed merely by connecting a resistor (RCR1) between OSC1 and OSC2 terminals.

OSC1

SLEEP status

OSC1

Note: Do not select CR oscillation for the OSC1

oscillation circuit when crystal oscillation is selected for the OSC3 oscillation circuit. When such a selection is made, the OSC3 clock may be supplied to the internal circuits even though the OSC3 oscillation has not stabilized.

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5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Oscillation Circuits)

5.4.4 OSC3 oscillation circuit

The OSC3 oscillation circuit generates the system clock when the CPU and some peripheral circuits are in high speed operation. This oscillation circuit stops when the SLP instruction is executed, or the SOSC3 register is set to "0". In terms of oscillation circuit types, any one of crystal oscillation, ceramic oscillation or CR oscillation can be selected with the mask option. Figure 5.4.4.1 shows the configuration of the OSC3 oscillation circuit.

OSC3

ON ON OSC3

OSC3

Oscillation circuit control signal

SLEEP status

fOSC3

Oscillation circuit control signal

SLEEP status

Program Execution Status

RESET

CLKCHG=0

CLKCHG=1

Low speed operation

X'tal 2

OSC4

or Ceramic

(1) Crystal/Ceramic oscillation circuit

OSC3

RCR3

OSC4

(2) CR oscillation circuit

Fig. 5.4.4.1 OSC3 oscillation circuit

When crystal or ceramic oscillation circuit is selected, the crystal or ceramic oscillation circuit (Max. 8.2 MHz) are formed by connecting either a crystal oscillator (X'tal2) or a combination of ceramic oscillator (Ceramic) and feedback resistor (Rf) between OSC3 and OSC4 terminals and connecting two capacitors (C

G2, CD2) between the

OSC3 terminal and VSS, and between the OSC4 terminal and VSS, respectively.

High speed operation

OSC1 OSC3 CPU clock

When CR oscillation is selected, the CR oscillation circuit (Max. 2.2 MHz) is formed merely by connecting a resistor (RCR3) between OSC3 and OSC4 terminals.

5.4.5 Switching the CPU clocks

You can use either OSC1 or OSC3 as the system clock for the CPU and you can switch over by means of software. You can save power by turning the OSC3 oscillation circuit off while the CPU is operating in OSC1. When you must operate on OSC3, you can change to high speed operation by turning the OSC3 oscillation circuit ON and switching over the system clock. In this case, since several msec to several tens of msec are necessary for the oscillation to stabilize after turning the OSC3 oscillation circuit ON, you should switch over the clock after stabilization time has elapsed. When switching over from the OSC3 to the OSC1, turn the OSC3 oscillation circuit OFF immediately following the clock changeover. When switching the system clock from OSC3 to OSC1 immediately after the power is turned on, it is necessary to wait for the OSC1 oscillation to stabilize before the clock can be switched. The OSC3 oscillation may take several tens of msec to several seconds until it has completely stabilized. (The oscillation start time will vary somewhat depending on the oscillator and on the externally attached parts. Refer to the oscillation start time example indicated in Chapter 8, "ELECTRICAL CHARACTERISTICS".)

Figure 5.4.5.1 indicates the status transition diagram for the clock changeover.

OSC1 OSC3 CPU clock

ON ON OSC1

SOSC3=0

SOSC3=1

Low speed and

low power operation

OSC1 OSC3 CPU clock

ON OFF OSC1

HALT status OSC1 OSC3 CPU clock

HALT instruction SLP instructionInterrupt Interrupt

ON or OFF

STOP

(Input interrupt)

SLEEP status OSC1 OSC3 CPU clock

OFF OFF STOP

Standby Status

The return destination from the standby status becomes the program execution status prior to shifting to the standby status.

Fig. 5.4.5.1 Status transition diagram for the clock changeover

42 EPSON S1C88650 TECHNICAL MANUAL

5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Oscillation Circuits)

5.4.6 Control of oscillation circuit

Table 5.4.6.1 shows the control bits for the oscillation circuits.

Table 5.4.6.1 Oscillation circuit control bits

Address Bit Name SR R/WFunction Comment10

00FF02 D7

D3 D2 D1 D0

EBR

WT2

WT1

WT0

CLKCHG SOSC3 – –

Bus release enable register (K03 and R33 terminal specification) Wait control register

WT2

CPU operating clock switch OSC3 oscillation On/Off control R/W register R/W register

WT1 1 1 1 1 0 0 0 0

WT0 1 1 0 0 1 1 0 0

1 0 1 0 1 0 1 0

Number

of state

14 12 10

8 6 4 2

No wait

K03 R33

BREQ BACK

OSC3

1 1

Input port

Output port

OSC1

Off

0 0

R/W

Reserved register

R/W

SOSC3: 00FF02H•D2

Controls the ON and OFF settings of the OSC3 oscillation circuit.

When "1" is written: OSC3 oscillation ON When "0" is written: OSC3 oscillation OFF Reading: Valid

When the CPU and some peripheral circuits are to be operated at high speed, SOSC3 is to be set to "1". At all other times, it should be set to "0" in order to reduce current consumption. At initial reset, SOSC3 is set to "1" (OSC3 oscillation ON).

5.4.7 Programming notes

(1) When the high speed CPU operation is not

necessary, you should operate the peripheral circuits according to the setting outline indicate below.

• CPU operating clock OSC1

• OSC3 oscillation circuit OFF

(When the OSC3 clock is not necessary for some peripheral circuits.)

(2) Since several msec to several tens of msec are

necessary for the oscillation to stabilize after turning the OSC3 oscillation circuit ON. Consequently, you should switch the CPU

CLKCHG: 00FF02H•D3

Selects the operating clock for the CPU.

When "1" is written: OSC3 clock When "0" is written: OSC1 clock Reading: Valid

When the operating clock for the CPU is switched to OSC3, CLKCHG should be set to "1" and when the clock is switched to OSC1, CLKCHG should be set to "0". At initial reset, CLKCHG is set to "1" (OSC3 clock).

operating clock (OSC1 → OSC3) after allowing for a sufficient waiting time once the OSC3 oscillation goes ON. (The oscillation start time will vary somewhat depending on the oscillator and on the externally attached parts. Refer to the oscillation start time example indicated in Chapter 8, "ELECTRICAL CHARACTERISTICS".)

(3) When switching the clock from OSC3 to OSC1, be

sure to switch OSC3 oscillation OFF with separate instructions. Using a single instruction to process simultaneously can cause a malfunction of the CPU.

(4) When switching the system clock from OSC3 to

OSC1 immediately after the power is turned on, it is necessary to wait the OSC1 oscillation to stabilize before the clock can be switched. The OSC3 oscillation takes several tens of msec to several seconds until it has completely stabilized. (The oscillation start time will vary somewhat depending on the oscillator and on the externally attached parts. Refer to the oscillation start time example indicated in Chapter 8, "ELECTRICAL CHARACTERISTICS".)

S1C88650 TECHNICAL MANUAL EPSON 43

5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Input Ports)

5.5 Input Ports (K ports)

5.5.1 Configuration of input ports

The S1C88650 is equipped with 8 input port bits (K00–K07) all of which are usable as general purpose input port terminals with interrupt function. K04–K07 terminals doubles as the external clock (EXCL0–EXCL3) input terminal of the programmable timer (event counter) with input port functions sharing the input signal as is. (See "5.10 Programmable Timer")

Furthermore, it should be noted, however, that K03 terminal is shared with the bus authority release request signal (BREQ) input terminal. Function assignment of this terminal can be selected in software. When this terminal is selected for BREQ signal, K03 cannot be used as an input port. (See "5.2 System Controller and Bus Control") In the explanation below, it is assumed that K03 is set as an input port.

Figure 5.5.1.1 shows the structure of the input port.

_________

Pull-up

control

5.5.2 Mask option

Input port pull-up resistors

K00 .... ■■ With resistor ■■ Gate direct

K01 .... ■■ With resistor ■■ Gate direct

K02 .... ■■ With resistor ■■ Gate direct

K03 .... ■■ With resistor ■■ Gate direct

K04 .... ■■ With resistor ■■ Gate direct

K05 .... ■■ With resistor ■■ Gate direct

K06 .... ■■ With resistor ■■ Gate direct

K07 .... ■■ With resistor ■■ Gate direct

Input port Input I/F level

K00 .... ■■ CMOS level ■■ CMOS schmitt

K01 .... ■■ CMOS level ■■ CMOS schmitt

K02 .... ■■ CMOS level ■■ CMOS schmitt

K03 .... ■■ CMOS level ■■ CMOS schmitt

K04 .... ■■ CMOS level ■■ CMOS schmitt

K05 .... ■■ CMOS level ■■ CMOS schmitt

K06 .... ■■ CMOS level ■■ CMOS schmitt

K07 .... ■■ CMOS level ■■ CMOS schmitt

Input ports K00–K07 are all equipped with pull-up resistors. The mask option can be used to select 'With resistor' or 'Gate direct' for each port (bit). Also the interface level, either CMOS level or CMOS Schmitt level, can be selected for each port (in a bit units).

Address

Mask option

Kxx

Mask option

VSS

KxxD

Address

Input interrupt circuit

Data bus

Fig. 5.5.1.1 Structure of input port

Each input port terminal is directly connected via a three-state buffer to the data bus. Furthermore, the input signal state at the instant of input port readout is read in that form as data.

44 EPSON S1C88650 TECHNICAL MANUAL

5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Input Ports)

5.5.3 Pull-up control

When "With resistor" is selected by mask option, the software can enable and disable the pull-up resistor for each port (1-bit units).

The pull-up resistor becomes effective by writing "1" to the pull-up control register PULK0x that corresponds to each port, and the input line is pulled up. When "0" has been written, no pull-up is done. When "Gate direct" is selected by mask option, the corresponding pull-up control register is disconnected from the input line, so it can be used as a general-purpose register. At initial reset, the pull-up control register is set to "1" (pulled up).

The input port with a pull-up resistor suits input from the push switch and key matrix.

When changing the input terminal from LOW level to HIGH with the built-in pull-up resistor, a delay in the waveform rise time will occur depending on the time constant of the pull-up resistor and the load capacitance of the terminal. It is necessary to set an appropriate wait time for introduction of an input port. In particular, special attention should be paid to key scan for key matrix formation. Make this wait time the amount of time or more calculated by the following expression.

Wait time = RIN x (CIN + load capacitance on the

board) x 1.6 [sec]

RIN: Pull up resistance Max. value CIN: Terminal capacitance Max. value

The input port without a pull-up resistor is suits for slide switch input and interfacing with other LSIs. In this case, take care that a floating state does not occur in input.

For unused ports, select "With resistor" and enable pull-up using the pull-up control registers.

5.5.4 Interrupt function and input comparison register

All the input ports (K00–K07) provide the interrupt functions. The conditions for issuing an interrupt can be set by the software. When the interrupt generation condition set for a terminal is met, the interrupt factor flag FK00–FK07 corresponding to the terminal is set at "1" and an interrupt is generated. Interrupt can be prohibited by setting the interrupt enable registers EK00–EK07 for the corresponding interrupt factor flags. Furthermore, the priority level for input interrupt can be set at the desired level (0–3) using the interrupt priority registers PK00–PK01. For details on the interrupt control registers for the above and on operations subsequent to interrupt generation, see "5.14 Interrupt and Standby Status".

The exception processing vectors for each interrupt factor are set as follows:

K07 input interrupt: 000006H K06 input interrupt: 000008H K05 input interrupt: 00000AH K04 input interrupt: 00000CH K03 input interrupt: 00000EH K02 input interrupt: 000010H K01 input interrupt: 000012H K00 input interrupt: 000014H

Figure 5.5.4.1 shows the configuration of the input interrupt circuit. The input comparison register KCP selects whether the interrupt for each input port will be generated on the rising edge or the falling edge of input. When the K0x input signal changes to the status set by the input comparison register KCP0x, the interrupt factor flag FK0x is set to "1" and an interrupt occurs. The input port has a chattering-eliminate circuit that checks input level to avoid unnecessary interrupt generation due to chattering. There are two separate chattering-eliminate circuits for K00– K03 and K04–K07 and they can be set up individually. The CTK00x–CTK02x registers allow selection of signal level check time as shown in Table 5.5.4.1.

S1C88650 TECHNICAL MANUAL EPSON 45

5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Input Ports)

Table 5.5.4.1 Setting the input level check time

CTK02x

Data bus

1 1 1 1 0 0 0 0

K00

Input port

K00D

Input comparison

Address

K01

K02

K03

K04

CTK01x

CTK00x

1 1 0 0 1 1 0 0

1 0 1 0 1 0 1 0

Check time

4/f

OSC3

2/f

OSC3 OSC3

1/f

4096/f

OSC1 OSC1

2048/f

512/f

OSC1

128/f

OSC1

None –

∗: When OSC1 = 32 kHz, OSC3 = 2 MHz

Check time setup register

CTK00L–CTK02L

Chattering-eliminate

circuit

Check time setup register

CTK00H–CTK02H

(∗)

(2 µs) (1 µs) (0.5 µs) (128 ms) (64 ms) (16 ms) (4 ms)

Address

Notes: • Be sure to disable interrupts before

Interrupt factor

flag FK00

Address

Interrupt enable

EK00

Address

changing the contents of the CTK0x register. Unnecessary interrupts may occur if the register is changed when the corresponding input port interrupts have been enabled by the interrupt enable register EK0x.

• The chattering-eliminate check time means the maximum pulse width that can be eliminated. The valid interrupt input needs a pulse width of the set check time (minimum) to twice that of the check time (maximum).

• The internal signal may oscillate if the rise / fall time of the input signal is too long because the input signal level transition to the threshold level duration of time is too long. This causes the input interrupt to malfunction, therefore setup the input signal so that the rise/fall time is 25 nsec or less.

OSC1

Divider

Interrupt

priority level

judgement

circuit

oscillation circuit

OSC3

oscillation circuit

OSC1

OSC3

Interrupt request

Input port

K04D

Input comparison

Address

K05

K06

K07

Chattering-eliminate

circuit

Interrupt factor

flag FK04

Address

Interrupt enable

EK04

Address

Interrupt

priority

PK00, PK01

Address

Fig. 5.5.4.1 Configuration of input interrupt circuit

46 EPSON S1C88650 TECHNICAL MANUAL

5.5.5 Control of input ports

Table 5.5.5.1 shows the input port control bits.

Table 5.5.5.1(a) Input port control bits

00FF52 D7

00FF54 D7

00FF56 D7

00FF58 D7

D6 D5 D4 D3 D2 D1 D0

D3 D2

KCP07 KCP06 KCP05 KCP04 KCP03 KCP02 KCP01 KCP00 K07D K06D K05D K04D K03D K02D K01D K00D PULK07 PULK06 PULK05 PULK04 PULK03 PULK02 PULK01 PULK00 – CTK02H

CTK01H

CTK00H

– CTK02L

CTK01L

CTK00L

(Input level check time)

CTK02H

1 1 1 1 0 0 0 0

CTK01H

1 1 0 0 1 1 0 0

CTK00H

1 0 1 0 1 0 1 0

– K00–K03 port chattering-eliminate setup

(Input level check time)

CTK02L

1 1 1 1 0 0 0 0

CTK01L

1 1 0 0 1 1 0 0

CTK00L

1 0 1 0 1 0 1 0

5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Input Ports)

SR R/WAddress Bit Name Function Comment10

Check time

[sec]

OSC3

4/f 2/fOSC3

1/fOSC3 4096/fOSC1 2048/fOSC1

512/fOSC1 128/fOSC1

None

Check time

[sec]

4/fOSC3

2/fOSC3

1/fOSC3 4096/fOSC1 2048/fOSC1

512/fOSC1 128/fOSC1

None

Interrupt

generated

at falling

edge

High level

input

On Off

Interrupt

generated

at rising

edge

Low level

input

1 R/W

–R

1 R/W

–

– 0

"0" when being read

R/W

"0" when being read

R/W

S1C88650 TECHNICAL MANUAL EPSON 47

5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Input Ports)

Table 5.5.5.1(b) Input port control bits

00FF20 D7

00FF24 EK07

00FF28 FK07

D6 D5 D4 D3 D2 D1

D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0

PK01 PK00 PSIF1 PSIF0 – – PTM1

PTM0

EK06 EK05 EK04 EK03 EK02 EK01 EK00

FK06 FK05 FK04 FK03 FK02 FK01 FK00

K00–K07 interrupt priority register

Serial interface interrupt priority register

– – Clock timer interrupt priority register

K07 interrupt enable K06 interrupt enable K05 interrupt enable K04 interrupt enable K03 interrupt enable K02 interrupt enable K01 interrupt enable K00 interrupt enable K07 interrupt factor flag K06 interrupt factor flag K05 interrupt factor flag K04 interrupt factor flag K03 interrupt factor flag K02 interrupt factor flag K01 interrupt factor flag K00 interrupt factor flag

PK01

PSIF1

1 1 0 0

– –

PTM1

1 1 0 0

Interrupt

enable

(R)

Interrupt

factor is

generated

(W)

Reset

PK00 PSIF0

1 0 1 0

PTM0

1 0 1 0

Priority

level Level 3 Level 2 Level 1 Level 0

– –

Priority level

Level 3 Level 2 Level 1 Level 0

Interrupt

disable

(R)

No interrupt

factor is

generated

(W)

No operation

SR R/WAddress Bit Name Function Comment10

– – 0

R/W

Constantly "0" when being read

R/W

K00D–K07D: 00FF54H

Input data of input port terminal K0x can be read out.

When "1" is read: HIGH level When "0" is read: LOW level Writing: Invalid

The terminal voltage of each of the input port K00– K07 can be directly read out as either a "1" for HIGH (V This bit is exclusively for readout and are not usable for write operations.

DD) level or a "0" for LOW (VSS) level.

PULK00–PULK07: 00FF56H

Controls the input pull-up resistor.

When "1" is written: Pull-up ON When "0" is written: Pull-up OFF Reading: Valid

PULK0x is the pull-up control register corresponding to the input port K0x that turns the pull-up resistor built into the input port ON and OFF. When "Gate direct" is selected by mask option, the corresponding pull-up control register is disconnected from the input line, so it can be used as a general-purpose register. When "1" is written to PULK0x, the corresponding input port K0x is pulled up to high. When "0" is written, the input port is not pulled up. At initial reset, this register is set to "1" (Pull-up ON).

48 EPSON S1C88650 TECHNICAL MANUAL

5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Input Ports)

KCP00–KCP07: 00FF52H

Sets the interrupt generation condition (interrupt generation timing) for input port terminals K00– K07.

When "1" is written: Falling edge When "0" is written: Rising edge Reading: Valid

KCP0x is the input comparison register which corresponds to the input port K0x. Interrupt in those ports which have been set to "1" is generated on the falling edge of the input and in those set to "0" on the rising edge. At initial reset, this register is set to "1" (falling edge).

CTK00L–CTK02L: 00FF58H•D0–D2

Sets the input level check time of the chatteringeliminate circuit for the K00–K03 input port interrupts as shown in Table 5.5.5.2.

Table 5.5.5.2 Setting the input level check time

CTK02L

CTK01L

1 1 1 1 0 0 0 0

CTK00L

1 1 0 0 1 1 0 0

Input level check time [sec]

4/f 2/f

1/f 4096/f 2048/f

512/f 128/f

None

OSC3 OSC3 OSC3

1 0 1 0 1 0 1 0

OSC1

OSC1 OSC1 OSC1

Be sure to disable interrupts before changing the contents of this register. Unnecessary interrupts may occur if the register is changed when the corresponding input port interrupts have been enabled by the interrupt enable register EK0x. At initial reset, this register is set to "0" (None).

CTK00H–CTK02H: 00FF58H•D4–D6

Sets the input level check time of the chatteringeliminate circuit for the K04–K07 input port interrupts as shown in Table 5.5.5.3.

Table 5.5.5.3 Setting the input level check time

CTK02H

Be sure to disable interrupts before changing the contents of this register. Unnecessary interrupt may occur if the register is changed when the corresponding input port interrupts have been enabled by the interrupt enable register EK0x. At initial reset, this register is set to "0" (None).

1 1 1 1 0 0 0 0

CTK01H

1 1 0 0 1 1 0 0

CTK00H

1 0 1 0 1 0 1 0

Input level check time [sec]

4/f 2/f

1/f 4096/f 2048/f

512/f 128/f

None

OSC3 OSC3 OSC3

OSC1

OSC1 OSC1 OSC1

PK00, PK01: 00FF20H•D6, D7

Sets the input interrupt priority level. PK00 and PK01 are the interrupt priority registers corresponding to the input interrupts. Table 5.5.5.4 shows the interrupt priority level which can be set by this register.

Table 5.5.5.4 Interrupt priority level settings

PK01 PK00 Interrupt priority level

1 1 0 0

1 0 1 0

Level 3 (IRQ3) Level 2 (IRQ2) Level 1 (IRQ1) Level 0 (None)

At initial reset, this register is set to "0" (level 0).

EK00–EK07: 00FF24H

How interrupt generation to the CPU is permitted or prohibited.

When "1" is written: Interrupt permitted When "0" is written: Interrupt prohibited Reading: Valid

EK0x is the interrupt enable register which correspond to the input port K0x. Interrupt is permitted in those terminals set to "1" and prohibited in those set to "0". At initial reset, this register is set to "0" (interrupt prohibited).

FK00–FK07: 00FF28H

Indicates the generation state for an input interrupt.

When "1" is read: Interrupt factor present When "0" is read:

When "1" is written: Reset factor flag When "0" is written: Invalid

The interrupt factor flag FK0x corresponds to K0x is set to "1" by the occurrence of an interrupt generation condition. When set in this manner, if the corresponding interrupt enable register is set to "1" and the corresponding interrupt priority register is set to a higher level than the setting of interrupt flags (I0 and I1), an interrupt will be generated to the CPU. Regardless of the interrupt enable register and interrupt priority register settings, the interrupt factor flag will be set to "1" by the occurrence of an interrupt generation condition. To accept the subsequent interrupt after interrupt generation, re-setting of the interrupt flags (set interrupt flag to lower level than the level indicated by the interrupt priority registers, or execute the RETE instruction) and interrupt factor flag reset are necessary. The interrupt factor flag is reset to "0" by writing "1". At initial reset, this flag is all reset to "0".

Interrupt factor not present

S1C88650 TECHNICAL MANUAL EPSON 49

5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Input Ports)

5.5.6 Programming notes

(1) When changing the input terminal from LOW

level to HIGH with the built-in pull-up resistor, a delay in the waveform rise time will occur depending on the time constant of the pull-up resistor and the load capacitance of the terminal. It is necessary to set an appropriate wait time for introduction of an input port. In particular, special attention should be paid to key scan for key matrix formation. Make this wait time the amount of time or more calculated by the following expression.

Wait time = RIN x (CIN + load capacitance on the

board) x 1.6 [sec]

RIN: Pull up resistance Max. value CIN: Terminal capacitance Max. value

(2) Be sure to disable interrupts before changing

the contents of the CTK0x register. Unnecessary interrupts may occur if the register is changed when the corresponding input port interrupts have been enabled by the interrupt enable register EK0x.

50 EPSON S1C88650 TECHNICAL MANUAL

5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Output Ports)

5.6 Output Ports (R ports)

5.6.1 Configuration of output ports

The S1C88650 is equipped with 26 bits of output ports (R00–R07, R10–R17, R20–R25, R30–R33). Depending on the bus mode setting, the configuration of the output ports may vary as shown in the table below.

Table 5.6.1.1 Configuration of output ports

Terminal

R00

Output port R00

R01

Output port R01

R02

Output port R02

R03

Output port R03

R04

Output port R04

R05

Output port R05

R06

Output port R06

R07

Output port R07

R10

Output port R10

R11

Output port R11

R12

Output port R12

R13

Output port R13

R14

Output port R14

R15

Output port R15

R16

Output port R16

R17

Output port R17

R20

Output port R20

R21

Output port R21

R22

Output port R22

R23

Output port R23

R24

Output port R24

R25

Output port R25

R30

Output port R30

R31

Output port R31

R32

Output port R32

R33

Output port R33

Only the configuration of the output ports in single chip mode will be discussed here. With respect to bus control, see "5.2 System Controller and Bus Control". Figure 5.6.1.1 shows the basic structure of the output ports.

Address

High impedance control register

Data register

Data bus

Address

Bus mode

ExpansionSingle chip

Address A0 Address A1 Address A2 Address A3 Address A4 Address A5 Address A6 Address A7 Address A8

Address A9 Address A10 Address A11 Address A12 Address A13 Address A14 Address A15 Address A16 Address A17 Address A18 Address A19

RD signal

WR signal Output port R30/CE0 signal Output port R31/CE1 signal Output port R32/CE2 signal

Output port R33/BACK signal

Rxx

In expansion mode, the data registers and high impedance control registers of the output ports used for bus function can be used as general purpose registers with read/write capabilities. This will not in any way affect bus signal output. The output specification of each output port is as complementary output with high impedance control in software possible.

5.6.2 High impedance control

The output port can be high impedance controlled in software. This makes it possible to share output signal lines with an other external device.

A high impedance control register is set for each series of output port terminals as shown below. Either complementary output and high impedance state can be selected with this register.

Table 5.6.2.1 High impedance control registers

HZR0L

HZR0H

HZR1L

HZR1H

HZR20 HZR21 HZR22 HZR23 HZR24 HZR25 HZR30 HZR31 HZR32 HZR33

R00–R03 R04–R07 R10–R13 R14–R17

R20 R21 R22 R23 R24 R25 R30 R31 R32 R33

When a high impedance control register HZRxx is set to "1", the corresponding output port terminal becomes high impedance state and when set to "0", it becomes complementary output.

5.6.3 DC output

As Figure 5.6.1.1 shows, when "1" is written to the output port data register, the output terminal switches to HIGH (VDD) level and when "0" is written it switches to LOW (VSS) level. When output is in a high impedance state, the data written to the data register is output from the terminal at the instant when output is switched to complementary.

Fig. 5.6.1.1 Structure of output ports

S1C88650 TECHNICAL MANUAL EPSON 51

5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Output Ports)

5.6.4 Control of output ports

Table 5.6.4.1 shows the output port control bits.

Table 5.6.4.1(a) Output port control bits

00FF70 D7

00FF71 D7

00FF72 –

00FF73 D7

00FF74 D7

00FF75 D7

D6 D5 D4 D3 D2 D1 D0

D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0

D6 D5 D4 D3 D2 D1 D0

– – – – HZR1H HZR1L HZR0H HZR0L – – HZR25 HZR24 HZR23 HZR22 HZR21 HZR20

– – – HZR33 HZR32 HZR31 HZR30 R07D R06D R05D R04D R03D R02D R01D R00D R17D R16D R15D R14D R13D R12D R11D R10D – – R25D R24D R23D R22D R21D R20D

R/W register R/W register R/W register R/W register R14–R17 high impedance control R10–R13 high impedance control R04–R07 high impedance control R00–R03 high impedance control R/W register R/W register R25 high impedance control R24 high impedance control R23 high impedance control R22 high impedance control R21 high impedance control R20 high impedance control R/W register R/W register R/W register R/W register R33 high impedance control R32 high impedance control R31 high impedance control R30 high impedance control R07 output port data R06 output port data R05 output port data R04 output port data R03 output port data R02 output port data R01 output port data R00 output port data R17 output port data R16 output port data R15 output port data R14 output port data R13 output port data R12 output port data R11 output port data R10 output port data R/W register R/W register R25 output port data R24 output port data R23 output port data R22 output port data R21 output port data R20 output port data

1 1 1 1

High

impedance

1 1

High

impedance

1 1 1 1

High

impedance

High Low

1 1

High

0 0 0 0

Comple-

mentary

0 0

Comple-

mentary

0 0 0 0

Comple-

mentary

0 0

Low

SR R/WAddress Bit Name Function Comment10

0 0 0 0

0 0

0 0 0 0

1 R/W

0 0

Reserved register

R/W R/W R/W R/W

R/W

Reserved register

R/W R/W

R/W

Reserved register

R/W R/W R/W R/W

R/W

Reserved register

R/W R/W

R/W

52 EPSON S1C88650 TECHNICAL MANUAL

00FF76 D7

D6 D5 D4 D3 D2 D1 D0

– – – – R33D R32D R31D R30D

Table 5.6.4.1(b) Output port control bits

R/W register R/W register R/W register R/W register R33 output port data R32 output port data R31 output port data R30 output port data

5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Output Ports)

SR R/WAddress Bit Name Function Comment10

Reserved register0

1 1 1 1

High

0 0 0 0

Low

R/W

HZR0L, HZR0H: 00FF70H•D0, D1 HZR1L, HZR1H: 00FF70H•D2, D3 HZR20–HZR25: 00FF71H•D0–D5 HZR30–HZR33: 00FF72H•D0–D3

Sets the output terminals to a high impedance state.

When "1" is written: High impedance When "0" is written: Complementary Reading: Valid

HZRxx is the high impedance control register which correspond as shown in Table 5.6.2.1 to the various output port terminals. When "1" is set to the HZRxx register, the corresponding output port terminal becomes high impedance state and when "0" is set, it becomes complementary output. At initial reset, this register is set to "0" (complementary).

R00D–R07D: 00FF73H R10D–R17D: 00FF74H R20D–R25D: 00FF75H•D0–D5 R30D–R33D: 00FF76H•D0–D3

Sets the data output from the output port terminal Rxx.

When "1" is written: HIGH level output When "0" is written: LOW level output Reading: Valid

RxxD is the data register for each output port. When "1" is set, the corresponding output port terminal switches to HIGH (V "0" is set, it switches to LOW (VSS) level. At initial reset, this register is set to "1" (HIGH level output). The output data registers set for bus signal output can be used as general purpose registers with read/ write capabilities which do not affect the output terminals.

DD) level, and when

S1C88650 TECHNICAL MANUAL EPSON 53

5 PERIPHERAL CIRCUITS AND THEIR OPERATION (I/O Ports)

5.7 I/O Ports (P ports)

5.7.1 Configuration of I/O ports

The S1C88650 is equipped with 16 bits of I/O ports (P00–P07, P10–P17). The configuration of these I/O ports will vary according to the bus mode as shown below.

Table 5.7.1.1 Configuration of I/O ports

Terminal

P00 P01 P02 P03 P04 P05 P06 P07 P10 P11 P12 P13 P14 P15 P16 P17

I/O port P00 I/O port P01 I/O port P02 I/O port P03 I/O port P04 I/O port P05 I/O port P06 I/O port P07

With respect to the data bus, see "5.2 System Controller and Bus Control". Figure 5.7.1.1 shows the structure of an I/O port.

Pull-up control register

I/O control register

Data

Data bus

Input control

*1:

During output mode

*2:

During input mode

*3:

Schmitt input can be selected for P10–P17 by mask option.

Fig. 5.7.1.1 Structure of I/O port

I/O port can be set for input or output mode in one bit unit. These settings are performed by writing data to the I/O control registers. I/O port terminals P10–P13 are shared with serial interface input/output terminals and the function of each terminal is switchable in software. With respect to serial interface see "5.8 Serial Interface".

Bus mode

ExpansionSingle chip

Data bus D0 Data bus D1 Data bus D2 Data bus D3 Data bus D4 Data bus D5 Data bus D6

Data bus D7 I/O port P10 (SIN) I/O port P11 (SOUT) I/O port P12 (SCLK) I/O port P13 (SRDY) I/O port P14 (TOUT0/TOUT1) I/O port P15 (TOUT2/TOUT3) I/O port P16 (FOUT) I/O port P17 (TOUT2/TOUT3)

Mask option

Pxx

The data registers and I/O control registers of I/O ports set for data bus and serial interface output terminals use are usable as general purpose registers with read/write capabilities which do not affect I/O activities of the terminal. The same as above, the I/O control register of I/O port set for serial interface input terminal use is usable as general purpose register.

In addition to the general-purpose DC output, special output can be selected for the I/O ports P14–P17 with the software.

5.7.2 Mask option

I/O port pull-up resistors

P00 ............ ■■ With resistor ■■ Gate direct

P01 ............ ■■ With resistor ■■ Gate direct

P02 ............ ■■ With resistor ■■ Gate direct

P03 ............ ■■ With resistor ■■ Gate direct

P04 ............ ■■ With resistor ■■ Gate direct

P05 ............ ■■ With resistor ■■ Gate direct

P06 ............ ■■ With resistor ■■ Gate direct

P07 ............ ■■ With resistor ■■ Gate direct

P10 ............ ■■ With resistor ■■ Gate direct

P11 ............ ■■ With resistor ■■ Gate direct

P12 ............ ■■ With resistor ■■ Gate direct

P13 ............ ■■ With resistor ■■ Gate direct

P14 ............ ■■ With resistor ■■ Gate direct

P15 ............ ■■ With resistor ■■ Gate direct

P16 ............ ■■ With resistor ■■ Gate direct

P17 ............ ■■ With resistor ■■ Gate direct

I/O port input interface level

P10 ............ ■■ CMOS level ■■ CMOS Schmitt

P11 ............ ■■ CMOS level ■■ CMOS Schmitt

P12 ............ ■■ CMOS level ■■ CMOS Schmitt

P13 ............ ■■ CMOS level ■■ CMOS Schmitt

P14 ............ ■■ CMOS level ■■ CMOS Schmitt

P15 ............ ■■ CMOS level ■■ CMOS Schmitt

P16 ............ ■■ CMOS level ■■ CMOS Schmitt

P17 ............ ■■ CMOS level ■■ CMOS Schmitt

I/O ports P00–P07 and P10–P17 are equipped with a pull-up resistor which goes ON in the input mode. Whether this resistor is used or not can be selected for each port (one bit unit). Furthermore, the interface level for each port in P10–P17 can be selected from CMOS level and CMOS Schmitt level.

5.7.3 I/O control registers and I/O mode

I/O ports P00–P07 and P10–P17 are set either to input or output modes by writing data to the I/O control registers IOC00–IOC07 and IOC10–IOC17 which correspond to each bit. To set an I/O port to input mode, write "0" to the I/ O control register. An I/O port which is set to input mode will shift to a high impedance state and functions as an input port.

54 EPSON S1C88650 TECHNICAL MANUAL

5 PERIPHERAL CIRCUITS AND THEIR OPERATION (I/O Ports)

Readout in input mode consists simply of a direct readout of the input terminal state: the data being "1" when the input terminal is at HIGH (VDD) level and "0" when it is at LOW (VSS) level. When the built-in pull-up resistor is enabled with the software, the port terminal will be pulled-up to high during input mode. Even in input mode, data can be written to the data registers without affecting the terminal state. To set an I/O port to output mode, write "1" to the I/O control register. An I/O port which is set to output mode functions as an output port. When port output data is "1", a HIGH (VDD) level is output and when it is "0", a LOW (VSS) level is output. Readout in output mode consists of the contents of the data register. At initial reset, I/O control registers are set to "0" (I/O ports are set to input mode).

5.7.4 Pull-up control

When "With resistor" is selected by mask option, the software can enable and disable the pull-up resistor for each port (1-bit units). The pull-up resistor becomes effective by writing "1" to the pull-up control register PULPxx that corresponds to each port, and the Pxx terminal is pulled up during the input mode. When "0" has been written, no pull-up is done. When "Gate direct" is selected by mask option, the corresponding pull-up control register is disconnected from the input line, so it can be used as a general-purpose register. When the port is set in the output mode, the setting of the pull-up control register becomes invalid (no pull-up is done during output). At initial reset, the pull-up control registers are set to "1" (pulled up).

When changing the port terminal from LOW level to HIGH with the built-in pull-up resistor, a delay in the waveform rise time will occur depending on the time constant of the pull-up resistor and the load capacitance of the terminal. It is necessary to set an appropriate wait time for introduction of an I/O port. Make this wait time the amount of time or more calculated by the following expression.

Wait time = RIN x (CIN + load capacitance on the

board) x 1.6 [sec]

RIN: Pull up resistance Max. value CIN: Terminal capacitance Max. value

For unused ports, select "With resistor" and enable pull-up using the pull-up control registers.

5.7.5 Special output

Besides general purpose DC input/output, I/O ports P14–P17 can also be assigned special output functions in software as shown in Table 5.7.5.1.

Table 5.7.5.1 Special output ports

Output port

P14 P15 P16 P17

When using P14–P17 as a special output port, write "1" to the corresponding I/O control register (IOC14–IOC17) to set the port to the output mode.

■ TOUT output (P14, P15)

In order for the S1C88650 to provide clock signal to an external device, the terminals P14 and P15 can be used to output a TOUTx signal (clock output by the programmable timer).

The output control for the TOUTx signals (x = 0–3) is done by the registers PTOUTx. When PTOUTx is set to "1", the TOUTx signal is output from the corresponding port terminal, when "0" is set, the port is set for DC output. When PTOUTx is "1", settings of the I/O control register IOC14/IOC15 and data register P14D/P15D become invalid. The TOUT0–TOUT3 signals are generated from the underflow and compare-match signals of the programmable timers 0–3. With respect to frequency control, see "5.10 Programmable Timer". Since the TOUTx signals are generated asynchronously from the registers PTOUTx, when the signals are turned ON or OFF by the register settings, a hazard of a 1/2 cycle or less is generated. Figure 5.7.5.1 shows the output waveform of the TOUT signal.

PTOUTx TOUTx output

(P14/15)

Fig. 5.7.5.1 Output waveform of TOUT signal

Note: If PTOUT0 and PTOUT1 are set to "1" at the

same time, PTOUT1 is effective. Similarly, if PTOUT2 and PTOUT3 are set to "1", PTOUT3 is effective.

Special output

TOUT0/TOUT1 output TOUT2/TOUT3 output

FOUT output

TOUT2/TOUT3 output

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■ FOUT output (P16)

In order for the S1C88650 to provide clock signal to an external device, a FOUT signal (oscillation clock fOSC1 or fOSC3 dividing clock) can be output from the P16 port terminal. The output control for the FOUT signal is done by the register FOUTON. When FOUTON is set to "1", the FOUT signal is output from the P16 port terminal, when "0" is set, the port is set for DC output. When FOUTON is "1", settings of the I/O control register IOC16 and data register P16D become invalid. The frequency of the FOUT signal can be selected in software by setting the registers FOUT0–FOUT2. The frequency is selected any one from among eight settings as shown in Table 5.7.5.2.

Table 5.7.5.2 FOUT frequency setting

FOUT2 FOUT frequency

FOUT1

1 1 1 1 0 0 0 0

FOUT0

1 1 0 0 1 1 0 0

1 0 1 0 1 0 1 0

fOSC1:

OSC1 oscillation frequency

OSC3:

OSC3 oscillation frequency

fOSC3 / 8 fOSC3 / 4 fOSC3 / 2 fOSC3 / 1 fOSC1 / 8 fOSC1 / 4 fOSC1 / 2 fOSC1 / 1

When the FOUT frequency is made "fOSC3/n", you must turn on the OSC3 oscillation circuit before outputting FOUT. A time interval of several msec to several 10 msec, from the turning ON of the OSC3 oscillation circuit to until the oscillation stabilizes, is necessary, due to the oscillation element that is used. Consequently, if an abnormality occurs as the result of an unstable FOUT signal being output externally, you should allow an adequate waiting time after turning ON of the OSC3 oscillation, before turning outputting FOUT. (The oscillation start time will vary somewhat depending on the oscillator and on the externally attached parts. Refer to the oscillation start time example indicated in Chapter 8, "ELECTRICAL CHARACTERISTICS".) Since the FOUT signal is generated asynchronously from the register FOUTON, when the signal is turned ON or OFF by the register settings, a hazard of a 1/2 cycle or less is generated. Figure 5.7.5.2 shows the output waveform of the FOUT signal.

■ Inverted TOUT output (P17)

The S1C88650 provides an output of the TOUT2 or TOUT3 inverted signal (programmable timer output clock) to supply a clock to external devices or to drive a buzzer. By using this output with the TOUT2 or TOUT3 output from the P15 terminal, the bias level to be applied to the buzzer can be increased.

___________

The output control for the TOUTx signals (x = 2 or

3) is done by the registers RPTOUTx. When

___________

RPTOUTx is set to "1", the TOUTx signal is output from the P17 port terminal, when "0" is set, the port is set for DC output. When RPTOUTx is "1", settings of the I/O control register IOC17 and data register P17D become invalid.

___________ ___________

The TOUT2 and TOUT3 signals are generated from the underflow and compare-match signals of the programmable timers 2 and 3. With respect to frequency control, see "5.10 Programmable Timer".

___________

Since the TOUTx signals are generated asynchronously from the registers RPTOUTx, when the signals are turned ON or OFF by the register settings, a hazard of a 1/2 cycle or less is generated. Figure 5.7.5.3 shows the output waveform of the

_________

TOUT signal.

RPTOUTx TOUTx output

(P17)

________

Fig. 5.7.5.3 Output waveform of TOUT signal

Note: If RPTOUT2 and RPTOUT3 are set to "1" at

the same time, RPTOUT3 is effective.

FOUTON FOUT output

(P16)

Fig. 5.7.5.2 Output waveform of FOUT signal

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5 PERIPHERAL CIRCUITS AND THEIR OPERATION (I/O Ports)

5.7.6 Control of I/O ports

Table 5.7.6.1 shows the I/O port control bits.

Table 5.7.6.1(a) I/O port control bits

Address Bit Name SR R/WFunction Comment10 00FF60 D7

00FF61 D7

00FF62 D7

00FF63 D7

00FF64 D7

00FF65 D7

D6 D5 D4 D3 D2 D1 D0

IOC07 IOC06 IOC05 IOC04 IOC03 IOC02 IOC01 IOC00 IOC17 IOC16 IOC15 IOC14 IOC13 IOC12 IOC11 IOC10 P07D P06D P05D P04D P03D P02D P01D P00D P17D P16D P15D P14D P13D P12D P11D P10D PULP07 PULP06 PULP05 PULP04 PULP03 PULP02 PULP01 PULP00 PULP17 PULP16 PULP15 PULP14 PULP13 PULP12 PULP11 PULP10

P07 I/O control register P06 I/O control register P05 I/O control register P04 I/O control register P03 I/O control register P02 I/O control register P01 I/O control register P00 I/O control register P17 I/O control register P16 I/O control register P15 I/O control register P14 I/O control register P13 I/O control register P12 I/O control register P11 I/O control register P10 I/O control register P07 I/O port data P06 I/O port data P05 I/O port data P04 I/O port data P03 I/O port data P02 I/O port data P01 I/O port data P00 I/O port data P17 I/O port data P16 I/O port data P15 I/O port data P14 I/O port data P13 I/O port data P12 I/O port data P11 I/O port data P10 I/O port data P07 pull-up control register P06 pull-up control register P05 pull-up control register P04 pull-up control register P03 pull-up control register P02 pull-up control register P01 pull-up control register P00 pull-up control register P17 pull-up control register P16 pull-up control register P15 pull-up control register P14 pull-up control register P13 pull-up control register P12 pull-up control register P11 pull-up control register P10 pull-up control register

0 R/WOutput Input

1 R/WHigh Low

1 R/WOn Off

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Table 5.7.6.1(b) I/O port control bits

00FF30

00FF31 D7

00FF38

00FF39 D7

00FF40 D7

MODE16_A

PTNREN_A –

–

PTOUT0

PTRUN0

PSET0

CKSEL0

–

PTOUT1

PTRUN1

PSET1

CKSEL1

MODE16_B

PTNREN_B –

RPTOUT2

PTOUT2

PTRUN2

PSET2

CKSEL2

–

– RPTOUT3

PTOUT3

PTRUN3

PSET3

CKSEL3

WDEN

FOUT2

FOUT1

FOUT0

FOUTON

D3 D2

WDRST

TMRST

TMRUN

PTM0–1 8/16-bit mode selection External clock 0 noise rejecter selection – R/W register PTM0 clock output control PTM0 Run/Stop control PTM0 preset PTM0 input clock selection – – – R/W register PTM1 clock output control PTM1 Run/Stop control PTM1 preset PTM1 input clock selection PTM2–3 8/16-bit mode selection External clock 1 noise rejecter selection – PTM2 inverted clock output control PTM2 clock output control PTM2 Run/Stop control PTM2 preset PTM2 input clock selection – – – PTM3 inverted clock output control PTM3 clock output control PTM3 Run/Stop control PTM3 preset PTM3 input clock selection Watchdog timer enable FOUT frequency selection

FOUT2

FOUT1

FOUT0

Frequency

OSC3

/ 8

OSC3

OSC1

f f

OSC1 OSC1

OSC1

/ 4 / 2 / 1 / 8 / 4 / 2 / 1

0 1 0 1 0 1 0

FOUT output control Watchdog timer reset Clock timer reset Clock timer Run/Stop control

16-bit x 1

Enable

– 1

Run

Preset

No operation

External clock

16-bit x 1

Enable

External clock

Enable Disable

– – – 1

Run

Preset

– On On

Run

Preset

–

– On On

Run

Preset

Reset Reset

Run

Internal clock

No operation

Internal clock

No operation

Internal clock

No operation

Internal clock

No operation No operation

bit x 2

Disable

– 0

Off

Stop

– – – 0

Off

Stop

bit x 2

Disable

– Off Off

Stop

–

– Off Off

Stop

Off

Stop

SR R/WAddress Bit Name Function Comment10

0 0 – 0 0 0 0 0 – – – 0 0 0 0 0 0 0 – 0 0 0 0 0 – – – 0 0 0 0 0 1 0

0 – – 0

R/W R/W

"0" when being read Reserved register

R/W R/W R/W

"0" when being read

R/W

Constantly "0" when being read

R/W

Reserved register

R/W R/W

"0" when being read

R/W R/W R/W

"0" when being read

R/W R/W R/W

"0" when being read

R/W

Constantly "0" when being read

R/W R/W R/W

"0" when being read

W R/W R/W R/W

R/W

Constantly "0" when

being read

W R/W

58 EPSON S1C88650 TECHNICAL MANUAL

5 PERIPHERAL CIRCUITS AND THEIR OPERATION (I/O Ports)

■ DC output control

P00D–P07D: 00FF62H P10D–P17D: 00FF63H

How I/O port terminal Pxx data readout and output data settings are performed.

When writing data:

When "1" is written: HIGH level When "0" is written: LOW level

When the I/O port is set to output mode, the data written is output as is to the I/O port terminal. In terms of port data, when "1" is written, the port terminal goes to HIGH (V written to a LOW (VSS) level. Even when the port is in input mode, data can still be written in.

When reading out data:

When "1" is read: HIGH level ("1") When "0" is read: LOW level ("0")

When an I/O port is in input mode, the voltage level being input to the port terminal is read out. When terminal voltage is HIGH (V a "1", and when it is LOW (VSS), it is read as a "0". Furthermore, in output mode, the contents of the data register are read out. At initial reset, this register is set to "1" (HIGH level).

DD) level and when "0" is

DD), it is read as

Note: The data registers of the ports that are

configured to the data bus, serial interface outputs and special outputs can be used as general purpose registers that do not affect the terminal inputs/outputs.

IOC00–IOC07: 00FF60H IOC10–IOC17: 00FF61H

Sets the I/O ports to input or output mode.

When "1" is written: Output mode When "0" is written: Input mode Reading: Valid

IOCxx is the I/O control register which correspond to each I/O port in a bit unit. Writing "1" to the IOCxx register will switch the corresponding I/O port Pxx to output mode, and writing "0" will switch it to input mode. When the special output is used, "1" must always be set for the I/O control registers (IOC14–IOC17) of I/O ports which will become output terminals. At initial reset, this register is set to "0" (input mode).

Note: The I/O control registers of the ports that are

configured to the data bus, serial interface inputs/outputs and special outputs can be used as general purpose registers that do not affect the terminal inputs/outputs.

PULP00–PULP07: 00FF64H PULP10–PULP17: 00FF65H

The pull-up during the input mode are set with these registers.

When "1" is written: Pull-up ON When "0" is written: Pull-up OFF Reading: Valid

PULPxx is the pull-up control register corresponding to each I/O port (in bit units). When "Gate direct" is selected by mask option, the corresponding pull-up control register is disconnected from the input line, so it can be used as a general-purpose register. By writing "1" to the PULPxx register, the corresponding I/O ports are pulled up (during input mode), while writing "0" turns the pull-up function OFF. At initial reset, these registers are all set to "1", so the pull-up function is set to ON.

Note: The pull-up control registers of the ports that

are configured to the serial interface outputs or special outputs can be used as general purpose registers that do not affect the pullup control. The pull-up control registers of the port that are configured to the serial interface inputs function the same as the I/O port.

■ Special output control

PTOUT0: 00FF30H•D3 PTOUT1: 00FF31H•D3 PTOUT2: 00FF38H•D3 PTOUT3: 00FF39H•D3

Controls the TOUT (programmable timer output clock) signal output.

When "1" is written: TOUT signal output When "0" is written: DC output Reading: Valid

PTOUT0–PTOUT3 are the output control registers for the TOUT0–TOUT3 signals. When PTOUT0 (or PTOUT1) is set to "1", the TOUT0 (or TOUT1) signal is output from the P14 port terminal. When PTOUT2 (or PTOUT3) is set to "1", the TOUT2 (or TOUT3) signal is output from the P15 port terminal. When "0" is set, P14/P15 is set for DC output. At this time, settings of the I/O control register IOC14/IOC15 and data register P14D/P15D become invalid. At initial reset, PTOUT is set to "0" (DC output).

Note: If PTOUT0 and PTOUT1 are set to "1" at the

same time, PTOUT1 is effective. Similarly, if PTOUT2 and PTOUT3 are set to "1", PTOUT3 is effective. Furthermore, if the programmable timer is set in 16-bit mode, the TOUT0 and TOUT2 signals cannot be output.

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RPTOUT2: 00FF38H•D4 RPTOUT3: 00FF39H•D4

Controls the TOUT2/TOUT3 (inverted TOUT2/ TOUT3) signal output.

When "1" is written: When "0" is written: DC output Reading: Valid

RPTOUT2 and RPTOUT3 are the output control registers for the TOUT2 and TOUT3 signals, respectively. When RPTOUT2 (or RPTOUT3) is set to "1", the TOUT2 (or TOUT3) signal is output from the P17 port terminal. When "0" is set, P17 is set for DC output. At this time, settings of the I/O control register IOC17 and data register P17D become invalid. At initial reset, RPTOUT is set to "0" (DC output).

Note: If RPTOUT2 and RPTOUT3 are set to "1" at

___________ ___________

_________

TOUT signal output

___________ ___________

the same time, RPTOUT3 is effective. Furthermore, if the programmable timer is set

________

in 16-bit mode, the TOUT2 signal cannot be output.

FOUTON: 00FF40H•D3

Controls the FOUT (fOSC1/fOSC3 dividing clock) signal output.

When "1" is written: FOUT signal output When "0" is written: DC output Reading: Valid

FOUTON is the output control register for FOUT signal. When "1" is set, the FOUT signal is output from the P16 port terminal and when "0" is set, P16 is set for DC output. At this time, settings of the I/ O control register IOC16 and data register P16D become invalid. At initial reset, FOUTON is set to "0" (DC output).

FOUT0–FOUT2: 00FF40H•D4–D6

FOUT signal frequency is set as shown in Table

5.7.6.2.

Table 5.7.6.2 FOUT frequency settings

FOUT2 FOUT frequency

At initial reset, this register is set to "0" (fOSC1/1).

FOUT1

1 1 1 1 0 0 0 0

FOUT0

1 1 0 0 1 1 0 0

1 0 1 0 1 0 1 0

fOSC1:

OSC1 oscillation frequency

OSC3:

OSC3 oscillation frequency

fOSC3 / 8 fOSC3 / 4 fOSC3 / 2 fOSC3 / 1 fOSC1 / 8 fOSC1 / 4 fOSC1 / 2 fOSC1 / 1

5.7.7 Programming notes

(1) When changing the port terminal in which the

pull-up resistor is enabled from LOW level to HIGH, a delay in the waveform rise time will occur depending on the time constant of the pull-up resistor and the load capacitance of the terminal. It is necessary to set an appropriate wait time for introduction of an I/O port. Make this wait time the amount of time or more calculated by the following expression.

Wait time = RIN x (CIN + load capacitance on the

board) x 1.6 [sec]

RIN: Pull up resistance Max. value CIN: Terminal capacitance Max. value

(2) Since the special output signals (TOUT0–3,

_______________ _ _____________________________

TOUT2–3, and FOUT) are generated asynchronously from the output control registers (PTOUT0–3, RPTOUT2–3, and FOUTON), when the signals is turned ON or OFF by the output control register settings, a hazard of a 1/2 cycle or less is generated.

(3) When the FOUT frequency is made "f

you must turn on the OSC3 oscillation circuit before outputting FOUT. A time interval of several msec to several 10 msec, from the turning ON of the OSC3 oscillation circuit to until the oscillation stabilizes, is necessary, due to the oscillation element that is used. Consequently, if an abnormality occurs as the result of an unstable FOUT signal being output externally, you should allow an adequate waiting time after turning ON of the OSC3 oscillation, before turning outputting FOUT. (The oscillation start time will vary somewhat depending on the oscillator and on the externally attached parts. Refer to the oscillation start time example indicated in Chapter 8, "ELECTRICAL CHARACTERISTICS".)

(4) The SLP instruction has executed when the

special output signals (TOUT0–3, TOUT2–3, and FOUT) are in the enable status, an unstable clock is output for the special output at the time of return from the SLEEP state. Consequently, when shifting to the SLEEP state, you should set the special output signal to the disable status prior to executing the SLP instruction.

OSC3/n",

_______________ _ _____________________________

60 EPSON S1C88650 TECHNICAL MANUAL

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5.8 Serial Interface

5.8.1 Configuration of serial interface

The S1C88650 incorporates a full duplex serial interface (when asynchronous system is selected) that allows the user to select either clock synchronous system or asynchronous system. The data transfer method can be selected in software. When the clock synchronous system is selected, 8bit data transfer is possible. When the asynchronous system is selected, either 7bit or 8-bit data transfer is possible, and a parity check of received data and the addition of a parity bit for transmitting data can automatically be done by selecting in software. Figure 5.8.1.1 shows the configuration of the serial interface.

Data bus

5.8.2 Switching of terminal functions

Serial interface input/output terminals, SIN, SOUT,

_________ _________

SCLK and SRDY are shared with I/O ports P10– P13. In order to utilize these terminals for the serial interface input/output terminals, "1" must be written to the ESIF register. At initial reset, these terminals are set as I/O port terminals. The direction of I/O port terminals set for serial interface input/output terminals are determined by the signal and transfer mode for each terminal. Furthermore, the settings for the corresponding I/ O control registers for the I/O ports become invalid.

Table 5.8.2.1 Configuration of input/output terminals

Terminal When serial interface is selected

P10 P11 P12 P13

* The terminals used may vary depending on the transfer mode.

SIN SOUT SCLK SRDY

SIN(P10)

SCLK(P12)

Serial I/O control & status register

Serial input control circuit

Start bit detection circuit

Received data buffer

Received data shift register

Clock control circuit

Error detection circuit

Transmitting data shift register

Programmable timer 1 underflow signal

Fig. 5.8.1.1 Configuration of serial interface

Interrupt control circuit

Serial output control circuit

READY output control circuit

Interrupt request

SOUT(P11)

SRDY(P13)

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5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Serial Interface)

The serial interface terminals are configured according to the transfer mode set using the registers SMD0 and SMD1. SIN and SOUT are serial data input and output terminals which function identically in clock synchronous system

_________

and asynchronous system. SCLK is exclusively for use with clock synchronous system and functions as a synchronous clock input/output terminal.

_________

SRDY is exclusively for use in clock synchronous slave mode and functions as a send-receive ready signal output terminal. When asynchronous system is selected, since SCLK

_________

and SRDY are superfluous, the I/O port terminals P12 and P13 can be used as I/O ports. In the same way, when clock synchronous master

_________

mode is selected, since SRDY is superfluous, the I/O port terminal P13 can be used as I/O port.

5.8.3 Transfer modes

There are four transfer modes for the serial interface and mode selection is made by setting the two bits of the mode selection registers SMD0 and SMD1 as shown in the table below.

Table 5.8.3.1 Transfer modes

SMD1 SMD0 Mode

1 1 0 0

Table 5.8.3.2 Terminal settings corresponding

Asynchronous 8-bit Asynchronous 7-bit Clock synchronous slave Clock synchronous master

At initial reset, transfer mode is set to clock synchronous master mode.

■ Clock synchronous master mode

In this mode, the internal clock is utilized as a synchronous clock for the built-in shift registers, and clock synchronous 8-bit serial transfers can be performed with this serial interface as the master. The synchronous clock is also output from the

_________

SCLK terminal which enables control of the external (slave side) serial I/O device. Since the

_________

SRDY terminal is not utilized in this mode, it can be used as an I/O port. Figure 5.8.3.1(a) shows the connection example of input/output terminals in the clock synchronous master mode.

1 0 1 0

Asynchronous 8-bit Asynchronous 7-bit Clock synchronous slave Clock synchronous master

to each transfer mode

Mode SIN

Input Input Input Input

SOUT SCLK SRDY

P13

Output Output Output Output

P12 P12

Input

Output

P13

Output

P13

■ Clock synchronous slave mode

In this mode, a synchronous clock from the external (master side) serial input/output device is utilized and clock synchronous 8-bit serial transfers can be performed with this serial interface as the slave.

_________

The synchronous clock is input to the SCLK terminal and is utilized by this interface as the synchronous clock.

_________

Furthermore, the SRDY signal indicating the transmit-receive ready status is output from the

_________

SRDY terminal in accordance with the serial interface operating status. In the slave mode, the settings for registers SCS0 and SCS1 used to select the clock source are invalid. Figure 5.8.3.1(b) shows the connection example of input/output terminals in the clock synchronous slave mode.

■ Asynchronous 7-bit mode

In this mode, asynchronous 7-bit transfer can be performed. Parity check during data reception and addition of parity bit (odd/even/none) during transmitting can be specified and data processed in 7 bits with or without parity. Since this mode employs the internal clock, the SCLK terminal is

_________

not used. Furthermore, since the SRDY terminal is not utilized either, both of these terminals can be used as I/O ports. Figure 5.8.3.1(c) shows the connection example of input/output terminals in the asynchronous mode.

■ Asynchronous 8-bit mode

In this mode, asynchronous 8-bit transfer can be performed. Parity check during data reception and addition of parity bit (odd/even/none) during transmitting can be specified and data processed in 8 bits with or without parity. Since this mode employs the internal clock, the SCLK terminal is

_________

62 EPSON S1C88650 TECHNICAL MANUAL

5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Serial Interface)

S1C88650

SIN(P10)

SOUT(P11)

SCLK(P12)

Input port(Kxx)

External serial device

Data input Data output CLOCK input READY output

(a) Clock synchronous master mode

S1C88650

SIN(P10)

SOUT(P11)

SCLK(P12)

SRDY(P13)

External serial device

Data input Data output CLOCK output READY input

(b) Clock synchronous slave mode

S1C88650

SIN(P10)

SOUT(P11)

External serial device

Data input Data output

Fig. 5.8.3.1 Connection examples of serial interface I/O terminals

This register setting is invalid in clock synchronous slave mode and the external clock input from the

_________

SCLK terminal is used. When the "programmable timer" is selected, the programmable timer 1 underflow signal is divided by 2 and this signal is used as the clock source. With respect to the transfer rate setting, see "5.10 Programmable Timer". At initial reset, the synchronous clock is set to "f

OSC3

/16". Whichever clock is selected, the signal is further divided by 16 and then used as the synchronous clock. Furthermore, external clock input is used as is for

_________

SCLK in clock synchronous slave mode. Table 5.8.4.2 shows an examples of transfer rates and OSC3 oscillation frequencies when the clock source is set to programmable timer. When the demultiplied signal of the OSC3 oscillation circuit is made the clock source, it is necessary to turn the OSC3 oscillation ON, prior to using the serial interface. A time interval of several msec to several 10 msec, from the turning ON of the OSC3 oscillation circuit to until the oscillation stabilizes, is necessary, due to the oscillation element that is used. Consequently,

5.8.4 Clock source

There are four clock sources and selection is made by setting the two bits of the clock source selection register SCS0 and SCS1 as shown in table below.

Table 5.8.4.1 Clock source

SCS1

1 1 0 0

Division of the synchronous clock

SCS0

1 0 1 0

Clock source

Programmable timer

Fig. 5.8.4.1

OSC3 / 4

f fOSC3 / 8

OSC3 / 16

OSC3 oscillation circuit

Programmable timer 1 underflow signal

you should allow an adequate waiting time after turning ON of the OSC3 oscillation, before starting transmitting/receiving of serial interface. (The oscillation start time will vary somewhat depending on the oscillator and on the externally attached parts. Refer to the oscillation start time example indicated in Chapter 8, "ELECTRICAL CHARACTERISTICS".) At initial reset, the OSC3 oscillation circuit is set to ON status.

OSC3

SCLK

1/4 1/8

Divider Selector Selector

1/16

1/2

(Clock synchronous slave mode)

Synchronous clock

Table 5.8.4.2 OSC3 oscillation frequencies and transfer rates

Transfer rate

(bps)

19,200

9,600 4,800 2,400 1,200

600 300 150

OSC3 oscillation frequency / Programmable timer settings

OSC3

= 2.4756 MHz f

PST1X

00H 00H 00H 00H 00H 00H 02H 02H

RDR1X

03H 07H 0FH 1FH 3FH 7FH 1FH 3FH

OSC3

= 3.0720 MHz f

PST1X

00H 00H 00H 00H 00H 00H 03H 03H

RDR1X

04H 09H 13H

27H 4FH 9FH

09H

13H

OSC3

= 3.6864 MHz

PST1X

00H 00H 00H 00H 00H 00H 01H 02H

RDR1X

05H

0BH

17H 2FH

5FH BFH BFH

5FH

∗ Since the underflow signal only is used as the clock source, the

CDR1X register value does not affect the transfer rates.

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5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Serial Interface)

5.8.5 Transmit-receive control

Below is a description of the registers which handle transmit-receive control. With respect to transmitreceive control procedures and operations, please refer to the following sections in which these are discussed on a mode by mode basis.

■ Shift register and received data buffer

Exclusive shift registers for transmitting and receiving are installed in this serial interface. Consequently, duplex communication simultaneous transmit and receive is possible when the asynchronous system is selected.

Data being transmitted are written to TRXD0– TRXD7 and converted to serial through the shift register and is output from the SOUT terminal.

In the reception section, a received data buffer is installed separate from the shift register. Data being received are input to the SIN terminal and is converted to parallel through the shift register and written to the received data buffer. Since the received data buffer can be read even during serial input operation, the continuous data is received efficiently. However, since buffer functions are not used in clock synchronous mode, be sure to read out data before the next data reception begins.

■ Transmit enable register and transmit

control bit

For transmitting control, use the transmit enable register TXEN and transmit control bit TXTRG.

The transmit enable register TXEN is used to set the transmitting enable/disable status. When "1" is written to this register to set the transmitting enable status, clock input to the shift register is enabled and the system is ready to transmit data. In the clock synchronous mode, synchronous clock input/ output from the SCLK terminal is also enabled.

The transmit control bit TXTRG is used as the trigger to start transmitting data. Data to be transmitted is written to the transmit data shift register, and when transmitting preparations a recomplete, "1" is written to TXTRG whereupon data transmitting begins. When interrupt has been enabled, an interrupt is generated when the transmission is completed. If there is subsequent data to be transmitted it can be sent using this interrupt.

_________

In addition, TXTRG can be read as the status. When set to "1", it indicates transmitting operation, and "0" indicates transmitting stop. For details on timing, see the timing chart which gives the timing for each mode.

When not transmitting, set TXEN to "0" to disable transmitting status.

■ Receive enable register, receive control bit

For receiving control, use the receive enable register RXEN and receive control bit RXTRG. Receive enable register RXEN is used to set receiving enable/disable status. When "1" is written into this register to set the receiving enable status, clock input to the shift register is enabled and the system is ready to receive data. In the clock synchronous mode, synchronous clock input/output from the

_________

SCLK terminal is also enabled. With the above setting, receiving begins and serial data input from the SIN terminal goes to the shift register. The operation of the receive control bit RXTRG is slightly different depending on whether a clock synchronous system or an asynchronous system is being used. In the clock synchronous system, the receive control bit RXTRG is used as the trigger to start receiving data. When received data has been read and the preparation for next data receiving is completed, write "1" into RXTRG to start receiving. (When "1" is written

_________

to RXTRG in slave mode, SRDY switches to "0".) In an asynchronous system, RXTRG is used to prepare for next data receiving. After reading the received data from the received data buffer, write "1" into RXTRG to signify that the received data buffer is empty. If "1" is not written into RXTRG, the overrun error flag OER will be set to "1" when the next receiving operation is completed. (An overrun error will be generated when receiving is completed between reading the received data and the writing of "1" to RXTRG.) In addition, RXTRG can be read as the status. In either clock synchronous mode or asynchronous mode, when RXTRG is set to "1", it indicates receiving operation and when set to "0", it indicates that receiving has stopped. For details on timing, see the timing chart which gives the timing for each mode.

When you do not receive, set RXEN to "0" to disable receiving status.

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5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Serial Interface)

5.8.6 Operation of clock synchronous transfer

Clock synchronous transfer involves the transfer of 8-bit data by synchronizing it to eight clocks. The same synchronous clock is used by both the transmitting and receiving sides. When the serial interface is used in the master mode, the clock signal selected using SCS0 and SCS1 is further divided by 1/16 and employed as the synchronous clock. This signal is then sent via

_________

the SCLK terminal to the slave side (external serial I/O device). When used in the slave mode, the clock input to the

_________

SCLK terminal from the master side (external serial input/output device) is used as the synchronous clock.

In the clock synchronous mode, since one clock line

_________

(SCLK) is shared for both transmitting and receiving, transmitting and receiving cannot be performed simultaneously. (Half duplex only is possible in clock synchronous mode.)

The transfer data length is fixed at 8 bits. Data can be switched using a register whether it is transmitted/received from LSB (bit 0) or MSB (bit

7).

LSB first

SCLK

Data D0 D1 D2 D3 D4 D5 D6 D7

MSB first

SCLK

Data D7 D6 D5 D4 D3 D2 D1 D0

Fig. 5.8.6.1 Transfer data configuration using

Below is a description of initialization when performing clock synchronous transfer, transmitreceive control procedures and operations. With respect to serial interface interrupt, see "5.8.8 Interrupt function".

LSB MSB

MSB LSB

clock synchronous mode

(2) Port selection

Because serial interface input/output ports SIN,

_________ _________

SOUT, SCLK and SRDY are set as I/O port terminals P10–P13 at initial reset, "1" must be written to the serial interface enable register ESIF in order to set these terminals for serial interface use.

(3) Setting of transfer mode

Select the clock synchronous mode by writing the data as indicated below to the two bits of the mode selection registers SMD0 and SMD1.

Master mode: SMD0 = "0", SMD1 = "0" Slave mode: SMD0 = "1", SMD1 = "0"

(4) Clock source selection

In the master mode, select the synchronous clock source by writing data to the two bits of the clock source selection registers SCS0 and SCS1. (See Table 5.8.4.1.) This selection is not necessary in the slave mode.

Since all the registers mentioned in (2)–(4) are assigned to the same address, it's possible to set them all with one instruction. The parity enable register EPR is also assigned to this address, however, since parity is not necessary in the clock synchronous mode, parity check will not take place regardless of how they are set.

(5) Clock source control

When the master mode is selected and programmable timer for the clock source is selected, set transfer rate on the programmable timer side. (See "5.10 Programmable Timer".) When the divided signal of OSC3 oscillation circuit is selected for the clock source, be sure that the OSC3 oscillation circuit is turned ON prior to commencing data transfer. (See "5.4 Oscillation Circuits".)

(6) Serial data input/output permutation

The S1C88650 provides the data input/output permutation select register SDP to select whether the serial data bits are transfered from the LSB or MSB. The SDP register should be set before writing data to TRXD0–TRXD7.

■ Initialization of serial interface

When performing clock synchronous transfer, the following initial settings must be made.

(1) Setting of transmitting/receiving disable

To set the serial interface into a status in which both transmitting and receiving are disabled, "0" must be written to both the transmit enable register TXEN and the receive enable register RXEN. Fix these two registers to a disable status until data transfer actually begins.

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5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Serial Interface)

■ Data transmit procedure

The control procedure and operation during transmitting is as follows.

(1) Write "0" in the transmit enable register TXEN

and the receive enable register RXEN to reset the serial interface.

(2) Write "1" in the transmit enable register TXEN

to set into the transmitting enable status.

(3) Write the transmitting data into TRXD0–

TRXD7.

(4) In case of the master mode, confirm the receive

ready status on the slave side (external serial input/output device), if necessary. Wait until it reaches the receive ready status.

(5) Write "1" in the transmit control bit TXTRG and

start transmitting. In the master mode, this control causes the

synchronous clock to change to enable and to be provided to the shift register for transmitting

_________

and output from the SCLK terminal. In the slave mode, it waits for the synchronous

_________

clock to be input from the SCLK terminal. The transmitting data of the shift register shifts one bit at a time at each falling edge of the synchronous clock and is output from the SOUT terminal. When the final bit (MSB when "LSB first" is selected, or LSB when "MSB first" is selected) is output, the SOUTx terminal is maintained at that level, until the next transmitting begins.

The transmitting complete interrupt factor flag FSTRA is set to "1" at the point where the data transmitting of the shift register is completed. When interrupt has been enabled, a transmit-

Fig. 5.8.6.2 Transmit procedure in clock synchronous mode

ting complete interrupt is generated at this point. Set the following transmitting data using this interrupt.

(6) Repeat steps (3) to (5) for the number of bytes of

transmitting data, and then set the transmit disable status by writing "0" to the transmit enable register TXEN, when the transmitting is completed.

Data transmitting

TXEN ← 0, RXEN ← 0

TXEN ← 1

Set transmitting data to TRXD0–TRXD7

Receiver ready ?

TXTRG ← 1

FSTRA = 1 ?

Transmit complete ?

TXEN ← 0

End

In case of master mode

Yes

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5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Serial Interface)

■ Data receive procedure

The control procedure and operation during receiving is as follows.

(1) Write "0" in the receive enable register RXEN

and transmit enable register TXEN to reset the serial interface.

(2) Write "1" in the receive enable register RXEN to

set into the receiving enable status.

(3) In case of the master mode, confirm the transmit

ready status on the slave side (external serial input/output device), if necessary. Wait until it reaches the transmit ready status.

(4) Write "1" in the receive control bit RXTRG and

start receiving. In the master mode, this control causes the

synchronous clock to change to enable and is provided to the shift register for receiving and

_________

output from the SCLK terminal. In the slave mode, it waits for the synchronous

_________

clock to be input from the SCLK terminal. The received data input from the SIN terminal is successively incorporated into the shift register in synchronization with the rising edge of the synchronous clock. At the point where the data of the 8th bit has been incorporated at the final (8th) rising edge of the synchronous clock, the content of the shift register is sent to the received data buffer and the receiving complete interrupt factor flag FSREC is set to "1". When interrupt has been enabled, a receiving complete interrupt is generated at this point.

(5) Read the received data from TRXD0–TRXD7

using receiving complete interrupt.

(6) Repeat steps (3) to (5) for the number of bytes of

receiving data, and then set the receive disable status by writing "0" to the receive enable register RXEN, when the receiving is completed.

Data receiving

RXEN ← 0, TXEN ← 0

RXEN ← 1

Transmitter ready ?

RXTRG ← 1

FSREC = 1 ?

Received data reading from TRXD0–TRXD7

Receiving complete ?

RXEN ← 0

Yes

In case of master mode

End

Fig. 5.8.6.3 Receiving procedure in clock synchronous mode

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5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Serial Interface)

■

Transmit/receive ready (SRDY) signal

_________

When this serial interface is used in the clock synchronous slave mode (external clock input), an

_________

SRDY signal is output to indicate whether or not this serial interface can transmit/receive to the master side (external serial input/output device).

_________

This signal is output from the SRDY terminal and when this interface enters the transmit or receive enable (READY) status, it becomes "0" (LOW level) and becomes "1" (HIGH level) when there is a BUSY status, such as during transmit/receive operation.

TXEN

TXTRG (RD)

TXTRG (WR)

SCLK

SOUT D0 D1 D2 D3 D4 D5 D6 D7

Interrupt

(a) Transmit timing for master mode

_________

The SRDY signal changes the "1" to "0," immediately after writing "1" into the transmit control bit TXTRG or the receive control bit RXTRG and returns from "0" to "1", at the point where the first synchronous clock has been input (falling edge). When you have set in the master mode, control the transfer by inputting the same signal from the slave side using the input port or I/O port. At this time,

_________

since the SRDY terminal is not set and instead P13 functions as the I/O port, you can apply this port for said control.

■ Timing chart

The timing chart for the clock synchronous system transmission is shown in Figure 5.8.6.4.

RXEN

RXTRG (RD)

RXTRG (WR)

SCLK

SIN D0 D1 D2 D3 D4 D5 D6 D7

TRXD 7F 1st data

Interrupt

TXEN

TXTRG (RD)

TXTRG (WR)

SCLK

SOUT D0 D1 D2 D3 D4 D5 D6 D7

SRDY

Interrupt

(b) Transmit timing for slave mode

Fig. 5.8.6.4 Timing chart (clock synchronous system transmission, LSB first)

RXEN

RXTRG (RD)

RXTRG (WR)

SCLK

SIN D0 D1D2D3D4D5D6D7

TRXD 7F 1st data

SRDY

Interrupt

(d) Receive timing for slave mode

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5.8.7 Operation of asynchronous transfer

Asynchronous transfer is a mode that transfers by adding a start bit and a stop bit to the front and the back of each piece of serial converted data. In this mode, there is no need to use a clock that is fully synchronized clock on the transmit side and the receive side, but rather transmission is done while adopting the synchronization at the start/stop bits that have attached before and after each piece of data. The RS-232C interface functions can be easily realized by selecting this transfer mode. This interface has separate transmit and receive shift registers and is designed to permit full duplex transmission to be done simultaneously for transmitting and receiving.

For transfer data in the asynchronous 7-bit mode, either 7 bits data (no parity) or 7 bits data + parity bit can be selected. In the asynchronous 8-bit mode, either 8 bits data (no parity) or 8 bits data + parity bit can be selected. Parity can be even or odd, and parity checking of received data and adding a party bit to transmitting data will be done automatically. Thereafter, it is not necessary to be conscious of parity itself in the program. The start bit length is fixed at 1 bit. For the stop bit length, either 1 bit or 2 bits can be selected using the stop bit select register STPB. Whether data is transmitted/received from LSB (bit 0) or MSB (bit

7) it can be switched using the data input/output

permutation select register SDP.

LSB first

Sampling clock

7bit data D0 7bit data

+parity 8bit data D0 D1 D2 D3 D4 D5 D6 D7s1 s2 8bit data

+parity

MSB first

Sampling clock

7bit data D6 7bit data

+parity 8bit data D7 8bit data

+parity

: Start bit (Low level, 1 bit)

: Stop bit (High level, 1 bit or 2 bits)

: Parity bit

Fig. 5.8.7.1 Transfer data configuration

Here following, we will explain the control sequence and operation for initialization and transmitting /receiving in case of asynchronous data transfer. See "5.8.8 Interrupt function" for the serial interface interrupts.

D1 D2 D3 D4 D5 D6s1 s2

D1 D2 D3 D4 D5 D6 ps1 s2

D1 D2 D3 D4 D5 D6 D7s1 p s2

D5 D4 D3 D2 D1 D0s1 s2

D5 D4 D3 D2 D1 D0 ps1 s2

D6 D5 D4 D3 D2 D1 D0s1 s2

D7 D6 D5 D4 D3 D2 D1 D0s1 p s2

for asynchronous system

■ Initialization of serial interface

The below initialization must be done in cases of asynchronous system transfer.

(1) Setting of transmitting/receiving disable

(2) Port selection

Because serial interface input/output terminals SIN and SOUT are set as I/O port terminals P10 and P11 at initial reset, "1" must be written to the serial interface enable register ESIF in order to set these terminals for serial interface use.

_________ _________

SCLK and SRDY terminals set in the clock synchronous mode are not used in the asynchronous mode. These terminals function as I/O port terminals P12 and P13.

(3) Setting of transfer mode

Select the asynchronous mode by writing the data as indicated below to the two bits of the mode selection registers SMD0 and SMD1.

7-bit mode: SMD0 = "0", SMD1 = "1" 8-bit mode: SMD0 = "1", SMD1 = "1"

(4) Parity bit selection

When checking and adding parity bits, write "1" into the parity enable register EPR to set to "with parity check". As a result of this setting, in the asynchronous 7-bit mode, it has a 7 bits data + parity bit configuration and in the asynchronous 8-bit mode it has an 8 bits data + parity bit configuration.In this case, parity checking for receiving and adding a party bit for transmitting is done automatically in hardware. Moreover, when "with parity check" has been selected, "odd" or "even" parity must be further selected in the parity mode selection register PMD. When "0" is written to the PMD register to select "without parity check" in the asynchronous 7-bit mode, data configuration is set to 7 bits data (no parity) and in the asynchronous 8-bit mode (no parity) it is set to 8 bits data (no parity) and parity checking and parity bit adding will not be done.

(5) Clock source selection

Select the clock source by writing data to the two bits of the clock source selection registers SCS0 and SCS1. (See Table 5.8.4.1.)

Since all the registers mentioned in (2)–(5) are assigned to the same address, it's possible to set them all with one instruction.

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5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Serial Interface)

(6) Clock source control

When the programmable timer is selected for the clock source, set transfer rate on the programmable timer side. (See "5.10 Programmable Timer".) When the divided signal of OSC3 oscillation circuit is selected for the clock source, be sure that the OSC3 oscillation circuit is turned ON prior to commencing data transfer. (See "5.4 Oscillation Circuits".)

(7) Stop bit length selection

The stop bit length can be configured to 1 bit or 2 bits using the stop bit select register STPB.

Table 5.8.7.1 Stop bit and parity bit settings

STPB

EPR

0 1

PMD

1 0 – 1 0 –

Stop bit

2 bits 2 bits 2 bits

1 bit 1 bit 1 bit

Settings

Parity bit

Odd

Even

Non parity

Odd

Even

Non parity

(8) Serial data input/output permutation

■ Data transmit procedure

The control procedure and operation during transmitting is as follows.

(1) Write "0" in the transmit enable register TXEN

to reset the serial interface.

(2) Write "1" in the transmit enable register TXEN

to set into the transmitting enable status. Write the transmitting data into TRXD0–TRXD7.

(3)

Also, when 7-bit data is selected, the TRXD7 data becomes invalid.

(4) Write "1" in the transmit control bit TXTRG and

start transmitting. This control causes the shift clock to change to enable and a start bit (LOW) is output to the SOUT terminal in synchronize to its rising edge. The transmitting data set to the shift register is shifted one bit at a time at each rising edge of the clock thereafter and is output from the SOUT terminal. After the data output, it outputs a stop bit (HIGH) and HIGH level is maintained until the next start bit is output.

The transmitting complete interrupt factor flag FSTRA is set to "1" at the point where the data transmitting is completed. When interrupt has been enabled, a transmitting complete interrupt is generated at this point. Set the following transmitting data using this interrupt.

(5) Repeat steps (3) to (4) for the number of bytes of

transmitting data, and then set the transmit disable status by writing "0" to the transmit enable register TXEN, when the transmitting is completed.

Data transmitting

TXEN ← 0

TXEN ← 1

Set transmitting data to TRXD0–TRXD7

TXTRG ← 1

FSTRA = 1 ?

Transmit complete ?

Yes

TXEN ← 0

End

Fig. 5.8.7.2 Transmit procedure in asynchronous mode

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5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Serial Interface)

■ Data receive procedure

The control procedure and operation during receiving is as follows.

Write "0" in the receive enable register RXEN to

(1)

set the receiving disable status and to reset the respective PER, OER, FER flags that indicate parity, overrun and framing errors.

(2)

Write "1" in the receive enable register RXEN to set into the receiving enable status.

(3)

The shift clock will change to enable from the point where the start bit (LOW) has been input from the SIN terminal and the receive data will be synchronized to the rising edge following the second clock, and will thus be successively incorporated into the shift register. After data bits have been incorporated, the stop bit is checked and, if it is not HIGH, it becomes a framing error and the error interrupt factor flag FSERR is set to "1". When interrupt has been enabled, an error interrupt is generated at this point. When receiving is completed, data in the shift register is transferred to the received data buffer and the receiving complete interrupt flag FSREC is set to "1". When interrupt has been enabled, a receiving complete interrupt is generated at this point. (When an overrun error is generated, the interrupt factor flag FSREC is not set to "1" and a receiving complete interrupt is not generated.) If "with parity check" has been selected, a parity check is executed when data is transferred into the received data buffer from the shift register and if a parity error is detected, the error interrupt factor flag is set to "1". When the interrupt has been enabled, an error interrupt is generated at this point just as in the framing error mentioned above.

(4)

Read the received data from TRXD0–TRXD7 using receiving complete interrupt.

Write "1" to the receive control bit RXTRG to

(5)

inform that the receive data has been read out. When the following data is received prior to writing "1" to RXTRG, it is recognized as an overrun error and the error interrupt factor flag is set to "1". When the interrupt has been enabled, an error interrupt is generated at this point just as in the framing error and parity error mentioned above.

(6)

Repeat steps (3) to (5) for the number of bytes of receiving data, and then set the receive disable status by writing "0" to the receive enable register RXEN, when the receiving is completed.

Data receiving

RXEN ← 0

Resets error flags

PER, OER and FER

RXEN ← 1

Error generated ?

Receiving interrupt ?

Received data reading from TRXD0–TRXD7

RXTRG ← 1

Receiving complete ?

RXEN ← 0

Yes

End

Yes

Error processing

Fig. 5.8.7.3 Receiving procedure in asynchronous mode

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5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Serial Interface)

■ Receive error

During receiving the following three types of errors can be detected by an interrupt.

(1) Parity error

When writing "1" to the EPR register to select "with parity check", a parity check (vertical parity check) is executed during receiving. After each data bit is sent a parity check bit is sent. The parity check bit is a "0" or a "1". Even parity checking will cause the sum of the parity bit and the other bits to be even. Odd parity causes the sum to be odd. This is checked on the receiving side. The parity check is performed when data received in the shift register is transferred to the received data buffer. It checks whether the parity check bit is a "1" or a "0" (the sum of the bits including the parity bit) and the parity set in the PMD register match. When it does not match, it is recognized as an parity error and the parity error flag PER and the error interrupt factor flag FSERR are set to "1". When interrupt has been enabled, an error interrupt is generated at this point. The PER flag is reset to "0" by writing "1". Even when this error has been generated, the received data corresponding to the error is transferred in the received data buffer and the receive operation also continues. The received data at this point cannot assured because of the parity error.

(2) Framing error

In asynchronous transfer, synchronization is adopted for each character at the start bit ("0") and the stop bit ("1"). When receiving has been done with the stop bit set at "0", the serial interface judges the synchronization to be off and a framing error is generated. When this error is generated, the framing error flag FER and the error interrupt factor flag FSERR are set to "1". When interrupt has been enabled, an error interrupt is generated at this point. The FER flag is reset to "0" by writing "1". Even when this error has been generated, the received data for it is loaded into the receive data buffer and the receive operation also continues. However, even when it does not become a framing error with the following data receipt, such data cannot be assured. Even when this error has been generated, the received data corresponding to the error is transferred in the received data buffer and the receive operation also continues. However, even when it does not become a framing error with the following data receiving, such data cannot be assured.

(3) Overrun error

When the next data is received before "1" is written to RXTRG, an overrun error will be generated, because the previous receive data will be overwritten. When this error is generated, the overrun error flag OER and the error interrupt factor flag FSERR are set to "1". When interrupt has been enabled, an error interrupt is generated at this point. The OER flag is reset to "0" by writing "1" into it. Even when this error has been generated, the received data corresponding to the error is transferred in the received data buffer and the receive operation also continues. Furthermore, when the timing for writing "1" to RXTRG and the timing for the received data transfer to the received data buffer overlap, it will be recognized as an overrun error.

■ Timing chart

Figure 5.8.7.4 show the asynchronous transfer timing chart.

72 EPSON S1C88650 TECHNICAL MANUAL

RXEN

RXTRG(RD)

RXTRG(WR) Sumpling

clock SIN

(In 8-bit mode/Non parity) TRXD

OER control signal

D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7D2 D3 D4 D5

5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Serial Interface)

TXEN

TXTRG(RD)

TXTRG(WR) Sumpling

clock SOUT

(In 8-bit mode/Non parity) Interrupt

(a) Transmit timing

D0 D1 D2 D3 D4 D5 D6 D7

1st data 2st data

OER

Interrupt

(b) Receive timing

Fig. 5.8.7.4 Timing chart (asynchronous transfer, LSB first, stop bit = 1 bit)

5.8.8 Interrupt function

This serial interface includes a function that generates the below indicated three types of interrupts.

• Transmitting complete interrupt

• Receiving complete interrupt

• Error interrupt

The interrupt factor flag FSxxx and the interrupt enable register ESxxx for the respective interrupt factors are provided and then the interrupt enable/ disable can be selected by the software. In addition, a priority level of the serial interface interrupt for the CPU can be optionally set at levels 0 to 3 by the interrupt priority registers PSIF0 and PSIF1. For details on the above mentioned interrupt control register and the operation following generation of an interrupt, see "5.14 Interrupt and Standby Status". Figure 5.8.8.1 shows the configuration of the serial interface interrupt circuit.

■ Transmitting complete interrupt

This interrupt factor is generated at the point where the sending of the data written into the shift register has been completed and sets the interrupt factor flag FSTRA to "1". When set in this manner, if the corresponding interrupt enable register ESTRA is set to "1" and the corresponding interrupt priority registers PSIF0 and PSIF1 are set to a higher level than the setting of interrupt flags (I0 and I1), an interrupt will be generated to the CPU. When "0" has been written into the interrupt enable register ESTRA and interrupt has been disabled, an interrupt is not generated to the CPU. Even in this case, the interrupt factor flag FSTRA is set to "1". The interrupt factor flag FSTRA is reset to "0" by writing "1". The following transmitting data can be set and the transmitting start (writing "1" to TXTRG) can be controlled by generation of this interrupt factor. The exception processing vector address is set as follows:

Transmitting complete interrupt: 00002CH

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Interrupt priority

Address

Error generation

Receive completion

Data bus

Transmit completion

Address

Interrupt factor flag FSERR

Interrupt enable register ESERR

Interrupt factor flag FSREC

Interrupt enable register ESREC

Interrupt factor flag FSTRA

Interrupt enable register ESTRA

Fig. 5.8.8.1 Configuration of serial interface interrupt circuit

■ Receiving complete interrupt

This interrupt factor is generated at the point where receiving has been completed and the receive data incorporated into the shift register has been transferred into the received data buffer and it sets the interrupt factor flag FSREC to "1". When set in this manner, if the corresponding interrupt enable register ESREC is set to "1" and the corresponding interrupt priority registers PSIF0 and PSIF1 are set to a higher level than the setting of interrupt flags (I0 and I1), an interrupt will be generated to the CPU. When "0" has been written into the interrupt enable register ESREC and interrupt has been disabled, an interrupt is not generated to the CPU. Even in this case, the interrupt factor flag FSREC is set to "1". The interrupt factor flag FSREC is reset to "0" by writing "1".

The generation of this interrupt factor permits the received data to be read.

Also, the interrupt factor flag is set to "1" when a parity error or framing error is generated.

The exception processing vector address is set as follows:

Receiving complete interrupt: 00002AH.

Interrupt priority level judgement circuit

Interrupt request

■ Error interrupt

This interrupt factor is generated at the point where a parity error, framing error or overrun error is detected during receiving and it sets the interrupt factor flag FSERR to "1". When set in this manner, if the corresponding interrupt enable register ESERR is set to "1" and the corresponding interrupt priority registers PSIF0 and PSIF1 are set to a higher level than the setting of interrupt flags (I0 and I1), an interrupt will be generated to the CPU. When "0" has been written in the interrupt enable register ESERR and interrupt has been disabled, an interrupt is not generated to the CPU. Even in this case, the interrupt factor flag FSERR is set to "1". The interrupt factor flag FSERR is reset to "0" by writing "1".

Since all three types of errors result in the same interrupt factor, you should identify the error that has been generated by the error flags PER (parity error), OER (overrun error) and FER (framing error).

The exception processing vector address is set as follows:

Receive error interrupt: 000028H.

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5.8.9 Control of serial interface

Table 5.8.9.1 show the serial interface control bits.

Table 5.8.9.1(a) Serial interface control bits

Address Bit Name SR R/WFunction Comment10

00FF48 D7

00FF49 D7

00FF4A D7

00FF4B D7

D6 D5 D4

D2 D1

D6 D5 D4 D3 D2 D1 D0

– EPR PMD SCS1

SCS0

SMD1

SMD0

ESIF – FER

PER

OER

RXTRG

RXEN TXTRG

TXEN TRXD7 TRXD6 TRXD5 TRXD4 TRXD3 TRXD2 TRXD1 TRXD0 – – – – – – STPB SDP

– Parity enable register Parity mode selection Clock source selection

SCS1

SCS0

Clock source Programmable timer fOSC3 / 4 fOSC3 / 8 fOSC3 / 16

Serial I/F mode selection

SMD1

SMD0

Asynchronous 8-bit

Asynchronous 7-bit

Clock synchronous slave

Clock synchronous master

Mode

Serial I/F enable register – Serial I/F framing error flag

Serial I/F parity error flag

Serial I/F overrun error flag

Serial I/F receive trigger/status

W Serial I/F receive enable Serial I/F transmit trigger/status

W Serial I/F transmit enable Serial I/F transmit/Receive data D7 (MSB) Serial I/F transmit/Receive data D6 Serial I/F transmit/Receive data D5 Serial I/F transmit/Receive data D4 Serial I/F transmit/Receive data D3 Serial I/F transmit/Receive data D2 Serial I/F transmit/Receive data D1 Serial I/F transmit/Receive data D0 (LSB) – – – – – – Serial I/F stop bit selection Serial I/F data input/output permutation selection

–

With parity

Odd

Serial I/F

–

Error

Reset (0)

Error

Reset (0)

Error

Reset (0)

Run

Trigger

Enable

Run

Trigger

Enable

– – – – – –

2 bits

MSB first

–

Non parity

Even

I/O port

–

No error

No operation

No error

No operation

No error

No operation

Stop

No operation

Disable

Stop

No operation

Disable

– – – – – –

1 bit

LSB first

– 0

R/W

R/W – 0

R/W

R/W 0

R/W

X R/WHigh Low

– – – – – – 00R/W

R/W

"0" when being read Only for

asynchronous mode

In the clock synchronous slave mode, external clock is selected.

"0" when being read Only for

asynchronous mode

Constantly "0" when being read

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Table 5.8.9.1(b) Serial interface control bits

Address Bit Name SR R/WFunction Comment10

00FF20 D7

00FF23 –

00FF27 D7

D6 D5 D4 D3 D2 D1

D7 D6 D5 D4 D3 D2 D1 D0

D6 D5 D4 D3 D2 D1 D0

PK01 PK00 PSIF1 PSIF0 – – PTM1

PTM0

– – – – ESERR ESREC ESTRA – – – – – FSERR FSREC FSTRA

K00–K07 interrupt priority register

Serial interface interrupt priority register

– – Clock timer interrupt priority register

– – – – – Serial I/F (error) interrupt enable register Serial I/F (receiving) interrupt enable register Serial I/F (transmitting) interrupt enable register – – – – – Serial I/F (error) interrupt factor flag Serial I/F (receiving) interrupt factor flag Serial I/F (transmitting) interrupt factor flag

PK01

PSIF1

1 1 0 0

– –

PTM1

1 1 0 0

– – – – –

Interrupt

enable

– – – – –

(R)

Generated

(W)

Reset

PK00 PSIF0

1 0 1 0

PTM0

1 0 1 0

Priority

level Level 3 Level 2 Level 1 Level 0

– –

Priority level

Level 3 Level 2 Level 1 Level 0

– – – – –

Interrupt

disable

– – – – –

(R)

No generated

(W)

No operation

R/W

– – 0

R/W

– – – – –

R/W

– – – – –

0 R/W

Constantly "0" when being read

ESIF: 00FF48H•D0

Sets the serial interface terminals (P10–P13).

When "1" is written: When "0" is written: I/O port terminal Reading: Valid

The ESIF is the serial interface enable register and P10–P13 terminals become serial input/output terminals (SIN, SOUT, SCLK, SRDY) when "1" is written, and they become I/O port terminals when "0" is written. Also, see Table 5.8.3.2 for the terminal settings according to the transfer modes. At initial reset, ESIF is set to "0" (I/O port).

Serial input/output terminal

_________ _________

SMD0, SMD1: 00FF48H•D1, D2

Set the transfer modes according to Table 5.8.9.2.

Table 5.8.9.2 Transfer mode settings

SMD1 SMD0 Mode

1 1 0 0

SMD0 and SMD1 can also read out. At initial reset, this register is set to "0" (clock synchronous master mode).

1 0 1 0

Asynchronous 8-bit Asynchronous 7-bit Clock synchronous slave Clock synchronous master

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SCS0, SCS1: 00FF48H•D3, D4

Select the clock source according to Table 5.8.9.3.

Table 5.8.9.3 Clock source selection

SCS1

1 1 0 0

SCS0

1 0 1 0

Clock source

Programmable timer

OSC3 / 4

f fOSC3 / 8

OSC3 / 16

SCS0 and SCS1 can also be read out. In the clock synchronous slave mode, setting of this register is invalid. At initial reset, this register is set to "0" (fOSC3/16).

SDP: 00FF4BH•D0

Selects the serial data input/output permutation.

When "1" is written: MSB first When "0" is written: LSB first Reading: Valid

Select whether the data input/output permutation will be MSB first or LSB first. At initial reset, SDP is set to "0" (LSB first).

STPB: 00FF4BH•D1

Selects the stop bit length for asynchronous data transfer.

When "1" is written: 2 bits When "0" is written: 1 bit Reading: Valid

STPB is the stop bit select register that is effective in asynchronous mode. When "1" is written to STPB, the stop bit length is set to 2 bits, and when "0" is written, it is set to 1 bit. In clock synchronous mode, no start/stop bits can be added to transfer data. Therefore, setting STPB becomes invalid. At initial reset, STPB is set to "0" (1 bit).

EPR: 00FF48H•D6

Selects the parity function.

When "1" is written: With parity When "0" is written: Non parity Reading: Valid

Selects whether or not to check parity of the received data and to add a parity bit to the transmitting data. When "1" is written to EPR, the most significant bit of the received data is considered to be the parity bit and a parity check is executed. A parity bit is added to the transmitting data. When "0" is written, neither checking is done nor is a parity bit added. Parity is valid only in asynchronous mode and the EPR setting becomes invalid in the clock synchronous mode. At initial reset, EPR is set to "0" (non parity).

PMD: 00FF48H•D5

Selects odd parity/even parity.

When "1" is written: Odd parity When "0" is written: Even parity Reading: Valid

When "1" is written to PMD, odd parity is selected and even parity is selected when "0" is written. The parity check and addition of a parity bit is only valid when "1" has been written to EPR. When "0" has been written to EPR, the parity setting by PMD becomes invalid. At initial reset, PMD is set to "0" (even parity).

TXEN: 00FF49H•D0

Sets the serial interface to the transmitting enable status.

When "1" is written: Transmitting enable When "0" is written: Transmitting disable Reading: Valid

When "1" is written to TXEN, the serial interface shifts to the transmitting enable status and shifts to the transmitting disable status when "0" is written. Set TXEN to "0" when making the initial settings of the serial interface and similar operations. At initial reset, TXEN is set to "0" (transmitting disable).

TXTRG: 00FF49H•D1

Functions as the transmitting start trigger and the operation status indicator (transmitting/stop status).

When "1" is read: During transmitting When "0" is read: During stop

When "1" is written: Transmitting start When "0" is written: Invalid

Starts the transmitting when "1" is written to TXTRG after writing the transmitting data. TXTRG can be read as the status. When set to "1", it indicates transmitting operation, and "0" indicates transmitting stop. At initial reset, TXTRG is set to "0" (during stop).

RXEN: 00FF49H•D2

Sets the serial interface to the receiving enable status.

When "1" is written: Receiving enable When "0" is written: Receiving disable Reading: Valid

When "1" is written to RXEN, the serial interface shifts to the receiving enable status and shifts to the receiving disable status when "0" is written. Set RXEN to "0" when making the initial settings of the serial interface and similar operations. At initial reset, RXEN is set to "0" (receiving disable).

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RXTRG: 00FF49H•D3

Functions as the receiving start trigger or preparation for the following data receiving and the operation status indicator (during receiving/during stop).

When "1" is read: During receiving When "0" is read: During stop

When "1" is written: Receiving start/following

data receiving preparation

When "0" is written: Invalid

RXTRG has a slightly different operation in the clock synchronous system and the asynchronous system.

The RXTRG in the clock synchronous system, is used as the trigger for the receiving start. Writes "1" into RXTRG to start receiving at the point where the receive data has been read and the following receive preparation has been done. (In

_________

the slave mode, SRDY becomes "0" at the point where "1" has been written into into the RXTRG.)

RXTRG is used in the asynchronous system for preparation of the following data receiving. Reads the received data located in the received data buffer and writes "1" into RXTRG to inform that the received data buffer has shifted to empty. When "1" has not been written to RXTRG, the overrun error flag OER is set to "1" at the point where the following receiving has been completed. (When the receiving has been completed between the operation to read the received data and the operation to write "1" into RXTRG, an overrun error occurs.)

In addition, RXTRG can be read as the status. In either clock synchronous mode or asynchronous mode, when RXTRG is set to "1", it indicates receiving operation and when set to "0", it indicates that receiving has stopped. At initial reset, RXTRG is set to "0" (during stop).

TRXD0–TRXD7: 00FF4AH

During transmitting

Write the transmitting data into the transmit shift register.

When "1" is written: HIGH level When "0" is written: LOW level

Write the transmitting data prior to starting transmitting. In the case of continuous transmitting, wait for the transmitting complete interrupt, then write the data. The TRXD7 becomes invalid for the asynchronous 7-bit mode. Converted serial data for which the bits set at "1" as HIGH (VDD) level and for which the bits set at "0" as LOW (VSS) level are output from the SOUT terminal.

During receiving

Read the received data.

When "1" is read: HIGH level When "0" is read: LOW level

The data from the received data buffer can be read out. Since the sift register is provided separately from this buffer, reading can be done during the receive operation in the asynchronous mode. (The buffer function is not used in the clock synchronous mode.) Read the data after waiting for the receiving complete interrupt. When performing parity check in the asynchronous 7-bit mode, "0" is loaded into the 8th bit (TRXD7) that corresponds to the parity bit. The serial data input from the SIN terminal is level converted, making the HIGH (VDD) level bit "1" and the LOW (VSS) level bit "0" and is then loaded into this buffer. At initial reset, the buffer content is undefined.

OER: 00FF49H•D4

Indicates the generation of an overrun error.

When "1" is read: Error When "0" is read: No error

When "1" is written: Reset to "0" When "0" is written: Invalid

OER is an error flag that indicates the generation of an overrun error and becomes "1" when an error has been generated. An overrun error is generated when the receiving of data has been completed prior to the writing of "1" to RXTRG in the asynchronous mode. OER is reset to "0" by writing "1". At initial reset and when RXEN is "0", OER is set to "0" (no error).

PER: 00FF49H•D5

Indicates the generation of a parity error.

When "1" is read: Error When "0" is read: No error

When "1" is written: Reset to "0" When "0" is written: Invalid

PER is an error flag that indicates the generation of a parity error and becomes "1" when an error has been generated. When a parity check is performed in the asynchronous mode, if data that does not match the parity is received, a parity error is generated. PER is reset to "0" by writing "1". At initial reset and when RXEN is "0", PER is set to "0" (no error).

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FER: 00FF49H•D6

Indicates the generation of a framing error.

When "1" is read: Error When "0" is read: No error

When "1" is written: Reset to "0" When "0" is written: Invalid

FER is an error flag that indicates the generation of a framing error and becomes "1" when an error has been generated. When the stop bit for the receiving of the asynchronous mode has become "0", a framing error is generated. FER is reset to "0" by writing "1". At initial reset and when RXEN is "0", FER is set to "0" (no error).

PSIF0, PSIF1: 00FF20H•D4, D5

Sets the priority level of the serial interface interrupt. The two bits PSIF0 and PSIF1 are the interrupt priority register corresponding to the serial interface interrupt. Table 5.8.9.4 shows the interrupt priority level which can be set by this register.

Table 5.8.9.4 Interrupt priority level settings

PSIF1 PSIF0 Interrupt priority level

1 1 0 0

1 0 1 0

Level 3 (IRQ3) Level 2 (IRQ2) Level 1 (IRQ1) Level 0 (None)

At initial reset, this register is set to "0" (level 0).

ESTRA, ESREC, ESERR: 00FF23H•D0, D1, D2

Enables or disables the generation of an interrupt for the CPU.

When "1" is written: Interrupt enabled When "0" is written: Interrupt disabled Reading: Valid

ESTRA, ESREC and ESERR are interrupt enable registers that respectively correspond to the interrupt factors for transmitting complete, receiving complete and receiving error. Interrupts set to "1" are enabled and interrupts set to "0" are disabled. At initial reset, this register is set to "0" (interrupt disabled).

FSTRA, FSREC, FSERR: 00FF27H•D0, D1, D2

Indicates the serial interface interrupt generation status.

When "1" is read: Interrupt factor present When "0" is read:

When "1" is written: Resets factor flag When "0" is written: Invalid

FSTRA, FSREC and FSERR are interrupt factor flags that respectively correspond to the interrupts for transmitting complete, receiving complete and receiving error and are set to "1" by generation of each factor. Transmitting complete interrupt factor is generated at the point where the data transmitting of the shift register has been completed. Receiving complete interrupt factor is generated at the point where the received data has been transferred into the received data buffer. Receive error interrupt factor is generated when a parity error, framing error or overrun error has been detected during data receiving. When set in this manner, if the corresponding interrupt enable register is set to "1" and the corresponding interrupt priority register is set to a higher level than the setting of interrupt flags (I0 and I1), an interrupt will be generated to the CPU. Regardless of the interrupt enable register and interrupt priority register settings, the interrupt factor flag will be set to "1" by the occurrence of an interrupt generation condition. To accept the subsequent interrupt after interrupt generation, re-setting of the interrupt flags (set interrupt flag to lower level than the level indicated by the interrupt priority registers, or execute the RETE instruction) and interrupt factor flag reset are necessary. The interrupt factor flag is reset to "0" by writing "1". At initial reset, this flag is reset to "0".

Interrupt factor not present

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5.8.10 Programming notes

(1)

Be sure to initialize the serial interface mode in the transmitting/receiving disable status (TXEN = RXEN = "0").

(2)

Do not perform double trigger (writing "1") to TXTRG (RXTRG) when the serial interface is in the transmitting (receiving) operation. Furthermore, do not execute the SLP instruction. (When executing the SLP instruction, set TXEN = RXEN = "0".)

(3) In the clock synchronous mode, since one clock

(4)

_________

line (SCLK) is shared for both transmitting and receiving, transmitting and receiving cannot be performed simultaneously. (Half duplex only is possible in clock synchronous mode.) Consequently, be sure not to write "1" to RXTRG (TXTRG) when TXTRG (RXTRG) is "1".

When a parity error or flaming error is generated during receiving in the asynchronous mode, the receiving error interrupt factor flag FSERR is set to "1" prior to the receiving complete interrupt factor flag FSREC for the time indicated in Table

5.8.10.1.

Consequently, when an error is generated, you should reset the receiving complete interrupt factor flag FSREC to "0" by providing a wait time in error processing routines and similar routines. When an overrun error is generated, the receiving complete interrupt factor flag FSREC is not set to "1" and a receiving complete interrupt is not generated.

Table 5.8.10.1 Time difference between FSERR

and FSREC on error generation

Clock source Time difference

fOSC3 / n Programmable timer

1/2 cycles of fOSC3 / n 1 cycle of timer 1 underflow

(5)

When the demultiplied signal of the OSC3 oscillation circuit is made the clock source, it is necessary to turn the OSC3 oscillation ON, prior to using the serial interface. A time interval of several msec to several 10 msec, from the turning ON of the OSC3 oscillation circuit to until the oscillation stabilizes, is necessary, due to the oscillation element that is used. Consequently, you should allow an adequate waiting time after turning ON of the OSC3 oscillation, before starting transmitting/receiving of serial interface. (The oscillation start time will vary somewhat depending on the oscillator and on the externally attached parts. Refer to the oscillation start time example indicated in Chapter 8, "ELECTRICAL CHARACTERISTICS".) At initial reset, the OSC3 oscillation circuit is set to ON status.

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5.9 Clock Timer

5.9.1 Configuration of clock timer

The S1C88650 has built in a clock timer that uses the OSC1 oscillation circuit as clock source. The clock timer is composed of an 8-bit binary counter that uses the 256 Hz signal dividing fOSC1 as its input clock and can read the data of each bit (128–1 Hz) by software. Normally, this clock timer is used for various timing functions such as clocks. The configuration of the clock timer is shown in Figure 5.9.1.1.

5.9.2 Interrupt function

The clock timer can generate an interrupt by each of the 32 Hz, 8 Hz, 2 Hz and 1 Hz signals. The configuration of the clock timer interrupt circuit is shown in Figure 5.9.2.1.

Interrupts are generated by respectively setting the corresponding interrupt factor flags FTM32, FTM8, FTM2 and FTM1 at the falling edge of the 32 Hz, 8 Hz, 2 Hz and 1 Hz signals to "1". Interrupt can be prohibited by the setting the interrupt enable registers ETM32, ETM8, ETM2 and ETM1 corresponding to each interrupt factor flag. In addition, a priority level of the clock timer interrupt for the CPU can be optionally set at levels 0 to 3 by the interrupt priority registers PTM0 and PTM1. For details on the above mentioned interrupt control register and the operation following generation of an interrupt, see "5.14 Interrupt and Standby Status".

The exception processing vector addresses for each interrupt factor are respectively set as shown below.

32 Hz interrupt: 000034H 8 Hz interrupt: 000036H 2 Hz interrupt: 000038H 1 Hz interrupt: 00003AH

Figure 5.9.2.2 shows the timing chart for the clock timer.

OSC1 oscillation circuit

fOSC1 256 Hz

Divider

TMRST TMRUN

Clock timer reset Clock timer Run/Stop

Data bus

Clock timer

64Hz32Hz16Hz8Hz4Hz2Hz1

128

Interrupt control circuit

TMD0–TMD7

Fig. 5.9.1.1 Configuration of clock timer

Interrupt request

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Interrupt priority

Address

32 Hz falling edge

8 Hz falling edge

Data bus

2 Hz falling edge

1 Hz falling edge

Address

Interrupt factor flag FTM32

Interrupt enable register ETM32

Interrupt factor flag FTM8

Interrupt enable register ETM8

Interrupt factor flag FTM2

Interrupt enable register ETM2

Interrupt factor flag FTM1

Interrupt enable register ETM1

Interrupt priority level judgement circuit

Interrupt request

OSC1/128

TMD0 TMD1 TMD2 TMD3 TMD4 TMD5 TMD6 TMD7

32 Hz interrupt

8 Hz interrupt 2 Hz interrupt 1 Hz interrupt

Fig. 5.9.2.1 Configuration of clock timer interrupt circuit

256 Hz 128 Hz

64 Hz 32 Hz 16 Hz

8 Hz 4 Hz 2 Hz 1 Hz

Fig. 5.9.2.2 Timing chart of clock timer

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5.9.3 Control of clock timer

Table 5.9.3.1 shows the clock timer control bits.

Table 5.9.3.1 Clock timer control bits

Address Bit Name SR R/WFunction Comment10

00FF40

D3 D2 D1 D0

00FF41 D7

D6 D5 D4 D3 D2 D1 D0

00FF20 D7

D6 D5 D4 D3 D2 D1

00FF22 D7

D6 D5 D4 D3 D2 D1 D0

00FF26 D7

D6 D5 D4 D3 D2 D1 D0

WDEN FOUT2

FOUT1

FOUT0

FOUTON WDRST TMRST TMRUN TMD7 TMD6 TMD5 TMD4 TMD3 TMD2 TMD1 TMD0 PK01 PK00 PSIF1 PSIF0 – – PTM1

PTM0

– – – – ETM32 ETM8 ETM2 ETM1 – – – – FTM32 FTM8 FTM2 FTM1

Watchdog timer enable FOUT frequency selection

FOUT2

FOUT1

0 0 0 0 1 1 1 1

FOUT0

0 0 1 1 0 0 1 1

Frequency

0 1 0 1 0 1 0 1

OSC1 OSC1

f f

OSC1 OSC1

OSC3

f f

OSC3

/ 1 / 2 / 4 / 8 / 1 / 2 / 4 / 8

1 Hz 2 Hz 4 Hz

8 Hz 16 Hz 32 Hz 64 Hz

128 Hz

K00–K07 interrupt priority register

Serial interface interrupt priority register

– – Clock timer interrupt priority register

– – – – Clock timer 32 Hz interrupt enable register Clock timer 8 Hz interrupt enable register Clock timer 2 Hz interrupt enable register Clock timer 1 Hz interrupt enable register – – – – Clock timer 32 Hz interrupt factor flag Clock timer 8 Hz interrupt factor flag Clock timer 2 Hz interrupt factor flag Clock timer 1 Hz interrupt factor flag

Enable

On Reset Reset

Run

High Low

PK01

PK00

PSIF1

PSIF0

– –

PTM1

PTM0

– – – –

Interrupt

enable

– – – –

(R)

Generated

(W)

Reset

Disable

Off No operation No operation

Stop

Priority

level Level 3 Level 2 Level 1 Level 0

– –

Priority level

Level 3 Level 2 Level 1 Level 0

– – – –

Interrupt

disable

– – – –

(R)

Not generated

(W)

No operation

R/W

–

R/W

– – 0

R/W

– – – –

0 R/W

– – – –

0 R/W

Constantly "0" when being read

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TMD0–TMD7: 00FF41H

The clock timer data can be read out. Each bit of TMD0–TMD7 and frequency correspondence are as follows:

TMD0: 128 Hz TMD4: 8 Hz TMD1: 64 Hz TMD5: 4 Hz TMD2: 32 Hz TMD6: 2 Hz TMD3: 16 Hz TMD7: 1 Hz

Since the TMD0–TMD7 is exclusively for reading, the write operation is invalid. At initial reset, the timer data is set to "00H".

TMRST: 00FF40H•D1

Resets the clock timer.

When "1" is written: Clock timer reset When "0" is written: No operation Reading: Always "0"

The clock timer is reset by writing "1" to the TMRST. When the clock timer is reset in the RUN status, it restarts immediately after resetting. In the case of the STOP status, the reset data "00H" is maintained. No operation results when "0" is written to the TMRST. Since the TMRST is exclusively for writing, it always becomes "0" during reading.

TMRUN: 00FF40H•D0

Controls RUN/STOP of the clock timer.

When "1" is written: RUN When "0" is written: STOP Reading: Valid

The clock timer starts up-counting by writing "1" to the TMRUN and stops by writing "0". In the STOP status, the count data is maintained until it is reset or set in the next RUN status. Also, when the STOP status changes to the RUN status, the data that was maintained can be used for resuming the count. At initial reset, the TMRUN is set to "0" (STOP).

PTM0, PTM1: 00FF20H•D0, D1

Sets the priority level of the clock timer interrupt. The two bits PTM0 and PTM1 are the interrupt priority register corresponding to the clock timer interrupt. Table 5.9.3.2 shows the interrupt priority level which can be set by this register.

Table 5.9.3.2 Interrupt priority level settings

PTM1 PTM0 Interrupt priority level

1 1 0 0

1 0 1 0

Level 3 (IRQ3) Level 2 (IRQ2) Level 1 (IRQ1) Level 0 (None)

ETM1, ETM2, ETM8, ETM32: 00FF22H•D0–D3

Enables or disables the generation of an interrupt for the CPU.

When "1" is written: Interrupt enabled When "0" is written: Interrupt disabled Reading: Valid

The ETM1, ETM2, ETM8 and ETM32 are interrupt enable registers that respectively correspond to the interrupt factors for 1 Hz, 2 Hz, 8 Hz and 32 Hz. Interrupts set to "1" are enabled and interrupts set to "0" are disabled. At initial reset, this register is set to "0" (interrupt disabled).

FTM1, FTM2, FTM8, FTM32: 00FF26H•D0–D3

Indicates the clock timer interrupt generation status.

When "1" is read: Interrupt factor present When "0" is read:

When "1" is written: Resets factor flag When "0" is written: Invalid

The FTM1, FTM2, FTM8 and FTM32 are interrupt factor flags that respectively correspond to the interrupts for 1 Hz, 2 Hz, 8 Hz and 32 Hz and are set to "1" at the falling edge of each signal. When set in this manner, if the corresponding interrupt enable register is set to "1" and the corresponding interrupt priority register is set to a higher level than the setting of interrupt flags (I0 and I1), an interrupt will be generated to the CPU. Regardless of the interrupt enable register and interrupt priority register settings, the interrupt factor flag will be set to "1" by the occurrence of an interrupt generation condition. To accept the subsequent interrupt after interrupt generation, re-setting of the interrupt flags (set interrupt flag to lower level than the level indicated by the interrupt priority registers, or execute the RETE instruction) and interrupt factor flag reset are necessary. The interrupt factor flag is reset to "0" by writing "1". At initial reset, this flag is reset to "0".

Interrupt factor not present

At initial reset, this register is set to "0" (level 0).

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5.9.4 Programming notes

(1) The clock timer is actually made to RUN/STOP

in synchronization with the falling edge of the 256 Hz signal after writing to the TMRUN register. Consequently, when "0" is written to the TMRUN, the timer shifts to STOP status when the counter is incremented "1". The TMRUN maintains "1" for reading until the timer actually shifts to STOP status. Figure 5.9.4.1 shows the timing chart of the RUN/STOP control.

256 Hz

TMRUN(RD)

TMRUN(WR)

TMDX 57H 58H 59H 5AH 5BH 5CH

Fig. 5.9.4.1 Timing chart of RUN/STOP control

(2) The SLP instruction is executed when the clock

timer is in the RUN status (TMRUN = "1"). The clock timer operation will become unstable when returning from SLEEP status. Therefore, when shifting to SLEEP status, set the clock timer to STOP status (TMRUN = "0") prior to executing the SLP instruction.

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5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Programmable Timer)

5.10 Programmable Timer

5.10.1 Configuration of programmable timer

The S1C88650 has four built-in 16-bit programmable timer systems. Each system timer consists of a 16-bit presettable down counter, and can be used as 16-bit × 1 channel or 8-bit × 2 channels of programmable timer. Furthermore, they function as event counters using the input port terminal. Figures 5.10.1.1 and 5.10.1.2 shows the configuration of the 16-bit programmable timers.

fOSC3/fOSC1

Input port (K04)

Clock output

Underflow

interrupt

Compare match

interrupt

fOSC3/fOSC1

Input port (K04)

Clock output

To serial I/F

Underflow

interrupt

Compare match

interrupt

Prescaler/clock

control circuit

Clock output circuit

Interrupt circuit

Prescaler/clock

control circuit

Clock output circuit

Interrupt circuit

INCL0

EXCL0

TOUT0

INCL1

EXCL0

TOUT1

Clock selection

circuit

Control circuit

Underflow signal

Clock selection

circuit

Control circuit

Two 8-bit down counters, the reload data register and compare data register corresponding to each down counter are arranged in the 16-bit programmable timer. The reload data register is used to set an initial value to the down counter. The compare data register stores data for comparison with the content of the down counter. By setting these registers, a PWM waveform is generated and it can be output to external devices as the TOUT0, 1, 2 or 3 signal. Furthermore, the serial interface clock is generated from the Timer 1 underflow signal. The Timer 5 underflow signal can be used to set the frame frequency for the LCD driver.

Timer 0

8-bit reload data register (RDR0)

Underflow

Compare match

Underflow

Compare match

8-bit down counter (PTM0)

Comparator

8-bit compare data register (CDR0)

Timer 0 control registers

Timer 1

8-bit reload data register (RDR1)

8-bit down counter (PTM1)

Comparator

8-bit compare data register (CDR1)

Timer 1 control registers

fOSC3/fOSC1

Input port (K05)

Clock output

Underflow

interrupt

Compare match

interrupt

fOSC3/fOSC1

Input port (K05)

Clock output

Underflow

interrupt

Compare match

interrupt

Prescaler/clock

control circuit

Clock output circuit

Interrupt circuit

Prescaler/clock

control circuit

Clock output circuit

Interrupt circuit

INCL2

EXCL1

TOUT2

INCL3

EXCL1

TOUT3

Clock selection

circuit

Control circuit

Underflow signal

Clock selection

circuit

Control circuit

Underflow

Compare match

Underflow

Compare match

Timer 2

8-bit reload data register (RDR2)

8-bit down counter (PTM2)

Comparator

8-bit compare data register (CDR2)

Timer 2 control registers

Timer 3

8-bit reload data register (RDR3)

8-bit down counter (PTM3)

Comparator

8-bit compare data register (CDR3)

Timer 3 control registers

Data bus

Fig. 5.10.1.1 Configuration of 16-bit programmable timer (Timers 1–3)

86 EPSON S1C88650 TECHNICAL MANUAL

5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Programmable Timer)

OSC3/fOSC1

Input port (K06)

Underflow

interrupt

Compare match

interrupt

OSC3/fOSC1

Input port (K06)

To LCD driver

Underflow

interrupt

Compare match

interrupt

OSC3/fOSC1

Input port (K07)

Underflow

interrupt

Compare match

interrupt

Prescaler/clock

control circuit

Interrupt circuit

Prescaler/clock

control circuit

Interrupt circuit

Prescaler/clock

control circuit

Interrupt circuit

INCL4

EXCL2

INCL5

EXCL2

INCL6

EXCL3

Clock selection

circuit

Control circuit

Underflow signal

Clock selection

circuit

Control circuit

Clock selection

circuit

Control circuit

Underflow

Compare match

Underflow

Compare match

Underflow

Compare match

Timer 4

8-bit reload data register (RDR4)

8-bit down counter (PTM4)

Comparator

8-bit compare data register (CDR4)

Timer 4 control registers

Timer 5

8-bit reload data register (RDR5)

8-bit down counter (PTM5)

Comparator

8-bit compare data register (CDR5)

Timer 5 control registers

Timer 6

8-bit reload data register (RDR6)

8-bit down counter (PTM6)

Comparator

8-bit compare data register (CDR6)

Data bus

Underflow signal

OSC3/fOSC1

Input port (K07)

Underflow

interrupt

Compare match

interrupt

Prescaler/clock

control circuit

Interrupt circuit

INCL7

EXCL3

Clock selection

circuit

Control circuit

Fig. 5.10.1.2 Configuration of 16-bit programmable timer (Timers 4–7)

5.10.2 Operation mode

Timers 0 and 1, Timers 2 and 3, Timers 4 and 5, or Timers 6 and 7 can be used as two channels of 8-bit timers or one channel of 16-bit timer. Two kinds of operation modes are provided corresponding to this configuration, and it can be selected by the 8/ 16-bit mode selection registers MODE16_A (for Timer 0–1) through MODE16_D (for Timer 6–7). When "0" is set to the MODE16_A register, Timers 0 and 1 enter the 8-bit mode (8-bit × 2 channels) and when "1" is set, they enter the 16-bit mode (16-bit × 1 channel).

Timer 6 control registers

Timer 7

8-bit reload data register (RDR7)

Underflow

Compare match

8-bit down counter (PTM7)

Comparator

8-bit compare data register (CDR7)

Timer 7 control registers

In the 8-bit mode, Timers 0 and 1 can be controlled individually. In the 16-bit mode, the underflow signal of Timer 0 is used as the input clock of Timer 1 so that the down counters operate as a 16-bit counter. The timer in the 16-bit mode is controlled with the control registers for Timer 0 except for the clock output. MODE16_B through MODE16_D have the same function.

Figure 5.10.2.1 shows the timer configuration depending on the operation mode and Table

5.10.2.1 shows the configuration of the control registers.

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5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Programmable Timer)

Timer 0 input clock

Timer 1 input clock

00FF30

D6 D5 D4 D3 D2 D1 D0

00FF31 D7

D6 D5 D4 D3 D2 D1 D0

[8-bit mode]

8-bit data

Timer 0

Timer 1

Interrupt request TOUT output

Timer 0 input clock

Timer 0 underflow signal

[16-bit mode]

Low-order 8-bit data

Timer 0

Timer 1

Interrupt request TOUT output

8-bit data High-order 8-bit data

Fig. 5.10.2.1 Counter configuration in 8- and 16-bit mode (example of Timers 0 and 1)

Table 5.10.2.1(a) Control registers in 8-bit mode (example of Timers 0 and 1)

SR R/WAddress Bit Name Function Comment10 MODE16_A PTNREN_A – – PTOUT0 PTRUN0 PSET0 CKSEL0 – – – – PTOUT1 PTRUN1 PSET1 CKSEL1

16-bit x 1

Enable

– 1

Run

Preset

External clock

– – – 1

Run

Preset

External clock

bit x 2

Disable

Stop No operation Internal clock

Off

R/W

–

0 0 0 0 –

–

0 0 0 0

"0" when being read

R/W

Reserved register

R/W R/W

"0" when being read

R/W

Constantly "0" when being read

R/W

Reserved register

R/W R/W

"0" when being read

R/W

Table 5.10.2.1(b) Control registers in 16-bit mode (example of Timers 0 and 1)

SR R/WAddress Bit Name Function Comment10

00FF30

00FF31 D7

MODE16_A

PTNREN_A

–

PTOUT0

PTRUN0

PSET0

CKSEL0 –

–

PTOUT1

PTRUN1

PSET1

CKSEL1

PTM0–1 8/16-bit mode selection External clock 0 noise rejecter selection – R/W register

Invalid (fixed at "0") PTM0 Run/Stop control PTM0 preset

PTM0 input clock selection – – – R/W register

PTM1 clock output control

Invalid (fixed at "0")

16-bit x 1

Enable

– 1

Invalid

Run

Preset

External clock

– – – 1

On Invalid Invalid Invalid

bit x 2

Disable

– 0

Fixed at "0"

Stop No operation Internal clock

– – – 0

Off Fixed at "0" Fixed at "0" Fixed at "0"

R/W

R/W – 0 0 0 0 0 – –

"0" when being read

R/W

Reserved register

R/W

"0" when being read

R/W

Constantly "0" when being read

– 0

R/W

Reserved register

R/W 0

"0" when being read

R/W

Note: The register names contain a timer number (0–7) to identify the timer to which the register belongs.

The following explanation uses "x" instead of the timer number except when it is required. For example, PTRUNx represents PTRUN0 through PTRUN7. Furthermore, a pair of timers are described as Timer(L) and Timer(H) in explanations for 16-bit mode. Timer(L) = Timer 0, Timer 2, Timer 4 or Timer 6 Timer(H) = Timer 1, Timer 3, Timer 5 or Timer 7

This is used for register names.

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5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Programmable Timer)

5.10.3 Setting of input clock

The clock to be input to the counter can be selected from either the internal clock or external clock by the input clock selection register (CKSEL) provided for each timer. The internal clock is an output of the prescaler. The external clock is used for the event counter function. A signal from the input port is used as the count clock. Table 5.10.3.1 shows the input clock selection register and input clock of each timer.

Table 5.10.3.1 Input clock selection

Timer

Timer 0

Timer 1

Timer 2

Timer 3

Timer 4

Timer 5

Timer 6

Timer 7

When the external clock is selected, a signal from the input port is input to the programmable timer. An noise rejecter is incorporated in the external clock input circuit and it can be enabled/disabled using the external clock noise rejecter select registers PTNREN_A through PTNREN_D corresponding to the EXCL0 through EXCL3 inputs. Writing "1" to PTNREN_A (–D) enables the noise rejecter for the external clock EXCL0 (–3). The noise rejecter regards pulses less than a 16/fOSC1 seconds in width as noise and rejects them (an external clock must have a pulse width at least double the rejected width). When PTNREN_A (–D) is "0", the external clock bypasses the noise rejecter.

When the internal clock is used, select a source clock and a division ratio of the prescaler to set the clock frequency for each timer. The source clock is specified using the source clock selection register PRTFx provided for each timer. When "1" is written to PRTFx, the OSC1 clock is selected as the source clock for Timer x. When "0" is written, the OSC3 clock is selected. The OSC3 oscillation circuit must be on before the OSC3 can be used. See "5.4 Oscillation Circuits" for the controlling of the OSC3 oscillation circuit.

The prescaler provides the division ratio selection register PSTx0–PSTx2 for each timer. Note that the division ratio varies depending on the selected source clock.

CKSEL0 = "0" CKSEL0 = "1" CKSEL1 = "0" CKSEL1 = "1" CKSEL2 = "0" CKSEL2 = "1" CKSEL3 = "0" CKSEL3 = "1" CKSEL4 = "0" CKSEL4 = "1" CKSEL5 = "0" CKSEL5 = "1" CKSEL6 = "0" CKSEL6 = "1" CKSEL7 = "0" CKSEL7 = "1"

Input clock

INCL0 (Prescaler) EXCL0 (K04 input) INCL1 (Prescaler) EXCL0 (K04 input) INCL2 (Prescaler) EXCL1 (K05 input) INCL3 (Prescaler) EXCL1 (K05 input) INCL4 (Prescaler) EXCL2 (K06 input) INCL5 (Prescaler) EXCL2 (K06 input) INCL6 (Prescaler) EXCL3 (K07 input) INCL7 (Prescaler) EXCL3 (K07 input)

Table 5.10.3.2 Division ratio and control registers

/4096 /1024 /256 /64 /32 /8 /2 /1

(OSC1)

OSC1 OSC1

f f

OSC1 OSC1

f f

OSC1

OSC1 OSC1

f f

OSC1

/128 /64 /32 /16 /8 /4 /2 /1

PSTx2

1 1 1 1 0 0 0 0

PSTx1

1 1 0 0 1 1 0 0

PSTx0

1 0 1 0 1 0 1 0

(OSC3)

OSC3 OSC3

f f

OSC3 OSC3

f f

OSC3

OSC3 OSC3

f f

OSC3

The set clock is output to Timer x by writing "1" to the clock control register PRPRTx.

When the 16-bit mode is selected, the programmable timer operates with the clock input to Timer(L), and Timer(H) inputs the Timer(L) underflow signal as the clock. Therefore, the setting of Timer(H) input clock is invalid.

5.10.4 Operation and control of timer

Reload data register and setting of initial value

The reload data register (RDRx) is used to set an initial value of the down counter. In the 8-bit mode, RDRx is used as an 8-bit register separated for each timer. In the 16-bit mode, the RDR(L) register is handled as low-order 8 bits of reload data, and the RDR(H) register is as high-order 8 bits.

The reload data register can be read and written, and all the registers are set to FFH at initial reset.

Data written in this register is loaded into the down counter, and a down counting starts from the value. The down counter is preset, in the following two cases:

1) When software presets

The software preset can be done using the preset control bits PSETx corresponding to Timer x. When the preset control bit is set to "1", the content of the reload data register is loaded into the down counter at that point. In the 16-bit mode, a 16-bit reload data is loaded all at one time by setting PSET(L). In this case, writing to PSET(H) is invalid.

2) When down counter has underflowed during a count

Since the down counter presets the reload data by the underflow, the underflow period is decided according to the value set in the reload data register. This underflow generates an interrupt, and controls the clock (TOUTx signal) output.

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5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Programmable Timer)

Compare data register

The programmable timer has a built-in data comparator so that count data can be compared with an optional value. The compare data register (CDRx) is used to set the value to be compared. In the 8-bit mode, CDRx is used as an 8-bit register separated for each timer. In the 16-bit mode, the CDR(L) register is handled as low-order 8 bits of compare data, and the CDR(H) register is as high-order 8 bits.

The compare data register can be read and written, and all the registers are set to 00H at initial reset.

The programmable timer compares count data with the compare data register (CDRx), and generates a compare match signal when they become the same value. This compare match signal generates an interrupt, and controls the clock (TOUTx signal) output.

Timer operation

Timer is equipped with PTRUNx register which controls the RUN/STOP of the timer. Timer x starts down counting by writing "1" to the PTRUNx register. However, it is necessary to control the input clock and to preset the reload data before starting a count.

When "0" is written to PTRUNx register, clock input is prohibited, and the count stops. This RUN/STOP control does not affect data in the counter. The data in the counter is maintained during count deactivation, so it is possible to resume counting from the data.

In the 8-bit mode, the timers can be controlled individually by the PTRUNx register. In the 16-bit mode, the PTRUN(L) register controls a pair of timers as a 16-bit timer. In this case, control of the PTRUN(H) register is invalid.

The buffers PTMx is attached to the counter, and reading is possible in optional timing.

When the counter agrees with the data set in the compare data register during down counting, the timer generates a compare match interrupt. And, when the counter underflows, an underflow interrupt is generated, and the initial value set in the reload data register is loaded to the counter. The interrupt generated does not stop the down counting. After an underflow interrupt is generated, the counter continues counting from the initial value reloaded.

PTRUNx PSETx RDRx CDRx Input clock PTMx7 PTMx6 PTMx5 PTMx4 PTMx3 PTMx2 PTMx1 PTMx0

A6H 58H

Preset Underflow interrupt

A6H

58H 58H

Compare match interrupt generation

generation

F3H

∗1

Reload

Fig. 5.10.4.1 Basic operation timing of counter (an example of 8-bit mode)

Note: The programmable timer counts down at the falling edge of the input clock and at the same time it

generates an interrupt if the counter underflows. Then it starts loading the reload data to the counter and the counter data is determined at the next rising edge of the input clock (period shown in as ∗1 in the figure). To avoid improper reloading, do not rewrite the reload data after an interrupt occurs until the counter data is determined including the reloading period ∗1. Be especially careful when using the OSC1 (low-speed clock) as the clock source of the programmable timer and the CPU is operating with the OSC3 (high-speed clock).

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5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Programmable Timer)

5.10.5 Interrupt function

The 16-bit programmable timer can generate an interrupt with the compare match signal and underflow signal of each timer. Figure 5.10.5.1 shows the configuration of the 16bit programmable timer interrupt circuit.

The compare match signal and underflow signal of each timer set the corresponding interrupt factor flag to "1". At that point, the interrupt is generated. The interrupt can also be prohibited by setting the interrupt enable register to correspond with the interrupt factor flag. Furthermore, the priority level of the interrupt for the CPU can be set to an optional level (0–3) using the interrupt priority register. Table 5.10.5.1 shows the interrupt factor flags, interrupt enable registers and interrupt priority registers corresponding to the interrupt factors.

In the 8-bit mode, the compare match interrupt factor flag and underflow interrupt factor flag are individually set to "1" by the timers.

Table 5.10.5.1 Interrupt control registers

Interrupt factor flag

Name

FTU0 FTC0 FTU1 FTC1 FTU2 FTC2 FTU3 FTC3 FTU4 FTC4 FTU5 FTC5 FTU6 FTC6 FTU7 FTC7

Timer 0

Timer 1

Timer 2

Timer 3

Timer 4

Timer 5

Timer 6

Timer 7

Interrupt factor

Counter underflow Compare match Counter underflow Compare match Counter underflow Compare match Counter underflow Compare match Counter underflow Compare match Counter underflow Compare match Counter underflow Compare match Counter underflow Compare match

In the 16-bit mode, the interrupt factor flags of Timer(H) are set to "1" by the compare match and underflow in 16 bits.

Refer to Section 5.14, "Interrupt and Standby Status", for details of the interrupt control registers and operations subsequent to interrupt generation.

The exception processing vector addresses for the 16bit programmable timer interrupt are set as follows:

Timer 0 underflow interrupt: 000016H Timer 0 compare match interrupt: 000018H Timer 1 underflow interrupt: 00001AH Timer 1 compare match interrupt: 00001CH Timer 2 underflow interrupt: 00001EH Timer 2 compare match interrupt: 000020H Timer 3 underflow interrupt: 000022H Timer 3 compare match interrupt: 000024H Timer 4 underflow interrupt: 00003CH Timer 4 compare match interrupt: 00003EH Timer 5 underflow interrupt: 000040H Timer 5 compare match interrupt: 000042H Timer 6 underflow interrupt: 000044H Timer 6 compare match interrupt: 000046H Timer 7 underflow interrupt: 000048H Timer 7 compare match interrupt: 00004AH

Address·Dx

00FF29H·D0 00FF29H·D1 00FF29H·D2 00FF29H·D3 00FF29H·D4 00FF29H·D5 00FF29H·D6 00FF29H·D7 00FF2EH·D0 00FF2EH·D1 00FF2EH·D2 00FF2EH·D3 00FF2EH·D4 00FF2EH·D5 00FF2EH·D6 00FF2EH·D7

Interrupt enable register

Name

ETU0 ETC0 ETU1 ETC1 ETU2 ETC2 ETU3 ETC3 ETU4 ETC4 ETU5 ETC5 ETU6 ETC6 ETU7 ETC7

Address·Dx

00FF25H·D0 00FF25H·D1 00FF25H·D2 00FF25H·D3 00FF25H·D4 00FF25H·D5 00FF25H·D6 00FF25H·D7 00FF2CH·D0 00FF2CH·D1 00FF2CH·D2 00FF2CH·D3 00FF2CH·D4 00FF2CH·D5 00FF2CH·D6 00FF2CH·D7

Interrupt priority register

Name

PPT0 PPT1

PPT2 PPT3

PPT4 PPT5

PPT6 PPT7

Address·Dx

00FF21H·D2 00FF21H·D3

00FF21H·D4 00FF21H·D5

00FF2AH·D0 00FF2AH·D1

00FF2AH·D2 00FF2AH·D3

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5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Programmable Timer)

Compare match

Data bus

Compare match

Address

Underflow

Address

Underflow

Address

Underflow

Address

Underflow

Address

Interrupt priority register PPT0, PPT1

Interrupt factor flag FTU0

Interrupt enable register ETU0

Interrupt factor flag FTC0

Interrupt enable register ETC0

Interrupt priority register PPT2, PPT3

Interrupt factor flag FTU2

Interrupt enable register ETU2

Interrupt factor flag FTC2

Interrupt enable register ETC2

Interrupt priority register PPT4, PPT5

Interrupt factor flag FTU4

Interrupt enable register ETU4

Interrupt factor flag FTC4

Interrupt enable register ETC4

Interrupt priority register PPT6, PPT7

Interrupt factor flag FTU6

Interrupt enable register ETU6

Interrupt factor flag FTC6

Interrupt enable register ETC6

Interrupt priority level judgment circuit

Timer 0

Timer 1

Interrupt priority level judgment circuit

Timer 2

Timer 3

Interrupt priority level judgment circuit

Timer 4

Timer 5

Interrupt priority level judgment circuit

Timer 6

Timer 7

Fig. 5.10.5.1 Configuration of 16-bit programmable timer interrupt circuit

Timer 0 interrupt request

Timer 1 interrupt request

Timer 2 interrupt request

Timer 3 interrupt request

Timer 4 interrupt request

Timer 5 interrupt request

Timer 6 interrupt request

Timer 7 interrupt request

92 EPSON S1C88650 TECHNICAL MANUAL

Epson S1C88650 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

1 INTRODUCTION

1.1 Features

1.2 Block Diagram

1.3 Pins

1.3.1 Pin layout diagram

1.3.2 Pin description

1.4 Mask Option

2 POWER SUPPLY

2.1 Operating V oltage

2.2 Internal Power Supply Circuit

3 CPU AND BUS CONFIGURATION

3.1 CPU

3.2 Internal Memory

3.2.1 Program ROM

3.2.2 RAM

3.2.3 I/O memory

3.2.4 Display memory

3.2.5 Kanji font ROM

3.3 Exception Processing Vectors

3.4 CC (Customized Condition Flag)

3.5 Chip Mode

3.5.1 MCU mode and MPU mode

3.5.2 Bus mode

3.5.3 CPU mode

3.6 External Bus

3.6.1 Data bus

3.6.2 Address bus

3.6.3 Read (RD)/write (WR) signals

3.6.4 Chip enable (CE) signal

3.6.5 WAIT control

3.6.6 Bus authority release state

4.1 Initial Reset Factors

4.1.1 RESET terminal

4 INITIAL RESET

4.1.3 Initial reset sequence

Initial Settings After Initial Reset

5.1 I/O Memory Map

System Controller and Bus Control

5.2.1 Bus mode and CPU mode settings

5.2.2 Address decoder (CE output) settings

5.2.3 WAIT state settings

5.2.4 Setting the bus authority release request signal

5.2.5 Stack page setting

5.2.6 Control of system controller

5.2.7 Programming notes

5.3 Watchdog Timer

5.3.1 Configuration of watchdog timer

5.3.2 Interrupt function

5.3.3 Control of watchdog timer

5.3.4 Programming notes

5.4 Oscillation Circuits

5.4.1 Configuration of oscillation circuits

5.4.2 Mask option

5.4.3 OSC1 oscillation circuit

5.4.4 OSC3 oscillation circuit

5.4.5 Switching the CPU clocks

5.4.6 Control of oscillation circuit

5.4.7 Programming notes

5.5 Input Ports (K ports)

5.5.1 Configuration of input ports

5.5.2 Mask option

5.5.3 Pull-up control

5.5.4 Interrupt function and input comparison register

5.5.5 Control of input ports

5.5.6 Programming notes

5.6 Output Ports (R ports)

5.6.1 Configuration of output ports

5.6.2 High impedance control

5.6.3 DC output

5.6.4 Control of output ports

5.7 I/O Ports (P ports)

5.7.1 Configuration of I/O ports

5.7.2 Mask option

5.7.3 I/O control registers and I/O mode

5.7.4 Pull-up control

5.7.5 Special output