Epson S1C6S3N2 Technical Manual

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MF859-06

CMOS 4-BIT SINGLE CHIP MICROCOMPUTER

S1C6S3N2

Technical Manual

S1C6S3N2 Technical Hardware/S1C6S3N2 Technical Software

Page 2

NOTICE

No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no representation that this material is applicable to products requiring high level reliability, such as medical products. Moreover, no license to any intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright infringement of a third party. This material or portions thereof may contain technology or the subject relating to strategic products under the control of the Foreign Exchange and Foreign Trade Law of Japan and may require an export license from the Ministry of International Trade and Industry or other approval from another government agency.

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PREFACE

This manual is individualy described about the hardware and the software of the S1C6S3N2.

I. S1C6S3N2 Technical Hardware

This part explains the function of the S1C6S3N2, the circuit configurations, and details the controlling method.

II. S1C6S3N2 Technical Software

This part explains the programming method of the S1C6S3N2.

Hardware

Software

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Page 5

The information of the product number change

Starting April 1, 2001, the product number will be changed as listed below. To order from April 1, 2001 please use the new product number. For further information, please contact Epson sales representative.

Configuration of product number

Devices

S1 C 60N01 F 0A01

Development tools

S5U1

∗1: For details about tool types, see the tables below. (In some manuals, tool types are represented by one digit.) ∗2: Actual versions are not written in the manuals.

C 60R08 D1 1

Packing specification Specification Package (D: die form; F: QFP) Model number Model name (C: microcomputer, digital products) Product classification (S1: semiconductor)

Packing specification Version (1: Version 1 ∗2) Tool type (D1: Development Tool ∗1) Corresponding model number (60R08: for S1C60R08) Tool classification (C: microcomputer use) Product classification (S5U1: development tool for semiconductor products)

Comparison table between new and previous number

S1C60 Family processors

Previous No.

E0C6001 E0C6002 E0C6003 E0C6004 E0C6005 E0C6006 E0C6007 E0C6008 E0C6009 E0C6011 E0C6013 E0C6014 E0C60R08

New No. S1C60N01 S1C60N02 S1C60N03 S1C60N04 S1C60N05 S1C60N06 S1C60N07 S1C60N08 S1C60N09 S1C60N11 S1C60N13 S1C60140 S1C60R08

S1C62 Family processors

Previous No.

E0C621A E0C6215 E0C621C E0C6S27 E0C6S37 E0C623A E0C623E E0C6S32 E0C6233 E0C6235 E0C623B E0C6244 E0C624A E0C6S46

New No. S1C621A0 S1C62150 S1C621C0 S1C6S2N7 S1C6S3N7 S1C6N3A0 S1C6N3E0 S1C6S3N2 S1C62N33 S1C62N35 S1C6N3B0 S1C62440 S1C624A0 S1C6S460

Previous No.

E0C6247 E0C6248 E0C6S48 E0C624C E0C6251 E0C6256 E0C6292 E0C6262 E0C6266 E0C6274 E0C6281 E0C6282 E0C62M2 E0C62T3

New No. S1C62470 S1C62480 S1C6S480 S1C624C0 S1C62N51 S1C62560 S1C62920 S1C62N62 S1C62660 S1C62740 S1C62N81 S1C62N82 S1C62M20 S1C62T30

Comparison table between new and previous number of development tools

Development tools for the S1C60/62 Family

Previous No.

ASM62 DEV6001 DEV6002 DEV6003 DEV6004 DEV6005 DEV6006 DEV6007 DEV6008 DEV6009 DEV6011 DEV60R08 DEV621A DEV621C DEV623B DEV6244 DEV624A DEV624C DEV6248 DEV6247

New No. S5U1C62000A S5U1C60N01D S5U1C60N02D S5U1C60N03D S5U1C60N04D S5U1C60N05D S5U1C60N06D S5U1C60N07D S5U1C60N08D S5U1C60N09D S5U1C60N11D S5U1C60R08D S5U1C621A0D S5U1C621C0D S5U1C623B0D S5U1C62440D S5U1C624A0D S5U1C624C0D S5U1C62480D S5U1C62470D

Previous No.

DEV6262 DEV6266 DEV6274 DEV6292 DEV62M2 DEV6233 DEV6235 DEV6251 DEV6256 DEV6281 DEV6282 DEV6S27 DEV6S32 DEV6S37 EVA6008 EVA6011 EVA621AR EVA621C EVA6237 EVA623A

New No. S5U1C62620D S5U1C62660D S5U1C62740D S5U1C62920D S5U1C62M20D S5U1C62N33D S5U1C62N35D S5U1C62N51D S5U1C62560D S5U1C62N81D S5U1C62N82D S5U1C6S2N7D S5U1C6S3N2D S5U1C6S3N7D S5U1C60N08E S5U1C60N11E S5U1C621A0E2 S5U1C621C0E S5U1C62N37E S5U1C623A0E

Previous No.

EVA623B EVA623E EVA6247 EVA6248 EVA6251R EVA6256 EVA6262 EVA6266 EVA6274 EVA6281 EVA6282 EVA62M1 EVA62T3 EVA6S27 EVA6S32R ICE62R KIT6003 KIT6004 KIT6007

New No. S5U1C623B0E S5U1C623E0E S5U1C62470E S5U1C62480E S5U1C62N51E1 S5U1C62N56E S5U1C62620E S5U1C62660E S5U1C62740E S5U1C62N81E S5U1C62N82E S5U1C62M10E S5U1C62T30E S5U1C6S2N7E S5U1C6S3N2E2 S5U1C62000H S5U1C60N03K S5U1C60N04K S5U1C60N07K

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S1C6S3N2

Technical Hardware

HardwareHardware

Page 8

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CONTENTS

CHAPTER 1 OVERVIEW....................................................................... I-1

1.1 Configuration................................................................... I-1

1.2 Features .......................................................................... I-2

1.3 Block Diagram................................................................. I-3

1.4 Pin Layout Diagram......................................................... I-4

1.5 Pin Description ................................................................ I-5

CHAPTER 2 POWER SUPPLY AND INITIAL RESET ................................ I-6

2.1 Power Supply .................................................................. I-6

2.2 Initial Reset..................................................................... I-10

Reset pin (RESET) ................................................... I-11

Simultaneous high input to input ports (K00–K03) .. I-11

Watchdog timer (Auxiliary reset).............................. I-11

Oscillation detection circuit (Auxiliary reset)............ I-12

Internal register at initial setting ............................. I-12

HardwareHardware

2.3 Test Terminal (TEST)..................................................... I-12

CHAPTER 3 CPU, ROM, RAM ............................................................ I-13

3.1 CPU................................................................................ I-13

3.2 ROM............................................................................... I-14

3.3 RAM ............................................................................... I-15

CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION ...................... I-16

4.1 Memory Map .................................................................. I-16

4.2 Resetting Watchdog Timer............................................. I-24

Configuration of watchdog timer.............................. I-24

Mask option ............................................................ I-24

Control of watchdog timer ....................................... I-25

Programming note................................................... I-25

S1C6S3N2 TECHNICAL HARDWARE EPSON I-i

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CONTENTS

4.3 Oscillation Circuit............................................................ I-26

OSC1 oscillation circuit........................................... I-26

OSC3 oscillation circuit........................................... I-26

Configuration of oscillation circuit........................... I-28

Control of oscillation circuit .................................... I-29

Programming notes ................................................. I-30

4.4 Input Ports (K00–K03, K10) ........................................... I-31

Configuration of input ports .................................... I-31

Differential registers and interrupt function ............ I-32

Mask option ............................................................ I-34

Control of input ports.............................................. I-35

Programming notes ................................................. I-37

4.5 Output Ports (R00–R03, R10–R13) ............................... I-40

Configuration of output ports .................................. I-40

Mask option ............................................................ I-40

Control of output ports............................................ I-43

Programming note................................................... I-45

4.6 I/O Ports (P00–P03, P10–P13) ...................................... I-46

Configuration of I/O ports....................................... I-46

I/O control register and I/O mode........................... I-47

Mask option ............................................................ I-47

Control of I/O ports ................................................ I-48

Programming notes ................................................. I-50

4.7 LCD Driver (COM0–3, SEG0–37) .................................. I-51

Configuration of LCD driver..................................... I-51

Switching between dynamic and ALL OFF ............... I-56

Mask option (segment allocation)............................. I-57

Control of LCD driver .............................................. I-59

Programming notes ................................................. I-60

4.8 Clock Timer .................................................................... I-61

Configuration of clock timer .................................... I-61

Interrupt function ................................................... I-62

Control of clock timer.............................................. I-63

Programming notes ................................................. I-65

I-ii EPSON S1C6S3N2 TECHNICAL HARDWARE

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CONTENTS

4.9 Stopwatch Counter......................................................... I-66

Configuration of stopwatch counter......................... I-66

Count-up pattern .................................................... I-67

Interrupt function ................................................... I-68

Control of stopwatch counter .................................. I-69

Programming notes ................................................. I-72

4.10 Event Counter ................................................................ I-73

Configuration of event counter ................................ I-73

Operation of event counter ...................................... I-73

Mask option ............................................................ I-74

Control of event counter.......................................... I-75

Programming note................................................... I-76

4.11 Analog Comparator ........................................................ I-77

Configuration of analog comparator ........................ I-77

Operation of analog comparator .............................. I-77

Control of analog comparator .................................. I-78

Programming notes ................................................. I-79

HardwareHardware

4.12 Supply Voltage Detection (SVD) Circuit

and Heavy Load Protection Function .............................

Configuration of SVD circuit.................................... I-80

Heavy load protection function ................................ I-81

Detection timing of SVD circuit ............................... I-82

Control of SVD circuit ............................................. I-84

Programing notes .................................................... I-86

I-80

4.13 Interrupt and HALT......................................................... I-88

Interrupt factors...................................................... I-90

Specific masks and factor flags for interrupt............ I-91

Interrupt vectors ..................................................... I-92

Control of interrupt and HALT................................. I-93

Programming notes ................................................. I-96

S1C6S3N2 TECHNICAL HARDWARE EPSON I-iii

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CONTENTS

CHAPTER 5 SUMMARY OF NOTES..................................................... I-97

5.1 Notes for Low Current Consumption.............................. I-97

5.2 Summary of Notes by Function...................................... I-98

CHAPTER 6 DIAGRAM OF BASIC

EXTERNAL CONNECTIONS ........................................... I-104

CHAPTER 7 ELECTRICAL CHARACTERISTICS ................................... I-107

7.1 Absolute Maximum Rating ............................................ I-107

7.2 Recommended Operating Conditions ........................... I-108

7.3 DC Characteristics ........................................................ I-109

7.4 Analog Circuit Characteristics

and Consumed Current .................................................

I-111

7.5 Oscillation Characteristics............................................. I-119

CHAPTER 8 PACKAGE ..................................................................... I-124

8.1 Plastic Package............................................................. I-124

8.2 Ceramic Package for Test Samples.............................. I-126

CHAPTER 9 PAD LAYOUT ................................................................. I-127

9.1 Diagram of Pad Layout.................................................. I-127

9.2 Pad Coordinates............................................................ I-128

I-iv EPSON S1C6S3N2 TECHNICAL HARDWARE

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CHAPTER 1 OVERVIEW

The S1C6S3N2 Series is a single-chip microcomputer made up of the 4-bit core CPU S1C6200A, ROM (2,048 words, 12 bits to a word), RAM (144 words, 4 bits to a word) LCD driver circuit, analog comparator, event counter, watchdog timer, and two types of time base counter. Because of its low-voltage operation and low power consumption, this series is ideal for a wide range of applications, and is especially suitable for battery-driven systems. Furthermore, the S1C6S3N2 is a shrunk model of the S1C62N32. It can be used as various controller applications such as a clock, game and pager.

1.1

Configuration

The S1C6S3N2 Series is configured as follows, depending on supply voltage and oscillation circuits.

CHAPTER 1: OVERVIEW

Model S1C6S3N2 S1C6S3L2 S1C6S3B2 S1C6S3A2

Supply Voltage 1.8*–3.6 V 0.9–1.8 V 0.9–3.6 V 1.8*–3.6 V

External Supports Supports

LCD 3.0 V 3.0 V

Power Supply LCD panels LCD panels LCD panels

Oscillation OSC1 only

Circuits (Single Clock) (Twin Clock)

Not

supported

Supports

4.5/3.0 V

OSC1 and OSC3

* Applications that display with an LCD panel require at

least 2.2 V of supply voltage because a voltage less than

2.2 V lowers the LCD drive voltage.

S1C6S3N2 TECHNICAL HARDWARE EPSON I-1

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CHAPTER 1: OVERVIEW

1.2 Features

OSC1 oscillation circuit OSC3 oscillation circuit

Instruction sets Instruction execution time (differs depending oninstruction) (CLK: CPU operation frequency) ROM capacity RAM capacity Input ports Output ports Input/output ports LCD driver

Time base counter Watchdog timer Event counter Analog comparator Supply voltage detection circuit (SVD) External interrupt Internal interrupt Supply voltage *2 Consumed current

(Typ. value)

Form when shipped

CLK = 32.768 kHz (when halted) CLK = 32.768 kHz (when executed) CLK = 1 MHz (when executed)

S1C6S3N2 S1C6S3L2 S1C6S3B2 S1C6S3A2

Crystal oscillation circuit 32.768 kHz (Typ.) No setting

100 types 153 µsec, 214 µsec, 366 µsec (CLK = 32.768 kHz)

2,048 words, 12 bits per word 144 words, 4 bits per word 5 bits (pull-down resistor can be added through mask option) 8 bits (BZ, BZ, FOUT outputs are available through mask option) 8 bits (pull-down resistor is added during input data read-out) Either 38 segments × 4 or 3 or 2 common *1 V-3V 1/4 or 1/3 or 1/2 duty (regulated voltage circut and booster voltage circuit built-in) Two types (timer and stopwatch) Built-in (can be disabled through mask option) One 8-bit inputs Inverted input x 1, noninverted input x 1

2.4 V Input port interrupt; dual system Time base counter interrupt; dual system

3.0 V (1.8–3.6 V)

0.65 µA

2.0 µA

–

80-pin QFP (plastic) or chip

1.2 V

1.5 V (0.9–1.8 V)

0.65 µA

2.0 µA

–

1.2 V

1.5 V (0.9–3.6 V)

0.65 µA

2.0 µA

–

CR or ceramic oscillation circuit *1 1 MHz

(Typ.)

5 µsec, 7 µsec, 12 µsec (CLK = 1 MHz)

2.4 V

3.0 V (1.8–3.6 V)

1.5 µA

4.0 µA

150 µA

*1 Selected by mask option *2 The supply voltage range of the S1C6S3N2 and S1C6S3A2 is 2.2 to 3.6 V when

an LCD panel is used.

In this manual, BLD and SVD (supply voltage detection) have the same meaning.

I-2 EPSON S1C6S3N2 TECHNICAL HARDWARE

Page 15

CHAPTER 1: OVERVIEW

Block Diagram1.3

COM0 | COM3

SEG0 | SEG37

| V

CA | CB

ROM

2,048 x 12

RAM

144 x 4

LCD

Driver

Power

Controller

OSC1

OSC2

OSC3

OSC4

OSC

Core CPU S1C6200A

RESET

System Reset Control

Interrupt

Generator

I Port

I/O Port

O Port

Comparator

K00–K03, K10

TEST

P00–P03

P10–P13

R00–R03

R10–R13

AMPP

AMPM

Timer

Stop

Watch

Fig. 1.3.1

SVD

Event

Counter

Block diagram

S1C6S3N2 TECHNICAL HARDWARE EPSON I-3

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CHAPTER 1: OVERVIEW

Pin Layout Diagram1.4

QFP5-80pin

64 41

Index

124

Pin No. Pin Name

Fig. 1.4.1(a)

Pin layout diagram

QFP14-80pin

60 41

Index

120

Pin No.

Fig. 1.4.1(b)

Pin layout diagram

Pin No. Pin Name

SEG17

TEST

SEG18

SEG19

SEG20

SEG21

SEG22

SEG23

SEG24

SEG25

SEG26

SEG27

SEG28

SEG29

SEG30

SEG31

SEG32

SEG33

SEG34

SEG35

SEG36

SEG37

AMPP

AMPM

K10

K03

K02

K01

K00

P03

P02

P01

P00

P13

P12

P11

P10

R03

R02

R01

Pin No. Pin Name

R00

R12

R11

R10

R13

RESET

OSC4

OSC3

OSC2

OSC1

N.C.

COM3

Pin No. Pin Name

COM2

COM1

COM0

SEG0

SEG1

SEG2

SEG3

SEG4

SEG5

SEG6

SEG7

SEG8

SEG9

SEG10

SEG11

SEG12

SEG13

SEG14

SEG15

SEG16

N.C. : No connection

Pin No.

AMPP

AMPM

K10

K03

K02

K01

K00

P03

P02

P01

P00

P13

P12

P11

P10

R03

R02

R01

R00

R12

R11

R10

R13

RESET

OSC4

OSC3

OSC2

OSC1

N.C.

COM3

COM2

COM1

DD L3 L2 L1

Pin No.

41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

COM0 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 TEST

Pin No.Pin Name Pin Name Pin Name Pin Name

SEG18

SEG19

SEG20

SEG21

SEG22

SEG23

SEG24

SEG25

SEG26

SEG27

SEG28

SEG29

SEG30

SEG31

SEG32

SEG33

SEG34

SEG35

SEG36

SEG37

N.C. : No connection

I-4 EPSON S1C6S3N2 TECHNICAL HARDWARE

Page 17

1.5 Pin Description

Table 1.5.1 Pin description

CHAPTER 1: OVERVIEW

Pin Name

VDD VSS VS1 VL1 VL2 VL3 CA, CB OSC1 OSC2 OSC3 OSC4 K00–10 P00–13 R00–03 R10 R13 R11 R12 AMPP AMPM SEG0–37

COM0–3 RESET TEST

Pin Number

QFP5-80

53 46 50 56 55 54

58, 59

52 51 49

48 25–29 30–37 38–41

1, 3–22,

64–80 60–63

QFP14-80

31 24 28 34 33 32

36, 37

30 29 27 26

3–7

8–15

16–19

22 23 21 20

1 2

42–59,

61–80 38–41

25 60

Input/

Output

(I) (I)

– – – – –

I/O

O O O O O

I I

Function

Power source positive terminal Power source negative terminal Constant voltage output terminal for oscillation Constant voltage output terminal for LCD (approx. -1.05 V) Booster output terminal for LCD (V Booster output terminal for LCD (V Booster condenser connector terminal Crystal oscillator input terminal Crystal oscillator output terminal *1 *2 Input terminal Input/output terminal Output terminal Output terminal (Can output BZ through mask option.) Output terminal (Can output BZ through mask option.) Output terminal Output terminal (Can output FOUT through mask option.) Analog comparator noninverted input terminal Analog comparator inverted input terminal LCD segment output terminal (DC output available through mask option.) LCD common output terminal Initial setting input terminal Test input terminal

L1 × 2) L1 × 3)

*1 6S3N2/6S3L2/6S3B2:Not connected

6S3A2: CR or ceramic oscillation input terminal

(Switchable through mask option.)

*2 6S3N2/6S3L2/6S3B2:Not connected

6S3A2: CR or ceramic oscillation output terminal

(Switchable through mask option.)

S1C6S3N2 TECHNICAL HARDWARE EPSON I-5

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CHAPTER 2: POWER SUPPLY AND INITIAL RESET

CHAPTER 2

POWER SUPPLY AND INITIAL RESET

2.1

Power Supply

With a single external power supply (*1) supplied to VDD through VSS, the S1C6S3N2 Series generates the necessary internal voltage with the regulated voltage circuit (<VS1> for oscillators, <VL1> for LCDs) and the voltage booster circuit (<VL2, VL3> for LCDs). Or the S1C6S3N2 Series generates the necessary internal voltage with the regulated voltage circuit (<VS1> for oscillators, <VL2> for LCDs) and the voltage booster circuit (<VL1, VL3> for LCDs). Figures 2.1.1(a) and 2.1.1(b) show the configuration of power supply.

*1 Supply voltage: 6S3N2 .. 1.8 (2.2)–3.6 V

6S3L2 .. 0.9–1.8 V 6S3B2 .. 0.9–3.6 V 6S3A2 .. 1.8 (2.2)–3.6 V

The values enclosed with ( ) are minimum voltages for applications that use LCD display.

Note

- External loads cannot be driven by the regulated voltage and voltage booster circuit's output voltage.

- See "7 ELECTRICAL CHARACTERISTICS" for voltage values.

I-6 EPSON S1C6S3N2 TECHNICAL HARDWARE

Page 19

CHAPTER 2: POWER SUPPLY AND INITIAL RESET

Internal circuit

Oscillation system regulated voltage circuit

Oscillation circuit

OSC1–4

External power supply

Fig. 2.1.1(a)

Example of configuration of

power supply

(S1C6S3L2/6S3B2)

External power supply

CA CB

LCD system regulated voltage circuit

LCD system voltage booster circuit

LCD driver circuit

COM0–3 SEG0–37

Internal circuit

Oscillation circuit

LCD driver circuit

OSC1–4

COM0–3 SEG0–37

Oscillation system regulated voltage circuit

LCD system regulated voltage circuit

CA CB

LCD system voltage booster/reducer circuit

Fig. 2.1.1(b)

Example of configuration of

power supply

(S1C6S3N2/6S3A2)

S1C6S3N2 TECHNICAL HARDWARE EPSON I-7

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CHAPTER 2: POWER SUPPLY AND INITIAL RESET

The LCD system regulated voltage circuit use can be prohibited by setting the mask option. In this case, external elements can be minimized because the external capacitors for the LCD system regulated voltage circuit are not necessary. However when the LCD system regulated voltage circuit is not used, the display quality of the LCD panel, when the supply voltage fluctuates (drops), is inferior to when the LCD system regulated voltage circuit is used. The S1C6S3B2 always uses the the LCD system regulated voltage circuit, therefore the external capacitors are required. Figure 2.1.2 shows the external elements when the the LCD sys-

tem regulated voltage circuit is not used.

• S1C6S3A2

4.5 V LCD panel 1/4, 1/3, 1/2 duty, 1/3 bias

VDD

VS1

VL1 VL2 VL3

VSS

C5 C2

3 V

Note: VL2 is shorted to VSS inside the IC.

Fig. 2.1.2

External elements when

LCD system regulated

voltage circuit is not used

• S1C6S3N2/S1C6S3A2

3 V LCD panel 3 V LCD panel 1/4, 1/3, 1/2 duty, 1/3 bias 1/4, 1/3, 1/2 duty, 1/2 bias

V V V

L2 L3

3 V

Note: VL3 is shorted to VSS inside the IC.

• S1C6S3L2

3 V LCD panel 1/4, 1/3, 1/2 duty, 1/2 bias

1.5 V

Note: VL1 is shorted to VSS inside the IC.

3 V

I-8 EPSON S1C6S3N2 TECHNICAL HARDWARE

Page 21

CHAPTER 2: POWER SUPPLY AND INITIAL RESET

LCD system power supply

For the LCD system power supply, either "internal" (to generate internally) or "external" (to supply from outside of the IC) can be selected. The LCD panel voltage has been decided depending on the model and selection of the LCD system power supply. When "external" is selected by the mask option, the specified LCD drive voltage terminal is connected to the VSS inside the IC.

1/3 Bias Internal

L1 / VL2

S1C6S3N2 S1C6S3A2 S1C6S3L2 S1C6S3B2

3.0 V LCD

1/2 Bias Internal

L1/VL2

S1C6S3N2 S1C6S3A2 S1C6S3L2

VL1 = VSS

× × × ×

VL1 = V

× × ×

× ×

3.0 V LCD

External

L2 = VSS

4.5 V LCD

× ×

External

= V

× × ×

VL3 = VSS

3.0 V LCD

VL3 = V

3.0 V LCD

Combinations that are marked with an "×" cannot be selected.

× ×

S1C6S3N2 TECHNICAL HARDWARE EPSON I-9

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CHAPTER 2: POWER SUPPLY AND INITIAL RESET

Initial Reset

2.2

To initialize the S1C6S3N2 Series circuits, initial reset must be executed. There are four ways of doing this. Four types of initial reset factors are available, however be sure to use (1) or (2) for resetting because (3) and (4) are auxiliary reset factors.

(1)External initial reset by the RESET terminal (2)External initial reset by simultaneous high input to

terminals K00–K03 (3)Initial reset by watchdog timer (4)Initial reset by the oscillation detection circuit

(The IC is reset after 1 sec has elapsed from a start of

oscillation.) Figure 2.2.1 shows the configuration of the initial reset

circuit.

OSC1 OSC2

K00

K01

K02

K03

RESET

Fig. 2.2.1

Configuration of

initial reset circuit

OSC1

Oscillation

circuit

Vss

Watchdog

timer

Oscillation

detection

circuit

Time

authorize

circuit

Noise rejector

Initial reset

I-10 EPSON S1C6S3N2 TECHNICAL HARDWARE

Page 23

CHAPTER 2: POWER SUPPLY AND INITIAL RESET

Reset pin (RESET)

Simultaneous high input to input ports (K00–K03)

Table 2.2.1

Input port combinations

Initial reset can be executed externally by setting the reset

terminal to the high level. This high level must be main-

tained for at least 5 msec (when oscillating frequency is

fOSC1 = 32 kHz, after oscillation circuit start up), because

the initial reset circuit contains a noise rejector circuit.

When the reset terminal goes low the CPU begins to operate.

Another way of executing initial reset externally is to input a

high signal simultaneously to the input ports (K00–K03)

selected with the mask option. The specified input port

terminals must be kept high for at least 5 msec (when

oscillating frequency is fOSC1 = 32 kHz, after oscillation

circuit start up), because the initial reset circuit contains a

noise rejector circuit. Table 2.2.1 shows the combinations of

input ports (K00–K03) that can be selected with the mask

option.

A Not used B K00*K01 C K00*K01*K02 D K00*K01*K02*K03

Watchdog timer (Auxiliary reset)

When, for instance, mask option D (K00*K01*K02*K03) is

selected, initial reset is executed when the signals input to

the four ports K00–K03 are all high at the same time.

Further, when the input time of the simultaneous HIGH

input is tested and found to be the same or more than the

defined time (1–3 sec), the time test circuit that performs

initial reset can be selected with the mask option.

If you use this function, make sure that the specified ports

do not go high at the same time during ordinary operation.

If the CPU runs away for some reason, the watchdog timer

will detect this situation and output an initial reset signal.

See "4.2 Resetting Watchdog Timer" for details.

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CHAPTER 2: POWER SUPPLY AND INITIAL RESET

Oscillation detection circuit (Auxiliary reset)

Internal register at initial setting

Table 2.2.2

Initial values

The oscillation detection circuit outputs the initial reset signal at power-on until the crystal oscillation circuit (OSC1) begins oscillating, or when this crystal oscillation circuit (OSC1) halts oscillating for some reason. However, depending on the power-on sequence (voltage rise timing), the circuit may not work properly. Therefore, use the reset terminal or reset by simultaneous high input to the input port (K00–K03) for initial reset after turning power on.

Initial reset initializes the CPU as shown in the table below.

CPU Core

Name Signal Number of Bits Setting Value

Program counter step PCS 8 00H Program counter page PCP 4 1H New page pointer NPP 4 1H Stack pointer SP 8 Undefined Index register X X 9 Undefined Index register Y Y 9 Undefined Register pointer RP 4 Undefined General-purpose register A A 4 Undefined General-purpose register B B 4 Undefined Interrupt flag I 1 0 Decimal flag D 1 Undefined Zero flag Z 1 Undefined Carry flag C 1 Undefined

Peripheral Circuits

Name Number of Bits Setting Value

RAM 4 Undefined Segment data 4 Undefined Other peripheral circuit 4 *1

*1 See "4.1 Memory Map"

Test Terminal (TEST)

2.3

This terminal is used when the IC load is being detected. During ordinary operation be certain to connect this terminal to VSS.

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CHAPTER 3: CPU, ROM, RAM

CHAPTER 3

CPU, ROM, RAM

3.1

CPU

The S1C6S3N2 Series employs the core CPU S1C6200A for

the CPU, so that register configuration, instructions and so

forth are virtually identical to those in other family proces-

sors using the S1C6200A.

Refer to "S1C6200/6200A Core CPU Manual" for details

about the S1C6200A.

Note the following points with regard to the S1C6S3N2

Series:

(1)The SLEEP operation is not assumed, so the SLP instruc-

tion cannot be used.

(2)Because the ROM capacity is 2,048 words, bank bits are

unnecessary and PCB and NBP are not used.

(3)The RAM page is set at 0 only, so that the page part (XP,

YP) of the index register that performs address specification is invalid.

PUSH XP PUSH YP POP XP POP YP LD XP,r LD YP,r LD r,XP LD r,YP

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CHAPTER 3: CPU, ROM, RAM

3.2

ROM

The built-in ROM, a mask ROM for loading the program, has a capacity of 2,048 steps, 12 bits each. The program area is 8 pages (0–7), each of 256 steps (00H–FFH). After initial reset, the program beginning address is page 1, step 00H. The interrupt vector is allocated to page 1, steps 01H–0FH.

Fig. 3.2.1

ROM configuration

5page

6page

7page

2page

3page

4page

0page

1page

00H step 01H step

0FH step 10H step

FFH step

12 bits

Program start address

Interrupt vector area

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CHAPTER 3: CPU, ROM, RAM

3.3 RAM

The RAM, a data memory storing a variety of data, has a

capacity of 144 words, each of four bits. When program-

ming, keep the following points in mind.

(1)Part of the data memory can be used as stack area when

saving subroutine calls and registers, so be careful not to overlap the data area and stack area.

(2)Subroutine calls and interrupts take up three words of

the stack area.

(3)The data memory 000H–00FH is for the register pointers

(RP), and is the addressable memory register area.

(4)The data memory is split into two areas, 000H–06FH and

080H–09FH, so take care when allocating the data. (See "4.1 Memory Map" for details.)

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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map)

CHAPTER 4

PERIPHERAL CIRCUITS AND OPERATION

Peripheral circuits (timer, I/O, and so on) of the S1C6S3N2 Series are memory mapped, and interfaced with the CPU. Thus, all the peripheral circuits can be controlled by using the memory operation command to access the I/O data memory in the memory map. The following sections describe how the peripheral circuits operation.

Memory Map

4.1

Data memory of the S1C6S3N2 Series has an address space of 160 words, of which 48 words are allocated to segment data memory and 32 words to I/O data memory. Figures 4.1.1 and 4.1.2 present the overall memory maps of the S1C6S3N2 Series, and Tables 4.1.1(a)–4.1.1(f) the peripheral circuits' (I/O space) memory maps.

Fig. 4.1.1

Memory map (page 0)

Address

Page High

Low

0123456789ABCDEF

M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 MA MB MC MD ME MF0 1 2 3 4 5 6 7 8 9

A B C D E F

RAM (112 words x 4 bits)

I/O data memory Tables 4.1.1(a)–4.1.1(d)

I/O data memory Tables 4.1.1(e)–4.1.1(f)

R/W

RAM (32 words x 4 bits)

R/W

Unused area

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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map)

Fig. 4.1.2

Memory map

(segment area)

Address

Page High

Note

(1)See Tables 4.1.1(a)–4.1.1(f) for details of I/O data memory.

Low

4 or C 5 or D 6 or E

0123456789ABCDEF

Segment data memory (38 words x 4 bits)

40H–6FH = R/W

C0H–EFH = W

(2)The mask option can be used to select whether to assign the

overall area of segment data memory to 40H–6FH or C0H– EFH.

When 40H–6FH is selected, read/write is enabled. When C0H–EFH is selected, write only is enabled.

If 40H–6FH is assigned, RAM is used as the segment area (48 words).

(3)Memory is not mounted in unused area within the memory map

and in memory area not indicated in this chapter. For this reason, normal operation cannot be assured for programs that have been prepared with access to these areas.

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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map)

Table 4.1.1(a) I/O memory map (070H–073H)

Address Comment

D3 D2 D1 D0 Name SR

TM3 TM2 TM1 TM0

TM3

TM2

Timer data (clock timer 2 Hz)

Timer data (clock timer 4 Hz)

070H

071H

072H

073H

SWL3 SWL2 SWL1 SWL0

SWH3 SWH2 SWH1 SWH0

K03 K02 K01 K00

TM1

TM0

SWL3

SWL2

SWL1

SWL0

SWH3

SWH2

SWH1

SWH0

K03

K02

K01

–

High

–

High

–

High

Timer data (clock timer 8 Hz)

Timer data (clock timer 16 Hz)

MSB

Stopwatch counter 1/100 sec (BCD)

LSB

MSB

Stopwatch counter 1/10 sec (BCD)

LSB

Low

Input port (K00–K03)

Low

K00

–

High

Low

*1 Initial value at the time of initial reset *2 Not set in the circuit *3 Undefined *4 Reset (0) immediately after being read *5 Constantly "0" when being read

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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map)

Table 4.1.1(b) I/O memory map (074H–077H)

Address Comment

D3 D2 D1 D0 Name SR

DFK03 DFK02 DFK01 DFK00

074H

EIK03 EIK02 EIK01 EIK00

075H

HLMOD

R/W

076H

R/W

BLD

EISWIT1 EISWIT0

BLS

R W

EIK10 DFK10 K10

R/W

DFK03

DFK02

DFK01

DFK00

EIK03

EIK02

EIK01

EIK00

HLMOD

BLD BLS

EISWIT1

EISWIT0

EIK10

Falling

Enable

Heavy

load

Low voltage

00Enable

Enable

–

Enable

Rising

Differential register

Rising

(K00–K03)

Rising

Mask

Interrupt mask register

Mask

(K00–K03)

Mask

Normal

Heavy load protection mode register

SVD evaluation data

Normal

SVD ON/OFF

OFF

Interrupt mask register

Mask

(stopwatch 1 Hz) Interrupt mask register

Mask

(stopwatch 10 Hz)

Unused

Mask

Interrupt mask register (K10)

077H

DFK10

Falling

Rising

Differential register (K10)

K10

–

High

Low

Input port (K10)

*1 Initial value at the time of initial reset *2 Not set in the circuit *3 Undefined *4 Reset (0) immediately after being read *5 Constantly "0" when being read

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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map)

Table 4.1.1(c) I/O memory map (078H–07BH)

Address Comment

D3 D2 D1 D0 Name SR

CSDC ETI2 ETI8 ETI32

078H

079H

IK1 IK0 SWIT1 SWIT0

07AH

R03 R01 R00

07BH

R/W

TI2 TI8 TI32

R02

R/W

CSDC

ETI2

ETI8

ETI32

TI2

TI8

TI32

IK1

IK0

SWIT1

SWIT0

R03

R02

R01

LCD drive switch

ALL OFF

Dynamic

Interrupt mask register

Yes

High

Mask

(clock timer 2 Hz) Interrupt mask register

Mask

(clock timer 8 Hz) Interrupt mask register

Mask

(clock timer 32 Hz) Unused

Interrupt factor flag

(clock timer 2 Hz) Interrupt factor flag

(clock timer 8 Hz) Interrupt factor flag

(clock timer 32 Hz) Interrupt factor flag

(K10) Interrupt factor flag

(K00–K03) Interrupt factor flag

(stopwatch 1 Hz) Interrupt factor flag

(stopwatch 10 Hz)

Low

Output port (R00–R03)

Low

Enable

–

R00

High

Low

*1 Initial value at the time of initial reset *2 Not set in the circuit *3 Undefined *4 Reset (0) immediately after being read *5 Constantly "0" when being read

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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map)

Table 4.1.1(d) I/O memory map (07CH–07FH)

Address Comment

D3 D2 D1 D0 Name SR

R13

R12 R11 R10

R/W

R13

R12

Low

High

Low

High

Output port (R13, BZ)

Output port (R12, FOUT)

07CH

07DH

07EH

07FH

R11

R10

P03 P02 P01 P00

R/W

SWRUN SWRST IOC0

TMRST

W R/W W R/W

WDRST WD2 WD1 WD0RWDRST

P03

P02

P01

P00

TMRST

SWRUN

SWRST

IOC0

WD2

WD1

WD0

–

Reset

Output

Reset

High

RUN

Low

Output port (R11)

Low

Output port (R10, BZ)

Low

I/O port (P00–P03)

Low

Output latch reset at time of SR

Low

–

Clock timer reset

STOP

Stopwatch counter RUN/STOP

–

Stopwatch counter reset

Input

I/O control register 0 (P00–P03)

Watchdog timer reset

Timer data (watchdog timer 1/4 Hz) Timer data (watchdog timer 1/2 Hz) Timer data (watchdog timer 1 Hz)

*1 Initial value at the time of initial reset *2 Not set in the circuit *3 Undefined *4 Reset (0) immediately after being read *5 Constantly "0" when being read

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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map)

Table 4.1.1(e) I/O memory map (0F6H–0F9H)

Address Comment

D3 D2 D1 D0 Name SR

BZFQ

R/W

0F6H

000

AMPDT AMPON

BZFQ

R/W

2 kHz 4 kHz

–

Buzzer frequency selection register

Unused

0F7H

0F8H

0F9H

EV03 EV02 EV01 EV00

EV07

EV06 EV05 EV04

AMPDT

AMPON

EV03

EV02

EV01

EV00

EV07

EV06

EV05

+ > -ON- > +

OFF

Analog comparator data

Analog comparator ON/OFF

Event counter Low order (EV00–EV03)

Event counter High order (EV04–EV07)

EV04

*1 Initial value at the time of initial reset *2 Not set in the circuit *3 Undefined *4 Reset (0) immediately after being read *5 Constantly "0" when being read

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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map)

Table 4.1.1(f) I/O memory map (0FCH–0FEH)

Address Comment

D3 D2 D1 D0 Name SR

0FCH

P13

0FDH

EVRUN EVRST

R/W W

P12 P11 P10

CLKCHG

R/W

OSCC IOC1

R/W

EVRUN

EVRST

P13

P12

P11

P10

CLKCHG

–

Reset

–

RUN

Reset

High

OSC3ONOSC1

Unused

STOP

Event counter RUN/STOP

Unused

Event counter reset

Low

I/O port (P10–P13) Output latch reset at time of SR

Low

Unused

CPU clock switch

0FEH

OSCC

IOC1

Output Input

OFF

OSC3 oscillator ON/OFF

I/O control register 1 (P10–P13)

*1 Initial value at the time of initial reset *2 Not set in the circuit *3 Undefined *4 Reset (0) immediately after being read *5 Constantly "0" when being read

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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Resetting Watchdog Timer)

Resetting Watchdog Timer

4.2

Configuration of watchdog timer

Fig. 4.2.1

Watchdog timer

block diagram

The S1C6S3N2 Series incorporates a watchdog timer as the source oscillator for OSC1 (clock timer 2 Hz signal). The watchdog timer must be reset cyclically by the software. If reset is not executed in at least 3 or 4 seconds, the initial reset signal is output automatically for the CPU. Figure 4.2.1 is the block diagram of the watchdog timer.

OSC1 demultiplier

(256 Hz)

Watchdog timer reset signal

Clock timer

TM0–TM3

2 Hz

Watchdog timer

WD0–WD2

Initial reset signal

The watchdog timer, configured of a three-bit binary counter (WD0–WD2), generates the initial reset signal internally by overflow of the MSB. Watchdog timer reset processing in the program's main routine enables detection of program overrun, such as when the main routine's watchdog timer processing is bypassed. Ordinarily this routine is incorporated where periodic processing takes place, just as for the timer interrupt routine. The watchdog timer operates in the halt mode. If the halt status continues for 3 or 4 seconds, the initial reset signal restarts operation.

Mask option

You can select whether or not to use the watchdog timer with the mask option. When "Not use" is chosen, there is no need to reset the watchdog timer.

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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Resetting Watchdog Timer)

Control of watchdog timer

Table 4.2.1 lists the watchdog timer's control bits and their addresses.

Table 4.2.1 Control bits of watchdog timer

Address Comment

07FH

D3 D2 D1 D0 Name 0

WDRST WD2 WD1 WD0RWDRST

*1 Initial value at the time of initial reset *2 Not set in the circuit *3 Undefined *4 Reset (0) immediately after being read *5 Constantly "0" when being read

WDRST:

This is the bit for resetting the watchdog timer.

Watchdog timer reset

(07FH·D3)

WD2

WD1

WD0

Reset

Watchdog timer reset Timer data

(watchdog timer 1/4 Hz) Timer data (watchdog timer 1/2 Hz) Timer data (watchdog timer 1 Hz)

When "1" is written : Watchdog timer is reset When "0" is written : No operation Read-out : Always "0"

Programming note

When "1" is written to WDRST , the watchdog timer is reset, and the operation restarts immediately after this. When "0" is written to WDRST, no operation results. This bit is dedicated for writing, and is always "0" for readout.

When the watchdog timer is being used, the software must reset it within 3-second cycles, and timer data (WD0–WD2) cannot be used for timer applications.

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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Oscillation Circuit)

4.3

Oscillation Circuit

OSC1 oscillation circuit

Fig. 4.3.1

OSC1 oscillation circuit

The S1C6S3N2 Series has a built-in crystal oscillation circuit. As an external element, the OSC1 oscillation circuit generates the operating clock for the CPU and peripheral circuitry by connecting the crystal oscillator (Typ. 32.768 kHz) and trimmer capacitor (5–25 pF). Figure 4.3.1 is the block diagram of the OSC1 oscillation circuit.

X'tal

OSC1

OSC2

To CPU and peripheral circuits

S1C6S3N2 Series

As Figure 4.3.1 indicates, the crystal oscillation circuit can be configured simply by connecting the crystal oscillator (X'tal) between terminals OSC1 and OSC2 to the trimmer capacitor (CGX) between terminals OSC1 and VDD.

OSC3 oscillation circuit

In the S1C6S3N2 Series, the S1C6S3A2 has twin clock specification. The mask option enables selection of either the CR or ceramic oscillation circuit (OSC3 oscillation circuit) as the CPU's subclock. Because the oscillation circuit itself is built-in, it provides the resistance as an external element when CR oscillation is selected, but when ceramic oscillation is selected both the ceramic oscillator and two capacitors (gate and drain capacitance) are required. Figure 4.3.2 is the block diagram of the OSC3 oscillation circuit.

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Fig. 4.3.2

OSC3 oscillation circuit

Note

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Oscillation Circuit)

OSC3

To CPU (SIO)

OSC4

Oscillation circuit control signal

S1C6S3A2

OSC3

To CPU (SIO)

Ceramic

OSC4

Oscillation circuit control signal

S1C6S3A2

The figure above is an equivalent circuit and is different from the actual circuit.

As indicated in Figure 4.3.2, the CR oscillation circuit can be configured simply by connecting the resistor (RCR) between terminals OSC3 and OSC4 when CR oscillation is selected. When 33 kΩ is used for RCR, the oscillation frequency is about 1 MHz. When ceramic oscillation is selected, the ceramic oscillation circuit can be configured by connecting the ceramic oscillator (Typ. 1 MHz) between terminals OSC3 and OSC4 to the two capacitors (CGC and CDC) located between terminals OSC3 and OSC4 and VDD. For both CGC and CDC, connect capacitors that are about 100 pF. To lower current consumption of the OSC3 oscillation circuit, oscillation can be stopped through the software.

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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Oscillation Circuit)

Configuration of oscillation circuit

Fig. 4.3.3

Oscillation system

The S1C6S3N2, 6S3L2 and 6S3B2 have one oscillation circuit (OSC1), and the S1C6S3A2 has two oscillation circuits (OSC1 and OSC3). OSC1 is a crystal oscillation circuit that supplies the operating clock the CPU and peripheral circuits. OSC3 is either a CR or ceramic oscillation circuit. When processing with the S1C6S3A2 requires highspeed operation, the CPU operating clock can be switched from OSC1 to OSC3. Figure 4.3.3 is the block diagram of this oscillation system.

OSC1 oscillation circuit

OSC3 oscillation circuit

Clock switch

CPU clock selection signal

Oscillation circuit control signal

To peripheral circuit

To CPU

For S1C6S3A2, selection of either OSC1 or OSC3 for the CPU's operating clock can be made through the software.

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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Oscillation Circuit)

Control of oscillation circuit

Table 4.3.1 lists the control bits and their addresses for the oscillation circuit.

Table 4.3.1 Control bits of oscillation circuit and prescaler

Address Comment

0FEH

D3 D2 D1 D0 Name SR

CLKCHG

OSCC IOC1R0

R/W

CLKCHG

OSCC

IOC1

*1 Initial value at the time of initial reset *2 Not set in the circuit *3 Undefined *4 Reset (0) immediately after being read *5 Constantly "0" when being read

OSCC:

OSC3 oscillation control

Controls oscillation ON/OFF for the OSC3 oscillation circuit. (S1C6S3A2 only.)

(0FEH·D1)

When "1" is written : The OSC3 oscillation ON When "0" is written : The OSC3 oscillation OFF Read-out : Valid

–

OSC3

Output

OSC1

OFF

Input

Unused

CPU clock switch

OSC3 oscillator ON/OFF

I/O control register 1 (P10–P13)

When it is necessary to operate the CPU of the S1C6S3A2 at high speed, set OSCC to "1". At other times, set it to "0" to lessen the current consumption. For the S1C6S3N2, 6S3L2 and 6S3B2, keep OSCC set to "0". At initial reset, OSCC is set to "0".

CLKCHG:

The CPU's clock switch

(0FEH·D2)

The CPU's operation clock is selected with this register. (S1C6S3A2 only.)

When "1" is written : OSC3 clock is selected When "0" is written : OSC1 clock is selected Read-out : Valid

When the S1C6S3A2's CPU clock is to be OSC3, set CLKCHG to "1"; for OSC1, set CLKCHG to "0". This register cannot be controlled for the S1C6S3N2, 6S3L2 and 6S3B2, so that OSC1 is selected no matter what the set value.

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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Oscillation Circuit)

Programming notes

At initial reset, CLKCHG is set to "0". (1)It takes at least 5 ms from the time the OSC3 oscillation

circuit goes ON until the oscillation stabilizes. Consequently, when switching the CPU operation clock from OSC1 to OSC3, do this after a minimum of 5 ms have elapsed since the OSC3 oscillation went ON. Further, the oscillation stabilization time varies depending on the external oscillator characteristics and conditions of use, so allow ample margin when setting the wait time.

(2)When switching the clock form OSC3 to OSC1, use a

separate instruction for switching the OSC3 oscillation OFF. An error in the CPU operation can result if this processing is performed at the same time by the one instruction.

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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports)

4.4

Input Ports (K00–K03, K10)

Configuration of input ports

Fig. 4.4.1

Configuration of

input port

The S1C6S3N2 Series has five bits general-purpose input ports. Each of the input port terminals (K00–K03, K10) provides internal pull-down resistor. Pull-down resistor can be selected for each bit with the mask option. Figure 4.4.1 shows the configuration of input port.

Interrupt request

Address

Vss

Mask option

Selection of "pull-down resistance enabled" with the mask option suits input from the push switch, key matrix, and so forth. When "pull-down resistance disabled" is selected, the port can be used for slide switch input and interfacing with other LSIs.

Data bus

Further, the input port terminal K10 or K03 is used as the input terminals for the event counter. (See "4.10 Event Counter" for details.)

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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports)

Differential registers and interrupt function

Data bus

Fig. 4.4.2

Input interrupt circuit

configuration

(K00–K03, K10)

All five bits of the input ports (K00–K03, K10) provide the interrupt function. The conditions for issuing an interrupt can be set by the software. Further, whether to mask the interrupt function can be selected individually for all five bits by the software. Figure 4.4.2 shows the configuration of K00–K03 and K10.

Address

Differential register (DFK)

Interrupt mask register (EIK)

Address

One for each terminal series

Noise rejector

Mask option (K00–K03, K10)

Interrupt factor flag (IK)

Address

The input interrupt timing for K00–K03 and K10 depends on the value set for the differential registers (DFK00–DFK03 and DFK10). Interrupt can be selected to occur at the rising or falling edge of the input. The interrupt mask registers (EIK00–EIK03, EIK10) enables the interrupt mask to be selected individually for K00–K03 and K10. However, whereas the interrupt function is enabled inside K00–K03, the interrupt occurs when the contents change from matching those of the differential register to non-matching contents. Interrupt for K10 can be generated by setting the same conditions individually. When the interrupt is generated, the interrupt factor flag (IK0 and IK1) is set to "1". Figure 4.4.3 shows an example of an interrupt for K00–K03.

Interrupt request

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Fig. 4.4.3

Example of interrupt of

K00–K03

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports)

Interrupt mask register Differential register

EIK03 EIK02 EIK01 EIK00 DFK03 DFK02 DFK01 DFK00

1110 1 0 1 0

With the above setting, the interrupt for K00–K03 occurs in the following conditions.

Input port

(1) K03 K02 K01 K00

1 0 1 0 (Initial value)

↓

(2) K03 K02 K01 K00

1011

↓

(3) K03 K02 K01 K00

0011 →

↓

(4) K03 K02 K01 K00

0111

Interrupt generated

K00 is masked, so the three bits of K01–K03 cease matching those of the differential register DFK01–DFK03, and an interrupt occurs.

K00 is masked by the interrupt mask register (EIK00), so that an interrupt does not occur at (2). At (3), K03 changes to "0"; the data of the terminal that is interrupt enabled no longer matches the data of the differential register, so that interrupt occurs. As already explained, the condition for the interrupt to occur is the change in the port data and contents of the differential register from matching to nonmatching. Hence, in (4), when the nonmatching status changes to another nonmatching status, an interrupt does not occur. Further, terminals that have been masked for interrupt do not affect the conditions for interrupt generation.

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Mask option

The contents that can be selected with the input port mask option are as follows:

(1)Internal pull-down resistor can be selected for each of the

five bits of the input ports (K00–K03, K10). When you have selected "pull-down resistor disabled", take care that the floating status does not occur for the input. Select "pull-down resistor enabled" for input ports that are not being used.

(2)The input interrupt circuit contains a noise rejector for

preventing interrupt occurring through noise. The mask option enables selection of whether to use the noise rejector for each separate terminal series. When "Use" is selected, a maximum delay of 1 ms occurs from the time interrupt condition is established until the interrupt factor flag (IK) is set to "1".

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Control of input ports

Table 4.4.1 Input port control bits

Address Comment

D3 D2 D1 D0 Name 0

K03 K02 K01 K00

073H

DFK03 DFK02 DFK01 DFK00

074H

EIK03 EIK02 EIK01 EIK00

075H

R/W

Table 4.4.1 list the input ports control bits and their addresses.

K03

K02

K01

K00

DFK03

DFK02

DFK01

DFK00

EIK03

EIK02

EIK01

–

High

–

High

–

High

–

High

Falling

Enable

Low

Input port (K00–K03)

Low

Rising

Differential register

Rising

(K00–K03)

Rising

Mask

Interrupt mask register

Mask

(K00–K03)

Mask

EIK00

EIK10 DFK10 K10

R/W

EIK10

–

077H

07AH

IK1 IK0 SWIT1 SWIT0

DFK10

K10

IK1

IK0

SWIT1

SWIT0

–

*1 Initial value at the time of initial reset *2 Not set in the circuit *3 Undefined *4 Reset (0) immediately after being read *5 Constantly "0" when being read

Enable

Falling

High

Yes

Mask

Unused

Mask

Interrupt mask register (K10)

Rising

Differential register (K10)

Low

Input port (K10) Interrupt factor flag

(K10) Interrupt factor flag

(K00–K03) Interrupt factor flag

(stopwatch 1 Hz) Interrupt factor flag

(stopwatch 10 Hz)

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K00–K03, K10:

Input port data

(073H, 077H·D0)

DFK00–DFK03, DFK10:

Differential registers

(074H, 077H·D1)

Input data of the input port terminals can be read out with these registers.

When "1" is read out : High level When "0" is read out : Low level Writing : Invalid

The read-out is "1" when the terminal voltage of the five bits of the input ports (K00–K03, K10) goes high (VDD), and "0" when the voltage goes low (VSS). These bits are dedicated for read-out, so writing cannot be done.

Interrupt conditions can be set with these registers.

When read out is "1" : Falling edge When read out is "0" : Rising edge Read-out : Valid

The interrupt conditions can be set for the rising or falling edge of input for each of the five bits (K00–K03 and K10), through the differential registers (DFK00–DFK03 and DFK10). At initial reset, these registers are set to "0".

EIK00–EIK03, EIK10:

Interrupt mask registers

(075H, 077H·D2)

Masking the interrupt of the input port terminals can be selected with these registers.

When "1" is written : Enable When "0" is written : Mask Read-out : Valid

With these registers, masking of the input port bits can be selected for each of the five bits. At initial reset, these registers are all set to "0".

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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports)

IK0, IK1:

Interrupt factor flags

(07AH·D2 and D3)

These flags indicate the occurrence of input interrupt.

When "1" is read out : Interrupt has occurred When "0" is read out : Interrupt has not occurred Writing : Invalid

The interrupt factor flags IK0 and IK1 are associated with K00–K03 and K10, respectively. From the status of these flags, the software can decide whether an input interrupt has occurred. These flags are reset when the software reads them. Reading of interrupt factor flags is available at EI, but be careful in the following cases. If the interrupt mask register value corresponding to the interrupt factor flags to be read is set to "1", an interrupt request will be generated by the interrupt factor flags set timing, or an interrupt request will not be generated. Be very careful when interrupt factor flags are in the same address. At initial reset, these flags are set to "0".

Programming notes

(1)When input ports are changed from high to low by pull-

down resistance, the fall of the waveform is delayed on account of the time constant of the pull-down resistance and input gate capacitance. Hence, when fetching input ports, set an appropriate wait time. Particular care needs to be taken of the key scan during key matrix configuration. Aim for a wait time of about 1 ms.

(2)When "noise rejector circuit enable" is selected with the

mask option, a maximum delay of 1 ms occurs from time the interrupt conditions are established until the interrupt factor flag (IK) is set to "1" (until the interrupt is actually generated). Hence, pay attention to the timing when reading out (resetting) the interrupt factor flag. For example, when performing a key scan with the key matrix, the key scan changes the input status to set the interrupt factor flag, so it has to be read out to reset it.

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However, if the interrupt factor flag is read out immediately after key scanning, the delay will cause the flag to be set after read-out, so that it will not be reset.

(3)Input interrupt programing related precautions

Differential register

Fig. 4.4.4

Input interrupt timing

Port K input

Mask register

When the content of the mask register is rewritten, while the port K input is in the active status. The input interrupt factor flags are set at ➀ and ➁, ➀ being the interrupt due to the falling edge and ➁ the interrupt due to the rising edge.

Active status

Falling edge interrupt

Factor flag set Not set ➁ Factor flag set

➀

Rising edge interrupt

Active status

When using an input interrupt, if you rewrite the content of the mask register, when the value of the input terminal which becomes the interrupt input is in the active status, the factor flag for input interrupt may be set. Therefore, when using the input interrupt, the active status of the input terminal implies

input terminal = Low status, when the falling edge

interrupt is effected and

input terminal = High status, when the rising edge

interrupt is effected. When an interrupt is triggered at the falling edge of an input terminal, a factor flag is set with the timing of ➀ shown in Figure 4.4.4. However, when clearing the content of the mask register with the input terminal kept in the Low status and then setting it, the factor flag of the input interrupt is again set at the timing that has been set. Consequently, when the input terminal is in the active status (Low status), do not rewrite the mask register (clearing, then setting the mask register), so that a factor flag will only set at the falling edge in this case. When clearing, then setting the mask register, set the mask register, when the input terminal is not in the active status (High status).

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When an interrupt is triggered at the rising edge of the input terminal, a factor flag will be set at the timing of ➁ shown in Figure 4.4.4. In this case, when the mask registers cleared, then set, you should set the mask register, when the input terminal is in the Low status. In addition, when the mask register = "1" and the content of the differential register is rewritten in the input terminal active status, an input interrupt factor flag may be set. Thus, you should rewrite the content of the differential register in the mask register = "0" status.

(4)Reading of interrupt factor flags is available at EI, but be

careful in the following cases. If the interrupt mask register value corresponding to the interrupt factor flags to be read is set to "1", an interrupt request will be generated by the interrupt factor flags set timing, or an interrupt request will not be generated. Be very careful when interrupt factor flags are in the same address.

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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports)

Output Ports (R00–R03, R10–R13)

4.5

Configuration of output ports

The S1C6S3N2 Series has general output ports (4 bits x 2). Output specifications of the output ports can be selected individually with the mask option. Two kinds of output specifications are available: complementary output and Pch open drain output. Further, the mask option enables the output ports R10, R12, and R13 to be used as special output ports. The R10, R11 and R13 ports have larger drive capability than the R00–R03 and R12 ports. Figure 4.5.1 shows the configuration of the output ports.

Data bus

Fig. 4.5.1

Configuration of output ports

Mask option

Address

Mask option

The mask option enables the following output port selection.

(1)Output specifications of output ports

Output specifications for the output ports (R00–R03, R10–R13) enable selection of either complementary output or Pch open drain output for each of the eight bits. However, even when Pch open drain output is selected, voltage exceeding source voltage must not be applied to the output port.

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(2)Special output

In addition to the regular DC output, special output can be selected for the output ports R10, R12, and R13 as shown in Table 4.5.1. Figure 4.5.2 shows the structure of the output ports R10–R13.

Table 4.5.1

Special output

Data bus

Pin Name When Special Output Selected

R10 BZ R13 BZ (Only when R10 = BZ output is selected) R12 FOUT

(R10)

(R13)

(Without SW)

R10

R13

Address (07CH)

(R11)

(R12 )

FOUT

Mask option

R11

R12

Fig. 4.5.2

Structure of output port

R10–R13

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BZ, BZ

(R10, R13)

Note

Fig. 4.5.3

Output waveform of

BZ and BZ

FOUT

(R12)

BZ and BZ are the buzzer signal output for driving the piezoelectric buzzer. The buzzer signal frequency of 2 or 4 kHz can be selected by software.

When the BZ and BZ output signals are turned ON or OFF, a hazard can result. When DC output is set for the output port R10, the output port R13 cannot be set for BZ output.

Figure 4.5.3 shows the output waveform for BZ and BZ.

BZ output (R10 terminal)

BZ output (R13 terminal)

"H"

"L" "H"

"L"

When the output port R12 is set for FOUT output, it outputs the clock of fOSC1 or the demultiplied fOSC1. The clock frequency is selectable with the mask options, from the frequencies listed in Table 4.5.2.

Table 4.5.2

FOUT clock frequency

Note

Setting Value

OSC1 /1 32,768

f f

OSC1 /2 16,384 OSC1 /4 8,192

f f

OSC1 /8 4,096 OSC1 /16 2,048

f f

OSC1 /32 1,024 OSC1 /64 512

f f

OSC1 /128 256

A hazard may occur when the FOUT signal is turned ON or

Clock Frequency (Hz)

OSC1 = 32,768

OFF.

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Control of output ports

Table 4.5.3 Control bits of output ports

Address Comment

D3 D2 D1 D0 Name 0

R03 R01 R00

07BH

R13

07CH

BZFQ BZFQ

0F6H

R02

R/W

R12 R11 R10

R/W

000

Table 4.5.3 lists the output ports' control bits and their addresses.

R03

R02

R01

R00

R13

R12

R11

R10

RR/W

–

Low

High

Low

High

Low

High

Low

High

Low

High

Low

High

Low

High

Low

High

2 kHz 4 kHz

Output port (R00–R03)

Output port (R13, BZ)

Output port (R12, FOUT)

Output port (R11)

Output port (R10, BZ)

Buzzer frequency selection register

Unused

*1 Initial value at the time of initial reset *2 Not set in the circuit *3 Undefined *4 Reset (0) immediately after being read *5 Constantly "0" when being read

R00–R03, R10–R13

Sets the output data for the output ports.

(when DC output):

Output port data

(07BH, 07CH)

When "1" is written : High output When "0" is written : Low output Read-out : Valid

The output port terminals output the data written in the corresponding registers (R00–R03, R10–R13) without changing it. When "1" is written in the register, the output port terminal goes high (VDD), and when "0" is written, the output port terminal goes low (VSS). At initial reset, all registers are set to "0".

–

Unused

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R10, R13 (when BZ and

BZ output is selected):

Special output port data

(07CH·D0 and D3)

These bits control the output of the buzzer signals (BZ, BZ).

When "1" is written : Buzzer signal is output When "0" is written : Low level (DC) is output Read-out : Valid

BZ is output from terminal R13. With the mask option, selection can be made perform this output control by R13, or to perform output control simultaneously with BZ by R10.

• When R13 controls BZ output BZ output and BZ output can be controlled independently.

BZ output is controlled by writing data to R10, and BZ output is controlled by writing data to R13.

• When R10 controls BZ output BZ output and BZ output can be controlled simultane-

ously by writing data to R10 only. For this case, R13 can be used as a one-bit general register having both read and write functions, and data of this register exerts no affect on BZ output (output from the R13 pin).

BZFQ:

Buzzer frequency

selection register

(0F6H·D3)

At initial reset, registers R10 and R13 are set to "0".

Selects the frequency of the buzzer signal.

When "1" is written : 2 kHz When "0" is written : 4 kHz Read-out : Valid

When "1" is written to register BZFQ, the frequency of the buzzer signal is set in 2 kHz, and in 4 kHz when "0" is written. At initial reset, BZFQ is set to "0" (4 kHz).

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R12

(when FOUT is selected):

Special output port data

(07CH·D2)

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports)

Controls the FOUT (clock) output.

When "1" is written : Clock output When "0" is written : Low level (DC) output Read-out : Valid

FOUT output can be controlled by writing data to R12. At initial reset, this register is set to "0".

Programming note

When BZ, BZ and FOUT are selected with the mask option, a hazard may be observed in the output waveform when the data of the output register changes.

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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (I/O Ports)

I/O Ports (P00–P03, P10–P13)

4.6

Configuration of I/O ports

Fig. 4.6.1

Configuration of I/O ports

The S1C6S3N2 Series has general-purpose I/O ports (4 bits x 2). Figure 4.6.1 shows the configuration of the I/O ports. The four bits of each of the I/O ports P00–P03 and P10–P13 can be set to either input mode or output mode. Modes can be set by writing data to the I/O control register.

Input control

Data bus

Address

I/O control register

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I/O control register and I/O mode

Mask option

Input or output mode can be set for the four bits of I/O port P00–P03 and I/O port P10–P13 by writing data into the corresponding I/O control register IOC0 and IOC1.

To set the input mode, "0" is written to the I/O control register. When an I/O port is set to input mode, it becomes high impedance status and works as an input port. However, the input line is pulled down when input data is read.

The output mode is set when "1" is written to the I/O control register. When an I/O port set to output mode works as an output port, it outputs a high signal (VDD) when the port output data is "1", and a low signal (VSS) when the port output data is "0".

At initial reset, the I/O control registers are set to "0", and the I/O port enters the input mode.

The output specification during output mode (IOC = "1") of these I/O ports can be set with the mask option for either complementary output or Pch open drain output. This setting can be performed for each bit of each port. However, when Pch open drain output has been selected, voltage in excess of the power voltage must not be applied to the port.

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Control of I/O ports

Table 4.6.1 I/O port control bits

Address Comment

07DH

07EH

0FDH

D3 D2 D1 D0 Name 0 P03 P02 P01 P00

SWRUN SWRST IOC0

TMRST

W R/W W R/W

P13

P12 P11 P10

Table 4.6.1 lists the I/O ports' control bits and their addresses.

R/W

P03

P02

P01

P00

TMRST

SWRUN

SWRST

IOC0

P13

P12

P11

Reset

–

Reset

RUN

Reset

Output

–

High

Low

I/O port (P00–P03)

Low

Output latch reset at time of SR

Low

–

Clock timer reset

STOP

Stopwatch counter RUN/STOP

–

Stopwatch counter reset

Input

I/O control register 0 (P00–P03)

Low

I/O port (P10–P13) Output latch reset at time of SR

Low

–

CLKCHG

OSCC IOC1

R/W

P10

CLKCHG

0FEH

OSCC

IOC1

*1 Initial value at the time of initial reset *2 Not set in the circuit *3 Undefined *4 Reset (0) immediately after being read *5 Constantly "0" when being read

High

OSC3

Output

Low

Unused

OSC1

CPU clock switch

OFF

OSC3 oscillator ON/OFF

Input

I/O control register 1 (P10–P13)

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P00–P03, P10–P13:

I/O port data

(07DH, 0FDH)

I/O port data can be read and output data can be set through these ports.

• When writing data

When "1" is written : High level When "0" is written : Low level

When an I/O port is set to the output mode, the written data is output unchanged from the I/O port terminal. When "1" is written as the port data, the port terminal goes high (VDD), and when "0" is written, the level goes low (VSS). Port data can be written also in the input mode.

• When reading data out

When "1" is read out : High level When "0" is read out : Low level

The terminal voltage level of the I/O port is read out. When the I/O port is in the input mode the voltage level being input to the port terminal can be read out; in the output mode the output voltage level can be read. When the terminal voltage is high (VDD) the port data that can be read is "1", and when the terminal voltage is low (VSS) the data is "0". Further, the built-in pull-down resistance goes ON during read-out, so that the I/O port terminal is pulled down.

Note

- When the I/O port is set to the output mode and a low-impedance load is connected to the port terminal, the data written to the register may differ from the data read out.

- When the I/O port is set to the input mode and a low-level voltage (VSS) is input, erroneous input results if the time constant of the capacitive load of the input line and the built-in pull-down resistance load is greater than the read-out time. When the input data is being read out, the time that the input line is pulled down is equivalent to 1.5 cycles of the CPU system clock. However, the electric potential of the terminals must be settled within 0.5 cycles. If this condition cannot be fulfilled, some measure must be devised such as arranging pull-down resistance externally, or performing multiple read-outs.

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IOC0, IOC1:

I/O control registers

(07EH·D0, 0FEH·D0)

Programming notes

The input and output modes of the I/O ports can be set with these registers.

When "1" is written : Output mode When "0" is written : Input mode Read-out : Valid

The input and output modes of the I/O ports are set in units of four bits. IOC0 sets the mode for P00–P03, and IOC1 sets the mode for P10–P13. Writing "1" to the I/O control register makes the corresponding I/O port enter the output mode, and writing "0" induces the input mode. At initial reset, these two registers are set to "0", so the I/O ports are in the input mode.

(1)When the I/O port is being read out, the built-in pull-

down resistance of the I/O port goes ON. Consequently, if data is read out while the CPU is running in the OSC3 oscillation circuit, data must be read out continuously for about 500 µs.

(2)When the I/O port is set to the output mode and the data

register has been read, the terminal data instead of the register data can be read out. Because of this, if a lowimpedance load is connected and read-out performed, the value of the register and the read-out result may differ.

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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)

LCD Driver (COM0–3, SEG0–37)

4.7

Configuration of LCD driver

The S1C6S3N2 Series has four common terminals and 38 segment terminals, so that it can drive an LCD with a maximum of 152 (38 x 4) segments. The mask option can select the LCD system power supply to generate power by the internal circuit of the CPU or to supply power from outside of the IC. The driving method is 1/4 duty (or 1/3, 1/2 duty by mask option) dynamic drive, adopting the four types of potential (1/3 bias), VDD, VL1, VL2 and VL3. Moreover, the 1/2 bias dynamic drive that uses three types of potential, VDD, VL1 = VL2 and VL3, can be selected by setting the mask option (drive duty can also be selected from 1/4, 1/3 or 1/2). 1/2 bias drive is effective when the LCD system regulated voltage circuit is not used. The VL1 terminal and the VL2 terminal should be connected outside of the IC. The frame frequency is fOSC1/1,024 Hz for 1/4 duty, fOSC1/ 768 Hz for 1/3 duty, and fOSC1/1,024 Hz for 1/2 duty. Figure 4.7.1 shows the drive waveform for 1/4 duty (1/3 bias), Figure 4.7.2 shows the drive waveform for 1/3 duty (1/3 bias), Figure 4.7.3 shows the drive waveform for 1/2 duty (1/3 bias), Figure 4.7.4 shows the drive waveform for 1/4 duty (1/2 bias), Figure 4.7.5 shows the drive waveform for 1/3 duty (1/2 bias) and Figure 4.7.6 shows the drive waveform for 1/2 duty (1/2 bias).

Note

OSC1

indicates the oscillation frequency of the OSC1 oscillation

circuit.

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COM0

COM1

LCD lighting status

-V

COM0

-V

COM1

-V

COM2 COM3

COM2

COM3

SEG 0–37

SEG0–37

Not lit Lit

-V

Fig. 4.7.1

Frame frequency

Drive waveform for

1/4 duty (1/3 bias)

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COM0

COM1

COM2

COM3

SEG 0–37

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)

LCD lighting status

-V

COM0

-V

COM1

-V

COM2

SEG0–37

Not lit Lit

-V

Fig. 4.7.2

Drive waveform for

1/3 duty (1/3 bias)

Fig. 4.7.3

Drive waveform for

1/2 duty (1/3 bias)

COM0

COM1

COM2

COM3

SEG 0–37

Frame frequency

LCD lighting status

-V

COM0

-V

COM1

-V

SEG0–37

Not lit Lit

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COM0

COM1

LCD lighting status

-V

L1,L2

COM0

-V

COM1 COM2 COM3

COM2

COM3

SEG 0–37

SEG0–37

Not lit Lit

-V

L1,L2

-V

Fig. 4.7.4

Frame frequency

Drive waveform for

1/4 duty (1/2 bias)

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COM0

COM1

COM2

COM3

SEG 0–37

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)

LCD lighting status

-V

L1,L2

COM0

-V

COM1 COM2

SEG0–37

Not lit Lit

-V

L1,L2

-V

Fig. 4.7.5

Drive waveform for

1/3 duty (1/2 bias)

Fig. 4.7.6

Drive waveform for

1/2 duty (1/2 bias)

COM0

COM1

COM2

COM3

SEG 0–37

Frame frequency

LCD lighting status

-V

L1,L2

COM0

-V

COM1

-V

L1,L2

-V

SEG0–37

Not lit Lit

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Switching between dynamic and ALL OFF

The S1C6S3N2 Series provides software setting of the LCD ALL OFF. This function enables easy ALL OFF of the LCD panel. (COM and SEG terminals output a constant voltage.)

The procedure for executing ALL OFF of the LCD is as follows:

• Write "0" to the register CSDC at address 078H, D3.

To turn the LCD on and to set dynamic drive:

• Write "1" to the register CSDC at address 078H, D3.

At initial reset, the LCD goes into ALL OFF state.

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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)

Mask option (segment allocation)

Address

06AH d c b a 06BH p g f e 06CH d' c' b' a' 06DH p' g' f' e'

Segment data memory allocation

(1)Segment allocation

As shown in Figure 4.1.2, segment data of the S1C6S3N2 Series is decided depending on display data written to the segment data memory (write-only) at address 40H–6FH or C0H–EFH.

➀ The mask option enables the segment data memory to

be allocated entirely to either 40H–6FH or C0H–EFH.

➁ The address and bits of the segment data memory can

be made to correspond to the segment pins (SEG0– SEG37) in any form through the mask option. This makes design easy by increasing the degree of freedom with which the liquid crystal panel can be designed.

Figure 4.7.7 shows an example of the relationship between the LCD segments (on the panel) and the segment data memory (when 40H–6FH is selected) for the case of 1/3 duty.

Data

D3 D2 D1 D0

SEG10 6A, D0 6B, D1 6B, D0

SEG11 6A, D1 6B, D2 6A, D3

→

SEG12 6D, D1 6A, D2 6B, D3

Common 0 Common 1 Common 2

(a) (f) (e)

(b) (g) (d)

(f' ) (c) (p)

Pin address allocation

↑

aa'

Fig. 4.7.7

Segment allocation

ee'

SEG10 SEG11 SEG12

Common 0 Common 1 Common 2

Example of LCD panel

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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)

(2)Drive duty

With the mask option, either 1/4, 1/3 or 1/2 duty can be selected for the LCD drive duty. Table 4.7.1 shows the differences in the number of segments depending on the selected duty.

Table 4.7.1 Differences depending on selected duty

Duty Pins used in common Maximum number of segments Frame frequency

1/4 COM0–3 152 (38 x 4) fOSC1/1,024 (32 Hz) 1/3 COM0–2 114 (38 1/2 COM0–1 76 (38

x 3) fOSC1/768 (42.7 Hz)

x 2) fOSC1/1,024 (32 Hz)

(3)Output specification

➀ The segment pins (SEG0–SEG37) are selected with the

mask option in pairs for either segment signal output or DC output (VDD and VSS binary output). When DC output is selected, the data corresponding to COM0 of each segment pin is output.

(when f

OSC1

= 32 kHz)

Note

➁ When DC output is selected, either complementary

output or Pch open drain output can be selected for each pin with the mask option.

The pin pairs are the combination of SEG2*n and SEG2*n + 1 (where n is an integer from 0 to 18).

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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)

Control of LCD driver

Table 4.7.2 Control bits of LCD driver

Address Comment

078H

D3 D2 D1 D0 Name 0

CSDC ETI2 ETI8 ETI32

*1 Initial value at the time of initial reset *2 Not set in the circuit *3 Undefined *4 Reset (0) immediately after being read *5 Constantly "0" when being read

Address

Page High

R/W

Low

4 or C 5 or D 6 or E

Table 4.7.2 shows the LCD driver's control bits and their addresses. Figure 4.7.8 shows the segment data memory map.

CSDC

ETI2

ETI8

ETI32

0123456789ABCDEF

Segment data memory (38 words x 4 bits)

Dynamic

Enable

40H–6FH = R/W

C0H–EFH = W

ALL OFF

Mask

LCD drive switch Interrupt mask register

(clock timer 2 Hz) Interrupt mask register (clock timer 8 Hz) Interrupt mask register (clock timer 32 Hz)

Fig. 4.7.8

Segment data memory map

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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)

CSDC:

LCD drive switch

(078H·D3)

Segment data memory

(40H–6FH or C0H–EFH)

The LCD drive mode can be selected with this switch.

When "1" is written : Dynamic drive (Normal mode) When "0" is written : LCD ALL OFF (ALL OFF mode) Read-out : Valid

At initial reset, this register is set to LCD ALL OFF.

The LCD segments are lit or turned off depending on this data.

When "1" is written : Lit When "0" is written : Not lit Read-out : Valid for 40H–6FH

Undefined C0H–EFH

By writing data into the segment data memory allocated to the LCD segment (on the panel), the segment can be lit or put out. At initial reset, the contents of the segment data memory are undefined.

Programming notes

(1)When 40H–6FH is selected for the segment data memory,

the memory data and the display will not match until the area is initialized (through, for instance, memory clear processing by the CPU). Initialize the segment data memory by executing initial processing.

(2)When C0H–EFH is selected for the segment data memory,

that area becomes write-only. Consequently, data cannot be rewritten by arithmetic operations (such as AND, OR, ADD, SUB).

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Clock Timer

4.8

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Clock Timer)

Configuration of clock timer

Fig. 4.8.1

Block diagram of clock timer

The S1C6S3N2 Series has a built-in clock timer as the source oscillator for OSC1 (crystal oscillator). The clock timer is configured of a seven-bit binary counter that serves as the input clock, a 256 kHz signal output by the prescaler. Data of the four high-order bits (16 Hz–2 Hz) can be read out by the software. Figure 4.8.1 is the block diagram for the clock timer.

Data bus

OSC1 oscillation circuit

Clock timer reset signal

256 Hz

128 Hz–32 Hz

16 Hz–2 Hz

Interrupt control

32 Hz, 8 Hz, 2 Hz

Interrupt request

Ordinarily, this clock timer is used for all types of timing functions such as clocks.

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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Clock Timer)

Interrupt function

070H

Fig. 4.8.2

Timing chart of

clock timer

32 Hz interrupt request

8 Hz interrupt request 2 Hz interrupt request

The clock timer can cause interrupts at the falling edge of 32 Hz, 8 Hz and 2 Hz signals. Software can set whether to mask any of these frequencies. Figure 4.8.2 is the timing chart of the clock timer.

Frequency

RegisterAddress

D0 16 Hz D1 D2 D3

8 Hz 4 Hz 2 Hz

Clock timer timing chart

As shown in Figure 4.8.2, interrupt is generated at the falling edge of the frequencies (32 Hz, 8 Hz, 2 Hz). At this time, the corresponding interrupt factor flag (TI32, TI8, TI2) is set to "1". Selection of whether to mask the separate interrupts can be made with the interrupt mask registers (ETI32, ETI8, ETI2). However, regardless of the interrupt mask register setting, the interrupt factor flag is set to "1" at the falling edge of the corresponding signal.

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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Clock Timer)

Control of clock timer

Table 4.8.1 Control bits of clock timer

Address Comment

D3 D2 D1 D0 Name SR 1 0

TM3 TM2 TM1 TM0RTM3

070H

CSDC0ETI2 ETI8 ETI32

078H

079H

TMRST

R/W

TI2 TI8 TI32

SWRUN SWRST IOC0

Table 4.8.1 shows the clock timer control bits and their addresses.

TM2

TM1

TM0

CSDC

ETI2

ETI8

ETI32

TI2

TI8

TI32

TMRST

Dynamic

Enable

–

Yes

Reset

Timer data (clock timer 2 Hz)

Timer data (clock timer 4 Hz)

Timer data (clock timer 8 Hz)

Timer data (clock timer 16 Hz)

LCD drive switch

ALL OFF

Interrupt mask register

Mask

(clock timer 2 Hz) Interrupt mask register

Mask

(clock timer 8 Hz) Interrupt mask register

Mask

(clock timer 32 Hz) Unused

Interrupt factor flag

(clock timer 2 Hz) Interrupt factor flag

(clock timer 8 Hz) Interrupt factor flag

(clock timer 32 Hz)

–

Clock timer reset

07EH

W R/W W R/W

SWRUN

SWRST

IOC0

Reset

RUN

Reset

Output

STOP

Stopwatch counter RUN/STOP

–

Stopwatch counter reset

Input

I/O control register 0 (P00–P03)

*1 Initial value at the time of initial reset *2 Not set in the circuit *3 Undefined *4 Reset (0) immediately after being read *5 Constantly "0" when being read

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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Clock Timer)

TM0–TM3:

Timer data

(070H)

ETI32, ETI8, ETI2:

Interrupt mask registers

(078H·D0–D2)

TI32, TI8, TI2:

Interrupt factor flags

(079H·D0–D2)

The 16 Hz–2 Hz timer data of the clock timer can be read out with this register. These four bits are read-out only, and writing operations are invalid. At initial reset, the timer data is initialized to "0H".

These registers are used to select whether to mask the clock timer interrupt.

When "1" is written : Enabled When "0" is written : Masked Read-out : Valid

The interrupt mask registers (ETI32, ETI8, ETI2) are used to select whether to mask the interrupt to the separate frequencies (32 Hz, 8 Hz, 2 Hz). At initial reset, these registers are all set to "0".

These flags indicate the status of the clock timer interrupt.

When "1" is read out : Interrupt has occurred When "0" is read out : Interrupt has not occurred Writing : Invalid

The interrupt factor flags (TI32, TI8, TI2) correspond to the clock timer interrupts of the respective frequencies (32 Hz, 8 Hz, 2 Hz). The software can judge from these flags whether there is a clock timer interrupt. However, even if the interrupt is masked, the flags are set to "1" at the falling edge of the signal. These flags can be reset through being read out by the software. Reading of interrupt factor flags is available at EI, but be careful in the following cases. If the interrupt mask register value corresponding to the interrupt factor flags to be read is set to "1", an interrupt request will be generated by the interrupt factor flags set timing, or an interrupt request will not be generated. Be very careful when interrupt factor flags are in the same address. At initial reset, these flags are set to "0".

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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Clock Timer)

TMRST:

Clock timer reset

(07EH·D3)

Programming notes

This bit resets the clock timer.

When "1" is written : Clock timer reset When "0" is written : No operation Read-out : Always "0"

The clock timer is reset by writing "1" to TMRST. The clock timer starts immediately after this. No operation results when "0" is written to TMRST. This bit is write-only, and so is always "0" at read-out.

(1)When the clock timer has been reset, the interrupt factor

flag (TI) may sometimes be set to "1". Consequently, perform flag read-out (reset the flag) as necessary at reset.

(2)The input clock of the watchdog timer is the 2 Hz signal

of the clock timer, so that the watch dog timer may be counted up at timer reset.

(3)Reading of interrupt factor flags is available at EI, but be

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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Stopwatch Counter)

Stopwatch Counter

4.9

Configuration of stopwatch counter

Fig. 4.9.1

Block diagram of

stopwatch counter

The S1C6S3N2 Series incorporates a 1/100 sec and 1/10 sec stopwatch counter. The stopwatch counter is configured of a two-stage, four-bit BCD counter serving as the input clock of an approximately 100 Hz signal (signal obtained by approximately demultiplying the 256 Hz signal output by the prescaler). Data can be read out four bits at a time by the software. Figure 4.9.1 is the block diagram of the stopwatch counter.

Data bus

OSC1 oscillation circuit

Stopwatch counter reset signal

Stopwatch counter RUN/STOP signal

256 Hz

SWL counter

10 Hz

SWH counter

10 Hz,1 Hz

Interrupt control

Interrupt request

The stopwatch counter can be used as a separate timer from the clock timer. In particular, digital watch stopwatch functions can be realized easily with software.

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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Stopwatch Counter)

Count-up pattern

SWH count up pattern

SWH count value

Count time (S)

SWL count up pattern 1

SWL count value

Count time (S)

The stopwatch counter is configured of four-bit BCD counters SWL and SWH. The counter SWL, at the stage preceding the stopwatch counter, has an approximated 100 Hz signal for the input clock. It counts up every 1/100 sec, and generates an approximated 10 Hz signal. The counter SWH has an approximated 10 Hz signal generated by the counter SWL for the input clock. It count-up every 1/10 sec, and generated 1 Hz signal. Figure 4.9.2 shows the count-up pattern of the stopwatch counter.

0 1 2 3 4 5 6 7 8 9 0

26 256

256

0 1 2 3 4 5 6 7 8 9 0

3 256

25 256

26 256

2 256

26 256

x 6 +

3 256

256

25 256

2 256

256

x 4 = 1 (S)

256

(S)

256

26 256

3 256

26 256

2 256

3 256

2 256

1 Hz signal generation

Approximate 10 Hz signal generation

SWL count up pattern 2

SWL count value

Count time (S)

Fig. 4.9.2

Count-up pattern of

stopwatch counter

0 1 2 3 4 5 6 7 8 9 0

3 256

2 256

3 256

26 256

2 256

(S)

3 256

2 256

3 256

2 256

Approximate 10 Hz signal generation

SWL generates an approximated 10 Hz signal from the basic 256 Hz signal. The count-up intervals are 2/256 sec and 3/ 256 sec, so that finally two patterns are generated: 25/256 sec and 26/256 sec intervals. Consequently, these patterns do not amount to an accurate 1/100 sec. SWH counts the approximated 10 Hz signals generated by the 25/256 sec and 26/256 sec intervals in the ratio of 4:6, to generate a 1 Hz signal. The count-up intervals are 25/ 256 sec and 26/256 sec, which do not amount to an accurate 1/10 sec.

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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Stopwatch Counter)

Interrupt function

Fig. 4.9.3

Timing chart for

stopwatch counter

The 10 Hz (approximate 10 Hz) and 1 Hz interrupts can be generated through the overflow of stopwatch counters SWL and SWH respectively. Also, software can set whether to separately mask the frequencies described earlier. Figure 4.9.3 is the timing chart for the stopwatch counter.

Address

071H

(1/100 sec BCD)

10 Hz interrupt request

Address

072H

(1/10 sec BCD)

1 Hz interrupt request

D0 D1 D2 D3

Stopwatch counter (SWL) timing chart

Stopwatch counter (SWH) timing chart

As shown in Figure 4.9.3, the interrupts are generated by the overflow of their respective counters ("9" changing to "0"). Also, at this time the corresponding interrupt factor flags (SWIT0, SWIT1) are set to "1". The respective interrupts can be masked separately through the interrupt mask registers (EISWIT0, EISWIT1). However, regardless of the setting of the interrupt mask registers, the interrupt factor flags are set to "1" by the overflow of their corresponding counters.

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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Stopwatch Counter)

Control of stopwatch counter

Table 4.9.1 list the stopwatch counter control bits and their addresses.

Table 4.9.1 Stopwatch counter control bits

Address Comment

D3 D2 D1 D0 Name 0

SWL3 SWL2 SWL1 SWL0

071H

SWH3 SWH2 SWH1 SWH0

072H

HLMOD

R/W

076H

IK1 IK0 SWIT1 SWIT0

07AH

TMRST

BLD

EISWIT1 EISWIT0

BLS

SWRUN SWRST IOC0

R/W

SWL3

SWL2

SWL1

SWL0

SWH3

SWH2

SWH1

SWH0

HLMOD

BLD BLS00

EISWIT1

EISWIT0

IK1

IK0

SWIT1

SWIT0

TMRST

Heavy

Low voltage

00Enable

Enable

Reset

load

Yes

MSB

Stopwatch counter 1/100 sec (BCD)

LSB

MSB

Stopwatch counter 1/10 sec (BCD)

LSB

Normal

Heavy load protection mode register

SVD evaluation data

Normal

SVD ON/OFF

OFF

Interrupt mask register

Mask

(stopwatch 1 Hz) Interrupt mask register

Mask

(stopwatch 10 Hz) Interrupt factor flag

(K10) Interrupt factor flag

(K00–K03) Interrupt factor flag

(stopwatch 1 Hz) Interrupt factor flag

(stopwatch 10 Hz)

Clock timer reset

07EH

W R/W W R/W

SWRUN

SWRST

IOC0

Reset

Output

RUN

Reset

STOP

Stopwatch counter RUN/STOP

Stopwatch counter reset

Input

I/O control register 0 (P00–P03)

*1 Initial value at the time of initial reset *2 Not set in the circuit *3 Undefined *4 Reset (0) immediately after being read *5 Constantly "0" when being read

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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Stopwatch Counter)

SWL0–SWL3:

Stopwatch counter

1/100 sec (071H)

SWH0–SWH3:

Stopwatch counter

1/10 sec (072H)

EISWIT0, EISWIT1:

Interrupt mask register

(076H·D0 and D1)

Data (BCD) of the 1/100 sec column of the stopwatch counter can be read out. These four bits are read-only, and cannot be used for writing operations. At initial reset, the counter data is set to "0H".

Data (BCD) of the 1/10 sec column of the stopwatch counter can be read out. These four bits are read-only, and cannot be used for writing operations. At initial reset, the counter data is set to "0H".

These registers are used to select whether to mask the stopwatch counter interrupt.

When "1" is written : Enabled When "0" is written : Masked Read-out : Valid

The interrupt mask registers (EISWIT0, EISWIT1) are used to separately select whether to mask the 10 Hz and 1 Hz interrupts. At initial reset, these registers are both set to "0".

SWIT0, SWIT1:

Interrupt factor flag

(07AH·D0 and D1)

These flags indicate the status of the stopwatch counter interrupt.

When "1" is read out : Interrupt has occurred When "0" is read out : Interrupt has not occurred Writing : Invalid

The interrupt factor flags (SWIT0, SWIT1) correspond to the 10 Hz and 1 Hz interrupts respectively. With these flags, the software can judge whether a stopwatch counter interrupt has occurred. However, regardless of the interrupt mask register setting, these flags are set to "1" by the counter overflow. These flags are reset when read out by the software. Reading of interrupt factor flags is available at EI, but be careful in the following cases. If the interrupt mask register value corresponding to the interrupt factor flags to be read is set to "1", an interrupt request will be generated by the interrupt factor flags set timing, or an interrupt request will not be generated. Be very careful when interrupt factor flags are in the same address. At initial reset, these flags are set to "0".

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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Stopwatch Counter)

SWRST:

Stopwatch counter reset

(07EH·D1)

SWRUN:

Stopwatch counter

RUN/STOP

(07EH·D2)

This bit resets the stopwatch counter.

When "1" is written : Stopwatch counter reset When "0" is written : No operation Read-out : Always "0"

The stopwatch counter is reset when "1" is written to SWRST. When the stopwatch counter is reset in the RUN status, operation restarts immediately. Also, in the STOP status the reset data is maintained. This bit is write-only, and is always "0" at read-out.

This bit controls RUN/STOP of the stopwatch counter.

When "1" is written : RUN When "0" is written : STOP Read-out : Valid

The stopwatch counter enters the RUN status when "1" is written to SWRUN, and the STOP status when "0" is written. In the STOP status, the counter data is maintained until the next RUN status or resets counter. Also, when the STOP status changes to the RUN status, the data that was maintained can be used for resuming the count. When the counter data is read out in the RUN status, correct read-out may be impossible because of the carry from the low-order bit (SWL) to the high-order bit (SWH). This occurs when read-out has extended over the SWL and SWH bits when the carry occurs. To prevent this, perform read out after entering the STOP status, and then return to the RUN status. Also, the duration of the STOP status must be within 976 µs (256 Hz 1/4 cycle). At initial reset, this register is set to "0".

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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Stopwatch Counter)

Programming notes

(1)If counter data is read out in the RUN status, the counter

must be made into the STOP status, and after data is read out the RUN status can be restored. If data is read out when a carry occurs, the data cannot be read correctly. Also, the processing above must be performed within the STOP interval of 976 µs (256 Hz 1/4 cycle).

(2)Reading of interrupt factor flags is available at EI, but be

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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Event Counter)

Configuration of event counter

Fig. 4.10.1

Configuration of

event counter

4.10

Event Counter

The S1C6S3N2 Series has an event counter that counts the clock signals input from outside. The event counter is configured of eight-bit binary counters (UP counters). The clock pulses are input through K10 pin or K03 pin of the input port. (K03 input can be selected by mask option.) Figure 4.10.1 shows the configuration of the event counter.

K10

Event counter RUN/STOP

Event counter reset

Input port

Noise rejector circuit

Interrupt request

Event counter

[EV00–EV07]

Data bus

Operation of event counter

Fig. 4.10.2

Timing chart of

event counter

The clock signal input from terminal K10 is input to the event counter via the noise rejector. (Either K10 or K03 can be selected as the event counter input by mask option.) The event counter increments when the clock signal is input, and the incremented data can be read out through the software. RUN and STOP of the event counter are performed by making the clock of the noise rejector ON and OFF. This is controlled by writing data to the EVRUN register. The counter counts up at the rising edge of the K10 input clock or the falling edge of the K03 input clock. Figure 4.10.2 is the timing chart for the event counter.

Input of K10 terminal

EVRUN

Input of event counter

Defined time

STOP

OFF

STP

ON2

≥ 1.5 T

≥ 1.0 T

< 0.5 T

≥ 0.5 T

≥ 1.5 TCH + T

OFF

STP

(Execution time)

RUN

ON2

STP

= 1/f

T Through the mask option, f selects f

OSC1

for the clock frequency of the noise rejector

/16 or f

OSC1

Noise

/128

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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Event Counter)

Mask option

Defined time depending

on frequency selected

Table 4.10.1

For the event counter input, either the K10 terminal or the K03 terminal can be selected by mask option. The clock frequency of the noise rejector can be selected as fOSC1/16 or fOSC1/128. Table 4.10.1 lists the defined time depending on the frequency selected.

Selection fOSC1/16 fOSC1/128

ON 0.74 5.86

OFF 0.49 3.91

N 0.24 1.95

STP 0.25 1.96

(Unit: msec)

OSC1 = 32.768 kHz

f T

N : Max value

Others : Min value

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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Event Counter)

Control of event counter

Table 4.10.2 Event counter control bits

Address Comment

D3 D2 D1 D0 Name 1 0

EV03 EV02 EV01 EV00

0F8H

EV07

0F9H

0FCH

EV06 EV05 EV04

EVRUN

R/W W

Table 4.10.2 shows the event counter control bits and their addresses.

EV03

EV02

EV01

EV00

EV07

EV06

EV05

EV04

EVRST

EVRUN

EVRST

Reset

–

RUN

–

Reset

Event counter Low order (EV00–EV03)

Event counter High order (EV04–EV07)

Unused

STOP

Event counter RUN/STOP

Unused

–

Event counter reset

*1 Initial value at the time of initial reset *2 Not set in the circuit *3 Undefined *4 Reset (0) immediately after being read *5 Constantly "0" when being read

EV00–EV03:

Event counter Low-order

(0F8H)

EV04–EV07:

Event counter High-order

(0F9H)

The four low-order data bits of event counter are read out. These four bits are read-only, and cannot be used for writing. At initial reset, this counter is set to "0H".

The four high-order data bits of event counter are read out. These four bits are read-only, and cannot be used for writing. At initial reset, this counter is set to "0H".

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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Event Counter)

EVRST:

Event counter reset

(0FCH·D0)

EVRUN:

Event counter RUN/STOP

(0FCH·D2)

This is the register for resetting event counter.

When "1" is written : Event counter reset When "0" is written : No operation Read-out : Always "0"

When "1" is written, event counter is reset and the data becomes "00H". When "0" is written, no operation is executed. This is a write-only bit, and is always "0" at read-out.

This register controls the event counter RUN/STOP status.

When "1" is written : RUN When "0" is written : STOP Read-out : Valid

When "1" is written, the event counter enters the RUN status and starts receiving the clock signal input. When "0" is written, the event counter enters the STOP status and the clock signal input is ignored. (However, input to the input port is valid.) At initial reset, this register is set to "0".

Programming note

To prevent erroneous reading of the event counter data, read out the counter data several times, compare it, and use the matching data as the result.

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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Analog Comparator)

4.11

Configuration of analog comparator

Fig. 4.11.1

Configuration of

analog comparator

Analog Comparator

The S1C6S3N2 Series incorporates an MOS input analog comparator. This analog comparator, which has two differential input terminals (inverted input terminal AMPM, noninverted input terminal AMPP), can be used for general purposes. Figure 4.11.1 shows the configuration of the analog comparator.

AMPP

AMPM

AMPDT

Input control

Power source

AMPON

control

Address

Data bus

Operation of analog comparator

The analog comparator is ON when the AMPON register is "1", and compares the input levels of the AMPP and AMPM terminals. The result of the comparison is read from the AMPDT register. It is "1" when AMPP (+) > AMPM (-) and "0" when AMPP (+) < AMPM (-).

After the analog comparator goes ON it takes a maximum of 3 ms until the output stabilizes.

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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Analog Comparator)

Control of analog comparator

Table 4.11.1 lists the analog comparator control bits and their addresses.

Table 4.11.1 Analog comparator control bits

Address Comment

0F7H

D3 D2 D1 D0 Name 0

AMPDT AMPONR–

––

*1 Initial value at the time of initial reset *2 Not set in the circuit *3 Undefined *4 Reset (0) immediately after being read *5 Constantly "0" when being read

AMPON:

Switches the analog comparator ON and OFF.

Analog comparator ON/

OFF (0F7H·D0)

R/W

–

AMPDT

AMPON

–

+ > -ON- > +

OFF

Unused

Analog comparator data

Analog comparator ON/OFF

When "1" is written : The analog comparator goes ON When "0" is written : The analog comparator goes OFF Read-out : Valid

The analog comparator goes ON when "1" is written to AMPON, and OFF when "0" is written. At initial reset, AMPON is set to "0".

AMPDT:

Analog comparator data

(0F7H·D1)

Reads out the output from the analog comparator.

When "1" is read out : AMPP (+) > AMPM (-) When "0" is read out : AMPP (+) < AMPM (-) Writing : Invalid

AMPDT is "0" when the input level of the inverted input terminal (AMPM) is greater than the input level of the noninverted input terminal (AMPP); and "1" when smaller. At initial reset, AMPDT is set to "1".

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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Analog Comparator)

Programming notes

(1)To reduce current consumption, set the analog compara-

tor to OFF when it is not necessary.

(2)After setting AMPON to "1", wait at least 3 ms for the

operation of the analog comparator to stabilize before reading the output data of the analog cpmparator from AMPDT.

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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (SVD Circuit and Heavy Load Protection Function)

Configuration of SVD circuit

4.12

Supply Voltage Detection (SVD) Circuit and Heavy Load Protection Function

The S1C6S3N2 Series has a built-in supply voltage detection (SVD) circuit, so that the software can find when the source voltage lowers. The configuration of the SVD circuit is shown in Figure 4.12.1. Turning the SVD operation ON/OFF is controlled through the software (HLMOD, BLS). Moreover, when a drop in source voltage (BLD = "1") is detected, SVD operation is periodically performed by the hardware until the source voltage is recovered (BLD = "0"). Because the power current consumption of the IC becomes big when the SVD operation is turned ON, set the SVD operation to OFF unless otherwise necessary. See "7 ELECTRICAL CHARACTERISTICS" for the evaluation voltage accuracy.

SVD circuit

Fig. 4.12.1

Configuration of SVD circuit

Detection output

One-shot control

Address 076H

BLS

BLD

HLMOD

Address 076H

Sampling at cycles of 2 Hz

Data bus

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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (SVD Circuit and Heavy Load Protection Function)

Heavy load protection function

Note that the heavy load protection function on the S1C6S3L2/6S3B2 is different from the S1C6S3N2/6S3A2.

(1)In case of S1C6S3L2/6S3B2

The S1C6S3L2/6S3B2 has the heavy load protection function for when the battery load becomes heavy and the source voltage drops, such as when an external buzzer sounds or an external lamp lights. The state where the heavy load protection function is in effect is called the heavy load protection mode. In this mode, operation with a lower voltage than normal is possible. The normal mode changes to the heavy load protection mode in the following two cases:

➀ When the software changes the mode to the heavy load

protection mode (HLMOD = "1")

➁ When supply voltage drop (BLD = "1") in the SVD

circuit is detected, the mode will automatically shift to the heavy load protection mode until the supply voltage is recovered (BLD = "0")

In the heavy load protection mode, the internally regulated voltage is generated by the liquid crystal driver source output VL2 so as to operate the internal circuit. Consequently, more current is consumed in the heavy load protection mode than in the normal mode. Unless it is necessary, be careful not to set the heavy load protection mode with the software. Also, when the BLS is to be turned on during operation in the heavy load protection mode, limit the ON time to 10 msec per second of operation time.

(2)In case of S1C6S3N2/6S3A2

The S1C6S3N2/6S3A2 has the heavy load protection function for when the battery load becomes heavy and the source voltage changes, such as when an external buzzer sounds or an external lamp lights. The state where the heavy load protection function is in effect is called the heavy load protection mode. Compared with the normal operation mode, this mode can reduce the output voltage variation of the constant voltage/booster voltage circuit of the LCD system. The normal mode changes to the heavy load protection mode in the following case:

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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (SVD Circuit and Heavy Load Protection Function)

➀ When the software changes the mode to the heavy load

protection mode (HLMOD = "1")

The heavy load protection mode switches the constant voltage circuit of the LCD system to the high-stability mode from the low current consumption mode. Consequently, more current is consumed in the heavy load protection mode than in the normal mode. Unless it is necessary, be careful not to set the heavy load protection mode with the software.

Detection timing of SVD circuit

This section explains the timing for when the SVD circuit writes the result of the source voltage detection to the SVD latch. Turning the SVD operation ON/OFF is controlled through the software (HLMOD, BLS). Moreover, when a drop in source voltage (BLD = "1") is detected, SVD operation is periodically performed by the hardware until the source voltage is recovered (BLD = "0"). The result of the source voltage detection is written to the SVD latch by the SVD circuit, and this data can be read out by the software to find the status of the source voltage. There are three methods, explained below, for executing the detection operation of the SVD circuit.

(1)Sampling with HLMOD set to "1"

When HLMOD is set to "1" and SVD sampling executed, the detection results can be written to the SVD latch in the following two timings.

➀ Immediately after the time for one instruction cycle

has ended immediately after HLMOD = "1"

➁ Immediately after sampling in the 2 Hz cycle output by

the clock timer while HLMOD = "1"

Consequently, the SVD latch data is loaded immediately after HLMOD has been set to "1", and at the same time the new detection result is written in 2 Hz cycles.

To obtain a stable SVD detection result, the SVD circuit must be set to ON with at least 100 µs. Consequently, when the CPU system clock is fOSC3 in S1C6S3A2, the detection result at the timing in ➀ above may be invalid or incorrect. (When performing SVD detection using the

timing in ➀, be sure that the CPU system clock is fOSC1.)

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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (SVD Circuit and Heavy Load Protection Function)

(2)Sampling with BLS set to "1"

When BLS is set to "1", SVD detection is executed. As soon as BLS is reset to "0" the detection result is loaded to the SVD latch. To obtain a stable SVD detection result, the SVD circuit must be set to ON with at least 100 µs. Hence, to obtain the SVD detection result, follow the programming sequence below.

0. Set HLMOD to "1" (only when the CPU system clock is fOSC3 in S1C6S3A2)

1. Set BLS to "1"

2. Maintain at 100 µs minimum

3. Set BLS to "0"

4. Read out BLD

5. Set HLMOD to "0" (only when the CPU system clock is fOSC3 in S1C6S3A2)

However, when a crystal oscillation clock (fOSC1) is selected for the CPU system clock in S1C6S3N2, S1C6S3L2, S1C6S3B2 and S1C6S3A2, the instruction cycles are long enough, so that there is no need for concern about maintaining 100 µs for the BLS = "1" with the software.

(3)Sampling by hardware when SVD latch is set to "1"

When SVD latch is set to "1", the detection results can be written to the SVD latch in the following two timings (same as that sampling with HLMOD set to "1").

➀ Immediately after the time for one instruction cycle

has ended immediately after BLD = "1"

➁ Immediately after sampling in the 2 Hz cycle output by

the clock timer while BLD = "1"

Consequently, the SVD latch data is loaded immediately after SVD latch has been set to "1", and at the same time the new detection result is written in 2 Hz cycles. To obtain a stable SVD detection result, the SVD circuit must be set to ON with at least 100 µs. When the CPU system clock is fOSC3 in S1C6S3A2, the detection result at the timing in ➀ above may be invalid or incorrect.

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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (SVD Circuit and Heavy Load Protection Function)

Control of SVD circuit

Table 4.12.1 shows the SVD circuit's control bits and their addresses.

Table 4.12.1 Control bits of SVD circuit

Address Comment

076H

D3 D2 D1 D0 Name 0

HLMOD

R/W

BLD

EISWIT1 EISWIT0

BLS

R/W

HLMOD

BLD BLS00

EISWIT1

EISWIT0

Heavy

Low voltage

00Enable

Enable

load

Normal

Heavy load protection mode register SVD evaluation data

Normal

SVD ON/OFF

OFF

Interrupt mask register

Mask

(stopwatch 1 Hz) Interrupt mask register

Mask

(stopwatch 10 Hz)

*1 Initial value at the time of initial reset *2 Not set in the circuit *3 Undefined *4 Reset (0) immediately after being read *5 Constantly "0" when being read

HLMOD:

Heavy load protection

mode (076H·D3)

When "1" is written : Heavy load protection mode is set When "0" is written : Heavy load protection mode

is released

Read-out : Valid

When HLMOD is set to "1", the IC operating status enters the heavy load protection mode and at the same time the supply voltage detection of the SVD circuit is controlled (ON/OFF). When HLMOD is set to "1", sampling control is executed for the SVD circuit ON time. There are two types of sampling time, as follows:

(1)Sampling at time of one instruction cycle immediately

after HLMOD = "1"

(2)Sampling at cycles of 2 Hz output by the clock timer

while HLMOD = "1"

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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (SVD Circuit and Heavy Load Protection Function)

The SVD circuit must be made ON with at least 100 µs for the SVD circuit to respond. Hence, when the CPU system clock is fOSC3 in S1C6S3A2, the detection result at the timing in (1) above may be invalid or incorrect. (When performing SVD detection using the timing in (1), be sure that the CPU system clock is fOSC1.)

When SVD sampling is done with HLMOD set to "1", the results are written to the SVD latch in the timing as follows:

(1)As soon as the time has elapsed for one instruction cycle

immediately following HLMOD = "0" → "1"

(2)Immediately on completion of sampling at cycles of 2 Hz

output by the clock timer while HLMOD = "1"

Consequently, the SVD latch data is written immediately after HLMOD is set to "0" → "1", and at the same time the new detection result is written in 2 Hz cycles.

BLS:

SVD detection (076H·D2)

BLD:

SVD data

When "0" is written : SVD detection OFF When "1" is written : SVD detection ON When "0" is read out : Source voltage (VDD–VSS)

is higher than SVD set value

When "1" is read out : Source voltage (VDD–VSS)

is lower than SVD set value

Note that the function of this bit when written is different to when read out. When this bit is written to, ON/OFF of the SVD detection operation is controlled; when this bit is read out, the result of the SVD detection (contents of SVD latch) is obtained. Appreciable current is consumed during operation of SVD detection, so keep SVD detection OFF except when necessary.

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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (SVD Circuit and Heavy Load Protection Function)

0. Set HLMOD to "1" (only when the CPU system clock is fOSC3 in S1C6S3A2)

1. Set BLS to "1"

2. Maintain at 100 µs minimum

3. Set BLS to "0"

4. Read out BLD

5. Set HLMOD to "0" (only when the CPU system clock is fOSC3 in S1C6S3A2)

Programming notes

(1)It takes 100 µs from the time the SVD circuit goes ON

until a stable result is obtained. For this reason, keep the following software notes in mind:

➀ When the CPU system clock is fOSC1

1. When detection is done at HLMOD After writing "1" on HLMOD, read the BLD after 1 instruction has passed.

2. When detection is done at BLS After writing "1" on BLS, write "0" after at least 100 µs has lapsed (the following instruction can write "0" because the instruction cycle is long enough) and then read the BLD.

➁ When the CPU system clock is fOSC3 (in case of

S1C6S3A2 only)

1. When detection is done at HLMOD After writing "1" on HLMOD, read the BLD after 0.6 second has passed. (HLMOD holds "1" for at least

0.6 second)

2. When detection is done at BLS Before writing "1" on BLS, write "1" on HLMOD first; after at least 100 µs has lapsed after writing "1" on BLS, write "0" on BLS and then read the BLD.

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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (SVD Circuit and Heavy Load Protection Function)

(2)BLS resides in the same bit at the same address as BLD,

and one or the other is selected by write or read operation. This means that arithmetic operations (AND, OR, ADD, SUB and so forth) at this address, pay attention to whether BLD is ON or OFF.

(3)Select one of the following software processing to return

to the normal mode after a heavy load has been driven in the heavy load protection mode (S1C6S3L2/6S3B2).

➀ After heavy load drive is completed, return to the

normal mode after at least one second has elapsed.

➁ After heavy load drive is completed, switch BLS ON

and OFF (at least 100 µs is necessary for the ON status) and then return to the normal mode.

The S1C6S3N2/6S3A2 returns to the normal mode after driving a heavy load without special software processing.

(4)When the BLS is to be turned on during operation in the

heavy load protection mode, limit the ON time to 10 msec per second of operation time.

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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT)

4.13 Interrupt and HALT

The S1C6S3N2 Series provides the following interrupt settings, each of which is maskable.

External interrupt : Input interrupt (two) Internal interrupt : Timer interrupt (three)

Stopwatch interrupt (two)

To authorize interrupt, the interrupt flag must be set to "1" (EI) and the necessary related interrupt mask registers must be set to "1" (enable). When an interrupt occurs the interrupt flag is automatically reset to "0" (DI), and interrupts after that are inhibited. When a HALT instruction is input the CPU operating clock stops, and the CPU enters the HALT status. The CPU is reactivated from the HALT status when an interrupt request occurs. If reactivation is not caused by an interrupt request, initial reset by the watchdog timer causes reactivates the CPU (when the watchdog timer is enabled). Figure 4.13.1 shows the configuration of the interrupt circuit.

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