Epson S1C63666 Technical Manual

CMOS 4-BIT SINGLE CHIP MICROCOMPUTER

S1C63666

Technical Manual

S1C63666 Technical Hardware

NOTICE

No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko
Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any
liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or
circuit and, further, there is no representation that this material is applicable to products requiring high level reliability, such
as medical products. Moreover, no license to any intellectual property rights is granted by implication or otherwise, and there
is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright
infringement of a third party. This material or portions thereof may contain technology or the subject relating to strategic
products under the control of the Foreign Exchange and Foreign Trade Law of Japan and may require an export license from
the Ministry of International Trade and Industry or other approval from another government agency.

© SEIKO EPSON CORPORA TION 2007, All rights reserved.

Revisions and Additions for this manual

Chapter

1

2

4

5

7

Appendix

Section

1.1

1.5

2.1.5

2.2

2.2.1

2.2.2

4.1

4.6.4

4.6.5

4.8.1

4.8.2

4.8.3

4.8.5

4.10.6

4.10.7

4.11.1

4.11.7

4.11.9

4.12.3

4.15.2

4.15.3

4.15.4

4.15.5

4.15.6

4.17.2

4.17.3

4.17.4

4.18

4.18.1

4.18.2

4.18.4

5.2

5.3

7.1

7.2

7.3

7.4

7.5

7.6

A.2

A.3.2

Page

1

5–8

11
12
12
13

17, 18, 20, 24

43–44

46
53
53
57

58
72

74, 76, 77

78
82

88
91

112

113–114

116–117

118, 120, 121

121
124
125
126

128
129
130

131–132

138
140
142
142
142
143

144
146
155
158

Item

Features
Mask Option
LCD system voltage circuit
Initial Reset
Reset terminal (RESET)
Simultaneous high input to terminals
K00–K03
Memory Map

Special output
I/O memory of output ports
Configuration of LCD driver
Power supply for LCD driving
Control of LCD display and drive waveform

Segment option
Interrupt function
I/O memory of stopwatch timer

Configuration of programmable timer
Control of TOUT output

I/O memory of programmable timer
Master mode and slave mode of serial interface
Connection terminals and CR oscillation
circuit
Operation of R/f conversion

Interrupt function

I/O memory of R/f converter

Programming notes
Mask option
SVD operation
I/O memory of SVD circuit

Interrupt and HALT
Interrupt factor
Interrupt mask
I/O memory of interrupt

Summary of Notes by Function
Precautions on Mounting
Absolute Maximum Rating
Recommended Operating Conditions
DC Characteristics
Analog Circuit Characteristics and Power
Current Consumption
Oscillation Characteristics
Serial Interface AC Characteristics
Connecting to the Target System
Differences with the actual IC

Contents

Explanation was revised.
Explanation was revised.
Figure 2.1.5.1 was revised.
Figure 2.2.1 was revised.
Explanation was added.
Explanation was revised.
Table 2.2.2.1 was revised.
Explanation was revised.
Tables 4.1.1(a), (c), (g) were revised.
Figures 4.6.4.1–4.6.4.2 were revised.
Explanation was revised.
Explanation was revised.
Explanation was revised.
Explanation was revised.
A note was added.
Figure 4.8.5.1 was revised.
Explanation was revised.
Table 4.10.7.1 was revised.
Explanation was revised.
Explanation was revised.
Figures 4.11.7.1–4.11.7.2 were revised.
Explanation was revised.
Explanation was revised.
Explanation was revised.
Explanation was revised.
Figure 4.15.2.3 was revised.
Explanation was revised.
Figures 4.15.3.1–4.15.3.2 were revised.
Explanation was revised.
Figures 4.15.4.1–4.15.4.4 were revised.
Table 4.15.5.1 was revised.
Explanation was revised.
Item (4) was added.
Explanation was revised.
Explanation was revised.
Table 4.17.4.1 was revised.
Explanation was revised.
Figure 4.18.1 was revised.
Table 4.18.1.1 was revised.
Table 4.18.2.1 was revised.
Tables 4.18.4.1(a), (b) were revised.
Explanation was revised.
Explanation was revised.
Explanation was revised.
Table was revised.
Table was revised.
Table was revised.
Table was revised.

Table was revised.
Figure was revised.
Figure A.2.1 was revised.
Explanation was revised.
Figure was deleted.

Configuration of product number

Devices

S1 C 63158 F 0A01

00

Packing specifications

00 : Besides tape & reel
0A : TCP BL 2 directions
0B : Tape & reel BACK
0C : TCP BR 2 directions
0D : TCP BT 2 directions
0E : TCP BD 2 directions
0F : Tape & reel FRONT
0G : TCP BT 4 directions
0H : TCP BD 4 directions
0J : TCP SL 2 directions
0K : TCP SR 2 directions
0L : Tape & reel LEFT
0M : TCP ST 2 directions
0N : TCP SD 2 directions
0P : TCP ST 4 directions
0Q : TCP SD 4 directions
0R : Tape & reel RIGHT
99 : Specs not fixed

Specification
Package

D: die form; F: QFP, B: BGA

Model number
Model name

C: microcomputer, digital products

Product classification

S1: semiconductor

Development tools

S5U1 C 63000 A1 1

00

Packing specifications

00: standard packing

Version

1: Version 1

Tool type

Hx : ICE
Ex : EVA board
Px : Peripheral board
Wx : Flash ROM writer for the microcomputer
Xx : ROM writer peripheral board

Cx : C compiler package
Ax : Assembler package
Dx : Utility tool by the model
Qx : Soft simulator

Corresponding model number

63000: common to S1C63 Family

Tool classification

C: microcomputer use

Product classification

S5U1: development tool for semiconductor products

CONTENTS

CONTENTS

CHAPTER

1OUTLINE ________________________________________________ 1

1.1 Features......................................................................................................... 1

1.2Block Diagram .............................................................................................. 2

1.3 Pin Layout Diagram .....................................................................................3

1.4 Pin Description ............................................................................................. 4

1.5 Mask Option.................................................................................................. 5

CHAPTER 2POWER SUPPLY AND INITIAL RESET ____________________________ 9

2.1 Power Supply ................................................................................................9

2.1.1 Voltage regulator for OSC1 oscillation circuit......................................... 10

2.1.2 Low-speed operation voltage regulator.................................................... 10

2.1.3 High-speed operation voltage regulator ................................................... 10

2.1.4 Internal operating voltage VD1....................................................................................... 10

2.1.5 LCD system voltage circuit ....................................................................... 10

2.1.6 Halver mode and saving power ................................................................ 11

2.1.7 Analog system power supply ..................................................................... 11

2.2 Initial Reset .................................................................................................. 12

2.2.1 Reset terminal (RESET) ............................................................................ 12

2.2.2 Simultaneous high input to terminals K00–K03 ...................................... 13

2.2.3 Internal register at initial resetting........................................................... 13

2.2.4 Terminal settings at initial resetting ......................................................... 14

2.3 Test Terminal (TEST) ...................................................................................14

CHAPTER 3 CPU, ROM, RAM________________________________________ 15

3.1 CPU.............................................................................................................. 15

3.2 Code ROM....................................................................................................15

3.3 RAM .............................................................................................................15

3.4 Data ROM ....................................................................................................16

CHAPTER 4PERIPHERAL CIRCUITS AND OPERATION__________________________ 17

4.1 Memory Map................................................................................................17

4.2 Power Control ..............................................................................................25

4.2.1 Configuration of power supply circuit...................................................... 25

4.2.2 Power control procedure........................................................................... 26

4.2.3 I/O memory for power control .................................................................. 27

4.2.4 Programming notes ................................................................................... 29

4.3Watchdog Timer ........................................................................................... 30

4.3.1 Configuration of watchdog timer.............................................................. 30

4.3.2 Interrupt function ...................................................................................... 30

4.3.3 I/O memory of watchdog timer ................................................................. 31

4.3.4 Programming notes ................................................................................... 31

4.4 Oscillation Circuit ....................................................................................... 32

4.4.1 Configuration of oscillation circuit .......................................................... 32

4.4.2 OSC1 oscillation circuit............................................................................ 32

4.4.3 OSC3 oscillation circuit............................................................................ 33

4.4.4 Switching of operating voltage ................................................................. 34

4.4.5 Clock frequency and instruction execution time....................................... 34

4.4.6 I/O memory of oscillation circuit.............................................................. 35

4.4.7 Programming notes ................................................................................... 36

S1C63666 TECHNICAL MANUAL EPSON i

CONTENTS

4.5 Input Ports (K00–K03 and K10–K13) .........................................................37

4.5.1 Configuration of input ports ..................................................................... 37

4.5.2 Interrupt function ...................................................................................... 37

4.5.3 Mask option ............................................................................................... 38

4.5.4 I/O memory of input ports......................................................................... 39

4.5.5 Programming notes ................................................................................... 41

4.6 Output Ports (R00–R03 and R10–R13) ....................................................... 42

4.6.1 Configuration of output ports ................................................................... 42

4.6.2 Mask option ............................................................................................... 42

4.6.3 High impedance control............................................................................ 43

4.6.4 Special output ............................................................................................ 43

4.6.5 I/O memory of output ports....................................................................... 45

4.6.6 Programming notes ................................................................................... 47

4.7 I/O Ports (P00–P03 and P10–P13) .............................................................48

4.7.1 Configuration of I/O ports ........................................................................ 48

4.7.2 Mask option ............................................................................................... 49

4.7.3 I/O control registers and input/output mode ............................................ 49

4.7.4 Pull-down during input mode ................................................................... 49

4.7.5 I/O memory of I/O ports............................................................................ 50

4.7.6 Programming note..................................................................................... 52

4.8 LCD Driver (COM0–COM7, SEG0–SEG63) .............................................53

4.8.1 Configuration of LCD driver .................................................................... 53

4.8.2 Power supply for LCD driving .................................................................. 53

4.8.3 Control of LCD display and drive waveform ........................................... 53

4.8.4 Display memory......................................................................................... 58

4.8.5 Segment option .......................................................................................... 58

4.8.6 LCD contrast adjustment .......................................................................... 60

4.8.7 I/O memory of LCD driver........................................................................ 61

4.8.8 Programming note..................................................................................... 62

4.9 Clock Timer ..................................................................................................63

4.9.1 Configuration of clock timer..................................................................... 63

4.9.2 Data reading and hold function................................................................ 63

4.9.3 Interrupt function ...................................................................................... 64

4.9.4 I/O memory of clock timer ........................................................................ 65

4.9.5 Programming notes ................................................................................... 66

4.10 Stopwatch Timer........................................................................................... 67

4.10.1 Configuration of stopwatch timer ........................................................... 67

4.10.2 Counter and prescaler ............................................................................. 67

4.10.3 Capture buffer and hold function............................................................ 68

4.10.4 Stopwatch timer RUN/STOP and reset ................................................... 69

4.10.5 Direct input function and key mask ........................................................ 69

4.10.6 Interrupt function .................................................................................... 72

4.10.7 I/O memory of stopwatch timer .............................................................. 74

4.10.8 Programming notes ................................................................................. 77

4.11 Programmable Timer ...................................................................................78

4.11.1 Configuration of programmable timer.................................................... 78

4.11.2 Basic count operation ............................................................................. 79

4.11.3 Setting the input clock ............................................................................. 80

4.11.4 Event counter mode (timer 0) ................................................................. 80

4.11.5 16-bit timer (timer 0 + timer 1) .............................................................. 81

4.11.6 Interrupt function .................................................................................... 82

4.11.7 Control of TOUT output .......................................................................... 82

4.11.8 Transfer rate setting for serial interface ................................................ 83

4.11.9 I/O memory of programmable timer ....................................................... 84

4.11.10 Programming notes ............................................................................... 89

ii EPSON S1C63666 TECHNICAL MANUAL

CONTENTS

4.12 Serial Interface (SIN, SOUT, SCLK, SRDY)................................................90

4.12.1 Configuration of serial interface ............................................................ 90

4.12.2 Mask option ............................................................................................. 91

4.12.3 Master mode and slave mode of serial interface.................................... 91

4.12.4 Data input/output and interrupt function ............................................... 92

4.12.5 I/O memory of serial interface................................................................ 95

4.12.6 Programming notes ................................................................................. 98

4.13 Sound Generator.......................................................................................... 99

4.13.1 Configuration of sound generator .......................................................... 99

4.13.2 Control of buzzer output.......................................................................... 99

4.13.3 Setting of buzzer frequency and sound level.......................................... 100

4.13.4 Digital envelope ..................................................................................... 101

4.13.5 One-shot output ...................................................................................... 102

4.13.6 I/O memory of sound generator............................................................. 103

4.13.7 Programming notes ................................................................................ 105

4.14 Integer Multiplier........................................................................................106

4.14.1 Configuration of integer multiplier........................................................ 106

4.14.2 Multiplication mode ............................................................................... 106

4.14.3 Division mode......................................................................................... 107

4.14.4 Execution cycle....................................................................................... 108

4.14.5 I/O memory of integer multiplier ........................................................... 109

4.14.6 Programming note.................................................................................. 110

4.15 R/f Converter...............................................................................................111

4.15.1 Configuration of R/f converter ............................................................... 111

4.15.2 Connection terminals and CR oscillation circuit.................................. 111

4.15.3 Operation of R/f conversion................................................................... 113

4.15.4 Interrupt function ................................................................................... 116

4.15.5 I/O memory of R/f converter .................................................................. 118

4.15.6 Programming notes ................................................................................ 121

4.16 Analog Comparator .................................................................................... 122

4.16.1 Configuration of analog comparator..................................................... 122

4.16.2 Analog comparator operation................................................................ 122

4.16.3 I/O memory of analog comparator ........................................................ 123

4.16.4 Programming notes ................................................................................ 123

4.17 SVD (Supply Voltage Detection) Circuit..................................................... 124

4.17.1 Configuration of SVD circuit ................................................................. 124

4.17.2 Mask option ............................................................................................ 124

4.17.3 SVD operation ........................................................................................ 125

4.17.4 I/O memory of SVD circuit..................................................................... 126

4.17.5 Programming notes ................................................................................ 126

4.18 Interrupt and HALT .................................................................................... 127

4.18.1 Interrupt factor....................................................................................... 129

4.18.2 Interrupt mask ........................................................................................ 130

4.18.3 Interrupt vector ...................................................................................... 130

4.18.4 I/O memory of interrupt ......................................................................... 131

4.18.5 Programming notes ................................................................................ 133

CHAPTER 5SUMMARY OF NOTES ______________________________________ 134

5.1 Notes for Low Current Consumption.......................................................... 134

5.2 Summary of Notes by Function................................................................... 135

5.3 Precautions on Mounting ...........................................................................139

CHAPTER 6BASIC EXTERNAL WIRING DIAGRAM ___________________________ 141

S1C63666 TECHNICAL MANUAL EPSON iii

CONTENTS

CHAPTER 7ELECTRICAL CHARACTERISTICS _______________________________ 142

7.1 Absolute Maximum Rating..........................................................................142

7.2 Recommended Operating Conditions......................................................... 142

7.3 DC Characteristics ..................................................................................... 142

7.4 Analog Circuit Characteristics and Power Current Consumption ............ 143

7.5 Oscillation Characteristics......................................................................... 144

7.6 Serial Interface AC Characteristics ...........................................................146

7.7 Timing Chart............................................................................................... 147

7.8 R/f Converter Characteristics.....................................................................147

CHAPTER 8PACKAGE _______________________________________________ 148

8.1 Plastic Package...........................................................................................148

8.2 Ceramic Package for Test Samples............................................................. 149

CHAPTER 9PAD LAYOUT ____________________________________________ 150

9.1 Diagram of Pad Layout............................................................................... 150

9.2 Pad Coordinates..........................................................................................151

APPENDIX S5U1C63000P1 MANUAL (PERIPHERAL CIRCUIT BOARD FOR S1C63666) __ 152

A.1 Names and Functions of Each Part ............................................................ 152

A.2 Connecting to the Target System ................................................................155

A.3 Usage Precautions ...................................................................................... 157

A.3.1 Operational precautions.......................................................................... 157

A.3.2 Differences with the actual IC................................................................. 157

iv EPSON S1C63666 TECHNICAL MANUAL

CHAPTER 1: OUTLINE

CHAPTER 1OUTLINE

The S1C63666 is a microcomputer which has a high-performance 4-bit CPU S1C63000 as the core CPU,

ROM (16,384 words × 13 bits), RAM (5,120 words × 4 bits), multiply-divide circuit, serial interface, watchdog
timer, programmable timer, time base counters (2 systems), an LCD driver that can drive a maximum 64
segments × 8 commons, sound generator and R/f converter built-in. The S1C63666 features low current
consumption, this makes it suitable for battery driven portable equipment with R/f converter.

1.1 Features

OSC1 oscillation circuit ...................... 32.768 kHz (Typ.) crystal oscillation circuit

OSC3 oscillation circuit ...................... 4 MHz (Max.) ceramic or 1.1 MHz (Typ.) CR oscillation circuit (∗1)

Instruction set ..................................... Basic instruction: 46 types (411 instructions with all)

Addressing mode: 8 types

Instruction execution time................... During operation at 32.768 kHz: 61 µsec 122 µsec 183 µsec

During operation at 4 MHz: 0.5 µsec 1 µsec 1.5 µsec

ROM capacity ..................................... Code ROM: 16,384 words × 13 bits

Data ROM: 4,096 words × 4 bits

RAM capacity...................................... Data memory: 5,120 words × 4 bits

Display memory: 160 words × 4 bits

Input port............................................. 8 bits (Pull-down resistors may be supplemented ∗1)

Output port.......................................... 8 bits (It is possible to switch the 2 bits to special output ∗2)

I/O port ................................................ 8 bits (It is possible to switch the 4 bits to serial I/F input/output ∗2)

Serial interface.................................... 1 port (8-bit clock synchronous system)

LCD driver........................................... 64 segments × 4, 5 or 8 commons (∗2)

Time base counter.............................. Clock timer

Stopwatch timer (1/1000 sec, with direct key input function)

Programmable timer ........................... 8 bits × 3 ch. or 16 bits × 1 ch. + 8 bits × 1 ch. (∗2)

Watchdog timer................................... Built-in

Sound generator................................. With envelope and 1-shot output functions

R/f converter ....................................... 2 ch., CR oscillation type, 20-bit counter

Multiply-divide circuit .......................... 8-bit accumulator × 1 ch.

Multiplication: 8 bits × 8 bits → 16-bit product
Division: 16 bits ÷ 8 bits → 8-bit quotient and 8-bit remainder

Analog comparator ............................. 1 ch.

Supply voltage detection (SVD) circuit.. Criteria voltage is selectable from 8 types (1.85 to 2.90 V ∗2)

(External voltage detection is possible ∗1)

External interrupt ................................ Input port interrupt: 2 systems

Internal interrupt ................................. Clock timer interrupt: 4 systems

Stopwatch timer interrupt: 4 systems
Programmable timer interrupt: 3 systems
Serial interface interrupt: 1 system
R/f converter interrupt: 2 systems

Power supply voltage.......................... 2.4 to 3.6 V: Max. 4 MHz operation in normal mode

2.4 to 3.6 V: 32 kHz operation in halver mode

1.5 to 3.6 V: 32 kHz operation in normal mode

Operating temperature range ............. -20 to 70°C

Current consumption (Typ.) ................ Low-speed operation (OSC1 = 32 kHz crystal oscillation):

During HALT 3.0 V (LCD ON, halver mode) 0.65 µA
During operation 3.0 V (LCD ON, halver mode) 2.5 µA

High-speed operation (OSC3):

During operation 3.0 V (LCD ON) 1 mA

Package .............................................. QFP20-144pin (plastic) or chip

∗1: Can be selected with mask option ∗2: Can be selected with software

S1C63666 TECHNICAL MANUAL EPSON 1

CHAPTER 1: OUTLINE

1.2 Block Diagram

OSC1
OSC2
OSC3
OSC4

COM0–7

SEG0–63

VDD

VDDA
VC1–3
VD1–2

VOSC

CA–CD

VSS

VSSA

SVD

ROM

16,384 words × 13 bits

OSC

RAM

5,120 words × 4 bits

Data ROM

4,096 words × 4 bits

LCD Driver

64 SEG × 8 COM

Power

Controller

SVD

System Reset

Core CPU S1C63000

Control

Interrupt

Generator

Clock
Timer

Stopwatch

Timer

Programmable

Timer/Counter

Input Port

Serial Interface

I/O Port

RESET

K00–K03
K10–K13

TEST

P00–P03
P10–P13

R00–R03
R10–R13

SEN0, SEN1
REF
RFIN
RFOUT

BZ
BZ

CMPP0

CMPM0

Sound

Generator

Analog

Comparator

Output Port

R/F Converter

Fig. 1.2.1 Block diagram

2 EPSON S1C63666 TECHNICAL MANUAL

1.3 Pin Layout Diagram

QFP20-144pin

CHAPTER 1: OUTLINE

73108

No.

10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36

1
2
3
4
5
6
7
8
9

109

INDEX

144

Pin name

N.C.
COM0
COM1
COM2
COM3
CA
CB
VC1
VC2
VC3
CMPP0
CMPM0
SVD
VSSA
RFOUT
RFIN
REF
SEN0
SEN1
VDDA
CC
CD
VD2
VDD
VOSC
OSC1
OSC2
VD1
OSC3
OSC4
VSS
TEST
RESET
N.C.
N.C.
N.C.

No.

37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72

Pin name

N.C.
SEG32
SEG33
SEG34
SEG35
SEG36
SEG37
SEG38
SEG39
SEG40
SEG41
SEG42
SEG43
SEG44
SEG45
SEG46
SEG47
SEG48
SEG49
SEG50
SEG51
SEG52
SEG53
SEG54
SEG55
SEG56
SEG57
SEG58
SEG59
SEG60
SEG61
SEG62
SEG63
N.C.
N.C.
N.C.

No.

73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98

99
100
101
102
103
104
105
106
107
108

Pin name

N.C.
N.C.
N.C.
COM4
COM5
COM6
COM7
VDD
K00
K01
K02
K03
K10
K11
K12
K13
P00
P01
P02
P03
P10
P11
P12
P13
R00
R01
R02
R03
R10
R11
R12
R13
BZ
BZ
VSS
N.C.

Fig. 1.3.1 Pin layout diagram (QFP20-144pin)

72

37

361

No.

Pin name

109

N.C.

110

SEG0

111

SEG1

112

SEG2

113

SEG3

114

SEG4

115

SEG5

116

SEG6

117

SEG7

118

SEG8

119

SEG9

120

SEG10

121

SEG11

122

SEG12

123

SEG13

124

SEG14

125

SEG15

126

SEG16

127

SEG17

128

SEG18

129

SEG19

130

SEG20

131

SEG21

132

SEG22

133

SEG23

134

SEG24

135

SEG25

136

SEG26

137

SEG27

138

SEG28

139

SEG29

140

SEG30

141

SEG31

142

N.C.

143

N.C.

144

N.C.

N.C. : No Connection

S1C63666 TECHNICAL MANUAL EPSON 3

CHAPTER 1: OUTLINE

1.4 Pin Description

Pin name

V

DD

V

SS

V

DDA

V

SSA

V

D1

V

D2

V

OSC

VC1–V

C3

CA, CB
CC, CD
OSC1
OSC2
OSC3
OSC4
K00–K03
K10–K13
P00
P01
P02
P03
P10–P13
R00
R01
R02
R03
R10–R13
COM0–COM7
SEG0–SEG63
SEN0
SEN1
REF
RFIN
RFOUT
CMPP0
CMPM0
BZ
BZ
SVD
RESET
TEST

Pin No.

24
31
20
14
28
23
25

8–10

6, 7

21, 22

26
27
29

30
81–84
85–88

89

90

91

92
93–96

97

98

99

100

101–104

2–5, 76–79

110–141, 38–69

18

19

17

16

15

11

12

105
106

13

33

32

Table 1.4.1 Pin description

I/O

Power (+) supply pin

–

Power (–) supply pin

–

Analog system power (+) supply pin (=V

–
–

Analog system power (–) supply pin (=V
Internal logic system regulated voltage output pin

–

1/2V

–
–
–
–
–

I

O

I

O

I

I
I/O
I/O
I/O
I/O
I/O

O
O
O
O
O
O
O
O
O
O

I

O

I

I

O
O

I

I

I

DD

voltage halver output pin
Oscillation system regulated voltage output pin
LCD system power supply pin
LCD system voltage booster capacitor connecting pin
Voltage halver capacitor connecting pin
Crystal oscillation input pin
Crystal oscillation output pin
Ceramic or CR oscillation input pin (selected by mask option)
Ceramic or CR oscillation output pin (selected by mask option)
Input port pins
Input port pins
I/O port or serial I/F data input pin (selected by software)
I/O port or serial I/F data output pin (selected by software)
I/O port or serial I/F clock I/O pin (selected by software)
I/O port or serial I/F ready signal output pin (selected by software)
I/O port pins
Output port pin
Output port pin
Output port or TOUT output pin (selected by software)
Output port or FOUT output pin (selected by software)
Output port pins
LCD common output pin (1/4, 1/5 or 1/8 duty is selectable by software)
LCD segment output pin
R/f converter sensor 0 CR oscillation output pin
R/f converter sensor 1 CR oscillation output pin
R/f converter reference resistor CR oscillation output pin
R/f converter CR oscillation input pin
R/f converter oscillation frequency output pin
Analog comparator non-inverted input pin
Analog comparator inverted input pin
Sound output pin
Sound inverted output pin
SVD external voltage input pin
Initial reset input pin
Testing input pin

Function

DD

)

SS

)

4 EPSON S1C63666 TECHNICAL MANUAL

CHAPTER 1: OUTLINE

1.5 Mask Option

Mask options shown below are provided for the S1C63666. Several hardware specifications are prepared
in each mask option, and one of them can be selected according to the application. The function option
generator winfog and segment option generator winsog, that have been prepared as the development
software tool of S1C63666, are used for this selection. Mask pattern of the IC is finally generated based on
the data created by winfog and winsog. Refer to the "S5U1C63000A Manual" for winfog and winsog.

<Outline of the mask option>

(1) OSC1 oscillation circuit

The OSC1 oscillation circuit is fixed at crystal oscillation. Refer to Section 4.4.2, "OSC1 oscillation
circuit", for details.

(2) OSC3 oscillation circuit

The OSC3 oscillator type can be selected from ceramic oscillation, CR oscillation (external R) and CR
oscillation (built-in R). Refer to Section 4.4.3, "OSC3 oscillation circuit", for details.

(3) External voltage detection of the SVD circuit

External voltage (SVD terminal voltage) detection can be selected in addition to supply voltage (V
terminal–VSS terminal) detection. Refer to Section 4.17.2, "Mask option", for details.

(4) Input port pull-down resistor

The mask option is used to select whether the pull-down resistor is supplemented to the input ports
or not. It is possible to select for each bit of the input ports.
Refer to Section 4.5.3, "Mask option", for details.

DD

(5) RESET terminal pull-down resistor

This option is used to select whether the pull-down resistor is supplemented to the RESET terminal or
not. Refer to Section 2.2.1, "Reset terminal (RESET)", for details.

(6) I/O port pull-down resistor

The mask option is used to select whether the pull-down resistor working in the input mode is
supplemented to the I/O ports or not. It is possible to select for each bit of the input ports.
Refer to Section 4.7.2, "Mask option", for details.

(7) Output specification of the output port

Either complementary output or P-channel open drain output can be selected as the output specifica­tion for the output ports R00–R03 and R10–R13. The selection is done in 1-bit units.
Refer to Section 4.6.2, "Mask option", for details.

(8) Output specification of the I/O port

For the output specification when the I/O ports P00–P03 and P10–P13 are in the output mode, either
complementary output or P-channel open drain output can be selected in 1-bit units.
Refer to Section 4.7.2, "Mask option", for details.

(9) External reset by simultaneous high input to the input port (K00–K03)

This function resets the IC when several keys are pressed simultaneously. The mask option is used to
select whether this function is used or not. Further when the function is used, a combination of the
input ports (K00–K03), which are connected to the keys to be pressed simultaneously, can be selected.
Refer to Section 2.2.2, "Simultaneous high input to terminals K00–K03", for details.

(10) Time authorize circuit for the simultaneous high input reset function

When the external reset function (shown in 9 above) is used, the time authorize circuit is enabled. The
reset function works only when the input time of simultaneous low is more than the rule time if the
time authorize circuit is being used. When the external reset function is not used, the time authorize
circuit cannot be used. Refer to Section 2.2.2, "Simultaneous high input to terminals K00–K03", for
details.

S1C63666 TECHNICAL MANUAL EPSON 5

CHAPTER 1: OUTLINE

(11) Synchronous clock polarity in the serial interface

The polarity of the synchronous clock SCLK and the SRDY signal in slave mode of the serial interface
is selected by mask option. Either positive polarity or negative polarity can be selected.
Refer to Section 4.12.2, "Mask option", for details.

(12) LCD drive power

Either the internal power supply or an external power supply can be selected for driving LCD.
Refer to Section 4.8.2, "Power supply for LCD driving", for details.

(13) LCD segment specification

The display memory can be allocated to the optional SEG terminal. It is also possible to set the
optional SEG terminal for DC output.
Refer to Section 4.8.5, "Segment option", for details.

<Option list>

The following is the option list for the S1C63666.
Multiple selections are available in each option item as indicated in the option list. Select the specifica­tions that meet the target system and check the appropriate box. Be sure to record the specifications for
unused functions too.

1. OSC1 SYSTEM CLOCK

■■ 1. Crystal

2. OSC3 SYSTEM CLOCK

■■ 1. CR (built-in R)

■■ 2. CR (external R)

■■ 3. Ceramic

3. SVD EXTERNAL VOLTAGE DETECTION

■■ 1. Not Use

■■ 2. Use

4. INPUT PORT PULL DOWN RESISTOR

• K00 ■■ 1. With Resistor ■■ 2. Gate Direct

• K01 ■■ 1. With Resistor ■■ 2. Gate Direct

• K02 ■■ 1. With Resistor ■■ 2. Gate Direct

• K03 ■■ 1. With Resistor ■■ 2. Gate Direct

• K10 ■■ 1. With Resistor ■■ 2. Gate Direct

• K11 ■■ 1. With Resistor ■■ 2. Gate Direct

• K12 ■■ 1. With Resistor ■■ 2. Gate Direct

• K13 ■■ 1. With Resistor ■■ 2. Gate Direct

5. RESET PORT PULL DOWN RESISTOR

• RESET ■■ 1. With Resistor ■■ 2. Gate Direct

6. I/O PORT PULL DOWN RESISTOR

• P00 ■■ 1. With Resistor ■■ 2. Gate Direct

• P01 ■■ 1. With Resistor ■■ 2. Gate Direct

• P02 ■■ 1. With Resistor ■■ 2. Gate Direct

• P03 ■■ 1. With Resistor ■■ 2. Gate Direct

• P10 ■■ 1. With Resistor ■■ 2. Gate Direct

• P11 ■■ 1. With Resistor ■■ 2. Gate Direct

• P12 ■■ 1. With Resistor ■■ 2. Gate Direct

• P13 ■■ 1. With Resistor ■■ 2. Gate Direct

6 EPSON S1C63666 TECHNICAL MANUAL

7. OUTPUT PORT OUTPUT SPECIFICATION

• R00 ■■ 1. Complementary ■■ 2. Pch-OpenDrain

• R01 ■■ 1. Complementary ■■ 2. Pch-OpenDrain

• R02 ■■ 1. Complementary ■■ 2. Pch-OpenDrain

• R03 ■■ 1. Complementary ■■ 2. Pch-OpenDrain

• R10 ■■ 1. Complementary ■■ 2. Pch-OpenDrain

• R11 ■■ 1. Complementary ■■ 2. Pch-OpenDrain

• R12 ■■ 1. Complementary ■■ 2. Pch-OpenDrain

• R13 ■■ 1. Complementary ■■ 2. Pch-OpenDrain

8. I/O PORT OUTPUT SPECIFICATION

• P00 ■■ 1. Complementary ■■ 2. Pch-OpenDrain

• P01 ■■ 1. Complementary ■■ 2. Pch-OpenDrain

• P02 ■■ 1. Complementary ■■ 2. Pch-OpenDrain

• P03 ■■ 1. Complementary ■■ 2. Pch-OpenDrain

• P10 ■■ 1. Complementary ■■ 2. Pch-OpenDrain

• P11 ■■ 1. Complementary ■■ 2. Pch-OpenDrain

• P12 ■■ 1. Complementary ■■ 2. Pch-OpenDrain

• P13 ■■ 1. Complementary ■■ 2. Pch-OpenDrain

9. MULTIPLE KEY ENTRY RESET COMBINATION

■■ 1. Not Use

■■ 2. Use (K00, K01)

■■ 3. Use (K00, K01, K02)

■■ 4. Use (K00, K01, K02, K03)

10. MULTIPLE KEY ENTRY RESET TIME AUTHORIZE

■■ 1. Not Use

■■ 2. Use

CHAPTER 1: OUTLINE

11. SIO SYNC CLOCK & SRDY

■■ 1. Negative

■■ 2. Positive

12. LCD DRIVING POWER

■■ 1. Internal Power (3.0 V panel)

■■ 2. External Power 1/3 bias, V

■■ 3. External Power 1/3 bias, V

■■ 4. External Power 1/2 bias, V

DD=VC2 (4.5 V panel)
DD=VC3 (3.0 V panel)
DD=VC3, VC1=VC2 (3.0 V panel)

S1C63666 TECHNICAL MANUAL EPSON 7

CHAPTER 1: OUTLINE

■ C■

■

■ C■

■

■ C■

■

■ C■

■

■ C■

■

■ C■

■

■ C■

■

■ C■

■

■ C■

■

■ C■

■

■ C■

■

■ C■

■

■ C■

■

■ C■

■

■ C■

■

■ C■

■

■ C■

■

■ C■

■

■ C■

■

■ C■

■

■ C■

■

■ C■

■

■ C■

■

■ C■

■

■ C■

■

■ C■

■

■ C■

■

■ C■

■

■ C■

■

■ C■

■

■ C■

■

■ C■

13. SEGMENT OPTION

Pin

name

SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8

SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
SEG32
SEG33
SEG34
SEG35
SEG36
SEG37
SEG38
SEG39
SEG40
SEG41
SEG42
SEG43
SEG44
SEG45
SEG46
SEG47
SEG48
SEG49
SEG50
SEG51
SEG52
SEG53
SEG54
SEG55
SEG56
SEG57
SEG58
SEG59
SEG60
SEG61
SEG62
SEG63

8 EPSON S1C63666 TECHNICAL MANUAL

COM0

H L D

<address> H:

L:
D:

COM1

H L D

RAM data high-order address (0–9)
RAM data low-order address (0–F)
Data bit (0–3)

COM2

H L D

Address (F0xx)

COM3

H L D

COM4

H L D

<Output specification> S:

COM5

H L D

C:
N:

COM6

H L D

Segment output
Complementary output
Nch open drain output

COM7 Output specification

H L D

SEG output■ S
DC output
SEG output
DC output
SEG output
DC output
SEG output
DC output
SEG output
DC output
SEG output
DC output
SEG output
DC output
SEG output
DC output
SEG output
DC output
SEG output
DC output
SEG output
DC output
SEG output
DC output
SEG output
DC output
SEG output
DC output
SEG output
DC output
SEG output
DC output
SEG output
DC output
SEG output
DC output
SEG output
DC output
SEG output
DC output
SEG output
DC output
SEG output
DC output
SEG output
DC output
SEG output
DC output
SEG output
DC output
SEG output
DC output
SEG output
DC output
SEG output
DC output
SEG output
DC output
SEG output
DC output
SEG output
DC output
SEG output
DC output

N

S

N

S

N

S

N

S

N

S

N

S

N

S

N

S

N

S

N

S

N

S

N

S

N

S

N

S

N

S

N

S

N

S

N

S

N

S

N

S

N

S

N

S

N

S

N

S

N

S

N

S

N

S

N

S

N

S

N

S

N

S

N

CHAPTER 2: POWER SUPPLY AND INITIAL RESET

CHAPTER 2POWER SUPPL Y AND INITIAL RESET

2.1 Power Supply

The S1C63666 operating power voltage is as follows:

Table 2.1.1 Operating voltage

Operating mode

Normal mode
Halver mode
Normal mode

The S1C63666 operates by applying a single power supply within the above range between VDD and VSS.
The S1C63666 itself generates the voltage necessary for all the internal circuits by the built-in power
supply circuits shown in Table 2.1.2.

Circuit

OSC1 circuit

Internal circuits
(low-speed operation)
OSC3 and internal circuits
(high-speed operation)
LCD driver

Maximum operating frequency

4 MHz (OSC3)
32 kHz (OSC1 only)
32 kHz (OSC1 only)

Table 2.1.2 Power supply circuits

Power supply

Voltage regulator for
OSC1 oscillation circuit
Low-speed operation
voltage regulator
High-speed operation
voltage regulator
LCD system voltage
circuit

Operating voltage

2.4 V to 3.6 V

2.4 V to 3.6 V

1.5 V to 3.6 V

Output voltage

V

OSC

V

D1L

V

D3

VC1–V

C3

Note: • Do not drive external loads with the output voltage from the internal power supply circuits.

• See Chapter 7, "Electrical Characteristics", for voltage values and drive capability.

CC

CD

DDA

External

power

supply

V

V

DD

V

D2

V

C1

V

C2

V

C3

CA

CB

+

OSC

V

V

D1

V

SS

V

SSA

VDC3

VDC2

Voltage

halver

VD2=1/2 V

LCD system voltage circuit

DD

LPWR

LCD system

voltage regulator

Voltage booster

Voltage regulator for

OSC1 oscillation circuit

Low-speed operation

voltage regulator

VDC0

High-speed operation

voltage regulator

VDC1

V

C1

V

C1

V

C2

V

C3

V

OSC

V

D1L

V

V

D3

R/f

converter

LCD driver

OSC1

oscillation circuit

D1

CPU,

internal circuits

OSC3

oscillation circuit

Fig. 2.1.1 Configuration of power supply

S1C63666 TECHNICAL MANUAL EPSON 9

CHAPTER 2: POWER SUPPLY AND INITIAL RESET

2.1.1 Voltage regulator for OSC1 oscillation circuit

This voltage regulator generates the VOSC voltage (0.98 V Typ.) for driving the OSC1 oscillation circuit.
This regulator always operates to drive the OSC1 oscillation circuit.

2.1.2 Low-speed operation voltage regulator

The low-speed operation voltage regulator generates the VD1L voltage (1.25 V Typ.) for driving the
internal logic circuits in low-speed mode. This regulator always operates and the output voltage is used
as the operating voltage of the CPU and internal logic circuits when they are driven with the OSC1 clock
(32 kHz).

2.1.3 High-speed operation voltage regulator

The high-speed operation voltage regulator generates the VD3 voltage (2.0 V Typ.) for driving the OSC3
oscillation circuit and the internal logic circuits in high-speed mode. Since this regulator stops normally, it
should be turned it on using software before switching to the high-speed mode. Refer to Section 4.4,
"Oscillation Circuit", for the control method.

2.1.4 Internal operating voltage VD1

The internal operating voltage V
The S1C63666 is designed with twin clock specifications; it has two types of oscillation circuits OSC1 and
OSC3 built-in. Use OSC1 clock for normal operation, and switch to OSC3 using software when high­speed operation is necessary. When switching the clock, the operating voltage V
using software to stabilize the operation of the oscillation circuit and internal circuits.
In low-speed operation, V
high-speed operation, V

D3 generated by the high-speed operation voltage regulator is used as VD1.

Refer to Section 4.4, "Oscillation Circuit", for the control method.

D1 is the voltage for driving the CPU and internal logic circuits.

D1 must be switched

D1L generated by the low-speed operation voltage regulator is used as VD1. In

2.1.5 LCD system voltage circuit

The LCD system voltage circuit generates the LCD drive voltage. This circuit allows the software to turn
on and off. Turn this circuit on before starting display on the LCD. The LCD system voltage circuit
generates V
3V

C1) by boosting VC1. The VC1 voltage value can be adjusted using software in 16 steps (0.95 to 1.40 V).

The LCD system voltage regulator can be disabled by mask option. In this case, external elements can be
minimized because the external capacitors for the LCD system voltage regulator are not necessary.
However when the LCD system voltage regulator is not used, the display quality of the LCD panel, when
the supply voltage fluctuates (drops), is inferior to when the LCD system voltage regulator is used.
Figure 2.1.5.1 shows the external element configuration when the LCD system voltage regulator is not
used.

C1 with the voltage regulator built-in, and generates two other voltages (VC2 = 2VC1, VC3 =

10 EPSON S1C63666 TECHNICAL MANUAL

4.5 V LCD panel
1/8, 1/5 or 1/4 duty, 1/3 bias

VDD

VC1
VC2
VC3

CA
CB

VSS

C2

C4

C1

CHAPTER 2: POWER SUPPLY AND INITIAL RESET

3.0 V

3 V LCD panel
1/8, 1/5 or 1/4 duty, 1/3 bias

VDD

VC1
VC2
VC3

CA
CB

VSS

C2
C3

C1

3.0 V

3 V LCD panel
1/8, 1/5 or 1/4 duty, 1/2 bias

VDD

VC1
VC2
VC3

CA
CB

VSS

C2

C1

3.0 V

Fig. 2.1.5.1 External elements when LCD system voltage regulator is not used

Refer to Section 4.8, "LCD Driver", for control of the LCD drive voltage.

2.1.6 Halver mode and saving power

When the supply voltage VDD is 2.4 V or more, the low-speed operation voltage regulator and LCD
system voltage circuit can be driven with the V

DD voltage halved. This status is the halver mode for

reducing current consumption during HALT or low-speed operation. At initial reset, the low-speed
operation voltage regulator and LCD system voltage circuit are set in the normal mode using V

DD. When

necessary switch to the halver mode using software. The halver mode supports only low-speed operation
using the OSC1 clock and cannot be set during high-speed operation using the OSC3 clock. The low­speed operation voltage regulator and the LCD system voltage circuit can be set to the halver mode
independently. Refer to Section 4.2, "Power Control", for control of the halver mode.

2.1.7 Analog system power supply

The VDDA and VSSA power supply terminals are provided only for the R/f converter in order to avoid
decreasing the conversion accuracy due to noise. However, the same voltage level as the V
be supplied to the V
V

DDA = VDD, VSSA = VSS

DDA–VSSA.

DD–VSS must

S1C63666 TECHNICAL MANUAL EPSON 11

CHAPTER 2: POWER SUPPLY AND INITIAL RESET

2.2 Initial Reset

To initialize the S1C63666 circuits, initial reset must be executed. There are two ways of doing this.

(1) External initial reset by the RESET terminal
(2) External initial reset by simultaneous high input to terminals K00–K03 (mask option setting)

The circuits are initialized by either (1) or (2). When the power is turned on, be sure to initialize using the
reset function. It is not guaranteed that the circuits are initialized by only turning the power on.

Figure 2.2.1 shows the configuration of the initial reset circuit.

OSC1
OSC2

Mask option

OSC1

oscillation

circuit

Divider

1 Hz
2 Hz

K00
K01
K02
K03

RESET

authorize

V

SS

Time

circuit

Mask option

Noise

reject

circuit

RQ
S

Internal
initial
reset

Fig. 2.2.1 Configuration of initial reset circuit

2.2.1 Reset terminal (RESET)

Initial reset can be executed externally by setting the reset terminal to a high level (VDD). After that the
initial reset is released by setting the reset terminal to a low level (V
The reset input signal is maintained by the RS latch and becomes the internal initial reset signal. The RS
latch is designed to be released by a 2 Hz signal (high) that is divided by the OSC1 clock. Therefore in
normal operation, a maximum of 250 msec (when f

OSC1 = 32.768 kHz) is needed until the internal initial

reset is released after the reset terminal goes to low level. Be sure to maintain a reset input of 0.1 msec or
more. However, when turning the power on, the reset terminal should be set at a high level as in the
timing shown in Figure 2.2.1.1.
Note that a reset pulse shorter than 100 nsec is rejected as noise.

SS) and the CPU starts operation.

1.8 V

V

DD

RESET

Power on

0.9•VDD or more (high level)

0.5•V

DD

2.0 msec or more

Fig. 2.2.1.1 Initial reset at power on

The reset terminal should be set to 0.9•V

DD or more (high level) until the supply voltage becomes 1.8 V

or more.
After that, a level of 0.5•V

DD or more should be maintained more than 2.0 msec.

The reset terminal incorporates a pull-down resistor and a mask option is provided to select whether the
resistor is used or not.

12 EPSON S1C63666 TECHNICAL MANUAL

CHAPTER 2: POWER SUPPLY AND INITIAL RESET

2.2.2 Simultaneous high input to terminals K00–K03

Another way of executing initial reset externally is to input a high signal simultaneously to the input
ports (K00–K03) selected with the mask option.
Since this initial reset passes through the noise reject circuit, maintain the specified input port terminals at
high level for at least 1.5 msec (when the oscillation frequency f
operation. The noise reject circuit does not operate immediately after turning the power on until the
oscillation circuit starts oscillating. Therefore, maintain the specified input port terminals at high level for
at least 1.5 msec (when the oscillation frequency f

OSC1 is 32.768 kHz) after oscillation starts.

Table 2.2.2.1 shows the combinations of input ports (K00–K03) that can be selected with the mask option.

Table 2.2.2.1 Combinations of input ports

Not use

1

K00∗K01

2

K00∗K01∗K02

3

K00∗K01∗K02∗K03

4

When, for instance, mask option 4 (K00∗K01∗K02∗K03) is
selected, initial reset is executed when the signals input to the
four ports K00–K03 are all high at the same time. When 2 or 3 is
selected, the initial reset is done when a key entry including a
combination of selected input ports is made.

Further, the time authorize circuit mask option is selected when this reset function is selected. The time
authorize circuit checks the input time of the simultaneous high input and performs initial reset if that
time is the defined time (1 to 2 sec) or more.
If using this function, make sure that the specified ports do not go high at the same time during ordinary
operation.

OSC1 is 32.768 kHz) during normal

2.2.3 Internal register at initial resetting

Initial reset initializes the CPU as shown in Table 2.2.3.1.
The registers and flags which are not initialized by initial reset should be initialized in the program if
necessary.
In particular, the stack pointers SP1 and SP2 must be set as a pair because all the interrupts including
NMI are masked after initial reset until both the SP1 and SP2 stack pointers are set with software.
When data is written to the EXT register, the E flag is set and the following instruction will be executed in
the extended addressing mode. If an instruction which does not permit extended operation is used as the
following instruction, the operation is not guaranteed. Therefore, do not write data to the EXT register for
initialization only.
Refer to the "S1C63000 Core CPU Manual" for extended addressing and usable instructions.

Table 2.2.3.1 Initial values

Name

Data register A
Data register B
Extension register EXT
Index register X
Index register Y
Program counter
Stack pointer SP1
Stack pointer SP2
Zero flag
Carry flag
Interrupt flag
Extension flag
Queue register

CPU core

Symbol

A
B

EXT

X
Y

PC
SP1
SP2

Z

C

I
E

Q

Number of bits

4
4

8
16
16
16

8

8

1

1

1

1
16

Setting value

Undefined
Undefined
Undefined
Undefined
Undefined

0110H
Undefined
Undefined
Undefined
Undefined

0
0

Undefined

Name

RAM
Display memory
Other peripheral circuits

Peripheral circuits

Number of bits

4
4
–

Setting value

∗ See Section 4.1, "Memory Map".

Undefined
Undefined

∗

S1C63666 TECHNICAL MANUAL EPSON 13

CHAPTER 2: POWER SUPPLY AND INITIAL RESET

2.2.4 Terminal settings at initial resetting

The output port (R) terminals and I/O port (P) terminals are shared with special output terminals and
input/output terminals of the serial interface. These functions are selected by the software. At initial
reset, these terminals are set to the general purpose output port terminals and I/O port terminals. Set
them according to the system in the initial routine. In addition, take care of the initial status of output
terminals when designing a system.
Table 2.2.4.1 shows the list of the shared terminal settings.

Table 2.2.4.1 List of shared terminal settings

Terminal

name

R00
R01
R02
R03

R10–R13

P00–P03

P10
P11
P12
P13

For setting procedure of the functions, see explanations for each of the peripheral circuits.

Terminal status

at initial reset

R00 (LOW output)
R01 (LOW output)
R02 (LOW output)
R03 (LOW output)
R10–R13 (LOW output)
P00–P03 (Input & pulled down∗)
P10 (Input & pulled down∗)
P11 (Input & pulled down∗)
P12 (Input & pulled down∗)
P13 (Input & pulled down∗)

∗ When "With Pull-Down" is selected by mask option
(high impedance when "Gate Direct" is selected)

Special output

TOUT FOUT

TOUT

FOUT

Serial I/F

Master Slave

SIN(I) SIN(I)
SOUT(O) SOUT(O)
SCLK(O) SCLK(I)

SRDY(O)

2.3 Test Terminal (TEST)

This is the terminal used for the factory inspection of the IC. During normal operation, connect the TEST
terminal to V

SS.

14 EPSON S1C63666 TECHNICAL MANUAL

CHAPTER 3: CPU, ROM, RAM

CHAPTER 3 CPU, R OM, RAM

3.1 CPU

The S1C63666 has a 4-bit core CPU S1C63000 built-in as its CPU part.
Refer to the "S1C63000 Core CPU Manual" for the S1C63000.

Note:

The SLP instruction cannot be used because the SLEEP operation is not assumed in the S1C63666.

3.2 Code ROM

The built-in code ROM is a mask ROM for loading programs, and has a capacity of 16,384 steps × 13 bits.
The core CPU can linearly access the program space up to step FFFFH from step 0000H, however, the
program area of the S1C63666 is step 0000H to step 3FFFH. The program start address after initial reset is
assigned to step 0110H. The non-maskable interrupt (NMI) vector and hardware interrupt vectors are
allocated to step 0100H and steps 0102H–010EH, respectively.

0000H

3FFFH

4000H

ROM

S1C63666
program area

S1C63000 core CPU
program space

0000H

0100H
0102H

010EH

0110H

Program area

NMI vector

Hardware

interrupt vectors

Program start address

FFFFH

Unused area

13 bits

Program area

Fig. 3.2.1 Configuration of code ROM

3.3 RAM

The RAM is a data memory for storing various kinds of data, and has a capacity of 5,120 words × 4 bits.
The RAM area is assigned to addresses 0000H to 01FFH on the data memory map. Addresses 0100H to
01FFH are 4-bit/16-bit data accessible areas and in other areas it is only possible to access 4-bit data.
When programming, keep the following points in mind.

(1) Part of the RAM area is used as a stack area for subroutine call and register evacuation, so pay

attention not to overlap the data area and stack area.

(2) The S1C63000 core CPU handles the stack using the stack pointer for 4-bit data (SP2) and the stack

pointer for 16-bit data (SP1).
16-bit data are accessed in stack handling by SP1, therefore, this stack area should be allocated to the
area where 4-bit/16-bit access is possible (0100H to 01FFH). The stack pointers SP1 and SP2 change
cyclically within their respective range: the range of SP1 is 0000H to 03FFH and the range of SP2 is
0000H to 00FFH. Therefore, pay attention to the SP1 value because it may be set to 0200H or more
exceeding the 4-bit/16-bit accessible range in the S1C63666 or it may be set to 00FFH or less. Memory
accesses except for stack operations by SP1 are 4-bit data access.
After initial reset, all the interrupts including NMI are masked until both the stack pointers SP1 and
SP2 are set by software. Further, if either SP1 or SP2 is re-set when both are set already, the interrupts
including NMI are masked again until the other is re-set. Therefore, the settings of SP1 and SP2 must
be done as a pair.

S1C63666 TECHNICAL MANUAL EPSON 15

CHAPTER 3: CPU, ROM, RAM

(3) Subroutine calls use 4 words (for PC evacuation) in the stack area for 16-bit data (SP1). Interrupts use

4 words (for PC evacuation) in the stack area for 16-bit data (SP1) and 1 word (for F register evacua­tion) in the stack area for 4-bit data.

0000H

00FFH
0100H

01FFH
0200H

13FFH

4 bits

4-bit access area
(SP2 stack area)

4/16-bit access area
(SP1 stack area)

4-bit access area
(Data area)

Fig. 3.3.1 Configuration of data RAM

3.4 Data ROM

The data ROM is a mask ROM for loading various static data such as a character generator, and has a
capacity of 4,096 words × 4 bits. The data ROM is assigned to addresses 8000H to 8FFFH on the data
memory map, and the data can be read using the same data memory access instructions as the RAM.

16 EPSON S1C63666 TECHNICAL MANUAL

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map)

CHAPTER 4

The peripheral circuits of S1C63666 (timer, I/O, etc.) are interfaced with the CPU in the memory
mapped I/O method. Thus, all the peripheral circuits can be controlled by accessing the I/O memory on
the memory map using the memory operation instructions. The following sections explain the detailed
operation of each peripheral circuit.

P

ERIPHERAL

C

IRCUITS AND

O

PERA TION

4.1 Memory Map

The S1C63666 data memory consists of 5,120-word RAM, 4,096-word data ROM, 160-word display
memory and 92-word peripheral I/O memory. Figure 4.1.1 shows the overall memory map of the
S1C63666, and Table 4.1.1 the peripheral circuits' (I/O space) memory maps.

0000H

RAM area

1400H

8000H

9000H

F000H

FF00H

FFFFH

Unused area

Data ROM area

Unused area

I/O memory area

F000H

Display memory area

F0A0H

Unused area

FF00H

Peripheral I/O area

FFFFH

Fig. 4.1.1 Memory map

Note: Memory is not implemented in unused areas within the memory map. Further, some non-imple-

mentation areas and unused (access prohibition) areas exist in the peripheral I/O area. If the

program that accesses these areas is generated, its operation cannot be guaranteed. Refer to the

I/O memory maps shown in Table 4.1.1 for the peripheral I/O area.

S1C63666 TECHNICAL MANUAL EPSON 17

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map)

Table 4.1.1 (a) I/O memory map (FF00H–FF31H)

Address Comment

VDC3 VDC2 VDC1 VDC0

FF00H

CLKCHG OSCC 0 0

FF01H

FF04H

CMPON CMPDT SVDDT SVDON

FF05H

FOUTE SWDIR FOFQ1 FOFQ0

FF06H

FF07H

SIK03 SIK02 SIK01 SIK00

FF20H

FF21H

KCP03 KCP02 KCP01 KCP00

FF22H

SIK13 SIK12 SIK11 SIK10

FF24H

FF25H

KCP13 KCP12 KCP11 KCP10

FF26H

R03HIZ R02HIZ R01HIZ R00HIZ

FF30H

FF31H

Register

D3 D2

D1 D0 Name Init

VDC3
VDC2

R/W

VDC1
VDC0

CLKCHG

OSCC

R/W R

0 SVDS2 SVDS1 SVDS0

RR/W

0
0

0
SVDS2
SVDS1
SVDS0

CMPON
CMPDT

R/W R/WR

SVDDT

SVDON

FOUTE
SWDIR

R/W

00WDEN WDRST

R/W WR

FOFQ1
FOFQ0

0

0

WDEN

WDRST

SIK03
SIK02

R/W

SIK01
SIK00

K03 K02 K01 K00

R

KCP03

KCP02

R/W

KCP01

KCP00

SIK13
SIK12
SIK11
SIK10

K12 K11 K10

K13

R/W

R

KCP13

KCP12

R/W

KCP11

KCP10
R03HIZ
R02HIZ

R/W

R01HIZ
R00HIZ

R03 R02 R01 R00

R/W

K03
K02
K01
K00

K13
K12
K11
K10

R03
R02
R01
R00

∗1

10

DD

V

DD

0

1/2V
1/2V

DD

0

On

0

D3

V

0
0

OSC3OnOSC1

0

∗

3

∗

2

–

∗

3

∗

2

–

∗

3

∗

2

–

0
0
0
0

On

0

+ > -

0

Low

0

On

0

Enable Disable

0

0
0

∗

3

∗

2

–

∗

3

∗

2

–

1

Reset

0
0
0

0
–
–
–
–

∗
∗
∗
∗

2
2
2
2

Enable

Reset
Enable
Enable
Enable
Enable

High
High
High
High

∗

3

LCD system voltage regulator power source switch

V

DD

Low-speed operation voltage regulator power source switch

Off

High-speed operation voltage regulator on/off

D1L

V

Logic system power source switch
CPU clock switch

Off

OSC3 oscillation On/Off
Unused
Unused
Unused

SVD criteria voltage setting

0

[SVDS2–0]
Voltage(V)

Analog comparator On/Off

Off

Analog comparator data

+ < -

SVD evaluation data

Normal

SVD circuit On/Off

Off

1

1.85/0.98

2.0022.1532.3042.4552.6062.7572.90

FOUT output enable
Stopwatch direct input switch
0: K00=Run/Stop, K01=Lap 1: K00=Lap, K01=Run/Stop

FOUT
frequency
selection

[FOFQ1, 0]
Frequency

Unused
Unused

Disable

Watchdog timer enable

Invalid

Watchdog timer reset (writing)

Disable
Disable

K00–K03 interrupt selection register

Disable
Disable

Low
Low

K00–K03 input port data

Low

Low
1
1
1

K00–K03 input comparison register

1
0

Enable
Enable
Enable
Enable

High
High
High
High

Disable
Disable

K10–K13 interrupt selection register

Disable
Disable

Low

Low

K10–K13 input port data

Low

Low

–
–
–
–

0
0
0

∗

2

∗

2

∗

2

∗

2

1
1
1

K10–K13 input comparison register

1
0

Hi-Z

0

Hi-Z

0

Hi-Z

0

Hi-Z

0

High

0

High

0

High

0

High

R03 (FOUTE=0)/FOUT (FOUTE=1) Hi-Z control

Output

R02 (PTOUT=0)/TOUT (PTOUT=1) Hi-Z control

Output

R01 Hi-Z control

Output

R00 Hi-Z control

Output

R03

Low

Low

Low

Low

output port data (

R02

output port data (

R01

output port data

R00

output port data

FOUTE=0
PTOUT=0

Remarks

∗1Initial value at initial reset
∗2 Not set in the circuit
∗3 Constantly "0" when being read

0

OSC1

/641f

f

OSC1

) Fix at "1" when
) Fix at "1" when

/82f

FOUT
TOUT

OSC1

OSC3

f

is used.
is used.

3

18 EPSON S1C63666 TECHNICAL MANUAL

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map)

Table 4.1.1 (b) I/O memory map (FF32H–FF62H)

Address Comment

FF32H

FF33H

IOC03 IOC02 IOC01 IOC00

FF40H

PUL03 PUL02 PUL01 PUL00

FF41H

FF42H

IOC13 IOC12 IOC11 IOC10

FF44H

PUL13 PUL12 PUL11 PUL10

FF45H

FF46H

LDUTY1 LDUTY0 STCD LPWR

FF60H

FF61H

FF62H

Register

D3 D2

D1 D0 Name Init

000R1HIZ

RR/W

R13 R12 R11 R10

R/W

R/W

R/W

P03 P02 P01 P00

R/W

R/W

R/W

P13 P12 P11 P10

R/W

R/W

0 ALOFF ALON 0

RRR/W

LC3 LC2 LC1 LC0

R/W

∗

3

0

∗

3

0

∗

3

0

R1HIZ

R13
R12
R11

R10
IOC03
IOC02
IOC01
IOC00
PUL03
PUL02
PUL01
PUL00

P03

P02

P01

P00
IOC13

IOC12

IOC11

IOC10

PUL13

PUL12

PUL11

PUL10

P13

P12

P11

P10

LDUTY1
LDUTY0

STCD
LPWR

∗

3

0
ALOFF

ALON

∗

3

0

LC3

LC2

LC1

LC0

∗1

10

∗

2

–

∗

2

–

∗

2

–

0Hi-ZOutput
0

High

0

High

0

High

0

High

0

Output

0

Output

0

Output

0

Output

1

On

1

On

1

On

1

On

∗

2

High

–

∗

2

–

High

∗

2

–

High

∗

2

–

High

Output

0

Output

0

Output

0

Output

0

On

1

On

1

On

1

On

1

∗

2

–

High

∗

2

High

–

∗

2

High

–

∗

2

High

–

0
0
00StaticOnDynamic

∗

2

–

1

All Off

Normal

0

All On

Normal

–

∗

2

0
0
0
0

Unused
Unused
Unused
R10–R13 Hi-Z control

Low
Low

R10–R13 output port data

Low

Low
Input
Input

P00–P03 I/O control register

Input
Input

Off
Off

P00–P03 pull-down control register

Off

Off
Low
Low

P00–P03 I/O port data

Low
Low

Input

P13 I/O control register

functions as a general-purpose register when SIF (slave) is selected

Input

P12 I/O control register (ESIF=0)
functions as a general-purpose register when SIF is selected

Input

P11 I/O control register (ESIF=0)
functions as a general-purpose register when SIF is selected

Input

P10 I/O control register (ESIF=0)
functions as a general-purpose register when SIF is selected

Off

P13 pull-down control register

functions as a general-purpose register when SIF (slave) is selected

Off

P12 pull-down control register (ESIF=0)

functions as a general-purpose register when SIF (master) is selected
SCLK (I) pull-down control register when SIF (slave) is selected

Off

P11 pull-down control register (ESIF=0)
functions as a general-purpose register when SIF is selected

Off

P10 pull-down control register (ESIF=0)
SIN pull-down control register

Low

P13 I/O port data

functions as a general-purpose register when SIF (slave) is selected

Low

P12 I/O port data (ESIF=0)

when SIF is selected

functions as a general-purpose register when SIF is selected

Low

P11 I/O port data (ESIF=0)
functions as a general-purpose register when SIF is selected

Low

P10 I/O port data (ESIF=0)
functions as a general-purpose register when SIF is selected
LCD drive duty
switch

[LDUTY1, 0]
Duty

LCD drive switch
LCD power On/Off

Off

Unused
LCD all Off control
LCD all On control
Unused

LCD contrast adjustment

[LC3–0]
Contrast

0

Light––15Dark

0

1/411/5

2, 3

1/8

S1C63666 TECHNICAL MANUAL EPSON 19

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map)

Table 4.1.1 (c) I/O memory map (FF6CH–FF79H)

Address Comment

ENRTM ENRST ENON BZE

FF6CH

FF6DH

FF6EH

FF6FH

FF70H

SDP SCPS SCS1 SCS0

FF71H

FF72H

FF73H

FF74H

FF75H

FF76H

EDIR DKM2 DKM1 DKM0

FF78H

LCURF CRNWF SWRUN SWRST

FF79H

Register

D3 D2

D1 D0 Name Init

ENRTM

ENRST

R/W W R/W

0 BZSTP BZSHT SHTPW

ENON

0

BZSTP

BZSHT

RW R/W

0 BZFQ2 BZFQ1 BZFQ0

RR/W

0 BDTY2 BDTY1 BDTY0

RR/W

SHTPW

0
BZFQ2
BZFQ1
BZFQ0
0
BDTY2
BDTY1
BDTY0

0

0 ESOUT SCTRG ESIF

ESOUT

SCTRG

RR/W

ESIF

SCPS

R/W

SCS1
SCS0

SD3 SD2 SD1 SD0

R/W

SD7 SD6 SD5 SD4

R/W

00TMRST TMRUN

WR/WR

0
0

TMRST

TMRUN

TM3 TM2 TM1 TM0

R

TM7 TM6 TM5 TM4

R

EDIR

DKM2

R/W

DKM1
DKM0

LCURF

CRNWF

R/W WR

SWRUN

SWRST

∗

BZE

∗

∗

∗

∗

∗

SDP

SD3
SD2
SD1
SD0
SD7
SD6
SD5
SD4

∗
∗

∗

TM3
TM2
TM1
TM0
TM7
TM6
TM5
TM4

∗1

0

3

Reset

0
0

3

∗

–

3

0
0

0

3

∗

–

0
0
0

3

∗

–

0
0
0

3

∗

–

0
0

0
0
0

0
0

∗

–

∗

–

∗

–

∗

–

∗

–

∗

–

∗

–

∗

–

3

∗

–

3

∗

–

3

Reset0Reset

0
0
0
0
0
0
0
0

0
0
0
0
0
0
0

∗

3

Reset

10

1 sec

0.5 sec

Reset

Invalid

On

Enable

Stop

Trigger

Busy

125 msec

Enable

Trigger

Disable

Invalid
Invalid
Ready

31.25 msec

Disable

Invalid

2

2

2

2

Run

SIF

MSB first LSB first

2

High

2

High

2

High

2

High

2

High

2

High

2

High

2

High

2
2

Invalid

Run

Enable Disable

Request
Renewal

Run

Reset

Invalid

Envelope releasing time selection
Envelope reset (writing)
Envelope On/Off

Off

Buzzer output enable
Unused
1-shot buzzer stop (writing)
1-shot buzzer trigger (writing)
1-shot buzzer status (reading)
1-shot buzzer pulse width setting

Unused
Buzzer
frequency
selection

[BZFQ2, 1, 0]
Frequency (Hz)
[BZFQ2, 1, 0]
Frequency (Hz)

Unused
Buzzer signal duty ratio selection

(refer to main manual)
Unused

SOUT enable
Serial I/F clock trigger (writing)
Serial I/F clock status (reading)

Stop

Serial I/F enable (P1 port function selection)

I/O

Serial I/F data input/output permutation
Serial I/F clock phase selection
–Negative polarity (mask option)
–Positive polarity (mask option)
Serial I/F
clock mode selection
MSB

Low
Low

Serial I/F transmit/receive data (low-order 4 bits)

Low

LSB

Low

MSB

Low
Low

Serial I/F transmit/receive data (high-order 4 bits)

Low

LSB

Low

Unused
Unused
Clock timer reset (writing)

Stop

Clock timer Run/Stop
Clock timer data (16 Hz)
Clock timer data (32 Hz)
Clock timer data (64 Hz)
Clock timer data (128 Hz)
Clock timer data (1 Hz)
Clock timer data (2 Hz)
Clock timer data (4 Hz)
Clock timer data (8 Hz)

Direct input enable
Key mask
selection

[DKM2, 1, 0]
Key mask

[DKM2, 1, 0]
Key mask

Lap data carry-up request flag

No

Capture renewal flag

No

Stopwatch timer Run/Stop

Stop

Stopwatch timer reset (writing)

0

4096.013276.822730.732340.6
4

2048.051638.461365.371170.3

[SCS1, 0]
Clock
[SCS1, 0]
Clock

0

Slave

2

OSC1/2

1

PT

3

OSC1

0

None1K022K02–033K02–03,10

4

K105K10–116K10–127K10–13

20 EPSON S1C63666 TECHNICAL MANUAL

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map)

Table 4.1.1 (d) I/O memory map (FF7AH–FF93H)

Address Comment

SWD3 SWD2 SWD1 SWD0

FF7AH

SWD7 SWD6 SWD5 SWD4

FF7BH

SWD11 SWD10 SWD9 SWD8

FF7CH

FF80H

FF81H

DRL3 DRL2 DRL1 DRL0

FF82H

DRL7 DRL6 DRL5 DRL4

FF83H

DRH3 DRH2 DRH1 DRH0

FF84H

DRH7 DRH6 DRH5 DRH4

FF85H

FF86H

FF90H

OVTBC OVMC

FF91H

MC3 MC2 MC1 MC0

FF92H

MC7 MC6 MC5 MC4

FF93H

Register

D3 D2

D1 D0 Name Init

R

R

R

SR3 SR2 SR1 SR0

R/W

SR7 SR6 SR5 SR4

R/W

R/W

R/W

R/W

R/W

NF VF ZF CALMD

RR/W

000SENSEL

RR/W

RFRUNR RFRUNS

R/W

R/W

R/W

SWD3
SWD2
SWD1
SWD0
SWD7
SWD6
SWD5

SWD4
SWD11
SWD10

SWD9

SWD8

SR3
SR2
SR1
SR0
SR7
SR6
SR5

SR4
DRL3
DRL2
DRL1
DRL0
DRL7
DRL6
DRL5
DRL4

DRH3
DRH2
DRH1
DRH0
DRH7
DRH6
DRH5
DRH4

NF
VF
ZF

CALMD

∗

3

0

∗

3

0

∗

3

0

SENSEL

OVTBC

OVMC
RFRUNR
RFRUNS

MC3
MC2
MC1
MC0
MC7
MC6
MC5
MC4

∗1

10
0
0
0
0
0
0
0
0
0
0
0
0

∗

2

–

∗

2

–

∗

2

–

∗

2

–

∗

2

–

∗

2

–

∗

2

–

∗

2

–

∗

2

–

∗

2

–

∗

2

–

∗

2

–

∗

2

–

∗

2

–

∗

2

–

∗

2

–

∗

2

–

∗

2

–

∗

2

–

∗

2

–

∗

2

–

∗

2

–

∗

2

–

∗

2

–

0

Negative

Positive

0

Overflow

0

Zero

0

Run

Div.
–
–
–

∗

2

∗

2

∗

2

Mult.

0 Sensor 1 Sensor 0
0

Overflow

Non-ov

0

Overflow

Non-ov

0

Run

0

Run

∗

2

–

∗

2

–

∗

2

–

∗

2

–

∗

2

–

∗

2

–

∗

2

–

∗

2

–

Stopwatch timer data
BCD (1/1000 sec)

Stopwatch timer data
BCD (1/100 sec)

Stopwatch timer data
BCD (1/10 sec)

Source register (low-order 4 bits)
LSB

MSB
Source register (high-order 4 bits)

Low-order 8-bit destination register
(low-order 4 bits)
LSB
MSB
Low-order 8-bit destination register
(high-order 4 bits)

High-order 8-bit destination register
(low-order 4 bits)
LSB
MSB
High-order 8-bit destination register
(high-order 4 bits)

Negative flag
Overflow flag

No

Zero flag

No

Operation status (reading)

Stop

Calculation mode selection (writing)
Unused
Unused
Unused
Sensor selection
Time base counter overflow flag
Measurement counter overflow flag
Reference oscillation Run/Stop control

Stop

Sensor oscillation Run/Stop control

Stop

Measurement counter MC0–MC3
LSB

Measurement counter MC4–MC7

S1C63666 TECHNICAL MANUAL EPSON 21

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map)

Table 4.1.1 (e) I/O memory map (FF94H–FFC5H)

Address Comment

MC11 MC10 MC9 MC8

FF94H

MC15 MC14 MC13 MC12

FF95H

MC19 MC18 MC17 MC16

FF96H

TC3 TC2 TC1 TC0

FF97H

TC7 TC6 TC5 TC4

FF98H

TC11 TC10 TC9 TC8

FF99H

TC15 TC14 TC13 TC12

FF9AH

TC19 TC18 TC17 TC16

FF9BH

MOD16

FFC0H

FFC1H

FFC2H

PTPS01 PTPS00 PTRST0 PTRUN0

FFC3H

PTPS11 PTPS10 PTRST1 PTRUN1

FFC4H

PTPS21 PTPS20 PTRST2 PTRUN2

FFC5H

Register

D3 D2

D1 D0 Name Init

MC11
MC10

R/W

MC9

MC8
MC15
MC14

R/W

MC13
MC12
MC19
MC18

R/W

MC17
MC16

TC3
TC2

R/W

TC1
TC0
TC7
TC6

R/W

TC5

TC4
TC11
TC10

R/W

TC9

TC8
TC15
TC14

R/W

TC13
TC12
TC19
TC18

R/W

EVCNT FCSEL PLPOL

R/W

0 CHSEL1 CHSEL0 PTOUT

RR/W

0 CKSEL2 CKSEL1 CKSEL0

RR/W

TC17
TC16

MOD16
EVCNT
FCSEL
PLPOL

0
CHSEL1
CHSEL0

PTOUT

0
CKSEL2
CKSEL1
CKSEL0

PTPS01
PTPS00

WR/WR/W

PTRST0

PTRUN0

PTPS11
PTPS10

WR/WR/W

PTRST1

PTRUN1

PTPS21
PTPS20

WR/WR/W

PTRST2

PTRUN2

∗1

10

∗

2

–

∗

2

–

∗

2

–

∗

2

–

∗

2

–

∗

2

–

∗

2

–

∗

2

–

∗

2

–

∗

2

–

∗

2

–

∗

2

–

∗

2

–

∗

2

–

∗

2

–

∗

2

–

∗

2

–

∗

2

–

∗

2

–

∗

2

–

∗

2

–

∗

2

–

∗

2

–

∗

2

–

∗

2

–

∗

2

–

∗

2

–

∗

2

–

∗

2

–

∗

2

–

∗

2

–

∗

2

–

0

16 bits

0

Event ct.

0

With NR

0

∗

3

∗

2

–

0
0
0OnOff

∗

3

∗

2

–

0

OSC3

0

OSC3

0

OSC3

0
0

∗

3

∗

2

Reset

–

0

Run
0
0

∗

3

∗

2

Reset

–

0

Run
0
0

∗

3

∗

2

Reset

–

0

Run

Measurement counter MC8–MC11

Measurement counter MC12–MC15

MSB
Measurement counter MC16–MC19

Time base counter TC0–TC3
LSB

Time base counter TC4–TC7

Time base counter TC8–TC11

Time base counter TC12–TC15

MSB
Time base counter TC16–TC19

16-bit mode selection

8 bits

Timer 0 counter mode selection

Timer

Timer 0 function selection (for event counter mode)

No NR

Timer 0 pulse polarity selection (for event counter mode)
Unused
TOUT output
selection

[CHSEL1,0]
Timer

TOUT output control
Unused
Prescaler 2 source clock selection

OSC1

Prescaler 1 source clock selection

OSC1

Prescaler 0 source clock selection

OSC1

Prescaler 0
division ratio
selection

Timer 0 reset (reload)

Invalid

Timer 0 Run/Stop

Stop

Prescaler 1
division ratio
selection

Timer 1 reset (reload)

Invalid

Timer 1 Run/Stop

Stop

Prescaler 2
division ratio
selection

Timer 2 reset (reload)

Invalid

Timer 2 Run/Stop

Stop

[PTPS01, 00]
Division ratio

[PTPS11, 10]
Division ratio

[PTPS21, 20]
Division ratio

0

Timer 01Timer 12Timer 2

0

1/111/421/3231/256

0

1/111/421/3231/256

0

1/111/421/3231/256

22 EPSON S1C63666 TECHNICAL MANUAL

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map)

Table 4.1.1 (f) I/O memory map (FFC6H–FFE3H)

Address Comment

RLD03 RLD02 RLD01 RLD00

FFC6H

RLD07 RLD06 RLD05 RLD04

FFC7H

RLD13 RLD12 RLD11 RLD10

FFC8H

RLD17 RLD16 RLD15 RLD14

FFC9H

RLD23 RLD22 RLD21 RLD20

FFCAH

RLD27 RLD26 RLD25 RLD24

FFCBH

PTD03 PTD02 PTD01 PTD00

FFCCH

PTD07 PTD06 PTD05 PTD04

FFCDH

PTD13 PTD12 PTD11 PTD10

FFCEH

PTD17 PTD16 PTD15 PTD14

FFCFH

PTD23 PTD22 PTD21 PTD20

FFD0H

PTD27 PTD26 PTD25 PTD24

FFD1H

FFE1H

FFE2H

FFE3H

Register

D3 D2

D1 D0 Name Init

RLD03
RLD02

R/W

RLD01
RLD00
RLD07
RLD06

R/W

RLD05
RLD04
RLD13
RLD12

R/W

RLD11
RLD10
RLD17
RLD16

R/W

RLD15
RLD14
RLD23
RLD22

R/W

RLD21
RLD20
RLD27
RLD26

R/W

RLD25
RLD24
PTD03
PTD02

R

PTD01
PTD00
PTD07
PTD06

R

PTD05
PTD04
PTD13
PTD12

R

PTD11
PTD10
PTD17
PTD16

R

PTD15
PTD14
PTD23
PTD22

R

PTD21
PTD20
PTD27
PTD26

R

0EIPT2 EIPT1 EIPT0

RR/W

000EISIF

RR/W

000EIK0

RR/W

PTD25
PTD24

0

EIPT2
EIPT1

EIPT0
0
0
0

EISIF
0
0
0

EIK0

∗1

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

∗

3

∗

2

–

0
0
0

∗

3

∗

2

–

∗

3

∗

2

–

∗

3

∗

2

–

0 Enable Mask

∗

3

∗

2

–

∗

3

∗

2

–

∗

3

∗

2

–

0 Enable Mask

10

Enable

Mask

Enable

Mask

Enable

Mask

MSB
Programmable timer 0 reload data (low-order 4 bits)
LSB

MSB
Programmable timer 0 reload data (high-order 4 bits)
LSB

MSB
Programmable timer 1 reload data (low-order 4 bits)
LSB

MSB
Programmable timer 1 reload data (high-order 4 bits)
LSB

MSB
Programmable timer 2 reload data (low-order 4 bits)
LSB

MSB
Programmable timer 2 reload data (high-order 4 bits)
LSB

MSB
Programmable timer 0 data (low-order 4 bits)
LSB

MSB
Programmable timer 0 data (high-order 4 bits)
LSB

MSB
Programmable timer 1 data (low-order 4 bits)
LSB

MSB
Programmable timer 1 data (high-order 4 bits)
LSB

MSB
Programmable timer 2 data (low-order 4 bits)
LSB

MSB
Programmable timer 2 data (high-order 4 bits)
LSB

Unused
Interrupt mask register (Programmable timer 2)
Interrupt mask register (Programmable timer 1)
Interrupt mask register (Programmable timer 0)
Unused
Unused
Unused
Interrupt mask register (Serial I/F)
Unused
Unused
Unused
Interrupt mask register (K00–K03)

S1C63666 TECHNICAL MANUAL EPSON 23

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map)

Table 4.1.1 (g) I/O memory map (FFE4H–FFF7H)

Address Comment

FFE4H

EIT3 EIT2 EIT1 EIT0

FFE5H

EIRUN EILAP EISW1 EISW10

FFE6H

FFE7H

FFF1H

FFF2H

FFF3H

FFF4H

FFF5H

IRUN ILAP ISW1 ISW10

FFF6H

FFF7H

Register

D3 D2

000EIK1

D1 D0 Name Init

0
0

RR/W

0

EIK1
EIT3
EIT2

R/W

EIT1
EIT0

EIRUN

EILAP

R/W

00EIRFB EIRFM

RR/W

0IPT2 IPT1 IPT0

RR/W

000ISIF

RR/W

000IK0

RR/W

000IK1

RR/W

IT3 IT2 IT1 IT0

R/W

EISW1

EISW10

0
0

EIRFB

EIRFM

0

IPT2
IPT1

IPT0
0
0
0

ISIF
0
0
0

IK0
0
0
0

IK1

IT3

IT2

IT1

IT0

IRUN
ILAP

R/W

00IRFB IRFM

RR/W

ISW1

ISW10
0
0

IRFB
IRFM

∗1

∗

3

∗

2

–

∗

3

∗

2

–

∗

3

∗

2

–

0 Enable Mask
0
0
0
0
0
0
0
0

∗

3

∗

2

–

∗

3

∗

2

–

00Enable

∗

3

∗

2

–

0
0
0

∗

3

∗

2

–

∗

3

∗

2

–

∗

3

∗

2

–

0

∗

3

∗

2

–

∗

3

∗

2

–

∗

3

∗

2

–

0

∗

3

∗

2

–

∗

3

∗

2

–

∗

3

∗

2

–

0
0
0
0
0
0
0
0
0

∗

3

∗

2

–

∗

3

∗

2

–

0
0

10

Enable

Mask

Enable

Mask

Enable

Mask

Enable

Mask

Enable

Mask

Enable

Mask

Enable

Mask

Enable

Mask

Mask

Enable

Mask

(R)

(R)

Yes

No

(W)

(W)

Reset

Invalid

(R)

(R)

Yes

No

(W)

(W)

Reset

Invalid

(R)

(R)

Yes

No

(W)

(W)

Reset

Invalid

(R)

(R)

Yes

No

(W)

(W)

Reset

Invalid

(R)

(R)

Yes

No

(W)

(W)

Reset

Invalid

(R)

(R)

Yes

No

(W)

(W)

Reset

Invalid

(R)

(R)

Yes

No

(W)

(W)

Reset

Invalid

Unused
Unused
Unused
Interrupt mask register (K10–K13)
Interrupt mask register (Clock timer 1 Hz)
Interrupt mask register (Clock timer 2 Hz)
Interrupt mask register (Clock timer 8 Hz)
Interrupt mask register (Clock timer 32 Hz)
Interrupt mask register (Stopwatch direct RUN)
Interrupt mask register (Stopwatch direct LAP)
Interrupt mask register (Stopwatch timer 1 Hz)
Interrupt mask register (Stopwatch timer 10 Hz)
Unused
Unused
Interrupt mask register (R/f converter reference oscillate completion)
Interrupt mask register (R/f converter sensor oscillate completion)
Unused
Interrupt factor flag (Programmable timer 2)
Interrupt factor flag (Programmable timer 1)
Interrupt factor flag (Programmable timer 0)
Unused
Unused
Unused
Interrupt factor flag (Serial I/F)
Unused
Unused
Unused
Interrupt factor flag (K00–K03)
Unused
Unused
Unused
Interrupt factor flag (K10–K13)
Interrupt factor flag (Clock timer 1 Hz)
Interrupt factor flag (Clock timer 2 Hz)
Interrupt factor flag (Clock timer 8 Hz)
Interrupt factor flag (Clock timer 32 Hz)
Interrupt factor flag (Stopwatch direct RUN)
Interrupt factor flag (Stopwatch direct LAP)
Interrupt factor flag (Stopwatch timer 1 Hz)
Interrupt factor flag (Stopwatch timer 10 Hz)
Unused
Unused
Interrupt factor flag (R/f converter reference oscillate completion)
Interrupt factor flag (R/f converter sensor oscillate completion)

24 EPSON S1C63666 TECHNICAL MANUAL

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Power Control)

4.2 Power Control

4.2.1 Configuration of power supply circuit

The S1C63666 has built-in power supply circuits shown in Figure 4.2.1.1 so the voltages to drive the CPU,
internal logic circuits, oscillation circuits and LCD driver can be generated on the chip.

CC

CD

DDA

External

power

supply

V

V

DD

V

D2

V

C1

V

C2

V

C3

CA

+

CB

OSC

V

V

D1

V

SS

V

SSA

VDC3

VDC2

Voltage

halver

VD2=1/2 V

LCD system voltage circuit

DD

LPWR

LCD system

voltage regulator

Voltage booster

Voltage regulator for

OSC1 oscillation circuit

Low-speed operation

voltage regulator

VDC0

High-speed operation

voltage regulator

VDC1

V

C1

V

C1

V

C2

V

C3

V

OSC

V

D1L

V

D3

converter

LCD driver

oscillation circuit

V

D1

internal circuits

oscillation circuit

R/f

OSC1

CPU,

OSC3

Fig. 4.2.1.1 Built-in power supply circuit

Voltage regulator for OSC1 oscillation circuit

This voltage regulator always operates to generate the VOSC voltage (0.98 V Typ.) for driving the
OSC1 oscillation circuit.

Low-speed operation voltage regulator

The low-speed operation voltage regulator always operates to generate the VD1L voltage (1.25 V Typ.)
for driving the internal logic circuits. The V
CPU and internal logic circuits when they are driven with the OSC1 clock (32 kHz). V

D1L voltage is used as the VD1 operating voltage of the

D1 should be

switched using software according to the operating clock.

High-speed operation voltage regulator

The high-speed operation voltage regulator generates the VD3 voltage (2.0 V Typ.) for driving the
OSC3 oscillation circuit and the internal logic circuits in high-speed mode. Since this regulator stops
normally, turn it on using the VDC1 register (VDC1 = "1") and switch the internal logic operating
voltage to V

D3 using the VDC0 register before starting the OSC3 oscillation.

LCD system voltage circuit

The LCD system voltage circuit generates the LCD drive voltage. This circuit can be turned on and off
using the LPWR register. Turn this circuit on (LPWR = "1") before starting display on the LCD.
The LCD system voltage circuit generates V
other voltages (V

C2 = 2VC1, VC3 = 3VC1) by boosting VC1. The VC1 voltage value can be adjusted using

software in 16 steps (0.95 to 1.40 V). Refer to Section 4.8, "LCD Driver", for control of the V
(contrast). This circuit does not operate when an external power supply is selected by mask option for
driving the LCD.

C1 with the built-in voltage regulator, and generates two

C1 voltage

S1C63666 TECHNICAL MANUAL EPSON 25

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Power Control)

Voltage halver

The voltage halver generates VD2 by halving the supply voltage VDD. Using this halved supply
voltage to drive the low-speed operation voltage regulator and LCD system voltage circuit reduces
current consumption during HALT or low-speed operation. This status is the halver mode and the
VDC2 register is used to set the low-speed operation voltage regulator into the halver mode and the
VDC3 register is used to set the LCD system voltage circuit. However, the supply voltage must be 2.4
V or more to set the halver mode. Furthermore, the halver mode cannot be set during high-speed
operation using the OSC3 clock.
In the normal mode, the low-speed operation voltage regulator and LCD system voltage circuit
operate with the supply voltage V

DD directly.

At initial reset, the normal mode is set by hardware.
The voltage halver always operates regardless of the mode set.

4.2.2 Power control procedure

At initial reset, the power supply, operating voltage and oscillation circuit are set as follows:

• Low-speed operation voltage regulator: ON
Normal mode (VDC2 = "0")

• LCD system voltage circuit: OFF (LPWR = "0")
Normal mode (VDC3 = "0")

• High-speed operation voltage regulator: OFF (VDC1 = "0")

• CPU/internal logic operating voltage: V

• CPU system clock: OSC1 (CLKCHG = "0")

• OSC3 oscillation circuit: OFF (OSCC = "0")

D1L (VDC0 = "0")

Setting halver mode

The low-speed operation voltage regulator and the LCD system voltage circuit can be set into the
halver mode independently.

Setting the low-speed operation voltage regulator

The low-speed operation voltage regulator can be set into the halver mode under the conditions
below.

• When the supply voltage V

• When the CPU/internal circuits operate with the V

The following shows the switching procedure from normal mode to halver mode.

1. Switch the CPU clock from OSC3 to OSC1 (CLKCHG = "0", when OSC3 is used as the CPU clock)

2. Stop the OSC3 oscillation (OSCC = "0")

3. Switch the internal operating voltage from V

4. Turn the high-speed operation voltage circuit off (VDC1 = "0")

5. Check that the supply voltage V

6. Set the halver mode (VDC2 = "1")

Steps 1 to 4 are necessary during high-speed operation.

Setting the LCD system voltage circuit

The LCD system voltage circuit can be set into the halver mode under the conditions below.

• When the supply voltage V

• When the V

C1 setup value for driving the LCD is 1.13 V or lower.

The following shows the switching procedure.

1. Check that the supply voltage V

2. Set the LCD drive voltage V

3. Set the halver mode (VDC3 = "1")

DD is 2.4 V or higher.

D1L operating voltage and OSC1 operating clock.

D3 to VD1L (VDC0 = "0")

DD is 2.4 V or higher using the SVD circuit

DD is 2.4 V or higher.

DD is 2.4 V or higher using the SVD circuit

C1 to 1.13 V or lower (LC3–LC0 ≤ 6)

26 EPSON S1C63666 TECHNICAL MANUAL

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Power Control)

Switching to high-speed operation

The S1C63666 is designed with twin clock specifications; it has two types of oscillation circuits OSC1
(for low-speed operation) and OSC3 (for high-speed operation) built-in. Use OSC1 clock for normal
operation, and switch it to OSC3 using software when high-speed operation is necessary. When
switching the clock, the operating voltage V

D1 must be switched using software to stabilize the

operation of the oscillation circuit and internal circuits.
The following shows the switching procedure. Refer to Section 4.4, "Oscillation Circuit", for control of
the oscillation circuit.

Switching from low-speed operation to high-speed operation

1. Set VDC2 to "0". (low-speed operation voltage regulator: halver mode → normal mode)

2. Set VDC1 to "1". (high-speed operation voltage regulator: off → on)

3. Set VDC0 to "1". (internal logic operating voltage: V

D1L → VD3)

4. Wait 2.5 msec or more.

5. Set OSCC to "1". (OSC3 oscillation: off → on)

6. Wait 5 msec or more.

7. Set CLKCHG to "1". (CPU clock: OSC1 → OSC3)

To switch from high-speed operation to low-speed operation, follow the procedure to set the halver
mode (see the previous page).

4.2.3 I/O memory for power control

Table 4.2.3.1 shows the I/O address and the control bits for power control.

Table 4.2.3.1 Power control bits

Address Comment

VDC3 VDC2 VDC1 VDC0

FF00H

LDUTY1 LDUTY0 STCD LPWR

FF60H

*1 Initial value at initial reset
*2 Not set in the circuit
*3 Constantly "0" when being read

D3 D2

Register

D1 D0 Name Init

R/W

R/W

VDC3
VDC2
VDC1

VDC0
LDUTY1
LDUTY0

STCD

LPWR

∗1

10

DD

V

On
V

DD

DD

V

DD

Off

D3

D1L

V

Off

0

1/2V
1/2V

0
0
0
0
0
00StaticOnDynamic

LCD system voltage regulator power source switch
Low-speed operation voltage regulator power source switch
High-speed operation voltage regulator on/off
Logic system power source switch

LCD drive duty
switch
LCD drive switch
LCD power On/Off

[LDUTY1, 0]
Duty

0

1/411/5

2, 3

1/8

VDC0: Internal logic system power switching register (FF00H•D0)

It is used to switch the operating voltage for the CPU and internal circuit.

When "1" is written: V
When "0" is written: V

D3 (for OSC3 operation)
D1L (for OSC1 operation)

Reading: Valid

When "1" is written to VDC0, the internal operating voltage is switched to V

D3. After switching to VD3,

the OSC3 oscillation can be started.
When the low-speed operation voltage regulator is in the halver mode, return it to the normal mode
before switching to V
When "0" is written to VDC0, the internal operating voltage is switched to V
before switching to V

D3.

D1L. Stop the OSC3 oscillation

D1L.

At initial reset, this register is set to "0".

S1C63666 TECHNICAL MANUAL EPSON 27

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Power Control)

VDC1: High-speed operation voltage regulator control (ON/OFF) register (FF00H•D1)

Turns the high-speed operation voltage regulator on and off.

When "1" is written: On
When "0" is written: Off

Reading: Valid

When "1" is written to VDC1, the high-speed operation voltage regulator goes to generate the high-speed
operation voltage V

D3 for the internal logic circuits.

When "0" is written to VDC1, the high-speed operation voltage regulator stops operating. Do not write
"0" to VDC1 while the CPU is operating with the OSC3 clock.
At initial reset, this register is set to "0".

VDC2: Low-speed operation voltage regulator power control register (FF00H•D2)

Sets the low-speed operation voltage regulator to the halver mode.

When "1" is written: Halver mode (driven with 1/2 V
When "0" is written: Normal mode (driven with V

DD)

DD)

Reading: Valid

When "1" is written to VDC2, the low-speed operation voltage regulator enters the halver mode. In this
mode, the low-speed operation voltage regulator operates with 1/2 the V
possible to reduce current consumption. However, the supply voltage V

DD voltage, this makes it

DD must be 2.4 V or higher.

Furthermore, this mode does not allow high-speed operation using the OSC3 clock.
When "0" is written to VDC2, the low-speed operation voltage regulator enters the normal mode and
operates with the supply voltage V

DD.

At initial reset, the hardware sets the normal mode and this register is set to "0".

VDC3: LCD system voltage circuit power control register (FF00H•D3)

Sets the LCD system voltage circuit to the halver mode.

When "1" is written: Halver mode (driven with 1/2 V
When "0" is written: Normal mode (driven with V

DD)

DD)

Reading: Valid

When "1" is written to VDC3, the LCD system voltage circuit enters the halver mode. In this mode, the
LCD system voltage circuit operates with 1/2 the V
consumption. However, the supply voltage V

DD voltage, this makes it possible to reduce current

DD must be 2.4 V or higher and the VC1 setup voltage must

be 1.13 V or lower. Furthermore, this mode does not allow high-speed operation using the OSC3 clock.
When "0" is written to VDC3, the LCD system voltage circuit enters the normal mode and operates with
the supply voltage V

DD.

At initial reset, the hardware sets the normal mode and this register is set to "0".

LPWR: LCD power control (ON/OFF) register (FF60H•D0)

Turns the LCD system voltage circuit on and off.

When "1" is written: On
When "0" is written: Off

Reading: Valid

When "1" is written to the LPWR register, the LCD system voltage circuit goes on and generates the LCD
drive voltage. When "0" is written, all the LCD drive voltages go to V

SS level.

It takes about 100 msec for the LCD drive voltage to stabilize after starting up the LCD system voltage
circuit by writing "1" to the LPWR register.
At initial reset, this register is set to "0".

28 EPSON S1C63666 TECHNICAL MANUAL

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Power Control)

4.2.4 Programming notes

(1) When setting the low-speed operation voltage regulator to the halver mode, make sure that the

supply voltage is 2.4 V or higher using the SVD circuit before writing "1" to VDC2. Furthermore,
switch the CPU clock to OSC1.

(2) When setting the LCD system voltage circuit to the halver mode, make sure that the supply voltage is

2.4 V or higher using the SVD circuit before writing "1" to VDC3. Furthermore, set the V
(contrast) to 1.13 V or lower (LC register = 6 or less).

C1 voltage

S1C63666 TECHNICAL MANUAL EPSON 29

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Watchdog Timer)

4.3 Watchdog Timer

4.3.1 Configuration of watchdog timer

The S1C63666 has a built-in watchdog timer that operates with a 256 Hz divided clock from the OSC1 as
the source clock. The watchdog timer starts operating after initial reset, however, it can be stopped by the
software. The watchdog timer must be reset cyclically by the software while it operates. If the watchdog
timer is not reset in at least 3–4 seconds, it generates a non-maskable interrupt (NMI) to the CPU.
Figure 4.3.1.1 is the block diagram of the watchdog timer.

OSC1 dividing signal 256 Hz

Watchdog timer enable signal

Watchdog timer reset signal

Fig. 4.3.1.1 Watchdog timer block diagram

The watchdog timer contains a 10-bit binary counter, and generates the non-maskable interrupt when the
last stage of the counter (0.25 Hz) overflows.
Watchdog timer reset processing in the program's main routine enables detection of program overrun,
such as when the main routine's watchdog timer processing is bypassed. Ordinarily this routine is
incorporated where periodic processing takes place, just as for the timer interrupt routine.
The watchdog timer operates in the HALT mode. If a HALT status continues for 3–4 seconds, the non­maskable interrupt releases the HALT status.

Watchdog timer

Non-maskable
interrupt (NMI)

4.3.2 Interrupt function

If the watchdog timer is not reset periodically, the non-maskable interrupt (NMI) is generated to the core
CPU. Since this interrupt cannot be masked, it is accepted even in the interrupt disable status (I flag =
"0"). However, it is not accepted when the CPU is in the interrupt mask state until SP1 and SP2 are set as a
pair, such as after initial reset or during re-setting the stack pointer. The interrupt vector of NMI is
assigned to 0100H in the program memory.

30 EPSON S1C63666 TECHNICAL MANUAL

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Watchdog Timer)

4.3.3 I/O memory of watchdog timer

Table 4.3.3.1 shows the I/O address and control bits for the watchdog timer.

Table 4.3.3.1 Control bits of watchdog timer

Address Comment

FF07H

*1 Initial value at initial reset
*2 Not set in the circuit
*3 Constantly "0" when being read

WDEN: Watchdog timer enable register (FF07H•D1)

Selects whether the watchdog timer is used (enabled) or not (disabled).

When "1" is written: Enabled
When "0" is written: Disabled

When "1" is written to the WDEN register, the watchdog timer starts count operation. When "0" is written,
the watchdog timer does not count and does not generate the interrupt (NMI).
At initial reset, this register is set to "1".

Register

D3 D2

00WDEN WDRST

D1 D0 Name Init

R/W WR

Reading: Valid

∗

0

∗

0

WDEN

WDRST

∗1

∗

2

∗

2

1

Enable

10

Disable

Reset

Invalid

Unused
Unused
Watchdog timer enable
Watchdog timer reset (writing)

3

–

3

–

∗

3

Reset

WDRST: Watchdog timer reset (FF07H•D0)

Resets the watchdog timer.

When "1" is written: Watchdog timer is reset
When "0" is written: No operation

Reading: Always "0"

When "1" is written to WDRST, the watchdog timer is reset and restarts immediately after that. When "0"
is written, no operation results.
This bit is dedicated for writing, and is always "0" for reading.

4.3.4 Programming notes

(1) When the watchdog timer is being used, the software must reset it within 3-second cycles.

(2) Because the watchdog timer is set in operation state by initial reset, set the watchdog timer to disabled

state (not used) before generating an interrupt (NMI) if it is not used.

S1C63666 TECHNICAL MANUAL EPSON 31

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Oscillation Circuit)

4.4 Oscillation Circuit

4.4.1 Configuration of oscillation circuit

The S1C63666 has two oscillation circuits (OSC1 and OSC3). OSC1 is a crystal oscillation circuit that
supplies the operating clock to the CPU and peripheral circuits. OSC3 is either a CR or a ceramic oscilla­tion circuit. When processing with the S1C63666 requires high-speed operation, the CPU operating clock
can be switched from OSC1 to OSC3 by the software. To stabilize operation of the internal circuits, the
operating voltage must be switched according to the oscillation circuit to be used. Figure 4.4.1.1 is the
block diagram of this oscillation system.

VOSC

VD1

OSC1
oscillation circuit

OSC3
oscillation circuit

Divider

Clock

switch

To peripheral circuits

To CPU

CPU clock selection signal

Oscillation circuit control signal

Operating voltage selection signal

Voltage regulator for
OSC1 oscillation circuit

High-speed operation
voltage regulator

Fig. 4.4.1.1 Oscillation system block diagram

4.4.2 OSC1 oscillation circuit

The OSC1 crystal oscillation circuit generates the main clock for the CPU and the peripheral circuits. The
oscillation frequency is 32.768 kHz (Typ.).
Figure 4.4.2.1 is the block diagram of the OSC1 oscillation circuit.

CGX

X'tal

VSS

OSC1

OSC2

FX

R

DX

R

To CPU
(and peripheral circuits)

CDX

Fig. 4.4.2.1 OSC1 oscillation circuit

VSS

As shown in Figure 4.4.2.1, the crystal oscillation circuit can be configured simply by connecting the
crystal oscillator (X'tal) of 32.768 kHz (Typ.) between the OSC1 and OSC2 terminals and the trimmer
capacitor (C

32 EPSON S1C63666 TECHNICAL MANUAL

GX) between the OSC1 and VSS terminals.

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Oscillation Circuit)

4.4.3 OSC3 oscillation circuit

The S1C63666 has built-in the OSC3 oscillation circuit that generates the CPU's sub-clock (Max. 4 MHz)
for high speed operation and the source clock for peripheral circuits needing a high speed clock (pro­grammable timer, FOUT output). The mask option enables selection of the oscillator type from CR
(external R type), CR (built-in R type) and ceramic oscillation circuit. When CR oscillation (external R
type) is selected, only a resistance is required as an external element. When ceramic oscillation is selected,
a ceramic oscillator and two capacitors (gate and drain capacitance) are required. When CR oscillation
(built-in R type) is selected, no external element is required.
Figure 4.4.3.1 is the block diagram of the OSC3 oscillation circuit.

C

CR

OSC3

CR

R

OSC4

(a) CR oscillation circuit (external R type)

CR

C

CR

R

To CPU
(and some peripheral circuits)

Oscillation circuit control signal

To CPU
(and some peripheral circuits)

Oscillation circuit control signal

(b) CR oscillation circuit (built-in R type)

C

GC

C

DC

V

SS

OSC3

Ceramic

OSC4

To CPU

FC

R

R

DC

(and some peripheral circuits)

Oscillation circuit control signal

(c) Ceramic oscillation circuit

Fig. 4.4.3.1 OSC3 oscillation circuit

As shown in Figure 4.4.3.1, the CR oscillation circuit (external R type) can be configured simply by
connecting the resistor R
Chapter 7, "Electrical Characteristics" for resistance value of R

CR between the OSC3 and OSC4 terminals when CR oscillation is selected. See

CR.

When ceramic oscillation is selected, the ceramic oscillation circuit can be configured by connecting the
ceramic oscillator (Max. 4 MHz) between the OSC3 and OSC4 terminals, capacitor C
and OSC4 terminals, and capacitor C

DC between the OSC4 and VSS terminals. For both CGC and CDC,

GC between the OSC3

connect capacitors that are about 30 pF. To reduce current consumption of the OSC3 oscillation circuit,
oscillation can be stopped by the software (OSCC register).

Table 4.4.3.1 OSC3 oscillation frequency

Oscillation circuit

Ceramic oscillation
CR oscillation (built-in R type)
CR oscillation (external R type)

Oscillation frequency

Max. 4 MHz

Typ. 1.1 MHz ±30%

200 kHz to 2 MHz

S1C63666 TECHNICAL MANUAL EPSON 33

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Oscillation Circuit)

4.4.4 Switching of operating voltage

The CPU system clock is switched to OSC1 or OSC3 by the software (CLKCHG register). In this case, to
obtain stable operation, the operating voltage for the internal circuits must be switched by the software
(VDC0 register).

When running with the OSC1 clock: Operating clock = V
When running with the OSC3 clock: Operating clock = V

The CPU clock should be switched using the following procedure. Pay special attention to the stability
waiting time for operating voltage and oscillation.
Note that the OSC3 clock cannot be used as the system clock in the halver mode. When the low-speed
operation voltage regulator is in the halver mode, return it to the normal mode before switching the
operating voltage.

OSC1 → OSC3

1. Set VDC2 to "0". (low-speed operation voltage regulator: halver mode → normal mode)

2. Set VDC1 to "1". (high-speed operation voltage regulator: off → on)

3. Set VDC0 to "1". (internal logic operating voltage: V

4. Wait 2.5 msec or more.

5. Set OSCC to "1". (OSC3 oscillation: off → on)

6. Wait 5 msec or more.

7. Set CLKCHG to "1". (CPU clock: OSC1 → OSC3)

OSC3 → OSC1

1. Set CLKCHG to "0". (CPU clock: OSC3 → OSC1)

2. Set OSCC to "0". (OSC3 oscillation: on → off)

3. Set VDC0 to "0". (internal logic operating voltage: V

4. Set the halver mode if necessary.

D1L (VDC0 = "0", VDC1 = "0")
D3 (VDC0 = "1", VDC1 = "1")

D1L → VD3)

D3 → VD1L)

Refer to Section 4.2, "Power Control", for the halver mode.

4.4.5 Clock frequency and instruction execution time

Table 4.4.5.1 shows the instruction execution time according to each frequency of the system clock.

Table 4.4.5.1 Clock frequency and instruction execution time

Clock frequency

OSC1: 32.768 kHz
OSC3: 1.1 MHz
OSC3: 4 MHz

1-cycle instruction 2-cycle instruction 3-cycle instruction

Instruction execution time (µsec)

61 122 183

1.8 3.6 5.5

0.5 1 1.5

34 EPSON S1C63666 TECHNICAL MANUAL

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Oscillation Circuit)

4.4.6 I/O memory of oscillation circuit

Table 4.4.6.1 shows the I/O address and the control bits for the oscillation circuit.

Table 4.4.6.1 Control bits of oscillation circuit

Address Comment

VDC3 VDC2 VDC1 VDC0

FF00H

CLKCHG OSCC 0 0

FF01H

*1 Initial value at initial reset
*2 Not set in the circuit
*3 Constantly "0" when being read

VDC0: Internal logic system power switching register (FF00H•D0)

It is used to switch the operating voltage for the CPU and internal circuit.

Register

D3 D2

R/W

R/W R

D1 D0 Name Init

VDC3

VDC2

VDC1

VDC0

CLKCHG

OSCC

∗

3

0

∗

3

0

–
–

∗1

0

1/2V
1/2V

0
0
0
0
0

∗

2

∗

2

10

DD

V

DD

DD

V

DD

On

Off

D3

D1L

V

V

OSC3OnOSC1

Off

LCD system voltage regulator power source switch
Low-speed operation voltage regulator power source switch
High-speed operation voltage regulator on/off
Logic system power source switch
CPU clock switch
OSC3 oscillation On/Off
Unused
Unused

When "1" is written: V
When "0" is written: V

D3 (for OSC3 operation)
D1L (for OSC1 operation)

Reading: Valid

When "1" is written to VDC0, the internal operating voltage is switched to V

D3. After switching to VD3,

the OSC3 oscillation can be started.
When the low-speed operation voltage regulator is in the halver mode, return it to the normal mode
before switching to V
When "0" is written to VDC0, the internal operating voltage is switched to V
before switching to V

D3.

D1L. Stop the OSC3 oscillation

D1L.

At initial reset, this register is set to "0".

OSCC: OSC3 oscillation control register (FF01H•D2)

Turns the OSC3 oscillation circuit on and off.

When "1" is written: OSC3 oscillation On
When "0" is written: OSC3 oscillation Off

Reading: Valid

When it is necessary to operate the CPU at high speed, set OSCC to "1". At other times, set it to "0" to
reduce current consumption. Furthermore, it is necessary to switch the operating voltage when turning
the OSC3 oscillation circuit on and off.
At initial reset, this register is set to "0".

CLKCHG: CPU system clock switching register (FF01H•D3)

The CPU's operation clock is selected with this register.

When "1" is written: OSC3 clock is selected
When "0" is written: OSC1 clock is selected

Reading: Valid

When the CPU clock is to be OSC3, set CLKCHG to "1"; for OSC1, set CLKCHG to "0".
After turning the OSC3 oscillation on (OSCC = "1"), switching of the clock should be done after waiting 5
msec or more.
When VDC0 = "0" and OSCC = "0" (OSC3 oscillation is off), setting of CLKCHG = "1" becomes invalid
and switching to OSC3 is not performed. Furthermore, do not switch the CPU clock to OSC3 in the halver
mode.
At initial reset, this register is set to "0".

S1C63666 TECHNICAL MANUAL EPSON 35

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Oscillation Circuit)

4.4.7 Programming notes

(1) When switching the CPU system clock from OSC1 to OSC3, first set the operating voltage for high-

speed operation (V
When switching from OSC3 to OSC1, set the operating voltage for low-speed operation (V
switching to OSC1 and turning the OSC3 oscillation off.

(2) It takes at least 5 msec from the time the OSC3 oscillation circuit goes on until the oscillation stabi-

lizes. Consequently, when switching the CPU operation clock from OSC1 to OSC3, do this after a
minimum of 5 msec have elapsed since the OSC3 oscillation went on.
Further, the oscillation stabilization time varies depending on the external oscillator characteristics
and conditions of use, so allow ample margin when setting the wait time.

(3) When switching the clock form OSC3 to OSC1, use a separate instruction for switching the OSC3

oscillation off. An error in the CPU operation can result if this processing is performed at the same
time by the one instruction.

(4) When the low-speed operation voltage regulator is in the halver mode (VDC2 = "1"), the system can

be operated only in low-speed using the OSC1 clock. Do not switch the system clock to OSC3.

(5) Do not switch the operating voltage to V

more, do not stop the high-speed operating voltage regulator.

D3). After that maintain 2.5 msec or more, and then turn the OSC3 oscillation on.

D1L) after

D1L while the CPU is operating with the OSC3 clock. Further-

36 EPSON S1C63666 TECHNICAL MANUAL

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports)

4.5 Input Ports (K00–K03 and K10–K13)

4.5.1 Configuration of input ports

The S1C63666 has eight bits of general-purpose input ports (K00–K03, K10–K13). Each input port termi­nal provides an internal pull-down resistor that can be enabled by mask option.
Figure 4.5.1.1 shows the configuration of input port.

V

DD

Interrupt
request

Kxx

Data bus

Address

V

SS

Mask option

Fig. 4.5.1.1 Configuration of input port

Selection of "With pull-down resistor" with the mask option suits input from the push switch, key matrix,
and so forth. When "Gate direct" is selected, the port can be used for slide switch input and interfacing
with other LSIs.
The K00 and K01 input ports can also be used as the Run/Stop and Lap direct inputs for the stopwatch
timer, and the K13 port can also be used as the event counter input for the programmable timer.

4.5.2 Interrupt function

All eight bits of the input ports (K00–K03, K10–K13) provide the interrupt function. The conditions for
issuing an interrupt can be set by the software. Further, whether to mask the interrupt function can be
selected by the software.
Figure 4.5.2.1 shows the configuration of K00–K03 (K10–K13) interrupt circuit.

K00, 10

Data bus

Address

Input comparison
register (KCP00, 10)

Interrupt selection
register (SIK00, 10)

K01, 11

K02, 12

K03, 13

Address

Address

Interrupt factor
flag (IK0, 1)

Address

Interrupt mask
register (EIK0, 1)

Interrupt
request

Address

Fig. 4.5.2.1 Input interrupt circuit configuration

S1C63666 TECHNICAL MANUAL EPSON 37

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports)

The interrupt selection register (SIK) and input comparison register (KCP) are individually set for the
input ports K00–K03 and K10–K13, and can specify the terminals for generating interrupt and interrupt
timing.
The interrupt selection registers (SIK00–SIK03, SIK10–SIK13) select what input of K00–K03 and K10–K13
to use for the interrupt. Writing "1" into an interrupt selection register incorporates that input port into
the interrupt generation conditions. The changing the input port where the interrupt selection register
has been set to "0" does not affect the generation of the interrupt.
The input interrupt timing can select that the interrupt be generated at the rising edge of the input or that
it be generated at the falling edge according to the set value of the input comparison registers (KCP00–
KCP03, KCP10–KCP13).
By setting these two conditions, the interrupt for K00–K03 or K10–K13 is generated when input ports in
which an interrupt has been enabled by the input selection registers and the contents of the input com­parison registers have been changed from matching to no matching.
The interrupt mask registers (EIK0, EIK1) enable the interrupt mask to be selected for K00–K03 and K10–
K13.
When the interrupt is generated, the interrupt factor flag (IK0, IK1) is set to "1".
Figure 4.5.2.2 shows an example of an interrupt for K00–K03.

Interrupt selection register

SIK031SIK021SIK011SIK00

0

With the above setting, the interrupt of K00–K03 is generated under the following condition:

Input comparison register

KCP031KCP020KCP011KCP00

0

Input port

K031K020K011K00

(1)

0

(Initial value)

K031K020K011K00

(2)

1

K030K020K011K00

(3)

K030K021K011K00

(4)

1

1

Interrupt generation

Because K00 interrupt is set to disable, interrupt will be
generated when no matching occurs between the
contents of the 3 bits K01–K03 and the 3 bits input
comparison register KCP01–KCP03.

Fig. 4.5.2.2 Example of interrupt of K00–K03

K00 interrupt is disabled by the interrupt selection register (SIK00), so that an interrupt does not occur at
(2). At (3), K03 changes to "0"; the data of the terminals that are interrupt enabled no longer match the
data of the input comparison registers, so that interrupt occurs. As already explained, the condition for
the interrupt to occur is the change in the port data and contents of the input comparison registers from
matching to no matching. Hence, in (4), when the no matching status changes to another no matching
status, an interrupt does not occur. Further, terminals that have been masked for interrupt do not affect
the conditions for interrupt generation.

4.5.3 Mask option

Internal pull-down resistor can be selected for each of the eight bits of the input ports (K00–K03, K10–
K13) with the input port mask option.
When "Gate direct" is selected, take care that the floating status does not occur for the input. Select "With
pull-down resistor" for input ports that are not being used.

38 EPSON S1C63666 TECHNICAL MANUAL

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports)

4.5.4 I/O memory of input ports

Table 4.5.4.1 shows the I/O addresses and the control bits for the input ports.

Table 4.5.4.1 Control bits of input ports

Address Comment

SIK03 SIK02 SIK01 SIK00

FF20H

FF21H

KCP03 KCP02 KCP01 KCP00

FF22H

SIK13 SIK12 SIK11 SIK10

FF24H

FF25H

KCP13 KCP12 KCP11 KCP10

FF26H

FFE3H

FFE4H

FFF3H

FFF4H

*1 Initial value at initial reset
*2 Not set in the circuit
*3 Constantly "0" when being read

Register

D3 D2

D1 D0 Name Init

R/W

K03 K02 K01 K00

R

KCP03
KCP02

R/W

KCP01
KCP00

R/W

K13 K12 K11 K10

R

KCP13
KCP12

R/W

000EIK0

RR/W

000EIK1

RR/W

000IK0

RR/W

000IK1

RR/W

KCP11
KCP10
0
0
0

0
0
0

0
0
0

0
0
0

SIK03

SIK02

SIK01

SIK00

K03
K02
K01
K00

SIK13

SIK12

SIK11

SIK10

K13
K12
K11
K10

EIK0

EIK1

IK0

IK1

∗1

0
0
0
0

∗

2

–

∗

2

–

∗

2

–

∗

2

–

1
1
1
1
0
0
0
0

∗

2

–

∗

2

–

∗

2

–

∗

2

–

1
1
1
1

∗

3

∗

2

–

∗

3

∗

2

–

∗

3

∗

2

–

0 Enable Mask

∗

3

∗

2

–

∗

3

∗

2

–

∗

3

∗

2

–

0 Enable Mask

∗

3

∗

2

–

∗

3

∗

2

–

∗

3

∗

2

–

0

∗

3

∗

2

–

∗

3

∗

2

–

∗

3

∗

2

–

0

10

Enable

Disable

Enable

Disable

Enable

Disable

Enable

Disable

High

Low

High

Low

High

Low

High

Low

Enable

Disable

Enable

Disable

Enable

Disable

Enable

Disable

High

Low

High

Low

High

Low

High

Low

(R)

(R)

Yes

No

(W)

(W)

Reset

Invalid

(R)

(R)

Yes

No

(W)

(W)

Reset

Invalid

K00–K03 interrupt selection register

K00–K03 input port data

K00–K03 input comparison register

K10–K13 interrupt selection register

K10–K13 input port data

K10–K13 input comparison register

Unused
Unused
Unused
Interrupt mask register (K00–K03)
Unused
Unused
Unused
Interrupt mask register (K10–K13)
Unused
Unused
Unused
Interrupt factor flag (K00–K03)
Unused
Unused
Unused
Interrupt factor flag (K10–K13)

K00–K03: K0 port input port data (FF21H)
K10–K13: K1 port input port data (FF25H)

Input data of the input port terminals can be read with these registers.

When "1" is read: High level
When "0" is read: Low level

Writing: Invalid

The reading is "1" when the terminal voltage of the eight bits of the input ports (K00–K03, K10–K13) goes
high (V

DD), and "0" when the voltage goes low (VSS).

These bits are dedicated for reading, so writing cannot be done.

S1C63666 TECHNICAL MANUAL EPSON 39

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports)

SIK00–SIK03: K0 port interrupt selection register (FF20H)
SIK10–SIK13: K1 port interrupt selection register (FF24H)

Selects the ports to be used for the K00–K03 and K10–K13 input interrupts.

When "1" is written: Enable
When "0" is written: Disable

Reading: Valid

Enables the interrupt for the input ports (K00–K03, K10–K13) for which "1" has been written into the
interrupt selection registers (SIK00–SIK03, SIK10–SIK13). The input port set for "0" does not affect the
interrupt generation condition.
At initial reset, these registers are set to "0".

KCP00–KCP03: K0 port input comparison register (FF22H)
KCP10–KCP13: K1 port input comparison register (FF26H)

Interrupt conditions for terminals K00–K03 and K10–K13 can be set with these registers.

When "1" is written: Falling edge
When "0" is written: Rising edge

Reading: Valid

The interrupt conditions can be set for the rising or falling edge of input for each of the eight bits (K00–
K03 and K10–K13), through the input comparison registers (KCP00–KCP03 and KCP10–KCP13).
For KCP00–KCP03, a comparison is done only with the ports that are enabled by the interrupt among
K00–K03 by means of the SIK00–SIK03 registers. For KCP10–KCP13, a comparison is done only with the
ports that are enabled by the interrupt among K10–K13 by means of the SIK10–SIK13 registers.
At initial reset, these registers are set to "1".

EIK0: K0 input interrupt mask register (FFE3H•D0)
EIK1: K1 input interrupt mask register (FFE4H•D0)

Masking the interrupt of the input port can be selected with these registers.

When "1" is written: Enable
When "0" is written: Mask

Reading: Valid

With these registers, masking of the input port interrupt can be selected for each of the two systems (K00–
K03, K10–K13).
At initial reset, these registers are set to "0".

IK0: K0 input interrupt factor flag (FFF3H•D0)
IK1: K1 input interrupt factor flag (FFF4H•D0)

These flags indicate the occurrence of input interrupt.

When "1" is read: Interrupt has occurred
When "0" is read: Interrupt has not occurred

When "1" is written: Flag is reset
When "0" is written: Invalid

The interrupt factor flags IK0 and IK1 are associated with K00–K03 and K10–K13, respectively. From the
status of these flags, the software can decide whether an input interrupt has occurred.
The interrupt factor flag is set to "1" when the interrupt condition is established regardless of the interrupt
mask register setting. However, the interrupt does not occur to the CPU when the interrupt is masked.
These flags are reset to "0" by writing "1" to them.
After an interrupt occurs, the same interrupt will occur again if the interrupt enabled state (I flag = "1") is
set or the RETI instruction is executed unless the interrupt factor flag is reset. Therefore, be sure to reset
(write "1" to) the interrupt factor flag in the interrupt service routine before shifting to the interrupt
enabled state.
At initial reset, these flags are set to "0".

40 EPSON S1C63666 TECHNICAL MANUAL

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports)

4.5.5 Programming notes

(1) When input ports are changed from high to low by pull-down resistors, the fall of the waveform is

delayed on account of the time constant of the pull-down resistor and input gate capacitance. Hence,
when fetching input ports, set an appropriate waiting time.
Particular care needs to be taken of the key scan during key matrix configuration.
Make this waiting time the amount of time or more calculated by the following expression.
10 × C × R

C: terminal capacitance 5 pF + parasitic capacitance ? pF
R: pull-down resistance 375 kΩ (Max.)

(2) After an interrupt occurs, the same interrupt will occur again if the interrupt enabled state (I flag =

"1") is set or the RETI instruction is executed unless the interrupt factor flag is reset. Therefore, be sure
to reset (write "1" to) the interrupt factor flag in the interrupt service routine before shifting to the
interrupt enabled state.

S1C63666 TECHNICAL MANUAL EPSON 41

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports)

4.6 Output Ports (R00–R03 and R10–R13)

4.6.1 Configuration of output ports

The S1C63666 has eight bits of general output ports.
Output specifications of the output ports can be selected individually with the mask option. Two kinds of
output specifications are available: complementary output and P-channel open drain output.
Figure 4.6.1.1 shows the configuration of the output port.

V

Address

High impedance

control register

DD

Data bus

Data register

Address

Mask option

V

Rxx

SS

Fig. 4.6.1.1 Configuration of output port

The R02 and R03 output terminals are shared with special output terminals (TOUT, FOUT), and this
function is selected by the software.
At initial reset, these are all set to the general purpose output port.
Table 4.6.1.1 shows the setting of the output terminals by function selection.

Table 4.6.1.1 Function setting of output terminals

Terminal

name

R00
R01
R02
R03

R10–R13

Terminal status

at initial reset

R00 (Low output)
R01 (Low output)
R02 (Low output)
R03 (Low output)
R10–R13 (Low output)

Special output

TOUT FOUT

R00 R00
R01 R01

TOUT

FOUT

R10–R13 R10–R13

When using the output port (R02, R03) as the special output port, the data register must be fixed at "1"
and the high impedance control register must be fixed at "0" (data output).

4.6.2 Mask option

Output specifications of the output ports are selected by mask option.
Either complementary output or P-channel open drain output can be selected individually (in 1-bit units).
However, when P-channel open drain output is selected, do not apply a voltage exceeding the power
supply voltage to the output port.

42 EPSON S1C63666 TECHNICAL MANUAL

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports)

4.6.3 High impedance control

The output ports can be set into a high impedance status. This control is done using the high impedance
control registers.
The high impedance control registers are provided to correspond with the output ports as shown below.

High impedance control register Corresponding output port

R00HIZ R00 (1 bit)
R01HIZ R01 (1 bit)
R02HIZ R02 (1 bit)
R03HIZ R03 (1 bit)

R1HIZ R10–R13 (4 bits)

When "1" is written to the high impedance control register, the corresponding output port terminal goes
into high impedance status. When "0" is written, the port outputs a signal according to the data register.

4.6.4 Special output

In addition to the regular DC output, special output can be selected for the output ports R02 and R03 as
shown in Table 4.6.4.1 with the software.
Figure 4.6.4.1 shows the configuration of the R02 and R03 output ports.

Table 4.6.4.1 Special output

Terminal

R03
R02

Special output

FOUT
TOUT

Output control register

FOUTE
PTOUT

FOUT

Register

FOUTE

R03
(FOUT)

R02
(TOUT)

Data bus

Register

R03

Register

R03HIZ

TOUT

Register

PTOUT

Register

R02

Register

R02HIZ

Fig. 4.6.4.1 Configuration of R02 and R03 output ports

At initial reset, the output port data register is set to "0" and the high impedance control register is set to
"0". Consequently, the output terminal goes low (VSS).
When using the output port (R02, R03) as the special output port, fix the data register (R02, R03) at "1"
and the high impedance control register (R02HIZ, R03HIZ) at "0" (data output). The respective signal
should be turned on and off using the special output control register.

Note: • Be aware that the output terminal is fixed at a low (VSS) level the same as the DC output if "0" is

written to the R02 and R03 registers when the special output has been selected.

• Be aware that the output terminal shifts into high impedance status when "1" is written to the
high impedance control register (R02HIZ, R03HIZ).

S1C63666 TECHNICAL MANUAL EPSON 43

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports)

•TOUT (R02)

The R02 terminal can output a TOUT signal.
The TOUT signal is the clock that is output from the programmable timer, and can be used to provide
a clock signal to an external device.
To output the TOUT signal, fix the R02 register at "1" and the R02HIZ register at "0", and turn the
signal on and off using the PTOUT register. It is, however, necessary to control the programmable
timer.
Refer to Section 4.11, "Programmable Timer" for details of the programmable timer.

Note: A hazard may occur when the TOUT signal is turned on and off.

Figure 4.6.4.2 shows the output waveform of the TOUT signal.

R02HIZ register

R02 register

PTOUT register

TOUT output

Fix at "0"

Fix at "1"

"1""0" "0"

Fig. 4.6.4.2 Output waveform of TOUT signal

• FOUT (R03)

The R03 terminal can output an FOUT signal.
The FOUT signal is a clock (f
f

OSC1 clock has divided in the internal circuit, and can be used to provide a clock signal to an external

device.
To output the FOUT signal, fix the R03 register at "1" and the R03HIZ register at "0", and turn the
signal on and off using the FOUTE register.
The frequency of the output clock may be selected from among 4 types shown in Table 4.6.4.2 by
setting the FOFQ0 and FOFQ1 registers.

When fOSC3 is selected for the FOUT signal frequency, it is necessary to control the OSC3 oscillation
circuit before output.
Refer to Section 4.4, "Oscillation Circuit", for the control and notes.

OSC1 or fOSC3) that is output from the oscillation circuit or a clock that the

Table 4.6.4.2 FOUT clock frequency

FOFQ1

fOSC1: Clock that is output from the OSC1 oscillation circuit
fOSC3: Clock that is output from the OSC3 oscillation circuit

FOFQ0

1
1
0
0

1
0
1
0

Clock frequency

f

OSC3

f

OSC1

f

OSC1

× 1/8

f

OSC1

× 1/64

Note: A hazard may occur when the FOUT signal is turned on and off.

Figure 4.6.4.3 shows the output waveform of the FOUT signal.

R03HIZ register

R03 register

FOUTE register

FOUT output

Fix at "0"

Fix at "1"

"1""0" "0"

Fig. 4.6.4.3 Output waveform of FOUT signal

44 EPSON S1C63666 TECHNICAL MANUAL

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports)

4.6.5 I/O memory of output ports

Table 4.6.5.1 shows the I/O addresses and control bits for the output ports.

Table 4.6.5.1 Control bits of output ports

Address Comment

FOUTE SWDIR FOFQ1 FOFQ0

FF06H

R03HIZ R02HIZ R01HIZ R00HIZ

FF30H

FF31H

FF32H

FF33H

FFC1H

*1 Initial value at initial reset
*2 Not set in the circuit
*3 Constantly "0" when being read

Register

D3 D2

R03 R02 R01 R00

000R1HIZ

R13 R12 R11 R10

0 CHSEL1 CHSEL0 PTOUT

RR/W

D1 D0 Name Init

FOUTE
SWDIR

R/W

R/W

R/W

RR/W

R/W

FOFQ1
FOFQ0
R03HIZ
R02HIZ
R01HIZ
R00HIZ

0
0
0

R1HIZ

0
CHSEL1
CHSEL0

PTOUT

∗1

0
0

0
0
0
0
0
0

R03

0

R02

0

R01

0

R00

0

∗

3

∗

2

–

∗

3

∗

2

–

∗

3

∗

2

–

0Hi-ZOutput

R13

0

R12

0

R11

0

R10

0

∗

3

∗

2

–

0
0
0OnOff

10

Enable Disable

Hi-Z

Output

Hi-Z

Output

Hi-Z

Output

Hi-Z

Output

High

Low

High

Low

High

Low

High

Low

High

Low

High

Low

High

Low

High

Low

FOUT output enable
Stopwatch direct input switch
0: K00=Run/Stop, K01=Lap 1: K00=Lap, K01=Run/Stop

FOUT
frequency
selection

R03 (FOUTE=0)/FOUT (FOUTE=1) Hi-Z control
R02 (PTOUT=0)/TOUT (PTOUT=1) Hi-Z control
R01 Hi-Z control
R00 Hi-Z control
R03

output port data (

R02

output port data (

R01

output port data

R00

output port data
Unused
Unused
Unused
R10–R13 Hi-Z control

R10–R13 output port data

Unused
TOUT output
selection
TOUT output control

[FOFQ1, 0]
Frequency

FOUTE=0
PTOUT=0

[CHSEL1,0]
Timer

0

OSC1

/641f

OSC1

/82f

FOUT
TOUT

OSC1

is used.
is used.

f

) Fix at "1" when
) Fix at "1" when

0

Timer 01Timer 12Timer 2

f

3

OSC3

R00HIZ–R03HIZ: R0 port high impedance control register (FF30H)
R1HIZ: R1 port high impedance control register (FF32H•D0)

Controls high impedance output of the output port.

When "1" is written: High impedance
When "0" is written: Data output

Reading: Valid

By writing "0" to the high impedance control register, the corresponding output terminal outputs accord­ing to the data register. When "1" is written, it shifts into high impedance status.
When the output ports R02 and R03 are used for special output (TOUT, FOUT), fix the R02HIZ register
and the R03HIZ register at "0" (data output).
At initial reset, these registers are set to "0".

S1C63666 TECHNICAL MANUAL EPSON 45

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports)

R00–R03: R0 output port data register (FF31H)
R10–R13: R1 output port data register (FF33H)

Set the output data for the output ports.

When "1" is written: High level output
When "0" is written: Low level output

Reading: Valid

The output port terminals output the data written in the corresponding data registers without changing
it. When "1" is written to the register, the output port terminal goes high (V
the output port terminal goes low (V

SS).

DD), and when "0" is written,

When the output ports R02 and R03 are used for special output (TOUT, FOUT), fix the R02 register and
the R03 register at "1".
At initial reset, these registers are all set to "0".

FOUTE: FOUT output control register (FF06H•D3)

Controls the FOUT output.

When "1" is written: FOUT output On
When "0" is written: FOUT output Off

Reading: Valid

By writing "1" to the FOUTE register when the R03 register has been set to "1" and the R03HIZ register
has been set to "0", the FOUT signal is output from the R03 terminal. When "0" is written, the R03 termi­nal goes low (V

SS).

When using the R03 output port for DC output, fix this register at "0".
At initial reset, this register is set to "0".

FOFQ0, FOFQ1: FOUT frequency selection register (FF06H•D0, D1)

Selects a frequency of the FOUT signal.

Table 4.6.5.2 FOUT clock frequency

FOFQ1

FOFQ0

1
1
0
0

1
0
1
0

Clock frequency

OSC3

f
f

OSC1

f

OSC1

× 1/8

OSC1

× 1/64

f

At initial reset, this register is set to "0".

PTOUT: TOUT output control register (FFC1H•D0)

Controls the TOUT output.

When "1" is written: TOUT output On
When "0" is written: TOUT output Off

Reading: Valid

By writing "1" to the PTOUT register when the R02 register has been set to "1" and the R02HIZ register
has been set to "0", the TOUT signal is output from the R02 terminal. When "0" is written, the R02 termi­nal goes high (V

DD).

When using the R02 output port for DC output, fix this register at "0".
At initial reset, this register is set to "0".

46 EPSON S1C63666 TECHNICAL MANUAL

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports)

4.6.6 Programming notes

(1) When using the output port (R02, R03) as the special output port, fix the data register (R02, R03) at "1"

and the high impedance control register (R02HIZ, R03HIZ) at "0" (data output).
Be aware that the output terminal is fixed at a low (V
written to the R02 and R03 registers when the special output has been selected.
Be aware that the output terminal shifts into high impedance status when "1" is written to the high
impedance control register (R02HIZ, R03HIZ).

(2) A hazard may occur when the FOUT signal and the TOUT signal are turned on and off.

SS) level the same as the DC output if "0" is

(3) When f

OSC3 is selected for the FOUT signal frequency, it is necessary to control the OSC3 oscillation

circuit before output.
Refer to Section 4.4, "Oscillation Circuit", for the control and notes.

S1C63666 TECHNICAL MANUAL EPSON 47

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (I/O Ports)

4.7 I/O Ports (P00–P03 and P10–P13)

4.7.1 Configuration of I/O ports

The S1C63666 has eight bits of general-purpose I/O ports. Figure 4.7.1.1 shows the configuration of the I/
O port.

Pull-down control

Address

register (PUL)

Address

Address

Data bus

Address

Data

register

I/O control

register (IOC)

Pxx

Mask
option

VSS

Fig. 4.7.1.1 Configuration of I/O port

The I/O port terminals P10 to P13 are shared with the serial interface input/output terminals. The
software can select the function to be used.
At initial reset, these terminals are all set to the I/O port.
Table 4.7.1.1 shows the setting of the input/output terminals by function selection.

Table 4.7.1.1 Function setting of input/output terminals

Terminal

P00–P03

P10
P11
P12
P13

∗ When "with pull-down resistor" is selected by the mask option

(high impedance when "gate direct" is set)

Terminal status

at initial reset

P00–P03 (Input & pull-down ∗)
P10 (Input & pull-down ∗)
P11 (Input & pull-down ∗)
P12 (Input & pull-down ∗)
P13 (Input & pull-down ∗)

Serial I/F

Master Slave

P00–P03 P00–P03

SIN(I) SIN(I)

SOUT(O) SOUT(O)

SCLK(O) SCLK(I)

P13 SRDY(O)

When these ports are used as I/O ports, the ports can be set to either input mode or output mode indi­vidually (in 1-bit unit). Modes can be set by writing data to the I/O control registers.
Refer to Section 4.12, "Serial Interface", for control of the serial interface.

48 EPSON S1C63666 TECHNICAL MANUAL

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (I/O Ports)

4.7.2 Mask option

The output specification of each I/O port during output mode can be selected from either complemen­tary output or P-channel open drain output by mask option. This selection can be done in 1-bit units.
When P-channel open drain output is selected, do not apply a voltage exceeding the power supply
voltage to the port.

The mask option also permits selection of whether the pull-down resistor is used or not during input
mode. This selection can be done in 1-bit units.
When "without pull-down" during the input mode is selected, take care that the floating status does not
occur.

The pull-down resistor for input mode and output specification (complementary output or P-channel
open drain output) selected by mask option are effective even when I/O ports are used for input/output
of the serial interface.

4.7.3 I/O control registers and input/output mode

Input or output mode can be set for the I/O ports by writing data into the corresponding I/O control
registers IOCxx.

To set the input mode, write "0" to the I/O control register. When an I/O port is set to input mode, it
becomes high impedance status and works as an input port.
However, when the pull-down explained in the following section has been set by software, the input line
is pulled down only during this input mode.

To set the output mode, write "1" is to the I/O control register. When an I/O port is set to output mode, it
works as an output port, it outputs a high level (V
(V

SS) when the port output data is "0".

If perform the read out in each mode; when output mode, the register value is read out, and when input
mode, the port value is read out.

At initial reset, the I/O control registers are set to "0", and the I/O ports enter the input mode.

The I/O control registers of the ports that are set as input/output for the serial interface can be used as
general purpose registers that do not affect the I/O control. (See Table 4.7.1.1.)

DD) when the port output data is "1", and a low level

4.7.4 Pull-down during input mode

A pull-down resistor that operates during the input mode is built into each I/O port of the S1C63666.
Mask option can set the use or non-use of this pull-down.

The pull-down resistor becomes effective by writing "1" to the pull-down control register PULxx that
corresponds to each port, and the input line is pulled down during the input mode. When "0" has been
written, no pull-down is done.
At initial reset, the pull-down control registers are set to "1".

The pull-down control registers of the ports in which "gate direct" has been selected can be used as
general purpose registers.
Even when "with pull-down" has been selected, the pull-down control registers of the ports, that are set
as output for the serial interface, can be used as general purpose registers that do not affect the pull-down
control. (See Table 4.7.1.1.)
The pull-down control registers of the port, that are set as input for the serial interface, function the same
as the I/O port.

S1C63666 TECHNICAL MANUAL EPSON 49

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (I/O Ports)

4.7.5 I/O memory of I/O ports

Table 4.7.5.1 shows the I/O addresses and the control bits for the I/O ports.

Table 4.7.5.1 Control bits of I/O ports

Address Comment

IOC03 IOC02 IOC01 IOC00

FF40H

PUL03 PUL02 PUL01 PUL00

FF41H

P03 P02 P01 P00

FF42H

IOC13 IOC12 IOC11 IOC10

FF44H

PUL13 PUL12 PUL11 PUL10

FF45H

P13 P12 P11 P10

FF46H

FF70H

*1 Initial value at initial reset
*2 Not set in the circuit
*3 Constantly "0" when being read

Register

D3 D2

D1 D0 Name Init

IOC03
IOC02

R/W

IOC01

IOC00
PUL03
PUL02

R/W

PUL01
PUL00

P03
P02

R/W

P01
P00

IOC13

IOC12

IOC11

R/W

IOC10

PUL13

PUL12

PUL11

R/W

PUL10

P13

P12

P11

R/W

P10

0

0 ESOUT SCTRG ESIF

ESOUT
SCTRG

RR/W

ESIF

∗1

10

0

Output

Input

0

Output

Input
0
0
1
1
1
1

–
–
–
–

0

0

Output
Output

On
On
On
On

∗

2

High

∗

2

High

∗

2

High

∗

2

High

Output

Output

P00–P03 I/O control register

Input

Input

Off
Off

P00–P03 pull-down control register

Off

Off
Low
Low

P00–P03 I/O port data

Low
Low

Input

P13 I/O control register

functions as a general-purpose register when SIF (slave) is selected

Input

P12 I/O control register (ESIF=0)
functions as a general-purpose register when SIF is selected

0

P11 I/O control register (ESIF=0)

Input

Output

functions as a general-purpose register when SIF is selected

0

P10 I/O control register (ESIF=0)

Input

Output

functions as a general-purpose register when SIF is selected

1

On

1

On

1

P13 pull-down control register

functions as a general-purpose register when SIF (slave) is selected

Off

P12 pull-down control register (ESIF=0)

functions as a general-purpose register when SIF (master) is selected
SCLK (I) pull-down control register when SIF (slave) is selected

Off

P11 pull-down control register (ESIF=0)

Off

On

functions as a general-purpose register when SIF is selected

1

P10 pull-down control register (ESIF=0)

Off

On

SIN pull-down control register

∗

–

–

2

∗

2

High

High

Low

P13 I/O port data

functions as a general-purpose register when SIF (slave) is selected

Low

P12 I/O port data (ESIF=0)
functions as a general-purpose register when SIF is selected

∗

–

2

High

Low

P11 I/O port data (ESIF=0)
functions as a general-purpose register when SIF is selected

∗

–

2

High

Low

P10 I/O port data (ESIF=0)
functions as a general-purpose register when SIF is selected

∗

3

∗

2

–

0
0

0

Enable
Trigger

Run

SIF

Unused
SOUT enable

Disable

Serial I/F clock trigger (writing)

Invalid

Serial I/F clock status (reading)

Stop

Serial I/F enable (P1 port function selection)

I/O

when SIF is selected

50 EPSON S1C63666 TECHNICAL MANUAL

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (I/O Ports)

(1) Selection of port function

ESIF: Serial interface enable register (FF70H•D0)

Selects function for P10–P13.

When "1" is written: Serial interface input/output port
When "0" is written: I/O port

Reading: Valid

When using the serial interface, write "1" to this register and when P10–P13 are used as the I/O port,
write "0". The configuration of the terminals within P10–P13 that are used for the serial interface is
decided by the mode selected with the SCS1 and SCS0 registers (see Section 4.12).
In the slave mode, all the P10–P13 ports are set to the serial interface input/output port. In the master
mode, P10–P12 are set to the serial interface input/output port and P13 can be used as the I/O port.
Furthermore, when the SOUT terminal is disabled (ESOUT = "0"), P11 can be used as the I/O port.
At initial reset, this register is set to "0".

(2) I/O port control

P00–P03: P0 I/O port data register (FF42H)
P10–P13: P1 I/O port data register (FF46H)

I/O port data can be read and output data can be set through these registers.

• When writing data

When "1" is written: High level
When "0" is written: Low level

When an I/O port is set to the output mode, the written data is output unchanged from the I/O port
terminal. When "1" is written as the port data, the port terminal goes high (V
the terminal goes low (V

SS).

DD), and when "0" is written,

Port data can be written also in the input mode.

• When reading data

When "1" is read: High level
When "0" is read: Low level

The terminal voltage level of the I/O port is read out. When the I/O port is in the input mode the voltage
level being input to the port terminal can be read out; in the output mode the register value can be read.
When the terminal voltage is high (V
voltage is low (V

SS) the data is "0".

DD) the port data that can be read is "1", and when the terminal

When "with pull-down resistor" has been selected with the mask option and the PUL register is set to "1",
the built-in pull-down resistor goes on during input mode, so that the I/O port terminal is pulled down.

The data registers of the port, which are set for the input/output of the serial interface (P10–P13), become
general-purpose registers that do not affect the input/output.

Note: When in the input mode, I/O ports are changed from high to low by pull-down resistor, the fall of

the waveform is delayed on account of the time constant of the pull-down resistor and input gate
capacitance. Hence, when fetching input ports, set an appropriate wait time.
Particular care needs to be taken of the key scan during key matrix configuration.
Make this waiting time the amount of time or more calculated by the following expression.
10

×

C × R
C: terminal capacitance 5 pF + parasitic capacitance ? pF
R: pull-down resistance 375 k

Ω

(Max.)

S1C63666 TECHNICAL MANUAL EPSON 51

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (I/O Ports)

IOC00–IOC03: P0 port I/O control register (FF40H)
IOC10–IOC13: P1 port I/O control register (FF44H)

The input and output modes of the I/O ports are set with these registers.

When "1" is written: Output mode
When "0" is written: Input mode

Reading: Valid

The input and output modes of the I/O ports are set in 1-bit unit.
Writing "1" to the I/O control register makes the corresponding I/O port enter the output mode, and
writing "0" induces the input mode.
At initial reset, these registers are all set to "0", so the I/O ports are in the input mode.
The I/O control registers of the port, which are set for the input/output of the serial interface (P10–P13),
become general-purpose registers that do not affect the input/output.

PUL00–PUL03: P0 port pull-down control register (FF41H)
PUL10–PUL13: P1 port pull-down control register (FF45H)

The pull-down during the input mode are set with these registers.

When "1" is written: Pull-down On
When "0" is written: Pull-down Off

Reading: Valid

The built-in pull-down resistor which is turned on during input mode is set to enable in 1-bit units. (The
pull-down resistor is included into the ports selected by mask option.)
By writing "1" to the pull-down control register, the corresponding I/O ports are pulled down (during
input mode), while writing "0" disables the pull-down function.
At initial reset, these registers are all set to "1", so the pull-down function is enabled.

The pull-down control registers of the ports in which the pull-down resistor is not included become the
general purpose register. The registers of the ports that are set as output for the serial interface can also be
used as general purpose registers that do not affect the pull-down control.
The pull-down control registers of the port that are set as input for the serial interface function the same
as the I/O port.

4.7.6 Programming note

When in the input mode, I/O ports are changed from high to low by pull-down resistor, the fall of the
waveform is delayed on account of the time constant of the pull-down resistor and input gate capaci­tance. Hence, when fetching input ports, set an appropriate wait time.
Particular care needs to be taken of the key scan during key matrix configuration.
Make this waiting time the amount of time or more calculated by the following expression.
10 × C × R

C: terminal capacitance 5 pF + parasitic capacitance ? pF
R: pull-down resistance 375 kΩ (Max.)

52 EPSON S1C63666 TECHNICAL MANUAL

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)

4.8 LCD Driver (COM0–COM7, SEG0–SEG63)

4.8.1 Configuration of LCD driver

The S1C63666 has 8 common terminals (COM0–COM7) and 64 segment terminals (SEG0–SEG63), so that
it can drive an LCD with a maximum of 512 (64 × 8) segments.
The driving method is 1/4 duty, 1/5 duty or 1/8 duty dynamic drive with three voltages (1/3 bias), V
V

C2 and VC3.

LCD display on/off can be controlled by the software.

4.8.2 Power supply for LCD driving

The power supply for driving LCD can be selected from the internal power supply and an external power
supply.

C1,

When the internal power supply is selected, the LCD drive voltages V

C1–VC3 are generated by the built-in

LCD system voltage circuit. The LCD system voltage circuit is turned on and off using the LPWR register.
When LPWR is set to "1", the LCD system voltage circuit outputs the LCD drive voltages V
LCD driver. The LCD system voltage circuit generates V
generates two other voltages (V

C2 = 2VC1, VC3 = 3VC1) by boosting VC1.

C1 with the voltage regulator built-in, and

C1–VC3 to the

When using an external power supply, select the voltage from the following 3 types and supply the LCD
drive voltage to the V

1) External power supply 1/3 bias (for 4.5 V panel) VDD = V

2) External power supply 1/3 bias (for 3.0 V panel) VDD = V

C1–VC3 terminals.

C2
C3

3) External power supply 1/2 bias (for 3.0 V panel) VDD = VC3, VC1 = VC2 (static drive function is available)

Note that the power control using the LPWR register is necessary even if an external power supply is
used. SEG output ports that are set for DC output by the mask option operate same as the output (R) port
regardless of the power on/off control by the LPWR register.

4.8.3 Control of LCD display and drive waveform

(1)Display on/off control

The S1C63666 incorporates the ALON and ALOFF registers to blink display. When "1" is written to
ALON, all the segments go on, and when "1" is written to ALOFF, all the segments go off. At such a
time, an on waveform or an off waveform is output from SEG terminals. When "0" is written to these
registers, normal display is performed. Furthermore, when "1" is written to both of the ALON and
ALOFF, ALON (all on) has priority over the ALOFF (all off).

(2)Setting of drive duty

In the S1C63666, the drive duty can be set to 1/4, 1/5 or 1/8 using the LDUTY1 and LDUTY0 registers
as shown in Table 4.8.3.1.

Table 4.8.3.1 LCD drive duty setting

LDUTY1

LDUTY0

1
0
0

∗

1
0

Drive duty

1/8
1/5
1/4

Common terminal used

COM0–COM7
COM0–COM4
COM0–COM3

Maximum segment number

512 (64 × 8)
320 (64 × 5)
256 (64 × 4)

Table 4.8.3.2 shows the frame frequency corresponding to the drive duty.

Table 4.8.3.2 Frame frequency

OSC1 oscillation

frequency

32.768 kHz

When 1/8 duty

is selected

32 Hz

When 1/5 duty

is selected

40 Hz

When 1/4 duty

is selected

32 Hz

Figures 4.8.3.1 to 4.8.3.3 show the dynamic drive waveform according to the duty.

S1C63666 TECHNICAL MANUAL EPSON 53

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)

COM0

COM1

COM2

COM3

COM4

V

C3

V

C2

V

C1

V

SS

V

C2

V

C1

COM5

COM6

COM7

SEG0

|

SEG63

• • •

V

C2

V

C1

V

C3

V

C2

V

C1

V

SS

LCD lighting status
COM0

COM1
COM2
COM3

SEG0–63

Not lit
Lit

Frame

Fig. 4.8.3.1 Dynamic drive waveform for 1/4 duty

54 EPSON S1C63666 TECHNICAL MANUAL

COM0

COM1

COM2

COM3

COM4

COM5

COM6

COM7

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)

V

C3

V

C2

V

C1

V

SS

V

C2

V

V
V

V
V
V
V

LCD lighting status

C1

COM0
COM1
COM2
COM3
COM4

C2
C1

C3
C2
C1
SS

SEG0–63

Not lit
Lit

SEG0

|

SEG63

• • •

Frame

Fig. 4.8.3.2 Dynamic drive waveform for 1/5 duty

S1C63666 TECHNICAL MANUAL EPSON 55

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)

COM0

COM1

COM2

COM3

V

C3

V

C2

V

C1

V

SS

COM4

COM5

COM6

COM7

SEG0

|

SEG63

• • •

V

C2

V

C1

V

C3

V

C2

V

C1

V

SS

LCD lighting status
COM0

COM1
COM2
COM3
COM4
COM5
COM6
COM7

SEG0–63

Not lit
Lit

Frame

Fig. 4.8.3.3 Dynamic drive waveform for 1/8 duty

56 EPSON S1C63666 TECHNICAL MANUAL

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)

(3)Static drive

The S1C63666 provides software setting of the LCD static drive. However, this function is available
only when "External power supply 1/2 bias (for 3.0 V panel)" is selected by mask option.
To set in static drive, write "1" to the common output signal control register STCD. Then, by writing
"1" to any one of COM0 to COM7 (display memory) corresponding to the SEG terminal, the SEG
terminal outputs a static on waveform. When all the COM0 to COM7 bits are set to "0", the SEG
terminal outputs a dynamic off waveform.
Figure 4.8.3.4 shows the static drive waveform.

LCD lighting status

COM0
COM1
:
COM7

Not lit

SEG0–63

Lit

:

:

COM
0–7

SEG
0–63

Frame frequency

Fig. 4.8.3.4 Static drive waveform

C3

-V

-V

C2

-V

C1

-V

SS

-V

C3

-V

C2

-V

C1

-V

SS

-V

C3

-V

C2

-V

C1

-V

SS

Note: To use the static drive function, select the "External power supply 1/2 bias (for 3.0 V panel)" mask

option. When an option for using the internal power supply or a 1/3 bias external power supply is
selected, static drive cannot be set using the STCD register.

S1C63666 TECHNICAL MANUAL EPSON 57

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)

4.8.4 Display memory

The display memory is allocated to F000H–F09FH in the data memory area and each data bit can be
allocated to an segment terminal (SEG0–SEG63) by mask option.
When a bit in the display memory is set to "1", the corresponding LCD segment goes on, and when it is
set to "0", the segment goes off.
At initial reset, the data memory content becomes undefined hence, there is need to initialize using the
software.
The display memory has read/write capability, and the addresses that have not been used for LCD
display can be used as general purpose registers.

4.8.5 Segment option

Segment allocation

The LCD driver has a segment decoder built-in, and the data bit (D0–D3) of the optional address in
the display memory area (F000H–F09FH) can be allocated to the optional segment. This makes design
easy by increasing the degree of freedom with which the liquid crystal panel can be designed.
Figure 4.8.5.1 shows an example of the relationship between the LCD segments (on the panel) and the
display memory for the case of 1/4 duty.

Address

F060H
F061H

D3

Data

D2

d
p

D1

c
g

D0

b
f

a
e

SEG10

SEG11

Common 0 Common 1 Common 2

61, D1

(f)

60, D0

(a)

61, D0

(e)

61, D2

(g)

60, D2

(c)

60, D1

(b)

Common 3

60, D3

(d)

61, D3

(p)

Display memory allocation

Pin address allocation

a

f

g

e

c

d

SEG10 SEG11

b

Common 0

p

Common 1

Common 2

Common 3

Fig. 4.8.5.1 Segment allocation

Output specification

1. The segment terminals (SEG0–SEG63) can be selected with the mask option in pairs∗ for either

segment signal output or DC output (V
When DC output is selected, the data corresponding to COM0 of each segment terminal is output.

2. When DC output is selected, either complementary output or N-channel open drain output can be
selected for each terminal with the mask option.

DD and VSS binary output).

∗ The terminal pairs are combination of SEG2 × n and SEG2 × n + 1 (where n is an integer from 0 to 31).

58 EPSON S1C63666 TECHNICAL MANUAL

Pin

■ C■

■

■

■

■ C■

■

■ C■

■

■ C■

■

■ C■

■

■ C■

■

■ C■

■ C■

■ C■

■ C■

■ C■

■ C■

■

name

SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8

SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
SEG32
SEG33
SEG34
SEG35
SEG36
SEG37
SEG38
SEG39
SEG40
SEG41
SEG42
SEG43
SEG44
SEG45
SEG46
SEG47
SEG48
SEG49
SEG50
SEG51
SEG52
SEG53
SEG54
SEG55
SEG56
SEG57
SEG58
SEG59
SEG60
SEG61
SEG62
SEG63

COM0

H L D

<address> H:

COM1

H L D

RAM data high-order address (0–9)

L:

RAM data low-order address (0–F)

D:

Data bit (0–3)

COM2

H L D

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)

Segment option list

Address (F0xx)

COM3

H L D

COM4

H L D

<Output specification> S:

COM5

H L D

COM6

H L D

Segment output

C:

Complementary output

N:

Nch open drain output

COM7 Output specification

H L D

SEG output■ S
DC output
SEG output■ S
DC output■ C■ N
SEG output
DC output■ C■ N
SEG output
DC output■ C■ N
SEG output■ S
DC output■ C■ N
SEG output
DC output■ C■ N
SEG output■ S
DC output
SEG output■ S
DC output■ C■ N
SEG output
DC output■ C■ N
SEG output■ S
DC output
SEG output■ S
DC output■ C■ N
SEG output
DC output■ C■ N
SEG output■ S
DC output
SEG output■ S
DC output■ C■ N
SEG output
DC output■ C■ N
SEG output■ S
DC output
SEG output■ S
DC output■ C■ N
SEG output
DC output■ C■ N
SEG output■ S
DC output
SEG output■ S
DC output■ C■ N
SEG output
DC output■ C■ N
SEG output■ S
DC output
SEG output■ S
DC output■ C■ N
SEG output■ S
DC output
SEG output■ S
DC output
SEG output■ S
DC output■ C■ N
SEG output■ S
DC output
SEG output■ S
DC output
SEG output■ S
DC output■ C■ N
SEG output■ S
DC output
SEG output■ S
DC output■ C■ N
SEG output
DC output■ C■ N

N

S

S

S

N

S

N

S

N

S

N

S

N

S

N

N

N

N

N

N

S

S1C63666 TECHNICAL MANUAL EPSON 59

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)

4.8.6 LCD contrast adjustment

In the S1C63666, the LCD contrast can be adjusted by the software.
It is realized by controlling the voltages V
The contrast can be adjusted to 16 levels as shown in Table 4.8.6.1. V

0.95 to 1.40 V (0.03 V step), and other voltages change according to V

No.

LC3

0

0

1

0

2

0

3

0

4

0

5

0

6

0

7

0

8

1

9

1

10

1

11

1

12

1

13

1

14

1

15

1

∗ Do not set VC1 to 1.16 V or more (LC = 7 or more) when the LCD system

voltage regulator is driven in the halver mode.

C1, VC2 and VC3 output from the LCD system voltage circuit.

Table 4.8.6.1 LCD contrast

LC2

LC1

0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

LC0

VC1 (V)

0

0

0.95

*

0

1

0.98

*

1

0

1.01

*

1

1

1.04

*

0

0

1.07

*

0

1

1.10

*

1

0

1.13

*

1

1

1.16

0

0

1.19

0

1

1.22

1

0

1.25

1

1

1.28

0

0

1.31

0

1

1.34

1

0

1.37

1

1

1.40

C1 is changed within the range from

C1.

Contrast

light

dark

At initial reset, the LC0–LC3 are set to 0000B. The software should initialize the register to get the desired
contrast.
When an external power supply is selected by mask option, the LC0–LC3 register becomes invalid.

60 EPSON S1C63666 TECHNICAL MANUAL

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)

4.8.7 I/O memory of LCD driver

Table 4.8.7.1 shows the I/O addresses and the control bits for the LCD driver. Figure 4.8.7.1 shows the
display memory map.

Table 4.8.7.1 Control bits of LCD driver

Address Comment

LDUTY1 LDUTY0 STCD LPWR

FF60H

FF61H

FF62H

*1 Initial value at initial reset

*2 Not set in the circuit

*3 Constantly "0" when being read

Register

D3 D2

0 ALOFF ALON 0

RRR/W

LC3 LC2 LC1 LC0

D1 D0 Name Init

R/W

R/W

LDUTY1
LDUTY0

STCD

LPWR

∗

3

0
ALOFF

ALON

∗

3

0

LC3
LC2
LC1
LC0

∗1

10
0
0
00StaticOnDynamic

∗

2

–

1

All Off

0

All On

∗

2

–

0
0
0
0

LCD drive duty
switch
LCD drive switch
LCD power On/Off

Off

Unused

Normal

LCD all Off control

Normal

LCD all On control
Unused

LCD contrast adjustment

[LC3–0]
Contrast

[LDUTY1, 0]
Duty

0

Light––15Dark

0

1/411/5

2, 3

1/8

Address

Base

F000H
F010H
F020H
F030H
F040H
F050H
F060H
F070H
F080H
F090H

Low

0123456789ABCDE

Display memory (160 words × 4 bits)

R/W

F

Fig. 4.8.7.1 Display memory map

LPWR: LCD power control (on/off) register (FF60H•D0)

Turns the LCD system voltage circuit on and off.

When "1" is written: On
When "0" is written: Off

Reading: Valid

When "1" is written to the LPWR register, the LCD system voltage circuit goes on and generates the LCD
drive voltage. When "0" is written, all the LCD drive voltages go to V

SS level.

It takes about 100 msec for the LCD drive voltage to stabilize after starting up the LCD system voltage
circuit by writing "1" to the LPWR register.
This control does not affect to SEG terminals that have been set for DC output.
At initial reset, this register is set to "0".

LDUTY0, LDUTY1: LCD drive duty switching register (FF60H•D2, D3)

Selects the LCD drive duty.

Table 4.8.7.2 Drive duty setting

LDUTY1

LDUTY0

1
0
0

∗

1
0

Drive duty

1/8
1/5
1/4

Common terminal used

COM0–COM7
COM0–COM4
COM0–COM3

Maximum segment number

512 (64 × 8)
320 (64 × 5)
256 (64 × 4)

At initial reset, this register is set to "0".

S1C63666 TECHNICAL MANUAL EPSON 61

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)

STCD: LCD drive switch register (FF60H•D1)

Switches the LCD driving method.

When "1" is written: Static drive
When "0" is written: Dynamic drive

Reading: Valid

By writing "1" to STCD, static drive is selected, and dynamic drive is selected when "0" is written.
At initial reset, this register is set to "0".

ALON: LCD all on control register (FF61H•D1)

Displays the all LCD segments on.

When "1" is written: All LCD segments displayed
When "0" is written: Normal display

Reading: Valid

By writing "1" to the ALON register, all the LCD segments go on, and when "0" is written, it returns to
normal display. This function outputs an on waveform to the SEG terminals, and segments not affect the
content of the display memory. ALON has priority over ALOFF.
At initial reset, this register is set to "0".

ALOFF: LCD all OFF control register (FF61H•D2)

Fade outs the all LCD segments.

When "1" is written: All LCD segments fade out
When "0" is written: Normal display

Reading: Valid

By writing "1" to the ALOFF register, all the LCD segments go off, and when "0" is written, it returns to
normal display. This function outputs an off waveform to the SEG terminals, and does not affect the
content of the display memory.
ALON (FF61H•D1) has priority over ALOFF, so all the LCD segments go on when ALON and ALOFF are
set to "1" simultaneously.
At initial reset, this register is set to "1".

LC3–LC0: LCD contrast adjustment register (FF62H)

Adjusts the LCD contrast.

LC3–LC0 = 0000B light

::

LC3–LC0 = 1111B dark

When the LCD drive voltage is supplied from outside by mask option selection, this adjustment becomes
invalid.
At initial reset, LC0–LC3 is set to 0000B.

4.8.8 Programming note

Because at initial reset, the contents of display memory are undefined and LC3–LC0 (LCD contrast) is set
to 0000B, there is need to initialize by the software. Furthermore, take care of the registers LPWR and
ALOFF because these are set so that the display goes off.

62 EPSON S1C63666 TECHNICAL MANUAL

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Clock Timer)

4.9 Clock T imer

4.9.1 Configuration of clock timer

The S1C63666 has a built-in clock timer that uses OSC1 (crystal oscillator) as the source oscillator. The
clock timer is configured of an 8-bit binary counter that serves as the input clock, f
output from the prescaler. Timer data (128–16 Hz and 8–1 Hz) can be read out by the software.
Figure 4.9.1.1 is the block diagram for the clock timer.

Data bus

OSC1 divided clock

OSC1
oscillation circuit
(f

OSC1

)

Clock timer reset signal

Clock timer RUN/STOP signal

Ordinarily, this clock timer is used for all types of timing functions such as clocks.

Divider

Fig. 4.9.1.1 Block diagram for the clock timer

256 Hz

128 Hz–16 Hz

Clock timer

8 Hz–1 Hz

32 Hz, 8 Hz, 2 Hz, 1 Hz

Interrupt

control

Interrupt
request

4.9.2 Data reading and hold function

The 8 bits timer data are allocated to the address FF75H and FF76H.

<FF75H> D0: TM0 = 128 Hz D1: TM1 = 64 Hz D2: TM2 = 32 Hz D3: TM3 = 16 Hz
<FF76H> D0: TM4 = 8 Hz D1: TM5 = 4 Hz D2: TM6 = 2 Hz D3: TM7 = 1 Hz

Since the clock timer data has been allocated to two addresses, a carry is generated from the low-order
data within the count (TM0–TM3: 128–16 Hz) to the high-order data (TM4–TM7: 8–1 Hz). When this carry
is generated between the reading of the low-order data and the high-order data, a content combining the
two does not become the correct value (the low-order data is read as FFH and the high-order data
becomes the value that is counted up 1 from that point).
The high-order data hold function in the S1C63666 is designed to operate to avoid this. This function
temporarily stops the counting up of the high-order data (by carry from the low-order data) at the point
where the low-order data has been read and consequently the time during which the high-order data is
held is the shorter of the two indicated here following.

1. Period until it reads the high-order data.

2. 0.48–1.5 msec (Varies due to the read timing.)

Note: Since the low-order data is not held when the high-order data has previously been read, the low-

order data should be read first.

S1C63666 TECHNICAL MANUAL EPSON 63

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Clock Timer)

4.9.3 Interrupt function

The clock timer can cause interrupts at the falling edge of 32 Hz, 8 Hz, 2 Hz and 1 Hz signals. Software
can set whether to mask any of these frequencies.
Figure 4.9.3.1 is the timing chart of the clock timer.

Address

FF75H

FF76H

Bit

Frequency Clock timer timing chart

D0

128 Hz

D1

D2

D3

D0

D1

D2

D3

32 Hz interrupt request

8 Hz interrupt request

2 Hz interrupt request

1 Hz interrupt request

64 Hz

32 Hz

16 Hz

8 Hz

4 Hz

2 Hz

1 Hz

Fig. 4.9.3.1 Timing chart of clock timer

As shown in Figure 4.9.3.1, interrupt is generated at the falling edge of the frequencies (32 Hz, 8 Hz, 2 Hz,
1 Hz). At this time, the corresponding interrupt factor flag (IT0, IT1, IT2, IT3) is set to "1". Selection of
whether to mask the separate interrupts can be made with the interrupt mask registers (EIT0, EIT1, EIT2,
EIT3). However, regardless of the interrupt mask register setting, the interrupt factor flag is set to "1" at
the falling edge of the corresponding signal.

64 EPSON S1C63666 TECHNICAL MANUAL

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Clock Timer)

4.9.4 I/O memory of clock timer

Table 4.9.4.1 shows the I/O addresses and the control bits for the clock timer.

Table 4.9.4.1 Control bits of clock timer

Address Comment

FF74H

TM3 TM2 TM1 TM0

FF75H

TM7 TM6 TM5 TM4

FF76H

EIT3 EIT2 EIT1 EIT0

FFE5H

FFF5H

*1 Initial value at initial reset
*2 Not set in the circuit
*3 Constantly "0" when being read

Register

D3 D2

00TMRST TMRUN

IT3 IT2 IT1 IT0

D1 D0 Name Init

WR/WR

R

R

R/W

R/W

∗

0

∗

0

TMRST

TMRUN

TM3
TM2
TM1
TM0
TM7
TM6
TM5
TM4
EIT3
EIT2
EIT1
EIT0

IT3
IT2
IT1
IT0

∗1

3

∗

–

3

∗

–

∗

3

Reset0Reset

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

10

2
2

Run

Enable
Enable
Enable
Enable

(R)

Yes

(W)

Reset

Unused
Unused

Invalid

Clock timer reset (writing)

Stop

Clock timer Run/Stop
Clock timer data (16 Hz)
Clock timer data (32 Hz)
Clock timer data (64 Hz)
Clock timer data (128 Hz)
Clock timer data (1 Hz)
Clock timer data (2 Hz)
Clock timer data (4 Hz)
Clock timer data (8 Hz)
Interrupt mask register (Clock timer 1 Hz)

Mask

Interrupt mask register (Clock timer 2 Hz)

Mask

Interrupt mask register (Clock timer 8 Hz)

Mask

Interrupt mask register (Clock timer 32 Hz)

Mask

Interrupt factor flag (Clock timer 1 Hz)

(R)

Interrupt factor flag (Clock timer 2 Hz)

No

Interrupt factor flag (Clock timer 8 Hz)

(W)

Interrupt factor flag (Clock timer 32 Hz)

Invalid

TM0–TM7: Timer data (FF75H, FF76H)

The 128–1 Hz timer data of the clock timer can be read out with these registers. These eight bits are read
only, and writing operations are invalid.
By reading the low-order data (FF75H), the high-order data (FF76H) is held until reading or for 0.48–1.5
msec (one of shorter of them).
At initial reset, the timer data is initialized to "00H".

TMRST: Clock timer reset (FF74H•D1)

This bit resets the clock timer.

When "1" is written: Clock timer reset
When "0" is written: No operation

Reading: Always "0"

The clock timer is reset by writing "1" to TMRST. When the clock timer is reset in the RUN status, opera­tion restarts immediately. Also, in the STOP status the reset data is maintained. No operation results
when "0" is written to TMRST.
This bit is write-only, and so is always "0" at reading.

TMRUN: Clock timer RUN/STOP control register (FF74H•D0)

Controls RUN/STOP of the clock timer.

When "1" is written: RUN
When "0" is written: STOP

Reading: Valid

The clock timer enters the RUN status when "1" is written to the TMRUN register, and the STOP status
when "0" is written. In the STOP status, the timer data is maintained until the next RUN status or the
timer is reset. Also, when the STOP status changes to the RUN status, the data that is maintained can be
used for resuming the count.
At initial reset, this register is set to "0".

S1C63666 TECHNICAL MANUAL EPSON 65

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Clock Timer)

EIT0: 32 Hz interrupt mask register (FFE5H•D0)
EIT1: 8 Hz interrupt mask register (FFE5H•D1)
EIT2: 2 Hz interrupt mask register (FFE5H•D2)
EIT3: 1 Hz interrupt mask register (FFE5H•D3)

These registers are used to select whether to mask the clock timer interrupt.

When "1" is written: Enabled
When "0" is written: Masked

Reading: Valid

The interrupt mask registers (EIT0, EIT1, EIT2, EIT3) are used to select whether to mask the interrupt to
the separate frequencies (32 Hz, 8 Hz, 2 Hz, 1 Hz).
At initial reset, these registers are set to "0".

IT0: 32 Hz interrupt factor flag (FFF5H•D0)
IT1: 8 Hz interrupt factor flag (FFF5H•D1)
IT2: 2 Hz interrupt factor flag (FFF5H•D2)
IT3: 1 Hz interrupt factor flag (FFF5H•D3)

These flags indicate the status of the clock timer interrupt.

When "1" is read: Interrupt has occurred
When "0" is read: Interrupt has not occurred

When "1" is written: Flag is reset
When "0" is written: Invalid

The interrupt factor flags (IT0, IT1, IT2, IT3) correspond to the clock timer interrupts of the respective
frequencies (32 Hz, 8 Hz, 2 Hz, 1 Hz). The software can judge from these flags whether there is a clock
timer interrupt. However, even if the interrupt is masked, the flags are set to "1" at the falling edge of the
signal.
These flags are reset to "0" by writing "1" to them.
After an interrupt occurs, the same interrupt will occur again if the interrupt enabled state (I flag = "1") is
set or the RETI instruction is executed unless the interrupt factor flag is reset. Therefore, be sure to reset
(write "1" to) the interrupt factor flag in the interrupt service routine before shifting to the interrupt
enabled state.
At initial reset, these flags are set to "0".

4.9.5 Programming notes

(1) Be sure to read timer data in the order of low-order data (TM0–TM3) then high-order data (TM4–

TM7).

(2) After an interrupt occurs, the same interrupt will occur again if the interrupt enabled state (I flag =

"1") is set or the RETI instruction is executed unless the interrupt factor flag is reset. Therefore, be sure
to reset (write "1" to) the interrupt factor flag in the interrupt service routine before shifting to the
interrupt enabled state.

66 EPSON S1C63666 TECHNICAL MANUAL

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Stopwatch Timer)

4.10 Stopwatch Timer

4.10.1 Configuration of stopwatch timer

The S1C63666 has a 1/1,000 sec stopwatch timer. The stopwatch timer is configured of a 3-stage, 4-bit
BCD counter serving as the input clock of a 1,000 Hz signal output from the prescaler. Data can be read
out four bits (1/1,000 sec, 1/100 sec and 1/10 sec) at a time by the software.
In addition it has a direct input function that controls the stopwatch timer RUN/STOP and LAP using the
input ports K00 and K01.
Figure 4.10.1.1 is the block diagram of the stopwatch timer.

[SWRST]

(1,000 Hz)

1/1,000 sec

counter

1/100 sec

Capture buffer

SWD0–3
reading

counter

Data bus

SWD4–7
reading

1/10 sec

counter

1 Hz interrupt request

10 Hz interrupt request

SWD8–11
reading

Direct RUN interrupt request
Direct LAP interrupt request

K01

K00

K02–K13

f

OSC1

/32

(1,024 Hz)

[SWDIR]

Direct

input

control

[DKM2–0]

[LCURF]

1,000 / 1,024

prescaler

Capture

control

circuit

[SWRUN]

[EDIR]

[CRNWF]

Fig. 4.10.1.1 Block diagram of stopwatch timer

The stopwatch timer can be used as a separate timer from the clock timer. In particular, digital watch
stopwatch functions can be realized easily with software.

4.10.2 Counter and prescaler

The stopwatch timer is configured of four-bit BCD counters SWD0–3, SWD4–7 and SWD8–11.
The counter SWD0–3, at the stage preceding the stopwatch timer, has a 1,000 Hz signal generated by the
prescaler for the input clock. It counts up every 1/1,000 sec, and generates 100 Hz signal. The counter
SWD4–7 has a 100 Hz signal generated by the counter SWD0–3 for the input clock. It count-up every
1/100 sec, and generated 10 Hz signal. The counter SWD8–11 has an approximated 10 Hz signal gener­ated by the counter SWD4–7 for the input clock. It count-up every 1/10 sec, and generated 1 Hz signal.

The prescaler inputs a 1,024 Hz clock dividing f
outputs 1,000 Hz counting clock for SWD0–3. To generate a 1,000 Hz clock from 1,024 Hz, 24 pulses from
1,024 pulses that are input to the prescaler every second are taken out.
When the counter becomes the value indicated below, one pulse (1,024 Hz) that is input immediately
after to the prescaler will be pulled out.

OSC1 (output from the OSC1 oscillation circuit), and

<Counter value (msec) in which the pulse correction is performed>

39, 79, 139, 179, 219, 259, 299, 319, 359, 399, 439, 479, 539, 579, 619, 659, 699, 719, 759, 799, 839, 879, 939, 979

S1C63666 TECHNICAL MANUAL EPSON 67

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Stopwatch Timer)

Figure 4.10.2.1 shows the operation of the prescaler.

START

Prescaler input clock (1,024 Hz)

Prescaler output clock

Counter data

000 001 002 037 038 039 040 041

Fig. 4.10.2.1 Timing of the prescaler operation

For the above reason, the counting clock is 1,024 Hz (0.9765625 msec) except during pulse correction.
Consequently, frequency of the prescaler output clock (1,000 Hz), 100 Hz generated by SWD0–3 and 10
Hz generated by SWD4–7 are approximate values.

4.10.3 Capture buffer and hold function

The stopwatch data, 1/1,000 sec, 1/100 sec and 1/10 sec, can be read from SWD0–3 (FF7AH), SWD4–7
(FF7BH) and SWD8–11 (FF7CH), respectively. The counter data are latched in the capture buffer when
reading, and are held until reading of three words is completed. For this reason, correct data can be read
even when a carry from lower digits occurs during reading the three words. Further, three counter data
are latched in the capture buffer at the same time when SWD0–3 (1/1,000 sec) is read. The data hold is
released when SWD8–11 (1/10 sec) reading is completed. Therefore, data should be read in order of
SWD0–3 → SWD4–7 → SWD8–11. If SWD4–7 or SWD8–11 is first read when data have not been held, the
hold function does not work and data in the counter is directly read out. When data that has not been
held is read in the stopwatch timer RUN status, you cannot judge whether it is correct or not.

The stopwatch timer has a LAP function using an external key input (explained later). The capture buffer
is also used to hold LAP data. In this case, data is held until SWD8–11 is read. However, when a LAP
input is performed before completing the reading, the content of the capture buffer is renewed at that
point. Remaining data that have not been read become invalid by the renewal, and the hold status is not
released if SWD8–11 is read. When SWD8–11 is read after the capture buffer is updated, the capture
renewal flag is set to "1" at that point. In this case, it is necessary to read from SWD0–3 again. The capture
renewal flag is renewed by reading SWD8–11.

Figure 4.10.3.1 shows the timing for data holding and reading.

Direct LAP input (K01/K00)
Direct LAP internal signal
Capture renewal flag CRNWF
SWD0–3 reading
SWD4–7 reading
SWD8–11 reading
Data holding

Fig. 4.10.3.1 Timing for data holding and reading

68 EPSON S1C63666 TECHNICAL MANUAL

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Stopwatch Timer)

4.10.4 Stopwatch timer RUN/STOP and reset

RUN/STOP control and reset of the stopwatch timer can be done by the software.

Stopwatch timer RUN/STOP

The stopwatch timer enters the RUN status when "1" is written to SWRUN, and the STOP status when
"0" is written. In the STOP status, the timer data is maintained until the next RUN status or resets
timer. Also, when the STOP status changes to the RUN status, the data that was maintained can be
used for resuming the count. The RUN/STOP operation of the stopwatch timer by writing to the
SWRUN register is performed in synchronization with the falling edge of the 1,024 Hz same as the
prescaler input clock. The SWRUN register can be read, and in this case it indicates the operating
status of the stopwatch timer.
Figure 4.10.4.1 shows the operating timing when controlling the SWRUN register.

fOSC1/32 (1,024 Hz)
SWRUN writing
SWRUN register
Count clock

Fig. 4.10.4.1 Operating timing when controlling SWRUN

When the direct input function (explained in next section) is set, RUN/STOP control is done by an
external key input. In this case, SWRUN becomes read only register that indicates the operating status
of the stopwatch timer.

Stopwatch timer reset

The stopwatch timer is reset when "1" is written to SWRST. With this, the counter value is cleared to
"000". Since this resetting does not affect the capture buffer, data that has been held in the capture
buffer is not cleared and is maintained as is. When the stopwatch timer is reset in the RUN status,
counting restarts from count "000". Also, in the STOP status the reset data "000" is maintained until the
next RUN.

4.10.5 Direct input function and key mask

The stopwatch timer has a direct input function that can control the RUN/STOP and LAP operation of
the stopwatch timer by external key input. This function is set by writing "1" to the EDIR register. When
EDIR is set to "0", only the software control is possible as explained in the previous section.

Input port configuration

In the direct input function, the input ports K00 and K01 are used as the RUN/STOP and LAP input
ports. The key assignment can be selected using the SWDIR register.

Table 4.10.5.1 RUN/STOP and LAP input ports

SWDIR

0
1

Direct RUN

When the direct input function is selected, RUN/STOP operation of the stopwatch timer can be
controlled by using the key connected to the input port K00/K01 (selected by SWDIR). K00/K01
works as a normal input port, but the input signal is sent to the stopwatch control circuit. The key
input signal from the K00/K01 port works as a toggle switch. When it is input in STOP status, the
stopwatch timer runs, and in RUN status, the stopwatch timer stops. RUN/STOP status of the
stopwatch timer can be checked by reading the SWRUN register. An interrupt is generated by direct
RUN input.
The sampling for key input signal is performed at the falling edge of 1,024 Hz signal same as the
SWRUN control. The chattering judgment is performed at the point where the key turns off, and a
chattering less than 46.8–62.5 msec is removed. Therefore, more time is needed for an interval be­tween RUN and STOP key inputs.

K00

RUN/STOP

LAP

K01

LAP

RUN/STOP

S1C63666 TECHNICAL MANUAL EPSON 69

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Stopwatch Timer)

Figure 4.10.5.1 shows the operating timing for the direct RUN input.

fOSC1/32 (1,024 Hz)
Direct RUN input (K00/K01)
Direct RUN internal signal
SWRUN register
Count clock
Direct RUN interrupt

Fig. 4.10.5.1 Operating timing for direct RUN input

Direct LAP

Control for the LAP can also be done by key input same as the direct RUN. When the direct input
function is selected, the input port K01/K00 (selected by SWDIR) becomes the LAP key input port.
Sampling for the input signal and the chattering judgment are the same as a direct RUN.
By entering the LAP key, the counter data at that point is latched into the capture buffer and is held.
The counter continues counting operation. Furthermore, an interrupt occurs by direct LAP input.
As stated above, the capture buffer data is held until SWD8–11 is read. If the LAP key is input when
data has been already held, it renews the content of the capture buffer. When SWD8–11 is read after
renewing, the capture renewal flag is set to "1". In this case, the hold status is not released by reading
SWD8–11, and it continues. Normally the LAP data should be read after the interrupt is generated.
After that, be sure to check the capture renewal flag. When the capture renewal flag is set, renewed
data is held in the capture buffer. So it is necessary to read from SWD0–3 again.
The stopwatch timer sets the 1 Hz interrupt factor flag ISW1 to "1" when requiring a carry-up to 1-sec
digit by an SWD8–11 overflow. If the capture buffer shifts into hold status (when SWD0–3 is read or
when LAP is input) while the 1 Hz interrupt factor flag ISW1 is set to "1", the lap data carry-up
request flag LCURF is set to "1" to indicate that a carry-up to 1-sec digit is required for the processing
of LAP input. In normal software processing, LAP processing may take precedence over 1-sec or
higher digits processing by a 1 Hz interrupt, therefore carry-up processing using this flag should be
used for time display in the LAP processing to prevent the 1-sec digit data decreasing by 1 second.
This flag is renewed when the capture buffer shifts into hold status.
Figure 4.10.5.2 shows the operating timing for the direct LAP input, and Figure 4.10.5.3 shows the
timings for data holding and reading during a direct LAP input and reading.

f

OSC1

/32 (1,024 Hz)
Direct LAP input (K01/K00)
Direct LAP internal signal
Data holding

SWD8–11 reading

Direct LAP interrupt

Fig. 4.10.5.2 Operating timing for direct LAP input

Direct LAP input (K01/K00)
Capture renewal flag CRNWF
SWD0–3 reading
SWD4–7 reading
SWD8–11 reading
Data holding
1 Hz interrupt factor flag ISW1
Lap data carry-up request flag LCURF
Counter data

999 000

Fig. 4.10.5.3 Timing for data holding and reading during direct LAP input

70 EPSON S1C63666 TECHNICAL MANUAL

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Stopwatch Timer)

Key mask

In stopwatch applications, some functions may be controlled by a combination of keys including
direct RUN or direct LAP. For instance, the RUN key can be used for other functions, such as reset and
setting a watch, by pressing the RUN key with another key. In this case, the direct RUN function or
direct LAP function must be invalid so that it does not function. For this purpose, the key mask
function is set so that it judges concurrence of input keys and invalidates RUN and LAP functions. A
combination of the key inputs for this judgment can be selected using the DKM0–DKM2 registers.

Table 4.10.5.2 Key mask selection

DKM2

0
0
0
0
1
1
1
1

RUN or LAP inputs become invalid in the following status.

1. The RUN or LAP key is pressed when one or more keys that are included in the selected combina­tion (here in after referred to as mask) are held down.

2. The RUN or LAP key has been pressed when the mask is released.

DKM1

0
0
1
1
0
0
1
1

DKM0

0
1
0
1
0
1
0
1

Mask key combination

None (at initial reset)
K02
K02, K03
K02, K03, K10
K10
K10, K11
K10, K11, K12
K10, K11, K12, K13

fOSC1/32 (1,024 Hz)
Direct RUN/LAP input
Key mask

valid

invalid

invalid

invalid

Fig. 4.10.5.4 Operation of key mask

RUN or LAP inputs become valid in the following status.

1. Either the RUN or LAP key is pressed independently if no other key is been held down.

2. Both the RUN and LAP keys are pressed at the same time if no other key is held down. (RUN and
LAP functions are effective.)

3. The RUN or LAP key is pressed if either is held down. (RUN and LAP functions are effective.)

4. Either the RUN or LAP key and the mask key are pressed at the same time if no other key is held
down.

5. Both the RUN and LAP keys and the mask key are pressed at the same time if no other key is held
down. (RUN and LAP functions are effective.)

* Simultaneous key input is referred to as two or more key inputs are sampled at the same falling

edge of 1,024 Hz clock.

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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Stopwatch Timer)

4.10.6 Interrupt function

10 Hz and 1 Hz interrupts

The 10 Hz and 1 Hz interrupts can be generated through the overflow of stopwatch timers SWD4–7
and SWD8–11 respectively. Also, software can set whether to separately mask the frequencies de­scribed earlier.
Figure 4.10.6.1 is the timing chart for the counters.

Address Register Stopwatch timer (SWD0–3) timing chart

D0

FF7AH

(1/1,000 sec BCD)

D1

D2

D3

Address Register Stopwatch timer (SWD4–7) timing chart

D0

FF7BH

(1/100 sec BCD)

D1

D2

D3

10 Hz interrupt request

Address Register Stopwatch timer (SWD8–11) timing chart

D0

FF7CH

(1/10 sec BCD)

D1

D2

D3

1 Hz interrupt request

Fig. 4.10.6.1 Timing chart for counters

As shown in Figure 4.10.6.1, the interrupts are generated by the overflow of their respective counters ("9"
changing to "0"). Also, at this time the corresponding interrupt factor flag (ISW10, ISW1) is set to "1".
The respective interrupts can be masked separately through the interrupt mask registers (EISW10,
EISW1). However, regardless of the setting of the interrupt mask registers, the interrupt factor flags
are set to "1" by the overflow of their corresponding counters.

72 EPSON S1C63666 TECHNICAL MANUAL

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Stopwatch Timer)

Direct RUN and direct LAP interrupts

When the direct input function is selected, the direct RUN and direct LAP interrupts can be generated.
The respective interrupts occur at the rising edge of the internal signal for direct RUN and direct LAP
after sampling the direct input signal in the falling edge of 1,024 Hz signal. Also, at this time the
corresponding interrupt factor flag (IRUN, ILAP) is set to "1".
The respective interrupts can be masked separately through the interrupt mask registers (EIRUN,
EILAP). However, regardless of the setting of the interrupt mask registers, the interrupt factor flags
are set to "1" by the inputs of the RUN and LAP.

The direct RUN and LAP functions use the K00 and K01 ports. Therefore, the direct input interrupt
and the K00–K03 inputs interrupt may generate at the same time depending on the interrupt condi­tion setting for the input port K00–K03. Consequently, when using the direct input interrupt, set the
interrupt selection registers SIK00 and SIK01 to "0" so that the input interrupt does not generate by
K00 and K01 inputs.

f

OSC1

/32 (1,024 Hz)

SWRST writing

EDIR writing

EDIR register

Direct RUN input

SWRUN writing

SWRUN register

Direct LAP input

Counter data

Capture buffer

SWD0–3 reading

SWD4–7 reading

SWD8–11 reading

CRNWF

1 Hz interrupt factor flag ISW1

LCURF

Direct RUN interrupt

Direct LAP interrupt

10 Hz interrupt

1 Hz interrupt

001 002 003 004 005 006 098 099 100 101 102 000 001 002 003 004 005 006 007 993 994000 995 996 997 998 999 000 001 002 003 004 005 006 007

003 005 995 001 006

Fig. 4.10.6.2 Timing chart for stopwatch timer

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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Stopwatch Timer)

4.10.7 I/O memory of stopwatch timer

Table 4.10.7.1 shows the I/O addresses and the control bits for the stopwatch timer.

Table 4.10.7.1 Control bits of stopwatch timer

Address Comment

FOUTE SWDIR FOFQ1 FOFQ0

FF06H

EDIR DKM2 DKM1 DKM0

FF78H

LCURF CRNWF SWRUN SWRST

FF79H

SWD3 SWD2 SWD1 SWD0

FF7AH

SWD7 SWD6 SWD5 SWD4

FF7BH

SWD11 SWD10 SWD9 SWD8

FF7CH

EIRUN EILAP EISW1 EISW10

FFE6H

IRUN ILAP ISW1 ISW10

FFF6H

*1 Initial value at initial reset
*2 Not set in the circuit
*3 Constantly "0" when being read

D3 D2

Register

D1 D0 Name Init

R/W

R/W

R/W WR

R

R

R

R/W

R/W

FOUTE
SWDIR

FOFQ1
FOFQ0

EDIR
DKM2
DKM1
DKM0

LCURF
CRNWF
SWRUN

SWRST

SWD3
SWD2
SWD1
SWD0
SWD7
SWD6
SWD5

SWD4
SWD11
SWD10

SWD9

SWD8

EIRUN

EILAP

EISW1

EISW10

IRUN

ILAP

ISW1

ISW10

∗1

10

0

Enable Disable

0

0
0
0

Enable Disable
0
0
0
0

Request

0

Renewal

0

Reset

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

Run

Reset

Enable

Enable

Enable

Enable

(R)
Yes
(W)

Reset

∗

3

FOUT output enable
Stopwatch direct input switch
0: K00=Run/Stop, K01=Lap 1: K00=Lap, K01=Run/Stop

FOUT
frequency
selection

Direct input enable
Key mask
selection

Lap data carry-up request flag

No

Capture renewal flag

No

Stopwatch timer Run/Stop

Stop

Stopwatch timer reset (writing)

Invalid

Stopwatch timer data
BCD (1/1000 sec)

Stopwatch timer data
BCD (1/100 sec)

Stopwatch timer data
BCD (1/10 sec)

Interrupt mask register (Stopwatch direct RUN)

Mask

Interrupt mask register (Stopwatch direct LAP)

Mask

Interrupt mask register (Stopwatch timer 1 Hz)

Mask

Interrupt mask register (Stopwatch timer 10 Hz)

Mask

Interrupt factor flag (Stopwatch direct RUN)

(R)

Interrupt factor flag (Stopwatch direct LAP)

No

Interrupt factor flag (Stopwatch timer 1 Hz)

(W)

Interrupt factor flag (Stopwatch timer 10 Hz)

Invalid

[FOFQ1, 0]
Frequency

[DKM2, 1, 0]
Key mask

[DKM2, 1, 0]
Key mask

None1K022K02–033K02–03,10

K105K10–116K10–127K10–13

f

OSC1

0
4

0

/641f

OSC1

/82f

OSC1

OSC3

f

3

SWD0–SWD3: Stopwatch timer data 1/1,000 sec (FF7AH)

Data (BCD) of the 1/1,000 sec column of the capture buffer can be read out.
The hold function of the capture buffer works by reading this data.
These 4 bits are read-only, and cannot be used for writing operations.
At initial reset, the timer data is set to "0".

SWD4–SWD7: Stopwatch timer data 1/100 sec (FF7BH)

Data (BCD) of the 1/100 sec column of the capture buffer can be read out. These 4 bits are read-only, and
cannot be used for writing operations.
At initial reset, the timer data is set to "0".

SWD8–SWD11: Stopwatch timer data 1/10 sec (FF7CH)

Data (BCD) of the 1/10 sec column of the capture buffer can be read out. These 4 bits are read-only, and
cannot be used for writing operations.
At initial reset, the timer data is set to "0".

Note: Be sure to data reading in the order of SWD0–3 → SWD4–7 → SWD8–11.

74 EPSON S1C63666 TECHNICAL MANUAL

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Stopwatch Timer)

EDIR: Direct input function enable register (FF78H•D3)

Enables the direct input (RUN/LAP) function.

When "1" is written: Enabled
When "0" is written: Disabled

Reading: Valid

The direct input function is enabled by writing "1" to EDIR, and then RUN/STOP and LAP control can be
done by external key input. When "0" is written, the direct input function is disabled, and the stopwatch
timer is controlled by the software only.
Further the function switching is actually done by synchronizing with the falling edge of f

OSC1/32 (1,024

Hz) after the data is written to this register (after 977 µsec maximum).
At initial reset, this register is set to "0".

SWDIR: Direct input switch register (FF06H•D2)

Switches the direct-input key assignment for the K00 and K01 ports.

When "1" is written: K00 = LAP, K01 = RUN/STOP
When "0" is written: K00 = RUN/STOP, K01 = LAP

Reading: Valid

The direct-input key assignment is selected using this register. The K00 and K01 port statuses are input to
the stopwatch timer as the RUN/STOP and LAP inputs according to this selection.
At initial reset, this register is set to "0".

DKM0–DKM2: Direct key mask selection register (FF78H•D0–D2)

Selects a combination of the key inputs for concurrence judgment with RUN and LAP inputs when the
direct input function is set.

Table 4.10.7.2 Key mask selection

DKM2

0
0
0
0
1
1
1
1

DKM1

0
0
1
1
0
0
1
1

DKM0

0
1
0
1
0
1
0
1

Mask key combination

None (at initial reset)
K02
K02, K03
K02, K03, K10
K10
K10, K11
K10, K11, K12
K10, K11, K12, K13

When the concurrence is detected, RUN and LAP inputs cannot be accepted until the concurrence is
released.
At initial reset, this register is set to "0".

SWRST: Stopwatch timer reset (FF79H•D0)

This bit resets the stopwatch timer.

When "1" is written: Stopwatch timer reset
When "0" is written: No operation

Reading: Always "0"

The stopwatch timer is reset when "1" is written to SWRST. When the stopwatch timer is reset in the RUN
status, operation restarts immediately. Also, in the STOP status the reset data is maintained.
Since this reset does not affect the capture buffer, the capture buffer data in hold status is not cleared and
is maintained.
This bit is write-only, and is always "0" at reading.

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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Stopwatch Timer)

SWRUN: Stopwatch timer RUN/STOP (FF79H•D1)

This register controls the RUN/STOP of the stopwatch timer, and the operating status can be monitored
by reading this register.

• When writing data

When "1" is written: RUN
When "0" is written: STOP

The stopwatch timer enters the RUN status when "1" is written to SWRUN, and the STOP status when "0"
is written. In the STOP status, the timer data is maintained until the next RUN status or resets timer. Also,
when the STOP status changes to the RUN status, the data that was maintained can be used for resuming
the count. RUN/STOP control with this register is valid only when the direct input function is set to
disable. When the direct input function is set, it becomes invalid.

• When reading data

When "1" is read: RUN
When "0" is read: STOP

Reading is always valid regardless of the direct input function setting. "1" is read when the stopwatch
timer is in the RUN status, and "0" is read in the STOP status.
At initial reset, this register is set to "0".

LCURF: Lap data carry-up request flag (FF79H•D3)

This flag indicates a carry that has been generated to 1 sec-digit when the data is held. Note that this flag
is invalid when the direct input function is disabled.

When "1" is read: Carry is required
When "0" is read: Carry is not required

Writing: Invalid

If the capture buffer shifts into hold status while the 1 Hz interrupt factor flag ISW1 is set to "1", LCURF is
set to "1" to indicate that a carry-up to 1-sec digit is required. When performing a processing such as a
LAP input preceding with 1 Hz interrupt processing, read this flag before processing and check whether
carry-up is needed or not.
This flag is renewed (set/reset) every time the capture buffer shifts into hold status.
At initial reset, this flag is set to "0".

CRNWF: Capture renewal flag (FF79H•D2)

This flag indicates that the content of the capture buffer has been renewed.

When "1" is read: Renewed
When "0" is read: Not renewed

Writing: Invalid

The content of the capture buffer is renewed if the LAP key is input when the data held into the capture
buffer has not yet been read. Reading SWD8–11 in that status sets this flag to "1", and the hold status is
maintained. Consequently, when data that is held by a LAP input is read, read this flag after reading the
SWD8–11 and check whether the data has been renewed or not.
This flag is renewed when SWD8–11 is read.
At initial reset, this flag is set to "0".

EIRUN, EILAP, EISW1, EISW10: Interrupt mask registers (FFE6H)

These registers are used to select whether to mask the stopwatch timer interrupt.

When "1" is written: Enabled
When "0" is written: Masked

Reading: Valid

The interrupt mask registers EIRUN, EILAP, EISW1 and EISW10 are used to separately select whether to
mask the direct RUN, direct LAP, 1 Hz and 10 Hz interrupts.
At initial reset, these registers are set to "0".

76 EPSON S1C63666 TECHNICAL MANUAL

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Stopwatch Timer)

IRUN, ILAP, ISW1, ISW10: Interrupt factor flags (FFF6H)

These flags indicate the status of the stopwatch timer interrupt.

When "1" is read: Interrupt has occurred
When "0" is read: Interrupt has not occurred

When "1" is written: Flag is reset
When "0" is written: Invalid

The interrupt factor flags IRUN, ILAP, ISW1 and ISW10 correspond to the direct RUN, direct LAP, 1 Hz
and 10 Hz interrupts respectively. The software can judge from these flags whether there is a stopwatch
timer interrupt. However, even if the interrupt is masked, the flags are set to "1" when the timing condi­tion is established.
These flags are reset to "0" by writing "1" to them.
After an interrupt occurs, the same interrupt will occur again if the interrupt enabled state (I flag = "1") is
set or the RETI instruction is executed unless the interrupt factor flag is reset. Therefore, be sure to reset
(write "1" to) the interrupt factor flag in the interrupt service routine before shifting to the interrupt
enabled state.
At initial reset, these flags are set to "0".

4.10.8 Programming notes

(1) The interrupt factor flag should be reset after resetting the stopwatch timer.
(2) Be sure to data reading in the order of SWD0–3 → SWD4–7 → SWD8–11.

(3) When data that is held by a LAP input is read, read the capture buffer renewal flag CRNWF after

reading the SWD8–11 and check whether the data has been renewed or not.

(4) When performing a processing such as a LAP input preceding with 1 Hz interrupt processing, read

the LAP data carry-up request flag LCURF before processing and check whether carry-up is needed or
not.

(5) After an interrupt occurs, the same interrupt will occur again if the interrupt enabled state (I flag =

"1") is set or the RETI instruction is executed unless the interrupt factor flag is reset. Therefore, be sure
to reset (write "1" to) the interrupt factor flag in the interrupt service routine before shifting to the
interrupt enabled state.

S1C63666 TECHNICAL MANUAL EPSON 77

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Programmable Timer)

4.11 Programmable Timer

4.11.1 Configuration of programmable timer

The S1C63666 has three 8-bit programmable timer systems (timer 0, timer 1 and timer 2) built-in.
The timers are composed of 8-bit presettable down counters and they can be used as 8 bits × 3 channels or
16 bits × 1 channel + 8 bits × 1 channel of programmable timers. Timer 0 also has an event counter
function using the K13 input port terminal.
Figure 4.11.1.1 shows the configuration of the programmable timer.

The programmable timer is designed to count down from the initial value set in the counter with soft­ware. An underflow according to the initial value occurs by counting down and is used for the following
functions:

• Presetting the initial value to the counter to generate the periodical underflow signal

• Generating an interrupt

• Generating a TOUT signal output from the R02 output port terminal

• Generating the synchronous clock source for the serial interface (timer 2 underflow is used, and it is
possible to set the transfer rate)

Interrupt
request

TOUT

(R02)

Serial
interface

OSC1
oscillation
circuit

OSC3
oscillation
circuit

Interrupt
control
circuit

Output port

f

R02

OSC3

Timer 0 Run/Stop

f

OSC1

Timer 1 Run/Stop

Timer 2 Run/Stop

PTRUN0

Selector

CKSEL0

PTRUN1

Selector

CKSEL1

PTRUN2

Selector

CKSEL2

1/2

PTOUT

1/2

K13

Divider

Input port

K13

2,048 Hz

Timer 0

Prescaler

Prescaler
setting

PTPS00
PTPS01

Timer function setting

FCSEL
PLPOL

Pulse polarity setting

PTRST0

Timer 0 reset

Clock
control
circuit

Event counter mode setting

16-bit mode selection

Timer 1

PTRST1

Timer 1 reset

Clock

Prescaler Selector

Prescaler
setting

PTPS10
PTPS11

control
circuit

Timer 2

PTRST2

Selector

CHSEL0
CHSEL1

Prescaler

Prescaler
setting

PTPS20
PTPS21

Timer 2 reset

Clock
control
circuit

Fig. 4.11.1.1 Configuration of programmable timer

EVCNT

MOD16

Reload data register

RLD00–RLD07

8-bit

down counter

Data buffer

PTD00–PTD07

Reload data register

RLD10–RLD17

8-bit

down counter

Data buffer

PTD10–PTD17

Reload data register

RLD20–RLD27

8-bit

down counter

Data buffer

PTD20–PTD27

Under­flow
signal

Under­flow
signal

Under­flow
signal

Data bus

78 EPSON S1C63666 TECHNICAL MANUAL

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Programmable Timer)

4.11.2 Basic count operation

This section explains the basic count operation when each timer is used as an individual 8-bit timer.

Each timer has an 8-bit down counter and an 8-bit reload data register.
The reload data register RLDx0–RLDx7 (x = timer number) is used to set the initial value to the down
counter.
By writing "1" to the timer reset bit PTRSTx, the down counter loads the initial value set in the reload
register. Therefore, down-counting is executed from the stored initial value by the input clock.
The PTRUNx register is provided to control the RUN/STOP for each timer. By writing "1" to this register
after presetting the reload data to the down counter, the down counter starts counting down. Writing "0"
stops the input count clock and the down counter stops counting. This control (RUN/STOP) does not
affect the counter data. The counter maintains its data while stopped, and can restart counting continuing
from that data.
The counter data can be read via the data buffer PTDx0–PTDx7 in optional timing. However, the counter
has the data hold function the same as the clock timer, that holds the high-order data (PTDx4–PTDx7)
when the low-order data (PTDx0–PTDx3) is read in order to prevent the borrowing operation between
low- and high-order reading, therefore be sure to read the low-order data first.
The counter reloads the initial value set in the reload data register when an underflow occurs through the
count down. It continues counting down from the initial value after reloading.
In addition to reloading the counter, this underflow signal controls the interrupt generation, pulse (TOUT
signal) output and clock supplying to the serial interface.

PTRUNx

PTRSTx

RLDx0–x7

Input clock

PTDx7

PTDx6

PTDx5

PTDx4

PTDx3

PTDx2

PTDx1

PTDx0

A6H F3H

Preset Reload &

Interrupt generation

Fig. 4.11.2.1 Basic operation timing of down counter

S1C63666 TECHNICAL MANUAL EPSON 79

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Programmable Timer)

4.11.3 Setting the input clock

A prescaler is provided for each timer. The prescaler generates the input clock for the timer by dividing
the source clock supplied from the OSC1 or OSC3 oscillation circuit.
The source clock (OSC1 or OSC3) and the division ratio of the prescaler can be selected with software for
each timer individually.
The input clock is set in the following sequence.

Selection of source clock

Select the source clock input to each prescaler from either OSC1 or OSC3. This selection is done using
the source clock selection register CKSELx; when "0" is written to the register, OSC1 is selected and
when "1" is written, OSC3 is selected.
When the OSC3 oscillation clock is selected for the clock source, it is necessary to turn the OSC3
oscillation on, prior to using the programmable timer. However the OSC3 oscillation circuit requires a
time at least 5 msec from turning the circuit on until the oscillation stabilizes. Therefore, allow an
adequate interval from turning the OSC3 oscillation circuit on to starting the programmable timer.
Refer to Section 4.4, "Oscillation Circuit", for the control and notes of the OSC3 oscillation circuit.
At initial reset, the OSC3 oscillation circuit is set in off state.

Selection of prescaler division ratio

Select the division ratio for each prescaler from among 4 types. This selection is done using the
prescaler division ratio selection register PTPSx0/PTPSx1. Table 4.11.3.1 shows the correspondence
between the setting value and the division ratio.

Table 4.11.3.1 Selection of prescaler division ratio

PTPSx1

PTPSx0

1
1
0
0

Prescaler division ratio

1
0
1
0

Source clock / 256
Source clock / 32
Source clock / 4
Source clock / 1

By writing "1" to the PTRUNx register, the prescaler inputs the source clock and outputs the clock
divided by the selected division ratio. The counter starts counting down by inputting the clock.

4.11.4 Event counter mode (timer 0)

Timer 0 has an event counter function that counts an external clock input to the input port K13. This
function is selected by writing "1" to timer 0 counter mode selection register EVCNT. At initial reset,
EVCNT is set to "0" and timer 0 is configured as a normal timer that counts the internal clock.
In the event counter mode, the clock is supplied to timer 0 from outside the IC, therefore, the settings of
the timer 0 prescaler division ratio selection register PTPS00–PTPS01 and the settings of the timer 0
source clock selection register CKSEL0 become invalid.
Count down timing can be selected from either the falling or rising edge of the input clock using the
timer 0 pulse polarity selection register PLPOL. When "0" is written to the PLPOL register, the falling
edge is selected, and when "1" is written, the rising edge is selected. The count down timing is shown in
Figure 4.11.4.1.

EVCNT

PTRUN0

1

PLPOL

K13 input

Count data

01

n n-1 n-2 n-3 n-4 n-5 n-6

Fig. 4.11.4.1 Timing chart in event counter mode

80 EPSON S1C63666 TECHNICAL MANUAL

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Programmable Timer)

The event counter mode also allows use of a noise reject function to eliminate noise such as chattering on
the external clock (K13 input signal). This function is selected by writing "1" to the timer 0 function
selection register FCSEL.
When "with noise rejector" is selected, an input pulse width for both low and high levels must be 0.98
msec∗ or more to count reliably. The noise rejector allows the counter to input the clock at the second
falling edge of the internal 2,048 Hz∗ signal after changing the input level of the K13 input port terminal.
Consequently, the pulse width of noise that can reliably be rejected is 0.48 msec∗ or less.
(∗: f

OSC1 = 32.768 kHz)

Figure 4.11.4.2 shows the count down timing with noise rejector.

2,048 Hz ∗

EVIN input (K13)

Counter
input clock ∗

Counter data n n-1 n-2 n-3

1

2

∗

1 When f

OSC1

∗

2 When PLPOL register is set to "0"

is 32.768 kHz

Fig. 4.11.4.2 Count down timing with noise rejector

The operation of the event counter mode is the same as the normal timer except it uses the K13 input as
the clock. Refer to Section 4.11.2, "Basic count operation" for basic operation and control.

4.11.5 16-bit timer (timer 0 + timer 1)

Timers 0 and 1 can be used as a 16-bit timer.
To use the 16-bit timer, write "1" to the timer 0 16-bit mode selection register MOD16.
The 16-bit timer is configured with timer 0 for low-order byte and timer 1 for high-order byte as shown in
Figure 4.11.5.1.

Timer 0 + Timer 1

Prescaler

Prescaler
setting

PTPS00
PTPS01

Timer function setting

FCSEL
PLPOL

Pulse polarity setting

PTRST0

Timer 0 reset

Clock
control
circuit

Event counter mode setting

OSC1
oscillation
circuit

OSC3
oscillation
circuit

f

f

OSC3

OSC1

K13

Timer 0 Run/Stop

PTRUN0

Selector

CKSEL0

Interrupt
TOUT

Input port

K13

Divider

Fig. 4.11.5.1 Configuration of 16-bit timer

The registers for timer 0 are used to control the timer. Thus the event counter function can also be used.
Timer 1 operates with the timer 0 underflow signal as the count clock, so the clock and RUN/STOP
control registers for timer 1 become invalid.
The counter data in 16-bit mode must be read in the order below.
PTD00–PTD03 → PTD04–PDT07 → PTD10–PTD13 → PTD14–PTD17

Timer 0 Timer 1

Low-order 8 bits High-order 8 bits

Reload data register

RLD00–RLD07

8-bit

down counter

Data buffer

PTD00–PTD07

EVCNT

Reload data register

RLD10–RLD17

8-bit

down counter

Data buffer

PTD10–PTD17

Under­flow
signal

Data bus

S1C63666 TECHNICAL MANUAL EPSON 81

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Programmable Timer)

4.11.6 Interrupt function

The programmable timer can generate an interrupt due to an underflow of each timer. See Figure 4.11.2.1
for the interrupt timing.

An underflow of timer x sets the corresponding interrupt factor flag IPTx to "1", and generates an inter­rupt. The interrupt can also be masked by setting the corresponding interrupt mask register EIPTx.
However, the interrupt factor flag is set to "1" by an underflow of the corresponding timer regardless of
the interrupt mask register setting.

When timers 0 and 1 are used as a 16-bit timer, an interrupt is generated by an underflow of timer 1. In
this case, IPT0 is not set to "1" by a timer 0 underflow.

4.11.7 Control of TOUT output

The programmable timer can generate a TOUT signal due to an underflow of a timer. The TOUT signal is
generated by dividing the underflows in 1/2. It is possible to select which timer's underflow is to be used
by the TOUT output channel selection register CHSEL0–CHSEL1.

Table 4.11.7.1 Selecting a timer for TOUT output

CHSEL1

Select timer 1 when generating the TOUT signal from the 16-bit timer output.

The TOUT signal can be output from the R02 output port terminal. Programmable clocks can be supplied
to external devices.
Figure 4.11.7.1 shows the configuration of the output port R02.

CHSEL0

1
0
0

TOUT output timer

∗

1
0

Timer 2
Timer 1
Timer 0

TOUT

Register

PTOUT

R02
(TOUT)

Data bus

Register

R02

Register

R02HIZ

Fig. 4.11.7.1 Configuration of R02

The output of a TOUT signal is controlled by the PTOUT register. When "1" is written to the PTOUT
register, the TOUT signal is output from the R02 output port terminal and when "0" is written, the
terminal goes to a high (V

DD) level. However, the data register R02 must always be "1" and the high

impedance control register R02HIZ must always be "0" (data output state).

Since the TOUT signal is generated asynchronously from the PTOUT register, a hazard within 1/2 cycle is
generated when the signal is turned on and off by setting the register.
Figure 4.11.7.2 shows the output waveform of the TOUT signal.

R02HIZ register

R02 register

PTOUT register

TOUT output

Fix at "0"

Fix at "1"

"1""0" "0"

Fig. 4.11.7.2 Output waveform of the TOUT signal

82 EPSON S1C63666 TECHNICAL MANUAL

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Programmable Timer)

4.11.8 Transfer rate setting for serial interface

The signal that is made from underflows of timer 2 by dividing them in 1/2, can be used as the clock
source for the serial interface.
The programmable timer outputs the clock to the serial interface by setting timer 2 into RUN state
(PTRUN2 = "1"). It is not necessary to control with the PTOUT register.

PTRUN2

Timer 2 underflow

Source clock for serial I/F

Fig. 4.11.8.1 Synchronous clock of serial interface

A setting value for the RLD2x register according to a transfer rate is calculated by the following expres­sion:

RLD2x = fosc / (2 ∗ bps ∗ division ratio of the prescaler) - 1

fosc:Oscillation frequency (OSC1/OSC3)
bps:Transfer rate

(00H can be set to RLD2x)

Be aware that the maximum clock frequency for the serial interface is limited to 1 MHz when OSC3 is
used as the clock source.

S1C63666 TECHNICAL MANUAL EPSON 83

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Programmable Timer)

4.11.9 I/O memory of programmable timer

Table 4.11.9.1 shows the I/O addresses and the control bits for the programmable timer.

Table 4.11.9.1(a) Control bits of programmable timer

Address Comment

MOD16

FFC0H

FFC1H

FFC2H

PTPS01 PTPS00 PTRST0 PTRUN0

FFC3H

PTPS11 PTPS10 PTRST1 PTRUN1

FFC4H

PTPS21 PTPS20 PTRST2 PTRUN2

FFC5H

RLD03 RLD02 RLD01 RLD00

FFC6H

RLD07 RLD06 RLD05 RLD04

FFC7H

RLD13 RLD12 RLD11 RLD10

FFC8H

RLD17 RLD16 RLD15 RLD14

FFC9H

RLD23 RLD22 RLD21 RLD20

FFCAH

RLD27 RLD26 RLD25 RLD24

FFCBH

PTD03 PTD02 PTD01 PTD00

FFCCH

PTD07 PTD06 PTD05 PTD04

FFCDH

Register

D3 D2

EVCNT FCSEL PLPOL

0 CHSEL1 CHSEL0 PTOUT

RR/W

0 CKSEL2 CKSEL1 CKSEL0

RR/W

D1 D0 Name Init

MOD16

EVCNT

R/W

FCSEL
PLPOL

0
CHSEL1
CHSEL0

PTOUT

0
CKSEL2
CKSEL1
CKSEL0

PTPS01
PTPS00

WR/WR/W

PTRST0
PTRUN0

PTPS11
PTPS10

WR/WR/W

PTRST1
PTRUN1

PTPS21
PTPS20

WR/WR/W

PTRST2
PTRUN2

RLD03

RLD02

R/W

RLD01

RLD00

RLD07

RLD06

R/W

RLD05

RLD04

RLD13

RLD12

R/W

RLD11

RLD10

RLD17

RLD16

R/W

RLD15

RLD14

RLD23

RLD22

R/W

RLD21

RLD20

RLD27

RLD26

R/W

RLD25

RLD24

PTD03

PTD02

R

PTD01

PTD00

PTD07

PTD06

R

PTD05

PTD04

∗1

10

0

16 bits

0

Event ct.

0

With NR

0

∗

3

∗

2

–

0
0
0OnOff

∗

3

∗

2

–

0

OSC3

0

OSC3

0

OSC3

0
0

∗

3

∗

2

Reset

–

0

Run
0
0

∗

3

∗

2

Reset

–

0

Run
0
0

∗

3

∗

2

Reset

–

0

Run
0

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

16-bit mode selection

8 bits

Timer 0 counter mode selection

Timer

Timer 0 function selection (for event counter mode)

No NR

Timer 0 pulse polarity selection (for event counter mode)
Unused
TOUT output
selection

[CHSEL1,0]
Timer

0

Timer 01Timer 12Timer 2

TOUT output control
Unused
Prescaler 2 source clock selection

OSC1

Prescaler 1 source clock selection

OSC1

Prescaler 0 source clock selection

OSC1

Prescaler 0
division ratio
selection

Timer 0 reset (reload)

Invalid

Timer 0 Run/Stop

Stop

Prescaler 1
division ratio
selection

Timer 1 reset (reload)

Invalid

Timer 1 Run/Stop

Stop

Prescaler 2
division ratio
selection

Timer 2 reset (reload)

Invalid

Timer 2 Run/Stop

Stop

[PTPS01, 00]
Division ratio

[PTPS11, 10]
Division ratio

[PTPS21, 20]
Division ratio

MSB
Programmable timer 0 reload data (low-order 4 bits)
LSB

MSB
Programmable timer 0 reload data (high-order 4 bits)
LSB

MSB
Programmable timer 1 reload data (low-order 4 bits)
LSB

MSB
Programmable timer 1 reload data (high-order 4 bits)
LSB

MSB
Programmable timer 2 reload data (low-order 4 bits)
LSB

MSB
Programmable timer 2 reload data (high-order 4 bits)
LSB

MSB
Programmable timer 0 data (low-order 4 bits)
LSB

MSB
Programmable timer 0 data (high-order 4 bits)
LSB

0

1/111/421/3231/256

0

1/111/421/3231/256

0

1/111/421/3231/256

84 EPSON S1C63666 TECHNICAL MANUAL

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Programmable Timer)

Table 4.11.9.1(b) Control bits of programmable timer

Address Comment

PTD13 PTD12 PTD11 PTD10

FFCEH

PTD17 PTD16 PTD15 PTD14

FFCFH

PTD23 PTD22 PTD21 PTD20

FFD0H

PTD27 PTD26 PTD25 PTD24

FFD1H

FFE1H

FFF1H

*1 Initial value at initial reset *3 Constantly "0" when being read
*2 Not set in the circuit

Register

D3 D2

0EIPT2 EIPT1 EIPT0

RR/W

0IPT2 IPT1 IPT0

RR/W

D1 D0 Name Init

PTD13
PTD12

R

R

R

R

PTD11
PTD10
PTD17
PTD16
PTD15
PTD14
PTD23
PTD22
PTD21
PTD20
PTD27
PTD26
PTD25
PTD24
0

EIPT2
EIPT1
EIPT0

0

IPT2
IPT1
IPT0

∗1

10
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

∗

3

∗

2

–

0

Enable

0

Enable

0

–

Enable

∗

2

(R)

0

Yes

0

(W)

0

Reset

∗

3

MSB
Programmable timer 1 data (low-order 4 bits)
LSB

MSB
Programmable timer 1 data (high-order 4 bits)
LSB

MSB
Programmable timer 2 data (low-order 4 bits)
LSB

MSB
Programmable timer 2 data (high-order 4 bits)
LSB

Unused
Interrupt mask register (Programmable timer 2)

Mask

Interrupt mask register (Programmable timer 1)

Mask

Interrupt mask register (Programmable timer 0)

Mask

Unused

(R)

Interrupt factor flag (Programmable timer 2)

No

Interrupt factor flag (Programmable timer 1)

(W)

Interrupt factor flag (Programmable timer 0)

Invalid

CKSEL0: Prescaler 0 source clock selection register (FFC2H•D0)
CKSEL1: Prescaler 1 source clock selection register (FFC2H•D1)
CKSEL2: Prescaler 2 source clock selection register (FFC2H•D2)

Selects the source clock of the prescaler.

When "1" is written: OSC3 clock
When "0" is written: OSC1 clock

Reading: Valid

The source clock for the prescaler is selected from OSC1 or OSC3. When "0" is written to the CKSELx
register, the OSC1 clock is selected as the input clock for the prescaler x (for timer x) and when "1" is
written, the OSC3 clock is selected.
When the event counter mode is selected for timer 0, the setting of CKSEL0 becomes invalid.
When timers 0 and 1 are used as a 16-bit timer, the setting of CKSEL1 becomes invalid.
At initial reset, these registers are set to "0".

PTPS00, PTPS01: Timer 0 prescaler division ratio selection register (FFC3H•D2, D3)
PTPS10, PTPS11: Timer 1 prescaler division ratio selection register (FFC4H•D2, D3)
PTPS20, PTPS21: Timer 2 prescaler division ratio selection register (FFC5H•D2, D3)

Sets the division ratio of the prescaler as shown in Table 4.11.9.2.

Table 4.11.9.2 Selection of prescaler division ratio

PTPSx1

PTPSx0

1
1
0
0

Prescaler division ratio

1
0
1
0

Source clock / 256
Source clock / 32
Source clock / 4
Source clock / 1

When the event counter mode is selected to timer 0, the setting of PTPS00 and PTPS01 becomes invalid.
When timers 0 and 1 are used as a 16-bit timer, the setting of PTPS10 and PTPS11 becomes invalid.
At initial reset, these registers are set to "0".

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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Programmable Timer)

MOD16: 16-bit mode selection register (FFC0H•D3)

Selects whether timers 0 and 1 are used as a 16-bit timer or 2 channels of 8-bit timer.

When "1" is written: 16-bit timer
When "0" is written: 8-bit timer

Reading: Valid

When "1" is written to MOD16, a 16-bit timer is configured with timer 0 for low-order byte and timer 1 for
high-order byte. Use the timer 0 registers for control. When "0" is written to MOD16, timer 0 and timer 1
are used as independent 8-bit timers.
At initial reset, this register is set to "0".

EVCNT: Timer 0 counter mode selection register (FFC0H•D2)

Selects a counter mode for timer 0.

When "1" is written: Event counter mode
When "0" is written: Timer mode

Reading: Valid

The counter mode for timer 0 is selected from either the event counter mode or timer mode. When "1" is
written to the EVCNT register, the event counter mode is selected and when "0" is written, the timer
mode is selected.
At initial reset, this register is set to "0".

FCSEL: Timer 0 function selection register (FFC0H•D1)

Selects whether the noise rejector of the clock input circuit will be used or not in the event counter mode.

When "1" is written: With noise rejector
When "0" is written: Without noise rejector

Reading: Valid

When "1" is written to the FCSEL register, the noise rejector is used and counting is done by an external
clock (K13) with 0.98 msec* or more pulse width. The noise rejector allows the counter to input the clock
at the second falling edge of the internal 2,048 Hz* signal after changing the input level of the K13 input
port terminal. Consequently, the pulse width of noise that can reliably be rejected is 0.48 msec* or less.
(∗: f

OSC1 = 32.768 kHz)

When "0" is written to the FCSEL register, the noise rejector is not used and the counting is done directly
by an external clock input to the K13 input port terminal.
Setting of this register is effective only when timer 0 is used in the event counter mode.
At initial reset, this register is set to "0".

PLPOL: Timer 0 pulse polarity selection register (FFC0H•D0)

Selects the count pulse polarity in the event counter mode.

When "1" is written: Rising edge
When "0" is written: Falling edge

Reading: Valid

The count timing in the event counter mode (timer 0) is selected from either the falling edge of the
external clock input to the K13 input port terminal or the rising edge. When "0" is written to the PLPOL
register, the falling edge is selected and when "1" is written, the rising edge is selected.
Setting of this register is effective only when timer 0 is used in the event counter mode.
At initial reset, this register is set to "0".

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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Programmable Timer)

RLD00–RLD07: Timer 0 reload data register (FFC6H, FFC7H)
RLD10–RLD17: Timer 1 reload data register (FFC8H, FFC9H)
RLD20–RLD27: Timer 2 reload data register (FFCAH, FFCBH)

Sets the initial value for the counter.
The reload data written in this register is loaded to the respective counters. The counter counts down
using the data as the initial value for counting.
Reload data is loaded to the counter when the counter is reset by writing "1" to the PTRSTx register, or
when counter underflow occurs.
At initial reset, these registers are set to "00H".

PTD00–PTD07: Timer 0 counter data (FFCCH, FFCDH)
PTD10–PTD17: Timer 1 counter data (FFCEH, FFCFH)
PTD20–PTD27: Timer 2 counter data (FFD0H, FFD1H)

Count data in the programmable timer can be read from these latches.
The low-order 4 bits of the count data in timer x can be read from PTDx0–PTDx3, and the high-order data
can be read from PTDx4–PTDx7. Since the high-order 4 bits are held by reading the low-order 4 bits, be
sure to read the low-order 4 bits first.
Since these latches are exclusively for reading, the writing operation is invalid.
At initial reset, these counter data are set to "00H".

PTRST0: Timer 0 reset (reload) (FFC3H•D1)
PTRST1: Timer 1 reset (reload) (FFC4H•D1)
PTRST2: Timer 2 reset (reload) (FFC5H•D1)

Resets the timer and presets reload data to the counter.

When "1" is written: Reset
When "0" is written: No operation

Reading: Always "0"

By writing "1" to PTRSTx, the reload data in the reload register RLDx0–RLDx7 is preset to the counter in
timer x. When the counter is preset in the RUN status, the counter restarts immediately after presetting.
In the case of STOP status, the reload data is preset to the counter and is maintained.
No operation results when "0" is written.
Since these bits are exclusively for writing, always set to "0" during reading.

PTRUN0: Timer 0 RUN/STOP control register (FFC3H•D0)
PTRUN1: Timer 1 RUN/STOP control register (FFC4H•D0)
PTRUN2: Timer 2 RUN/STOP control register (FFC5H•D0)

Controls the RUN/STOP of the counter.

When "1" is written: RUN
When "0" is written: STOP

Reading: Valid

The counter in timer x starts counting down by writing "1" to the PTRUNx register and stops by writing
"0". In STOP status, the counter data is maintained until the counter is reset or is set in the next RUN
status. When STOP status changes to RUN status, the data that has been maintained can be used for
resuming the count.
At initial reset, these registers are set to "0".

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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Programmable Timer)

CHSEL0, CHSEL1: TOUT output channel selection register (FFC1H•D1, D2)

Selects the channel used for TOUT signal output.

Table 4.11.9.3 Selecting a timer for TOUT output

CHSEL1

CHSEL0

1
0
0

∗

1
0

TOUT output timer

Timer 2
Timer 1
Timer 0

At initial reset, this register is set to "0".

PTOUT: TOUT output control register (FFC1H•D0)

Turns TOUT signal output on and off.

When "1" is written: On
When "0" is written: Off

Reading: Valid

PTOUT is the output control register for the TOUT signal. When "1" is written to the register, the TOUT
signal is output from the output port terminal R02 and when "0" is written, the terminal goes to a high
(V

DD) level. However, the data register R02 must always be "1" and the high impedance control register

R02HIZ must always be "0" (data output state).
At initial reset, this register is set to "0".

EIPT0: Timer 0 interrupt mask register (FFE1H•D0)
EIPT1: Timer 1 interrupt mask register (FFE1H•D1)
EIPT2: Timer 2 interrupt mask register (FFE1H•D2)

These registers are used to select whether to mask the programmable timer interrupt or not.

When "1" is written: Enabled
When "0" is written: Masked

Reading: Valid

The timer x interrupt can be masked individually by the interrupt mask registers EIPTx.
At initial reset, these registers are set to "0".

IPT0: Timer 0 interrupt factor flag (FFF1H•D0)
IPT1: Timer 1 interrupt factor flag (FFF1H•D1)
IPT2: Timer 2 interrupt factor flag (FFF1H•D2)

These flags indicate the status of the programmable timer interrupt.

When "1" is read: Interrupt has occurred
When "0" is read: Interrupt has not occurred

When "1" is written: Flag is reset
When "0" is written: Invalid

The interrupt factor flags IPTx correspond to the timer x interrupt. The software can judge from these
flags whether there is a programmable timer interrupt. However, even if the interrupt is masked, the flags
are set to "1" by the underflows of the corresponding counters.
These flags are reset to "0" by writing "1" to them.
After an interrupt occurs, the same interrupt will occur again if the interrupt enabled state (I flag = "1") is
set or the RETI instruction is executed unless the interrupt factor flag is reset. Therefore, be sure to reset
(write "1" to) the interrupt factor flag in the interrupt service routine before shifting to the interrupt
enabled state.
At initial reset, these flags are set to "0".

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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Programmable Timer)

4.11.10 Programming notes

(1) When reading counter data, be sure to read the low-order 4 bits (PTDx0–PTDx3) first. Furthermore,

the high-order 4 bits (PTDx4–PTDx7) should be read within 0.73 msec (when f
reading the low-order 4 bits (PTDx0–PTDx3).

(2) The programmable timer actually enters RUN/STOP status in synchronization with the falling edge

of the input clock after writing to the PTRUNx register. Consequently, when "0" is written to the
PTRUNx register, the timer enters STOP status at the point where the counter is decremented (-1). The
PTRUNx register maintains "1" for reading until the timer actually stops.
Figure 4.11.10.1 shows the timing chart for the RUN/STOP control.

Input clock

OSC1 is 32.768 kHz) of

PTRUNx (RD)

PTRUNx (WR)

PTDx0–PTDx7 42H 41H 40H 3FH 3EH 3DH

"1" (RUN)
writing

"0" (STOP)
writing

Fig. 4.11.10.1 Timing chart for RUN/STOP control

It is the same even in the event counter mode. Therefore, be aware that the counter does not enter
RUN/STOP status if a clock is not input after setting the RUN/STOP control register (PTRUN0).

(3) Since the TOUT signal is generated asynchronously from the PTOUT register, a hazard within 1/2

cycle is generated when the signal is turned on and off by setting the register.

(4) When the OSC3 oscillation clock is selected for the clock source, it is necessary to turn the OSC3

oscillation ON, prior to using the programmable timer. However the OSC3 oscillation circuit requires
a time at least 5 msec from turning the circuit ON until the oscillation stabilizes. Therefore, allow an
adequate interval from turning the OSC3 oscillation circuit ON to starting the programmable timer.
Refer to Section 4.4, "Oscillation Circuit", for the control and notes of the OSC3 oscillation circuit.
At initial reset, the OSC3 oscillation circuit is set in the off state.

(5) After an interrupt occurs, the same interrupt will occur again if the interrupt enabled state (I flag =

"1") is set or the RETI instruction is executed unless the interrupt factor flag is reset. Therefore, be sure
to reset (write "1" to) the interrupt factor flag in the interrupt service routine before shifting to the
interrupt enabled state.

(6) For the reason below, pay attention to the reload data write timing when changing the interval of the

programmable timer interrupts while the programmable timer is running.
The programmable timer counts down at the falling edge of the input clock and at the same time it
generates an interrupt if the counter underflows. Then it starts loading the reload data to the counter
and the counter data is determined at the next rising edge of the input clock (period shown in as ➀ in
the figure).

Input clock
Counter data

(continuous mode)

03H 02H 01H 00H 25H 24H

➀

(Reload data = 25H)

Counter data is determined by reloading.Underflow (interrupt is generated)

Fig. 4.11.10.2 Reload timing for programmable timer

To avoid improper reloading, do not rewrite the reload data after an interrupt occurs until the counter
data is determined including the reloading period ➀. Be especially careful when using the OSC1 (low­speed clock) as the clock source of the programmable timer and the CPU is operating with the OSC3
(high-speed clock).

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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface)

4.12 Serial Interface (SIN, SOUT, SCLK, SRDY)

4.12.1 Configuration of serial interface

The S1C63666 has a synchronous clock type 8 bits serial interface built-in.
The configuration of the serial interface is shown in Figure 4.12.1.1.
The CPU, via the 8-bit shift register, can read the serial input data from the SIN terminal. Moreover, via
the same 8-bit shift register, it can convert parallel data to serial data and output it to the SOUT terminal.
The synchronous clock for serial data input/output may be set by selecting by software any one of three
types of master mode (internal clock mode: when the S1C63666 is to be the master for serial input/
output) and a type of slave mode (external clock mode: when the S1C63666 is to be the slave for serial
input/output).
Also, when the serial interface is used at slave mode, SRDY signal which indicates whether or not the
serial interface is available to transmit or receive can be output to the SRDY terminal.

SD0–SD7

SIN
(P10)

SCLK
or
SCLK
(P12)

SCS0 SCS1

Serial clock
selector

Serial clock
generator

Serial I/F
activating
circuit

SCTRG

Shift register (8 bits)

SCPS

Serial clock

counter

f

OSC1

Programmable
timer 2 underflow
signal

Output
latch

ESOUT

Serial I/F interrupt
control circuit

SOUT
(P11)

Interrupt
request

SRDY
or
SRDY
(P13)

Fig. 4.12.1.1 Configuration of serial interface

The input/output ports of the serial interface are shared with the I/O ports P10–P13, and function of
these ports can be selected through the software.
P10–P13 terminals and serial input/output correspondence are as follows:

Master mode Slave mode

P10 = SIN (I) P10 = SIN (I)
P11 = SOUT (O) P11 = SOUT (O)
P12 = SCLK (O) P12 = SCLK (I)
P13 = I/O port (I/O) P13 = SRDY (O)

The SOUT output using the P11 port is enabled when "1" is written to the ESOUT register. If ESOUT is
"0", P11 functions as a general-purpose I/O port.

Note: At initial reset, P10–P13 are set to I/O ports.

When using the serial interface, switch the function (ESIF = "1", ESOUT = "1") in the initial routine.

90 EPSON S1C63666 TECHNICAL MANUAL