Page 1
CMOS 4-BIT SINGLE CHIP MICROCOMPUTER
S1C63656
Technical Manual
S1C63656 Technical Hardware
Page 2
NOTICE
No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko
Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any
liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or
circuit and, further, there is no representation that this material is applicable to products requiring high level reliability, such
as medical products. Moreover, no license to any intellectual property rights is granted by implication or otherwise, and there
is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright
infringement of a third party. This material or portions thereof may contain technology or the subject relating to strategic
products under the control of the Foreign Exchange and Foreign Trade Law of Japan and may require an export license from
the Ministry of International Trade and Industry or other approval from another government agency.
© SEIKO EPSON CORPORA TION 2007, All rights reserved.
Page 3
Revisions and Additions for this manual
Chapter
1
2
4
5
7
9
Appendix
Section
1.1
1.5
2.2.2
4.1
4.7.1
4.7.2
4.7.3
4.10.1
4.14.3
4.14.4
4.14.5
4.14.6
5.2
7.1
7.2
7.3
9.1
A.4.2
Page
1
5–8
13
22
48
48
51
72
112–113
115–116
117, 119
120
142
146
146
146
155
166
Item
Features
Mask Option
Simultaneous high input to terminals
K00–K03
Memory Map
Configuration of LCD driver
Power supply for LCD driving
Control of LCD display and drive waveform
Configuration of programmable timer
Operation of R/f conversion
Interrupt function
I/O memory of R/f converter
Programming notes
Summary of Notes by Function
Absolute Maximum Rating
Recommended Operating Conditions
DC Characteristics
Diagram of Pad Layout
Differences with the actual IC
Contents
Explanation was revised.
Explanation was revised.
Explanation was revised.
Table 2.2.2.1 was revised.
Table 4.1.1(e) was revised.
Explanation was revised.
Explanation was revised.
Explanation was revised.
A note was added.
Explanation was revised.
Explanation was revised.
Figures 4.14.3.1–4.14.3.2 were revised.
Explanation was revised.
Figures 4.14.4.1–4.14.4.4 were revised.
Table 4.14.5.1 was revised.
Explanation was revised.
Explanation was revised.
Explanation was revised.
Table was revised.
Table was revised.
Table was revised.
Figure was revised.
Explanation was revised.
Figure was deleted.
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Page 5
Configuration of product number
Devices
S1 C 63158 F 0A01
00
Packing specifications
00 : Besides tape & reel
0A : TCP BL 2 directions
0B : Tape & reel BACK
0C : TCP BR 2 directions
0D : TCP BT 2 directions
0E : TCP BD 2 directions
0F : Tape & reel FRONT
0G : TCP BT 4 directions
0H : TCP BD 4 directions
0J : TCP SL 2 directions
0K : TCP SR 2 directions
0L : Tape & reel LEFT
0M : TCP ST 2 directions
0N : TCP SD 2 directions
0P : TCP ST 4 directions
0Q : TCP SD 4 directions
0R : Tape & reel RIGHT
99 : Specs not fixed
Specification
Package
D: die form; F: QFP, B: BGA
Model number
Model name
C: microcomputer, digital products
Product classification
S1: semiconductor
Development tools
S5U1 C 63000 A1 1
00
Packing specifications
00: standard packing
Version
1: Version 1
Tool type
Hx : ICE
Ex : EVA board
Px : Peripheral board
Wx : Flash ROM writer for the microcomputer
Xx : ROM writer peripheral board
Cx : C compiler package
Ax : Assembler package
Dx : Utility tool by the model
Qx : Soft simulator
Corresponding model number
63000: common to S1C63 Family
Tool classification
C: microcomputer use
Product classification
S5U1: development tool for semiconductor products
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CONTENTS
CONTENTS
CHAPTER
1OUTLINE ________________________________________________ 1
1.1 Features......................................................................................................... 1
1.2Block Diagram .............................................................................................. 2
1.3 Pin Layout Diagram .....................................................................................3
1.4 Pin Description ............................................................................................. 4
1.5 Mask Option.................................................................................................. 5
CHAPTER 2POWER SUPPLY AND INITIAL RESET ____________________________ 9
2.1 Power Supply ................................................................................................9
2.1.1 Voltage regulator for OSC1 oscillation circuit......................................... 10
2.1.2 High-speed operation voltage regulator ................................................... 10
2.1.3 Internal operating voltage VD1....................................................................................... 10
2.1.4 LCD system voltage circuit ....................................................................... 10
2.1.5 Analog system power supply ..................................................................... 11
2.2 Initial Reset .................................................................................................. 12
2.2.1 Reset terminal (RESET) ............................................................................ 12
2.2.2 Simultaneous high input to terminals K00–K03 ...................................... 13
2.2.3 Internal register at initial resetting........................................................... 13
2.2.4 Terminal settings at initial resetting ......................................................... 14
2.3 Test Terminal (TEST) ...................................................................................14
CHAPTER 3 CPU, ROM, RAM________________________________________ 15
3.1 CPU.............................................................................................................. 15
3.2 Code ROM....................................................................................................15
3.3 RAM .............................................................................................................15
3.4 Data ROM ....................................................................................................16
CHAPTER 4PERIPHERAL CIRCUITS AND OPERATION__________________________ 17
4.1 Memory Map................................................................................................17
4.2Watchdog Timer ........................................................................................... 26
4.2.1 Configuration of watchdog timer.............................................................. 26
4.2.2 Interrupt function ...................................................................................... 26
4.2.3 I/O memory of watchdog timer ................................................................. 27
4.2.4 Programming notes ................................................................................... 27
4.3 Oscillation Circuit ....................................................................................... 28
4.3.1 Configuration of oscillation circuit .......................................................... 28
4.3.2 OSC1 oscillation circuit............................................................................ 28
4.3.3 OSC3 oscillation circuit............................................................................ 29
4.3.4 Switching of CPU clock ............................................................................ 30
4.3.5 Clock frequency and instruction execution time....................................... 30
4.3.6 I/O memory of oscillation circuit.............................................................. 31
4.3.7 Programming notes ................................................................................... 32
4.4 Input Ports (K00–K03 and K10–K13) .........................................................33
4.4.1 Configuration of input ports ..................................................................... 33
4.4.2 Interrupt function ...................................................................................... 33
4.4.3 Mask option ............................................................................................... 34
4.4.4 I/O memory of input ports......................................................................... 35
4.4.5 Programming notes ................................................................................... 37
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4.5 Output Ports (R00–R03) ..............................................................................38
4.5.1 Configuration of output ports ................................................................... 38
4.5.2 Mask option ............................................................................................... 38
4.5.3 High impedance control............................................................................ 39
4.5.4 Special output ............................................................................................ 39
4.5.5 I/O memory of output ports....................................................................... 41
4.5.6 Programming notes ................................................................................... 42
4.6 I/O Ports (P00–P03 and P10–P13) .............................................................43
4.6.1 Configuration of I/O ports ........................................................................ 43
4.6.2 Mask option ............................................................................................... 44
4.6.3 I/O control registers and input/output mode ............................................ 44
4.6.4 Pull-down during input mode ................................................................... 44
4.6.5 I/O memory of I/O ports............................................................................ 45
4.6.6 Programming note..................................................................................... 47
4.7 LCD Driver (COM0–COM3, SEG0–SEG37) .............................................48
4.7.1 Configuration of LCD driver .................................................................... 48
4.7.2 Power supply for LCD driving .................................................................. 48
4.7.3 Control of LCD display and drive waveform ........................................... 48
4.7.4 Display memory......................................................................................... 52
4.7.5 Segment option .......................................................................................... 52
4.7.6 LCD contrast adjustment .......................................................................... 54
4.7.7 I/O memory of LCD driver........................................................................ 55
4.7.8 Programming note..................................................................................... 56
4.8 Clock Timer ..................................................................................................57
4.8.1 Configuration of clock timer..................................................................... 57
4.8.2 Data reading and hold function................................................................ 57
4.8.3 Interrupt function ...................................................................................... 58
4.8.4 I/O memory of clock timer ........................................................................ 59
4.8.5 Programming notes ................................................................................... 60
4.9 Stopwatch Timer........................................................................................... 61
4.9.1 Configuration of stopwatch timer ............................................................. 61
4.9.2 Counter and prescaler............................................................................... 61
4.9.3 Capture buffer and hold function.............................................................. 62
4.9.4 Stopwatch timer RUN/STOP and reset ..................................................... 63
4.9.5 Direct input function and key mask .......................................................... 63
4.9.6 Interrupt function ...................................................................................... 66
4.9.7 I/O memory of stopwatch timer ................................................................ 68
4.9.8 Programming notes ................................................................................... 71
4.10 Programmable Timer ...................................................................................72
4.10.1 Configuration of programmable timer.................................................... 72
4.10.2 Basic count operation ............................................................................. 73
4.10.3 Setting the input clock ............................................................................. 74
4.10.4 Event counter mode (timer 0) ................................................................. 74
4.10.5 PWM mode (timer 0, timer 1) ................................................................. 75
4.10.6 16-bit timer (timer 0 + timer 1) .............................................................. 76
4.10.7 Interrupt function .................................................................................... 76
4.10.8 Control of TOUT output .......................................................................... 77
4.10.9 Transfer rate setting for serial interface ................................................ 78
4.10.10 I/O memory of programmable timer..................................................... 79
4.10.11 Programming notes ............................................................................... 85
4.11 Serial Interface (SIN, SOUT, SCLK, SRDY)................................................87
4.11.1 Configuration of serial interface ............................................................ 87
4.11.2 Mask option ............................................................................................. 88
4.11.3 Master mode and slave mode of serial interface.................................... 88
4.11.4 Data input/output and interrupt function ............................................... 89
4.11.5 I/O memory of serial interface................................................................ 92
4.11.6 Programming notes ................................................................................. 95
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4.12 Sound Generator.......................................................................................... 96
4.12.1 Configuration of sound generator .......................................................... 96
4.12.2 Control of buzzer output.......................................................................... 96
4.12.3 Setting of buzzer frequency and sound level........................................... 97
4.12.4 Digital envelope ...................................................................................... 98
4.12.5 One-shot output ....................................................................................... 99
4.12.6 I/O memory of sound generator............................................................. 100
4.12.7 Programming notes ................................................................................ 102
4.13 Integer Multiplier........................................................................................103
4.13.1 Configuration of integer multiplier........................................................ 103
4.13.2 Multiplication mode ............................................................................... 103
4.13.3 Division mode......................................................................................... 104
4.13.4 Execution cycle....................................................................................... 105
4.13.5 I/O memory of integer multiplier ........................................................... 106
4.13.6 Programming note.................................................................................. 107
4.14 R/f Converter...............................................................................................108
4.14.1 Configuration of R/f converter ............................................................... 108
4.14.2 Connection terminals and CR oscillation circuit.................................. 109
4.14.3 Operation of R/f conversion................................................................... 112
4.14.4 Interrupt function ................................................................................... 115
4.14.5 I/O memory of R/f converter .................................................................. 117
4.14.6 Programming notes ................................................................................ 120
4.15 Stepping Motor Driver................................................................................ 121
4.15.1 Configuration of stepping motor driver................................................. 121
4.15.2 Setting up the motor-drive pulse............................................................ 122
4.15.3 Pulse output control ............................................................................... 123
4.15.4 Interrupt function ................................................................................... 123
4.15.5 I/O memory of stepping motor driver .................................................... 124
4.15.6 Programming notes ................................................................................ 127
4.16 SVD (Supply Voltage Detection) Circuit..................................................... 128
4.16.1 Configuration of SVD circuit ................................................................. 128
4.16.2 SVD operation ........................................................................................ 128
4.16.3 I/O memory of SVD circuit..................................................................... 129
4.16.4 Programming notes ................................................................................ 130
4.17 Interrupt and HALT .................................................................................... 131
4.17.1 Interrupt factor....................................................................................... 133
4.17.2 Interrupt mask ........................................................................................ 134
4.17.3 Interrupt vector ...................................................................................... 134
4.17.4 I/O memory of interrupt ......................................................................... 135
4.17.5 Programming notes ................................................................................ 137
CHAPTER 5SUMMARY OF NOTES ______________________________________ 138
5.1 Notes for Low Current Consumption.......................................................... 138
5.2 Summary of Notes by Function................................................................... 139
5.3 Precautions on Mounting ...........................................................................143
CHAPTER 6BASIC EXTERNAL WIRING DIAGRAM ___________________________ 145
CHAPTER 7ELECTRICAL CHARACTERISTICS _______________________________ 146
7.1 Absolute Maximum Rating..........................................................................146
7.2 Recommended Operating Conditions......................................................... 146
7.3 DC Characteristics ..................................................................................... 146
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7.4 Analog Circuit Characteristics and Power Current Consumption ............ 147
7.5 Oscillation Characteristics......................................................................... 148
7.6 Serial Interface AC Characteristics ...........................................................150
7.7 Timing Chart............................................................................................... 151
7.8 R/f Converter Characteristics.....................................................................152
CHAPTER 8PACKAGE _______________________________________________ 153
8.1 Plastic Package...........................................................................................153
8.2 Ceramic Package for Test Samples............................................................. 154
CHAPTER 9PAD LAYOUT ____________________________________________ 155
9.1 Diagram of Pad Layout............................................................................... 155
9.2 Pad Coordinates..........................................................................................156
APPENDIX PERIPHERAL CIRCUIT BOARDS FOR S1C63656 ____________________ 157
A.1 Names and Functions of Each Part ............................................................ 157
A.1.1 S5U1C63000P1........................................................................................ 157
A.1.2 S5U1C63658P2........................................................................................ 160
A.2 Connecting to the Target System ................................................................161
A.3 Downloading to S5U1C63000P1 ............................................................... 164
A.3.1 Downloading Circuit Data 1
– when new ICE (S5U1C63000H2) is used............................................ 164
A.3.2 Downloading Circuit Data 2
– when previous ICE (S5U1C63000H1) is used .................................... 164
A.4 Usage Precautions ...................................................................................... 165
A.4.1 Operational precautions.......................................................................... 165
A.4.2 Differences with the actual IC................................................................. 165
A.5 Product Specifications ................................................................................ 168
A.5.1 Specifications of S5U1C63000P1 ........................................................... 168
A.5.2 Specifications of S5U1C63658P2 ........................................................... 168
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CHAPTER 1: OUTLINE
CHAPTER 1OUTLINE
The S1C63656 is a microcomputer which has a high-performance 4-bit CPU S1C63000 as the core CPU,
ROM (6,144 words × 13 bits), RAM (1,024 words × 4 bits), multiply-divide circuit, serial interface, watchdog
timer, programmable timer, time base counters (2 systems), an LCD driver that can drive a maximum 38
segments × 4 commons, sound generator, R/f converter and stepping motor driver built-in. The S1C63656
features low current consumption, this makes it suitable for battery driven clocks and watches with temperature and humidity measurement functions.
1.1 Features
OSC1 oscillation circuit ...................... 32.768 kHz (Typ.) crystal oscillation circuit
OSC3 oscillation circuit ...................... 4 MHz (Max.) ceramic (2 MHz Max. when OSC3 is used as the R/f
converter operating clock),
1.1 MHz (Typ.) CR oscillation circuit
or not used (∗1)
Instruction set ..................................... Basic instruction: 46 types (411 instructions with all)
Addressing mode: 8 types
Instruction execution time................... During operation at 32.768 kHz: 61 µsec 122 µsec 183 µsec
During operation at 4 MHz: 0.5 µsec 1 µsec 1.5 µsec
ROM capacity ..................................... Code ROM: 6,144 words × 13 bits
Data ROM: 1,024 words × 4 bits
RAM capacity...................................... Data memory: 1,024 words × 4 bits
Display memory: 48 words × 4 bits
Input port............................................. 8 bits (Pull-down resistors may be supplemented ∗1)
Output port.......................................... 4 bits (It is possible to switch the 2 bits to special output ∗2)
I/O port ................................................ 8 bits (It is possible to switch the 4 bits to serial I/F input/output ∗2)
Serial interface.................................... 1 port (8-bit clock synchronous system)
LCD driver........................................... 38 segments × 4 or 3 commons (∗2)
Time base counter.............................. Clock timer
Stopwatch timer (1/1000 sec, with direct key input function)
Programmable timer ........................... 8-bit PWM × 2 ch. or 16-bit PWM × 1 ch. (∗2)
Watchdog timer................................... Built-in
Sound generator................................. With envelope and 1-shot output functions
R/f converter ....................................... 2 ch., CR oscillation type, 20-bit counter
Supports resistive humidity sensors
Multiply-divide circuit .......................... 8-bit accumulator × 1 ch.
Multiplication: 8 bits × 8 bits → 16-bit product
Division: 16 bits ÷ 8 bits → 8-bit quotient and 8-bit remainder
Stepping motor driver ......................... 2 ch., a clock or watch controller can be implemented
Supply voltage detection (SVD) circuit.. Criteria voltages: 1.85–2.90 V (1.13–1.64 V when OSC3 is not used)
are selectable (∗2)
External interrupt ................................ Input port interrupt: 2 systems
Internal interrupt ................................. Clock timer interrupt: 5 systems
Stopwatch timer interrupt: 4 systems
Programmable timer interrupt: 4 systems
Serial interface interrupt: 1 system
R/f converter interrupt: 2 systems
Motor driver interrupt: 2 systems
Power supply voltage.......................... 2.4 to 3.6 V: Max. 4 MHz operation (when OSC3 is used)
1.1 to 3.6 V: 32 kHz operation (when OSC3 is not used)
Operating temperature range ............. -20 to 70°C
Current consumption (Typ.) ................ Low-speed operation (OSC1 = 32 kHz crystal oscillation):
During HALT 3.0 V (LCD ON) 0.60 µA
During operation 3.0 V (LCD ON) 2.50 µA
High-speed operation (OSC3 ceramic oscillation):
During operation 3.0 V (LCD ON) 1.0 mA
Package .............................................. QFP20-144pin (plastic) or chip
∗1: Can be selected with mask option ∗2: Can be selected with software
S1C63656 TECHNICAL MANUAL EPSON 1
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CHAPTER 1: OUTLINE
1.2 Block Diagram
OSC1
OSC2
OSC3
OSC4
COM0–3
SEG0–37
VDD
VDDA
VC1–3
VD1
VOSC
CA–CB
VSS
VSSA
ROM
6,144 words × 13 bits
OSC
RAM
1,024 words × 4 bits
Data ROM
1,024 words × 4 bits
LCD Driver
38 SEG × 4 COM
Power
Controller
SVD
System Reset
Core CPU S1C63000
Control
Interrupt
Generator
Clock
Timer
Stopwatch
Timer
Programmable
Timer/Counter
Input Port
Serial Interface
I/O Port
RESET
K00–K03
K10–K13
TEST
P00–P03
P10–P13
BZ
AO1
AO2
BO1
BO2
Sound
Generator
Stepping
Motor Driver
Output Port
R/f Converter
R00–R03
SEN0, SEN1, HUD
REF0, REF1
RFIN0, RFIN1
RFOUT
Fig. 1.2.1 Block diagram
2 EPSON S1C63656 TECHNICAL MANUAL
Page 13
1.3 Pin Layout Diagram
QFP20-144pin
CHAPTER 1: OUTLINE
73108
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
109
INDEX
144
Pin name
CB
VC1
VC2
VC3
VSSA
RFOUT
N.C.
RFIN0
RFIN1
REF0
SEN0
REF1
SEN1
N.C.
N.C.
HUD
N.C.
N.C.
N.C.
N.C.
N.C.
VDDA
VDDA
VOSC
N.C.
N.C.
N.C.
N.C.
OSC1
OSC2
VD1
N.C.
OSC3
OSC4
VSS
TEST
No.
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
Pin name
RESET
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
SEG32
SEG33
SEG34
SEG35
SEG36
SEG37
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
COM2
COM3
No.
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
Pin name
VDD
K00
K01
K02
N.C.
K03
K10
K11
K12
K13
N.C.
N.C.
P00
N.C.
P01
P02
P03
N.C.
N.C.
P10
P11
P12
N.C.
P13
R00
N.C.
R01
R02
N.C.
R03
BZ
VSS
AO1
AO2
BO1
BO2
Fig. 1.3.1 Pin layout diagram (QFP20-144pin)
72
37
361
No.
Pin name
109
VDD
110
N.C.
111
N.C.
112
N.C.
113
N.C.
114
N.C.
115
N.C.
116
N.C.
117
N.C.
118
SEG0
119
SEG1
120
SEG2
121
SEG3
122
SEG4
123
SEG5
124
SEG6
125
SEG7
126
SEG8
127
SEG9
128
SEG10
129
SEG11
130
SEG12
131
SEG13
132
SEG14
133
SEG15
134
SEG16
135
SEG17
136
SEG18
137
N.C.
138
N.C.
139
N.C.
140
N.C.
141
N.C.
142
COM0
143
COM1
144
CA
N.C. : No Connection
S1C63656 TECHNICAL MANUAL EPSON 3
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CHAPTER 1: OUTLINE
1.4 Pin Description
Pin name
V
DD
V
SS
V
DDA
V
SSA
V
D1
V
OSC
VC1–V
C3
CA, CB
OSC1
OSC2
OSC3
OSC4
K00–K03
K10–K13
P00–P03
P10
P11
P12
P13
R00
R01
R02
R03
AO1
AO2
BO1
BO2
COM0–COM3
SEG0–SEG37
SEN0
SEN1
REF0
REF1
HUD
RFIN0
RFIN1
RFOUT
BZ
RESET
TEST
Pin No.
73, 109
35, 104
22, 23
5
31
24
2–4
144, 1
29
30
33
34
74–76, 78
79–82
85, 87–89
92
93
94
96
97
99
100
102
105
106
107
108
142, 143, 71, 72
118–136, 46–64
11
13
10
12
16
8
9
6
103
37
36
Table 1.4.1 Pin description
I/O
Power (+) supply pin
–
Power (–) supply pin
–
Analog system power (+) supply pin (=V
–
–
Analog system power (–) supply pin (=V
–
Internal logic operating voltage output pin
–
Oscillation system regulated voltage output pin
–
LCD system power supply pin
–
LCD system voltage booster capacitor connecting pin
I
Crystal oscillation input pin
O
Crystal oscillation output pin
I
Ceramic or CR oscillation input pin (selected by mask option)
O
Ceramic or CR oscillation output pin (selected by mask option)
I
Input port pins
I
Input port pins
I/O
I/O port pins
I/O
I/O port or serial I/F data input pin (selected by software)
I/O
I/O port or serial I/F data output pin (selected by software)
I/O
I/O port or serial I/F clock I/O pin (selected by software)
I/O
I/O port or serial I/F ready signal output pin (selected by software)
O
Output port pin
O
Output port pin
O
Output port or TOUT output pin (selected by software)
O
Output port or FOUT output pin (selected by software)
O
Motor driver Ch. 1 drive pulse output pin 1
O
Motor driver Ch. 1 drive pulse output pin 2
O
Motor driver Ch. 2 drive pulse output pin 1
O
Motor driver Ch. 2 drive pulse output pin 2
O
LCD common output pin (1/4 or 1/3 duty is selectable by software)
O
LCD segment output pin
O
R/f converter Ch. 0 CR oscillation output pin
O
R/f converter Ch. 1 CR oscillation output pin
O
R/f converter Ch. 0 reference resistor CR oscillation output pin
O
R/f converter Ch. 1 reference resistor CR oscillation output pin
O
R/f converter AC-bias oscillation output pin for humidity sensor
I
R/f converter Ch. 0 CR oscillation input pin
I
R/f converter Ch. 1 CR oscillation input pin
O
R/f converter oscillation frequency output pin
O
Sound output pin
I
Initial reset input pin
I
Testing input pin
Function
DD
)
SS
)
4 EPSON S1C63656 TECHNICAL MANUAL
Page 15
CHAPTER 1: OUTLINE
1.5 Mask Option
Mask options shown below are provided for the S1C63656. Several hardware specifications are prepared
in each mask option, and one of them can be selected according to the application. The function option
generator winfog and segment option generator winsog, that have been prepared as the development
software tool of S1C63656, are used for this selection. Mask pattern of the IC is finally generated based on
the data created by winfog and winsog. Refer to the "S5U1C63000A Manual" for winfog and winsog.
<Outline of the mask option>
(1) OSC1 oscillation circuit
The OSC1 oscillation circuit is fixed at crystal oscillation. Refer to Section 4.3.2, "OSC1 oscillation
circuit", for details.
(2) OSC3 oscillation circuit
The OSC3 oscillator type can be selected from ceramic oscillation, CR oscillation (external R), CR
oscillation (built-in R) and no operation (not used). Refer to Section 4.3.3, "OSC3 oscillation circuit",
for details.
(3) Input port pull-down resistor
The mask option is used to select whether the pull-down resistor is supplemented to the input ports
or not. It is possible to select for each bit of the input ports. Refer to Section 4.4.3, "Mask option", for
details.
(4) RESET terminal pull-down resistor
This option is used to select whether the pull-down resistor is supplemented to the RESET terminal or
not. Refer to Section 2.2.1, "Reset terminal (RESET)", for details.
(5) I/O port pull-down resistor
The mask option is used to select whether the pull-down resistor working in the input mode is
supplemented to the I/O ports or not. It is possible to select for each bit of the input ports. Refer to
Section 4.6.2, "Mask option", for details.
(6) Output specification of the output port
Either complementary output or P-channel open drain output can be selected as the output specification for the output ports R00–R03. The selection is done in 1-bit units. Refer to Section 4.5.2, "Mask
option", for details.
(7) Output specification of the I/O port
For the output specification when the I/O ports P00–P03 and P10–P13 are in the output mode, either
complementary output or P-channel open drain output can be selected in 1-bit units. Refer to Section
4.6.2, "Mask option", for details.
(8) External reset by simultaneous high input to the input port (K00–K03)
This function resets the IC when several keys are pressed simultaneously. The mask option is used to
select whether this function is used or not. Further when the function is used, a combination of the
input ports (K00–K03), which are connected to the keys to be pressed simultaneously, can be selected.
Refer to Section 2.2.2, "Simultaneous high input to terminals K00–K03", for details.
(9) Time authorize circuit for the simultaneous high input reset function
When the external reset function (shown in 8 above) is used, the time authorize circuit is enabled. The
reset function works only when the input time of simultaneous low is more than the rule time if the
time authorize circuit is being used. When the external reset function is not used, the time authorize
circuit cannot be used. Refer to Section 2.2.2, "Simultaneous high input to terminals K00–K03", for
details.
S1C63656 TECHNICAL MANUAL EPSON 5
Page 16
CHAPTER 1: OUTLINE
(10) Synchronous clock polarity in the serial interface
The polarity of the synchronous clock SCLK and the SRDY signal in slave mode of the serial interface
is selected by mask option. Either positive polarity or negative polarity can be selected. Refer to
Section 4.11.2, "Mask option", for details.
(11) LCD drive power
Either the internal power supply or an external power supply can be selected for driving LCD. Refer
to Section 4.7.2, "Power supply for LCD driving", for details.
(12) LCD segment specification
The display memory can be allocated to the optional SEG terminal. It is also possible to set the
optional SEG terminal for DC output. Refer to Section 4.7.5, "Segment option", for details.
<Option list>
The following is the option list for the S1C63656.
Multiple selections are available in each option item as indicated in the option list. Select the specifications that meet the target system and check the appropriate box. Be sure to record the specifications for
unused functions too.
1. OSC1 SYSTEM CLOCK
■■ 1. Crystal
2. OSC3 SYSTEM CLOCK
■■ 1. CR (built-in R)
■■ 2. CR (external R)
■■ 3. Ceramic
■■ 4. No Operation (disabled)
3. INPUT PORT PULL DOWN RESISTOR
• K00 ■■ 1. With Resistor ■■ 2. Gate Direct
• K01 ■■ 1. With Resistor ■■ 2. Gate Direct
• K02 ■■ 1. With Resistor ■■ 2. Gate Direct
• K03 ■■ 1. With Resistor ■■ 2. Gate Direct
• K10 ■■ 1. With Resistor ■■ 2. Gate Direct
• K11 ■■ 1. With Resistor ■■ 2. Gate Direct
• K12 ■■ 1. With Resistor ■■ 2. Gate Direct
• K13 ■■ 1. With Resistor ■■ 2. Gate Direct
4. RESET PORT PULL DOWN RESISTOR
• RESET ■■ 1. With Resistor ■■ 2. Gate Direct
5. I/O PORT PULL DOWN RESISTOR
• P00 ■■ 1. With Resistor ■■ 2. Gate Direct
• P01 ■■ 1. With Resistor ■■ 2. Gate Direct
• P02 ■■ 1. With Resistor ■■ 2. Gate Direct
• P03 ■■ 1. With Resistor ■■ 2. Gate Direct
• P10 ■■ 1. With Resistor ■■ 2. Gate Direct
• P11 ■■ 1. With Resistor ■■ 2. Gate Direct
• P12 ■■ 1. With Resistor ■■ 2. Gate Direct
• P13 ■■ 1. With Resistor ■■ 2. Gate Direct
6. OUTPUT PORT OUTPUT SPECIFICATION
• R00 ■■ 1. Complementary ■■ 2. Pch-OpenDrain
• R01 ■■ 1. Complementary ■■ 2. Pch-OpenDrain
• R02 ■■ 1. Complementary ■■ 2. Pch-OpenDrain
• R03 ■■ 1. Complementary ■■ 2. Pch-OpenDrain
6 EPSON S1C63656 TECHNICAL MANUAL
Page 17
7. I/O PORT OUTPUT SPECIFICATION
• P00 ■■ 1. Complementary ■■ 2. Pch-OpenDrain
• P01 ■■ 1. Complementary ■■ 2. Pch-OpenDrain
• P02 ■■ 1. Complementary ■■ 2. Pch-OpenDrain
• P03 ■■ 1. Complementary ■■ 2. Pch-OpenDrain
• P10 ■■ 1. Complementary ■■ 2. Pch-OpenDrain
• P11 ■■ 1. Complementary ■■ 2. Pch-OpenDrain
• P12 ■■ 1. Complementary ■■ 2. Pch-OpenDrain
• P13 ■■ 1. Complementary ■■ 2. Pch-OpenDrain
8. MULTIPLE KEY ENTRY RESET COMBINATION
■■ 1. Not Use
■■ 2. Use (K00, K01)
■■ 3. Use (K00, K01, K02)
■■ 4. Use (K00, K01, K02, K03)
9. MULTIPLE KEY ENTRY RESET TIME AUTHORIZE
■■ 1. Not Use
■■ 2. Use
10. SIO SYNC CLOCK & SRDY
■■ 1. Negative
■■ 2. Positive
11. LCD DRIVING POWER
■■ 1. Internal Power (3.0 V panel, normal mode with contrast adjustment function)
■■ 2. External Power 1/3 bias, V
■■ 3. External Power 1/3 bias, V
■■ 4. External Power 1/2 bias, V
■■ 5. Internal Power (3.0 V panel, low-power mode without contrast adjustment function)
DD=VC2 (4.5 V panel)
DD=VC3 (3.0 V panel)
DD=VC3, VC1=VC2 (3.0 V panel)
CHAPTER 1: OUTLINE
S1C63656 TECHNICAL MANUAL EPSON 7
Page 18
CHAPTER 1: OUTLINE
12. SEGMENT OPTION
Pin
name
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
SEG32
SEG33
SEG34
SEG35
SEG36
SEG37
<address> H:
COM0
H L D
RAM data high-order address (0–9)
L:
RAM data low-order address (0–F)
D:
Data bit (0–3)
Address (F0xx)
COM1
H L D
COM2
H L D
<Output specification> S:
COM3
H L D
C:
N:
Output specification
SEG output■ S
DC output■ C■ N
SEG output■ S
DC output■ C■ N
SEG output■ S
DC output■ C■ N
SEG output■ S
DC output■ C■ N
SEG output■ S
DC output■ C■ N
SEG output■ S
DC output■ C■ N
SEG output■ S
DC output■ C■ N
SEG output■ S
DC output■ C■ N
SEG output■ S
DC output■ C■ N
SEG output■ S
DC output■ C■ N
SEG output■ S
DC output■ C■ N
SEG output■ S
DC output■ C■ N
SEG output■ S
DC output■ C■ N
SEG output■ S
DC output■ C■ N
SEG output■ S
DC output■ C■ N
SEG output■ S
DC output■ C■ N
SEG output■ S
DC output■ C■ N
SEG output■ S
DC output■ C■ N
SEG output■ S
DC output■ C■ N
Segment output
Complementary output
Nch open drain output
8 EPSON S1C63656 TECHNICAL MANUAL
Page 19
CHAPTER 2: POWER SUPPLY AND INITIAL RESET
CHAPTER 2POWER SUPPL Y AND INITIAL RESET
2.1 Power Supply
The S1C63656 operating power voltage is as follows. The operating power voltage range depends on a
mask option selection whether the OSC3 clock is used or not.
Table 2.1.1 Operating voltage
OSC3 oscillation circuit
Used
Not used
The S1C63656 operates by applying a single power supply within the above range between VDD and VSS.
The S1C63656 itself generates the voltage necessary for all the internal circuits by the built-in power
supply circuits shown in Table 2.1.2.
Circuit
OSC1 circuit
Internal circuits
(when OSC3 is not used)
OSC3 and internal circuits
(when OSC3 is used)
LCD driver
Maximum operating frequency
4 MHz (OSC3)
32 kHz (OSC1 only)
Table 2.1.2 Power supply circuits
Power supply
Voltage regulator for
OSC1 oscillation circuit
Voltage regulator for
OSC1 oscillation circuit
High-speed operation
voltage regulator
LCD system voltage
circuit
Operating voltage
2.4 V to 3.6 V
1.1 V to 3.6 V
Output voltage
VOSC
VOSC
VD3
VC1–VC3
Note: • Do not drive external loads with the output voltage from the internal power supply circuits.
• See Chapter 7, "Electrical Characteristics", for voltage values and drive capability.
R/f
converter
LCD driver
OSC1
oscillation circuit
CPU,
internal circuits
OSC3
oscillation circuit
External
power
supply
V
DDA
LCD system voltage circuit
LPWR
V
DD
V
C1
V
C2
V
C3
CA
CB
+
V
OSC
Mask option
V
D1
V
SS
V
SSA
LCD system
voltage regulator
V
C1
Voltage booster
Voltage regulator for
OSC1 oscillation circuit
Mask option
High-speed operation
voltage regulator
V
C1
V
C2
V
C3
V
OSC
V
D1
V
D3
Fig. 2.1.1 Configuration of power supply
The two switches in dotted boxes shown in Figure 2.1.1 are mask options for the OSC3 oscillation circuit.
The figure shows the switch status when an option (an oscillator type) that uses the OSC3 oscillation
circuit has been selected. When the option (No Operation) to disable the OSC3 oscillation circuit is
selected, both the switches are flipped to the other position.
S1C63656 TECHNICAL MANUAL EPSON 9
Page 20
CHAPTER 2: POWER SUPPLY AND INITIAL RESET
2.1.1 Voltage regulator for OSC1 oscillation circuit
This voltage regulator generates the VOSC voltage (0.98 V Typ.) for driving the OSC1 oscillation circuit.
This regulator always operates to drive the OSC1 oscillation circuit.
2.1.2 High-speed operation voltage regulator
The high-speed operation voltage regulator generates the VD3 voltage (2.0 V Typ.) for driving the OSC3
oscillation circuit and the internal logic circuits in high-speed mode. When a mask option for using OSC3
is selected, this voltage regulator always operates. When the option to disable OSC3 is selected, this
voltage regulator does not operate and current consumption can be reduced.
2.1.3 Internal operating voltage VD1
V
D1 is the operating voltage for the CPU and internal logic circuits. The OSC1 clock allows operation with
low-power voltage and low-current consumption as compared with the OSC3 clock for high-speed
operation. To take advantage of this feature, the power source of the V
D1 voltage is switched according to
the mask option selection whether OSC3 is used or not.
When the option to disable OSC3, V
oscillation circuit is used as V
When an option for using OSC3, V
tor is used as V
D1.
OSC (0.98 V Typ.) generated by the voltage regulator for the OSC1
D1.
D3 (2.0 V Typ.) generated by the high-speed operation voltage regula-
2.1.4 LCD system voltage circuit
The LCD system voltage circuit generates the LCD drive voltage. This circuit allows the software to turn
on and off. Turn this circuit on before starting display on the LCD. The LCD system voltage circuit
generates V
3V
C1) by boosting VC1.
The voltage regulator that generates V
adjustment of LCD contrast and low-power mode without a contrast adjustment function. One of them
can be selected by mask option.
When normal mode is selected, the V
LCD contrast changes.
When low-power mode is selected, current consumption can be reduced but the contrast adjustment
function is not available.
C1 with the voltage regulator built-in, and generates two other voltages (VC2 = 2VC1, VC3 =
C1 provides two operating modes, normal mode that allows
C1 voltage can be adjusted to 16 steps (1.03–1.40 V), as a result the
The LCD system voltage regulator can be disabled by mask option. In this case, external elements can be
minimized because the external capacitors for the LCD system voltage regulator are not necessary.
However when the LCD system voltage regulator is not used, the display quality of the LCD panel, when
the supply voltage fluctuates (drops), is inferior to when the LCD system voltage regulator is used.
Figure 2.1.4.1 shows the external element configuration when the LCD system voltage regulator is not
used.
4.5 V LCD panel
1/3 or 1/4 duty
1/3 bias
VDD
VC1
VC2
VC3
CA
CB
V
SS
C2
C4
C1
3.0 V
3 V LCD panel
1/3 or 1/4 duty
1/3 bias
VDD
VC1
VC2
VC3
CA
CB
V
SS
C2
C3
C1
3.0 V
3 V LCD panel
1/3 or 1/4 duty
1/2 bias
VDD
VC1
VC2
VC3
CA
CB
V
SS
C2
C1
3.0 V
Fig. 2.1.4.1 External elements when LCD system voltage regulator is not used
Refer to Section 4.7, "LCD Driver", for control of the LCD drive voltage.
10 EPSON S1C63656 TECHNICAL MANUAL
Page 21
CHAPTER 2: POWER SUPPLY AND INITIAL RESET
2.1.5 Analog system power supply
The VDDA and VSSA power supply terminals are provided only for the R/f converter in order to avoid
decreasing the conversion accuracy due to noise. However, the same voltage level as the V
be supplied to the V
V
DDA = VDD, VSSA = VSS
DDA–VSSA.
DD–VSS must
S1C63656 TECHNICAL MANUAL EPSON 11
Page 22
CHAPTER 2: POWER SUPPLY AND INITIAL RESET
2.2 Initial Reset
To initialize the S1C63656 circuits, initial reset must be executed. There are two ways of doing this.
(1) External initial reset by the RESET terminal
(2) External initial reset by simultaneous high input to terminals K00–K03 (mask option setting)
The circuits are initialized by either (1) or (2). When the power is turned on, be sure to initialize using the
reset function. It is not guaranteed that the circuits are initialized by only turning the power on.
Figure 2.2.1 shows the configuration of the initial reset circuit.
OSC1
OSC2
Mask option
OSC1
oscillation
circuit
Divider
1 Hz
2 Hz
K00
K01
K02
K03
RESET
authorize
V
SS
Time
circuit
Mask option
Noise
reject
circuit
RQ
S
Internal
initial
reset
Fig. 2.2.1 Configuration of initial reset circuit
2.2.1 Reset terminal (RESET)
Initial reset can be executed externally by setting the reset terminal to a high level (VDD). After that the
initial reset is released by setting the reset terminal to a low level (V
The reset input signal is maintained by the RS latch and becomes the internal initial reset signal. The RS
latch is designed to be released by a 2 Hz signal (high) that is divided by the OSC1 clock. Therefore in
normal operation, a maximum of 250 msec (when f
OSC1 = 32.768 kHz) is needed until the internal initial
reset is released after the reset terminal goes to low level. Be sure to maintain a reset input of 0.1 msec or
more. However, when turning the power on, the reset terminal should be set at a high level as in the
timing shown in Figure 2.2.1.1.
Note that a reset pulse shorter than 100 nsec is rejected as noise.
SS) and the CPU starts operation.
V
DD
RESET
1.1 V
Power on
0.9•VDD or more (high level)
DD
0.5•V
2.0 msec or more
Fig. 2.2.1.1 Initial reset at power on
The reset terminal should be set to 0.9•V
DD or more (high level) until the supply voltage becomes 1.1 V
or more.
After that, a level of 0.5•V
DD or more should be maintained more than 2.0 msec.
The reset terminal incorporates a pull-down resistor and a mask option is provided to select whether the
resistor is used or not.
12 EPSON S1C63656 TECHNICAL MANUAL
Page 23
CHAPTER 2: POWER SUPPLY AND INITIAL RESET
2.2.2 Simultaneous high input to terminals K00–K03
Another way of executing initial reset externally is to input a high signal simultaneously to the input
ports (K00–K03) selected with the mask option.
Since this initial reset passes through the noise reject circuit, maintain the specified input port terminals at
high level for at least 1.5 msec (when the oscillation frequency f
operation. The noise reject circuit does not operate immediately after turning the power on until the
oscillation circuit starts oscillating. Therefore, maintain the specified input port terminals at high level for
at least 1.5 msec (when the oscillation frequency f
OSC1 is 32.768 kHz) after oscillation starts.
Table 2.2.2.1 shows the combinations of input ports (K00–K03) that can be selected with the mask option.
Table 2.2.2.1 Combinations of input ports
Not use
1
K00∗K01
2
K00∗K01∗K02
3
K00∗K01∗K02∗K03
4
When, for instance, mask option 4 (K00∗K01∗K02∗K03) is
selected, initial reset is executed when the signals input to the
four ports K00–K03 are all high at the same time. When 2 or 3 is
selected, the initial reset is done when a key entry including a
combination of selected input ports is made.
Further, the time authorize circuit mask option is selected when this reset function is selected. The time
authorize circuit checks the input time of the simultaneous high input and performs initial reset if that
time is the defined time (1 to 2 sec) or more.
If using this function, make sure that the specified ports do not go high at the same time during ordinary
operation.
OSC1 is 32.768 kHz) during normal
2.2.3 Internal register at initial resetting
Initial reset initializes the CPU as shown in Table 2.2.3.1.
The registers and flags which are not initialized by initial reset should be initialized in the program if
necessary.
In particular, the stack pointers SP1 and SP2 must be set as a pair because all the interrupts including
NMI are masked after initial reset until both the SP1 and SP2 stack pointers are set with software.
When data is written to the EXT register, the E flag is set and the following instruction will be executed in
the extended addressing mode. If an instruction which does not permit extended operation is used as the
following instruction, the operation is not guaranteed. Therefore, do not write data to the EXT register for
initialization only.
Refer to the "S1C63000 Core CPU Manual" for extended addressing and usable instructions.
Table 2.2.3.1 Initial values
Name
Data register A
Data register B
Extension register EXT
Index register X
Index register Y
Program counter
Stack pointer SP1
Stack pointer SP2
Zero flag
Carry flag
Interrupt flag
Extension flag
Queue register
CPU core
Symbol
A
B
EXT
X
Y
PC
SP1
SP2
Z
C
I
E
Q
Number of bits
4
4
8
16
16
16
8
8
1
1
1
1
16
Setting value
Undefined
Undefined
Undefined
Undefined
Undefined
0110H
Undefined
Undefined
Undefined
Undefined
0
0
Undefined
Name
RAM
Display memory
Other peripheral circuits
Peripheral circuits
Number of bits
4
4
–
Setting value
∗ See Section 4.1, "Memory Map".
Undefined
Undefined
∗
S1C63656 TECHNICAL MANUAL EPSON 13
Page 24
CHAPTER 2: POWER SUPPLY AND INITIAL RESET
2.2.4 Terminal settings at initial resetting
The output port (R) terminals and I/O port (P) terminals are shared with special output terminals and
input/output terminals of the serial interface. These functions are selected by the software. At initial
reset, these terminals are set to the general purpose output port terminals and I/O port terminals. Set
them according to the system in the initial routine. In addition, take care of the initial status of output
terminals when designing a system.
Table 2.2.4.1 shows the list of the shared terminal settings.
Table 2.2.4.1 List of shared terminal settings
Terminal
name
R00
R01
R02
R03
P00–P03
P10
P11
P12
P13
∗ When "With Pull-Down" is selected by mask option (high impedance when "Gate Direct" is selected)
For setting procedure of the functions, see explanations for each of the peripheral circuits.
Terminal status
at initial reset
R00 (LOW output)
R01 (LOW output)
R02 (LOW output)
R03 (LOW output)
P00–P03 (Input & pulled down∗)
P10 (Input & pulled down∗)
P11 (Input & pulled down∗)
P12 (Input & pulled down∗)
P13 (Input & pulled down∗)
Special output
TOUT FOUT
TOUT
FOUT
Serial I/F
Master
SIN(I)
SOUT(O)
SCLK(O)
Slave
SIN(I)
SOUT(O)
SCLK(I)
SRDY(O)
2.3 Test Terminal (TEST)
This is the terminal used for the factory inspection of the IC. During normal operation, connect the TEST
terminal to V
SS.
14 EPSON S1C63656 TECHNICAL MANUAL
Page 25
CHAPTER 3: CPU, ROM, RAM
CHAPTER 3 CPU, R OM, RAM
3.1 CPU
The S1C63656 has a 4-bit core CPU S1C63000 built-in as its CPU part.
Refer to the "S1C63000 Core CPU Manual" for the S1C63000.
Note:
The SLP instruction cannot be used because the SLEEP operation is not assumed in the S1C63656.
3.2 Code ROM
The built-in code ROM is a mask ROM for loading programs, and has a capacity of 6,144 steps × 13 bits.
The core CPU can linearly access the program space up to step FFFFH from step 0000H, however, the
program area of the S1C63656 is step 0000H to step 17FFH. The program start address after initial reset is
assigned to step 0110H. The non-maskable interrupt (NMI) vector and hardware interrupt vectors are
allocated to step 0100H and steps 0102H–010EH, respectively.
0000H
17FFH
1800H
ROM
S1C63656
program area
S1C63000 core CPU
program space
0000H
0100H
0102H
010EH
0110H
Program area
NMI vector
Hardware
interrupt vectors
Program start address
FFFFH
Unused area
13 bits
Program area
Fig. 3.2.1 Configuration of code ROM
3.3 RAM
The RAM is a data memory for storing various kinds of data, and has a capacity of 1,024 words × 4 bits.
The RAM area is assigned to addresses 0000H to 03FFH on the data memory map. Addresses 0100H to
01FFH are 4-bit/16-bit data accessible areas and in other areas it is only possible to access 4-bit data.
When programming, keep the following points in mind.
(1) Part of the RAM area is used as a stack area for subroutine call and register evacuation, so pay
attention not to overlap the data area and stack area.
(2) The S1C63000 core CPU handles the stack using the stack pointer for 4-bit data (SP2) and the stack
pointer for 16-bit data (SP1).
16-bit data are accessed in stack handling by SP1, therefore, this stack area should be allocated to the
area where 4-bit/16-bit access is possible (0100H to 01FFH). The stack pointers SP1 and SP2 change
cyclically within their respective range: the range of SP1 is 0000H to 03FFH and the range of SP2 is
0000H to 00FFH. Therefore, pay attention to the SP1 value because it may be set to 0200H or more
exceeding the 4-bit/16-bit accessible range in the S1C63656 or it may be set to 00FFH or less. Memory
accesses except for stack operations by SP1 are 4-bit data access.
After initial reset, all the interrupts including NMI are masked until both the stack pointers SP1 and
SP2 are set by software. Further, if either SP1 or SP2 is re-set when both are set already, the interrupts
including NMI are masked again until the other is re-set. Therefore, the settings of SP1 and SP2 must
be done as a pair.
S1C63656 TECHNICAL MANUAL EPSON 15
Page 26
CHAPTER 3: CPU, ROM, RAM
(3) Subroutine calls use 4 words (for PC evacuation) in the stack area for 16-bit data (SP1). Interrupts use
4 words (for PC evacuation) in the stack area for 16-bit data (SP1) and 1 word (for F register evacuation) in the stack area for 4-bit data.
0000H
00FFH
0100H
01FFH
0200H
03FFH
4 bits
4-bit access area
(SP2 stack area)
4/16-bit access area
(SP1 stack area)
4-bit access area
(Data area)
Fig. 3.3.1 Configuration of data RAM
3.4 Data ROM
The data ROM is a mask ROM for loading various static data such as a character generator, and has a
capacity of 1,024 words × 4 bits. The data ROM is assigned to addresses 8000H to 83FFH on the data
memory map, and the data can be read using the same data memory access instructions as the RAM.
16 EPSON S1C63656 TECHNICAL MANUAL
Page 27
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map)
CHAPTER 4
The peripheral circuits of S1C63656 (timer, I/O, etc.) are interfaced with the CPU in the memory
mapped I/O method. Thus, all the peripheral circuits can be controlled by accessing the I/O memory on
the memory map using the memory operation instructions. The following sections explain the detailed
operation of each peripheral circuit.
P
ERIPHERAL
C
IRCUITS AND
O
PERA TION
4.1 Memory Map
The S1C63656 data memory consists of 1,024-word RAM, 1,024-word data ROM, 48-word display
memory and 101-word peripheral I/O memory. Figure 4.1.1 shows the overall memory map of the
S1C63656, and Table 4.1.1 the peripheral circuits' (I/O space) memory maps.
0000H
RAM area
0400H
8000H
8400H
F000H
FF00H
FFFFH
Unused area
Data ROM area
Unused area
I/O memory area
F000H
Display memory area
F030H
Unused area
FF00H
Peripheral I/O area
FFFFH
Fig. 4.1.1 Memory map
Note: Memory is not implemented in unused areas within the memory map. Further, some non-imple-
mentation areas and unused (access prohibition) areas exist in the peripheral I/O area. If the
program that accesses these areas is generated, its operation cannot be guaranteed. Refer to the
I/O memory maps shown in Table 4.1.1 for the peripheral I/O area.
S1C63656 TECHNICAL MANUAL EPSON 17
Page 28
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map)
Table 4.1.1 (a) I/O memory map (FF01H–FF20H)
Address Comment
CLKCHG OSCC 0 0
FF01H
FF04H
FF05H
FOUTE SWDIR FOFQ1 FOFQ0
FF06H
FF07H
FF10H
FF11H
PFWA3 PFWA2 PFWA1 PFWA0
FF12H
FF13H
PFWB3 PFWB2 PFWB1 PFWB0
FF14H
FF15H
SIK03 SIK02 SIK01 SIK00
FF20H
Register
D3 D2
D1 D0 Name Init
CLKCHG
OSCC
R/W R
0 SVDS2 SVDS1 SVDS0
RR/W
00SVDDT SVDON
RR/W
0
0
0
SVDS2
SVDS1
SVDS0
0
0
SVDDT
SVDON
FOUTE
SWDIR
FTRG1
FRUN1
R
FOFQ1
FOFQ0
0
0
WDEN
WDRST
0
0
FTRG2
FRUN2
FTRG1
FRUN1
R/W
00WDEN WDRST
R/W WR
00
R
FTRG2
FRUN2
WRW
0
000PFWA4
0
0
RR/W
PFWA4
PFWA3
PFWA2
PFWA1
R/W
PFWA0
0
000PFWB4
0
0
RR/W
PFWB4
PFWB3
PFWB2
PFWB1
R/W
000PFTYP
RR/W
PFWB0
0
0
0
PFTYP
SIK03
SIK02
R/W
SIK01
SIK00
∗1
0
0
∗
3
∗
2
–
∗
3
∗
2
–
∗
3
∗
2
–
0
0
0
∗
3
∗
2
–
∗
3
∗
2
–
00LowOnNormal
0
0
0
0
∗
3
∗
2
–
∗
3
∗
2
–
1
∗
3
Reset
∗
3
∗
2
–
∗
3
∗
2
–
∗
2
–
0
∗
2
–
0
∗
3
∗
2
–
∗
3
∗
2
–
∗
3
∗
2
–
0
0
0
0
0
∗
3
∗
2
–
∗
3
∗
2
–
∗
3
∗
2
–
0
0
0
0
0
∗
3
∗
2
–
∗
3
∗
2
–
∗
3
∗
2
–
0 Short Long
0
0
0
0
10
OSC3OnOSC1
Off
Off
Enable Disable
Enable
Disable
Reset
Invalid
Trigger
Invalid
Run
Stop
Trigger
Invalid
Run
Stop
Enable
Disable
Enable
Disable
Enable
Disable
Enable
Disable
CPU clock switch
OSC3 oscillation On/Off
Unused
Unused
Unused
SVD criteria voltage setting
(V1: when OSC3 is used, V2: when OSC3 is not used)
[SVDS2–0]
V1 (V)
V2 (V)
1.85
1
0
2.00
2.15
1.13
–
1.22
Unused
Unused
SVD evaluation data
SVD circuit On/Off
FOUT output enable
Stopwatch direct input switch
0: K00=Run/Stop, K01=Lap 1: K00=Lap, K01=Run/Stop
FOUT
frequency
selection
[FOFQ1, 0]
Frequency
Unused
Unused
Watchdog timer enable
Watchdog timer reset (writing)
Unused
Unused
Motor driver Ch. 2 trigger (writing)
Motor driver Ch. 2 status (reading)
Motor driver Ch. 1 trigger (writing)
Motor driver Ch. 1 status (reading)
Unused
Unused
Unused
Motor driver
Ch. 1
pulse width
selection
Unused
Unused
Unused
Motor driver
Ch. 2
pulse width
selection
[PFWA4–0]
[PFWB4–0]
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H–1FH
Unused
Unused
Unused
Pulse width base clock selection
K00–K03 interrupt selection register
Remarks
∗1Initial value at initial reset
∗2 Not set in the circuit
∗3 Constantly "0" when being read
2
3
2.30
1.30
0
OSC1/64
f
(PFTYP = "1")
1.46 msec
1.71 msec
1.95 msec
2.20 msec
2.44 msec
2.69 msec
2.93 msec
3.17 msec
3.42 msec
3.66 msec
3.91 msec
4.15 msec
4.40 msec
4.64 msec
4.88 msec
5.13 msec
5.37 msec
5.62 msec
5.86 msec
6.10 msec
6.35 msec
6.59 msec
6.84 msec
7.08 msec
3.42 msec
4
2.45
2.60
1.39
1.47
1
fOSC1/82fOSC1
Pulse width
(PFTYP = "0")
5
6
2.75
1.56
11.72 msec
13.67 msec
15.63 msec
17.58 msec
19.53 msec
21.48 msec
23.44 msec
25.39 msec
27.34 msec
29.30 msec
31.25 msec
33.20 msec
35.16 msec
37.11 msec
39.06 msec
41.02 msec
42.97 msec
44.92 msec
46.88 msec
48.83 msec
50.78 msec
52.73 msec
54.69 msec
56.64 msec
27.34 msec
2.90
1.64
OSC3
f
7
3
18 EPSON S1C63656 TECHNICAL MANUAL
Page 29
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map)
Table 4.1.1 (b) I/O memory map (FF21H–FF45H)
Address Comment
FF21H
KCP03 KCP02 KCP01 KCP00
FF22H
SIK13 SIK12 SIK11 SIK10
FF24H
FF25H
KCP13 KCP12 KCP11 KCP10
FF26H
R03HIZ R02HIZ R01HIZ R00HIZ
FF30H
FF31H
IOC03 IOC02 IOC01 IOC00
FF40H
PUL03 PUL02 PUL01 PUL00
FF41H
FF42H
IOC13 IOC12 IOC11 IOC10
FF44H
PUL13 PUL12 PUL11 PUL10
FF45H
Register
D3 D2
D1 D0 Name Init
K03 K02 K01 K00
R
R/W
R/W
K12 K11 K10
K13
R
R/W
R/W
R03 R02 R01 R00
R/W
R/W
R/W
P03 P02 P01 P00
R/W
R/W
R/W
K03
K02
K01
K00
KCP03
KCP02
KCP01
KCP00
SIK13
SIK12
SIK11
SIK10
K13
K12
K11
K10
KCP13
KCP12
KCP11
KCP10
R03HIZ
R02HIZ
R01HIZ
R00HIZ
R03
R02
R01
R00
IOC03
IOC02
IOC01
IOC00
PUL03
PUL02
PUL01
PUL00
P03
P02
P01
P00
IOC13
IOC12
IOC11
IOC10
PUL13
PUL12
PUL11
PUL10
–
–
–
–
1
1
1
1
0
0
0
0
–
–
–
–
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
–
–
–
–
0
0
0
0
1
1
1
1
∗1
10
∗
2
High
∗
2
High
∗
2
High
∗
2
High
Enable
Enable
Enable
Enable
∗
2
High
∗
2
High
∗
2
High
∗
2
High
Hi-Z
Hi-Z
Hi-Z
Hi-Z
High
High
High
High
Output
Output
Output
Output
On
On
On
On
∗
2
High
∗
2
High
∗
2
High
∗
2
High
Output
Output
Output
Output
On
On
On
On
Low
Low
K00–K03 input port data
Low
Low
K00–K03 input comparison register
Disable
Disable
K10–K13 interrupt selection register
Disable
Disable
Low
Low
K10–K13 input port data
Low
Low
K10–K13 input comparison register
R03 (FOUTE=0)/FOUT (FOUTE=1) Hi-Z control
Output
R02 (PTOUT=0)/TOUT (PTOUT=1) Hi-Z control
Output
R01 Hi-Z control
Output
R00 Hi-Z control
Output
R03
Low
Low
Low
Low
output port data (
R02
output port data (
R01
output port data
R00
output port data
FOUTE=0
PTOUT=0
) Fix at "1" when
) Fix at "1" when
Input
Input
P00–P03 I/O control register
Input
Input
Off
Off
P00–P03 pull-down control register
Off
Off
Low
Low
P00–P03 I/O port data
Low
Low
Input
P13 I/O control register
functions as a general-purpose register when SIF (slave) is selected
Input
P12 I/O control register (ESIF=0)
functions as a general-purpose register when SIF is selected
Input
P11 I/O control register (ESIF=0)
functions as a general-purpose register when SIF is selected
Input
P10 I/O control register (ESIF=0)
functions as a general-purpose register when SIF is selected
Off
P13 pull-down control register
functions as a general-purpose register when SIF (slave) is selected
Off
P12 pull-down control register (ESIF=0)
functions as a general-purpose register when SIF (master) is selected
SCLK (I) pull-down control register when SIF (slave) is selected
Off
P11 pull-down control register (ESIF=0)
functions as a general-purpose register when SIF is selected
Off
P10 pull-down control register (ESIF=0)
SIN pull-down control register
when SIF is selected
FOUT
TOUT
is used.
is used.
S1C63656 TECHNICAL MANUAL EPSON 19
Page 30
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map)
Table 4.1.1 (c) I/O memory map (FF46H–FF73H)
Address Comment
(XSRDY)
FF46H
LDUTY1 LDUTY0 STCD LPWR
FF60H
FF61H
FF62H
ENRTM ENRST ENON BZE
FF6CH
R/W W R/W
FF6DH
FF6EH
FF6FH
FF70H
SDP SCPS SCS1 SCS0
FF71H
SD3 SD2 SD1 SD0
FF72H
SD7 SD6 SD5 SD4
FF73H
Register
D3 D2
D1 D0 Name Init
P13
P13
P12
P11
P10
(XSCLK)
(SOUT)
(SIN)
P12
P11
R/W
P10
LDUTY1
LDUTY0
R/W
0 ALOFF ALON 0
RRR/W
LC3 LC2 LC1 LC0
R/W
STCD
LPWR
0
ALOFF
ALON
0
LC3
LC2
LC1
LC0
ENRTM
ENRST
ENON
BZE
0 BZSTP BZSHT SHTPW
0
BZSTP
BZSHT
RW R/W
0 BZFQ2 BZFQ1 BZFQ0
RR/W
0 BDTY2 BDTY1 BDTY0
RR/W
SHTPW
0
BZFQ2
BZFQ1
BZFQ0
0
BDTY2
BDTY1
BDTY0
0
0 ESOUT SCTRG ESIF
ESOUT
SCTRG
RR/W
ESIF
SDP
SCPS
R/W
SCS1
SCS0
SD3
SD2
R/W
SD1
SD0
SD7
SD6
R/W
SD5
SD4
∗1
∗
2
–
∗
2
–
∗
2
–
∗
2
–
0
0
00StaticOnDynamic
∗
3
∗
2
–
1
All Off
0
–
All On
∗
2
∗
3
0
0
0
0
0
∗
3
Reset
0
0
–
–
∗
0
0
0
∗
Enable
2
Trigger
125 msec
2
∗
3
∗
3
∗
3
0
0
0
∗
3
∗
2
–
0
0
0
∗
3
∗
2
–
0
Enable
0
Trigger
0
MSB first LSB first
0
0
0
0
∗
2
–
∗
2
–
∗
2
–
∗
2
–
∗
2
–
∗
2
–
∗
2
–
∗
2
–
10
Low
High
Low
High
Low
High
Low
High
Off
Normal
Normal
1 sec
0.5 sec
Reset
Invalid
On
Off
Disable
Stop
Invalid
Invalid
Busy
Ready
31.25 msec
Disable
Invalid
Run
Stop
SIF
I/O
High
Low
High
Low
High
Low
High
Low
High
Low
High
Low
High
Low
High
Low
P13 I/O port data
functions as a general-purpose register when SIF (slave) is selected
P12 I/O port data (ESIF=0)
functions as a general-purpose register when SIF is selected
P11 I/O port data (ESIF=0)
functions as a general-purpose register when SIF is selected
P10 I/O port data (ESIF=0)
functions as a general-purpose register when SIF is selected
LCD drive duty
switch
[LDUTY1, 0]
Duty
LCD drive switch
LCD power On/Off
Unused
LCD all Off control
LCD all On control
Unused
LCD contrast adjustment
[LC3–0]
Contrast
0
Light––15Dark
Envelope releasing time selection
Envelope reset (writing)
Envelope On/Off
Buzzer output enable
Unused
1-shot buzzer stop (writing)
1-shot buzzer trigger (writing)
1-shot buzzer status (reading)
1-shot buzzer pulse width setting
Unused
Buzzer
frequency
selection
[BZFQ2, 1, 0]
Frequency (Hz)
[BZFQ2, 1, 0]
Frequency (Hz)
Unused
Buzzer signal duty ratio selection
(refer to main manual)
Unused
SOUT enable
Serial I/F clock trigger (writing)
Serial I/F clock status (reading)
Serial I/F enable (P1 port function selection)
Serial I/F data input/output permutation
Serial I/F clock phase selection
–Negative polarity (mask option)
–Positive polarity (mask option)
Serial I/F
clock mode selection
MSB
Serial I/F transmit/receive data (low-order 4 bits)
LSB
MSB
Serial I/F transmit/receive data (high-order 4 bits)
LSB
0
1,2–3
1/4
1/3
0
4096.013276.822730.732340.6
4
2048.051638.461365.371170.3
[SCS1, 0]
Clock
[SCS1, 0]
Clock
0
Slave
2
OSC1/2
1
PT
3
OSC1
20 EPSON S1C63656 TECHNICAL MANUAL
Page 31
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map)
Table 4.1.1 (d) I/O memory map (FF74H–FF85H)
Address Comment
FF74H
TM3 TM2 TM1 TM0
FF75H
TM7 TM6 TM5 TM4
FF76H
EDIR DKM2 DKM1 DKM0
FF78H
LCURF CRNWF SWRUN SWRST
FF79H
SWD3 SWD2 SWD1 SWD0
FF7AH
SWD7 SWD6 SWD5 SWD4
FF7BH
SWD11 SWD10 SWD9 SWD8
FF7CH
SR3 SR2 SR1 SR0
FF80H
SR7 SR6 SR5 SR4
FF81H
DRL3 DRL2 DRL1 DRL0
FF82H
DRL7 DRL6 DRL5 DRL4
FF83H
DRH3 DRH2 DRH1 DRH0
FF84H
DRH7 DRH6 DRH5 DRH4
FF85H
Register
D3 D2
D1 D0 Name Init
00TMRST TMRUN
WR/WR
R
R
R/W
R/W WR
R
R
R
R/W
R/W
R/W
R/W
R/W
R/W
∗
0
∗
0
TMRST
TMRUN
TM3
TM2
TM1
TM0
TM7
TM6
TM5
TM4
EDIR
DKM2
DKM1
DKM0
LCURF
CRNWF
SWRUN
SWRST
SWD3
SWD2
SWD1
SWD0
SWD7
SWD6
SWD5
SWD4
SWD11
SWD10
SWD9
SWD8
SR3
SR2
SR1
SR0
SR7
SR6
SR5
SR4
DRL3
DRL2
DRL1
DRL0
DRL7
DRL6
DRL5
DRL4
DRH3
DRH2
DRH1
DRH0
DRH7
DRH6
DRH5
DRH4
∗1
3
∗
2
–
3
∗
2
–
∗
3
Reset0Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
∗
3
Reset
0
0
0
0
0
0
0
0
0
0
0
0
∗
2
–
∗
2
–
∗
2
–
∗
2
–
∗
2
–
∗
2
–
∗
2
–
∗
2
–
∗
2
–
∗
2
–
∗
2
–
∗
2
–
∗
2
–
∗
2
–
∗
2
–
∗
2
–
∗
2
–
∗
2
–
∗
2
–
∗
2
–
∗
2
–
∗
2
–
∗
2
–
∗
2
–
10
Invalid
Run
Stop
Enable Disable
Request
Renewal
Run
Reset
No
No
Stop
Invalid
Unused
Unused
Clock timer reset (writing)
Clock timer Run/Stop
Clock timer data (16 Hz)
Clock timer data (32 Hz)
Clock timer data (64 Hz)
Clock timer data (128 Hz)
Clock timer data (1 Hz)
Clock timer data (2 Hz)
Clock timer data (4 Hz)
Clock timer data (8 Hz)
Direct input enable
Key mask
selection
[DKM2, 1, 0]
Key mask
[DKM2, 1, 0]
Key mask
0
None1K022K02–033K02–03,10
4
K105K10–116K10–127K10–13
Lap data carry-up request flag
Capture renewal flag
Stopwatch timer Run/Stop
Stopwatch timer reset (writing)
Stopwatch timer data
BCD (1/1000 sec)
Stopwatch timer data
BCD (1/100 sec)
Stopwatch timer data
BCD (1/10 sec)
Source register (low-order 4 bits)
LSB
MSB
Source register (high-order 4 bits)
Low-order 8-bit destination register
(low-order 4 bits)
LSB
MSB
Low-order 8-bit destination register
(high-order 4 bits)
High-order 8-bit destination register
(low-order 4 bits)
LSB
MSB
High-order 8-bit destination register
(high-order 4 bits)
S1C63656 TECHNICAL MANUAL EPSON 21
Page 32
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map)
Table 4.1.1 (e) I/O memory map (FF86H–FFC0H)
Address Comment
FF86H
FF90H
OVTBC OVMC
FF91H
MC3 MC2 MC1 MC0
FF92H
MC7 MC6 MC5 MC4
FF93H
MC11 MC10 MC9 MC8
FF94H
MC15 MC14 MC13 MC12
FF95H
MC19 MC18 MC17 MC16
FF96H
TC3 TC2 TC1 TC0
FF97H
TC7 TC6 TC5 TC4
FF98H
TC11 TC10 TC9 TC8
FF99H
TC15 TC14 TC13 TC12
FF9AH
TC19 TC18 TC17 TC16
FF9BH
MOD16
FFC0H
Register
D3 D2
D1 D0 Name Init
NF VF ZF CALMD
RR/W
0 RFCLK RFSEL SENSEL
RR/W
RFRUNR RFRUNS
R/W
CALMD
0
RFCLK
RFSEL
SENSEL
OVTBC
OVMC
RFRUNR
RFRUNS
MC3
MC2
R/W
MC1
MC0
MC7
MC6
R/W
MC5
MC4
MC11
MC10
R/W
MC9
MC8
MC15
MC14
R/W
MC13
MC12
MC19
MC18
R/W
MC17
MC16
TC3
TC2
R/W
TC1
TC0
TC7
TC6
R/W
TC5
TC4
TC11
TC10
R/W
TC9
TC8
TC15
TC14
R/W
TC13
TC12
TC19
TC18
R/W
EVCNT FCSEL PLPOL
R/W
TC17
TC16
MOD16
EVCNT
FCSEL
PLPOL
NF
VF
ZF
∗1
10
0
Negative
0
Overflow
0
Zero
0
Run
Div.
∗
3
∗
2
–
0
OSC3
0
AC
0
Ch. 1
0
Overflow
0
Overflow
0
Run
0
Run
∗
2
–
∗
2
–
∗
2
–
∗
2
–
∗
2
–
∗
2
–
∗
2
–
∗
2
–
∗
2
–
∗
2
–
∗
2
–
∗
2
–
∗
2
–
∗
2
–
∗
2
–
∗
2
–
∗
2
–
∗
2
–
∗
2
–
∗
2
–
∗
2
–
∗
2
–
∗
2
–
∗
2
–
∗
2
–
∗
2
–
∗
2
–
∗
2
–
∗
2
–
∗
2
–
∗
2
–
∗
2
–
∗
2
–
∗
2
–
∗
2
–
∗
2
–
∗
2
–
∗
2
–
∗
2
–
∗
2
–
0
16 bits
0
Event ct.
0
With NR
0
Negative flag
Positive
Overflow flag
No
Zero flag
No
Operation status (reading)
Stop
Calculation mode selection (writing)
Mult.
Unused
OSC1
R/f conversion clock selection
DC
Ch. 1 sensor type selection
Ch. 0
Conversion channel selection
Time base counter overflow flag
Non-ov
Measurement counter overflow flag
Non-ov
Reference oscillation Run control/status (writing "0" is ineffective)
Stop
Sensor oscillation Run control/status (writing "0" is ineffective)
Stop
Measurement counter MC0–MC3
LSB
Measurement counter MC4–MC7
Measurement counter MC8–MC11
Measurement counter MC12–MC15
MSB
Measurement counter MC16–MC19
Time base counter TC0–TC3
LSB
Time base counter TC4–TC7
Time base counter TC8–TC11
Time base counter TC12–TC15
MSB
Time base counter TC16–TC19
16-bit mode selection
8 bits
Timer 0 counter mode selection
Timer
Timer 0 function selection (for event counter mode)
No NR
Timer 0 pulse polarity selection (for event counter mode)
22 EPSON S1C63656 TECHNICAL MANUAL
Page 33
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map)
Table 4.1.1 (f) I/O memory map (FFC1H–FFD3H)
Address Comment
FFC1H
FFC2H
PTPS01 PTPS00 PTRST0 PTRUN0
FFC3H
PTPS11 PTPS10 PTRST1 PTRUN1
FFC4H
RLD03 RLD02 RLD01 RLD00
FFC6H
RLD07 RLD06 RLD05 RLD04
FFC7H
RLD13 RLD12 RLD11 RLD10
FFC8H
RLD17 RLD16 RLD15 RLD14
FFC9H
PTD03 PTD02 PTD01 PTD00
FFCCH
PTD07 PTD06 PTD05 PTD04
FFCDH
PTD13 PTD12 PTD11 PTD10
FFCEH
PTD17 PTD16 PTD15 PTD14
FFCFH
CD03 CD02 CD01 CD00
FFD2H
CD07 CD06 CD05 CD04
FFD3H
Register
D3 D2
D1 D0 Name Init
00CHSEL0 PTOUT
RR/W
00CKSEL1 CKSEL0
RR/W
WR/WR/W
WR/WR/W
R/W
R/W
R/W
R/W
R
R
R
R
R/W
R/W
∗
0
∗
0
CHSEL0
PTOUT
∗
0
∗
0
CKSEL1
CKSEL0
PTPS01
PTPS00
PTRST0
PTRUN0
PTPS11
PTPS10
PTRST1
PTRUN1
RLD03
RLD02
RLD01
RLD00
RLD07
RLD06
RLD05
RLD04
RLD13
RLD12
RLD11
RLD10
RLD17
RLD16
RLD15
RLD14
PTD03
PTD02
PTD01
PTD00
PTD07
PTD06
PTD05
PTD04
PTD13
PTD12
PTD11
PTD10
PTD17
PTD16
PTD15
PTD14
CD03
CD02
CD01
CD00
CD07
CD06
CD05
CD04
∗1
3
–
3
–
10
∗
2
∗
2
00Timer 1OnTimer 0
3
∗
2
–
3
∗
2
–
00OSC3
OSC3
0
0
∗
3
∗
2
Reset
–
0
Run
0
0
∗
3
∗
2
Reset
–
0
Run
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Unused
Unused
TOUT output selection
Off
TOUT output control
Unused
Unused
OSC1
Prescaler 1 source clock selection
OSC1
Prescaler 0 source clock selection
Prescaler 0
division ratio
selection
Timer 0 reset (reload)
Invalid
Timer 0 Run/Stop
Stop
Prescaler 1
division ratio
selection
Timer 1 reset (reload)
Invalid
Timer 1 Run/Stop
Stop
[PTPS01, 00]
Division ratio
[PTPS11, 10]
Division ratio
MSB
Programmable timer 0 reload data (low-order 4 bits)
LSB
MSB
Programmable timer 0 reload data (high-order 4 bits)
LSB
MSB
Programmable timer 1 reload data (low-order 4 bits)
LSB
MSB
Programmable timer 1 reload data (high-order 4 bits)
LSB
MSB
Programmable timer 0 data (low-order 4 bits)
LSB
MSB
Programmable timer 0 data (high-order 4 bits)
LSB
MSB
Programmable timer 1 data (low-order 4 bits)
LSB
MSB
Programmable timer 1 data (high-order 4 bits)
LSB
MSB
Programmable timer 0 compare data (low-order 4 bits)
LSB
MSB
Programmable timer 0 compare data (high-order 4 bits)
LSB
0
1/111/421/3231/256
0
1/111/421/3231/256
S1C63656 TECHNICAL MANUAL EPSON 23
Page 34
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map)
Table 4.1.1 (g) I/O memory map (FFD4H–FFF0H)
Address Comment
CD13 CD12 CD11 CD10
FFD4H
CD17 CD16 CD15 CD14
FFD5H
FFD8H
FFE0H
FFE1H
FFE2H
FFE3H
FFE4H
EIT3 EIT2 EIT1 EIT0
FFE5H
EIRUN EILAP EISW1 EISW10
FFE6H
FFE7H
FFE8H
FFE9H
FFF0H
Register
D3 D2
D1 D0 Name Init
R/W
R/W
00PTSEL1 PTSEL0
RR/W
00ECTC1 ECTC0
RR/W
00EIPT1 EIPT0
RR/W
000EISIF
RR/W
000EIK0
RR/W
000EIK1
RR/W
R/W
R/W
00EIRFB EIRFM
RR/W
00EISMD2 EISMD1
RR/W
000EIT4
RR/W
00ICTC1 ICTC0
RR/W
CD13
CD12
CD11
CD10
CD17
CD16
CD15
CD14
∗
3
0
∗
3
0
PTSEL1
PTSEL0
∗
3
0
∗
3
0
ECTC1
ECTC0
∗
3
0
∗
3
0
EIPT1
EIPT0
∗
3
0
∗
3
0
∗
3
0
EISIF
∗
3
0
∗
3
0
∗
3
0
EIK0
∗
3
0
∗
3
0
∗
3
0
EIK1
EIT3
EIT2
EIT1
EIT0
EIRUN
EILAP
EISW1
EISW10
∗
3
0
∗
3
0
EIRFB
EIRFM
∗
3
0
∗
3
0
EISMD2
EISMD1
∗
3
0
∗
3
0
∗
3
0
EIT4
∗
3
0
∗
3
0
ICTC1
ICTC0
∗1
10
0
0
0
0
0
0
0
0
∗
2
–
∗
2
–
00PWM
PWM
∗
2
–
∗
2
–
00Enable
Enable
∗
2
–
∗
2
–
00Enable
Enable
∗
2
–
∗
2
–
∗
2
–
0 Enable Mask
∗
2
–
∗
2
–
∗
2
–
0 Enable Mask
∗
2
–
∗
2
–
∗
2
–
0 Enable Mask
0
Enable
0
Enable
0
Enable
0
Enable
0
Enable
0
Enable
0
Enable
0
Enable
∗
2
–
∗
2
–
00Enable
Enable
∗
2
–
∗
2
–
00Enable
Enable
∗
2
–
∗
2
–
∗
2
–
0 Enable Mask
∗
2
–
–
(R)
∗
2
Yes
0
(W)
0
Reset
MSB
Programmable timer 1 compare data (low-order 4 bits)
LSB
MSB
Programmable timer 1 compare data (high-order 4 bits)
LSB
Unused
Unused
Normal
Programmable timer 1 PWM output selection
Normal
Programmable timer 0 PWM output selection
Unused
Unused
Mask
Interrupt mask register (Programmable timer 1 compare match)
Mask
Interrupt mask register (Programmable timer 0 compare match)
Unused
Unused
Mask
Interrupt mask register (Programmable timer 1 underflow)
Mask
Interrupt mask register (Programmable timer 0 underflow)
Unused
Unused
Unused
Interrupt mask register (Serial I/F)
Unused
Unused
Unused
Interrupt mask register (K00–K03)
Unused
Unused
Unused
Interrupt mask register (K10–K13)
Interrupt mask register (Clock timer 1 Hz)
Mask
Interrupt mask register (Clock timer 2 Hz)
Mask
Interrupt mask register (Clock timer 8 Hz)
Mask
Interrupt mask register (Clock timer 32 Hz)
Mask
Interrupt mask register (Stopwatch direct RUN)
Mask
Interrupt mask register (Stopwatch direct LAP)
Mask
Interrupt mask register (Stopwatch timer 1 Hz)
Mask
Interrupt mask register (Stopwatch timer 10 Hz)
Mask
Unused
Unused
Mask
Interrupt mask register (R/f converter reference oscillate completion)
Mask
Interrupt mask register (R/f converter sensor oscillate completion)
Unused
Unused
Mask
Interrupt mask register (Motor driver Ch. 2)
Mask
Interrupt mask register (Motor driver Ch. 1)
Unused
Unused
Unused
Interrupt mask register (Clock timer 16 Hz)
Unused
(R)
Unused
No
Interrupt factor flag (Programmable timer 1 compare match)
(W)
Interrupt factor flag (Programmable timer 0 compare match)
Invalid
24 EPSON S1C63656 TECHNICAL MANUAL
Page 35
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map)
Table 4.1.1 (h) I/O memory map (FFF1H–FFF9H)
Address Comment
FFF1H
FFF2H
FFF3H
FFF4H
FFF5H
IRUN ILAP ISW1 ISW10
FFF6H
FFF7H
FFF8H
FFF9H
Register
D3 D2
00IPT1 IPT0
D1 D0 Name Init
0
0
RR/W
000ISIF
RR/W
000IK0
RR/W
000IK1
RR/W
0
0
0
0
0
0
0
0
0
IT3 IT2 IT1 IT0
R/W
R/W
00IRFB IRFM
ISW10
0
0
RR/W
00ISMD2 ISMD1
RR/W
000IT4
RR/W
0
0
ISMD2
ISMD1
0
0
0
IPT1
IPT0
ISIF
IK0
IK1
IT3
IT2
IT1
IT0
IRUN
ILAP
ISW1
IRFB
IRFM
IT4
∗1
∗
2
∗
2
0
0
∗
2
∗
2
∗
2
0
∗
2
∗
2
∗
2
0
∗
2
∗
2
∗
2
0
0
0
0
0
0
0
0
0
∗
2
∗
2
0
0
∗
2
∗
2
0
0
∗
2
∗
2
∗
2
0
10
(R)
(R)
Yes
No
(W)
(W)
Reset
Invalid
(R)
(R)
Yes
No
(W)
(W)
Reset
Invalid
(R)
(R)
Yes
No
(W)
(W)
Reset
Invalid
(R)
(R)
Yes
No
(W)
(W)
Reset
Invalid
(R)
(R)
Yes
No
(W)
(W)
Reset
Invalid
(R)
(R)
Yes
No
(W)
(W)
Reset
Invalid
(R)
(R)
Yes
No
(W)
(W)
Reset
Invalid
(R)
(R)
Yes
No
(W)
(W)
Reset
Invalid
(R)
(R)
Yes
No
(W)
(W)
Reset
Invalid
Unused
Unused
Interrupt factor flag (Programmable timer 1 underflow)
Interrupt factor flag (Programmable timer 0 underflow)
Unused
Unused
Unused
Interrupt factor flag (Serial I/F)
Unused
Unused
Unused
Interrupt factor flag (K00–K03)
Unused
Unused
Unused
Interrupt factor flag (K10–K13)
Interrupt factor flag (Clock timer 1 Hz)
Interrupt factor flag (Clock timer 2 Hz)
Interrupt factor flag (Clock timer 8 Hz)
Interrupt factor flag (Clock timer 32 Hz)
Interrupt factor flag (Stopwatch direct RUN)
Interrupt factor flag (Stopwatch direct LAP)
Interrupt factor flag (Stopwatch timer 1 Hz)
Interrupt factor flag (Stopwatch timer 10 Hz)
Unused
Unused
Interrupt factor flag (R/f converter reference oscillate completion)
Interrupt factor flag (R/f converter sensor oscillate completion)
Unused
Unused
Interrupt factor flag (Motor driver Ch. 2)
Interrupt factor flag (Motor driver Ch. 1)
Unused
Unused
Unused
Interrupt factor flag (Clock timer 16 Hz)
∗
3
–
∗
3
–
∗
3
–
∗
3
–
∗
3
–
∗
3
–
∗
3
–
∗
3
–
∗
3
–
∗
3
–
∗
3
–
∗
3
–
∗
3
–
∗
3
–
∗
3
–
∗
3
–
∗
3
–
∗
3
–
S1C63656 TECHNICAL MANUAL EPSON 25
Page 36
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Watchdog Timer)
4.2 Watchdog Timer
4.2.1 Configuration of watchdog timer
The S1C63656 has a built-in watchdog timer that operates with a 256 Hz divided clock from the OSC1 as
the source clock. The watchdog timer starts operating after initial reset, however, it can be stopped by the
software. The watchdog timer must be reset cyclically by the software while it operates. If the watchdog
timer is not reset in at least 3–4 seconds, it generates a non-maskable interrupt (NMI) to the CPU.
Figure 4.2.1.1 is the block diagram of the watchdog timer.
OSC1 dividing signal 256 Hz
Watchdog timer enable signal
Watchdog timer reset signal
Fig. 4.2.1.1 Watchdog timer block diagram
The watchdog timer contains a 10-bit binary counter, and generates the non-maskable interrupt when the
last stage of the counter (0.25 Hz) overflows.
Watchdog timer reset processing in the program's main routine enables detection of program overrun,
such as when the main routine's watchdog timer processing is bypassed. Ordinarily this routine is
incorporated where periodic processing takes place, just as for the timer interrupt routine.
The watchdog timer operates in the HALT mode. If a HALT status continues for 3–4 seconds, the nonmaskable interrupt releases the HALT status.
Watchdog timer
Non-maskable
interrupt (NMI)
4.2.2 Interrupt function
If the watchdog timer is not reset periodically, the non-maskable interrupt (NMI) is generated to the core
CPU. Since this interrupt cannot be masked, it is accepted even in the interrupt disable status (I flag =
"0"). However, it is not accepted when the CPU is in the interrupt mask state until SP1 and SP2 are set as a
pair, such as after initial reset or during re-setting the stack pointer. The interrupt vector of NMI is
assigned to 0100H in the program memory.
26 EPSON S1C63656 TECHNICAL MANUAL
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Watchdog Timer)
4.2.3 I/O memory of watchdog timer
Table 4.2.3.1 shows the I/O address and control bits for the watchdog timer.
Table 4.2.3.1 Control bits of watchdog timer
Address Comment
FF07H
*1 Initial value at initial reset
*2 Not set in the circuit
*3 Constantly "0" when being read
WDEN: Watchdog timer enable register (FF07H•D1)
Selects whether the watchdog timer is used (enabled) or not (disabled).
When "1" is written: Enabled
When "0" is written: Disabled
When "1" is written to the WDEN register, the watchdog timer starts count operation. When "0" is written,
the watchdog timer does not count and does not generate the interrupt (NMI).
At initial reset, this register is set to "1".
Register
D3 D2
00WDEN WDRST
D1 D0 Name Init
R/W WR
Reading: Valid
∗
0
∗
0
WDEN
WDRST
∗1
∗
2
∗
2
1
10
Enable
Disable
Reset
Invalid
Unused
Unused
Watchdog timer enable
Watchdog timer reset (writing)
3
–
3
–
∗
3
Reset
WDRST: Watchdog timer reset (FF07H•D0)
Resets the watchdog timer.
When "1" is written: Watchdog timer is reset
When "0" is written: No operation
Reading: Always "0"
When "1" is written to WDRST, the watchdog timer is reset and restarts immediately after that. When "0"
is written, no operation results.
This bit is dedicated for writing, and is always "0" for reading.
4.2.4 Programming notes
(1) When the watchdog timer is being used, the software must reset it within 3-second cycles.
(2) Because the watchdog timer is set in operation state by initial reset, set the watchdog timer to disabled
state (not used) before generating an interrupt (NMI) if it is not used.
S1C63656 TECHNICAL MANUAL EPSON 27
Page 38
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Oscillation Circuit)
4.3 Oscillation Circuit
4.3.1 Configuration of oscillation circuit
The S1C63656 has two oscillation circuits (OSC1 and OSC3). OSC1 is a crystal oscillation circuit that
supplies the operating clock to the CPU and peripheral circuits. OSC3 is either a CR or a ceramic oscillation circuit. When processing with the S1C63656 requires high-speed operation, the CPU operating clock
can be switched from OSC1 to OSC3 by the software.
If the application needs low-voltage and low-power operations precedence to performance, the OSC3
oscillation circuit and the high-speed operation voltage regulator can be disabled by mask option.
Figure 4.3.1.1 is the block diagram of this oscillation system.
VOSC
VD1
OSC1
oscillation circuit
OSC3
oscillation circuit
Divider
Clock
switch
To peripheral circuits
To CPU
CPU clock selection signal
Oscillation circuit control signal
Voltage regulator for
OSC1 oscillation circuit
High-speed operation
voltage regulator
Mask option
Fig. 4.3.1.1 Oscillation system block diagram
4.3.2 OSC1 oscillation circuit
The OSC1 crystal oscillation circuit generates the main clock for the CPU and the peripheral circuits. The
oscillation frequency is 32.768 kHz (Typ.).
Figure 4.3.2.1 is the block diagram of the OSC1 oscillation circuit.
CGX
X'tal
VSS
OSC1
OSC2
FX
R
DX
R
To CPU
(and peripheral circuits)
CDX
Fig. 4.3.2.1 OSC1 oscillation circuit
VSS
As shown in Figure 4.3.2.1, the crystal oscillation circuit can be configured simply by connecting the
crystal oscillator (X'tal) of 32.768 kHz (Typ.) between the OSC1 and OSC2 terminals and the trimmer
capacitor (C
28 EPSON S1C63656 TECHNICAL MANUAL
GX) between the OSC1 and VSS terminals.
Page 39
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Oscillation Circuit)
4.3.3 OSC3 oscillation circuit
The S1C63656 has built-in the OSC3 oscillation circuit that generates the CPU's sub-clock (Max. 4 MHz)
for high speed operation and the source clock for peripheral circuits needing a high speed clock (programmable timer, FOUT output). The mask option enables selection of the oscillator type from CR
(external R type), CR (built-in R type) and ceramic oscillation circuit. When CR oscillation (external R
type) is selected, only a resistance is required as an external element. When ceramic oscillation is selected,
a ceramic oscillator and two capacitors (gate and drain capacitance) are required. When CR oscillation
(built-in R type) is selected, no external element is required. If the application needs low-voltage and lowpower operations precedence to performance, the OSC3 oscillation circuit and the high-speed operation
voltage regulator can be disabled by mask option.
Figure 4.3.3.1 is the block diagram of the OSC3 oscillation circuit.
C
CR
OSC3
CR
R
OSC4
CR
R
(a) CR oscillation circuit (external R type)
CR
C
To CPU
(and some peripheral circuits)
Oscillation circuit control signal
To CPU
(and some peripheral circuits)
Oscillation circuit control signal
(b) CR oscillation circuit (built-in R type)
C
GC
C
DC
V
SS
OSC3
Ceramic
OSC4
To CPU
FC
R
(c) Ceramic oscillation circuit
R
DC
(and some peripheral circuits)
Oscillation circuit control signal
Fig. 4.3.3.1 OSC3 oscillation circuit
As shown in Figure 4.3.3.1, the CR oscillation circuit (external R type) can be configured simply by
connecting the resistor R
Chapter 7, "Electrical Characteristics" for resistance value of R
CR between the OSC3 and OSC4 terminals when CR oscillation is selected. See
CR.
When ceramic oscillation is selected, the ceramic oscillation circuit can be configured by connecting the
ceramic oscillator (Max. 4 MHz) between the OSC3 and OSC4 terminals, capacitor C
and OSC4 terminals, and capacitor C
DC between the OSC4 and VSS terminals. For both CGC and CDC,
GC between the OSC3
connect capacitors that are about 30 pF. To reduce current consumption of the OSC3 oscillation circuit,
oscillation can be stopped by the software (OSCC register).
Table 4.3.3.1 OSC3 oscillation frequency
Oscillation circuit
Ceramic oscillation
CR oscillation (built-in R type)
CR oscillation (external R type)
Oscillation frequency
Max. 4 MHz (2 MHz
Typ. 1.1 MHz ±30%
200 kHz to 2 MHz
Note
)
Note: When selecting OSC3 for the time base counter clock of the R/f converter, the maximum frequency
of the OSC3 clock is limited to 2 MHz.
S1C63656 TECHNICAL MANUAL EPSON 29
Page 40
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Oscillation Circuit)
4.3.4 Switching of CPU clock
In the system that uses the OSC3 oscillation circuit (selected by mask option), the system clock can be
selected between OSC1 and OSC3 with software (using the CLKCHG register). The control sequence
described below is not necessary in the system that uses the OSC1 oscillation circuit only.
The CPU clock should be switched using the following procedure. Pay special attention to the stability
waiting time for oscillation.
OSC1 → OSC3
1. Set OSCC to "1". (OSC3 oscillation: off → on)
2. Wait 5 msec or more.
3. Set CLKCHG to "1". (CPU clock: OSC1 → OSC3)
Note: It takes at least 5 msec from the time the OSC3 oscillation circuit goes on until the oscillation
stabilizes. Consequently, when switching the CPU operation clock from OSC1 to OSC3, do this
after a minimum of 5 msec have elapsed since the OSC3 oscillation went on.
Further, the oscillation stabilization time varies depending on the external oscillator characteristics
and conditions of use, so allow ample margin when setting the wait time.
OSC3 → OSC1
1. Set CLKCHG to "0". (CPU clock: OSC3 → OSC1)
2. Set OSCC to "0". (OSC3 oscillation: on → off)
Note: When switching the clock form OSC3 to OSC1, use a separate instruction for switching the OSC3
oscillation off. An error in the CPU operation can result if this processing is performed at the same
time by the one instruction.
4.3.5 Clock frequency and instruction execution time
Table 4.3.5.1 shows the instruction execution time according to each frequency of the system clock.
Table 4.3.5.1 Clock frequency and instruction execution time
Clock frequency
OSC1: 32.768 kHz
OSC3: 1.1 MHz
OSC3: 2 MHz
OSC3: 4 MHz
1-cycle instruction 2-cycle instruction 3-cycle instruction
Instruction execution time (µsec)
61 122 183
1.8 3.6 5.5
123
0.5 1 1.5
30 EPSON S1C63656 TECHNICAL MANUAL
Page 41
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Oscillation Circuit)
4.3.6 I/O memory of oscillation circuit
Table 4.3.6.1 shows the I/O address and the control bits for the oscillation circuit.
Note: The control bits for the oscillation circuit described below are effective only when the OSC3
oscillation circuit is used. If the system uses the OSC1 oscillation circuit only, do not change the
default settings.
Table 4.3.6.1 Control bits of oscillation circuit
Address Comment
CLKCHG OSCC 0 0
FF01H
*1 Initial value at initial reset
*2 Not set in the circuit
*3 Constantly "0" when being read
OSCC: OSC3 oscillation control register (FF01H•D2)
Turns the OSC3 oscillation circuit on and off.
When "1" is written: OSC3 oscillation On
When "0" is written: OSC3 oscillation Off
When it is necessary to operate the CPU at high speed, set OSCC to "1". At other times, set it to "0" to
reduce current consumption.
At initial reset, this register is set to "0".
Register
D3 D2
R/W R
Reading: Valid
D1 D0 Name Init
CLKCHG
OSCC
∗
3
0
∗
3
0
–
–
∗1
0
0
∗
2
∗
2
10
OSC3OnOSC1
Off
CPU clock switch
OSC3 oscillation On/Off
Unused
Unused
CLKCHG: CPU system clock switching register (FF01H•D3)
The CPU's operation clock is selected with this register.
When "1" is written: OSC3 clock is selected
When "0" is written: OSC1 clock is selected
Reading: Valid
When the CPU clock is to be OSC3, set CLKCHG to "1"; for OSC1, set CLKCHG to "0".
After turning the OSC3 oscillation on (OSCC = "1"), switching of the clock should be done after waiting 5
msec or more.
At initial reset, this register is set to "0".
S1C63656 TECHNICAL MANUAL EPSON 31
Page 42
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Oscillation Circuit)
4.3.7 Programming notes
(1) It takes at least 5 msec from the time the OSC3 oscillation circuit goes on until the oscillation stabi-
lizes. Consequently, when switching the CPU operation clock from OSC1 to OSC3, do this after a
minimum of 5 msec have elapsed since the OSC3 oscillation went on.
Further, the oscillation stabilization time varies depending on the external oscillator characteristics
and conditions of use, so allow ample margin when setting the wait time.
(2) When switching the clock form OSC3 to OSC1, use a separate instruction for switching the OSC3
oscillation off. An error in the CPU operation can result if this processing is performed at the same
time by the one instruction.
(3) When selecting OSC3 for the time base counter clock of the R/f converter, the maximum frequency of
the OSC3 clock is limited to 2 MHz.
32 EPSON S1C63656 TECHNICAL MANUAL
Page 43
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports)
4.4 Input Ports (K00–K03 and K10–K13)
4.4.1 Configuration of input ports
The S1C63656 has eight bits of general-purpose input ports (K00–K03, K10–K13). Each input port terminal provides an internal pull-down resistor that can be enabled by mask option.
Figure 4.4.1.1 shows the configuration of input port.
V
DD
Interrupt
request
Kxx
Data bus
Address
V
SS
Mask option
Fig. 4.4.1.1 Configuration of input port
Selection of "With pull-down resistor" with the mask option suits input from the push switch, key matrix,
and so forth. When "Gate direct" is selected, the port can be used for slide switch input and interfacing
with other LSIs.
The K00 and K01 input ports can also be used as the Run/Stop and Lap direct inputs for the stopwatch
timer, and the K13 port can also be used as the event counter input for the programmable timer.
4.4.2 Interrupt function
All eight bits of the input ports (K00–K03, K10–K13) provide the interrupt function. The conditions for
issuing an interrupt can be set by the software. Further, whether to mask the interrupt function can be
selected by the software.
Figure 4.4.2.1 shows the configuration of K00–K03 (K10–K13) interrupt circuit.
K00, 10
Data bus
Address
Input comparison
register (KCP00, 10)
Interrupt selection
register (SIK00, 10)
K01, 11
K02, 12
K03, 13
Address
Address
Interrupt factor
flag (IK0, 1)
Address
Interrupt mask
register (EIK0, 1)
Interrupt
request
Address
Fig. 4.4.2.1 Input interrupt circuit configuration
S1C63656 TECHNICAL MANUAL EPSON 33
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports)
The interrupt selection register (SIK) and input comparison register (KCP) are individually set for the
input ports K00–K03 and K10–K13, and can specify the terminals for generating interrupt and interrupt
timing.
The interrupt selection registers (SIK00–SIK03, SIK10–SIK13) select what input of K00–K03 and K10–K13
to use for the interrupt. Writing "1" into an interrupt selection register incorporates that input port into
the interrupt generation conditions. The changing the input port where the interrupt selection register
has been set to "0" does not affect the generation of the interrupt.
The input interrupt timing can select that the interrupt be generated at the rising edge of the input or that
it be generated at the falling edge according to the set value of the input comparison registers (KCP00–
KCP03, KCP10–KCP13).
By setting these two conditions, the interrupt for K00–K03 or K10–K13 is generated when input ports in
which an interrupt has been enabled by the input selection registers and the contents of the input comparison registers have been changed from matching to no matching.
The interrupt mask registers (EIK0, EIK1) enable the interrupt mask to be selected for K00–K03 and K10–
K13.
When the interrupt is generated, the interrupt factor flag (IK0, IK1) is set to "1".
Figure 4.4.2.2 shows an example of an interrupt for K00–K03.
Interrupt selection register
SIK031SIK021SIK011SIK00
0
With the above setting, the interrupt of K00–K03 is generated under the following condition:
Input comparison register
KCP031KCP020KCP011KCP00
0
Input port
K031K020K011K00
(1)
0
(Initial value)
K031K020K011K00
(2)
1
K030K020K011K00
(3)
K030K021K011K00
(4)
1
1
Interrupt generation
Because K00 interrupt is set to disable, interrupt will be
generated when no matching occurs between the
contents of the 3 bits K01–K03 and the 3 bits input
comparison register KCP01–KCP03.
Fig. 4.4.2.2 Example of interrupt of K00–K03
K00 interrupt is disabled by the interrupt selection register (SIK00), so that an interrupt does not occur at
(2). At (3), K03 changes to "0"; the data of the terminals that are interrupt enabled no longer match the
data of the input comparison registers, so that interrupt occurs. As already explained, the condition for
the interrupt to occur is the change in the port data and contents of the input comparison registers from
matching to no matching. Hence, in (4), when the no matching status changes to another no matching
status, an interrupt does not occur. Further, terminals that have been masked for interrupt do not affect
the conditions for interrupt generation.
4.4.3 Mask option
Internal pull-down resistor can be selected for each of the eight bits of the input ports (K00–K03, K10–
K13) with the input port mask option.
When "Gate direct" is selected, take care that the floating status does not occur for the input. Select "With
pull-down resistor" for input ports that are not being used.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports)
4.4.4 I/O memory of input ports
Table 4.4.4.1 shows the I/O addresses and the control bits for the input ports.
Table 4.4.4.1 Control bits of input ports
Address Comment
SIK03 SIK02 SIK01 SIK00
FF20H
FF21H
KCP03 KCP02 KCP01 KCP00
FF22H
SIK13 SIK12 SIK11 SIK10
FF24H
FF25H
KCP13 KCP12 KCP11 KCP10
FF26H
FFE3H
FFE4H
FFF3H
FFF4H
*1 Initial value at initial reset
*2 Not set in the circuit
*3 Constantly "0" when being read
Register
D3 D2
D1 D0 Name Init
R/W
K03 K02 K01 K00
R
KCP03
KCP02
R/W
KCP01
KCP00
R/W
K13 K12 K11 K10
R
KCP13
KCP12
R/W
000EIK0
RR/W
000EIK1
RR/W
000IK0
RR/W
000IK1
RR/W
KCP11
KCP10
0
0
0
0
0
0
0
0
0
0
0
0
SIK03
SIK02
SIK01
SIK00
K03
K02
K01
K00
SIK13
SIK12
SIK11
SIK10
K13
K12
K11
K10
EIK0
EIK1
IK0
IK1
∗1
0
0
0
0
∗
2
–
∗
2
–
∗
2
–
∗
2
–
1
1
1
1
0
0
0
0
∗
2
–
∗
2
–
∗
2
–
∗
2
–
1
1
1
1
∗
3
∗
2
–
∗
3
∗
2
–
∗
3
∗
2
–
0 Enable Mask
∗
3
∗
2
–
∗
3
∗
2
–
∗
3
∗
2
–
0 Enable Mask
∗
3
∗
2
–
∗
3
∗
2
–
∗
3
∗
2
–
0
∗
3
∗
2
–
∗
3
∗
2
–
∗
3
∗
2
–
0
10
Enable
Disable
Enable
Disable
Enable
Disable
Enable
Disable
High
Low
High
Low
High
Low
High
Low
Enable
Disable
Enable
Disable
Enable
Disable
Enable
Disable
High
Low
High
Low
High
Low
High
Low
(R)
(R)
Yes
No
(W)
(W)
Reset
Invalid
(R)
(R)
Yes
No
(W)
(W)
Reset
Invalid
K00–K03 interrupt selection register
K00–K03 input port data
K00–K03 input comparison register
K10–K13 interrupt selection register
K10–K13 input port data
K10–K13 input comparison register
Unused
Unused
Unused
Interrupt mask register (K00–K03)
Unused
Unused
Unused
Interrupt mask register (K10–K13)
Unused
Unused
Unused
Interrupt factor flag (K00–K03)
Unused
Unused
Unused
Interrupt factor flag (K10–K13)
K00–K03: K0 port input port data (FF21H)
K10–K13: K1 port input port data (FF25H)
Input data of the input port terminals can be read with these registers.
When "1" is read: High level
When "0" is read: Low level
Writing: Invalid
The reading is "1" when the terminal voltage of the eight bits of the input ports (K00–K03, K10–K13) goes
high (V
DD), and "0" when the voltage goes low (VSS).
These bits are dedicated for reading, so writing cannot be done.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports)
SIK00–SIK03: K0 port interrupt selection register (FF20H)
SIK10–SIK13: K1 port interrupt selection register (FF24H)
Selects the ports to be used for the K00–K03 and K10–K13 input interrupts.
When "1" is written: Enable
When "0" is written: Disable
Reading: Valid
Enables the interrupt for the input ports (K00–K03, K10–K13) for which "1" has been written into the
interrupt selection registers (SIK00–SIK03, SIK10–SIK13). The input port set for "0" does not affect the
interrupt generation condition.
At initial reset, these registers are set to "0".
KCP00–KCP03: K0 port input comparison register (FF22H)
KCP10–KCP13: K1 port input comparison register (FF26H)
Interrupt conditions for terminals K00–K03 and K10–K13 can be set with these registers.
When "1" is written: Falling edge
When "0" is written: Rising edge
Reading: Valid
The interrupt conditions can be set for the rising or falling edge of input for each of the eight bits (K00–
K03 and K10–K13), through the input comparison registers (KCP00–KCP03 and KCP10–KCP13).
For KCP00–KCP03, a comparison is done only with the ports that are enabled by the interrupt among
K00–K03 by means of the SIK00–SIK03 registers. For KCP10–KCP13, a comparison is done only with the
ports that are enabled by the interrupt among K10–K13 by means of the SIK10–SIK13 registers.
At initial reset, these registers are set to "1".
EIK0: K0 input interrupt mask register (FFE3H•D0)
EIK1: K1 input interrupt mask register (FFE4H•D0)
Masking the interrupt of the input port can be selected with these registers.
When "1" is written: Enable
When "0" is written: Mask
Reading: Valid
With these registers, masking of the input port interrupt can be selected for each of the two systems (K00–
K03, K10–K13).
At initial reset, these registers are set to "0".
IK0: K0 input interrupt factor flag (FFF3H•D0)
IK1: K1 input interrupt factor flag (FFF4H•D0)
These flags indicate the occurrence of input interrupt.
When "1" is read: Interrupt has occurred
When "0" is read: Interrupt has not occurred
When "1" is written: Flag is reset
When "0" is written: Invalid
The interrupt factor flags IK0 and IK1 are associated with K00–K03 and K10–K13, respectively. From the
status of these flags, the software can decide whether an input interrupt has occurred.
The interrupt factor flag is set to "1" when the interrupt condition is established regardless of the interrupt
mask register setting. However, the interrupt does not occur to the CPU when the interrupt is masked.
These flags are reset to "0" by writing "1" to them.
After an interrupt occurs, the same interrupt will occur again if the interrupt enabled state (I flag = "1") is
set or the RETI instruction is executed unless the interrupt factor flag is reset. Therefore, be sure to reset
(write "1" to) the interrupt factor flag in the interrupt service routine before shifting to the interrupt
enabled state.
At initial reset, these flags are set to "0".
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports)
4.4.5 Programming notes
(1) When input ports are changed from high to low by pull-down resistors, the fall of the waveform is
delayed on account of the time constant of the pull-down resistor and input gate capacitance. Hence,
when fetching input ports, set an appropriate waiting time.
Particular care needs to be taken of the key scan during key matrix configuration.
Make this waiting time the amount of time or more calculated by the following expression.
10 × C × R
C: terminal capacitance 5 pF + parasitic capacitance ? pF
R: pull-down resistance 375 kΩ (Max.)
(2) After an interrupt occurs, the same interrupt will occur again if the interrupt enabled state (I flag =
"1") is set or the RETI instruction is executed unless the interrupt factor flag is reset. Therefore, be sure
to reset (write "1" to) the interrupt factor flag in the interrupt service routine before shifting to the
interrupt enabled state.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports)
4.5 Output Ports (R00–R03)
4.5.1 Configuration of output ports
The S1C63656 has four bits of general output ports.
Output specifications of the output ports can be selected individually with the mask option. Two kinds of
output specifications are available: complementary output and P-channel open drain output.
Figure 4.5.1.1 shows the configuration of the output port.
V
Address
High impedance
control register
DD
Data bus
Data register
Address
Mask option
Rxx
V
SS
Fig. 4.5.1.1 Configuration of output port
The R02 and R03 output terminals are shared with special output terminals (TOUT, FOUT), and this
function is selected by the software.
At initial reset, these are all set to the general purpose output port.
Table 4.5.1.1 shows the setting of the output terminals by function selection.
Table 4.5.1.1 Function setting of output terminals
Terminal
name
R00
R01
R02
R03
Terminal status
at initial reset
R00 (Low output)
R01 (Low output)
R02 (Low output)
R03 (Low output)
Special output
TOUT FOUT
R00 R00
R01 R01
TOUT
FOUT
When using the output port (R02, R03) as the special output port, the data register must be fixed at "1"
and the high impedance control register must be fixed at "0" (data output).
4.5.2 Mask option
Output specifications of the output ports are selected by mask option.
Either complementary output or P-channel open drain output can be selected individually (in 1-bit units).
However, when P-channel open drain output is selected, do not apply a voltage exceeding the power
supply voltage to the output port.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports)
4.5.3 High impedance control
The output ports can be set into a high impedance status. This control is done using the high impedance
control registers.
The high impedance control registers are provided to correspond with the output ports as shown below.
High impedance control register Corresponding output port
R00HIZ R00 (1 bit)
R01HIZ R01 (1 bit)
R02HIZ R02 (1 bit)
R03HIZ R03 (1 bit)
When "1" is written to the high impedance control register, the corresponding output port terminal goes
into high impedance status. When "0" is written, the port outputs a signal according to the data register.
4.5.4 Special output
In addition to the regular DC output, special output can be selected for the output ports R02 and R03 as
shown in Table 4.5.4.1 with the software.
Figure 4.5.4.1 shows the configuration of the R02 and R03 output ports.
Table 4.5.4.1 Special output
Terminal
R03
R02
Special output
FOUT
TOUT
Output control register
FOUTE
PTOUT
FOUT
Register
FOUTE
R03
(FOUT)
R02
(TOUT)
Data bus
Register
R03
Register
R03HIZ
TOUT
Register
PTOUT
Register
R02
Register
R02HIZ
Fig. 4.5.4.1 Configuration of R02 and R03 output ports
At initial reset, the output port data register is set to "0" and the high impedance control register is set to
"0". Consequently, the output terminal goes low (VSS).
When using the output port (R02, R03) as the special output port, fix the data register (R02, R03) at "1"
and the high impedance control register (R02HIZ, R03HIZ) at "0" (data output). The respective signal
should be turned on and off using the special output control register.
Note: • Be aware that the output terminal is fixed at a low (VSS) level the same as the DC output if "0" is
written to the R02 and R03 registers when the special output has been selected.
• Be aware that the output terminal shifts into high impedance status when "1" is written to the
high impedance control register (R02HIZ, R03HIZ).
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports)
•TOUT (R02)
The R02 terminal can output a TOUT signal.
The TOUT signal is the clock that is output from the programmable timer, and can be used to provide
a clock signal to an external device.
To output the TOUT signal, fix the R02 register at "1" and the R02HIZ register at "0", and turn the
signal on and off using the PTOUT register. It is, however, necessary to control the programmable
timer.
Refer to Section 4.10, "Programmable Timer" for details of the programmable timer.
Note: A hazard may occur when the TOUT signal is turned on and off.
Figure 4.5.4.2 shows the output waveform of the TOUT signal.
R02HIZ register
R02 register
PTOUT register
TOUT output
Fix at "0"
Fix at "1"
"1""0" "0"
Fig. 4.5.4.2 Output waveform of TOUT signal
• FOUT (R03)
The R03 terminal can output an FOUT signal.
The FOUT signal is a clock (f
f
OSC1 clock has divided in the internal circuit, and can be used to provide a clock signal to an external
device.
To output the FOUT signal, fix the R03 register at "1" and the R03HIZ register at "0", and turn the
signal on and off using the FOUTE register.
The frequency of the output clock may be selected from among 4 types shown in Table 4.5.4.2 by
setting the FOFQ0 and FOFQ1 registers.
When fOSC3 is selected for the FOUT signal frequency, it is necessary to control the OSC3 oscillation
circuit before output.
Refer to Section 4.3, "Oscillation Circuit", for the control and notes.
f
OSC3 is available when a mask option for using the OSC3 oscillation circuit is selected. If the system
uses the OSC1 oscillation circuit only, do not set the FOFQ register to "11".
OSC1 or fOSC3) that is output from the oscillation circuit or a clock that the
Table 4.5.4.2 FOUT clock frequency
FOFQ1
fOSC1: Clock that is output from the OSC1 oscillation circuit
fOSC3: Clock that is output from the OSC3 oscillation circuit
FOFQ0
1
1
0
0
1
0
1
0
Clock frequency
f
OSC3
f
OSC1
f
OSC1
× 1/8
f
OSC1
× 1/64
Note: A hazard may occur when the FOUT signal is turned on and off.
Figure 4.5.4.3 shows the output waveform of the FOUT signal.
R03HIZ register
R03 register
FOUTE register
FOUT output
Fix at "0"
Fix at "1"
"1""0" "0"
Fig. 4.5.4.3 Output waveform of FOUT signal
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports)
4.5.5 I/O memory of output ports
Table 4.5.5.1 shows the I/O addresses and control bits for the output ports.
Table 4.5.5.1 Control bits of output ports
Address Comment
FOUTE SWDIR FOFQ1 FOFQ0
FF06H
R03HIZ R02HIZ R01HIZ R00HIZ
FF30H
FF31H
FFC1H
*1 Initial value at initial reset
*2 Not set in the circuit
*3 Constantly "0" when being read
Register
D3 D2
R03 R02 R01 R00
00CHSEL0 PTOUT
RR/W
D1 D0 Name Init
R/W
R/W
R/W
FOUTE
SWDIR
FOFQ1
FOFQ0
R03HIZ
R02HIZ
R01HIZ
R00HIZ
R03
R02
R01
R00
∗
3
0
∗
3
0
CHSEL0
PTOUT
∗1
10
0
Enable Disable
0
0
0
0
Hi-Z
Hi-Z
Hi-Z
Hi-Z
High
High
High
High
Output
Output
Output
Output
0
0
0
0
0
0
0
∗
2
–
∗
2
–
00Timer 1OnTimer 0
FOUT output enable
Stopwatch direct input switch
0: K00=Run/Stop, K01=Lap 1: K00=Lap, K01=Run/Stop
FOUT
frequency
selection
R03 (FOUTE=0)/FOUT (FOUTE=1) Hi-Z control
R02 (PTOUT=0)/TOUT (PTOUT=1) Hi-Z control
R01 Hi-Z control
R00 Hi-Z control
R03
Low
Low
Low
Low
Off
output port data (
R02
output port data (
R01
output port data
R00
output port data
Unused
Unused
TOUT output selection
TOUT output control
[FOFQ1, 0]
Frequency
FOUTE=0
PTOUT=0
1
0
OSC1/64
f
) Fix at "1" when
) Fix at "1" when
fOSC1/82fOSC1
FOUT
TOUT
f
is used.
is used.
3
OSC3
R00HIZ–R03HIZ: R0 port high impedance control register (FF30H)
Controls high impedance output of the output port.
When "1" is written: High impedance
When "0" is written: Data output
Reading: Valid
By writing "0" to the high impedance control register, the corresponding output terminal outputs according to the data register. When "1" is written, it shifts into high impedance status.
When the output ports R02 and R03 are used for special output (TOUT, FOUT), fix the R02HIZ register
and the R03HIZ register at "0" (data output).
At initial reset, these registers are set to "0".
R00–R03: R0 output port data register (FF31H)
Set the output data for the output ports.
When "1" is written: High level output
When "0" is written: Low level output
Reading: Valid
The output port terminals output the data written in the corresponding data registers without changing
it. When "1" is written to the register, the output port terminal goes high (V
the output port terminal goes low (V
SS).
DD), and when "0" is written,
When the output ports R02 and R03 are used for special output (TOUT, FOUT), fix the R02 register and
the R03 register at "1".
At initial reset, these registers are all set to "0".
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports)
FOUTE: FOUT output control register (FF06H•D3)
Controls the FOUT output.
When "1" is written: FOUT output On
When "0" is written: FOUT output Off
Reading: Valid
By writing "1" to the FOUTE register when the R03 register has been set to "1" and the R03HIZ register
has been set to "0", the FOUT signal is output from the R03 terminal. When "0" is written, the R03 terminal goes low (V
SS).
When using the R03 output port for DC output, fix this register at "0".
At initial reset, this register is set to "0".
FOFQ0, FOFQ1: FOUT frequency selection register (FF06H•D0, D1)
Selects a frequency of the FOUT signal.
Table 4.5.5.2 FOUT clock frequency
FOFQ1
FOFQ0
1
1
0
0
1
0
1
0
Clock frequency
OSC3
f
f
OSC1
f
OSC1
× 1/8
OSC1
× 1/64
f
At initial reset, this register is set to "0".
Note: f
OSC3
is available when a mask option for using the OSC3 oscillation circuit is selected. If the
system uses the OSC1 oscillation circuit only, do not set the FOFQ register to "11".
PTOUT: TOUT output control register (FFC1H•D0)
Controls the TOUT output.
When "1" is written: TOUT output On
When "0" is written: TOUT output Off
Reading: Valid
By writing "1" to the PTOUT register when the R02 register has been set to "1" and the R02HIZ register
has been set to "0", the TOUT signal is output from the R02 terminal. When "0" is written, the R02 terminal goes high (V
DD).
When using the R02 output port for DC output, fix this register at "0".
At initial reset, this register is set to "0".
4.5.6 Programming notes
(1) When using the output port (R02, R03) as the special output port, fix the data register (R02, R03) at "1"
and the high impedance control register (R02HIZ, R03HIZ) at "0" (data output).
Be aware that the output terminal is fixed at a low (V
written to the R02 and R03 registers when the special output has been selected.
Be aware that the output terminal shifts into high impedance status when "1" is written to the high
impedance control register (R02HIZ, R03HIZ).
(2) A hazard may occur when the FOUT signal and the TOUT signal are turned on and off.
(3) When f
OSC3 is selected for the FOUT signal frequency, it is necessary to control the OSC3 oscillation
circuit before output. Refer to Section 4.3, "Oscillation Circuit", for the control and notes.
f
OSC3 is available when a mask option for using the OSC3 oscillation circuit is selected. If the system
uses the OSC1 oscillation circuit only, do not set the FOFQ register to "11".
SS) level the same as the DC output if "0" is
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (I/O Ports)
4.6 I/O Ports (P00–P03 and P10–P13)
4.6.1 Configuration of I/O ports
The S1C63656 has eight bits of general-purpose I/O ports. Figure 4.6.1.1 shows the configuration of the I/
O port.
Pull-down control
Address
register (PUL)
Address
Address
Data bus
Address
Data
register
I/O control
register (IOC)
Pxx
Mask
option
VSS
Fig. 4.6.1.1 Configuration of I/O port
The I/O port terminals P10 to P13 are shared with the serial interface input/output terminals. The
software can select the function to be used.
At initial reset, these terminals are all set to the I/O port.
Table 4.6.1.1 shows the setting of the input/output terminals by function selection.
Table 4.6.1.1 Function setting of input/output terminals
Terminal
P00–P03
P10
P11
P12
P13
∗ When "with pull-down resistor" is selected by the mask option
(high impedance when "gate direct" is set)
Terminal status
at initial reset
P00–P03 (Input & pull-down ∗)
P10 (Input & pull-down ∗)
P11 (Input & pull-down ∗)
P12 (Input & pull-down ∗)
P13 (Input & pull-down ∗)
SOUT(O)
Master
P00–P03
SIN(I)
SCLK(O)
P13
Serial I/F
Slave
P00–P03
SIN(I)
SOUT(O)
SCLK(I)
SRDY(O)
When these ports are used as I/O ports, the ports can be set to either input mode or output mode individually (in 1-bit unit). Modes can be set by writing data to the I/O control registers.
Refer to Section 4.11, "Serial Interface", for control of the serial interface.
S1C63656 TECHNICAL MANUAL EPSON 43
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (I/O Ports)
4.6.2 Mask option
The output specification of each I/O port during output mode can be selected from either complementary output or P-channel open drain output by mask option. This selection can be done in 1-bit units.
When P-channel open drain output is selected, do not apply a voltage exceeding the power supply
voltage to the port.
The mask option also permits selection of whether the pull-down resistor is used or not during input
mode. This selection can be done in 1-bit units.
When "without pull-down" during the input mode is selected, take care that the floating status does not
occur.
The pull-down resistor for input mode and output specification (complementary output or P-channel
open drain output) selected by mask option are effective even when I/O ports are used for input/output
of the serial interface.
4.6.3 I/O control registers and input/output mode
Input or output mode can be set for the I/O ports by writing data into the corresponding I/O control
registers IOCxx.
To set the input mode, write "0" to the I/O control register. When an I/O port is set to input mode, it
becomes high impedance status and works as an input port.
However, when the pull-down explained in the following section has been set by software, the input line
is pulled down only during this input mode.
To set the output mode, write "1" is to the I/O control register. When an I/O port is set to output mode, it
works as an output port, it outputs a high level (V
(V
SS) when the port output data is "0".
If perform the read out in each mode; when output mode, the register value is read out, and when input
mode, the port value is read out.
At initial reset, the I/O control registers are set to "0", and the I/O ports enter the input mode.
The I/O control registers of the ports that are set as input/output for the serial interface can be used as
general purpose registers that do not affect the I/O control. (See Table 4.6.1.1.)
DD) when the port output data is "1", and a low level
4.6.4 Pull-down during input mode
A pull-down resistor that operates during the input mode is built into each I/O port of the S1C63656.
Mask option can set the use or non-use of this pull-down.
The pull-down resistor becomes effective by writing "1" to the pull-down control register PULxx that
corresponds to each port, and the input line is pulled down during the input mode. When "0" has been
written, no pull-down is done.
At initial reset, the pull-down control registers are set to "1".
The pull-down control registers of the ports in which "gate direct" has been selected can be used as
general purpose registers.
Even when "with pull-down" has been selected, the pull-down control registers of the ports, that are set
as output for the serial interface, can be used as general purpose registers that do not affect the pull-down
control. (See Table 4.6.1.1.)
The pull-down control registers of the port, that are set as input for the serial interface, function the same
as the I/O port.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (I/O Ports)
4.6.5 I/O memory of I/O ports
Table 4.6.5.1 shows the I/O addresses and the control bits for the I/O ports.
Table 4.6.5.1 Control bits of I/O ports
Address Comment
IOC03 IOC02 IOC01 IOC00
FF40H
PUL03 PUL02 PUL01 PUL00
FF41H
FF42H
IOC13 IOC12 IOC11 IOC10
FF44H
PUL13 PUL12 PUL11 PUL10
FF45H
(XSRDY)
FF46H
FF70H
*1 Initial value at initial reset
*2 Not set in the circuit
*3 Constantly "0" when being read
Register
D3 D2
D1 D0 Name Init
IOC03
IOC02
R/W
IOC01
IOC00
PUL03
PUL02
R/W
PUL01
PUL00
P03 P02 P01 P00
R/W
IOC13
IOC12
IOC11
R/W
IOC10
PUL13
PUL12
PUL11
P13
R/W
P12
(XSCLK)
P11
(SOUT)
PUL10
P10
(SIN)
R/W
0
0 ESOUT SCTRG ESIF
ESOUT
SCTRG
RR/W
ESIF
P03
P02
P01
P00
P13
P12
P11
P10
∗1
10
0
Output
Input
0
Output
Input
0
0
1
1
1
1
–
–
–
–
0
0
∗
∗
∗
∗
2
2
2
2
Output
Output
On
On
On
On
High
High
High
High
Output
Output
P00–P03 I/O control register
Input
Input
Off
Off
P00–P03 pull-down control register
Off
Off
Low
Low
P00–P03 I/O port data
Low
Low
Input
P13 I/O control register
functions as a general-purpose register when SIF (slave) is selected
Input
P12 I/O control register (ESIF=0)
functions as a general-purpose register when SIF is selected
0
P11 I/O control register (ESIF=0)
Input
Output
functions as a general-purpose register when SIF is selected
0
P10 I/O control register (ESIF=0)
Input
Output
functions as a general-purpose register when SIF is selected
1
On
1
On
1
P13 pull-down control register
functions as a general-purpose register when SIF (slave) is selected
Off
P12 pull-down control register (ESIF=0)
functions as a general-purpose register when SIF (master) is selected
SCLK (I) pull-down control register when SIF (slave) is selected
Off
P11 pull-down control register (ESIF=0)
Off
On
functions as a general-purpose register when SIF is selected
1
P10 pull-down control register (ESIF=0)
Off
On
SIN pull-down control register
∗
2
–
–
∗
2
High
High
Low
P13 I/O port data
functions as a general-purpose register when SIF (slave) is selected
Low
P12 I/O port data (ESIF=0)
functions as a general-purpose register when SIF is selected
∗
–
2
High
Low
P11 I/O port data (ESIF=0)
functions as a general-purpose register when SIF is selected
∗
–
2
High
Low
P10 I/O port data (ESIF=0)
functions as a general-purpose register when SIF is selected
∗
3
∗
2
–
0
0
0
Enable
Trigger
Run
SIF
Unused
SOUT enable
Disable
Serial I/F clock trigger (writing)
Invalid
Serial I/F clock status (reading)
Stop
Serial I/F enable (P1 port function selection)
I/O
when SIF is selected
S1C63656 TECHNICAL MANUAL EPSON 45
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (I/O Ports)
(1) Selection of port function
ESIF: Serial interface enable register (FF70H•D0)
Selects function for P10–P13.
When "1" is written: Serial interface input/output port
When "0" is written: I/O port
Reading: Valid
When using the serial interface, write "1" to this register and when P10–P13 are used as the I/O port,
write "0". The configuration of the terminals within P10–P13 that are used for the serial interface is
decided by the mode selected with the SCS1 and SCS0 registers (see Section 4.11).
In the slave mode, all the P10–P13 ports are set to the serial interface input/output port. In the master
mode, P10–P12 are set to the serial interface input/output port and P13 can be used as the I/O port.
Furthermore, when the SOUT terminal is disabled (ESOUT = "0"), P11 can be used as the I/O port.
At initial reset, this register is set to "0".
(2) I/O port control
P00–P03: P0 I/O port data register (FF42H)
P10–P13: P1 I/O port data register (FF46H)
I/O port data can be read and output data can be set through these registers.
• When writing data
When "1" is written: High level
When "0" is written: Low level
When an I/O port is set to the output mode, the written data is output unchanged from the I/O port
terminal. When "1" is written as the port data, the port terminal goes high (V
the terminal goes low (V
SS).
DD), and when "0" is written,
Port data can be written also in the input mode.
• When reading data
When "1" is read: High level
When "0" is read: Low level
The terminal voltage level of the I/O port is read out. When the I/O port is in the input mode the voltage
level being input to the port terminal can be read out; in the output mode the register value can be read.
When the terminal voltage is high (V
voltage is low (V
SS) the data is "0".
DD) the port data that can be read is "1", and when the terminal
When "with pull-down resistor" has been selected with the mask option and the PUL register is set to "1",
the built-in pull-down resistor goes on during input mode, so that the I/O port terminal is pulled down.
The data registers of the port, which are set for the input/output of the serial interface (P10–P13), become
general-purpose registers that do not affect the input/output.
Note: When in the input mode, I/O ports are changed from high to low by pull-down resistor, the fall of
the waveform is delayed on account of the time constant of the pull-down resistor and input gate
capacitance. Hence, when fetching input ports, set an appropriate wait time.
Particular care needs to be taken of the key scan during key matrix configuration.
Make this waiting time the amount of time or more calculated by the following expression.
10
×
C × R
C: terminal capacitance 5 pF + parasitic capacitance ? pF
R: pull-down resistance 375 k
Ω
(Max.)
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (I/O Ports)
IOC00–IOC03: P0 port I/O control register (FF40H)
IOC10–IOC13: P1 port I/O control register (FF44H)
The input and output modes of the I/O ports are set with these registers.
When "1" is written: Output mode
When "0" is written: Input mode
Reading: Valid
The input and output modes of the I/O ports are set in 1-bit unit.
Writing "1" to the I/O control register makes the corresponding I/O port enter the output mode, and
writing "0" induces the input mode.
At initial reset, these registers are all set to "0", so the I/O ports are in the input mode.
The I/O control registers of the port, which are set for the input/output of the serial interface (P10–P13),
become general-purpose registers that do not affect the input/output.
PUL00–PUL03: P0 port pull-down control register (FF41H)
PUL10–PUL13: P1 port pull-down control register (FF45H)
The pull-down during the input mode are set with these registers.
When "1" is written: Pull-down On
When "0" is written: Pull-down Off
Reading: Valid
The built-in pull-down resistor which is turned on during input mode is set to enable in 1-bit units. (The
pull-down resistor is included into the ports selected by mask option.)
By writing "1" to the pull-down control register, the corresponding I/O ports are pulled down (during
input mode), while writing "0" disables the pull-down function.
At initial reset, these registers are all set to "1", so the pull-down function is enabled.
The pull-down control registers of the ports in which the pull-down resistor is not included become the
general purpose register. The registers of the ports that are set as output for the serial interface can also be
used as general purpose registers that do not affect the pull-down control.
The pull-down control registers of the port that are set as input for the serial interface function the same
as the I/O port.
4.6.6 Programming note
When in the input mode, I/O ports are changed from high to low by pull-down resistor, the fall of the
waveform is delayed on account of the time constant of the pull-down resistor and input gate capacitance. Hence, when fetching input ports, set an appropriate wait time.
Particular care needs to be taken of the key scan during key matrix configuration.
Make this waiting time the amount of time or more calculated by the following expression.
10 × C × R
C: terminal capacitance 5 pF + parasitic capacitance ? pF
R: pull-down resistance 375 kΩ (Max.)
S1C63656 TECHNICAL MANUAL EPSON 47
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)
4.7 LCD Driver (COM0–COM3, SEG0–SEG37)
4.7.1 Configuration of LCD driver
The S1C63656 has four common terminals (COM0–COM3) and 38 segment terminals (SEG0–SEG37), so
that it can drive an LCD with a maximum of 152 (38 × 4) segments.
The driving method is 1/4 duty or 1/3 duty dynamic drive with three voltages (1/3 bias), V
V
C3.
LCD display on/off can be controlled by the software.
4.7.2 Power supply for LCD driving
The power supply for driving LCD can be selected from the internal power supply and an external power
supply.
C1, VC2 and
When the internal power supply is selected, the LCD drive voltages V
C1–VC3 are generated by the built-in
LCD system voltage circuit. The LCD system voltage circuit is turned on and off using the LPWR register.
When LPWR is set to "1", the LCD system voltage circuit outputs the LCD drive voltages V
LCD driver. The LCD system voltage circuit generates V
generates two other voltages (V
C2 = 2VC1, VC3 = 3VC1) by boosting VC1.
C1 with the voltage regulator built-in, and
C1–VC3 to the
When using an external power supply, select the voltage from the following 3 types and supply the LCD
drive voltage to the V
1) External power supply 1/3 bias (for 4.5 V panel) VDD = V
2) External power supply 1/3 bias (for 3.0 V panel) VDD = V
C1–VC3 terminals.
C2
C3
3) External power supply 1/2 bias (for 3.0 V panel) VDD = VC3, VC1 = VC2 (static drive function is available)
Note that the power control using the LPWR register is necessary even if an external power supply is
used. SEG output ports that are set for DC output by the mask option operate same as the output (R) port
regardless of the power on/off control by the LPWR register.
4.7.3 Control of LCD display and drive waveform
(1)Display on/off control
The S1C63656 incorporates the ALON and ALOFF registers to blink display. When "1" is written to
ALON, all the segments go on, and when "1" is written to ALOFF, all the segments go off. At such a
time, an on waveform or an off waveform is output from SEG terminals. When "0" is written to these
registers, normal display is performed. Furthermore, when "1" is written to both of the ALON and
ALOFF, ALON (all on) has priority over the ALOFF (all off).
(2)Setting of drive duty
In the S1C63656, the drive duty can be set to 1/4 or 1/3 using the LDUTY1 and LDUTY0 registers as
shown in Table 4.7.3.1.
Table 4.7.3.1 LCD drive duty setting
LDUTY1
LDUTY0
1
1
0
0
1
0
1
0
Drive duty
1/3
–
–
1/4
Common terminal used
COM0–COM2
–
–
COM0–COM3
Maximum segment number
114 (38 × 3)
–
–
152 (38 × 4)
Table 4.7.3.2 shows the frame frequency corresponding to the drive duty.
Table 4.7.3.2 Frame frequency
OSC1 oscillation frequency
32.768 kHz
When 1/3 duty is selected
42.7 Hz
When 1/4 duty is selected
32 Hz
Figures 4.7.3.1 and 4.7.3.2 show the dynamic drive waveform according to the duty.
48 EPSON S1C63656 TECHNICAL MANUAL
Page 59
COM0
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)
V
C3
V
C2
V
C1
V
SS
COM1
COM2
COM3
SEG0
|
SEG37
• • •
LCD lighting status
COM0
COM1
COM2
COM3
SEG0–37
Not lit
Lit
V
C2
V
C1
V
C3
V
C2
V
C1
V
SS
Frame
Fig. 4.7.3.1 Dynamic drive waveform for 1/4 duty
S1C63656 TECHNICAL MANUAL EPSON 49
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)
COM0
C3
V
V
C2
V
C1
V
SS
COM1
COM2
COM3
SEG0
|
SEG37
• • •
LCD lighting status
COM0
COM1
COM2
SEG0–37
V
C2
V
C1
V
C2
V
C1
V
C3
V
C2
V
C1
V
SS
Not lit
Lit
Frame
Fig. 4.7.3.2 Dynamic drive waveform for 1/3 duty
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)
(3)Static drive
The S1C63656 provides software setting of the LCD static drive. However, this function is available
only when "External power supply 1/2 bias (for 3.0 V panel)" is selected by mask option.
To set in static drive, write "1" to the common output signal control register STCD. Then, by writing
"1" to any one of COM0 to COM3 (display memory) corresponding to the SEG terminal, the SEG
terminal outputs a static on waveform. When all the COM0 to COM3 bits are set to "0", the SEG
terminal outputs a dynamic off waveform.
Figure 4.7.3.3 shows the static drive waveform.
LCD lighting status
COM0
COM1
COM2
COM3
Not lit
SEG0–37
Lit
COM
0–3
SEG
0–37
Frame frequency
Fig. 4.7.3.3 Static drive waveform
C3
-V
-V
C2
-V
C1
-V
SS
-V
C3
-V
C2
-V
C1
-V
SS
-V
C3
-V
C2
-V
C1
-V
SS
Note: To use the static drive function, select the "External power supply 1/2 bias (for 3.0 V panel)" mask
option. When an option for using the internal power supply or a 1/3 bias external power supply is
selected, static drive cannot be set using the STCD register.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)
4.7.4 Display memory
The display memory is allocated to F000H–F02FH in the data memory area and each data bit can be
allocated to an segment terminal (SEG0–SEG37) by mask option.
When a bit in the display memory is set to "1", the corresponding LCD segment goes on, and when it is
set to "0", the segment goes off.
At initial reset, the data memory content becomes undefined hence, there is need to initialize using the
software.
The display memory has read/write capability, and the addresses that have not been used for LCD
display can be used as general purpose registers.
4.7.5 Segment option
Segment allocation
The LCD driver has a segment decoder built-in, and the data bit (D0–D3) of the optional address in
the display memory area (F000H–F02FH) can be allocated to the optional segment. This makes design
easy by increasing the degree of freedom with which the liquid crystal panel can be designed.
Figure 4.7.5.1 shows an example of the relationship between the LCD segments (on the panel) and the
display memory for the case of 1/4 duty.
Address
F020H
F021H
D3
Data
D2
d
p
D1
c
g
D0
b
f
a
e
SEG10
SEG11
Common 0 Common 1 Common 2
21, D1
(f)
20, D0
(a)
21, D0
(e)
21, D2
(g)
20, D2
(c)
20, D1
(b)
Common 3
20, D3
(d)
21, D3
(p)
Display memory allocation
Pin address allocation
a
f
g
e
c
d
SEG10 SEG11
b
Common 0
p
Common 1
Common 2
Common 3
Fig. 4.7.5.1 Segment allocation
Output specification
1. The segment terminals (SEG0–SEG37) can be selected with the mask option in pairs∗ for either
segment signal output or DC output (V
When DC output is selected, the data corresponding to COM0 of each segment terminal is output.
2. When DC output is selected, either complementary output or N-channel open drain output can be
selected for each terminal with the mask option.
DD and VSS binary output).
∗ The terminal pairs are combination of SEG2 × n and SEG2 × n + 1 (where n is an integer from 0 to 18).
52 EPSON S1C63656 TECHNICAL MANUAL
Page 63
Pin
■
■ C■
■
name
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
SEG32
SEG33
SEG34
SEG35
SEG36
SEG37
<address> H:
H L D
COM0
RAM data high-order address (0–9)
L:
RAM data low-order address (0–F)
D:
Data bit (0–3)
COM1
H L D
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)
Segment option list
Address (F0xx)
COM2
H L D
<Output specification> S:
COM3
H L D
C:
N:
Output specification
SEG output■ S
DC output■ C■ N
SEG output
DC output
SEG output■ S
DC output■ C■ N
SEG output■ S
DC output■ C■ N
SEG output■ S
DC output■ C■ N
SEG output■ S
DC output■ C■ N
SEG output
DC output■ C■ N
SEG output■ S
DC output■ C■ N
SEG output■ S
DC output■ C■ N
SEG output■ S
DC output■ C■ N
SEG output■ S
DC output■ C■ N
SEG output■ S
DC output■ C■ N
SEG output■ S
DC output■ C■ N
SEG output■ S
DC output■ C■ N
SEG output■ S
DC output■ C■ N
SEG output■ S
DC output■ C■ N
SEG output■ S
DC output■ C■ N
SEG output■ S
DC output■ C■ N
SEG output■ S
DC output■ C■ N
Segment output
Complementary output
Nch open drain output
S
S
N
S1C63656 TECHNICAL MANUAL EPSON 53
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)
4.7.6 LCD contrast adjustment
When "Internal power supply (normal mode)" is selected by mask option for the LCD drive power,
software can adjust the LCD contrast.
It is realized by controlling the voltages V
The contrast can be adjusted to 16 levels as shown in Table 4.7.6.1. V
1.03 to 1.40 V, and other voltages change according to V
No.
LC3
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
8
1
9
1
10
1
11
1
12
1
13
1
14
1
15
1
C1, VC2 and VC3 output from the LCD system voltage circuit.
C1 is changed within the range from
C1.
Table 4.7.6.1 LCD contrast
LC2
LC1
LC0
VC1 (V)
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
0
1.03
1
1.06
0
1.09
1
1.12
0
1.15
1
1.18
0
1.20
1
1.23
0
1.26
1
1.28
0
1.30
1
1.32
0
1.34
1
1.36
0
1.38
1
1.40
Contrast
light
dark
At initial reset, the LC0–LC3 are set to 0000B. The software should initialize the register to get the desired
contrast.
When an external power supply is selected by mask option, the LC0–LC3 register becomes invalid.
Furthermore, the contrast adjustment function cannot be used when "Internal power supply (low-power
mode)" is selected. Setting the above register is ignored.
In this case, the V
C1 voltage is fixed at 0.98 V (Typ.).
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)
4.7.7 I/O memory of LCD driver
Table 4.7.7.1 shows the I/O addresses and the control bits for the LCD driver. Figure 4.7.7.1 shows the
display memory map.
Table 4.7.7.1 Control bits of LCD driver
Address Comment
LDUTY1 LDUTY0 STCD LPWR
FF60H
FF61H
FF62H
*1 Initial value at initial reset
*2 Not set in the circuit
*3 Constantly "0" when being read
Register
D3 D2
0 ALOFF ALON 0
RRR/W
LC3 LC2 LC1 LC0
D1 D0 Name Init
R/W
R/W
LDUTY1
LDUTY0
STCD
LPWR
∗
3
0
ALOFF
ALON
∗
3
0
LC3
LC2
LC1
LC0
∗1
10
0
0
00StaticOnDynamic
∗
2
–
1
All Off
All On
Normal
Normal
0
–
0
0
0
0
∗
2
LCD drive duty
switch
LCD drive switch
LCD power On/Off
Off
Unused
LCD all Off control
LCD all On control
Unused
LCD contrast adjustment
[LC3–0]
Contrast
[LDUTY1, 0]
Duty
0
Light––15Dark
1/4
0
1,2–3
1/3
Address
Base
F000H
F010H
F020H
Low
0123456789ABCDE
Display memory (48 words × 4 bits)
R/W
F
Fig. 4.7.7.1 Display memory map
LPWR: LCD power control (on/off) register (FF60H•D0)
Turns the LCD system voltage circuit on and off.
When "1" is written: On
When "0" is written: Off
Reading: Valid
When "1" is written to the LPWR register, the LCD system voltage circuit goes on and generates the LCD
drive voltage. When "0" is written, all the LCD drive voltages go to V
SS level.
It takes about 100 msec for the LCD drive voltage to stabilize after starting up the LCD system voltage
circuit by writing "1" to the LPWR register.
This control does not affect to SEG terminals that have been set for DC output.
At initial reset, this register is set to "0".
LDUTY0, LDUTY1: LCD drive duty switching register (FF60H•D2, D3)
Selects the LCD drive duty.
Table 4.7.7.2 Drive duty setting
LDUTY1
LDUTY0
1
1
0
0
1
0
1
0
Drive duty
1/3
–
–
1/4
Common terminal used
COM0–COM2
–
–
COM0–COM3
Maximum segment number
114 (38 × 3)
–
–
152 (38 × 4)
At initial reset, this register is set to "0".
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)
STCD: LCD drive switch register (FF60H•D1)
Switches the LCD driving method.
When "1" is written: Static drive
When "0" is written: Dynamic drive
Reading: Valid
By writing "1" to STCD, static drive is selected, and dynamic drive is selected when "0" is written.
At initial reset, this register is set to "0".
ALON: LCD all on control register (FF61H•D1)
Displays the all LCD segments on.
When "1" is written: All LCD segments displayed
When "0" is written: Normal display
Reading: Valid
By writing "1" to the ALON register, all the LCD segments go on, and when "0" is written, it returns to
normal display. This function outputs an on waveform to the SEG terminals, and segments not affect the
content of the display memory. ALON has priority over ALOFF.
At initial reset, this register is set to "0".
ALOFF: LCD all OFF control register (FF61H•D2)
Fade outs the all LCD segments.
When "1" is written: All LCD segments fade out
When "0" is written: Normal display
Reading: Valid
By writing "1" to the ALOFF register, all the LCD segments go off, and when "0" is written, it returns to
normal display. This function outputs an off waveform to the SEG terminals, and does not affect the
content of the display memory.
ALON (FF61H•D1) has priority over ALOFF, so all the LCD segments go on when ALON and ALOFF are
set to "1" simultaneously.
At initial reset, this register is set to "1".
LC3–LC0: LCD contrast adjustment register (FF62H)
Adjusts the LCD contrast.
LC3–LC0 = 0000B light
::
LC3–LC0 = 1111B dark
When the LCD drive voltage is supplied from outside by mask option selection, this adjustment becomes
invalid. Furthermore, the contrast adjustment function cannot be used when "Internal power supply
(low-power mode)" is selected. Setting of this register is ignored.
At initial reset, LC0–LC3 is set to 0000B.
4.7.8 Programming note
Because at initial reset, the contents of display memory are undefined and LC3–LC0 (LCD contrast) is set
to 0000B, there is need to initialize by the software. Furthermore, take care of the registers LPWR and
ALOFF because these are set so that the display goes off.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Clock Timer)
4.8 Clock T imer
4.8.1 Configuration of clock timer
The S1C63656 has a built-in clock timer that uses OSC1 (crystal oscillator) as the source oscillator. The
clock timer is configured of an 8-bit binary counter that serves as the input clock, f
output from the prescaler. Timer data (128–16 Hz and 8–1 Hz) can be read out by the software.
Figure 4.8.1.1 is the block diagram for the clock timer.
Data bus
OSC1 divided clock
OSC1
oscillation circuit
(fOSC1)
Clock timer reset signal
Clock timer RUN/STOP signal
Ordinarily, this clock timer is used for all types of timing functions such as clocks.
Divider
Fig. 4.8.1.1 Block diagram for the clock timer
256 Hz
128 Hz–16 Hz
Clock timer
8 Hz–1 Hz
32 Hz, 16 Hz, 8 Hz, 2 Hz, 1 Hz
Interrupt
control
Interrupt
request
4.8.2 Data reading and hold function
The 8 bits timer data are allocated to the address FF75H and FF76H.
<FF75H> D0: TM0 = 128 Hz D1: TM1 = 64 Hz D2: TM2 = 32 Hz D3: TM3 = 16 Hz
<FF76H> D0: TM4 = 8 Hz D1: TM5 = 4 Hz D2: TM6 = 2 Hz D3: TM7 = 1 Hz
Since the clock timer data has been allocated to two addresses, a carry is generated from the low-order
data within the count (TM0–TM3: 128–16 Hz) to the high-order data (TM4–TM7: 8–1 Hz). When this carry
is generated between the reading of the low-order data and the high-order data, a content combining the
two does not become the correct value (the low-order data is read as FFH and the high-order data
becomes the value that is counted up 1 from that point).
The high-order data hold function in the S1C63656 is designed to operate to avoid this. This function
temporarily stops the counting up of the high-order data (by carry from the low-order data) at the point
where the low-order data has been read and consequently the time during which the high-order data is
held is the shorter of the two indicated here following.
1. Period until it reads the high-order data.
2. 0.48–1.5 msec (Varies due to the read timing.)
Note: Since the low-order data is not held when the high-order data has previously been read, the low-
order data should be read first.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Clock Timer)
4.8.3 Interrupt function
The clock timer can cause interrupts at the falling edge of 32 Hz, 8 Hz, 2 Hz, 1 Hz and 16 Hz signals.
Software can set whether to mask any of these frequencies.
Figure 4.8.3.1 is the timing chart of the clock timer.
Address
FF75H
FF76H
Bit
D0
D1
D2
D3
D0
D1
D2
D3
32 Hz interrupt request
16 Hz interrupt request
8 Hz interrupt request
2 Hz interrupt request
1 Hz interrupt request
Frequency Clock timer timing chart
128 Hz
64 Hz
32 Hz
16 Hz
8 Hz
4 Hz
2 Hz
1 Hz
Fig. 4.8.3.1 Timing chart of clock timer
As shown in Figure 4.8.3.1, interrupt is generated at the falling edge of the frequencies (32 Hz, 8 Hz, 2 Hz,
1 Hz, 16 Hz). At this time, the corresponding interrupt factor flag (IT0, IT1, IT2, IT3, IT4) is set to "1".
Selection of whether to mask the separate interrupts can be made with the interrupt mask registers (EIT0,
EIT1, EIT2, EIT3, EIT4). However, regardless of the interrupt mask register setting, the interrupt factor
flag is set to "1" at the falling edge of the corresponding signal.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Clock Timer)
4.8.4 I/O memory of clock timer
Table 4.8.4.1 shows the I/O addresses and the control bits for the clock timer.
Table 4.8.4.1 Control bits of clock timer
Address Comment
FF74H
TM3 TM2 TM1 TM0
FF75H
TM7 TM6 TM5 TM4
FF76H
EIT3 EIT2 EIT1 EIT0
FFE5H
FFE9H
FFF5H
FFF9H
*1 Initial value at initial reset
*2 Not set in the circuit
*3 Constantly "0" when being read
Register
D3 D2
00TMRST TMRUN
000EIT4
IT3 IT2 IT1 IT0
000IT4
D1 D0 Name Init
WR/WR
R
R
R/W
RR/W
R/W
RR/W
0
0
TMRST
TMRUN
0
0
0
0
0
0
∗
∗
TM3
TM2
TM1
TM0
TM7
TM6
TM5
TM4
EIT3
EIT2
EIT1
EIT0
∗
∗
∗
EIT4
IT3
IT2
IT1
IT0
∗
∗
∗
IT4
3
–
3
–
∗
3
Reset0Reset
3
–
3
–
3
–
3
–
3
–
3
–
∗1
10
∗
2
∗
2
Invalid
Run
Stop
0
0
0
0
0
0
0
0
0
Enable
Mask
0
Enable
Mask
0
Enable
Mask
0
Enable
(R)
Yes
(W)
Reset
(R)
Yes
(W)
Reset
Mask
(R)
No
(W)
Invalid
(R)
No
(W)
Invalid
∗
2
∗
2
∗
2
0 Enable Mask
0
0
0
0
∗
2
∗
2
∗
2
0
Unused
Unused
Clock timer reset (writing)
Clock timer Run/Stop
Clock timer data (16 Hz)
Clock timer data (32 Hz)
Clock timer data (64 Hz)
Clock timer data (128 Hz)
Clock timer data (1 Hz)
Clock timer data (2 Hz)
Clock timer data (4 Hz)
Clock timer data (8 Hz)
Interrupt mask register (Clock timer 1 Hz)
Interrupt mask register (Clock timer 2 Hz)
Interrupt mask register (Clock timer 8 Hz)
Interrupt mask register (Clock timer 32 Hz)
Unused
Unused
Unused
Interrupt mask register (Clock timer 16 Hz)
Interrupt factor flag (Clock timer 1 Hz)
Interrupt factor flag (Clock timer 2 Hz)
Interrupt factor flag (Clock timer 8 Hz)
Interrupt factor flag (Clock timer 32 Hz)
Unused
Unused
Unused
Interrupt factor flag (Clock timer 16 Hz)
TM0–TM7: Timer data (FF75H, FF76H)
The 128–1 Hz timer data of the clock timer can be read out with these registers. These eight bits are read
only, and writing operations are invalid.
By reading the low-order data (FF75H), the high-order data (FF76H) is held until reading or for 0.48–1.5
msec (one of shorter of them).
At initial reset, the timer data is initialized to "00H".
TMRST: Clock timer reset (FF74H•D1)
This bit resets the clock timer.
When "1" is written: Clock timer reset
When "0" is written: No operation
Reading: Always "0"
The clock timer is reset by writing "1" to TMRST. When the clock timer is reset in the RUN status, operation restarts immediately. Also, in the STOP status the reset data is maintained. No operation results
when "0" is written to TMRST.
This bit is write-only, and so is always "0" at reading.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Clock Timer)
TMRUN: Clock timer RUN/STOP control register (FF74H•D0)
Controls RUN/STOP of the clock timer.
When "1" is written: RUN
When "0" is written: STOP
Reading: Valid
The clock timer enters the RUN status when "1" is written to the TMRUN register, and the STOP status
when "0" is written. In the STOP status, the timer data is maintained until the next RUN status or the
timer is reset. Also, when the STOP status changes to the RUN status, the data that is maintained can be
used for resuming the count.
At initial reset, this register is set to "0".
EIT0: 32 Hz interrupt mask register (FFE5H•D0)
EIT1: 8 Hz interrupt mask register (FFE5H•D1)
EIT2: 2 Hz interrupt mask register (FFE5H•D2)
EIT3: 1 Hz interrupt mask register (FFE5H•D3)
EIT4: 16 Hz interrupt mask register (FFE9H•D0)
These registers are used to select whether to mask the clock timer interrupt.
When "1" is written: Enabled
When "0" is written: Masked
Reading: Valid
The interrupt mask registers (EIT0, EIT1, EIT2, EIT3, EIT4) are used to select whether to mask the interrupt to the separate frequencies (32 Hz, 8 Hz, 2 Hz, 1 Hz, 16 Hz).
At initial reset, these registers are set to "0".
IT0: 32 Hz interrupt factor flag (FFF5H•D0)
IT1: 8 Hz interrupt factor flag (FFF5H•D1)
IT2: 2 Hz interrupt factor flag (FFF5H•D2)
IT3: 1 Hz interrupt factor flag (FFF5H•D3)
IT4: 16 Hz interrupt factor flag (FFF9H•D0)
These flags indicate the status of the clock timer interrupt.
When "1" is read: Interrupt has occurred
When "0" is read: Interrupt has not occurred
When "1" is written: Flag is reset
When "0" is written: Invalid
The interrupt factor flags (IT0, IT1, IT2, IT3, IT4) correspond to the clock timer interrupts of the respective
frequencies (32 Hz, 8 Hz, 2 Hz, 1 Hz, 16 Hz). The software can judge from these flags whether there is a
clock timer interrupt. However, even if the interrupt is masked, the flags are set to "1" at the falling edge
of the signal.
These flags are reset to "0" by writing "1" to them.
After an interrupt occurs, the same interrupt will occur again if the interrupt enabled state (I flag = "1") is
set or the RETI instruction is executed unless the interrupt factor flag is reset. Therefore, be sure to reset
(write "1" to) the interrupt factor flag in the interrupt service routine before shifting to the interrupt
enabled state.
At initial reset, these flags are set to "0".
4.8.5 Programming notes
(1) Be sure to read timer data in the order of low-order data (TM0–TM3) then high-order data (TM4–
TM7).
(2) After an interrupt occurs, the same interrupt will occur again if the interrupt enabled state (I flag =
"1") is set or the RETI instruction is executed unless the interrupt factor flag is reset. Therefore, be sure
to reset (write "1" to) the interrupt factor flag in the interrupt service routine before shifting to the
interrupt enabled state.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Stopwatch Timer)
4.9 Stopwatch Timer
4.9.1 Configuration of stopwatch timer
The S1C63656 has a 1/1,000 sec stopwatch timer. The stopwatch timer is configured of a 3-stage, 4-bit
BCD counter serving as the input clock of a 1,000 Hz signal output from the prescaler. Data can be read
out four bits (1/1,000 sec, 1/100 sec and 1/10 sec) at a time by the software.
In addition it has a direct input function that controls the stopwatch timer RUN/STOP and LAP using the
input ports K00 and K01.
Figure 4.9.1.1 is the block diagram of the stopwatch timer.
[SWRST]
(1,000 Hz)
1/1,000 sec
counter
1/100 sec
Capture buffer
SWD0–3
reading
Data bus
counter
SWD4–7
reading
1/10 sec
counter
1 Hz interrupt request
10 Hz interrupt request
SWD8–11
reading
Direct RUN interrupt request
Direct LAP interrupt request
K01
K00
K02–K13
f
OSC1
/32
(1,024 Hz)
[SWDIR]
Direct
input
control
[DKM2–0]
[LCURF]
1,000 / 1,024
prescaler
Capture
control
circuit
[SWRUN]
[EDIR]
[CRNWF]
Fig. 4.9.1.1 Block diagram of stopwatch timer
The stopwatch timer can be used as a separate timer from the clock timer. In particular, digital watch
stopwatch functions can be realized easily with software.
4.9.2 Counter and prescaler
The stopwatch timer is configured of four-bit BCD counters SWD0–3, SWD4–7 and SWD8–11.
The counter SWD0–3, at the stage preceding the stopwatch timer, has a 1,000 Hz signal generated by the
prescaler for the input clock. It counts up every 1/1,000 sec, and generates 100 Hz signal. The counter
SWD4–7 has a 100 Hz signal generated by the counter SWD0–3 for the input clock. It count-up every
1/100 sec, and generated 10 Hz signal. The counter SWD8–11 has an approximated 10 Hz signal generated by the counter SWD4–7 for the input clock. It count-up every 1/10 sec, and generated 1 Hz signal.
The prescaler inputs a 1,024 Hz clock dividing f
outputs 1,000 Hz counting clock for SWD0–3. To generate a 1,000 Hz clock from 1,024 Hz, 24 pulses from
1,024 pulses that are input to the prescaler every second are taken out.
When the counter becomes the value indicated below, one pulse (1,024 Hz) that is input immediately
after to the prescaler will be pulled out.
OSC1 (output from the OSC1 oscillation circuit), and
<Counter value (msec) in which the pulse correction is performed>
39, 79, 139, 179, 219, 259, 299, 319, 359, 399, 439, 479, 539, 579, 619, 659, 699, 719, 759, 799, 839, 879, 939, 979
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Stopwatch Timer)
Figure 4.9.2.1 shows the operation of the prescaler.
START
Prescaler input clock (1,024 Hz)
Prescaler output clock
Counter data
000 001 002 037 038 039 040 041
Fig. 4.9.2.1 Timing of the prescaler operation
For the above reason, the counting clock is 1,024 Hz (0.9765625 msec) except during pulse correction.
Consequently, frequency of the prescaler output clock (1,000 Hz), 100 Hz generated by SWD0–3 and 10
Hz generated by SWD4–7 are approximate values.
4.9.3 Capture buffer and hold function
The stopwatch data, 1/1,000 sec, 1/100 sec and 1/10 sec, can be read from SWD0–3 (FF7AH), SWD4–7
(FF7BH) and SWD8–11 (FF7CH), respectively. The counter data are latched in the capture buffer when
reading, and are held until reading of three words is completed. For this reason, correct data can be read
even when a carry from lower digits occurs during reading the three words. Further, three counter data
are latched in the capture buffer at the same time when SWD0–3 (1/1,000 sec) is read. The data hold is
released when SWD8–11 (1/10 sec) reading is completed. Therefore, data should be read in order of
SWD0–3 → SWD4–7 → SWD8–11. If SWD4–7 or SWD8–11 is first read when data have not been held, the
hold function does not work and data in the counter is directly read out. When data that has not been
held is read in the stopwatch timer RUN status, you cannot judge whether it is correct or not.
The stopwatch timer has a LAP function using an external key input (explained later). The capture buffer
is also used to hold LAP data. In this case, data is held until SWD8–11 is read. However, when a LAP
input is performed before completing the reading, the content of the capture buffer is renewed at that
point. Remaining data that have not been read become invalid by the renewal, and the hold status is not
released if SWD8–11 is read. When SWD8–11 is read after the capture buffer is updated, the capture
renewal flag is set to "1" at that point. In this case, it is necessary to read from SWD0–3 again. The capture
renewal flag is renewed by reading SWD8–11.
Figure 4.9.3.1 shows the timing for data holding and reading.
Direct LAP input (K01/K00)
Direct LAP internal signal
Capture renewal flag CRNWF
SWD0–3 reading
SWD4–7 reading
SWD8–11 reading
Data holding
Fig. 4.9.3.1 Timing for data holding and reading
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Stopwatch Timer)
4.9.4 Stopwatch timer RUN/STOP and reset
RUN/STOP control and reset of the stopwatch timer can be done by the software.
Stopwatch timer RUN/STOP
The stopwatch timer enters the RUN status when "1" is written to SWRUN, and the STOP status when
"0" is written. In the STOP status, the timer data is maintained until the next RUN status or resets
timer. Also, when the STOP status changes to the RUN status, the data that was maintained can be
used for resuming the count. The RUN/STOP operation of the stopwatch timer by writing to the
SWRUN register is performed in synchronization with the falling edge of the 1,024 Hz same as the
prescaler input clock. The SWRUN register can be read, and in this case it indicates the operating
status of the stopwatch timer.
Figure 4.9.4.1 shows the operating timing when controlling the SWRUN register.
fOSC1/32 (1,024 Hz)
SWRUN writing
SWRUN register
Count clock
Fig. 4.9.4.1 Operating timing when controlling SWRUN
When the direct input function (explained in next section) is set, RUN/STOP control is done by an
external key input. In this case, SWRUN becomes read only register that indicates the operating status
of the stopwatch timer.
Stopwatch timer reset
The stopwatch timer is reset when "1" is written to SWRST. With this, the counter value is cleared to
"000". Since this resetting does not affect the capture buffer, data that has been held in the capture
buffer is not cleared and is maintained as is. When the stopwatch timer is reset in the RUN status,
counting restarts from count "000". Also, in the STOP status the reset data "000" is maintained until the
next RUN.
4.9.5 Direct input function and key mask
The stopwatch timer has a direct input function that can control the RUN/STOP and LAP operation of
the stopwatch timer by external key input. This function is set by writing "1" to the EDIR register. When
EDIR is set to "0", only the software control is possible as explained in the previous section.
Input port configuration
In the direct input function, the input ports K00 and K01 are used as the RUN/STOP and LAP input
ports. The key assignment can be selected using the SWDIR register.
Table 4.9.5.1 RUN/STOP and LAP input ports
SWDIR
0
1
Direct RUN
When the direct input function is selected, RUN/STOP operation of the stopwatch timer can be
controlled by using the key connected to the input port K00/K01 (selected by SWDIR). K00/K01
works as a normal input port, but the input signal is sent to the stopwatch control circuit. The key
input signal from the K00/K01 port works as a toggle switch. When it is input in STOP status, the
stopwatch timer runs, and in RUN status, the stopwatch timer stops. RUN/STOP status of the
stopwatch timer can be checked by reading the SWRUN register. An interrupt is generated by direct
RUN input.
The sampling for key input signal is performed at the falling edge of 1,024 Hz signal same as the
SWRUN control. The chattering judgment is performed at the point where the key turns off, and a
chattering less than 46.8–62.5 msec is removed. Therefore, more time is needed for an interval between RUN and STOP key inputs.
K00
RUN/STOP
LAP
K01
LAP
RUN/STOP
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Stopwatch Timer)
Figure 4.9.5.1 shows the operating timing for the direct RUN input.
fOSC1/32 (1,024 Hz)
Direct RUN input (K00/K01)
Direct RUN internal signal
SWRUN register
Count clock
Direct RUN interrupt
Fig. 4.9.5.1 Operating timing for direct RUN input
Direct LAP
Control for the LAP can also be done by key input same as the direct RUN. When the direct input
function is selected, the input port K01/K00 (selected by SWDIR) becomes the LAP key input port.
Sampling for the input signal and the chattering judgment are the same as a direct RUN.
By entering the LAP key, the counter data at that point is latched into the capture buffer and is held.
The counter continues counting operation. Furthermore, an interrupt occurs by direct LAP input.
As stated above, the capture buffer data is held until SWD8–11 is read. If the LAP key is input when
data has been already held, it renews the content of the capture buffer. When SWD8–11 is read after
renewing, the capture renewal flag is set to "1". In this case, the hold status is not released by reading
SWD8–11, and it continues. Normally the LAP data should be read after the interrupt is generated.
After that, be sure to check the capture renewal flag. When the capture renewal flag is set, renewed
data is held in the capture buffer. So it is necessary to read from SWD0–3 again.
The stopwatch timer sets the 1 Hz interrupt factor flag ISW1 to "1" when requiring a carry-up to 1-sec
digit by an SWD8–11 overflow. If the capture buffer shifts into hold status (when SWD0–3 is read or
when LAP is input) while the 1 Hz interrupt factor flag ISW1 is set to "1", the lap data carry-up
request flag LCURF is set to "1" to indicate that a carry-up to 1-sec digit is required for the processing
of LAP input. In normal software processing, LAP processing may take precedence over 1-sec or
higher digits processing by a 1 Hz interrupt, therefore carry-up processing using this flag should be
used for time display in the LAP processing to prevent the 1-sec digit data decreasing by 1 second.
This flag is renewed when the capture buffer shifts into hold status.
Figure 4.9.5.2 shows the operating timing for the direct LAP input, and Figure 4.9.5.3 shows the
timings for data holding and reading during a direct LAP input and reading.
f
OSC1
/32 (1,024 Hz)
Direct LAP input (K01/K00)
Direct LAP internal signal
Data holding
SWD8–11 reading
Direct LAP interrupt
Fig. 4.9.5.2 Operating timing for direct LAP input
Direct LAP input (K01/K00)
Capture renewal flag CRNWF
SWD0–3 reading
SWD4–7 reading
SWD8–11 reading
Data holding
1 Hz interrupt factor flag ISW1
Lap data carry-up request flag LCURF
Counter data
999 000
Fig. 4.9.5.3 Timing for data holding and reading during direct LAP input
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Stopwatch Timer)
Key mask
In stopwatch applications, some functions may be controlled by a combination of keys including
direct RUN or direct LAP. For instance, the RUN key can be used for other functions, such as reset and
setting a watch, by pressing the RUN key with another key. In this case, the direct RUN function or
direct LAP function must be invalid so that it does not function. For this purpose, the key mask
function is set so that it judges concurrence of input keys and invalidates RUN and LAP functions. A
combination of the key inputs for this judgment can be selected using the DKM0–DKM2 registers.
Table 4.9.5.2 Key mask selection
DKM2
0
0
0
0
1
1
1
1
RUN or LAP inputs become invalid in the following status.
1. The RUN or LAP key is pressed when one or more keys that are included in the selected combination (here in after referred to as mask) are held down.
2. The RUN or LAP key has been pressed when the mask is released.
DKM1
0
0
1
1
0
0
1
1
DKM0
0
1
0
1
0
1
0
1
Mask key combination
None (at initial reset)
K02
K02, K03
K02, K03, K10
K10
K10, K11
K10, K11, K12
K10, K11, K12, K13
fOSC1/32 (1,024 Hz)
Direct RUN/LAP input
Key mask
valid
invalid
invalid
invalid
Fig. 4.9.5.4 Operation of key mask
RUN or LAP inputs become valid in the following status.
1. Either the RUN or LAP key is pressed independently if no other key is been held down.
2. Both the RUN and LAP keys are pressed at the same time if no other key is held down. (RUN and
LAP functions are effective.)
3. The RUN or LAP key is pressed if either is held down. (RUN and LAP functions are effective.)
4. Either the RUN or LAP key and the mask key are pressed at the same time if no other key is held
down.
5. Both the RUN and LAP keys and the mask key are pressed at the same time if no other key is held
down. (RUN and LAP functions are effective.)
* Simultaneous key input is referred to as two or more key inputs are sampled at the same falling
edge of 1,024 Hz clock.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Stopwatch Timer)
4.9.6 Interrupt function
10 Hz and 1 Hz interrupts
The 10 Hz and 1 Hz interrupts can be generated through the overflow of stopwatch timers SWD4–7
and SWD8–11 respectively. Also, software can set whether to separately mask the frequencies described earlier.
Figure 4.9.6.1 is the timing chart for the counters.
Address Register Stopwatch timer (SWD0–3) timing chart
D0
FF7AH
(1/1,000 sec BCD)
D1
D2
D3
Address Register Stopwatch timer (SWD4–7) timing chart
D0
FF7BH
(1/100 sec BCD)
D1
D2
D3
10 Hz interrupt request
Address Register Stopwatch timer (SWD8–11) timing chart
D0
FF7CH
(1/10 sec BCD)
D1
D2
D3
1 Hz interrupt request
Fig. 4.9.6.1 Timing chart for counters
As shown in Figure 4.9.6.1, the interrupts are generated by the overflow of their respective counters ("9"
changing to "0"). Also, at this time the corresponding interrupt factor flag (ISW10, ISW1) is set to "1".
The respective interrupts can be masked separately through the interrupt mask registers (EISW10,
EISW1). However, regardless of the setting of the interrupt mask registers, the interrupt factor flags
are set to "1" by the overflow of their corresponding counters.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Stopwatch Timer)
Direct RUN and direct LAP interrupts
When the direct input function is selected, the direct RUN and direct LAP interrupts can be generated.
The respective interrupts occur at the rising edge of the internal signal for direct RUN and direct LAP
after sampling the direct input signal in the falling edge of 1,024 Hz signal. Also, at this time the
corresponding interrupt factor flag (IRUN, ILAP) is set to "1".
The respective interrupts can be masked separately through the interrupt mask registers (EIRUN,
EILAP). However, regardless of the setting of the interrupt mask registers, the interrupt factor flags
are set to "1" by the inputs of the RUN and LAP.
The direct RUN and LAP functions use the K00 and K01 ports. Therefore, the direct input interrupt
and the K00–K03 inputs interrupt may generate at the same time depending on the interrupt condition setting for the input port K00–K03. Consequently, when using the direct input interrupt, set the
interrupt selection registers SIK00 and SIK01 to "0" so that the input interrupt does not generate by
K00 and K01 inputs.
f
OSC1
/32 (1,024 Hz)
SWRST writing
EDIR writing
EDIR register
Direct RUN input
SWRUN writing
SWRUN register
Direct LAP input
Counter data
Capture buffer
SWD0–3 reading
SWD4–7 reading
SWD8–11 reading
CRNWF
1 Hz interrupt factor flag ISW1
LCURF
Direct RUN interrupt
Direct LAP interrupt
10 Hz interrupt
1 Hz interrupt
001 002 003 004 005 006 098 099 100 101 102 000 001 002 003 004 005 006 007 993 994000 995 996 997 998 999 000 001 002 003 004 005 006 007
003 005 995 001 006
Fig. 4.9.6.2 Timing chart for stopwatch timer
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Stopwatch Timer)
4.9.7 I/O memory of stopwatch timer
Table 4.9.7.1 shows the I/O addresses and the control bits for the stopwatch timer.
Table 4.9.7.1 Control bits of stopwatch timer
Address Comment
FOUTE SWDIR FOFQ1 FOFQ0
FF06H
EDIR DKM2 DKM1 DKM0
FF78H
LCURF CRNWF SWRUN SWRST
FF79H
SWD3 SWD2 SWD1 SWD0
FF7AH
SWD7 SWD6 SWD5 SWD4
FF7BH
SWD11 SWD10 SWD9 SWD8
FF7CH
EIRUN EILAP EISW1 EISW10
FFE6H
IRUN ILAP ISW1 ISW10
FFF6H
*1 Initial value at initial reset
*2 Not set in the circuit
*3 Constantly "0" when being read
D3 D2
Register
D1 D0 Name Init
R/W
R/W
R/W WR
R
R
R
R/W
R/W
FOUTE
SWDIR
FOFQ1
FOFQ0
EDIR
DKM2
DKM1
DKM0
LCURF
CRNWF
SWRUN
SWRST
SWD3
SWD2
SWD1
SWD0
SWD7
SWD6
SWD5
SWD4
SWD11
SWD10
SWD9
SWD8
EIRUN
EILAP
EISW1
EISW10
IRUN
ILAP
ISW1
ISW10
∗1
10
0
Enable Disable
0
0
0
0
Enable Disable
0
0
0
0
Request
0
Renewal
0
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Run
Reset
Enable
Enable
Enable
Enable
(R)
Yes
(W)
Reset
∗
3
FOUT output enable
Stopwatch direct input switch
0: K00=Run/Stop, K01=Lap 1: K00=Lap, K01=Run/Stop
FOUT
frequency
selection
Direct input enable
Key mask
selection
Lap data carry-up request flag
No
Capture renewal flag
No
Stopwatch timer Run/Stop
Stop
Stopwatch timer reset (writing)
Invalid
Stopwatch timer data
BCD (1/1000 sec)
Stopwatch timer data
BCD (1/100 sec)
Stopwatch timer data
BCD (1/10 sec)
Interrupt mask register (Stopwatch direct RUN)
Mask
Interrupt mask register (Stopwatch direct LAP)
Mask
Interrupt mask register (Stopwatch timer 1 Hz)
Mask
Interrupt mask register (Stopwatch timer 10 Hz)
Mask
Interrupt factor flag (Stopwatch direct RUN)
(R)
Interrupt factor flag (Stopwatch direct LAP)
No
Interrupt factor flag (Stopwatch timer 1 Hz)
(W)
Interrupt factor flag (Stopwatch timer 10 Hz)
Invalid
[FOFQ1, 0]
Frequency
[DKM2, 1, 0]
Key mask
[DKM2, 1, 0]
Key mask
0
OSC1
/641f
OSC1
f
0
None1K022K02–033K02–03,10
4
K105K10–116K10–127K10–13
/82f
OSC1
f
3
OSC3
SWD0–SWD3: Stopwatch timer data 1/1,000 sec (FF7AH)
Data (BCD) of the 1/1,000 sec column of the capture buffer can be read out.
The hold function of the capture buffer works by reading this data.
These 4 bits are read-only, and cannot be used for writing operations.
At initial reset, the timer data is set to "0".
SWD4–SWD7: Stopwatch timer data 1/100 sec (FF7BH)
Data (BCD) of the 1/100 sec column of the capture buffer can be read out. These 4 bits are read-only, and
cannot be used for writing operations.
At initial reset, the timer data is set to "0".
SWD8–SWD11: Stopwatch timer data 1/10 sec (FF7CH)
Data (BCD) of the 1/10 sec column of the capture buffer can be read out. These 4 bits are read-only, and
cannot be used for writing operations.
At initial reset, the timer data is set to "0".
Note: Be sure to data reading in the order of SWD0–3 → SWD4–7 → SWD8–11.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Stopwatch Timer)
EDIR: Direct input function enable register (FF78H•D3)
Enables the direct input (RUN/LAP) function.
When "1" is written: Enabled
When "0" is written: Disabled
Reading: Valid
The direct input function is enabled by writing "1" to EDIR, and then RUN/STOP and LAP control can be
done by external key input. When "0" is written, the direct input function is disabled, and the stopwatch
timer is controlled by the software only.
Further the function switching is actually done by synchronizing with the falling edge of f
OSC1/32 (1,024
Hz) after the data is written to this register (after 977 µsec maximum).
At initial reset, this register is set to "0".
SWDIR: Direct input switch register (FF06H•D2)
Switches the direct-input key assignment for the K00 and K01 ports.
When "1" is written: K00 = LAP, K01 = RUN/STOP
When "0" is written: K00 = RUN/STOP, K01 = LAP
Reading: Valid
The direct-input key assignment is selected using this register. The K00 and K01 port statuses are input to
the stopwatch timer as the RUN/STOP and LAP inputs according to this selection.
At initial reset, this register is set to "0".
DKM0–DKM2: Direct key mask selection register (FF78H•D0–D2)
Selects a combination of the key inputs for concurrence judgment with RUN and LAP inputs when the
direct input function is set.
Table 4.9.7.2 Key mask selection
DKM2
0
0
0
0
1
1
1
1
DKM1
0
0
1
1
0
0
1
1
DKM0
0
1
0
1
0
1
0
1
Mask key combination
None (at initial reset)
K02
K02, K03
K02, K03, K10
K10
K10, K11
K10, K11, K12
K10, K11, K12, K13
When the concurrence is detected, RUN and LAP inputs cannot be accepted until the concurrence is
released.
At initial reset, this register is set to "0".
SWRST: Stopwatch timer reset (FF79H•D0)
This bit resets the stopwatch timer.
When "1" is written: Stopwatch timer reset
When "0" is written: No operation
Reading: Always "0"
The stopwatch timer is reset when "1" is written to SWRST. When the stopwatch timer is reset in the RUN
status, operation restarts immediately. Also, in the STOP status the reset data is maintained.
Since this reset does not affect the capture buffer, the capture buffer data in hold status is not cleared and
is maintained.
This bit is write-only, and is always "0" at reading.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Stopwatch Timer)
SWRUN: Stopwatch timer RUN/STOP (FF79H•D1)
This register controls the RUN/STOP of the stopwatch timer, and the operating status can be monitored
by reading this register.
• When writing data
When "1" is written: RUN
When "0" is written: STOP
The stopwatch timer enters the RUN status when "1" is written to SWRUN, and the STOP status when "0"
is written. In the STOP status, the timer data is maintained until the next RUN status or resets timer. Also,
when the STOP status changes to the RUN status, the data that was maintained can be used for resuming
the count. RUN/STOP control with this register is valid only when the direct input function is set to
disable. When the direct input function is set, it becomes invalid.
• When reading data
When "1" is read: RUN
When "0" is read: STOP
Reading is always valid regardless of the direct input function setting. "1" is read when the stopwatch
timer is in the RUN status, and "0" is read in the STOP status.
At initial reset, this register is set to "0".
LCURF: Lap data carry-up request flag (FF79H•D3)
This flag indicates a carry that has been generated to 1 sec-digit when the data is held. Note that this flag
is invalid when the direct input function is disabled.
When "1" is read: Carry is required
When "0" is read: Carry is not required
Writing: Invalid
If the capture buffer shifts into hold status while the 1 Hz interrupt factor flag ISW1 is set to "1", LCURF is
set to "1" to indicate that a carry-up to 1-sec digit is required. When performing a processing such as a
LAP input preceding with 1 Hz interrupt processing, read this flag before processing and check whether
carry-up is needed or not.
This flag is renewed (set/reset) every time the capture buffer shifts into hold status.
At initial reset, this flag is set to "0".
CRNWF: Capture renewal flag (FF79H•D2)
This flag indicates that the content of the capture buffer has been renewed.
When "1" is read: Renewed
When "0" is read: Not renewed
Writing: Invalid
The content of the capture buffer is renewed if the LAP key is input when the data held into the capture
buffer has not yet been read. Reading SWD8–11 in that status sets this flag to "1", and the hold status is
maintained. Consequently, when data that is held by a LAP input is read, read this flag after reading the
SWD8–11 and check whether the data has been renewed or not.
This flag is renewed when SWD8–11 is read.
At initial reset, this flag is set to "0".
EIRUN, EILAP, EISW1, EISW10: Interrupt mask registers (FFE6H)
These registers are used to select whether to mask the stopwatch timer interrupt.
When "1" is written: Enabled
When "0" is written: Masked
Reading: Valid
The interrupt mask registers EIRUN, EILAP, EISW1 and EISW10 are used to separately select whether to
mask the direct RUN, direct LAP, 1 Hz and 10 Hz interrupts.
At initial reset, these registers are set to "0".
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Stopwatch Timer)
IRUN, ILAP, ISW1, ISW10: Interrupt factor flags (FFF6H)
These flags indicate the status of the stopwatch timer interrupt.
When "1" is read: Interrupt has occurred
When "0" is read: Interrupt has not occurred
When "1" is written: Flag is reset
When "0" is written: Invalid
The interrupt factor flags IRUN, ILAP, ISW1 and ISW10 correspond to the direct RUN, direct LAP, 1 Hz
and 10 Hz interrupts respectively. The software can judge from these flags whether there is a stopwatch
timer interrupt. However, even if the interrupt is masked, the flags are set to "1" when the timing condition is established.
These flags are reset to "0" by writing "1" to them.
After an interrupt occurs, the same interrupt will occur again if the interrupt enabled state (I flag = "1") is
set or the RETI instruction is executed unless the interrupt factor flag is reset. Therefore, be sure to reset
(write "1" to) the interrupt factor flag in the interrupt service routine before shifting to the interrupt
enabled state.
At initial reset, these flags are set to "0".
4.9.8 Programming notes
(1) The interrupt factor flag should be reset after resetting the stopwatch timer.
(2) Be sure to data reading in the order of SWD0–3 → SWD4–7 → SWD8–11.
(3) When data that is held by a LAP input is read, read the capture buffer renewal flag CRNWF after
reading the SWD8–11 and check whether the data has been renewed or not.
(4) When performing a processing such as a LAP input preceding with 1 Hz interrupt processing, read
the LAP data carry-up request flag LCURF before processing and check whether carry-up is needed or
not.
(5) After an interrupt occurs, the same interrupt will occur again if the interrupt enabled state (I flag =
"1") is set or the RETI instruction is executed unless the interrupt factor flag is reset. Therefore, be sure
to reset (write "1" to) the interrupt factor flag in the interrupt service routine before shifting to the
interrupt enabled state.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Programmable Timer)
4.10 Programmable Timer
4.10.1 Configuration of programmable timer
The S1C63656 has two 8-bit programmable timer systems (timer 0 and timer 1) built-in.
The timers are composed of 8-bit presettable down counters and they can be used as 8 bits × 2 channels or
16 bits × 1 channel of programmable timers. Timer 0 also has an event counter function using the K13
input port terminal.
Figure 4.10.1.1 shows the configuration of the programmable timer.
Each timer has an 8-bit down counter and an 8-bit reload data register. The down counter counts the
input clock. When the down counter underflows, the timer outputs the underflow and interrupt signals
and resets the counter to its initial value. The reload data register is used to store that initial value. The
underflow signal of timer 1 is used as the source clock of the serial interface, this makes it possible to
program a flexible transfer rate.
Each timer has an 8-bit compare data register in addition to the above registers. This register is used to
store data to be compared with the contents of the down counter. When the timer is set in the PWM
mode, the timer outputs the compare match signal if the contents between the down counter and the
compare data register are matched, and an interrupt occurs at the same time. Also the compare match
signal is used with the underflow signal to generate a PWM waveform.
The signal generated by the programmable timer can be output from the R02 output port terminal.
OSC1
oscillation
circuit
OSC3
oscillation
circuit
Interrupt
request
TOUT
(R02)
Serial
interface
f
OSC3
Timer 0 Run/Stop
f
OSC1
Timer 1 Run/Stop
Interrupt
control
circuit
Output port
R02
PTRUN0
Selector
CKSEL0
PTRUN1
Selector
CKSEL1
K13
PTOUT
Selector
CHSEL0
Divider
Input port
K13
2,048 Hz
Timer 0
Prescaler
Prescaler
setting
PTPS00
PTPS01
Timer function setting
FCSEL
PLPOL
Pulse polarity setting
PTRST0
Timer 0 reset
Clock
control
circuit
PWM waveform
generator
Timer 1
PTRST1
Timer 1 reset
Clock
Prescaler Selector
Prescaler
setting
PTPS10
PTPS11
1/2
1/2
control
circuit
PWM waveform
generator
Fig. 4.10.1.1 Configuration of programmable timer
Compare
match
signal
EVCNT
Event counter
mode setting
MOD16
Compare
match
signal
Reload data register
RLD00–RLD07
Comparator
Compare data register
PWM output selection
16-bit mode selection
Reload data register
RLD10–RLD17
Comparator
Compare data register
PWM output selection
8-bit
down counter
PTD00–PTD07
CD00–CD07
PTSEL0
8-bit
down counter
PTD10–PTD17
CD10–CD17
PTSEL1
Data buffer
Data buffer
Underflow
signal
Underflow
signal
Data bus
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Programmable Timer)
4.10.2 Basic count operation
This section explains the basic count operation when each timer is used as an individual 8-bit timer.
Each timer has an 8-bit down counter and an 8-bit reload data register.
The reload data register RLDx0–RLDx7 (x = timer number) is used to set the initial value to the down
counter.
By writing "1" to the timer reset bit PTRSTx, the down counter loads the initial value set in the reload
register. Therefore, down-counting is executed from the stored initial value by the input clock.
The PTRUNx register is provided to control the RUN/STOP for each timer. By writing "1" to this register
after presetting the reload data to the down counter, the down counter starts counting down. Writing "0"
stops the input count clock and the down counter stops counting. This control (RUN/STOP) does not
affect the counter data. The counter maintains its data while stopped, and can restart counting continuing
from that data.
The counter data can be read via the data buffer PTDx0–PTDx7 in optional timing. However, the counter
has the data hold function the same as the clock timer, that holds the high-order data (PTDx4–PTDx7)
when the low-order data (PTDx0–PTDx3) is read in order to prevent the borrowing operation between
low- and high-order reading, therefore be sure to read the low-order data first.
The counter reloads the initial value set in the reload data register when an underflow occurs through the
count down. It continues counting down from the initial value after reloading.
In addition to reloading the counter, this underflow signal controls the interrupt generation, pulse (TOUT
signal) output and clock supplying to the serial interface.
PTRUNx
PTRSTx
RLDx0–x7
Input clock
PTDx7
PTDx6
PTDx5
PTDx4
PTDx3
PTDx2
PTDx1
PTDx0
A6H F3H
Preset Reload &
underflow interrupt
Fig. 4.10.2.1 Basic operation timing of down counter
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Programmable Timer)
4.10.3 Setting the input clock
A prescaler is provided for each timer. The prescaler generates the input clock for the timer by dividing
the source clock supplied from the OSC1 or OSC3 oscillation circuit. The source clock (OSC1 or OSC3)
and the division ratio of the prescaler can be selected with software for each timer individually.
The input clock is set in the following sequence.
Selection of source clock
Select the source clock input to each prescaler from either OSC1 or OSC3. This selection is done using
the source clock selection register CKSELx; when "0" is written to the register, OSC1 is selected and
when "1" is written, OSC3 is selected.
When the OSC3 oscillation clock is selected for the clock source, it is necessary to turn the OSC3
oscillation on, prior to using the programmable timer. However the OSC3 oscillation circuit requires a
time at least 5 msec from turning the circuit on until the oscillation stabilizes. Therefore, allow an
adequate interval from turning the OSC3 oscillation circuit on to starting the programmable timer.
Refer to Section 4.3, "Oscillation Circuit", for the control and notes of the OSC3 oscillation circuit.
At initial reset, the OSC3 oscillation circuit is set in off state.
Note: When the mask option to disable the OSC3 oscillation circuit is selected, no source clock can be
selected (fixed at OSC1). Do not set the CKSELx register to "1".
Selection of prescaler division ratio
Select the division ratio for each prescaler from among 4 types. This selection is done using the
prescaler division ratio selection register PTPSx0/PTPSx1. Table 4.10.3.1 shows the correspondence
between the setting value and the division ratio.
Table 4.10.3.1 Selection of prescaler division ratio
PTPSx1
PTPSx0
1
1
0
0
Prescaler division ratio
1
0
1
0
Source clock / 256
Source clock / 32
Source clock / 4
Source clock / 1
By writing "1" to the PTRUNx register, the prescaler inputs the source clock and outputs the clock
divided by the selected division ratio. The counter starts counting down by inputting the clock.
4.10.4 Event counter mode (timer 0)
Timer 0 has an event counter function that counts an external clock input to the input port K13. This
function is selected by writing "1" to timer 0 counter mode selection register EVCNT. At initial reset,
EVCNT is set to "0" and timer 0 is configured as a normal timer that counts the internal clock.
In the event counter mode, the clock is supplied to timer 0 from outside the IC, therefore, the settings of
the timer 0 prescaler division ratio selection register PTPS00–PTPS01 and the settings of the timer 0
source clock selection register CKSEL0 become invalid.
Count down timing can be selected from either the falling or rising edge of the input clock using the
timer 0 pulse polarity selection register PLPOL. When "0" is written to the PLPOL register, the falling
edge is selected, and when "1" is written, the rising edge is selected. The count down timing is shown in
Figure 4.10.4.1.
EVCNT
PTRUN0
1
PLPOL
K13 input
Count data
01
n n-1 n-2 n-3 n-4 n-5 n-6
Fig. 4.10.4.1 Timing chart in event counter mode
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Programmable Timer)
The event counter mode also allows use of a noise reject function to eliminate noise such as chattering on
the external clock (K13 input signal). This function is selected by writing "1" to the timer 0 function
selection register FCSEL.
When "with noise rejector" is selected, an input pulse width for both low and high levels must be 0.98
msec∗ or more to count reliably. The noise rejector allows the counter to input the clock at the second
falling edge of the internal 2,048 Hz∗ signal after changing the input level of the K13 input port terminal.
Consequently, the pulse width of noise that can reliably be rejected is 0.48 msec∗ or less.
(∗: f
OSC1 = 32.768 kHz)
Figure 4.10.4.2 shows the count down timing with noise rejector.
2,048 Hz
EVIN input (K13)
Counter
input clock
Counter data n n-1 n-2 n-3
∗1
∗2
∗1 When f
∗2 When PLPOL register is set to "0"
OSC1
is 32.768 kHz
Fig. 4.10.4.2 Count down timing with noise rejector
The operation of the event counter mode is the same as the normal timer except it uses the K13 input as
the clock. Refer to Section 4.10.2, "Basic count operation" for basic operation and control.
4.10.5 PWM mode (timer 0, timer 1)
Timer 0 and timer 1 can generate a PWM waveform. When using this function, write "1" to the PTSEL0
register (for timer 0) or PTSEL1 register (for timer 1) to set the timer in the PWM mode.
The compare data register CDx0–CDx7 (x represents a timer number) is provided for timers 0 and 1 to
control the PWM waveform. When the timer is set in the PWM mode, the timer compares data between
the down counter and the compare data register and outputs the compare match signal if their contents
are matched. At the same time a compare match interrupt occurs. Furthermore, the timer output signal
rises with the underflow signal and falls with the compare match signal. As shown in Figure 4.10.5.1, the
cycle and duty ratio of the output signal can be controlled using the reload data register and the compare
data register, respectively, to generate a PWM signal. Note, however, the following condition must be
met: RLD (reload data) > CD (compare data) and CD ≠ 0. If RLD ≤ CD, the output signal is fixed at "1"
after the first underflow occurs and does not fall to "0".
The generated PWM signal can be output from the R02 output port terminal (see Section 4.10.8).
PWM mode
Input clock
RLD register
CD register
Down-counter value
Compare match signal
Underflow signal
Timer output signal
Compare match interrupt
Underflow interrupt
Normal mode
Compare match signal
Underflow signal
Timer output signal
Underflow interrupt
70 6 5 4 3 2 1 0 7 6 5 4
Fig. 4.10.5.1 Generating PWM waveform
7
6
3 2 1 0 7 6 5 4 3 2 1
CD register value
RLD register value + 1
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Programmable Timer)
4.10.6 16-bit timer (timer 0 + timer 1)
Timers 0 and 1 can be used as a 16-bit timer.
To use the 16-bit timer, write "1" to the timer 0 16-bit mode selection register MOD16.
The 16-bit timer is configured with timer 0 for low-order byte and timer 1 for high-order byte as shown in
Figure 4.10.6.1.
Timer 0 Timer 1
8 low-order bits 8 high-order bits
Reload data register
RLD00–RLD07
8-bit
down counter
Data buffer
PTD00–PTD07
Compare data register
CD00–CD07
PWM output selection
Reload data register
RLD10–RLD17
down counter
PTD10–PTD17
Comparator
Compare data register
CD10–CD17
PTSEL1
Data buffer
8-bit
Underflow
signal
OSC1
oscillation
circuit
OSC3
oscillation
circuit
f
OSC1
f
OSC3
Interrupt
TOUT
Input port
K13
Timer 0 Run/Stop
PTRUN0
Selector
CKSEL0
Divider
1/2
K13
Timer 0 + Timer 1
Timer 0 reset
Timer 1 reset
Prescaler
Prescaler
setting
PTPS00
PTPS01
Timer function setting
FCSEL
Pulse polarity setting
PLPOL
Event counter mode setting
EVCNT
PTRST0
PTRST1
Compare match signal
PWM waveform
generator
Clock
control
circuit
Fig. 4.10.6.1 Configuration of 16-bit timer
The registers for timer 0 are used to control the timer. The event counter and PWM output functions can
also be used.
Timer 1 operates with the timer 0 underflow signal as the count clock, so the clock and RUN/STOP
control registers for timer 1 become invalid. However, reload data (PTRSTx) must be preset to timers 0
and 1 separately.
The counter data in 16-bit mode must be read in the order below.
PTD00–PTD03 → PTD04–PDT07 → PTD10–PTD13 → PTD14–PTD17
Data bus
4.10.7 Interrupt function
The programmable timer can generate an interrupt due to an underflow of each timer or a compare
match of timers 0 and 1. See Figures 4.10.2.1 and 4.10.5.1 for the interrupt timing.
Note: The compare match interrupt can be generated only when timer 0 or 1 is set in PWM mode.
An underflow/compare match of timer x sets the corresponding interrupt factor flag IPTx/ICTCx to "1",
and generates an interrupt. The interrupt can also be masked by setting the corresponding interrupt mask
register EIPTx/ECTCx. However, the interrupt factor flag is set to "1" by an underflow/compare match of
the corresponding timer regardless of the interrupt mask register setting.
When timers 0 and 1 are used as a 16-bit timer, an interrupt is generated by an underflow of timer 1. In
this case, IPT0 is not set to "1" by a timer 0 underflow. The compare match interrupt uses ICTC1 of timer
1.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Programmable Timer)
4.10.8 Control of TOUT output
The programmable timer can generate a TOUT signal from the timer underflow and compare match
signals. The TOUT signal is generated by dividing the underflow signal by 2 in the normal mode. In the
PWM mode, the PWM signal generated by timer 0/1 is output as the TOUT signal. It is possible to select
which timer output is to be used by the TOUT output channel selection register CHSEL0.
Table 4.10.8.1 Selecting a timer for TOUT output
CHSEL0
1
0
Select timer 1 when generating the TOUT signal from the 16-bit timer output.
The TOUT signal can be output from the R02 output port terminal.
Figure 4.10.8.1 shows the configuration of the output port R02.
TOUT
Register
PTOUT
TOUT output timer
Timer 1
Timer 0
R02
(TOUT)
Data bus
Register
R02
Register
R02HIZ
Fig. 4.10.8.1 Configuration of R02
The output of a TOUT signal is controlled by the PTOUT register. When "1" is written to the PTOUT
register, the TOUT signal is output from the R02 output port terminal and when "0" is written, the
terminal goes to a high (V
DD) level. However, the data register R02 must always be "1" and the high
impedance control register R02HIZ must always be "0" (data output state).
Since the TOUT signal is generated asynchronously from the PTOUT register, a hazard within 1/2 cycle is
generated when the signal is turned on and off by setting the register.
Figure 4.10.8.2 shows the output waveform of the TOUT signal.
R02HIZ register
R02 register
PTOUT register
TOUT output
Fix at "0"
Fix at "1"
"1""0" "0"
Fig. 4.10.8.2 Output waveform of the TOUT signal
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Programmable Timer)
4.10.9 Transfer rate setting for serial interface
The signal that is made from underflows of timer 1 by dividing them in 1/2, can be used as the clock
source for the serial interface.
The programmable timer outputs the clock to the serial interface by setting timer 1 into RUN state
(PTRUN1 = "1"). It is not necessary to control with the PTOUT register.
PTRUN1
Timer 1 underflow
Source clock for serial I/F
Fig. 4.10.9.1 Synchronous clock of serial interface
A setting value for the RLD1x register according to a transfer rate is calculated by the following expression:
RLD1x = fosc / (2 ∗ bps ∗ division ratio of the prescaler) - 1
fosc:Oscillation frequency (OSC1/OSC3)
bps:Transfer rate
(00H can be set to RLD1x)
Be aware that the maximum clock frequency for the serial interface is limited to 1 MHz when OSC3 is
used as the clock source.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Programmable Timer)
4.10.10 I/O memory of programmable timer
Table 4.10.10.1 shows the I/O addresses and the control bits for the programmable timer.
Table 4.10.10.1(a) Control bits of programmable timer
Address Comment
MOD16
FFC0H
FFC1H
FFC2H
PTPS01 PTPS00 PTRST0 PTRUN0
FFC3H
PTPS11 PTPS10 PTRST1 PTRUN1
FFC4H
RLD03 RLD02 RLD01 RLD00
FFC6H
RLD07 RLD06 RLD05 RLD04
FFC7H
RLD13 RLD12 RLD11 RLD10
FFC8H
RLD17 RLD16 RLD15 RLD14
FFC9H
PTD03 PTD02 PTD01 PTD00
FFCCH
PTD07 PTD06 PTD05 PTD04
FFCDH
PTD13 PTD12 PTD11 PTD10
FFCEH
PTD17 PTD16 PTD15 PTD14
FFCFH
CD03 CD02 CD01 CD00
FFD2H
*1 Initial value at initial reset *3 Constantly "0" when being read
*2 Not set in the circuit
S1C63656 TECHNICAL MANUAL EPSON 79
Register
D3 D2
D1 D0 Name Init
EVCNT FCSEL PLPOL
R/W
00CHSEL0 PTOUT
RR/W
00CKSEL1 CKSEL0
RR/W
WR/WR/W
WR/WR/W
R/W
R/W
R/W
R/W
R
R
R
R
R/W
MOD16
EVCNT
FCSEL
PLPOL
∗
3
0
∗
3
0
CHSEL0
PTOUT
∗
3
0
∗
3
0
CKSEL1
CKSEL0
PTPS01
PTPS00
∗
PTRST0
PTRUN0
PTPS11
PTPS10
∗
PTRST1
PTRUN1
RLD03
RLD02
RLD01
RLD00
RLD07
RLD06
RLD05
RLD04
RLD13
RLD12
RLD11
RLD10
RLD17
RLD16
RLD15
RLD14
PTD03
PTD02
PTD01
PTD00
PTD07
PTD06
PTD05
PTD04
PTD13
PTD12
PTD11
PTD10
PTD17
PTD16
PTD15
PTD14
CD03
CD02
CD01
CD00
∗1
10
0
16 bits
0
Event ct.
0
With NR
0
∗
2
–
∗
2
–
00Timer 1OnTimer 0
∗
2
–
∗
2
–
00OSC3
OSC3
0
0
3
∗
2
Reset
–
0
Run
0
0
3
∗
2
Reset
–
0
Run
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16-bit mode selection
8 bits
Timer 0 counter mode selection
Timer
Timer 0 function selection (for event counter mode)
No NR
Timer 0 pulse polarity selection (for event counter mode)
Unused
Unused
TOUT output selection
Off
TOUT output control
Unused
Unused
OSC1
Prescaler 1 source clock selection
OSC1
Prescaler 0 source clock selection
Prescaler 0
division ratio
selection
Timer 0 reset (reload)
Invalid
Timer 0 Run/Stop
Stop
Prescaler 1
division ratio
selection
Timer 1 reset (reload)
Invalid
Timer 1 Run/Stop
Stop
[PTPS01, 00]
Division ratio
[PTPS11, 10]
Division ratio
MSB
Programmable timer 0 reload data (low-order 4 bits)
LSB
MSB
Programmable timer 0 reload data (high-order 4 bits)
LSB
MSB
Programmable timer 1 reload data (low-order 4 bits)
LSB
MSB
Programmable timer 1 reload data (high-order 4 bits)
LSB
MSB
Programmable timer 0 data (low-order 4 bits)
LSB
MSB
Programmable timer 0 data (high-order 4 bits)
LSB
MSB
Programmable timer 1 data (low-order 4 bits)
LSB
MSB
Programmable timer 1 data (high-order 4 bits)
LSB
MSB
Programmable timer 0 compare data (low-order 4 bits)
LSB
0
1/111/421/3231/256
0
1/111/421/3231/256
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Programmable Timer)
Table 4.10.10.1(b) Control bits of programmable timer
Address Comment
CD07 CD06 CD05 CD04
FFD3H
CD13 CD12 CD11 CD10
FFD4H
CD17 CD16 CD15 CD14
FFD5H
FFD8H
FFE0H
FFE1H
FFF0H
FFF1H
*1 Initial value at initial reset *3 Constantly "0" when being read
*2 Not set in the circuit
Register
D3 D2
D1 D0 Name Init
R/W
R/W
R/W
00PTSEL1 PTSEL0
RR/W
00ECTC1 ECTC0
RR/W
00EIPT1 EIPT0
RR/W
00ICTC1 ICTC0
RR/W
00IPT1 IPT0
RR/W
CD07
CD06
CD05
CD04
CD13
CD12
CD11
CD10
CD17
CD16
CD15
CD14
∗
3
0
∗
3
0
PTSEL1
PTSEL0
∗
3
0
∗
3
0
ECTC1
ECTC0
∗
3
0
∗
3
0
EIPT1
EIPT0
∗
3
0
∗
3
0
ICTC1
ICTC0
∗
3
0
∗
3
0
IPT1
IPT0
∗1
0
0
0
0
0
0
0
0
0
0
0
0
∗
2
–
∗
2
–
00PWM
∗
2
–
∗
2
–
00Enable
∗
2
–
∗
2
–
00Enable
∗
2
–
∗
2
–
0
0
∗
2
–
∗
2
–
0
0
10
Normal
PWM
Normal
Mask
Enable
Mask
Mask
Enable
Mask
(R)
(R)
Yes
No
(W)
(W)
Reset
Invalid
(R)
(R)
Yes
No
(W)
(W)
Reset
Invalid
MSB
Programmable timer 0 compare data (high-order 4 bits)
LSB
MSB
Programmable timer 1 compare data (low-order 4 bits)
LSB
MSB
Programmable timer 1 compare data (high-order 4 bits)
LSB
Unused
Unused
Programmable timer 1 PWM output selection
Programmable timer 0 PWM output selection
Unused
Unused
Interrupt mask register (Programmable timer 1 compare match)
Interrupt mask register (Programmable timer 0 compare match)
Unused
Unused
Interrupt mask register (Programmable timer 1 underflow)
Interrupt mask register (Programmable timer 0 underflow)
Unused
Unused
Interrupt factor flag (Programmable timer 1 compare match)
Interrupt factor flag (Programmable timer 0 compare match)
Unused
Unused
Interrupt factor flag (Programmable timer 1 underflow)
Interrupt factor flag (Programmable timer 0 underflow)
CKSEL0: Prescaler 0 source clock selection register (FFC2H•D0)
CKSEL1: Prescaler 1 source clock selection register (FFC2H•D1)
Selects the source clock of the prescaler.
When "1" is written: OSC3 clock
When "0" is written: OSC1 clock
Reading: Valid
The source clock for the prescaler is selected from OSC1 or OSC3. When "0" is written to the CKSELx
register, the OSC1 clock is selected as the input clock for the prescaler x (for timer x) and when "1" is
written, the OSC3 clock is selected.
When the event counter mode is selected for timer 0, the setting of CKSEL0 becomes invalid.
When timers 0 and 1 are used as a 16-bit timer, the setting of CKSEL1 becomes invalid.
At initial reset, these registers are set to "0".
Note: When the mask option to disable the OSC3 oscillation circuit is selected, no source clock can be
selected (fixed at OSC1). Do not set the CKSELx register to "1".
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Programmable Timer)
PTPS00, PTPS01: Timer 0 prescaler division ratio selection register (FFC3H•D2, D3)
PTPS10, PTPS11: Timer 1 prescaler division ratio selection register (FFC4H•D2, D3)
Sets the division ratio of the prescaler as shown in Table 4.10.10.2.
Table 4.10.10.2 Selection of prescaler division ratio
PTPSx1
PTPSx0
1
1
0
0
Prescaler division ratio
1
0
1
0
Source clock / 256
Source clock / 32
Source clock / 4
Source clock / 1
When the event counter mode is selected to timer 0, the setting of PTPS00 and PTPS01 becomes invalid.
When timers 0 and 1 are used as a 16-bit timer, the setting of PTPS10 and PTPS11 becomes invalid.
At initial reset, these registers are set to "0".
MOD16: 16-bit mode selection register (FFC0H•D3)
Selects whether timers 0 and 1 are used as a 16-bit timer or 2 channels of 8-bit timer.
When "1" is written: 16-bit timer
When "0" is written: 8-bit timer
Reading: Valid
When "1" is written to MOD16, a 16-bit timer is configured with timer 0 for low-order byte and timer 1 for
high-order byte. Use the timer 0 registers for control. When "0" is written to MOD16, timer 0 and timer 1
are used as independent 8-bit timers.
At initial reset, this register is set to "0".
EVCNT: Timer 0 counter mode selection register (FFC0H•D2)
Selects a counter mode for timer 0.
When "1" is written: Event counter mode
When "0" is written: Timer mode
Reading: Valid
The counter mode for timer 0 is selected from either the event counter mode or timer mode. When "1" is
written to the EVCNT register, the event counter mode is selected and when "0" is written, the timer
mode is selected.
At initial reset, this register is set to "0".
FCSEL: Timer 0 function selection register (FFC0H•D1)
Selects whether the noise rejector of the clock input circuit will be used or not in the event counter mode.
When "1" is written: With noise rejector
When "0" is written: Without noise rejector
Reading: Valid
When "1" is written to the FCSEL register, the noise rejector is used and counting is done by an external
clock (K13) with 0.98 msec* or more pulse width. The noise rejector allows the counter to input the clock
at the second falling edge of the internal 2,048 Hz* signal after changing the input level of the K13 input
port terminal. Consequently, the pulse width of noise that can reliably be rejected is 0.48 msec* or less.
(∗: f
OSC1 = 32.768 kHz)
When "0" is written to the FCSEL register, the noise rejector is not used and the counting is done directly
by an external clock input to the K13 input port terminal.
Setting of this register is effective only when timer 0 is used in the event counter mode.
At initial reset, this register is set to "0".
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Programmable Timer)
PLPOL: Timer 0 pulse polarity selection register (FFC0H•D0)
Selects the count pulse polarity in the event counter mode.
When "1" is written: Rising edge
When "0" is written: Falling edge
Reading: Valid
The count timing in the event counter mode (timer 0) is selected from either the falling edge of the
external clock input to the K13 input port terminal or the rising edge. When "0" is written to the PLPOL
register, the falling edge is selected and when "1" is written, the rising edge is selected.
Setting of this register is effective only when timer 0 is used in the event counter mode.
At initial reset, this register is set to "0".
PTSEL0: Timer 0 PWM mode selection register (FFD8H•D0)
PTSEL1: Timer 1 PWM mode selection register (FFD8H•D1)
Sets timer 0 or 1 for PWM output.
When "1" is written: PWM output
When "0" is written: Normal output
Reading: Valid
When "1" is written to the PTSELx, the compare data register becomes valid and PWM waveform is
generated using the underflow and compare match signals. When "0" is written, the timer outputs the
normal clock generated from the underflow signal. When timers 0 and 1 are used as a 16-bit timer, the
setting of PTSEL1 becomes invalid.
At initial reset, these registers are set to "0".
RLD00–RLD07: Timer 0 reload data register (FFC6H, FFC7H)
RLD10–RLD17: Timer 1 reload data register (FFC8H, FFC9H)
Sets the initial value for the counter.
The reload data written in this register is loaded to the respective counters. The counter counts down
using the data as the initial value for counting.
Reload data is loaded to the counter when the counter is reset by writing "1" to the PTRSTx register, or
when counter underflow occurs.
At initial reset, these registers are set to "00H".
PTD00–PTD07: Timer 0 counter data (FFCCH, FFCDH)
PTD10–PTD17: Timer 1 counter data (FFCEH, FFCFH)
Count data in the programmable timer can be read from these latches.
The low-order 4 bits of the count data in timer x can be read from PTDx0–PTDx3, and the high-order data
can be read from PTDx4–PTDx7. Since the high-order 4 bits are held by reading the low-order 4 bits, be
sure to read the low-order 4 bits first.
Since these latches are exclusively for reading, the writing operation is invalid.
At initial reset, these counter data are set to "00H".
CD00–CD07: Timer 0 compare data register (FFD2H, FFD3H)
CD10–CD17: Timer 1 compare data register (FFD4H, FFD5H)
Set the compare data for PWM output.
When the timer is set in the PWM mode, the compare data set in this register is compared with the
counter data and outputs the compare match signal if they are matched. The compare match signal is
used for generating an interrupt and controlling the duty ratio of the PWM waveform.
At initial reset, these registers are set to "00H".
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Programmable Timer)
PTRST0: Timer 0 reset (reload) (FFC3H•D1)
PTRST1: Timer 1 reset (reload) (FFC4H•D1)
Resets the timer and presets reload data to the counter.
When "1" is written: Reset
When "0" is written: No operation
Reading: Always "0"
By writing "1" to PTRSTx, the reload data in the reload register RLDx0–RLDx7 is preset to the counter in
timer x. When the counter is preset in the RUN status, the counter restarts immediately after presetting.
In the case of STOP status, the reload data is preset to the counter and is maintained.
No operation results when "0" is written.
Since these bits are exclusively for writing, always set to "0" during reading.
PTRUN0: Timer 0 RUN/STOP control register (FFC3H•D0)
PTRUN1: Timer 1 RUN/STOP control register (FFC4H•D0)
Controls the RUN/STOP of the counter.
When "1" is written: RUN
When "0" is written: STOP
Reading: Valid
The counter in timer x starts counting down by writing "1" to the PTRUNx register and stops by writing
"0". In STOP status, the counter data is maintained until the counter is reset or is set in the next RUN
status. When STOP status changes to RUN status, the data that has been maintained can be used for
resuming the count.
At initial reset, these registers are set to "0".
CHSEL0: TOUT output channel selection register (FFC1H•D1)
Selects the channel used for TOUT signal output.
When "1" is written: Timer 1
When "0" is written: Timer 0
Reading: Valid
This register selects which timer's output (timer 0 or timer 1) is used to generate a TOUT signal. When "0"
is written to the CHSEL0 register, timer 0 is selected and when "1" is written, timer 1 is selected. In the 16bit mode (MOD16 = "1"), timer 1 is always selected regardless of this register setting.
At initial reset, this register is set to "0".
PTOUT: TOUT output control register (FFC1H•D0)
Turns TOUT signal output on and off.
When "1" is written: On
When "0" is written: Off
Reading: Valid
PTOUT is the output control register for the TOUT signal. When "1" is written to the register, the TOUT
signal is output from the output port terminal R02 and when "0" is written, the terminal goes to a high
(V
DD) level. However, the data register R02 must always be "1" and the high impedance control register
R02HIZ must always be "0" (data output state).
At initial reset, this register is set to "0".
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EIPT0, ECTC0: Timer 0 interrupt mask registers (FFE1H•D0, FFE0H•D0)
EIPT1, ECTC1: Timer 1 interrupt mask registers (FFE1H•D1, FFE0H•D1)
These registers are used to select whether to mask the programmable timer interrupt or not.
When "1" is written: Enabled
When "0" is written: Masked
Reading: Valid
EIPTx and ECTCx are the interrupt mask registers that respectively correspond to the counter underflow
and compare match interrupt factors. Interrupts set to "1" are enabled and interrupts set to "0" are disabled.
At initial reset, these registers are set to "0".
IPT0, ICTC0: Timer 0 interrupt factor flags (FFF1H•D0, FFF0H•D0)
IPT1, ICTC1: Timer 1 interrupt factor flags (FFF1H•D1, FFF0H•D1)
These flags indicate the status of the programmable timer interrupt.
When "1" is read: Interrupt has occurred
When "0" is read: Interrupt has not occurred
When "1" is written: Flag is reset
When "0" is written: Invalid
IPTx and ICTCx are the interrupt factor flags that respectively correspond to the interrupts for counter
underflow and compare match, and are set to "1" by generation of each factor.
The underflow interrupt factor is generated at the point where the counter underflows.
The compare match interrupt factor is generated if the counter data and the compare data are matched
when the timer is set in the PWM mode.
The software can judge from these flags whether there is a programmable timer interrupt. However, even
if the interrupt is masked, the flags are set to "1" by an underflow and compare match of the corresponding counter.
These flags are reset to "0" by writing "1" to them.
After an interrupt occurs, the same interrupt will occur again if the interrupt enabled state (I flag = "1") is
set or the RETI instruction is executed unless the interrupt factor flag is reset. Therefore, be sure to reset
(write "1" to) the interrupt factor flag in the interrupt service routine before shifting to the interrupt
enabled state.
At initial reset, these flags are set to "0".
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4.10.11 Programming notes
(1) When reading counter data, be sure to read the low-order 4 bits (PTDx0–PTDx3) first. Furthermore,
the high-order 4 bits (PTDx4–PTDx7) are not latched when the low-order 4 bits are read. Therefore,
the high-order 4 bits should be read within 0.73 msec (when f
low-order 4 bits. When the CPU is running with the OSC1 clock and the programmable timer is
running with the OSC3 clock, stop the timer before reading the counter data. The counter running
with OSC3 counts down for the value listed in Table 4.10.11.1 while the CPU running with OSC1 reads
the low-order 4 bits and high-order 4 bits of the counter data by two instructions.
Table 4.10.11.1 Counter change with OSC3 between readings low-order and high-order data with OSC1
Count clock
OSC3/1
OSC3/4
OSC3/32
Counter change between reading
In 16-bit mode, the counter data must be read in the order below.
PTD00–PTD03 → PTD04–PDT07 → PTD10–PTD13 → PTD14–PTD17
(2) The programmable timer actually enters RUN/STOP status in synchronization with the falling edge
of the input clock after writing to the PTRUNx register. Consequently, when "0" is written to the
PTRUNx register, the timer enters STOP status at the point where the counter is decremented (-1). The
PTRUNx register maintains "1" for reading until the timer actually stops.
Figure 4.10.11.1 shows the timing chart for the RUN/STOP control.
OSC1 is 32.768 kHz) from reading the
0200H
001AH
0002H
Input clock
PTRUNx (RD)
PTRUNx (WR)
PTDx0–PTDx7 42H 41H 40H 3FH 3EH 3DH
"1" (RUN)
writing
"0" (STOP)
writing
Fig. 4.10.11.1 Timing chart for RUN/STOP control
It is the same even in the event counter mode. Therefore, be aware that the counter does not enter
RUN/STOP status if a clock is not input after setting the RUN/STOP control register (PTRUN0).
(3) Since the TOUT signal is generated asynchronously from the PTOUT register, a hazard within 1/2
cycle is generated when the signal is turned on and off by setting the register.
(4) When the OSC3 oscillation clock is selected for the clock source, it is necessary to turn the OSC3
oscillation ON, prior to using the programmable timer. However the OSC3 oscillation circuit requires
a time at least 5 msec from turning the circuit ON until the oscillation stabilizes. Therefore, allow an
adequate interval from turning the OSC3 oscillation circuit ON to starting the programmable timer.
Refer to Section 4.3, "Oscillation Circuit", for the control and notes of the OSC3 oscillation circuit.
At initial reset, the OSC3 oscillation circuit is set in the off state.
(5) After an interrupt occurs, the same interrupt will occur again if the interrupt enabled state (I flag =
"1") is set or the RETI instruction is executed unless the interrupt factor flag is reset. Therefore, be sure
to reset (write "1" to) the interrupt factor flag in the interrupt service routine before shifting to the
interrupt enabled state.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Programmable Timer)
(6) For the reason below, pay attention to the reload data write timing when changing the interval of the
programmable timer interrupts while the programmable timer is running.
The programmable timer counts down at the falling edge of the input clock and at the same time it
generates an interrupt if the counter underflows. Then it starts loading the reload data to the counter
and the counter data is determined at the next rising edge of the input clock (period shown in as ➀ in
the figure).
Input clock
Counter data
(continuous mode)
03H 02H 01H 00H 25H 24H
➀
(Reload data = 25H)
Counter data is determined by reloading.Underflow (interrupt is generated)
Fig. 4.10.11.2 Reload timing for programmable timer
To avoid improper reloading, do not rewrite the reload data after an interrupt occurs until the counter
data is determined including the reloading period ➀. Be especially careful when using the OSC1 (lowspeed clock) as the clock source of the programmable timer and the CPU is operating with the OSC3
(high-speed clock).
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4.11 Serial Interface (SIN, SOUT, SCLK, SRDY)
4.11.1 Configuration of serial interface
The S1C63656 has a synchronous clock type 8 bits serial interface built-in.
The configuration of the serial interface is shown in Figure 4.11.1.1.
The CPU, via the 8-bit shift register, can read the serial input data from the SIN terminal. Moreover, via
the same 8-bit shift register, it can convert parallel data to serial data and output it to the SOUT terminal.
The synchronous clock for serial data input/output may be set by selecting by software any one of three
types of master mode (internal clock mode: when the S1C63656 is to be the master for serial input/
output) and a type of slave mode (external clock mode: when the S1C63656 is to be the slave for serial
input/output).
Also, when the serial interface is used at slave mode, SRDY signal which indicates whether or not the
serial interface is available to transmit or receive can be output to the SRDY terminal.
SD0–SD7
SIN
(P10)
SCLK
or
SCLK
(P12)
SCS0 SCS1
Serial clock
selector
Serial clock
generator
Serial I/F
activating
circuit
SCTRG
Shift register (8 bits)
SCPS
Serial clock
counter
f
OSC1
Programmable
timer 1 underflow
signal
Output
latch
ESOUT
Serial I/F interrupt
control circuit
SOUT
(P11)
Interrupt
request
SRDY
or
SRDY
(P13)
Fig. 4.11.1.1 Configuration of serial interface
The input/output ports of the serial interface are shared with the I/O ports P10–P13, and function of
these ports can be selected through the software.
P10–P13 terminals and serial input/output correspondence are as follows:
Master mode Slave mode
P10 = SIN (I) P10 = SIN (I)
P11 = SOUT (O) P11 = SOUT (O)
P12 = SCLK (O) P12 = SCLK (I)
P13 = I/O port (I/O) P13 = SRDY (O)
The SOUT output using the P11 port is enabled when "1" is written to the ESOUT register. If ESOUT is
"0", P11 functions as a general-purpose I/O port.
Note: At initial reset, P10–P13 are set to I/O ports.
When using the serial interface, switch the function (ESIF = "1", ESOUT = "1") in the initial routine.
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4.11.2 Mask option
Terminal specification
Since the input/output terminals of the serial interface is shared with the I/O ports (P10–P13), the
mask option that selects the output specification for the I/O port is also applied to the serial interface.
The output specification of the terminals SOUT, SCLK (during the master mode) and SRDY (during
the slave mode) that are used as output in the input/output port of the serial interface is respectively
selected by the mask options of P11, P12 and P13. Either complementary output or P-channel open
drain output can be selected as the output specification. However, when P-channel open drain output
is selected, do not apply a voltage exceeding the power supply voltage to the terminal.
Furthermore, the pull-down resistor for the SIN terminal and the SCLK terminal (during slave mode)
that are used as input terminals can be selected by mask option. The pull-down register can be added
by the mask options of P10 and P12. When "without pull-down" is selected, take care that the floating
status does not occur.
Polarity of synchronous clock and ready signal
Polarity of the synchronous clock and the ready signal that is output in the slave mode can be selected
from either positive polarity (high active, SCLK & SRDY) or negative polarity (low active, SCLK &
_________
SRDY).
When operating the serial interface in the slave mode, the synchronous clock is input from a external
device. Be aware that the terminal specification is pull-down only and a pull-up resistor cannot be
built in if negative polarity is selected.
In the following explanation, it is assumed that positive polarity (SCLK, SRDY) has been selected.
_________
4.11.3 Master mode and slave mode of serial interface
The serial interface of the S1C63656 has two types of operation mode: master mode and slave mode.
The master mode uses an internal clock as the synchronous clock for the built-in shift register, and
outputs this internal clock from the SCLK (P12) terminal to control the external (slave side) serial device.
In the slave mode, the synchronous clock output from the external (master side) serial device is input
from the SCLK (P12) terminal and it is used as the synchronous clock for the built-in shift register.
The master mode and slave mode are selected by writing data to the SCS1 and SCS0 registers.
When the master mode is selected, a synchronous clock may be selected from among 3 types as shown in
Table 4.11.3.1.
Table 4.11.3.1 Synchronous clock selection
SCS1
1
1
0
0
∗ The maximum clock is limited to 1 MHz.
When the programmable timer is selected, the signal that is generated by dividing the underflow signal
of the programmable timer (timer 1) in 1/2 is used as the synchronous clock. In this case, the programmable timer must be controlled before operating the serial interface. Refer to Section 4.10, "Programmable
Timer" for the control of the programmable timer.
At initial reset, the slave mode (external clock mode) is selected.
Moreover, the synchronous clock, along with the input/output of the 8-bit serial data, is controlled as
follows:
•In the master mode, after output of 8 clocks from the SCLK (P12) terminal, clock output is automatically suspended and the SCLK (P12) terminal is fixed at low level (or high level when negative
polarity is selected by mask option).
•In the slave mode, after input of 8 clocks to the SCLK (P12) terminal, subsequent clock inputs are
masked.
SCS0
1
0
1
0
Mode
Master mode
Slave mode
Synchronous clock
OSC1
OSC1 /2
Programmable timer ∗
External clock ∗
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface)
A sample basic serial input/output portion connection is shown in Figure 4.11.3.1.
S1C63656
SCLK
SOUT
SIN
Input terminal
External
serial device
CLK
SOUT
SIN
READY
S1C63656
SCLK
SOUT
SIN
SRDY
External
serial device
CLK
SOUT
SIN
Input terminal
(a) Master mode (b) Slave mode
Fig. 4.11.3.1 Sample basic connection of serial input/output section
4.11.4 Data input/output and interrupt function
The serial interface of S1C63656 can input/output data via the internal 8-bit shift register. The shift
register operates by synchronizing with either the synchronous clock output from the SCLK (P12) terminal (master mode), or the synchronous clock input to the SCLK (P12) terminal (slave mode).
The serial interface generates an interrupt on completion of the 8-bit serial data input/output. Detection
of serial data input/output is done by counting of the synchronous clock SCLK; the clock completes
input/output operation when 8 counts (equivalent to 8 cycles) have been made and then generates an
interrupt.
The serial data input/output procedure is explained below:
Serial data output procedure and interrupt
The S1C63656 serial interface is capable of outputting parallel data as serial data, in units of 8 bits.
By setting the parallel data to the data registers SD0–SD3 (FF72H) and SD4–SD7 (FF73H) and writing
"1" to SCTRG bit (FF70H•D1), it synchronizes with the synchronous clock and the serial data is output
to the SOUT (P11) terminal. The synchronous clock used here is as follows: in the master mode,
internal clock which is output to the SCLK (P12) terminal while in the slave mode, external clock
which is input from the SCLK (P12) terminal.
Shift timing of serial data is as follows:
• When positive polarity is selected for the synchronous clock (mask option):
The serial data output to the SOUT (P11) terminal changes at the rising edge of the clock input or
output from/to the SCLK (P12) terminal. The data in the shift register is shifted at the rising edge of
the SCLK signal when the SCPS register is "1" and is shifted at the falling edge of the SCLK signal
when the SCPS register is "0".
• When negative polarity is selected for the synchronous clock (mask option):
The serial data output to the SOUT (P11) terminal changes at the falling edge of the clock input or
output from/to the SCLK (P12) terminal. The data in the shift register is shifted at the falling edge of
_________
the SCLK signal when the SCPS register (FF71H•D2) is "1" and is shifted at the rising edge of the
_________
_________
SCLK signal when the SCPS register is "0".
When the output of the 8-bit data from SD0 to SD7 is completed, the interrupt factor flag ISIF
(FFF2H•D0) is set to "1" and an interrupt occurs. Moreover, the interrupt can be masked by the
interrupt mask register EISIF (FFE2H•D0). However, regardless of the interrupt mask register setting,
the interrupt factor flag is set to "1" after output of the 8-bit data.
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Serial data input procedure and interrupt
The S1C63656 serial interface is capable of inputting serial data as parallel data, in units of 8 bits.
The serial data is input from the SIN (P10) terminal, synchronizes with the synchronous clock, and is
sequentially read in the 8-bit shift register. The synchronous clock used here is as follows: in the
master mode, internal clock which is output to the SCLK (P12) terminal while in the slave mode,
external clock which is input from the SCLK (P12) terminal.
Shift timing of serial data is as follows:
• When positive polarity is selected for the synchronous clock (mask option):
The serial data is read into the built-in shift register at the rising edge of the SCLK signal when the
SCPS register is "1" and is read at the falling edge of the SCLK signal when the SCPS register is "0".
The shift register is sequentially shifted as the data is fetched.
• When negative polarity is selected for the synchronous clock (mask option):
The serial data is read into the built-in shift register at the falling edge of the SCLK signal when the
_________
_________
SCPS register is "1" and is read at the rising edge of the SCLK signal when the SCPS register is "0". The
shift register is sequentially shifted as the data is fetched.
When the input of the 8-bit data from SD0 to SD7 is completed, the interrupt factor flag ISIF is set to
"1" and an interrupt is generated. Moreover, the interrupt can be masked by the interrupt mask
register EISIF. However, regardless of the interrupt mask register setting, the interrupt factor flag is
set to "1" after input of the 8-bit data.
The data input in the shift register can be read from data registers SD0–SD7 by software.
Serial data input/output permutation
The S1C63656 allows the input/output permutation of serial data to be selected by the SDP register
(FF71H•D3) as to either LSB first or MSB first. The block diagram showing input/output permutation
in case of LSB first and MSB first is provided in Figure 4.11.4.1. The SDP register should be set before
setting data to SD0–SD7.
SIN
SIN
Address [FF73H]
SD7 SD6 SD5 SD4
Address [FF72H] Address [FF73H]
SD0 SD1 SD2 SD3
Address [FF72H]
SD3 SD2 SD1 SD0
(LSB first)
SD4 SD5 SD6 SD7
(MSB first)
Output
latch
Output
latch
SOUT
SOUT
Fig. 4.11.4.1 Serial data input/output permutation
SRDY signal
When the S1C63656 serial interface is used in the slave mode (external clock mode), SRDY signal is
used to indicate whether the internal serial interface is available to transmit or receive data for the
master side (external) serial device. SRDY signal is output from the SRDY (P13) terminal.
Output timing of SRDY signal is as follows:
•When positive polarity is selected (mask option):
SRDY signal goes "1" (high) when the S1C63656 serial interface is available to transmit or receive data;
normally, it is at "0" (low).
SRDY signal changes from "0" to "1" immediately after "1" is written to SCTRG and returns from "1" to
"0" when "1" is input to the SCLK (P12) terminal (i.e., when the serial input/output begins transmitting or receiving data). Moreover, when high-order data is read from or written to SD4–SD7, the SRDY
signal returns to "0".
•When negative polarity is selected (mask option):
_________
SRDY signal goes "0" (low) when the S1C63656 serial interface is available to transmit or receive data;
normally, it is at "1" (high).
_________
SRDY signal changes from "1" to "0" immediately after "1" is written to SCTRG and returns from "0" to
"1" when "0" is input to the SCLK (P12) terminal (i.e., when the serial input/output begins transmitting or receiving data). Moreover, when high-order data is read from or written to SD4–SD7, the SRDY
signal returns to "1".
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