Epson S1C63616 Technical Manual

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Page 1

S1C63616

Technical Manual

Rev.1.0

Page 2

NOTICE

No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no representation that this material is applicable to products requiring high level reliability, such as, medical products. Moreover, no license to any intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright infringement of a third party. This material or portions thereof may contain technology or the subject relating to strategic products under the control of the Foreign Exchange and Foreign Trade Law of Japan and may require an export license from the Ministry of Economy, Trade and Industry or other approval from another government agency.

All brands or product names mentioned herein are trademarks and/or registered trademarks of their respective companies.

Page 3

Configuration of product number

Devices

C 17xxx F 00E1

Packing specifications

00 : Besides tape & reel 0A : TCP BL 2 directions 0B : Tape & reel BACK 0C : TCP BR 2 directions 0D : TCP BT 2 directions 0E : TCP BD 2 directions 0F : Tape & reel FRONT 0G: TCP BT 4 directions 0H : TCP BD 4 directions 0J : TCP SL 2 directions 0K : TCP SR 2 directions 0L : Tape & reel LEFT 0M: TCP ST 2 directions 0N : TCP SD 2 directions 0P : TCP ST 4 directions 0Q: TCP SD 4 directions 0R : Tape & reel RIGHT 99 : Specs not fixed

Specification

Package

D: die form; F: QFP, B: BGA

Model number

Model name

C: microcomputer, digital products

Product classification

S1: semiconductor

Development tools

S5U1

C 17000 H2 1

Packing specifications

00: standard packing

Version

1: Version 1

Tool type

Hx : ICE Dx : Evaluation board Ex : ROM emulation board Mx: Emulation memory for external ROM Tx : A socket for mounting

Cx : Compiler package Sx : Middleware package

Corresponding model number

17xxx: for S1C17xxx

Tool classification

C: microcomputer use

Product classification

S5U1: development tool for semiconductor products

Page 4

SIC63616-(Rev. 1.0) NO. 4

Contents

Chapter 1 outline ___________________________________________________1

1.1 Features ......................................................................................................... 1

1.2 Block Diagram ............................................................................................... 2

1.3 Pin Layout Diagram ...................................................................................... 3

1.4 Pin Description .............................................................................................. 5

1.5 Mask Option .................................................................................................. 6

Chapter 2 power supply and initial reset _______________________________9

2.1 Power Supply ................................................................................................. 9

2.1.1 Operating voltage .......................................................................................... 9

2.1.2 Internal power supply circuit ........................................................................ 9

2.2 Initial Reset .................................................................................................. 11

2.2.1 Reset terminal (RESET)............................................................................... 11

2.2.2 Simultaneous high input to P1x ports (P10-P13) ........................................12

2.2.3 Internal register at initial resetting .............................................................12

2.2.4 Terminal settings at initial resetting ............................................................ 13

2.3 Test Terminal (TEST) ................................................................................... 13

Chapter 3 Cpu, roM, raM _________________________________________14

3.1 CPU ............................................................................................................. 14

3.2 Code ROM ................................................................................................... 14

3.3 RAM ............................................................................................................. 14

3.4 Data ROM .................................................................................................... 15

Chapter 4 peripheral CirCuits and operation _______________________________16

4.1 Memory Map ............................................................................................... 16

4.2 Power Control .............................................................................................. 32

4.2.1 Conﬁguration of power supply circuit ......................................................... 32

4.2.2 Controlling the power supply voltage booster/halver and voltage regulators 33

4.2.3 Heavy load protection function ................................................................... 34

4.2.4 I/O memory for power control ..................................................................... 34

4.2.5 Programming notes ..................................................................................... 36

4.3 Watchdog Timer ........................................................................................... 37

4.3.1 Conﬁguration of watchdog timer ................................................................. 37

4.3.2 Interrupt function ........................................................................................ 37

4.3.3 I/O memory of watchdog timer .................................................................... 38

4.3.4 Programming notes ..................................................................................... 38

4.4 Oscillation Circuit ....................................................................................... 39

4.4.1 Conﬁguration of oscillation circuit ............................................................. 39

4.4.2 Mask option ................................................................................................. 39

4.4.3 OSC1 oscillation circuit .............................................................................. 40

4.4.4 OSC3 oscillation circuit .............................................................................. 40

4.4.5 Switching the CPU clock ............................................................................. 41

4.4.6 I/O memory of oscillation circuit ................................................................42

4.4.7 Programming notes ..................................................................................... 43

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SIC63616-(Rev. 1.0) NO. 5

4.5 I/O Ports

4.5.1 Conﬁguration of I/O ports ........................................................................... 44

4.5.2 Mask option ................................................................................................. 45

4.5.3 I/O control registers and input/output mode ............................................... 46

4.5.4 Input interface level ..................................................................................... 46

4.5.5 Pull-down during input mode ...................................................................... 46

4.5.6 Special output .............................................................................................. 47

4.5.7 Key input interrupt function ........................................................................ 49

4.5.8 I/O memory of I/O ports .............................................................................. 51

4.5.9 Programming notes ..................................................................................... 61

(P00-P03, P10-P13, P20-P23 and P40-P43)

............... 44

4.6 LCD Driver .................................................................................................. 62

4.6.1 Conﬁguration of LCD driver ....................................................................... 62

4.6.2 Power supply for LCD driving ....................................................................63

4.6.3 Controlling LCD display ............................................................................. 65

4.6.4 Display memory ........................................................................................... 69

4.6.5 LCD contrast adjustment ............................................................................. 72

4.6.6 I/O memory of LCD driver .......................................................................... 73

4.6.7 Programming notes ..................................................................................... 78

4.7 Clock Timer ................................................................................................. 79

4.7.1 Conﬁguration of clock timer ........................................................................ 79

4.7.2 Controlling clock manager .......................................................................... 79

4.7.3 Data reading and hold function ..................................................................79

4.7.4 Interrupt function ........................................................................................ 80

4.7.5 I/O memory of clock timer ........................................................................... 81

4.7.6 Programming notes ..................................................................................... 83

4.8 Stopwatch Timer .......................................................................................... 84

4.8.1 Conﬁguration of stopwatch timer ................................................................ 84

4.8.2 Controlling clock manager .......................................................................... 84

4.8.3 Counter and prescaler ................................................................................. 85

4.8.4 Capture buffer and hold function ................................................................85

4.8.5 Stopwatch timer RUN/STOP and reset ........................................................ 86

4.8.6 Direct input function and key mask ............................................................. 87

4.8.7 Interrupt function ........................................................................................ 90

4.8.8 I/O memory of stopwatch timer ................................................................... 92

4.8.9 Programming notes ..................................................................................... 96

4.9 Programmable Timer ................................................................................... 97

4.9.1 Conﬁguration of programmable timer......................................................... 97

4.9.2 Controlling clock manager ....................................................................... 100

4.9.3 Basic count operation ................................................................................ 101

4.9.4 Event counter mode (Timers 0, 2, 4 and 6) ............................................... 102

4.9.5 PWM mode (Timers 0-7) ........................................................................... 103

4.9.6 16-bit timer mode (Timer 0 + 1, Timer 2 + 3, Timer 4 + 5, Timer 6 + 7) . 104

4.9.7 Interrupt function ...................................................................................... 105

4.9.8 Control of TOUT output ............................................................................105

4.9.9 Clock output to serial interface and R/f converter .................................... 106

4.9.10 I/O memory of programmable timer ........................................................ 107

4.9.11 Programming notes ................................................................................. 119

4.10 Serial Interface .......................................................................................... 121

4.10.1 Conﬁguration of serial interface ............................................................. 121

4.10.2 Serial interface terminals ........................................................................ 121

4.10.3 Mask option ............................................................................................. 122

4.10.4 Operating mode of serial interface ......................................................... 123

4.10.5 Setting synchronous clock........................................................................ 124

4.10.6 Data input/output and interrupt function ................................................ 125

4.10.7 Data transfer in SPI mode ....................................................................... 128

4.10.8 I/O memory of serial interface ................................................................129

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SIC63616-(Rev. 1.0) NO. 6

4.10.9 Programming notes ................................................................................. 134

4.11 Sound Generator........................................................................................ 135

4.11.1 Conﬁguration of sound generator ........................................................... 135

4.11.2 Controlling clock manager ...................................................................... 135

4.11.3 Control of buzzer output .......................................................................... 135

4.11.4 Setting of buzzer frequency and sound level ............................................ 136

4.11.5 Digital envelope ...................................................................................... 137

4.11.6 One-shot output ....................................................................................... 138

4.11.7 I/O memory of sound generator ..............................................................139

4.11.8 Programming notes ................................................................................. 142

4.12 Integer Multiplier ....................................................................................... 143

4.12.1 Conﬁguration of integer multiplier .......................................................... 143

4.12.2 Controlling clock manager ...................................................................... 143

4.12.3 Multiplication mode ................................................................................ 143

4.12.4 Division mode .......................................................................................... 144

4.12.5 Execution cycle ........................................................................................ 145

4.12.6 I/O memory of integer multiplier ............................................................. 146

4.12.7 Programming note ................................................................................... 148

4.13 R/f Converter ............................................................................................. 149

4.13.1 Conﬁguration of R/f converter ................................................................. 149

4.13.2 Controlling clock manager ...................................................................... 150

4.13.3 Connection terminals and CR oscillation circuit .................................... 150

4.13.4 Operation of R/f conversion .................................................................... 152

4.13.5 Interrupt function .................................................................................... 154

4.13.6 Continuous oscillation function............................................................... 156

4.13.7 I/O memory of R/f converter .................................................................... 156

4.13.8 Programming notes ................................................................................. 160

4.14 SVD (Supply Voltage Detection) Circuit .................................................... 161

4.14.1 Conﬁguration of SVD circuit ................................................................... 161

4.14.2 SVD operation ......................................................................................... 161

4.14.3 I/O memory of SVD circuit ...................................................................... 162

4.14.4 Programming notes ................................................................................. 162

4.15 Interrupt and HALT/SLEEP ...................................................................... 163

4.15.1 Interrupt factor ........................................................................................ 165

4.15.2 Interrupt mask .........................................................................................166

4.15.3 Interrupt vector........................................................................................ 167

4.15.4 I/O memory of interrupt .......................................................................... 169

4.15.5 Programming notes ................................................................................. 172

Chapter 5 suMMary of notes ________________________________________ 173

5.1 Notes for Low Current Consumption ......................................................... 173

5.2 Summary of Notes by Function .................................................................. 174

5.3 Precautions on Mounting .......................................................................... 179

Chapter 6 BasiC external wiring diagraM _____________________________ 181

Chapter 7 eleCtriCal CharaCteristiCs_________________________________ 182

7.1 Absolute Maximum Rating ........................................................................ 182

7.2 Recommended Operating Conditions ........................................................ 182

7.3 DC Characteristics .................................................................................... 183

7.4 Analog Circuit Characteristics and Current Consumption ....................... 184

7.5 Oscillation Characteristics ........................................................................ 187

7.6 Serial Interface AC Characteristics ........................................................... 188

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SIC63616-(Rev. 1.0) NO. 7

7.7 Timing Chart .............................................................................................. 189

7.8 Characteristics Curves (reference value) .................................................. 190

Chapter 8 paCkage ________________________________________________201

8.1 Plastic Package .......................................................................................... 201

8.2 Ceramic Package for Test Samples ............................................................ 202

Chapter 9 pad layout ______________________________________________203

9.1 Diagram of Pad Layout ............................................................................. 203

9.2 Pad Coordinates ........................................................................................ 204

appendix a

peripheral CirCuit Boards for s1C6f632 ________________________205

A.1 Names and Functions of Each Part ........................................................... 205

A.1.1 S5U1C63000P6......................................................................................... 205

A.1.2 S5U1C6F632P2 ........................................................................................ 208

A.2 Connecting to the Target System................................................................ 210

A.3 Downloading to S5U1C63000P6 .............................................................. 214

A.3.1 Downloading Circuit Data 1 -

when new ICE (S5U1C63000H2/S5U1C63000H6) is used ............ 214

A.3.2 Downloading Circuit Data 2 -

when previous ICE (S5U1C63000H1) is used.................................215

A.4 Usage Precautions ..................................................................................... 216

A.4.1 Operational precautions ........................................................................... 216

A.4.2 Differences with the actual IC...................................................................216

A.5 Product Speciﬁcations ............................................................................... 219

A.5.1 Speciﬁcations of S5U1C63000P6 ............................................................. 219

A.5.2 Speciﬁcations of S5U1C6F632P2 ............................................................. 220

revision history _________________________________________221

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SIC63616-(Rev. 1.0) NO. P1

chapter 1 Outline

The S1C63616 is a microcomputer which has a 4-bit CPU S1C63000 as the core CPU, ROM (16,384 words × 13 bits), RAM (2,048 words × 4 bits), multiply-divide circuit, serial interface, watchdog timer, programmable timer, time base counters (2 systems), a dot matrix LCD driver that can drive a maximum 1,280 dots of LCD panel, and an R/f converter that can measure temperature and humidity using sensors such as a thermistor. The S1C63616 features low current consumption, this makes it suitable for battery driven clocks and watches with temperature and humidity measurement functions.

1.1 Features

OSC1 oscillation circuit OSC3 oscillation circuit Instruction set

Instruction execution time

ROM capacity

RAM capacity

I/O port

Serial interface LCD driver

Time base counter

Programmable timer

Watchdog timer Sound generator

R/f converter ........................................

Multiply-divide circuit ...........................

Supply voltage detection (SVD) circuit External interrupt Internal interrupt

Power supply voltage Operating temperature range Current consumption (Typ.)

Shipment form

............................................Basic instruction: 47 types (411 instructions with all)

............................................Code ROM: 16,384 words × 13 bits

............................................Data memory: 2,048 words × 4 bits

....................................................... 16 bits (pull-down resistors may be incorporated∗1

..........................................1 port (8-bit clock synchronous system)

.................................................40 segments × 32 commons, 48 segments × 24 commons, or

...........................................TQFP15-128pin or die form

...........................32.768 kHz (Typ.) crystal oscillation circuit

...........................

.......................During operation at 32.768 kHz: 61 µsec 122 µsec 183 µsec

...................................Clock timer

................................16-bit timer × 4 ch. (each 16-bit timer is conﬁgurable to two 8-bit

.........................................Built-in

....................................... With envelope and 1-shot output functions

......................................Key input interrupt: 8 systems

.......................................Clock timer interrupt: 8 systems

...............................1.6 to 5.5 V

................. -40 to 85°C

....................During SLEEP (32 kHz) 0.08 µA

4.2 MHz (Max.) ceramic or 1.8 MHz (Typ.) CR oscillation circuit (∗1)

Addressing mode: 8 types

During operation at 4 MHz: 0.5 µsec 1 µsec 1.5 µsec

Data ROM: 2,048 words × 4 bits

Display memory: 2,048 bits

Shared with 4 serial I/F I/O pins, 4 R/f converter I/O pins, and 3 special output pins ∗2)

56 segments × 16 commons (∗2)

Stopwatch timer (1/1000 sec, with direct key input function)

timer channels ∗2)

2 ch., CR oscillation type, 20-bit counter Supports resistive humidity sensors 8-bit accumulator × 1 ch. Multiplication: 8 bits × 8 bits → 16-bit product Division: 16 bits ÷ 8 bits → 8-bit quotient and 8-bit remainder Programmable 16 detection voltage levels (∗2)

Stopwatch timer interrupt: 4 systems Programmable timer interrupt: 16 systems Serial interface interrupt: 1 system R/f converter interrupt: 3 systems

During HALT (32 kHz) 0.6 µA During running (32 kHz) 2.5 µA During running (4 MHz) 320 µA

1: Can be selected with mask option ∗2: Can be selected with software

∗

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1.2 Block Diagram

OSC1 OSC2 OSC3 OSC4

TEST

COM0–15

(SEG55–40)COM16–31

SEG0–39

C1–5

D1–2

OSC

CA–CG

RESET

P00–03, P10–13 P20–23 P40–43

SEN0(P02), REF0(P01), RFOUT(P03) RFIN0(P00) SEN1, HUD, REF1 RFIN1

BZ(P03)

TOUT_A(P13)

SIN(P22) SOUT(P21) SRDY/SS(P23) SCLK(P20)

Core CPU S1C63000

Code ROM

16,384 words × 13 bits

System Reset

Control

Interrupt

Generator

OSC

RAM

2,048 words × 4 bits

Data ROM

2,048 words × 4 bits

LCD Controller

& Driver

Power

Controller

SVD

Watchdog

Timer

Clock

Timer

Stopwatch

Timer

Programmable

Timer

Sound

Generator

Integer Multiplier

Test

R/f Converter

I/O Port

Serial

Interface

SIC63616-(Rev. 1.0) NO. P2

Fig. 1.2.1 Block diagram

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1.3 Pin Layout Diagram

12345678910111213141516171819202122232425262728293031

96959493929190898887868584838281807978777675747372717069686766

SEG17

N.C.

SEG18

SEG19

SEG20

SEG21

SEG22

SEG23

SEG24

SEG25

SEG26

SEG27

SEG28

SEG29

SEG30

SEG31

SEG32

SEG33

SEG34

SEG35

SEG36

SEG37

SEG38

SEG39

SEG40/COM31

SEG41/COM30

SEG42/COM29

SEG43/COM28

N.C.

COM0

N.C.

HUD

SEN1

REF1

RFIN1

P00/RFIN0

P01/REF0

P02/SEN0

VDDP03/RFOUT/BZ

P10/RUN/LAP

P11/RUN/LAP

P12/EVIN_A

P13/TOUT_A

P20/SCLK

P21/SOUT

P22/SIN

P23/SRDY/SS/FOUT

P40

P41/EVIN_B

P42/EVIN_C

P43/EVIN_D

RESET

TEST

OSCVD1

N.C.

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33

97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128

OSC2 OSC1 V

OSC4 OSC3 V

CA CB CC CD CE CF CG V

COM16/SEG55 COM17/SEG54 COM18/SEG53 COM19/SEG52 COM20/SEG51 COM21/SEG50 COM22/SEG49 COM23/SEG48 COM24/SEG47 COM25/SEG46 COM26/SEG45 COM27/SEG44

COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8

COM9 COM10 COM11 COM12 COM13 COM14 COM15

SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8

SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16

TQFP15-128pin (Plastic Package)

SIC63616-(Rev. 1.0) NO. P3

Fig. 1.3.1 Pin layout diagram (TQFP15-128pin)

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QFP17-144pin (Ceramic Package for Test Samples)

SIC63616-(Rev. 1.0) NO. P4

N.C. N.C. N.C.

COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8

COM9 COM10 COM11 COM12 COM13 COM14 COM15

SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8

SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16

RFIN1

N.C.

103

102

N.C.

P00/RFIN0

P01/REF0

P02/SEN0

VDDP03/RFOUT/BZ

P10/RUN/LAP

P11/RUN/LAP

P12/EVIN_A

P13/TOUT_A

P20/SCLK

P21/SOUT

P22/SIN

P23/SRDY/SS/FOUT

P40

P41/EVIN_B

P42/EVIN_C

P43/EVIN_D

RESET

TEST

N.C.

999897969594939291908988878685848382818079787776757473

101

100

109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144

N.C.

108

HUD

107

SEN1

REF1

106

105

N.C.

104

1234567891011121314151617181920212223242526272829303132333435

OSC

N.C.

OSC2

OSC1

70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37

OSC4 OSC3 V

VC1 VC2 VC3 VC4 VC5 CA CB CC CD CE CF CG V

VSS COM16/SEG55 COM17/SEG54 COM18/SEG53 COM19/SEG52 COM20/SEG51 COM21/SEG50 COM22/SEG49 COM23/SEG48 COM24/SEG47 COM25/SEG46 COM26/SEG45 COM27/SEG44

N.C. N.C. N.C. N.C.

N.C.

SEG17

SEG18

SEG19

SEG20

SEG21

SEG22

SEG23

SEG24

SEG25

SEG26

SEG27

SEG28

SEG29

SEG30

SEG31

SEG32

SEG33

SEG34

SEG35

SEG36

SEG37

SEG38

SEG39

Fig. 1.3.2 Pin layout diagram (QFP17-144pin)

SEG40/COM31

SEG41/COM30

SEG42/COM29

N.C.

SEG43/COM28

N.C.

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1.4 Pin Description

SIC63616-(Rev. 1.0) NO. P5

Table 1.4.1 Pin description

Pin name

V VSS VD1 VOSC VD2 VC1–VC5 CA–CE CF, CG OSC1 OSC2 OSC3 OSC4 P00/RFIN0 P01/REF0 P02/SEN0 P03/RFOUT/BZ

P10/RUN/LAP P11/RUN/LAP P12/EVIN_A P13/TOUT_A P20/SCLK P21/SOUT P22/SIN P23/SRDY/SS /FOUT P40 P41/EVIN_B P42/EVIN_C P43/EVIN_D COM0–COM15 COM16–COM31 /SEG55–SEG40 SEG0–SEG39 RFIN1 REF1 SEN1 HUD RESET TEST

Die

53, 76

39, 56, 80

59 60

40 52–48 47–43 42, 41

85–100

38–23

101–118, 1–22

Pin No.

TQFP15-128

59, 85

45, 62, 89

68 68

46 58–54 53–49 48, 47

96–111

44–33, 29–26

112–128, 4–25,

QFP17-144

67, 96

53, 70, 100

73 75

54 66–62 61–57 56, 55

112–127

52–41, 28–25

128–144, 2–24,

103 105 106 107

I/O

Power (+) supply pins

–

Power (–) supply pins

–

Internal logic voltage regulator output pin

–

Crystal oscillation circuit operating voltage output pin

–

Power supply voltage booster/halver output pin

–

LCD drive voltage output pins

–

LCD system voltage boost capacitor connecting pins

–

Power supply voltage boost/halving capacitor connecting pins

–

Crystal oscillation input pin

Crystal oscillation output pin

Ceramic or CR oscillation input pin (mask option)

Ceramic or CR oscillation output pin (mask option)

I/O port or R/f converter Ch.0 CR oscillation input pin (software switch)

I/O port or R/f converter Ch.0 reference oscillation output pin (software switch)

I/O

I/O port or R/f converter Ch.0 CR oscillation output pin (software switch)

I/O

I/O port, R/f converter oscillation frequency output pin, or sound output pin

I/O

(software switch) I/O port or stopwatch Run/Lap input pin (software switch)

I/O

I/O port or stopwatch Run/Lap input pin (software switch)

I/O

I/O port or event counter input pin (software switch)

I/O

I/O port or programmable timer output pin (software switch)

I/O

I/O port or serial I/F clock I/O pin (software switch)

I/O

I/O port or serial I/F data output pin (software switch)

I/O

I/O port or serial I/F data input pin (software switch)

I/O

I/O port, serial I/F ready signal output, SS signal input or FOUT clock output pin

I/O

(software switch) I/O port pin

I/O

I/O port or event counter input pin (software switch)

I/O

I/O port or event counter input pin (software switch)

I/O

I/O port or event counter input pin (software switch)

I/O

LCD common output pins

LCD common output or segment output pins (software switch)

LCD segment output pins

R/f converter Ch.1 CR oscillation input pin

R/f converter Ch.1 reference oscillation output pin

R/f converter Ch.1 CR oscillation output pin

R/f converter AC-bias oscillation output pin for humidity sensor

Initial reset input pin

Test input pin

Function

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Page 13

SIC63616-(Rev. 1.0) NO. P6

1.5 Mask Option

Mask options shown below are provided for the S1C63616. Several hardware speciﬁcations are prepared in each mask option, and one of them can be selected according to the application. The function option generator winfog, that has been prepared as the development software tool of S1C63616, is used for this selection. Mask pattern of the IC is ﬁnally generated based on the data created by the winfog. Refer to the "S5U1C63000A Manual" for the winfog.

(1) OSC1 oscillation circuit

The OSC1 oscillator type is ﬁxed at crystal oscillation. Refer to Section 4.4.3, "OSC1 oscillation circuit", for details.

(2) OSC3 oscillation circuit

The OSC3 oscillator type can be selected from ceramic oscillation or CR oscillation (external R). Refer to Section 4.4.4, "OSC3 oscillation circuit", for details.

(3) RESET terminal pull-down resistor

This option is used to select whether an internal pull-down resistor is incorporated into the RESET input port. Refer to Section 2.2.1, "Reset terminal (RESET)", for details.

(4) I/O port pull-down resistor

This option is used to select whether an internal pull-down resistor that will be enabled in input mode is incorporated into each I/O port (P00–P03, P10–P13, P20–P23, P40–P43). Refer to Section 4.5.2, "Mask option", for details.

(5) Output speciﬁcation of the I/O port

This option is used to select either complementary output or P-channel open drain output as the output cell type of each I/O port (P00–P03, P10–P13, P20–P23, P40–P43). Refer to Section 4.5.2, "Mask option", for details.

(6) Multiple key entry reset function (by simultaneous high input to the P1x ports)

This option is used to select whether the function to reset the IC by pressing multiple keys simultaneously is implemented or not. A combination of the P1x ports (P10–P13) to be used for this function can also be selected. Refer to Section 2.2.2, "Simultaneous high input to P1x ports (P10–P13)", for details.

(7) Time authorize circuit for the multiple key entry reset function

When the multiple key entry reset option (option (6)) is selected, the time authorize circuit can also be incorporated. The time authorize circuit measures the high pulse width of the simultaneous input signals and asserts the reset signal if it is longer than the predetermined time. This option is not available when the multiple key entry reset option is not selected. Refer to Section 2.2.2, "Simultaneous high input to P1x ports (P10–P13)", for details.

(8) LCD drive power supply

This option is used to select the LCD drive bias from 1/5 bias (with VC2 reference voltage), 1/4 bias (with VC2 reference voltage) and 1/4 bias (with VC1 reference voltage). Refer to Section 4.6.2, "Power supply for LCD driving", for details.

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SIC63616-(Rev. 1.0) NO. P7

The following is the option list for the S1C63616. Multiple selections are available in each option item as indicated in the option list. Select the speciﬁcations that meet the target system and check the appropriate box. Be sure to record the speciﬁcations for unused functions too, according to the instructions provided.

1. OSC1 SYSTEM CLOCK

1. Crystal

2. OSC3 SYSTEM CLOCK

1. CR (external R)

2. Ceramic (4.2 MHz)

3. RESET PORT PULL DOWN RESISTOR

 •RESET 1. Use 2. Not Use

4. I/O PORT PULL DOWN RESISTOR

 •P00 1. Use 2. Not Use  •P01 1. Use 2. Not Use  •P02 1. Use 2. Not Use  •P03 1. Use 2. Not Use  •P10 1. Use 2. Not Use  •P11 1. Use 2. Not Use  •P12 1. Use 2. Not Use  •P13 1. Use 2. Not Use  •P20 1. Use 2. Not Use  •P21 1. Use 2. Not Use  •P22 1. Use 2. Not Use  •P23 1. Use 2. Not Use  •P40 1. Use 2. Not Use  •P41 1. Use 2. Not Use  •P42 1. Use 2. Not Use  •P43 1. Use 2. Not Use

5. I/O PORT OUTPUT SPECIFICATION

 •P00 1. Complementary 2. Pch Open Drain  •P01 1. Complementary 2. Pch Open Drain  •P02 1. Complementary 2. Pch Open Drain  •P03 1. Complementary 2. Pch Open Drain  •P10 1. Complementary 2. Pch Open Drain  •P11 1. Complementary 2. Pch Open Drain  •P12 1. Complementary 2. Pch Open Drain  •P13 1. Complementary 2. Pch Open Drain  •P20 1. Complementary 2. Pch Open Drain  •P21 1. Complementary 2. Pch Open Drain  •P22 1. Complementary 2. Pch Open Drain  •P23 1. Complementary 2. Pch Open Drain  •P40 1. Complementary 2. Pch Open Drain  •P41 1. Complementary 2. Pch Open Drain  •P42 1. Complementary 2. Pch Open Drain  •P43 1. Complementary 2. Pch Open Drain

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6. MULTIPLE KEY ENTRY RESET COMBINATION

1. Not Use

2. Use <P10, P11>

3. Use <P10, P11, P12>

4. Use <P10, P11, P12, P13>

7. MULTIPLE KEY ENTRY RESET TIME AUTHORIZE

1. Not Use

2. Use

8. LCD DRIVING POWER

1. 1/5 Bias, VC2 Reference

2. 1/4 Bias, VC2 Reference

3. 1/4 Bias, VC1 Reference

SIC63616-(Rev. 1.0) NO. P8

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SIC63616-(Rev. 1.0) NO. P9

chapter 2 pOwer Supply and initial reSet

2.1 Power Supply

This section explains the operating voltage and the conﬁguration of the internal power supply circuit of the S1C63616.

2.1.1 Operating voltage

The S1C63616 operating power voltage is as follows:

1.6 V to 5.5 V

2.1.2 Internal power supply circuit

The S1C63616 incorporates the power supply circuit shown in Figure 2.1.2.1. When voltage within the range described above is supplied to VDD (+) and VSS (GND), all the voltages needed for the internal circuits are generated internally in the IC.

External

power

supply

∗1

∗2

CG V VD1

VOSC

VC1 VC2 VC3 VC4 VC5

CB CC CD

Power supply voltage

booster/halver

VD2

∗3

VDD

VCSEL

Oscillation system

voltage regulator

VOSC

LCD system

voltage

regulator

VC1–VC5

DBON

HLON

VDD

Internal voltage

regulator

∗4

Internal circuits

VD1

OSC3

oscillation circuit

OSC1

oscillation circuit

LCD

driver

circuit

OSC3 OSC4

OSC1 OSC2

COM0–COM31 SEG0–SEG39

∗1 Leave these terminals open when the power supply voltage booster/halver is not used. ∗2 Connect when the 1/5 bias LCD drive power is used. (Leave the terminal open when the 1/4 bias LCD drive power is used.) ∗3 Can be selected as the power source for the LCD system voltage regulator when the power supply voltage booster/halver

operates in boost mode. ∗4 HLON is prohibited from use.

Fig. 2.1.2.1 Conﬁguration of power supply circuit

The power supply circuit is broadly divided into four blocks.

Table 2.1.2.1 Power supply circuit

Circuit

Internal and oscillation system voltage regulators Internal circuits and OSC3 oscillation circuit OSC1 oscillation circuit LCD system voltage regulator LCD driver

Power supply voltage (VDD) Internal voltage regulator Oscillation system voltage regulator Power supply voltage booster/halver (halving mode) LCD system voltage regulator

Power supply circuit

Output voltage

—

VD1

VOSC

VDD or VD2

VC1—VC5

Note: The supply voltage booster/halver circuit can perform either boosting or halving the supply voltage at

a time. The boosting and halving operations cannot be performed simultaneously.

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SIC63616-(Rev. 1.0) NO. P10

Power supply voltage booster/halver circuit

The S1C63616 supports a wide supply voltage (VDD) range that exceeds the operating voltage range of the voltage regulator (LCD system voltage regulator). The power supply voltage booster/halver circuit generates the VD2 voltage to drive the voltage regulators when the supply voltage VDD is out of the operating voltage range of the voltage regulators.

Table 2.1.2.2 Relationship between supply voltage VDD and voltage regulator operating voltage

Power supply

voltage VDD

1.6 to 2.5 V

2.5 to 5.5 V

When a VC2 reference voltage option for the LCD drive power supply is selected, the LCD system voltage regulator must be driven with a 2.5 V or more operating voltage. Therefore, the LCD system voltage regulator can be driven with VDD if 2.5 V or more supply voltage VDD is used. When the supply voltage VDD is less than 2.5 V, drive the power supply voltage booster/halver in boost mode to generate VD2 and use it to drive the LCD system voltage regulator. The VD2 voltage generated in boost mode is about double the VDD voltage level.

The VD2 voltage is not required when the power supply voltage (VDD) is within the range from 2.5 V to

5.5 V (1.6 V to 5.5 V when the VC1 reference LCD drive power option is selected). In this case the power supply voltage booster/halver can be turned off. The S1C63616 allows software to control the power supply voltage booster/halver and to select the power source of the voltage regulator. Refer to Section 4.2, "Power Control", for details.

Power source for

LCD system voltage regulator

VD2 (≈ VDD × 2)

VDD

Internal voltage regulator

The internal voltage regulator generates the operating voltage VD1 for driving the internal logic circuits and the OSC3 oscillation circuit.

Oscillation system voltage regulator

The oscillation system voltage regulator generates the V circuit and is provided separately with the internal voltage regulator to stabilize the oscillation and to reduce power consumption.

OSC

voltage for driving the OSC1 oscillation

LCD system voltage regulator

The LCD system voltage regulator generates the LCD drive voltages VC1 to VC5. See Chapter 7, "Electrical Characteristics" for the voltage values. In the S1C63616, the LCD drive voltage is supplied to the built-in LCD driver which drives the LCD panel connected to the SEG and COM terminals.

Notes:• BesurenottousetheVD1,VD2,V

circuits.

 • IfVDDequaltoorlessthan2.5VisusedasthepowersourcefortheLCDsystemvoltage

regulator,theVC1toVC5voltagescannotbegeneratedwithinspecications(whenaVC2 reference

voltage option is selected).

 • HLONisprohibitedfromuse.Alwaysbesuretosetto"0".

OSC

andVC1toVC5 terminal output voltages to drive external

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SIC63616-(Rev. 1.0) NO. P11

2.2 Initial Reset

The S1C63616 should be reset to initialize the internal circuits. There are two ways of doing this.

(1) External initial reset by the RESET terminal (2) External initial reset by simultaneous high input to P10–P13 ports (mask option)

The circuits are initialized by either (1) or (2). When the power is turned on, be sure to initialize using the reset function. It is not guaranteed that the circuits are initialized by only turning the power on.

Figure 2.2.1 shows the conﬁguration of the initial reset circuit.

OSC1

OSC2

P10

P11

P12

P13

RESET

OSC1

oscillation

circuit

Mask option

Divider

1 kHz 16 Hz 1 Hz

Time

authorize

circuit

Mask option

Noise reject circuit

R Q

Internal initial reset

VSS

Fig. 2.2.1 Conﬁguration of initial reset circuit

2.2.1 Reset terminal (RESET)

Initial reset can be executed externally by setting the reset terminal to a high level (VDD). After that the initial reset is released by setting the reset terminal to a low level (VSS) and the CPU starts operating. The reset input signal is maintained by the RS latch and becomes the internal initial reset signal. The RS latch is designed to be released by a 16 Hz signal (high) that is divided by the OSC1 clock. Therefore in normal operation, a maximum of 16,396/f

OSC1

seconds (500 msec when f the internal initial reset is released after the reset terminal goes to low level. Be sure to maintain a reset input of 0.1 msec or more. However, when turning the power on, the reset terminal should be set at a high level as in the timing shown in Figure 2.2.1.1. Note that a reset pulse shorter than 100 nsec is rejected as noise.

1.3 V

VDD

OSC1

= 32.768 kHz) is needed until

RESET

Power on

0.9•VDD or more (high level)

0.5•V

2.0 msec or more

Fig. 2.2.1.1 Initial reset at power on

Theresetterminalshouldbesetto0.9•VDD or more (high level) until the supply voltage becomes 1.3 V or

more.

Afterthat,alevelof0.5•VDD or more should be maintained more than 2.0 msec.

The reset terminal incorporates a pull-down resistor and a mask option is provided to select whether the resistor is used or not.

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SIC63616-(Rev. 1.0) NO. P12

2.2.2 Simultaneous high input to P1x ports (P10-P13)

Another way of executing initial reset externally is to input high level signals simultaneously to the P1x ports (P10–P13) selected by a mask option. Since this initial reset passes through the noise reject circuit, maintain the speciﬁed input port terminals at high level for at least 1.5 msec (when the oscillation frequency f operation. The noise reject circuit does not operate immediately after turning the power on until the oscilla-tion. The noise reject circuit does not operate immediately after turning the power on until the oscillation circuit starts oscillating. Therefore, maintain the speciﬁed input port terminals at high level for at least 1.5 msec (when the oscillation frequency f

OSC1

is 32.768 kHz) after oscillation starts.

Table 2.2.2.1 shows the combinations of P1x ports (P10–P13) that can be selected by a mask option.

Table 2.2.2.1 Combinations of P1x ports

Not use

P10∗P11

P10∗P11∗P12

P10∗P11∗P12∗P13

When, for instance, mask option 4 (P10∗P11∗P12∗P13) is selected, initial reset is executed when the signals input to the four ports P10–P13 are all high at the same time. When 2 or 3 is selected, the initial reset is done when a key entry including a combination of selected input ports is made. Further, the time authorize circuit mask option is selected when this reset function is selected. The time authorize circuit checks the input time of the simultaneous high input and performs initial reset if that time is the deﬁned time (1 to 2 sec) or more. If using this function, make sure that the speciﬁed ports do not go high at the same time during ordinary operation.

OSC1

is 32.768 kHz) during normal

2.2.3 Internal register at initial resetting

Initial reset initializes the CPU as shown in Table 2.2.3.1. The registers and ﬂags which are not initialized by initial reset should be initialized in the program if necessary. In particular, the stack pointers SP1 and SP2 must be set as a pair because all the interrupts including NMI are masked after initial reset until both the SP1 and SP2 stack pointers are set with software. When data is written to the EXT register, the E ﬂag is set and the following instruction will be executed in the extended addressing mode. If an instruction which does not permit extended operation is used as the following instruction, the operation is not guaranteed. Therefore, do not write data to the EXT register for initialization only. Refer to the "S1C63000 Core CPU Manual" for extended addressing and usable instructions.

Table 2.2.3.1 Initial values

Name

Data register A

Data register B

Extension register EXT

Index register X

Index register Y

Program counter

Stack pointer SP1

Stack pointer SP2

Zero flag

Carry flag

Interrupt flag

Extension flag

Queue register

CPU core

Symbol

EXT

SP1

SP2

Number of bits

Setting value

Undefined

0110H

Undefined

Name

RAM

Display memory

Other peripheral circuits

Peripheral circuits

Number of bits

–

See Section 4.1, "Memory Map".

∗

Setting value

Undefined

∗

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SIC63616-(Rev. 1.0) NO. P13

2.2.4 Terminal settings at initial resetting

The I/O port (P) terminals are shared with special output terminals and input/output terminals of the serial interface, R/f converter, stopwatch timer and programmable timer (event counter). These functions are selected by the software. At initial reset, these terminals are conﬁgured to the general purpose I/O port terminals. Set them according to the system in the initial routine. Table 2.2.4.1 shows the list of the shared terminal settings.

Table 2.2.4.1 List of shared terminal settings

Terminal

name

P00

P00 (Input & pulled down∗)

P01

P01 (Input & pulled down∗)

P02

P02 (Input & pulled down∗)

P03

P03 (Input & pulled down∗)

P10

P10 (Input & pulled down∗)

P11

P11 (Input & pulled down∗)

P12

P12 (Input & pulled down∗)

P13

P13 (Input & pulled down∗)

P20

P20 (Input & pulled down∗)

P21

P21 (Input & pulled down∗)

P22

P22 (Input & pulled down∗)

P23

P23 (Input & pulled down∗)

P40

P40 (Input & pulled down∗)

P41

P41 (Input & pulled down∗)

P42

P42 (Input & pulled down∗)

P43

P43 (Input & pulled down∗)

Terminal status

at initial reset

TOUT_A

When special outputs/peripheral functions are used (selected by software)

Special output

TOUT

FOUT

∗ When "With Pull-Down" is selected by mask option (high impedance when "Gate Direct" is selected)

BZBZMaster

SCLK(O)

SOUT(O)

SIN(I)

Serial I/F

SCLK(I)

SOUT(O)

SIN(I)

SRDY(O)/SS(I)

Slave

R/f converter

RFIN0

REF0

SEN0

RFOUT

Stopwatch

direct input

RUN/LAP

Event

counter

EVIN_A

EVIN_B

EVIN_C

EVIN_D

For setting procedure of the functions, see explanations for each of the peripheral circuits.

2.3 Test Terminal (TEST)

This is the terminal used for the factory inspection of the IC. During normal operation, connect the TEST terminal to VSS.

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SIC63616-(Rev. 1.0) NO. P14

0000H

3FFFH

4000H

FFFFH

0000H

0100H

0101H

0110H

0100H

0101H

0102H

0103H

0104H

0105H

0106H

0107H

0108H

0109H

010AH

010BH

010CH

010DH

010EH

010FH

Program area

NMI vector

Hardware

interrupt vectors

Program start address

Program area

Code ROM

Unused area

13 bits

S1C63000 core CPU

program space

Watchdog timer

R/f converter

Programmable timer 0

Programmable timer 1

Programmable timer 2

Programmable timer 3

Programmable timer 4

Programmable timer 5

Programmable timer 6

Programmable timer 7

Serial interface

Key input interrupt (P1)

Key input interrupt (P4)

Stopwatch

Clock timer (128/64/32/16 Hz)

Clock timer (8/4/2/1 Hz)

S1C63616

program area

Chapter 3 Cpu, roM, raM

3.1 CPU

The S1C63616 has a 4-bit core CPU S1C63000 built-in as its CPU part. Refer to the "S1C63000 Core CPU Manual" for the S1C63000.

3.2 Code ROM

The built-in code ROM is a mask ROM for loading programs, and has a capacity of 16,384 words × 13 bits. The core CPU can linearly access the program space up to step FFFFH from step 0000H, however, the program area of the S1C63616 is step 0000H to step 3FFFH. The program start address after initial reset is assigned to step 0110H. The non-maskable interrupt (NMI) vector and hardware interrupt vectors are allocated to step 0100H and steps 0101H–010FH, respectively.

Fig. 3.2.1 Conﬁguration of code ROM

3.3 RAM

The RAM is a data memory for storing various kinds of data, and has a capacity of 2,048 words × 4 bits. The RAM area is assigned to addresses 0000H to 07FFH on the data memory map. Addresses 0100H to 01FFH are 4-bit/16-bit data accessible areas and in other areas it is only possible to access 4-bit data. When programming, keep the following points in mind.

(1) Part of the RAM area is used as a stack area for subroutine call and register evacuation, so pay atten-

tion not to overlap the data area and stack area.

(2) The S1C63000 core CPU handles the stack using the stack pointer for 4-bit data (SP2) and the stack

pointer for 16-bit data (SP1). 16-bit data are accessed in stack handling by SP1, therefore, this stack area should be allocated to the area where 4-bit/16-bit access is possible (0100H to 01FFH). The stack pointers SP1 and SP2 change cyclically within their respective range: the range of SP1 is 0000H to 07FFH and the range of SP2 is 0000H to 00FFH. Therefore, pay attention to the SP1 value because it may be set to 0200H or more exceeding the 4-bit/16-bit accessible range in the S1C63616 or it may be set to 00FFH or less. Memory accesses except for stack operations by SP1 are 4-bit data access. After initial reset, all the interrupts including NMI are masked until both the stack pointers SP1 and SP2 are set by software. Further, if either SP1 or SP2 is re-set when both are set already, the interrupts including NMI are masked again until the other is re-set. Therefore, the settings of SP1 and SP2 must be done as a pair.

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SIC63616-(Rev. 1.0) NO. P15

(3) Subroutine calls use 4 words (for PC evacuation) in the stack area for 16-bit data (SP1). Interrupts

use 4 words (for PC evacuation) in the stack area for 16-bit data (SP1) and 1 word (for F register evacuation) in the stack area for 4-bit data.

0000H

0800H

8000H

8800H

F000H

FF00H

FFFFH

RAM

Unused area

Data ROM

Unused area

Display memory area

Unused area

I/O memory area

0000H

00FFH

0100H

01FFH

0200H

07FFH

4-bit access area

(SP2 stack area)

4/16-bit access area

(SP1 stack area)

4-bit access area

(Data area)

4 bits

Fig. 3.3.1 Conﬁguration of data RAM

3.4 Data ROM

The data ROM is a mask ROM for loading various static data such as a character generator, and has a capacity of 2,048 words × 4 bits. The data ROM is assigned to addresses 8000H to 87FFH on the data memory map, and the data can be read using the same data memory access instructions as the RAM.

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SIC63616-(Rev. 1.0) NO. P16

Chapter 4 peripheral CirCuits and operation

The peripheral circuits of S1C63616 (timer, I/O, etc.) are interfaced with the CPU in the memory mapped I/ O method. Thus, all the peripheral circuits can be controlled by accessing the I/O memory on the memory map using the memory operation instructions. The following sections explain the detailed operation of each peripheral circuit.

4.1 Memory Map

The S1C63616 data memory consists of 2,048-word RAM, 2,048-word mask ROM, 2,048-bit display memory and 170-word peripheral I/O memory. Figure 4.1.1 shows the overall memory map of the S1C63616, and Table 4.1.1 the peripheral circuits' (I/O space) memory maps.

0000H

RAM area

0800H

Unused area

8000H

Data ROM area

8800H

Unused area

F000H

Display memory area

F36FH

Unused area

F000H

FF00H FFFFH

Display memory area

Unused area

I/O memory area

FF00H

Peripheral I/O area

FFFFH

Fig. 4.1.1 Memory map

Note: Memory is not implemented in unused areas within the memory map. Further, some non-implemen-

tation areas and unused (access prohibition) areas exist in the peripheral I/O area. If the program that accesses these areas is generated, its operation cannot be guaranteed. Refer to the I/O memory maps shown in Table 4.1.1 for the peripheral I/O area.

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SIC63616-(Rev. 1.0) NO. P17

Table 4.1.1 (a) I/O memory map (FF00H-FF16H)

Address Comment

CLKCHG

FF00H

FF01H

VDSEL VCSEL HLON DBON

FF02H

VCHLMOD VDHLMOD

FF03H

SVDS3 SVDS2 SVDS1 SVDS0

FF04H

FF05H

FOUT3 FOUT2 FOUT1 FOUT0

FF10H

NRSP11 NRSP10 NRSP01 NRSP00

FF11H

FLCKS1 FLCKS0 VCCKS1 VCCKS0

FF12H

General

FF14H

General RFCKS2 RFCKS1 RFCKS0

FF15H

MDCKE SGCKE SWCKE RTCKE

FF16H

D3 D2

D1 D0 Name Init

OSCC 0 0

R/W R

0 0 WDEN WDRST

R/W WR

R/W

General LPWR

R/W

0 0 SVDDT SVDON

R R/W

R/W

SIFCKS2 SIFCKS1 SIFCKS0

R/W

CLKCHG

OSCC

∗

WDEN

WDRST

VDSEL VCSEL

HLON

DBON VCHLMOD VDHLMOD

General

LPWR

SVDS3 SVDS2 SVDS1 SVDS0

∗

SVDDT

SVDON

FOUT3

FOUT2

FOUT1

FOUT0

NRSP11 NRSP10 NRSP01 NRSP00 FLCKS1 FLCKS0 VCCKS1 VCCKS0

General

SIFCKS2

SIFCKS1

SIFCKS0

General

RFCKS2

RFCKS1

RFCKS0

MDCKE SGCKE SWCKE

RTCKE

∗1

OSC3OnOSC1

∗

–

∗

–

∗

–

∗

–

Reset

Enable

Reset

∗

0 0 0 0 0 0 0 0 0 0 0 0

∗

–

∗

–

00LowOnNormal

0 0 0 0 0 0 0 0 0

Enable

1 0

V On On On On

1 0

CPU clock switch

Off

OSC3 oscillation On/Off

Unused

Disable

Watchdog timer enable

Invalid

Watchdog timer reset (writing)

General-purpose register

Power source select for LCD system voltage regulator

Off

Power voltage booster/halver halving mode On/Off

Off

Power voltage booster/halver boost mode On/Off

Heavy load protection mode On/Off for LCD system voltage regulator

Off

Heavy load protection mode On/Off for internal voltage regulator

Off

General-purpose register

LCD system voltage regulator On/Off

Off

SVD criteria voltage setting

[SVDS3–0] Voltage (V) [SVDS3–0] Voltage (V)

1.6

2.5

1.8

2.6

Unused

SVD evaluation data

Off

SVD circuit On/Off

FOUT frequency selection

[FOUT3–0] Frequency [FOUT3–0] Frequency [FOUT3–0] Frequency

Key input interrupt noise reject frequency selection

[NRSP11, 10] (P40–P43) Frequency [NRSP01, 00] (P10–P13)

Frequency Frame frequency selection VC boost frequency selection

OSC1/256

Off1f

OSC1/2

OSC3/16

[FLCKS1, 0] Frequency

[VCCKS1, 0] Frequency

fOSC1/643fOSC1/324fOSC1/165fOSC1/4

OSC1

OSC3/8

Off

32 Hz124 Hz216 Hz38 Hz

General-purpose register

Serial I/F

clock frequency

selection

[SIFCKS2–0] Frequency

Off/External

General-purpose register

R/f converter

clock frequency

selection

Integer multiplier clock enable

Disable

Sound generator clock enable

Disable

Stopwatch timer clock enable

Disable

Clock timer clock enable

Disable

[RFCKS2–0] Frequency

Remarks

1 Initial value at initial reset

∗

2 Not set in the circuit

∗

3 Constantly "0" when being read

∗

1.9 10

2.7

OSC3/256

OSC3/4

OSC1/16

Off

PT1

Off

PT1

2.0

2.1 12

2.9

OSC3/64

OSC3/2

OSC1/64

2.2 13

3.0

2.8

2 kHz

OSC1

OSC1/2

OSC3

OSC3/2

OSC1

OSC1/2

OSC3

OSC3/2

2.3

2.4

3.1

3.2

OSC3/32

OSC3

OSC1/256

2, 3

Prohibited

fOSC1/4

fOSC3/4

fOSC1/4

fOSC3/4

3240-0412

Page 25

SIC63616-(Rev. 1.0) NO. P18

Table 4.1.1 (b) I/O memory map (FF18H-FF20H)

Address Comment

PTPS03 PTPS02 PTPS01 PTPS00

FF18H

PTPS13 PTPS12 PTPS11 PTPS10

FF19H

PTPS23 PTPS22 PTPS21 PTPS20

FF1AH

PTPS33 PTPS32 PTPS31 PTPS30

FF1BH

PTPS43 PTPS42 PTPS41 PTPS40

FF1CH

PTPS53 PTPS52 PTPS51 PTPS50

FF1DH

PTPS63 PTPS62 PTPS61 PTPS60

FF1EH

PTPS73 PTPS72 PTPS71 PTPS70

FF1FH

(RFOUT/

FF20H

D3 D2 D1 D0 Name Init

PTPS03

PTPS02

R/W

PTPS01

PTPS00

PTPS13

PTPS12

R/W

PTPS11

PTPS10

PTPS23

PTPS22

R/W

PTPS21

PTPS20

PTPS33

PTPS32

R/W

PTPS31

PTPS30

PTPS43

PTPS42

R/W

PTPS41

PTPS40

PTPS53

PTPS52

R/W

PTPS51

PTPS50

PTPS63

PTPS62

R/W

PTPS61

PTPS60

PTPS73

PTPS72

R/W

PTPS71

PTPS70

P03

P02

P01

(REF0)

P00

(RFIN0)

P02

(SEN0)

BZ)

P01

R/W

P00

∗1

1 0

High

Programmable timer 0 count clock frequency selection

[PTPS03–00] Frequency [PTPS03–00] Frequency [PTPS03–00] Frequency

Off1f

OSC1/2

OSC3/16

OSC1/256

fOSC1/643fOSC1/324fOSC1/165fOSC1/4

OSC1

OSC3/256

OSC3/8

Programmable timer 1 count clock frequency selection

[PTPS13–10] Frequency [PTPS13–10] Frequency [PTPS13–10] Frequency

Off1f

OSC1/2

OSC3/16

OSC1/256

fOSC1/643fOSC1/324fOSC1/165fOSC1/4

OSC1

OSC3/256

OSC3/8

Programmable timer 2 count clock frequency selection

[PTPS23–20] Frequency [PTPS23–20] Frequency [PTPS23–20] Frequency

Off1f

OSC1/2

OSC3/16

OSC1/256

fOSC1/643fOSC1/324fOSC1/165fOSC1/4

OSC1

OSC3/256

OSC3/8

Programmable timer 3 count clock frequency selection

[PTPS33–30] Frequency [PTPS33–30] Frequency [PTPS33–30] Frequency

Off1f

OSC1/2

OSC3/16

OSC1/256

fOSC1/643fOSC1/324fOSC1/165fOSC1/4

OSC1

OSC3/256

OSC3/8

Programmable timer 4 count clock frequency selection

[PTPS43–40] Frequency [PTPS43–40] Frequency [PTPS43–40] Frequency

Off1f

OSC1/2

OSC3/16

OSC1/256

fOSC1/643fOSC1/324fOSC1/165fOSC1/4

OSC1

OSC3/256

OSC3/8

Programmable timer 5 count clock frequency selection

[PTPS53–50] Frequency [PTPS53–50] Frequency [PTPS53–50] Frequency

Off1f

OSC1/2

OSC3/16

OSC1/256

fOSC1/643fOSC1/324fOSC1/165fOSC1/4

OSC1

OSC3/256

OSC3/8

Programmable timer 6 count clock frequency selection

[PTPS63–60] Frequency [PTPS63–60] Frequency [PTPS63–60] Frequency

Off1f

OSC1/2

OSC3/16

OSC1/256

fOSC1/643fOSC1/324fOSC1/165fOSC1/4

OSC1

OSC3/256

OSC3/8

Programmable timer 7 count clock frequency selection

fOSC1/643fOSC1/324fOSC1/165fOSC1/4

OSC1

OSC3/256

OSC3/8

P03 I/O port data

Low

[PTPS73–70] Frequency [PTPS73–70] Frequency [PTPS73–70] Frequency

Off1f

OSC1/2

OSC3/16

OSC1/256

functions as a general-purpose register when R/f or BZ is used

High

Low

P02 I/O port data

functions as a general-purpose register when R/f is used

High

Low

P01 I/O port data

functions as a general-purpose register when R/f is used

High

Low

P00 I/O port data

functions as a general-purpose register when R/f is used

OSC3/4

OSC3/64

OSC3/2

OSC3/64

OSC3/2

OSC3/64

OSC3/2

OSC3/64

OSC3/2

OSC3/64

OSC3/2

OSC3/64

OSC3/2

OSC3/64

OSC3/2

OSC3/64

OSC3/2

OSC3/32

OSC3

OSC3/32

OSC3

OSC3/32

OSC3

OSC3/32

OSC3

OSC3/32

OSC3

OSC3/32

OSC3

OSC3/32

OSC3

OSC3/32

OSC3

3240-0412

Page 26

SIC63616-(Rev. 1.0) NO. P19

Table 4.1.1 (c) I/O memory map (FF21H-FF28H)

Address Comment

IOC03 IOC02 IOC01 IOC00

FF21H

PUL03 PUL02 PUL01 PUL00

FF22H

SMT03 SMT02 SMT01 SMT00

FF23H

(TOUT_A)

FF24H

IOC13 IOC12 IOC11 IOC10

FF25H

PUL13 PUL12 PUL11 PUL10

FF26H

SMT13 SMT12 SMT11 SMT10

FF27H

SRDY/

FOUT)

FF28H

D3 D2

P13

P12 P11 P10

P23 (SS/

P22

(SIN)

D1 D0 Name Init

R/W

P21

(SOUT)

R/W

P20

(SCLK)

IOC03

IOC02

IOC01

IOC00

PUL03

PUL02

PUL01

PUL00

SMT03 SMT02 SMT01 SMT00

P13

P12 P11 P10

IOC13

IOC12 IOC11 IOC10 PUL13

PUL12 PUL11 PUL10

SMT13

SMT12 SMT11 SMT10

P23

P22 P21

P20

∗1

1 0

Output

High

Output

Schmitt

High

P03 I/O control register

Input

functions as a general-purpose register when R/f or BZ is used

Input

P02 I/O control register

functions as a general-purpose register when R/f is used

Input

P01 I/O control register

functions as a general-purpose register when R/f is used

Input

P00 I/O control register

functions as a general-purpose register when R/f is used

P03 pull-down control register

Off

functions as a general-purpose register when R/f or BZ is used

Off

P02 pull-down control register

functions as a general-purpose register when R/f is used

Off

P01 pull-down control register

functions as a general-purpose register when R/f is used

Off

P00 pull-down control register

functions as a general-purpose register when R/f is used

General-purpose register

P13 I/O port data

Low

functions as a general-purpose register when TOUT_A is used

P12 I/O port data

Low

P11 I/O port data

Low

P10 I/O port data

Low

P13 I/O control register

Input

functions as a general-purpose register when TOUT_A is used

P12 I/O control register

Input

P11 I/O control register

Input

P10 I/O control register

Input

P13 pull-down control register

Off

functions as a general-purpose register when TOUT_A is used

P12 pull-down control register

Off

P11 pull-down control register

Off

P10 pull-down control register

Off

P13 input interface level select register

CMOS

functions as a general-purpose register when TOUT_A is used

P12 input interface level select register

CMOS

P11 input interface level select register

CMOS

P10 input interface level select register

CMOS

P23 I/O port data

Low

functions as a general-purpose register when SIF (slave, SRDY)

or FOUT is used

P22 I/O port data

Low

P21 I/O port data

Low

functions as a general-purpose register when SIF is used

P20 I/O port data

Low

functions as a general-purpose register when SIF (master) is used

3240-0412

Page 27

SIC63616-(Rev. 1.0) NO. P20

Table 4.1.1 (d) I/O memory map (FF29H-FF2BH)

Address Comment

IOC23 IOC22 IOC21 IOC20

FF29H

PUL23 PUL22 PUL21 PUL20

FF2AH

SMT23 SMT22 SMT21 SMT20

FF2BH

D3 D2 D1 D0 Name Init

IOC23

IOC22

IOC21

R/W

IOC20

PUL23

PUL22

PUL21

PUL20

SMT23

SMT22

SMT21

SMT20

∗1

1 0

Output

Schmitt

P23 I/O control register

Input

functions as a general-purpose register when SIF or FOUT is used

Input

P22 I/O control register

functions as a general-purpose register when SIF is used

Input

P21 I/O control register

functions as a general-purpose register when SIF is used

Input

P20 I/O control register

functions as a general-purpose register when SIF is used

Off

P23 pull-down control register

SS pull-down control register

functions as a general-purpose register when SIF (slave, SRDY)

or FOUT is used

Off

P22 pull-down control register

SIN pull-down control register

Off

P21 pull-down control register

functions as a general-purpose register when SIF (SOUT) is used

Off

P20 pull-down control register

SCLK (I) pull-down control register when SIF (slave) is used

functions as a general-purpose register when SIF (master) is used

CMOS

P23 input interface level select register

SS input I/F level select register

functions as a general-purpose register when SIF (slave, SRDY)

or FOUT is used

CMOS

P22 input interface level select register

SIN input interface level select register

CMOS

P21 input interface level select register

functions as a general-purpose register when SIF (SOUT) is used

CMOS

P20 input interface level select register

SCLK (I)

functions as a general-purpose register when SIF (master) is used

input I/F level select

when SIF (slave, SS) is

when SIF is

when SIF (slave, SS) is

used

when SIF is

used

3240-0412

Page 28

SIC63616-(Rev. 1.0) NO. P21

Table 4.1.1 (e) I/O memory map (FF30H-FF41H)

Address Comment

FF30H

IOC43 IOC42 IOC41 IOC40

FF31H

PUL43 PUL42 PUL41 PUL40

FF32H

SMT43 SMT42 SMT41 SMT40

FF33H

SIP03 SIP02 SIP01 SIP00

FF3CH

PCP03 PCP02 PCP01 PCP00

FF3DH

SIP13 SIP12 SIP11 SIP10

FF3EH

PCP13 PCP12 PCP11 PCP10

FF3FH

FF40H

TM3 TM2 TM1 TM0

FF41H

D3 D2 D1 D0 Name Init

P43 P42 P41 P40

R/W

P43 P42 P41

P40 IOC43 IOC42

R/W

IOC41 IOC40 PUL43 PUL42

R/W

PUL41 PUL40

SMT43 SMT42

R/W

SMT41 SMT40

SIP03 SIP02

R/W

SIP01

SIP00 PCP03 PCP02

R/W

PCP01 PCP00

SIP13

SIP12

R/W

SIP11

SIP10 PCP13 PCP12

R/W

0 0 TMRST TMRUN

W R/WR

PCP11 PCP10 0 0

TMRST

TMRUN

∗

–

∗

–

∗

Reset0Reset

TM3 TM2

TM1 TM0

∗1

1 0

High High High

High Output Output Output Output

On On On On

Enable Enable Enable Enable

Low Low

P40–P43 I/O port data

Low

Low Input Input

P40–P43 I/O control register

Input Input

Off Off

P40–P43 pull-down control register

Off

Off CMOS CMOS

P40–P43 input interface level select register

CMOS CMOS

Disable Disable

P10–P13 interrupt select register

Disable Disable

1 1 1 0 0 0 0 1 1 1 1 1

Schmitt

Schmitt 0 0 0 0 1 1 1

P10–P13 interrupt polarity select register

1 0

Enable Enable Enable Enable

Disable Disable

P40–P43 interrupt select register

Disable Disable

0 0 0 1 1 1

P40–P43 interrupt polarity select register

∗

Run 0 0 0 0

Unused

Invalid

Clock timer reset (writing)

Stop

Clock timer Run/Stop

Clock timer data (16 Hz)

Clock timer data (32 Hz)

Clock timer data (64 Hz)

Clock timer data (128 Hz)

3240-0412

Page 29

SIC63616-(Rev. 1.0) NO. P22

Table 4.1.1 (f) I/O memory map (FF42H-FF51H)

Address Comment

TM7 TM6 TM5 TM4

FF42H

ENRTM ENRST ENON BZE

FF44H

FF45H

FF46H

FF47H

FF48H

FF49H

LCURF CRNWF SWRUN SWRST

FF4AH

SWD3 SWD2 SWD1 SWD0

FF4BH

SWD7 SWD6 SWD5 SWD4

FF4CH

SWD11 SWD10 SWD9 SWD8

FF4DH

General LPAGE DSPC1 DSPC0

FF50H

General LDUTY2 LDUTY1 LDUTY0

FF51H

D3 D2 D1 D0 Name Init

TM7 TM6

TM5 TM4

ENRTM

∗

ENRST

Reset

R/W W R/W

0 BZSTP BZSHT SHTPW

ENON

BZE

BZSTP

∗

–

∗

BZSHT

R W R/W

0 BZFQ2 BZFQ1 BZFQ0

R R/W

0 BDTY2 BDTY1 BDTY0

R R/W

0 0 SWDIR EDIR

SHTPW

0 BZFQ2 BZFQ1 BZFQ0 0 BDTY2 BDTY1 BDTY0 0 0

∗

–

∗

–

∗

–

∗

–

SWDIR

R R/W

0 DKM2 DKM1 DKM0

R R/W

EDIR

DKM2 DKM1 DKM0

∗

–

LCURF

CRNWF

R/W WR

SWRUN SWRST

∗

Reset SWD3 SWD2

SWD1 SWD0 SWD7 SWD6

SWD5 SWD4

SWD11 SWD10

SWD9 SWD8

General

LPAGE

R/W

DSPC1 DSPC0

General

LDUTY2

R/W

LDUTY1

LDUTY0

∗1

1 0 0 0 0 0 0

1 sec

0.5 sec

Reset

Enable

Stop

Trigger

Busy

125 msec

Invalid

Off

Disable

Invalid Invalid Ready

31.25 msec

0 0

∗

0 0

∗

0 0 0

∗

0 0 0

∗

0 Enable Disable

∗

0 0 0 0

Request

Renewal

Run

Reset

No No

Stop

Invalid 0 0 0 0 0 0 0 0 0 0 0 0 0

F200-F36F0F000-F16F

0 0 0

1 0

Clock timer data (1 Hz)

Clock timer data (2 Hz)

Clock timer data (4 Hz)

Clock timer data (8 Hz)

Envelope releasing time selection

Envelope reset (writing)

Envelope On/Off

Buzzer output enable

Unused

1-shot buzzer stop (writing)

1-shot buzzer trigger (writing)

1-shot buzzer status (reading)

1-shot buzzer pulse width setting

Unused

Buzzer

frequency

selection

[BZFQ2–0] Frequency (Hz)

4096.013276.822730.732340.6 4

2048.051638.461365.371170.3

Unused

Buzzer signal duty ratio selection

(refer to main manual)

Unused

Stopwatch direct input switch

0: P10=Run/Stop, P11=Lap 1: P10=Lap, P11=Run/Stop

Direct input enable

Unused

Key mask

selection

[DKM2–0] Key mask

None1P122P12–133P12–13,40

P405P40–416P40–427P40–43

Lap data carry-up request flag

Capture renewal flag

Stopwatch timer Run/Stop

Stopwatch timer reset (writing)

Stopwatch timer data

BCD (1/1000 sec)

Stopwatch timer data

BCD (1/100 sec)

Stopwatch timer data

BCD (1/10 sec)

General-purpose register

Display memory area (when 1/16 duty is selected)

functions as a general-purpose register when 1/24 or 1/32 is selected

LCD display

mode selection

[DSPC1, 0] Display mode

Normal1Reverse

General-purpose register

LCD

drive duty

selection

[LDUTY2–0] Duty

1/32 (32 Hz)

1/24 (21 Hz)

All lit3All off

Prohibited

1/16 (32 Hz)

1/24 (42 Hz)

5–7

Prohibited

3240-0412

Page 30

SIC63616-(Rev. 1.0) NO. P23

Table 4.1.1 (g) I/O memory map (FF52H-FF67H)

Address Comment

FF52H

FF58H

SCPS1 SCPS0 SDP SMOD

FF59H

FF5AH

FF5BH

FF5CH

RFCNT RFOUT ERF1 ERF0

FF60H

OVTC OVMC

FF61H

MC3 MC2 MC1 MC0

FF62H

MC7 MC6 MC5 MC4

FF63H

MC11 MC10 MC9 MC8

FF64H

MC15 MC14 MC13 MC12

FF65H

MC19 MC18 MC17 MC16

FF66H

FF67H

D3 D2 D1 D0 Name Init

LC3 LC2 LC1 LC0

R/W

0 ESOUT SCTRG ESIF

LC3 LC2 LC1

LC0 0 ESOUT

∗

–

SCTRG

R R/W

ESIF SCPS1 SCPS0

0 0

R/W

ESREADY

ENCS

SDP

SMOD 0 0

∗

–

∗

–

ESREADY

R R/W

SD3 SD2 SD1 SD0

R/W

SD7 SD6 SD5 SD4

R/W

ENCS

SD3 SD2 SD1 SD0 SD7 SD6 SD5 SD4

– – – – – – –

– RFCNT RFOUT

R/W

RFRUNR RFRUNS

R/W

TC3 TC2 TC1 TC0

R/W

ERF1 ERF0

OVTC

OVMC RFRUNR RFRUNS

MC3 MC2 MC1 MC0 MC7 MC6 MC5

MC4 MC11 MC10

MC9

MC8 MC15 MC14 MC13 MC12 MC19 MC18 MC17 MC16

TC3

TC2

TC1

TC0

– – – – – – – – – – – – – – – – – – – – – – – –

∗1

1 0 0 0 0 0

∗

Enable

Trigger

Run

SIF 0 0

MSB first

Master

∗

00SRDY

SIFSSI/O

∗

High

∗

High

∗

High

∗

High

∗

High

∗

High

∗

High

∗

High

Continue

Enable 0 0 0

Overflow

Run

∗

LCD contrast adjustment

[LC3–0] Contrast

Light––15Dark

Unused

SOUT enable

Disable

Serial I/F clock trigger (writing)

Invalid

Serial I/F clock status (reading)

Stop

Serial I/F enable (P2 port function selection)

I/O

Serial I/F clock

format selection

LSB first

Serial I/F data input/output permutation

Slave

Serial I/F mode selection

[SCPS1, 0] Polarity phase

Unused

P23 port

function selection

Serial I/F enable

(P23 function selection)

MSB

Low Low

Serial I/F transmit/receive data (low-order 4 bits)

Low

LSB

Low

MSB

Low Low

Serial I/F transmit/receive data (high-order 4 bits)

Low

LSB

Low

Continuous oscillation enable

Normal

RFOUT enable

Disable

R/f conversion selection

Time base counter overflow flag

Non-ov

Measurement counter overflow flag

Non-ov

Reference oscillation Run control/status

Stop

Sensor oscillation Run control/status

Stop

ESREADY

[ERF1, 0] R/f conversion

x 0 1

I/O1Ch.0 DC2Ch.1 AC3Ch.1 DC

Measurement counter MC0–MC3

LSB

Measurement counter MC4–MC7

Measurement counter MC8–MC11

Measurement counter MC12–MC15

MSB

Measurement counter MC16–MC19

Time base counter TC0–TC3

ENCS

0P1P2N3

Slave

(SMOD=0)

P23

I/O

SRDY

Master

(SMOD=1)

P23 I/O I/O

Prohibited

3240-0412

Page 31

SIC63616-(Rev. 1.0) NO. P24

Table 4.1.1 (h) I/O memory map (FF68H-FF82H)

Address Comment

FF68H

TC11 TC10 TC9 TC8

FF69H

TC15 TC14 TC13 TC12

FF6AH

TC19 TC18 TC17 TC16

FF6BH

FF70H

FF71H

DRL3 DRL2 DRL1 DRL0

FF72H

DRL7 DRL6 DRL5 DRL4

FF73H

DRH3 DRH2 DRH1 DRH0

FF74H

DRH7 DRH6 DRH5 DRH4

FF75H

FF76H

MOD16_A EVCNT_A

FF80H

PTSEL1 PTSEL0

FF81H

PTRST1 PTRUN1 PTRST0 PTRUN0

FF82H

D3 D2 D1 D0 Name Init

TC7

TC7 TC6 TC5 TC4

R/W

SR3 SR2 SR1 SR0

R/W

SR7 SR6 SR5 SR4

R/W

NF VF ZF CALMD

TC6 TC5

TC4 TC11 TC10

TC9

TC8 TC15 TC14 TC13 TC12 TC19 TC18 TC17 TC16

SR3

SR2

SR1

SR0

SR7

SR6

SR5

SR4 DRL3 DRL2 DRL1 DRL0 DRL7 DRL6 DRL5 DRL4

DRH3 DRH2 DRH1 DRH0 DRH7 DRH6 DRH5 DRH4

NF VF

– – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –

R R/W

FCSEL_A PLPUL_A

R/W

CHSEL_A PTOUT_A

R/W

CALMD

MOD16_A EVCNT_A FCSEL_A PLPUL_A

PTSEL1

PTSEL0 CHSEL_A PTOUT_A

PTRST1

∗

–

PTRUN1

∗

PTRST0

W R/W W R/W

–

PTRUN0

0 0 0 0

0 0 0 0 0 0 0 0

∗1

∗

1 0

Negative Overflow

Zero Run

Div.

16 bits Event ct. With NR

PWM PWM

Timer 1

Reset

Run

Reset

Run

Time base counter TC4–TC7

Time base counter TC8–TC11

Time base counter TC12–TC15

MSB

Time base counter TC16–TC19

Source register (low-order 4 bits)

LSB

MSB

Source register (high-order 4 bits)

Low-order 8-bit destination register

(low-order 4 bits)

LSB

MSB

Low-order 8-bit destination register

(high-order 4 bits)

High-order 8-bit destination register

(low-order 4 bits)

LSB

MSB

High-order 8-bit destination register

(high-order 4 bits)

Positive

Negative flag

Overflow flag

Zero flag

Stop

Operation status (reading)

Mult.

Calculation mode selection (writing)

8 bits

PTM0–1 16-bit mode selection

Timer

PTM0 counter mode selection

No NR

PTM0 function selection (for event counter mode)

PTM0 pulse polarity selection (for event counter mode)

Normal

Programmable timer 1 PWM output selection

Normal

Programmable timer 0 PWM output selection

Timer 0

PTM0–1 TOUT_A output selection

Off

PTM0–1 TOUT_A output control

Invalid

Programmable timer 1 reset (reload)

Stop

Programmable timer 1 Run/Stop

Invalid

Programmable timer 0 reset (reload)

Stop

Programmable timer 0 Run/Stop

3240-0412

Page 32

SIC63616-(Rev. 1.0) NO. P25

Table 4.1.1 (i) I/O memory map (FF84H-FF91H)

Address Comment

RLD03 RLD02 RLD01 RLD00

FF84H

RLD07 RLD06 RLD05 RLD04

FF85H

RLD13 RLD12 RLD11 RLD10

FF86H

RLD17 RLD16 RLD15 RLD14

FF87H

PTD03 PTD02 PTD01 PTD00

FF88H

PTD07 PTD06 PTD05 PTD04

FF89H

PTD13 PTD12 PTD11 PTD10

FF8AH

PTD17 PTD16 PTD15 PTD14

FF8BH

CD03 CD02 CD01 CD00

FF8CH

CD07 CD06 CD05 CD04

FF8DH

CD13 CD12 CD11 CD10

FF8EH

CD17 CD16 CD15 CD14

FF8FH

MOD16_B EVCNT_B

FF90H

PTSEL3 PTSEL2

FF91H

D3 D2 D1 D0 Name Init

RLD03 RLD02

R/W

FCSEL_B PLPUL_B

R/W

CHSEL_BPTOUT_B

R/W

RLD01 RLD00 RLD07 RLD06 RLD05 RLD04 RLD13 RLD12 RLD11 RLD10 RLD17 RLD16 RLD15 RLD14 PTD03 PTD02 PTD01 PTD00 PTD07 PTD06 PTD05 PTD04 PTD13 PTD12 PTD11 PTD10 PTD17 PTD16 PTD15 PTD14

CD03 CD02 CD01 CD00 CD07 CD06 CD05 CD04 CD13 CD12 CD11 CD10 CD17 CD16 CD15

CD14 MOD16_B EVCNT_B FCSEL_B PLPUL_B

PTSEL3

PTSEL2 CHSEL_B PTOUT_B

∗1

1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

16 bits

Event ct.

With NR 0 0

PWM

MSB

Programmable timer 0 reload data (low-order 4 bits)

LSB

MSB

Programmable timer 0 reload data (high-order 4 bits)

LSB

MSB

Programmable timer 1 reload data (low-order 4 bits)

LSB

MSB

Programmable timer 1 reload data (high-order 4 bits)

LSB

MSB

Programmable timer 0 data (low-order 4 bits)

LSB

MSB

Programmable timer 0 data (high-order 4 bits)

LSB

MSB

Programmable timer 1 data (low-order 4 bits)

LSB

MSB

Programmable timer 1 data (high-order 4 bits)

LSB

MSB

Programmable timer 0 compare data (low-order 4 bits)

LSB

MSB

Programmable timer 0 compare data (high-order 4 bits)

LSB

MSB

Programmable timer 1 compare data (low-order 4 bits)

LSB

MSB

Programmable timer 1 compare data (high-order 4 bits)

LSB

8 bits

PTM2–3 16-bit mode selection

Timer

PTM2 counter mode selection

No NR

PTM2 function selection (for event counter mode)

PTM2 pulse polarity selection (for event counter mode)

Normal

Programmable timer 3 PWM output selection

Normal

Programmable timer 2 PWM output selection

General-purpose register

3240-0412

Page 33

SIC63616-(Rev. 1.0) NO. P26

Table 4.1.1 (j) I/O memory map (FF92H-FFA0H)

Address Comment

PTRST3 PTRUN3 PTRST2 PTRUN2

FF92H

RLD23 RLD22 RLD21 RLD20

FF94H

RLD27 RLD26 RLD25 RLD24

FF95H

RLD33 RLD32 RLD31 RLD30

FF96H

RLD37 RLD36 RLD35 RLD34

FF97H

PTD23 PTD22 PTD21 PTD20

FF98H

PTD27 PTD26 PTD25 PTD24

FF99H

PTD33 PTD32 PTD31 PTD30

FF9AH

PTD37 PTD36 PTD35 PTD34

FF9BH

CD23 CD22 CD21 CD20

FF9CH

CD27 CD26 CD25 CD24

FF9DH

CD33 CD32 CD31 CD30

FF9EH

CD37 CD36 CD35 CD34

FF9FH

MOD16_C EVCNT_C

FFA0H

D3 D2 D1 D0 Name Init

∗

–

PTRST3

PTRUN3

∗

PTRST2

W R/W W R/W

–

PTRUN2

RLD23 RLD22

R/W

RLD21 RLD20 RLD27 RLD26

R/W

RLD25 RLD24 RLD33 RLD32

R/W

RLD31 RLD30 RLD37 RLD36

R/W

RLD35 RLD34 PTD23 PTD22

PTD21 PTD20 PTD27 PTD26

PTD25 PTD24 PTD33 PTD32

PTD31 PTD30 PTD37 PTD36

PTD35 PTD34

CD23 CD22

R/W

CD21 CD20 CD27 CD26

R/W

CD25 CD24 CD33 CD32

R/W

CD31 CD30 CD37 CD36

R/W

FCSEL_C PLPUL_C

R/W

CD35

CD34 MOD16_C EVCNT_C

FCSEL_C

PLPUL_C

∗1

1 0

∗

Reset

Invalid

Run

∗

Reset

Run 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

16 bits

Event ct.

With NR

Programmable timer 3 reset (reload)

Stop

Programmable timer 3 Run/Stop

Invalid

Programmable timer 2 reset (reload)

Stop

Programmable timer 2 Run/Stop

MSB

Programmable timer 2 reload data (low-order 4 bits)

LSB

MSB

Programmable timer 2 reload data (high-order 4 bits)

LSB

MSB

Programmable timer 3 reload data (low-order 4 bits)

LSB

MSB

Programmable timer 3 reload data (high-order 4 bits)

LSB

MSB

Programmable timer 2 data (low-order 4 bits)

LSB

MSB

Programmable timer 2 data (high-order 4 bits)

LSB

MSB

Programmable timer 3 data (low-order 4 bits)

LSB

MSB

Programmable timer 3 data (high-order 4 bits)

LSB

MSB

Programmable timer 2 compare data (low-order 4 bits)

LSB

MSB

Programmable timer 2 compare data (high-order 4 bits)

LSB

MSB

Programmable timer 3 compare data (low-order 4 bits)

LSB

MSB

Programmable timer 3 compare data (high-order 4 bits)

LSB

8 bits

PTM4–5 16-bit mode selection

Timer

PTM4 counter mode selection

No NR

PTM4 function selection (for event counter mode)

PTM4 pulse polarity selection (for event counter mode)

3240-0412

Page 34

SIC63616-(Rev. 1.0) NO. P27

Table 4.1.1 (k) I/O memory map (FFA1H-FFAFH)

Address Comment

PTSEL5 PTSEL4

FFA1H

PTRST5 PTRUN5 PTRST4 PTRUN4

FFA2H

RLD43 RLD42 RLD41 RLD40

FFA4H

RLD47 RLD46 RLD45 RLD44

FFA5H

RLD53 RLD52 RLD51 RLD50

FFA6H

RLD57 RLD56 RLD55 RLD54

FFA7H

PTD43 PTD42 PTD41 PTD40

FFA8H

PTD47 PTD46 PTD45 PTD44

FFA9H

PTD53 PTD52 PTD51 PTD50

FFAAH

PTD57 PTD56 PTD55 PTD54

FFABH

CD43 CD42 CD41 CD40

FFACH

CD47 CD46 CD45 CD44

FFADH

CD53 CD52 CD51 CD50

FFAEH

CD57 CD56 CD55 CD54

FFAFH

D3 D2 D1 D0 Name Init

CHSEL_C PTOUT_C

R/W

PTSEL5

PTSEL4 CHSEL_C PTOUT_C PTRST5

∗

–

PTRUN5

∗

PTRST4

W R/W W R/W

–

PTRUN4

RLD43 RLD42

R/W

RLD41 RLD40 RLD47 RLD46

R/W

RLD45 RLD44 RLD53 RLD52

R/W

RLD51 RLD50 RLD57 RLD56

R/W

RLD55 RLD54 PTD43 PTD42

PTD41 PTD40 PTD47 PTD46

PTD45 PTD44 PTD53 PTD52

PTD51 PTD50 PTD57 PTD56

PTD55 PTD54

CD43 CD42

R/W

CD41 CD40 CD47 CD46

R/W

CD45 CD44 CD53 CD52

R/W

CD51 CD50 CD57 CD56

R/W

CD55 CD54

∗1

1 0

PWM

Normal

PWM

∗

Reset

Run

∗

Reset

Run 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Programmable timer 5 PWM output selection

Normal

Programmable timer 4 PWM output selection

General-purpose register

Invalid

Programmable timer 5 reset (reload)

Stop

Programmable timer 5 Run/Stop

Invalid

Programmable timer 4 reset (reload)

Stop

Programmable timer 4 Run/Stop

MSB

Programmable timer 4 reload data (low-order 4 bits)

LSB

MSB

Programmable timer 4 reload data (high-order 4 bits)

LSB

MSB

Programmable timer 5 reload data (low-order 4 bits)

LSB

MSB

Programmable timer 5 reload data (high-order 4 bits)

LSB

MSB

Programmable timer 4 data (low-order 4 bits)

LSB

MSB

Programmable timer 4 data (high-order 4 bits)

LSB

MSB

Programmable timer 5 data (low-order 4 bits)

LSB

MSB

Programmable timer 5 data (high-order 4 bits)

LSB

MSB

Programmable timer 4 compare data (low-order 4 bits)

LSB

MSB

Programmable timer 4 compare data (high-order 4 bits)

LSB

MSB

Programmable timer 5 compare data (low-order 4 bits)

LSB

MSB

Programmable timer 5 compare data (high-order 4 bits)

LSB

3240-0412

Page 35

SIC63616-(Rev. 1.0) NO. P28

Table 4.1.1 (l) I/O memory map (FFB0H-FFBEH)

Address Comment

MOD16_D EVCNT_D

FFB0H

PTSEL7 PTSEL6

FFB1H

PTRST7 PTRUN7 PTRST6 PTRUN6

FFB2H

RLD63 RLD62 RLD61 RLD60

FFB4H

RLD67 RLD66 RLD65 RLD64

FFB5H

RLD73 RLD72 RLD71 RLD70

FFB6H

RLD77 RLD76 RLD75 RLD74

FFB7H

PTD63 PTD62 PTD61 PTD60

FFB8H

PTD67 PTD66 PTD65 PTD64

FFB9H

PTD73 PTD72 PTD71 PTD70

FFBAH

PTD77 PTD76 PTD75 PTD74

FFBBH

CD63 CD62 CD61 CD60

FFBCH

CD67 CD66 CD65 CD64

FFBDH

CD73 CD72 CD71 CD70

FFBEH

D3 D2 D1 D0 Name Init

PTOUT_D

MOD16_D EVCNT_D

FCSEL_D

PLPUL_D

PTSEL7 PTSEL6

CHSEL_D PTOUT_D PTRST7

∗

–

FCSEL_D PLPUL_D

R/W

CHSEL_D

R/W

PTRUN7

∗

PTRST6

W R/W W R/W

–

PTRUN6

RLD63 RLD62

R/W

RLD61 RLD60 RLD67 RLD66

R/W

RLD65 RLD64 RLD73 RLD72

R/W

RLD71 RLD70 RLD77 RLD76

R/W

RLD75 RLD74 PTD63 PTD62

PTD61 PTD60 PTD67 PTD66

PTD65 PTD64 PTD73 PTD72

PTD71 PTD70 PTD77 PTD76

PTD75 PTD74

CD63 CD62

R/W

CD61 CD60 CD67 CD66

R/W

CD65 CD64 CD73 CD72

R/W

CD71 CD70

∗1

1 0

16 bits

8 bits

Event ct.

With NR 0 0

PWM

∗

Reset

Run

∗

Reset

Run 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PTM6–7 16-bit mode selection

Timer

PTM6 counter mode selection

No NR

PTM6 function selection (for event counter mode)

PTM6 pulse polarity selection (for event counter mode)

Normal

Programmable timer 7 PWM output selection

Normal

Programmable timer 6 PWM output selection

General-purpose register

Invalid

Programmable timer 7 reset (reload)

Stop

Programmable timer 7 Run/Stop

Invalid

Programmable timer 6 reset (reload)

Stop

Programmable timer 6 Run/Stop

MSB

Programmable timer 6 reload data (low-order 4 bits)

LSB

MSB

Programmable timer 6 reload data (high-order 4 bits)

LSB

MSB

Programmable timer 7 reload data (low-order 4 bits)

LSB

MSB

Programmable timer 7 reload data (high-order 4 bits)

LSB

MSB

Programmable timer 6 data (low-order 4 bits)

LSB

MSB

Programmable timer 6 data (high-order 4 bits)

LSB

MSB

Programmable timer 7 data (low-order 4 bits)

LSB

MSB

Programmable timer 7 data (high-order 4 bits)

LSB

MSB

Programmable timer 6 compare data (low-order 4 bits)

LSB

MSB

Programmable timer 6 compare data (high-order 4 bits)

LSB

MSB

Programmable timer 7 compare data (low-order 4 bits)

LSB

3240-0412

Page 36

SIC63616-(Rev. 1.0) NO. P29

Table 4.1.1 (m) I/O memory map (FFBFH-FFEDH)

Address Comment

CD77 CD76 CD75 CD74

FFBFH

General EIRFE EIRFR EIRFS

FFE1H

General General EIPT0 EICTC0

FFE2H

General General EIPT1 EICTC1

FFE3H

General General EIPT2 EICTC2

FFE4H

General General EIPT3 EICTC3

FFE5H

General General EIPT4 EICTC4

FFE6H

General General EIPT5 EICTC5

FFE7H

General General EIPT6 EICTC6

FFE8H

General General EIPT7 EICTC7

FFE9H

General General General EISIF

FFEAH

EIK03 EIK02 EIK01 EIK00

FFEBH

EIK13 EIK12 EIK11 EIK10

FFECH

EIRUN EILAP EISW1 EISW10

FFEDH

D3 D2 D1 D0 Name Init

R/W

CD77 CD76 CD75 CD74

General

EIRFE EIRFR

EIRFS General General

EIPT0 EICTC0 General General

EIPT1 EICTC1 General General

EIPT2 EICTC2 General General

EIPT3 EICTC3 General General

EIPT4 EICTC4 General General

EIPT5 EICTC5 General General

EIPT6 EICTC6 General General

EIPT7 EICTC7 General General General

EISIF EIK03 EIK02 EIK01 EIK00 EIK13 EIK12 EIK11 EIK10

EIRUN

EILAP

EISW1

EISW10

∗1

1 0 0 0 0 0 0

1 0

Enable

1 0

Enable

1 0

Enable

1 0

Enable

1 0

Enable

1 0

Enable

1 0

Enable

1 0

Enable

1 0

Enable

1 0

Enable

MSB

Programmable timer 7 compare data (high-order 4 bits)

LSB

General-purpose register

Interrupt mask register (

Mask

Interrupt mask register (R/f converter reference oscillate completion)

Mask

Interrupt mask register (R/f converter sensor oscillate completion)

Mask

General-purpose register

Interrupt mask register (Programmable timer 0 underflow)

Mask

Interrupt mask register (Programmable timer 0 compare match)

Mask

General-purpose register

Interrupt mask register (Programmable timer 1 underflow)

Mask

Interrupt mask register (Programmable timer 1 compare match)

Mask

General-purpose register

Mask

Interrupt mask register (Programmable timer 2 underflow)

Mask

Interrupt mask register (Programmable timer 2 compare match)

General-purpose register

Mask

Interrupt mask register (Programmable timer 3 underflow)

Mask

Interrupt mask register (Programmable timer 3 compare match)

General-purpose register

Mask

Interrupt mask register (Programmable timer 4 underflow)

Mask

Interrupt mask register (Programmable timer 4 compare match)

General-purpose register

Mask

Interrupt mask register (Programmable timer 5 underflow)

Mask

Interrupt mask register (Programmable timer 5 compare match)

General-purpose register

Mask

Interrupt mask register (Programmable timer 6 underflow)

Mask

Interrupt mask register (Programmable timer 6 compare match)

General-purpose register

Mask

Interrupt mask register (Programmable timer 7 underflow)

Mask

Interrupt mask register (Programmable timer 7 compare match)

General-purpose register

Mask

Interrupt mask register (Serial interface)

Mask

Interrupt mask register (Key input interrupt 3 <P13>)

Mask

Interrupt mask register (Key input interrupt 2 <P12>)

Mask

Interrupt mask register (Key input interrupt 1 <P11>)

Mask

Interrupt mask register (Key input interrupt 0 <P10>)

Mask

Interrupt mask register (Key input interrupt 7 <P43>)

Mask

Interrupt mask register (Key input interrupt 6 <P42>)

Mask

Interrupt mask register (Key input interrupt 5 <P41>)

Mask

Interrupt mask register (Key input interrupt 4 <P40>)

Mask

Interrupt mask register (Stopwatch direct RUN)

Mask

Interrupt mask register (Stopwatch direct LAP)

Mask

Interrupt mask register (Stopwatch timer 1 Hz)

Mask

Interrupt mask register (Stopwatch timer 10 Hz)

R/f converter

error)

3240-0412

Page 37

SIC63616-(Rev. 1.0) NO. P30

Table 4.1.1 (n) I/O memory map (FFEEH-FFFCH)

Address Comment

EIT3 EIT2 EIT1 EIT0

FFEEH

EIT7 EIT6 EIT5 EIT4

FFEFH

FFF1H

FFF2H

FFF3H

FFF4H

FFF5H

FFF6H

FFF7H

FFF8H

FFF9H

FFFAH

IK03 IK02 IK01 IK00

FFFBH

IK13 IK12 IK11 IK10

FFFCH

D3 D2 D1 D0 Name Init

EIT3 EIT2

R/W

EIT1 EIT0 EIT7 EIT6

R/W

EIT5 EIT4

∗3

IRFE IRFR IRFS

∗3

IPT0

ICTC0

∗3

IPT1

ICTC1

∗3

IPT2

ICTC2

∗3

IPT3

ICTC3

∗3

IPT4

ICTC4

∗3

IPT5

ICTC5

∗3

IPT6

ICTC6

∗3

IPT7

ICTC7

∗3

ISIF

–

– –

– – –

R/W

0 IRFE IRFR IRFS

R/W

0 0 IPT0 ICTC0

R/W

0 0 IPT1 ICTC1

R/W

0 0 IPT2 ICTC2

R/W

0 0 IPT3 ICTC3

R/W

0 0 IPT4 ICTC4

R/W

0 0 IPT5 ICTC5

R/W

0 0 IPT6 ICTC6

R/W

0 0 IPT7 ICTC7

R/W

0 0 0 ISIF

IK03

IK02

R/W

IK01

IK00

IK13

IK12

R/W

IK11

IK10

∗1

1 0

Enable

∗

(R)

Yes

(W)

Reset

∗

(R)

∗

Yes

(W)

Reset

∗

(R)

∗

Yes

(W)

Reset

∗

(R)

∗

Yes

(W)

Reset

∗

(R)

∗

Yes

(W)

Reset

∗

(R)

∗

Yes

(W)

Reset

∗

(R)

∗

Yes

(W)

Reset

∗

(R)

∗

Yes

(W)

Reset

∗

(R)

∗

Yes

(W)

Reset

∗

(R)

∗

Yes

∗

(W)

Reset

(R)

Yes

(W)

Reset

(R)

Yes

(W)

Reset

Interrupt mask register (Clock timer 16 Hz)

Mask

Interrupt mask register (Clock timer 32 Hz)

Mask

Interrupt mask register (Clock timer 64 Hz)

Mask

Interrupt mask register (Clock timer 128 Hz)

Mask

Interrupt mask register (Clock timer 1 Hz)

Mask

Interrupt mask register (Clock timer 2 Hz)

Mask

Interrupt mask register (Clock timer 4 Hz)

Mask

Interrupt mask register (Clock timer 8 Hz)

Mask

(R)

Unused

Interrupt factor flag (R/f converter error)

Interrupt factor flag (R/f converter reference oscillate completion)

(W)

Interrupt factor flag (R/f converter sensor oscillate completion)

Invalid

Unused

(R)

Unused

Interrupt factor flag (Programmable timer 0 underflow)

(W)

Interrupt factor flag (Programmable timer 0 compare match)

Invalid

(R)

Unused

(W)

Interrupt factor flag (Programmable timer 1 underflow)

Invalid

Interrupt factor flag (Programmable timer 1 compare match)

(R)

Unused

(W)

Interrupt factor flag (Programmable timer 2 underflow)

Invalid

Interrupt factor flag (Programmable timer 2 compare match)

(R)

Unused

(W)

Interrupt factor flag (Programmable timer 3 underflow)

Invalid

Interrupt factor flag (Programmable timer 3 compare match)

(R)

Unused

(W)

Interrupt factor flag (Programmable timer 4 underflow)

Invalid

Interrupt factor flag (Programmable timer 4 compare match)

(R)

Unused

(W)

Interrupt factor flag (Programmable timer 5 underflow)

Invalid

Interrupt factor flag (Programmable timer 5 compare match)

(R)

Unused

(W)

Interrupt factor flag (Programmable timer 6 underflow)

Invalid

Interrupt factor flag (Programmable timer 6 compare match)

(R)

Unused

(W)

Interrupt factor flag (Programmable timer 7 underflow)

Invalid

Interrupt factor flag (Programmable timer 7 compare match)

(R)

Unused

(W)

Unused

Invalid

Interrupt factor flag (Serial interface)

(R)

Interrupt factor flag (Key input interrupt 3 <P13>)

Interrupt factor flag (Key input interrupt 2 <P12>)

(W)

Interrupt factor flag (Key input interrupt 1 <P11>)

Invalid

Interrupt factor flag (Key input interrupt 0 <P10>)

(R)

Interrupt factor flag (Key input interrupt 7 <P43>)

Interrupt factor flag (Key input interrupt 6 <P42>)

(W)

Interrupt factor flag (Key input interrupt 5 <P41>)

Invalid

Interrupt factor flag (Key input interrupt 4 <P40>)

3240-0412

Page 38

SIC63616-(Rev. 1.0) NO. P31

Table 4.1.1 (o) I/O memory map (FFFDH-FFFFH)

Address Comment

IRUN ILAP ISW1 ISW10

FFFDH

FFFEH

FFFFH

D3 D2 D1 D0 Name Init

IRUN

ILAP

R/W

IT3 IT2 IT1 IT0

R/W

IT7 IT6 IT5 IT4

R/W

ISW1

ISW10

IT3 IT2 IT1 IT0 IT7 IT6 IT5 IT4

∗1

1 0

(R)

Yes

(W)

Reset

(R)

Yes

(W)

Reset

(R)

Yes

(W)

Reset

Interrupt factor flag (Stopwatch direct RUN)

(R)

Interrupt factor flag (Stopwatch direct LAP)

Interrupt factor flag (Stopwatch timer 1 Hz)

(W)

Interrupt factor flag (Stopwatch timer 10 Hz)

Invalid

Interrupt factor flag (Clock timer 16 Hz)

(R)

Interrupt factor flag (Clock timer 32 Hz)

Interrupt factor flag (Clock timer 64 Hz)

(W)

Interrupt factor flag (Clock timer 128 Hz)

Invalid

(R)

Interrupt factor flag (Clock timer 1 Hz)

Interrupt factor flag (Clock timer 2 Hz)

(W)

Interrupt factor flag (Clock timer 4 Hz)

Invalid

Interrupt factor flag (Clock timer 8 Hz)

3240-0412

Page 39

SIC63616-(Rev. 1.0) NO. P32

4.2 Power Control

4.2.1 Conﬁguration of power supply circuit

The S1C63616 has built-in power supply circuits shown in Figure 4.2.1.1 so the voltages to drive the CPU, internal logic circuits, oscillation circuits and LCD driver can be generated on the chip.

External

power

supply

∗1

∗2

CG VD2 VD1

VOSC

VC1 VC2 VC3 VC4 VC5

Power supply voltage

booster/halver

VD2

∗3

VDD

VCSEL

Oscillation system

voltage regulator

VOSC

LCD system

voltage

regulator

C1–VC5

VDD

Internal voltage

LPWR

VCHLMOD

DBON

HLON

VDHLMOD

regulator

∗4

Internal circuits

VD1

OSC3

oscillation circuit

OSC1

oscillation circuit

LCD

driver

circuit

OSC3 OSC4

OSC1 OSC2

COM0–COM31 SEG0–SEG39

operates in boost mode. ∗4 HLON is prohibited from use.

Fig. 4.2.1.1 Built-in power supply circuit

Power supply voltage booster/halver

The power supply voltage booster/halver generates the operating voltage VD2 for the voltage regulator (LCD system voltage regulator). The S1C63616 allows software to control the power supply voltage booster/halver and to select the power source of the voltage regulator.

Internal voltage regulator

This voltage regulator always operates to generate the VD1 operating voltage for the internal logic circuits and OSC3 oscillation circuit.

Oscillation system voltage regulator

This voltage regulator always operates to generate the V circuit.

OSC

voltage for driving the OSC1 oscillation

LCD system voltage regulator

Note: BesurenottousetheVD1,VD2,V

circuits.

OSC

andVC1toVC5 terminal output voltages to drive external

3240-0412

Page 40

SIC63616-(Rev. 1.0) NO. P33

4.2.2 Controlling the power supply voltage booster/halver and voltage regulators

Controlling the power supply voltage booster/halver

The power supply voltage booster/halver generates the operating voltage VD2 for driving the voltage regulator (LCD system voltage regulator) when the supply voltage VDD is out of their operating voltage range. The power supply voltage booster/halver has two operating modes, boost mode and halving mode, that can be selected using the DBON and HLON registers according to the VDD value being supplied. The power supply voltage booster/halver enters boost mode by setting DBON to "1" and boosts the supply voltage VDD to generate VD2 (about double VDD). The power supply voltage booster/halver should be placed in boost mode only when VD2 is required for driving the LCD system voltage regulator (see "Controlling the LCD system voltage regulator" described below). HLON is prohibited from use. Always be sure to set to "0". Setting both DBON and HLON to "0" turns the power supply voltage booster/halver off. The VD2 voltage is not required when the supply voltage VDD is within the range from 2.5 V to 5.5 V (1.6 V to 5.5 V when the VC1 reference LCD drive power option is selected). In this case the power supply voltage booster/halver should be turned off to reduce current consumption. At initial reset, DBON and HLON are both set to "0" and the power supply voltage booster/halver does not activate.

Controlling the LCD system voltage regulator

When the VC2 reference LCD drive power option is selected, the LCD system voltage regulator must be driven with a 2.5 V or more power voltage. Therefore, they can be driven with VDD if the supply voltage VDD is 2.5 V or more. When the supply voltage VDD less than 2.5 V is used, drive the power supply voltage booster/halver in boost mode to generate VD2 and use it to drive the LCD system voltage regulator. Use VCSEL to select the power source voltage (VDD or VD2) for the LCD system voltage regulator. It is driven with VDD by setting VCSEL to "0" or VD2 by setting VCSEL to "1". At initial reset, VCSEL is set to "0" so that VDD is selected as the power source for the LCD system voltage regulator.

To generate the LCD drive voltages by the LCD system voltage regulator (to start LCD display), turn the LCD system voltage regulator on using the LPWR register. When "1" is written to LPWR, the LCD system voltage regulator goes on and generates the LCD drive voltages. At initial reset, LPWR is set to "0" (Off). When LCD display is not necessary, turn the LCD system voltage regulator off to reduce power consumption.

Notes:• WhendrivingtheLCDsystemvoltageregulatorwithVD2,besuretowrite"1"toDBONtoplace

thepowersupplyvoltagebooster/halverinboostmodebeforesettingVCSELto"1".Furthermore, donotswitchthepowersourcetoVD2forabout1msecuntiltheVD2 voltage has stabilized after

the power supply voltage booster/halver is turned on.

 • DonotsetDBONto"1"(boostmode)andVCSELto"1"(drivingwithVD2) if the supply voltage

VDDexceeds2.5V,asitmaycausedamageoftheIC.

 • IfVDDlessthan2.5VisusedasthepowersourcefortheLCDsystemvoltageregulator,theVC1

toVC5voltagescannotbegeneratedwithinspecications(whenaVC2 reference voltage option is

selected).

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Table 4.2.2.1 lists settings of the above registers according to the supply voltage VDD.

Table 4.2.2.1 Power control register settings according to supply voltage VDD

When VC2 reference LCD drive power option is selected

Power supply

voltage VDD

1.6 to 2.5 V

2.5 to 5.5 V

When VC1 reference LCD drive power option is selected

Power supply

voltage VDD

1.6 to 5.5 V

DBON

DBON0HLON0VDSEL0VCSEL

HLON

VDSEL

1 0

0 0

VCSEL

0 0

1 0

Power source for internal and

oscillation system voltage regulators

VDD VDD

Power source for internal and

oscillation system voltage regulators

VDD

Power source for LCD system

voltage regulator (VC2 reference)

VD2 (≈ VDD × 2)

VDD

Power source for LCD system

voltage regulator (VC1 reference)

VDD

4.2.3 Heavy load protection function

In order to ensure a stable circuit behavior and LCD display quality even if the power supply voltage ﬂuctuates due to driving an external load, the internal operating voltage regulator and the LCD system voltage regulator have a heavy load protection function. The internal operating voltage regulator enters heavy load protection mode by writing "1" to the VDHLMOD register and it ensures stable VD1 output. Use the heavy load protection function when a heavy load such as a lamp or buzzer is driven with a port output.

The LCD system voltage regulator enters heavy load protection mode by writing "1" to the VCHLMOD register and it ensures stable VC1–VC5 outputs. Use the heavy load protection function when the LCD display has inconsistencies in density.

Note: Current consumption increases in heavy load protection mode, therefore do not set heavy load

protection mode with software if unnecessary.

4.2.4 I/O memory for power control

Table 4.2.4.1 shows the I/O address and the control bits for power control.

Table 4.2.4.1 Power control bits

Address Comment

VDSEL VCSEL HLON DBON

FF02H

VCHLMOD VDHLMOD

FF03H

*1 Initial value at initial reset *3 Constantly "0" when being read

*2 Not set in the circuit

DBON: Power supply voltage booster/halver boost mode On/Off register (FF02H•D0)

Activates the power supply voltage booster/halver in boost mode.

When "1" is written: Booster On When "0" is written: Booster Off

When "1" is written to DBON, the power supply voltage booster/halver activates in boost mode and almost doubles the VDD voltage to generate the VD2 voltage. Turn the power supply voltage booster/halver on when driving the LCD system voltage regulator with VD2 (VC2 reference voltage, VDD = 1.6 to 2.5 V). When "0" is written to DBON, the voltage boost operation is deactivated. Be sure to set DBON to "0" (Off) when driving the LCD system voltage regulator with VDD. Furthermore, do not set both DBON and HLON to "1". At initial reset, this register is set to "0".

D3 D2

Reading: Valid

D1 D0 Name Init

VDSEL VCSEL

R/W

General LPWR

R/W

HLON

DBON VCHLMOD VDHLMOD

General

LPWR

∗1

1 0

General-purpose register

0 0 0 0 0 0 0 0

Power source select for LCD system voltage regulator

Off On On On

Power voltage booster/halver halving mode On/Off

Off

Power voltage booster/halver boost mode On/Off

Heavy load protection mode On/Off for LCD system voltage regulator

Off

Heavy load protection mode On/Off for internal voltage regulator

Off

General-purpose register

LCD system voltage regulator On/Off

Off

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HLON: Power supply voltage booster/halver halving mode On/Off register (FF02H•D1)

Activates the power supply voltage booster/halver in halving mode.

When "1" is written: Halver On When "0" is written: Halver Off

Reading: Valid

HLON is prohibited from use. Always be sure to set to "0". At initial reset, this register is set to "0".

VCSEL: LCD system voltage regulator power source switch register (FF02H•D2)

Selects the power voltage for the LCD system voltage regulator.

When "1" is written: V When "0" is written: V

Reading: Valid

When "1" is written to VCSEL, the LCD system voltage regulator is driven with VD2 generated by the power supply voltage booster/halver. Before this setting is made, it is necessary to write "1" to DBON to activate the power supply voltage booster (boost mode). Furthermore, do not switch the power voltage to VD2 for at least 1 msec after the power supply voltage booster/halver is turned on to allow VD2 to stabilize. When "0" is written to VCSEL, the LCD system voltage regulator is driven with VDD. At initial reset, this register is set to "0".

Note: DonotsetDBONto"1"(boostmode)andVCSELto"1"(drivingwithVD2)ifthesupplyvoltageVDD

exceeds2.5V,asitmaycausedamageoftheIC.

LPWR: LCD system voltage regulator On/Off register (FF03H•D0)

Turns the LCD system voltage regulator on and off.

When "1" is written: On When "0" is written: Off

Reading: Valid

When "1" is written to LPWR, the LCD system voltage regulator goes on and generates the LCD drive voltages. When "0" is written, all the LCD drive voltages go to VSS level. It takes about 100 msec for the LCD drive voltages to stabilize after starting up the LCD system voltage regulator by writing "1" to LPWR. At initial reset, this register is set to "0".

VDHLMOD: Internal operating voltage regulator heavy load protection On/Off register (FF03H•D2)

Enables heavy load protection function for the internal operating voltage regulator.

When "1" is written: On When "0" is written: Off

Reading: Valid

By writing "1" to VDHLMOD, the internal operating voltage regulator enters heavy load protection mode and it ensures stable VD1 output. The heavy load protection function is effective when the buzzer/FOUT signal is being output. However, heavy load protection mode increases current consumption compared with normal operation mode. Therefore, do not set heavy load protection mode unless it is necessary. At initial reset, this register is set to "0".

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VCHLMOD: LCD system voltage regulator heavy load protection On/Off register (FF03H•D3)

Enables heavy load protection function for the LCD system voltage regulator.

When "1" is written: On When "0" is written: Off

Reading: Valid

By writing "1" to VCHLMOD, the LCD system voltage regulator enters heavy load protection mode to minimize degradation in display quality when ﬂuctuations in the supply voltage occurs due to driving a heavy load. The heavy load protection function is effective when the OSC3 clock is used or the buzzer/ FOUT signal is being output. However, heavy load protection mode increases current consumption compared with normal operation mode. Therefore, do not set heavy load protection mode unless it is necessary. At initial reset, this register is set to "0".

4.2.5 Programming notes

(1) When the power supply voltage booster/halver is turned on, the VD2 output voltage requires about

1 msec to stabilize. Do not switch the power source for the voltage regulator (LCD system voltage regulator) to VD2 until the stabilization time has elapsed.

(2) HLON is prohibited from use, as it may cause malfunctions. Always be sure to set to "0".

(3) Do not set DBON to "1" (boost mode) and VCSEL to "1" (driving with VD2) if the supply voltage VDD

exceeds 2.5 V, as it may cause damage of the IC.

(4) Current consumption increases in heavy load protection mode, therefore do not set heavy load pro-

tection mode with software if unnecessary.

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4.3 Watchdog Timer

4.3.1 Conﬁguration of watchdog timer

The S1C63616 has a built-in watchdog timer that operates with a 256 Hz divided clock from the OSC1 as the source clock. The watchdog timer starts operating after initial reset, however, it can be stopped by the software. The watchdog timer must be reset cyclically by the software while it operates. If the watchdog timer is not reset in at least 3–4 seconds, it generates a non-maskable interrupt (NMI) to the CPU. Figure 4.3.1.1 is the block diagram of the watchdog timer.

OSC1 dividing signal 256 Hz

Watchdog timer enable signal

Watchdog timer reset signal

Watchdog timer

Non-maskable interrupt (NMI)

Fig. 4.3.1.1 Watchdog timer block diagram

The watchdog timer contains a 10-bit binary counter, and generates the non-maskable interrupt when the last stage of the counter (0.25 Hz) overﬂows. Watchdog timer reset processing in the program's main routine enables detection of program overrun, such as when the main routine's watchdog timer processing is bypassed. Ordinarily this routine is incorporated where periodic processing takes place, just as for the timer interrupt routine. The watchdog timer operates in the HALT mode. If a HALT status continues for 3–4 seconds, the nonmaskable interrupt releases the HALT status.

4.3.2 Interrupt function

If the watchdog timer is not reset periodically, the non-maskable interrupt (NMI) is generated to the core CPU. Since this interrupt cannot be masked, it is accepted even in the interrupt disable status (I ﬂag = "0"). However, it is not accepted when the CPU is in the interrupt mask state until SP1 and SP2 are set as a pair, such as after initial reset or during re-setting the stack pointer. The interrupt vector of NMI is assigned to 0100H in the program memory.

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4.3.3 I/O memory of watchdog timer

Table 4.3.3.1 shows the I/O address and control bits for the watchdog timer.

Table 4.3.3.1 Control bits of watchdog timer

Address Comment

FF01H

*1 Initial value at initial reset

*2 Not set in the circuit

*3 Constantly "0" when being read

WDRST: Watchdog timer reset (FF01H•D0)

Resets the watchdog timer.

When "1" is written: Watchdog timer is reset When "0" is written: No operation

When "1" is written to WDRST, the watchdog timer is reset and restarts immediately after that. When "0" is written, no operation results. This bit is dedicated for writing, and is always "0" for reading.

WDEN: Watchdog timer enable register (FF01H•D1)

Selects whether the watchdog timer is used (enabled) or not (disabled).

D3 D2

0 0 WDEN WDRST

D1 D0 Name Init

R/W WR

Reading: Always "0"

0 0

WDEN

WDRST

∗1

∗

–

∗

–

∗

Reset

1 0

∗

Enable

Reset

Unused

Disable

Watchdog timer enable

Invalid

Watchdog timer reset (writing)

When "1" is written: Enabled When "0" is written: Disabled

Reading: Valid

When "1" is written to the WDEN register, the watchdog timer starts count operation. When "0" is written, the watchdog timer does not count and does not generate the interrupt (NMI). At initial reset, this register is set to "1".

4.3.4 Programming notes

(1) When the watchdog timer is being used, the software must reset it within 3-second cycles.

(2) Because the watchdog timer is set in operation state by initial reset, set the watchdog timer to dis-

abled state (not used) before generating an interrupt (NMI) if it is not used.

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4.4 Oscillation Circuit

4.4.1 Conﬁguration of oscillation circuit

The S1C63616 is conﬁgured as a twin clock system with two internal oscillation circuits (OSC1 and OSC3). The OSC1 oscillation circuit generates the main-clock (Typ. 32.768 kHz) for low-power operation and the

OSC3 oscillation circuit generates the sub-clock (Max. 4.2 MHz) to run the CPU and some peripheral circuits in high speed. Figure 4.4.1.1 shows the conﬁguration of the oscillation circuit.

oscillation circuit

SLEEP

status

OSC1

OSC3

Oscillation circuit control signal

OSCC

(fOSC1)

OSC3)

Prescaler

Clock

switch

CPU clock selection signal

CLKCHG

To peripheral circuits

To CPU

To some peripheral circuits

Fig. 4.4.1.1 Oscillation system block diagram

At initial reset, OSC1 oscillation circuit is selected as the CPU operating clock source. The S1C63616 allows the software to turn the OSC3 oscillation circuit on and off, and to switch the system clock between OSC3 and OSC1. The OSC3 oscillation circuit is used when the CPU and some peripheral circuits need high speed

operation. Otherwise, use the OSC1 oscillation circuit to generate the operating clock and stop the OSC3 oscillation circuit to reduce current consumption.

Note: The S1C63616 supports the SLEEP function and both the OSC1 and OSC3 oscillation circuits

stop oscillating when the CPU enters SLEEP mode. To prevent the CPU from a malfunction when it resumes operating from SLEEP mode, switch the CPU clock to OSC1 before placing the CPU into SLEEP mode.

4.4.2 Mask option

The OSC1 oscillator type is ﬁxed at crystal. For the OSC3 oscillator type, either ceramic or CR (external R) can be selected.

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4.4.3 OSC1 oscillation circuit

The OSC1 oscillation circuit generates the 32.768 kHz (Typ.) system clock which is used during low speed (low power) operation of the CPU and peripheral circuits. Furthermore, even when OSC3 is used as the system clock, OSC1 continues to generate the source clock for the clock timer and stopwatch timer. This oscillation circuit stops when the SLP instruction is executed. Figure 4.4.3.1 shows the conﬁguration of the OSC1 oscillation circuit.

SLEEP status

OSC1

CG1

X'tal

OSC2

VSS

fOSC1

VSS

Fig. 4.4.3.1 OSC1 oscillation circuit (crystal oscillation)

A crystal oscillation circuit can be conﬁgured simply by connecting a crystal oscillator X'tal (Typ. 32.768 kHz) between the OSC1 and OSC2 terminals along with a trimmer capacitor CG1 (0–25 pF) between the OSC1 terminal and VSS.

4.4.4 OSC3 oscillation circuit

The OSC3 oscillation circuit generates the system clock to run the CPU and some peripheral circuits at high speed. This oscillation circuit stops when the SLP instruction is executed or the OSCC register is set to "0". The oscillator type can be selected from ceramic or CR by mask option. Figure 4.4.4.1 shows the conﬁguration of the OSC3 oscillation circuit.

CG3

OSC3

Ceramic

VSS

OSC4

(1) Ceramic oscillation circuit

fOSC3

Oscillation circuit control signal

SLEEP status

OSC3

fOSC3

Oscillation circuit

OSC4

control signal SLEEP status

(2) CR oscillation circuit

Fig. 4.4.4.1 OSC3 oscillation circuit

When ceramic oscillation circuit (Max. 4.2 MHz) is selected, connect a ceramic oscillator (Ceramic) between the OSC3 and OSC4 terminals and connecting two capacitors (CG3, CD3) between the OSC3 terminal and VSS, and between the OSC4 terminal and VSS, respectively.

When CR oscillation (Max. 2 MHz) is selected, connect a resistor (RCR) between the OSC3 and OSC4 terminals.

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4.4.5 Switching the CPU clock

Either the OSC1 clock or the OSC3 clock can be selected as the CPU system clock using the CLKCHG register. The OSC3 oscillation circuit can be turned off (OSCC = "0") to save power while the CPU is operating with the OSC1 clock (CLKCHG = "0"). If the system needs high speed operation, turn the OSC3 oscillation circuit on (OSCC = "1") and switch over the system clock to OSC3 (CLKCHG = "0" → "1"). In this case, since 1 msec to several tens of msec are necessary for the oscillation to stabilize after turning the OSC3 oscillation circuit on, you should switch over the clock after the stabilization time has elapsed. For the oscillation start time, refer to Chapter 8, "Electrical Characteristics". After the clock is switched from OSC3 to OSC1, the OSC3 oscillation circuit can be turned off immediately. When switching the clock from OSC3 to OSC1 (CLKCHG = "1" → "0"), be sure to switch OSC3 oscillation off with separate instructions. Using a single instruction to process simultaneously can cause a malfunction of the CPU.

Figure 4.4.5.1 indicates the status transition diagram for the clock changeover.

Program Execution Status

RESET

High speed operation

OSC1 OSC3 CPU clock

ON ON OSC3

CLKCHG=0

CLKCHG=1

Low speed operation

OSC1 OSC3 CPU clock

ON ON OSC1

OSCC=0

OSCC=1

Low speed and

low power operation OSC1 OSC3 CPU clock

ON OFF OSC1

* *

HALT status OSC1 OSC3 CPU clock

HALT instruction SLP instructionInterrupt Interrupt

(Key input interrupt)

ON or OFF

STOP

SLEEP status OSC1 OSC3 CPU clock

OFF OFF STOP

Standby Status

* The return destination from the standby status becomes the program execution status prior to shifting to the standby status.

Fig. 4.4.5.1 Status transition diagram for the clock changeover

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4.4.6 I/O memory of oscillation circuit

Table 4.4.6.1 shows the I/O address and the control bits for the oscillation circuit.

Note: The control bits for the oscillation circuit described below are effective only when the OSC3 oscil-

lation circuit is used. If the system uses the OSC1 oscillation circuit only, do not change the default settings.

Table 4.4.6.1 Control bits of oscillation circuit

Address Comment

CLKCHG

FF00H

*1 Initial value at initial reset

*2 Not set in the circuit

*3 Constantly "0" when being read

OSCC: OSC3 oscillation control register (FF00H•D2)

Turns the OSC3 oscillation circuit on and off.

When "1" is written: OSC3 oscillation On When "0" is written: OSC3 oscillation Off

When it is necessary to operate the CPU at high speed, set OSCC to "1". At other times, set it to "0" to reduce current consumption. At initial reset, this register is set to "0".

D3 D2

OSCC 0 0

R/W R

Reading: Valid

D1 D0 Name Init

CLKCHG

OSCC

∗

–

∗1

0 0

∗

1 0

OSC3OnOSC1

Off

CPU clock switch

OSC3 oscillation On/Off

Unused

CLKCHG: CPU system clock switching register (FF00H•D3)

The CPU's operation clock is selected with this register.

When "1" is written: OSC3 clock is selected When "0" is written: OSC1 clock is selected

Reading: Valid

When the CPU clock is to be OSC3, set CLKCHG to "1"; for OSC1, set CLKCHG to "0". At initial reset, this register is set to "0".

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4.4.7 Programming notes

(1) When the high speed CPU operation is not necessary, you should operate the peripheral circuits accord-

ing to the setting outline indicate below.

 •CPUoperatingclock: OSC1  •OSC3oscillationcircuit:Off

(When the OSC3 clock is not necessary for some peripheral circuits.)

(2) Since 1 msec to several tens of msec are necessary for the oscillation to stabilize after turning the OSC3

oscillation circuit on. Consequently, you should switch the CPU operating clock (OSC1 → OSC3) after allowing for a sufﬁcient waiting time once the OSC3 oscillation goes on. (The oscillation start time will vary somewhat depending on the oscillator and on the externally attached parts. Refer to the oscillation start time example indicated in Chapter 7, "Electrical Characteristics".)

(3) When switching the clock from OSC3 to OSC1, be sure to switch OSC3 oscillation off with separate

instructions. Using a single instruction to process simultaneously can cause a malfunction of the CPU.

(4) The S1C63616 supports the SLEEP function and both the OSC1 and OSC3 oscillation circuits stop oscil-

lating when the CPU enters SLEEP mode. To prevent the CPU from a malfunction when it resumes operating from SLEEP mode, switch the CPU clock to OSC1 before placing the CPU into SLEEP mode.

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4.5 I/O Ports

(P00-P03, P10-P13, P20-P23 and P40-P43)

4.5.1 Conﬁguration of I/O ports

The S1C63616 is equipped with 16 bits of I/O ports (P00–P03, P10–P13, P20–P23 and P40–P43) in which the input/output direction can be switched with software. Figure 4.5.1.1 shows the structure of an I/O port.

Pull-down control

Data bus

I/O control

Data

Input

control

∗1: During output mode ∗2: During input mode

Fig. 4.5.1.1 Structure of I/O port

VDD

Pxx

Mask option

VSS

Note: If an output terminal (including a special output terminal) of this IC is used to drive an external com-

ponent that consumes a large amount of current such as a bipolar transistor, design the pattern of traces on the printed circuit board so that the operation of the external component does not affect

theICpowersupply.Referto<OutputTerminals>inSection5.3,"PrecautionsonMounting",for

more information.

Each I/O port terminal provides an internal pull-down resistor. The mask option allows selection of the pull-down resistor to be connected or disconnected in 1-bit units. When "Use" is selected by mask option, the port suits input from the push switch, key matrix, and so forth. When "Not use" is selected, the port can be used for slide switch input and interfacing with other LSIs.

The P10 and P11 I/O ports can also be used as the Run/Stop and Lap direct inputs for the stopwatch timer. The P12 and P41–P43 ports can also be used as the event counter inputs for the programmable timer.

The I/O port terminals P00–P03, P13, P20–P23 are shared with the R/f converter input/output terminals, serial interface input/output terminals and special output (BZ, FOUT, TOUT_A) terminals. The software can select the function to be used. At initial reset, these terminals are all set to the I/O port. Table 4.5.1.1 shows the setting of the input/output terminals by function selection.

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Table 4.5.1.1 Function setting of input/output terminals

Terminal

name

P00

P00 (Input & pulled down∗)

P01

P01 (Input & pulled down∗)

P02

P02 (Input & pulled down∗)

P03

P03 (Input & pulled down∗)

P10

P10 (Input & pulled down∗)

P11

P11 (Input & pulled down∗)

P12

P12 (Input & pulled down∗)

P13

P13 (Input & pulled down∗)

P20

P20 (Input & pulled down∗)

P21

P21 (Input & pulled down∗)

P22

P22 (Input & pulled down∗)

P23

P23 (Input & pulled down∗)

P40

P40 (Input & pulled down∗)

P41

P41 (Input & pulled down∗)

P42

P42 (Input & pulled down∗)

P43

P43 (Input & pulled down∗)

Terminal status

at initial reset

TOUT_A

When special outputs/peripheral functions are used (selected by software)

Special output

TOUT

FOUT

∗ When "With Pull-Down" is selected by mask option (high impedance when "Gate Direct" is selected)

BZBZMaster

SCLK(O)

SOUT(O)

SIN(I)

Serial I/F

SCLK(I)

SOUT(O)

SIN(I)

SRDY(O)/SS(I)

Slave

R/f converter

RFIN0

REF0

SEN0

RFOUT

Stopwatch

direct input

RUN/LAP

Event

counter

EVIN_A

EVIN_B

EVIN_C

EVIN_D

When these ports are used as I/O ports, the ports can be set to either input mode or output mode individually (in 1-bit units). The mode can be set by writing data to the I/O control registers.

When the special output or peripheral function is used, the input/output direction of the port is automatically conﬁgured by switching the terminal function. For controlling the serial interface, R/f converter, BZ output, stopwatch timer, and event counter, refer to "4.10 Serial Interface", "4.13 R/f Converter", "4.11 Sound Generator", "4.8 Stopwatch Timer", and "4.9 Programmable Timer".

Note: Beforetheportfunctioniscongured,thecircuitthatusestheport(e.g.inputinterrupt,multiplekey

entry reset, serial interface, event counter input, direct RUN/LAP input for stopwatch) must be disabled.

4.5.2 Mask option

The output speciﬁcation of each I/O port during output mode can be selected from either complementary output or P-channel open drain output by mask option. This selection can be done in 1-bit units. When P-channel open drain output is selected, do not apply a voltage exceeding the power supply voltage to the port.

The mask option also allows selection of whether the pull-down resistor is used or not during input mode. This selection can be done in 1-bit units. When "Not use" is selected, take care that the ﬂoating status does not occur during input mode.

The pull-down resistor for input mode and output speciﬁcation (complementary output or P-channel open drain output) selected by mask option are effective even when I/O ports are used for input/output of the serial interface and R/f converter.

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4.5.3 I/O control registers and input/output mode

The I/O ports can be placed into input or output mode by writing data to the corresponding I/O control registers IOCxx.

To set a port to input mode, write "0" to the I/O control register. When an I/O port is set to input mode, it becomes high impedance status and works as an input port. However, when the pull-down explained in Section 4.5.5 has been enabled by software, the input line is pulled down only during this input mode.

To set a port to output mode, write "1" to the I/O control register. When an I/O port is set to output mode, it works as an output port. The port outputs a high level (VDD) when the port output data is "1", and a low level (VSS) when the port output data is "0". The I/O ports allow software to read data even in output mode. In this case, the data register value is read out. At initial reset, the I/O control registers are set to "0", and the I/O ports enter input mode.

When the peripheral input/output or special output function is selected (see Table 4.5.1.1), the input/ output direction is controlled by the hardware. In this case, the I/O control register of the port can be used as a general purpose register that does not affect the I/O control.

4.5.4 Input interface level

The I/O ports (P1x, P2x, P4x) allow software to select an input interface level. When the input interface level select register SMTxx is set to "0", the corresponding port is conﬁgured with a CMOS level input interface. When SMTxx is set to "1", the port is conﬁgured with a CMOS Schmitt level input interface. (P0x is the ﬁxed setting for CMOS Schmitt level.) At initial reset, all the ports are conﬁgured with a CMOS Schmitt level interface.

The input interface level select register of the port that is set for a peripheral output , R/f converter input/ output or special output (see Table 4.5.1.1) can be used as a general-purpose register. The input interface level select register of the port that is set for a peripheral input (except for the R/f converter) functions the same as the I/O port.

4.5.5 Pull-down during input mode

A pull-down resistor that activates during the input mode can be built into the I/O ports of the S1C63616. The pull-down resistor becomes effective by writing "1" to the pull-down control register PULxx that corresponds to each port, and the input line is pulled down during input mode. When "0" is written to PULxx or in output mode, the port will not be pulled down. At initial reset, the pull-down control registers are set to "1".

The pull-down control registers of the ports in which the pull-down resistor is disconnected by mask option can be used as general purpose registers. Even if the pull-down resistor has been connected, the pull-down control register of the port that is set for a peripheral output, R/f converter input/output or output special output (see Table 4.5.1.1) can be used as a general purpose register that does not affect the pull-down control. The pull-down control register of the port that is set for a peripheral input (except for the R/f converter) functions the same as the I/O port.

3240-0412

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SIC63616-(Rev. 1.0) NO. P47

4.5.6 Special output

Besides general purpose DC input/output, the I/O ports P03, P13 and P23 can also be assigned special output functions in software as shown in Table 4.5.6.1.

Table 4.5.6.1 Special output ports

Port

P03

P13

P23

When a special output function is enabled using the special output control register, the corresponding I/O port is automatically conﬁgured for output. The data register, I/O control register, pull-down control register and input interface level select register of the special output port can be used as general-purpose registers that do not affect the output status.

TOUT output (P13)

In order for the S1C63616 to provide clock signals to external devices, the P13 terminal can be used to output the TOUT_A signal (clocks output by the programmable timer).

The TOUT_A signal is enabled to output by the PTOUT_A register. When PTOUT_A is set to "1", the TOUT_A signal is output from the corresponding port terminal (P13). The I/O control register (IOC13), pull-down control register (PUL13) and data register (P13) setting is ineffective while the TOUT_A signal is being output. When PTOUT_A is set to "0", the port is conﬁgured as a general-purpose DC input/output port.

The TOUT_A signal is generated from the underﬂow and compare-match signals of a programmable timer. Refer to Section 4.9, "Programmable Timer", for controlling the clock output and frequency. Since the TOUT_A signal is generated asynchronously from the PTOUT_A register, a hazard of a 1/2 cycle or less is generated when the signal is turned on or off by setting the register. Figure 4.5.6.1 shows the output waveform of the TOUT_A signal.

Special output

TOUT_A

FOUT

Special output control register

BZE, BZSHT

PTOUT_A

FOUT0–FOUT3

PTOUT_A

TOUT_A output (P13)

0 1

Fig. 4.5.6.1 Output waveform of TOUT_A signal

FOUT output (P23)

In order for the S1C63616 to provide a clock signal to an external device, the FOUT signal (f or a divided clock) can be output from the P23 port terminal.

The FOUT signal is enabled to output by the FOUT0–FOUT3 registers. When the output clock frequency is selected using FOUT0–FOUT3, the FOUT signal is output from the P23 port terminal. The I/O control register (IOC23), pull-down control register (PUL23) and data register (P23) settings are ineffective while the FOUT signal is being output. When FOUT0–FOUT3 are set to "0", the P23 port is conﬁgured as a general-purpose DC input/output port.

The frequency of the FOUT signal can be selected from among 15 settings as shown in Table 4.5.6.2.

OSC1

, f

OSC3

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Page 55

FOUT3

1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0

Table 4.5.6.2 FOUT frequency selection

FOUT2

FOUT1

1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0

FOUT0

1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0

1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0

FOUT frequency

fOSC3 fOSC3 / 2 fOSC3 / 4 fOSC3 / 8 fOSC3 / 16 fOSC3 / 32 fOSC3 / 64 fOSC3 / 256 fOSC1 (32 kHz) fOSC1 / 2 (16 kHz) fOSC1 / 4 (8 kHz) fOSC1 / 16 (2 kHz) fOSC1 / 32 (1 kHz) fOSC1 / 64 (512 Hz) fOSC1 / 256 (128 Hz) Off

SIC63616-(Rev. 1.0) NO. P48

OSC1

: OSC1 oscillation frequency. ( ) indicates the clock frequency when f

OSC3

: OSC3 oscillation frequency

When the FOUT frequency is set to "f

OSC3

/n", the OSC3 oscillation circuit must be turned on before

OSC1

= 32 kHz.

outputting the FOUT signal. A time interval of several tens of µsec to several tens of msec, from turning the OSC3 oscillation circuit on until the oscillation stabilizes, is necessary, due to the oscillation element that is used. Consequently, if an abnormality occurs as the result of an unstable FOUT signal being output externally, you should allow an adequate waiting time after turning the OSC3 oscillation on, before starting FOUT output. (The oscillation start time will vary somewhat depending on the oscillator and on the externally attached parts. Refer to the oscillation start time example indicated in Chapter 7, "Electrical Characteristics".) Since the FOUT signal is generated asynchronously from the FOUT0–FOUT3 registers, a hazard of a 1/2 cycle or less is generated when the signal is turned on or off by setting the registers. Figure 4.5.6.2 shows the output waveform of the FOUT signal.

FOUT0–3

FOUT output (P23)

0 0Other than 0

Fig. 4.5.6.2 Output waveform of FOUT signal

Note: The P23 terminal used for FOUT output is also shared with the SRDY output or SS input for the

serialinterface.WhentheP23portisconguredfortheserialinterface,theFOUT0–FOUT3registers

become ineffective.

BZ (P03)

The P03 terminal can output the BZ signal. The BZ signal is the buzzer signal generated by the sound generator. Use the BZE or BZSHT register for controlling (On/Off) the BZ signal output. Refer to Section 4.11, "Sound Generator", for details of the buzzer signal and controlling method.

Note: TheP03terminalusedforBZoutputisalsosharedwiththeRFOUToutputfortheR/fconverter.Do

notenabletheRFOUTandBZsignalstooutputsimultaneously.

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SIC63616-(Rev. 1.0) NO. P49

4.5.7 Key input interrupt function

Eight bits of the I/O ports (P10–P13, P40–P43) provide the interrupt function. The conditions for generating an interrupt can be set with software. Further, whether to mask the interrupt function can be selected with software. Figure 4.5.7.1 shows the conﬁguration of the key input interrupt circuit.

Data bus

P10

Interrupt polarity select

Interrupt select

Interrupt mask

P11

P12

P13

Noise reject select

P40

Interrupt polarity select

Interrupt select

Address

Noise

rejector

Noise

rejector

MUX

Interrupt factor

flag (IK00)

Address

Interrupt factor

flag (IK10)

Address

Sleep cancellation

Interrupt request

Sleep cancellation

Interrupt request

Interrupt mask

P41

P42

P43

Noise reject select

Address

Fig. 4.5.7.1 Key input interrupt circuit conﬁguration

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SIC63616-(Rev. 1.0) NO. P50

The interrupt select registers (SIP00–SIP03, SIP10–SIP13) and interrupt polarity select registers (PCP00– PCP03, PCP10–PCP13) are individually provided for the I/O ports P10–P13 and P40–P43.

The interrupt select registers (SIPxx) select the ports to be used for generating interrupts or canceling SLEEP mode. Writing "1" to an interrupt select register incorporates that port into the interrupt generation conditions. Changing the port where the interrupt select register has been set to "0" does not affect the generation of the interrupt.

The input interrupt timing can be selected using the interrupt polarity select registers (PCPxx) so that an interrupt will be generated at the rising edge or falling edge of the input.

By setting these two conditions, an interrupt request signal and a SLEEP cancellation signal are generated at the rising or falling edge (selected by PCPxx) of the signal input to the port (selected by SIPxx).

When an interrupt factor occurs, the interrupt factor ﬂag (IK00–IK03, IK10–IK13) is set to "1". At the same time, an interrupt request is generated to the CPU if the corresponding interrupt mask register (EIK00– EIK03, EIK10–EIK13) is set to "1". When the interrupt mask register (EIKxx) is set to "0", the interrupt request is masked and no interrupt is generated to the CPU. However, SLEEP mode can be cancelled regardless of the interrupt mask register setting.

The key input interrupt circuit has a noise rejector to avoid unnecessary interrupt generation due to noise or chattering. This noise rejector allows selection of a noise-reject frequency from among three types shown in Table 4.5.7.1. Use the NRSP01 and NRSP00 registers for P10–P13 ports or NRSP11 and NRSP10 registers for P40–P43 ports to select a noise-reject frequency. If a pulse shorter than the selected width is input to the port, an interrupt is not generated. When high speed response is required, turns the noise rejecter off (bypassed).

Table 4.5.7.1 Setting up noise rejector

NRSP01 NRSP11

1 1 0 0

NRSP00 NRSP10

1 0 1 0

Noise reject frequency

fOSC1 / 256 (128 Hz) fOSC1 / 64 (512 Hz) fOSC1 / 16 (2 kHz) OFF (bypassed)

Reject pulse width

7.8 msec

2.0 msec

0.5 msec –

Notes:• BesuretoturnthenoiserejectoroffbeforeexecutingtheSLPinstruction.

 • ReactivatingfromSLEEPstatuscanonlybedonebygenerationofakeyinputinterruptfactor.

Therefore when using the SLEEP function, it is necessary to set the interrupt select register (SIPxx

="1")oftheporttobeusedforreleasingSLEEPstatusbeforeexecutingtheSLPinstruction.

Furthermore, enable the key input interrupt using the corresponding interrupt mask register (EIKxx

="1")beforeexecutingtheSLPinstructiontorunkeyinputinterrupthandlerroutineafterSLEEP

status is released.

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4.5.8 I/O memory of I/O ports

Table 4.5.8.1 shows the I/O addresses and the control bits for the I/O ports.

Table 4.5.8.1(a) Control bits of I/O ports

Address Comment

FOUT3 FOUT2 FOUT1 FOUT0

FF10H

NRSP11 NRSP10 NRSP01 NRSP00

FF11H

(RFOUT/

FF20H

IOC03 IOC02 IOC01 IOC00

FF21H

PUL03 PUL02 PUL01 PUL00

FF22H

SMT03 SMT02 SMT01 SMT00

FF23H

(TOUT_A)

FF24H

IOC13 IOC12 IOC11 IOC10

FF25H

*1 Initial value at initial reset

*2 Not set in the circuit

*3 Constantly "0" when being read

D3 D2 D1 D0 Name Init ∗11 0

P03

P02

(SEN0)

R/W

P01

(REF0)

FOUT3

FOUT2

FOUT1

FOUT0

NRSP11 NRSP10 NRSP01 NRSP00

P00

(RFIN0)

P03

P02

0 0 0 0 1

High

BZ)

P01

High

P13

P12 P11 P10

R/W

P00

IOC03

IOC02

IOC01

IOC00

PUL03

PUL02

PUL01

PUL00

SMT03 SMT02 SMT01 SMT00

P13

P12 P11 P10

IOC13

IOC12 IOC11 IOC10

High

Output

High

Output

FOUT frequency selection

[FOUT3–0] Frequency [FOUT3–0] Frequency [FOUT3–0] Frequency

Key input interrupt noise reject frequency selection

[NRSP11, 10] (P40–P43) Frequency [NRSP01, 00] (P10–P13) Frequency

P03 I/O port data

Low

Off1f

OSC1/2

OSC3/16

OSC1/256

fOSC1/643fOSC1/324fOSC1/165fOSC1/4

OSC1

OSC3/8

Off

functions as a general-purpose register when R/f or BZ is used

P02 I/O port data

Low

functions as a general-purpose register when R/f is used

P01 I/O port data

Low

functions as a general-purpose register when R/f is used

P00 I/O port data

Low

functions as a general-purpose register when R/f is used

P03 I/O control register

Input

functions as a general-purpose register when R/f or BZ is used

P02 I/O control register

Input

functions as a general-purpose register when R/f is used

P01 I/O control register

Input

functions as a general-purpose register when R/f is used

P00 I/O control register

Input

functions as a general-purpose register when R/f is used

P03 pull-down control register

Off

functions as a general-purpose register when R/f or BZ is used

P02 pull-down control register

Off

functions as a general-purpose register when R/f is used

P01 pull-down control register

Off

functions as a general-purpose register when R/f is used

P00 pull-down control register

Off

functions as a general-purpose register when R/f is used

General-purpose register

P13 I/O port data

Low

functions as a general-purpose register when TOUT_A is used

P12 I/O port data

Low

P11 I/O port data

Low

P10 I/O port data

Low

P13 I/O control register

Input

functions as a general-purpose register when TOUT_A is used

P12 I/O control register

Input

P11 I/O control register

Input

P10 I/O control register

Input

SIC63616-(Rev. 1.0) NO. P51

OSC3/256

OSC3/4

OSC1/16

OSC3/64

OSC3/2

OSC1/64

OSC3/32

OSC3

OSC1/256

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SIC63616-(Rev. 1.0) NO. P52

Table 4.5.8.1(b) Control bits of I/O ports

Address Comment

PUL13 PUL12 PUL11 PUL10

FF26H

SMT13 SMT12 SMT11 SMT10

FF27H

SRDY/ FOUT)

FF28H

IOC23 IOC22 IOC21 IOC20

FF29H

PUL23 PUL22 PUL21 PUL20

FF2AH

SMT23 SMT22 SMT21 SMT20

FF2BH

*1 Initial value at initial reset

*2 Not set in the circuit

*3 Constantly "0" when being read

D3 D2 D1 D0 Name Init ∗11 0

R/W

P23 (SS/

P22

P21

(SIN)

(SOUT)

R/W

P20

(SCLK)

PUL13

PUL12 PUL11 PUL10

SMT13

SMT12 SMT11 SMT10

P23

P22 P21

P20

IOC23

IOC22

IOC21

IOC20

PUL23

PUL22

PUL21

PUL20

SMT23

SMT22

SMT21

SMT20

Schmitt

CMOS

Schmitt Schmitt Schmitt

High

High High

High

Output

Schmitt

CMOS CMOS CMOS

CMOS

1 1 1

1 1

P13 pull-down control register

Off

functions as a general-purpose register when TOUT_A is used

P12 pull-down control register

Off

P11 pull-down control register

Off

P10 pull-down control register

Off

P13 input interface level select register

functions as a general-purpose register when TOUT_A is used

P12 input interface level select register

P11 input interface level select register

P10 input interface level select register

P23 I/O port data

Low

functions as a general-purpose register when SIF (slave, SRDY)

or FOUT is used

P22 I/O port data

Low

P21 I/O port data

Low

functions as a general-purpose register when SIF is used

P20 I/O port data

Low

functions as a general-purpose register when SIF (master) is used

P23 I/O control register

Input

functions as a general-purpose register when SIF or FOUT is used

P22 I/O control register

Input

functions as a general-purpose register when SIF is used

P21 I/O control register

Input

functions as a general-purpose register when SIF is used

P20 I/O control register

Input

functions as a general-purpose register when SIF is used

P23 pull-down control register

Off

SS pull-down control register

functions as a general-purpose register when SIF (slave, SRDY)

or FOUT is used

P22 pull-down control register

Off

SIN pull-down control register

P21 pull-down control register

Off

functions as a general-purpose register when SIF (SOUT) is used

P20 pull-down control register

Off

SCLK (I) pull-down control register when SIF (slave) is used

functions as a general-purpose register when SIF (master) is used

P23 input interface level select register

SS input I/F level select register

functions as a general-purpose register when SIF (slave, SRDY)

or FOUT is used

P22 input interface level select register

SIN input interface level select register

P21 input interface level select register

functions as a general-purpose register when SIF (SOUT) is used

P20 input interface level select register

SCLK (I)

functions as a general-purpose register when SIF (master) is used

input I/F level select

when SIF (slave, SS) is

when SIF is

when SIF (slave, SS) is

used

when SIF is

used

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SIC63616-(Rev. 1.0) NO. P53

Table 4.5.8.1(c) Control bits of I/O ports

Address Comment

FF30H

IOC43 IOC42 IOC41 IOC40

FF31H

PUL43 PUL42 PUL41 PUL40

FF32H

SMT43 SMT42 SMT41 SMT40

FF33H

SIP03 SIP02 SIP01 SIP00

FF3CH

*1 Initial value at initial reset

*2 Not set in the circuit

*3 Constantly "0" when being read

D3 D2 D1 D0 Name Init ∗11 0

P43 P42 P41 P40

R/W

P43 P42 P41

P40 IOC43 IOC42 IOC41 IOC40 PUL43 PUL42 PUL41 PUL40

SMT43 SMT42 SMT41 SMT40

SIP03 SIP02 SIP01 SIP00

High

Output

Schmitt Schmitt Schmitt Schmitt

Enable Enable Enable Enable

CMOS CMOS CMOS

CMOS Disable Disable Disable Disable

1 1 1 0 0 0 0

Low Low

P40–P43 I/O port data

Low

Low Input Input

P40–P43 I/O control register

Input Input

Off Off

P40–P43 pull-down control register

Off Off

P40–P43 input interface level select register

P10–P13 interrupt select register

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SIC63616-(Rev. 1.0) NO. P54

Table 4.5.8.1(d) Control bits of I/O ports

Address Comment

PCP03 PCP02 PCP01 PCP00

FF3DH

SIP13 SIP12 SIP11 SIP10

FF3EH

PCP13 PCP12 PCP11 PCP10

FF3FH

ENRTM ENRST ENON BZE

FF44H

FF45H

FF48H

FF58H

FF5AH

RFCNT RFOUT ERF1 ERF0

FF60H

MOD16_A EVCNT_A

FF80H

PTSEL1 PTSEL0

FF81H

MOD16_B EVCNT_B

FF90H

PTSEL3 PTSEL2

FF91H

MOD16_C EVCNT_C

FFA0H

*1 Initial value at initial reset *3 Constantly "0" when being read *2 Not set in the circuit

D3 D2 D1 D0 Name Init ∗11 0

R/W

R/W W R/W

0 BZSTP BZSHT SHTPW

R W R/W

0 0 SWDIR EDIR

R R/W

0 ESOUT SCTRG ESIF

R R/W

0 0

ESREADY

ENCS

R R/W

R/W

FCSEL_A PLPUL_A

R/W

CHSEL_A PTOUT_A

R/W

FCSEL_B PLPUL_B

R/W

CHSEL_B PTOUT_B

R/W

FCSEL_C PLPUL_C

R/W

PCP03 PCP02 PCP01 PCP00

SIP13 SIP12 SIP11

SIP10 PCP13 PCP12 PCP11 PCP10 ENRTM

ENRST

ENON

BZSTP

BZSHT

SHTPW

0 0 SWDIR

0 ESOUT SCTRG

0 0

ESREADY

ENCS

RFCNT RFOUT

MOD16_A

EVCNT_A FCSEL_A PLPUL_A

PTSEL1

PTSEL0

CHSEL_A

PTOUT_A MOD16_B

EVCNT_B FCSEL_B PLPUL_B

PTSEL3

PTSEL2

CHSEL_B

PTOUT_B MOD16_C EVCNT_C FCSEL_C PLPUL_C

BZE

EDIR

ESIF

ERF1 ERF0

∗

1 1 1 1 0

Enable

Enable 1 1 1 1 0

1 sec

Reset

Enable

∗

–

Stop

Trigger

Busy

125 msec

∗

–

∗

–

0 Enable Disable

∗

–

Enable 0

Trigger

Run

SIF

∗

–

∗

–

00SRDY

SIFSSI/O

Continue

Enable 0 0 0

16 bits 0

Event ct.

With NR 0 0

PWM

Timer 1

16 bits

Event ct.

With NR 0 0

PWM

16 bits

Event ct.

With NR 0

Disable Disable Disable Disable

0.5 sec Invalid

Disable

Invalid Invalid Ready

31.25 msec

Disable

Invalid

Normal Disable

No NR

Normal Normal Timer 0

No NR

Normal Normal

No NR

P10–P13 interrupt polarity select register

P40–P43 interrupt select register

P40–P43 interrupt polarity select register

Envelope releasing time selection

Envelope reset (writing)

Envelope On/Off

Off

Buzzer output enable

Unused

1-shot buzzer stop (writing)

1-shot buzzer trigger (writing)

1-shot buzzer status (reading)

1-shot buzzer pulse width setting

Unused

Stopwatch direct input switch

0: P10=Run/Stop, P11=Lap 1: P10=Lap, P11=Run/Stop

Direct input enable

Unused

SOUT enable

Serial I/F clock trigger (writing)

Serial I/F clock status (reading)

Stop

Serial I/F enable (P2 port function selection)

I/O

Unused

P23 port

function selection

ESREADY

Serial I/F enable

(P23 function selection)

ENCS x 0 1

Continuous oscillation enable

RFOUT enable R/f conversion selection

PTM0–1 16-bit mode selection

8 bits

PTM0 counter mode selection

Timer

[ERF1, 0] R/f conversion

I/O1Ch.0 DC2Ch.1 AC3Ch.1 DC

PTM0 function selection (for event counter mode)

PTM0 pulse polarity selection (for event counter mode)

Programmable timer 1 PWM output selection

Programmable timer 0 PWM output selection

PTM0–1 TOUT_A output selection

PTM0–1 TOUT_A output control

Off

PTM2–3 16-bit mode selection

8 bits

PTM2 counter mode selection

Timer

PTM2 function selection (for event counter mode)

PTM2 pulse polarity selection (for event counter mode)

Programmable timer 3 PWM output selection

Programmable timer 2 PWM output selection

General-purpose register

PTM4–5 16-bit mode selection

8 bits

PTM4 counter mode selection

Timer

PTM4 function selection (for event counter mode)

PTM4 pulse polarity selection (for event counter mode)

0 1 1

Slave

(SMOD=0)

P23 I/O

SRDY

Master

(SMOD=1)

P23

I/O I/O

Prohibited

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SIC63616-(Rev. 1.0) NO. P55

Table 4.5.8.1(e) Control bits of I/O ports

Address Comment

PTSEL5 PTSEL4

FFA1H

MOD16_D EVCNT_D FCSEL_D

FFB0H

PTSEL7 PTSEL6

FFB1H

EIK03 EIK02 EIK01 EIK00

FFEBH

EIK13 EIK12 EIK11 EIK10

FFECH

FFFBH

FFFCH

*1 Initial value at initial reset *3 Constantly "0" when being read

*2 Not set in the circuit

D3 D2 D1 D0 Name Init ∗11 0

CHSEL_C PTOUT_C

R/W

CHSEL_D PTOUT_D

R/W

IK03 IK02 IK01 IK00

R/W

IK13 IK12 IK11 IK10

R/W

PLPUL_D

PTSEL5 PTSEL4 CHSEL_C

PTOUT_C MOD16_D EVCNT_D

FCSEL_D PLPUL_D

PTSEL7

PTSEL6

CHSEL_D

PTOUT_D

EIK03 EIK02 EIK01 EIK00 EIK13 EIK12 EIK11 EIK10

IK03 IK02 IK01 IK00 IK13 IK12 IK11 IK10

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PWM PWM

1 1

16 bits

Event ct.

With NR

PWM PWM

1 Enable Enable Enable Enable Enable Enable Enable Enable

(R) Yes

(W)

Reset

(R) Yes

(W)

Reset

Programmable timer 5 PWM output selection

Normal

Programmable timer 4 PWM output selection

Normal

General-purpose register

PTM6–7 16-bit mode selection

8 bits

PTM6 counter mode selection

Timer

PTM6 function selection (for event counter mode)

No NR

PTM6 pulse polarity selection (for event counter mode)

Programmable timer 7 PWM output selection

Normal

Programmable timer 6 PWM output selection

Normal

General-purpose register

Interrupt mask register (Key input interrupt 3 <P13>)

Mask

Interrupt mask register (Key input interrupt 2 <P12>)

Mask

Interrupt mask register (Key input interrupt 1 <P11>)

Mask

Interrupt mask register (Key input interrupt 0 <P10>)

Mask

Interrupt mask register (Key input interrupt 7 <P43>)

Mask

Interrupt mask register (Key input interrupt 6 <P42>)

Mask

Interrupt mask register (Key input interrupt 5 <P41>)

Mask

Interrupt mask register (Key input interrupt 4 <P40>)

Mask

Interrupt factor flag (Key input interrupt 3 <P13>)

(R)

Interrupt factor flag (Key input interrupt 2 <P12>)

Interrupt factor flag (Key input interrupt 1 <P11>)

(W)

Interrupt factor flag (Key input interrupt 0 <P10>)

Invalid

Interrupt factor flag (Key input interrupt 7 <P43>)

(R)

Interrupt factor flag (Key input interrupt 6 <P42>)

Interrupt factor flag (Key input interrupt 5 <P41>)

(W)

Interrupt factor flag (Key input interrupt 4 <P40>)

Invalid

(1) Selecting port functions

ESIF: Serial interface enable (P2 port function select) register (FF58H•D0)

Selects the function for P20–P23.

When "1" is written: Serial interface input/output port When "0" is written: I/O port

Reading: Valid

When using the serial interface, write "1" to this register and when P20–P23 are used as I/O ports, write "0". The conﬁguration of the terminals within P20–P23 that are used for the serial interface depends on master or slave mode set by the SMOD register (see Section 4.10). In slave mode, all the P20–P23 ports are set to the serial interface input/output port. In master mode, P20–P22 are set to the serial interface input/output port and P23 can be used as an I/O port. Furthermore, when the SOUT terminal is disabled (ESOUT = "0"), P21 can be used as an I/O port. At initial reset, this register is set to "0".

ENCS: Serial interface enable (P23 port function select) register (FF5AH•D0)

Selects the function for P23.

When "1" is written: Serial interface input/output port (SRDY or SS) When "0" is written: I/O port

Reading: Valid

Set this register to "0" to use P23 as an I/O port if SRDY output or SS input is not used in slave mode. At initial reset, this register is set to "0".

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ERF1, ERF0: R/f conversion select register (FF60H•D1, D0)

Selects the function for P00–P03. When using the R/f converter, write "01B–11B" to this register and when P00–P03 are used as I/O ports, write "00B". Furthermore, when the RFOUT terminal is disabled (RFOUT = "0"), P03 can be used as an I/O port even if the R/f converter is used. At initial reset, this register is set to "0".

EDIR: Direct input function enable register (FF48H•D0)

Enables the direct input (RUN/LAP) function.

When "1" is written: Enabled When "0" is written: Disabled

Reading: Valid

The direct input function of the stopwatch timer is enabled by writing "1" to EDIR, and the P10 and P11 ports are set for the RUN/STOP and LAP key input ports. When "0" is written to EDIR, the direct input function is disabled, and P10 and P11 can be used as I/O ports. At initial reset, this register is set to "0".

EVCNT_A: PTM0 counter mode select register (FF80H•D2) EVCNT_B: PTM2 counter mode select register (FF90H•D2) EVCNT_C: PTM4 counter mode select register (FFA0H•D2) EVCNT_D: PTM6 counter mode select register (FFB0H•D2)

Selects a counter mode for programmable timer 0/2/4/6.

When "1" is written: Event counter mode When "0" is written: Timer mode

Reading: Valid

When "1" is written to the EVCNT_A/B/C/D register, programmable timer 0/2/4/6 is placed into event counter mode. In this mode, P12/P41/P42/P43 is used as an external clock input port for the event counter. When "0" is written to EVCNT_A/B/C/D, P12/P41/P42/P43 can be used as an I/O port. At initial reset, these registers are set to "0".

(2) I/O port control

P00–P03: P0 I/O port data register (FF20H) P10–P13: P1 I/O port data register (FF24H) P20–P23: P2 I/O port data register (FF28H) P40–P43: P4 I/O port data register (FF30H)

I/O port data can be read and output data can be set through these registers.

• When writing data

When "1" is written: High level When "0" is written: Low level

When an I/O port is placed into output mode, the written data is output unchanged from the I/O port terminal. When "1" is written as port data, the port terminal goes high (VDD), and when "0" is written, the terminal goes low (VSS). Port data can be written also in the input mode.

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• When reading data

When "1" is read: High level When "0" is read: Low level

When the I/O port is placed into input mode, the voltage level being input to the port terminal can be read out. When the terminal voltage is high (VDD), the port data that can be read is "1", and when the terminal voltage is low (VSS) the read data is "0". When the pull-down resistor option has been selected and the PULxx register is set to "1", the built-in pulldown resistor goes on during input mode, so that the I/O port terminal is pulled down.

When the I/O port is placed into output mode, the register value is read. Therefore, when using the data register of a port that is not used for signal input/output as a general-purpose register, set the port to output mode. At initial reset, these registers are set to "1". The data register of the port, which is set for an input/output of the serial interface or R/f converter or a special output, becomes a general-purpose register that does not affect the input/output status.

Note: WhenI/Oportssetininputmodeischangedfromhightolowbythepull-downresistor,thefallof

the waveform is delayed on account of the time constant of the pull-down resistor and input gate

capacitance.Hence,whenfetchinginputdata,setanappropriatewaittime.

Particular care needs to be taken of the key scan during key matrix conﬁguration. Make this waiting time the amount of time or more calculated by the following expression.

 10×C×R

C: terminal capacitance 5 pF + parasitic capacitance ? pF R: pull-down resistance 375 kΩ (Max.)

IOC00–IOC03: P0 port I/O control register (FF21H) IOC10–IOC13: P1 port I/O control register (FF25H) IOC20–IOC23: P2 port I/O control register (FF29H) IOC40–IOC43: P4 port I/O control register (FF31H)

Sets the I/O ports to input or output mode.

When "1" is written: Output mode When "0" is written: Input mode

Reading: Valid

The input/output mode of the I/O ports are set in 1-bit units. Writing "1" to the I/O control register places the corresponding I/O port into output mode, and writing "0" sets input mode. At initial reset, these registers are all set to "0", so the I/O ports are placed in input mode.

The I/O control register of the port, which is set for an input/output of the serial interface or R/f converter or a special output, becomes a general-purpose register that does not affect the input/output status.

PUL00–PUL03: P0 port pull-down control register (FF22H) PUL10–PUL13: P1 port pull-down control register (FF26H) PUL20–PUL23: P2 port pull-down control register (FF2AH) PUL40–PUL43: P4 port pull-down control register (FF32H)

Enables the pull-down during input mode.

When "1" is written: Pull-down On When "0" is written: Pull-down Off

Reading: Valid

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These registers enable the built-in pull-down resistor to be effective during input mode in 1-bit units. (The pull-down resistor is included into the ports selected by mask option.) By writing "1" to the pull-down control register, the corresponding I/O ports are pulled down during input mode, while writing "0" or output mode disables the pull-down function. At initial reset, these registers are all set to "1", so the pull-down function is enabled.

The pull-down control register of the port in which the pull-down resistor is not included becomes a general-purpose register. The register of the port that is set as output for the serial interface, input/output for the R/f converter or a special output can also be used as a general-purpose register that does not affect the pull-down control. The pull-down control register of the port that is set as input for the serial interface functions the same as the I/O port.

SMT10–SMT01: P1 port input interface level select register (FF27H) SMT20–SMT23: P2 port input interface level select register (FF2BH) SMT40–SMT43: P4 port input interface level select register (FF33H)

Selects an input interface level.

When "1" is written: CMOS Schmitt level When "0" is written: CMOS level

Reading: Valid

These registers select the input interface level of the I/O ports in 1-bit units. When "1" is written to SMTxx, the corresponding I/O port Pxx is conﬁgured with a CMOS Schmitt level input interface. When "0" is written, the port is conﬁgured with a CMOS level input interface. (P0x is the ﬁxed setting for CMOS Schmitt level.) At initial reset, these registers are set to "1".

SIP00–SIP03: P1 port interrupt select register (FF3CH) SIP10–SIP13: P4 port interrupt select register (FF3EH)

Selects the ports used for the key input interrupt from P10–P13 and P40–P43.

When "1" is written: Interrupt enable When "0" is written: Interrupt disable

Reading: Valid

By writing "1" to an interrupt select register (SIP00–SIP03, SIP10–SIP13), the corresponding I/O port (P10 –P13, P40–P43) is enabled to generate interrupts. When "0" is written, the I/O port does not affect the interrupt generation. Reactivating from SLEEP status can only be done by generation of a key input interrupt factor. Therefore when using the SLEEP function, it is necessary to set the interrupt select register (SIPxx = "1") of the port to be used for releasing SLEEP status before executing the SLP instruction. At initial reset, these registers are set to "0".

PCP00–PCP03: P1 port interrupt polarity select register (FF3DH) PCP10–PCP13: P4 port interrupt polarity select register (FF3FH)

Sets the interrupt conditions.

When "1" is written: Falling edge When "0" is written: Rising edge

Reading: Valid

When "1" is written to an interrupt polarity select register (PCP00–PCP03, PCP10–PCP13), the corresponding I/O port (P10–P13, P40–P43) generates an interrupt at the falling edge of the input signal. When "0" is written, the I/O port generates an interrupt at the rising edge of the input signal. At initial reset, these registers are set to "1".

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NRSP01, NRSP00: Key input interrupt 0–3 noise reject frequency select register (FF11H•D1, D0) NRSP11, NRSP10: Key input interrupt 4–7 noise reject frequency select register (FF11H•D3, D2)

Selects the noise reject frequency for the key input interrupts.

Table 4.5.8.2 Setting up noise rejector

NRSP01 NRSP11

1 1 0 0

NRSP00 NRSP10

1 0 1 0

Noise reject frequency

fOSC1 / 256 (128 Hz) fOSC1 / 64 (512 Hz) fOSC1 / 16 (2 kHz) OFF (bypassed)

Reject pulse width

7.8 msec

2.0 msec

0.5 msec –

NRSP0x and NRSP1x are the noise reject frequency select registers that correspond to the key input interrupts 0–3 (P10–P13) and the key input interrupts 4–7 (P40–P43), respectively. At initial reset, these registers are set to "00B".

EIK00–EIK03: Key input interrupt 0–3 mask register (FFEBH) EIK10–EIK13: Key input interrupt 4–7 mask register (FFECH)

Enable/disable the key input interrupts.

When "1" is written: Enable When "0" is written: Mask

Reading: Valid

EIK0x and EIK1x are the interrupt mask registers that correspond to the key input interrupts 0–3 (P10–P13) and the key input interrupts 4–7 (P40–P43), respectively. Setting EIKxx to "1" enables the interrupt and setting EIKxx to "0" disables the interrupt. The SLEEP cancellation signal will be generated even if this register is set to "0". However, enable the key input interrupt using the corresponding interrupt mask register before executing the SLP instruction to execute the key input interrupt handler routine after SLEEP status is released. At initial reset, these registers are set to "0".

IK00–IK03: Key input interrupt 0–3 factor ﬂag (FFFBH) IK10–IK13: Key input interrupt 4–7 factor ﬂag (FFFCH)

These ﬂags indicate the occurrence of key input interrupts.

When "1" is read: Interrupt has occurred When "0" is read: Interrupt has not occurred

When "1" is written: Flag reset When "0" is written: Invalid

The interrupt factor ﬂags IK00–IK03 and IK10–IK13 are associated with the key input interrupts 0–3 (P10 –P13) and the key input interrupts 4–7 (P40–P43), respectively. From the status of these ﬂags, the software can decide whether an key input interrupt has occurred. The interrupt factor ﬂag is set to "1" when the interrupt condition is established regardless of the interrupt mask register setting. However, the interrupt does not occur to the CPU when the interrupt is masked. These ﬂags are reset to "0" by writing "1" to them. After an interrupt occurs, the same interrupt will occur again if the interrupt enabled state (I ﬂag = "1") is set or the RETI instruction is executed unless the interrupt factor ﬂag is reset. Therefore, be sure to reset (write "1" to) the interrupt factor ﬂag in the interrupt service routine before shifting to the interrupt enabled state. At initial reset, these ﬂags are set to "0".

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(3) Special output control

FOUT0–FOUT3: FOUT frequency select register (FF10H)

Selects the frequency of the FOUT signal and controls the FOUT output.

Table 4.5.8.3 FOUT clock frequency

FOUT3

: OSC1 oscillation frequency. ( ) indicates the clock frequency when fOSC1 = 32 kHz.

OSC1

: OSC3 oscillation frequency

OSC3

FOUT2

1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0

FOUT1

1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0

FOUT0

1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0

1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0

FOUT frequency

SIC63616-(Rev. 1.0) NO. P60

Selecting an FOUT frequency (writing 1–15 to this register) outputs the FOUT signal from the P23 terminal. Set FOUT0–FOUT3 to "0" to use P23 as a general-purpose DC input/output port. At initial reset, these registers are set to "0".

BZE: Buzzer output control register (FF44H•D0)

Controls the buzzer signal output.

When "1" is written: Buzzer output On When "0" is written: Buzzer output Off

Reading: Valid

When "1" is written to BZE, the BZ signal is output from the P03 terminal. When "0" is written, P03 is used as a general-purpose DC input/output port. At initial reset, this register is set to "0".

BZSHT: One-shot buzzer trigger/status (FF45H•D1)

Controls the one-shot buzzer output.

• When writing

When "1" is written: Trigger When "0" is written: No operation

Writing "1" into BZSHT causes the one-short output circuit to operate and a buzzer signal to be output from the P03 terminal. This output is automatically turned off after the time set by SHTPW has elapsed. The oneshot output is only valid when the normal buzzer output is off (BZE = "0") and will be invalid when the normal buzzer output is on (BZE = "1"). When a re-trigger is assigned during a one-shot output, the oneshot output time set with SHTPW is measured again from that point (time extension).

• When reading

When "1" is read: BUSY When "0" is read: READY

During reading BZSHT shows the operation status of the one-shot output circuit. During one-shot output, BZSHT becomes "1" and the output goes off, it shifts to "0".

At initial reset, this register is set to "0".

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PTOUT_A: TOUT_A output control register (FF81H•D0)

Controls the TOUT_A output.

When "1" is written: TOUT output On When "0" is written: TOUT output Off

Reading: Valid

By writing "1" to the PTOUT_A register, the TOUT_A signal is output from the P13 terminal. When "0" is written, the corresponding terminal is used as a general-purpose DC input/output port. At initial reset, these registers are set to "0".

4.5.9 Programming notes

(1) When an I/O ports in input mode is changed from high to low by the pull-down resistor, the fall of the

waveform is delayed on account of the time constant of the pull-down resistor and input gate capacitance. Hence, when fetching input data, set an appropriate wait time. Particular care needs to be taken of the key scan during key matrix conﬁguration. Make this waiting time the amount of time or more calculated by the following expression. 10 × C × R

C: terminal capacitance 15 pF + parasitic capacitance ? pF R: pull-down resistance 500 kΩ (Max.)

(2) Be sure to turn the noise rejector off before executing the SLP instruction.

(3) Reactivating from SLEEP status can only be done by generation of a key input interrupt factor. There-

fore when using the SLEEP function, it is necessary to set the interrupt select register (SIPxx = "1") of the port to be used for releasing SLEEP status before executing the SLP instruction. Furthermore, enable the key input interrupt using the corresponding interrupt mask register (EIKxx = "1") before executing the SLP instruction to run key input interrupt handler routine after SLEEP status is released.

(4) A hazard may occur when the TOUT_A and FOUT signals are turned on and off.

(5) When f

OSC3

is selected for the FOUT signal frequency, it is necessary to control the OSC3 oscillation

circuit before output. Refer to Section 4.4, "Oscillation Circuit", for the control and notes.

(6) After an interrupt occurs, the same interrupt will occur again if the interrupt enabled state (I ﬂag = "1")

is set or the RETI instruction is executed unless the interrupt factor ﬂag is reset. Therefore, be sure to reset (write "1" to) the interrupt factor ﬂag in the interrupt service routine before shifting to the interrupt enabled state.

(7) Before the port function is conﬁgured, the circuit that uses the port (e.g. input interrupt, multiple key

entry reset, serial interface, event counter input, direct RUN/LAP input for stopwatch) must be disabled.

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4.6 LCD Driver

4.6.1 Conﬁguration of LCD driver

The S1C63616 has a built-in dot matrix LCD driver that can drive an LCD panel with a maximum of 1,280 dots (40 segments × 32 commons). Figures 4.6.1.1 to 4.6.1.3 show the conﬁguration of the LCD driver and the drive power supply.

VCCKS1

VCCKS0

FLCKS1

FLCKS0

DBON

VD2

OSC1

Oscillation circuit

Power supply

voltage

booster/halver

Clock

manager

VDDVD2

VCSEL

VSS

VC1

VC2

VC3

VC4

VC5

CB CC CD

LCD system

voltage regulator

C1–VC5

LCD contrast

adjustment circuit

LCD driver

Display memory

LC3

LC2

LC1

LC0

DSPC1

DSPC0

LDUTY2

LDUTY1

LDUTY0

LPAGE

COM0–COM31 SEG0–SEG39

Fig. 4.6.1.1 Conﬁguration of LCD driver and drive power supply (VC2 reference, 1/5 bias)

VSS

VD2

VC1

VC2

VC3

VC4

VC5

CA CB CC CD CE

VCSEL

OSC1

Oscillation circuit

Power supply

voltage

booster/halver

VDDVD2

LCD system

voltage regulator

C1–VC5

Clock

manager

LCD contrast

adjustment circuit

LCD driver

Display memory

VCCKS1

VCCKS0

FLCKS1

FLCKS0

DBON

LC3

LC2

LC1

LC0

DSPC1

DSPC0

LDUTY2

LDUTY1

LDUTY0

LPAGE

COM0–COM15 SEG0–SEG55

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Fig. 4.6.1.2 Conﬁguration of LCD driver and drive power supply (VC2 reference, 1/4 bias)

OSC1

Oscillation circuit

VSS

VD2

VC1

VC2

VC3

VC4

VC5

CA CB CC CD CE

VCSEL

Power supply

voltage

booster/halver

VDDVD2

LCD system

voltage regulator

Fig. 4.6.1.3 Conﬁguration of LCD driver and drive power supply (VC1 reference, 1/4 bias)

4.6.2 Power supply for LCD driving

C1–VC5

Clock

manager

LCD contrast

adjustment circuit

LCD driver

Display memory

VCCKS1

VCCKS0

FLCKS1

FLCKS0

DBON

LC3

LC2

LC1

LC0

DSPC1

DSPC0

LDUTY2

LDUTY1

LDUTY0

LPAGE

COM0–COM15 SEG0–SEG55

(1) Mask option

The S1C63616 provides three options to conﬁgure the internal LCD power supply for generating the LCD drive voltages VC1–VC5.

TYPE 1 VC2 reference, 1/5 bias VDD = 1.6 to 2.5 V (power supply voltage booster/halver is used) VDD = 2.5 to 5.5 V (power supply voltage booster/halver is not used) TYPE 2 VC2 reference, 1/4 bias VDD = 1.6 to 2.5 V (power supply voltage booster/halver is used) VDD = 2.5 to 5.5 V (power supply voltage booster/halver is not used) TYPE 3 VC1 reference, 1/4 bias VDD = 1.6 to 5.5 V (power supply voltage booster/halver is not used)

Select one from three types according to the supply voltage and the LCD panel characteristics.

The LCD drive voltages are generated by boosting/halving the VC1 or VC2 reference voltage output from the voltage regulator. Table 4.6.2.1 lists the VC1, VC2, VC3, VC4 and VC5 voltage values and boosting/halving status. Note that the number of externally attached parts differs according to the selected bias (1/5 or 1/4). (See Figures

4.6.1.1 to 4.6.1.3.)

Table 4.6.2.1 LCD drive voltage

LCD drive voltage

VC1 VC2 VC3 VC4 VC5

Note: Each LCD drive voltage varies depending on the contrast adjustment register (LCx) setting.

TYPE 1

VC2 × 0.5

VC2 (reference)

VC2 × 1.5

VC2 × 2

VC2 × 2.5

[V]

1.10

2.20

3.30

4.40

5.50

TYPE 2

VC2 × 0.5

VC2 (reference)

= VC2

VC2 × 1.5

VC2 × 2

[V]

1.13

2.25

3.38

4.50

TYPE 3

VC1 (reference)

VC1 × 2

= VC2

VC1 × 3 VC1 × 4

[V]

1.13

2.25

3.38

4.50

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(2) Controlling the LCD system voltage regulator

To start LCD display, turn the LCD system voltage regulator on using the LPWR register. When "1" is written to LPWR, the LCD system voltage regulator goes on and generates the LCD drive voltages listed in Table 4.6.2.1. At initial reset, LPWR is set to "0" (Off). When LCD display is not necessary, turn the LCD system voltage regulator off to reduce power consumption.

To generate stable LCD drive voltages, the LCD system voltage regulator must be driven with a source voltage higher than the reference voltage VC2 or VC1. When a VC2 reference voltage option (TYPE 1 or TYPE 2) is selected, the LCD system voltage regulator can be driven with the VD2 voltage generated by the power supply voltage booster/halver (boost mode) if the supply voltage VDD is less than 2.5 V. The VD2 voltage is generated by approximately doubling the VDD voltage. Use the VCSEL register to select VDD or VD2 to drive the LCD system voltage regulator. VDD is selected when VCSEL is "0" and VD2 is selected when VCSEL is "1". When using VD2, the power supply voltage booster/halver must be turned on by writing "1" to the DBON register before switching to VD2. When the VC1 reference voltage option (TYPE 3) is selected, this control is not required. In this case, VCSEL and DBON should be set to "0".

Furthermore, the LCD system voltage regulator uses the boost clock supplied from the clock manager for boosting/halving the voltage. The clock supply is controlled by the VCCKS0–VCCKS1 register. Set VCCKS to "01B" before writing "1" to LPWR. When LCD display is not necessary, stop the clock supply by setting VCCKS to "00B" to reduce power consumption.

Table 4.6.2.2 Controlling boost clock

VCCKS1

1 0 0

VCCKS0

* 1 0

Boost clock control

Prohibited

On (2 kHz)

Off

Note: The oscillation circuit stops oscillating in SLEEP mode set by the SLP instruction of the CPU.

Therefore,thepowersupplyvoltagebooster/halvercannotgenerateVD2inSLEEPmode.Before executingtheSLPinstruction,conguretheLCDsystemvoltageregulator(VCSEL="0",DBON="0") sothatitwillbedrivenwithVDD.

(3) Heavy load protection mode for LCD system voltage regulator

The LCD system voltage regulator has a heavy load protection function that can be activated with software to stabilize display on the LCD as much as possible (to minimize degradation in display quality) even if ﬂuctuations in the supply voltage occur due to driving an external load. By writing "1" to the VCHLMOD register, the LCD system voltage regulator enters heavy load protection mode to stabilize the VC1 to VC5 outputs. Use the heavy load protection function if the LCD display has inconsistencies in density when a heavy load such as a lamp or buzzer is driven with a port output. At initial reset, VCHLMOD is set to "0" (Off).

Note: The heavy load protection mode increases current consumption compared with normal operation

mode. Therefore, do not set heavy load protection mode unless it is necessary.

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4.6.3 Controlling LCD display

(1) Selecting display mode

In addition to the LPWR register for turning the display on and off, the DSPC0–DSPC1 register is provided to select a display mode. There are four display modes available as shown in Table 4.6.3.1.

Table 4.6.3.1 Display mode

DSPC1

1 1 0 0

DSPC0

1 0 1 0

Normal mode: The screen image written in the display RAM is output without being processed.

(default)

Reverse mode: The screen image written in the display RAM is output in reverse video. The con-

tents in the display RAM are not modiﬁed.

All black mode: Turns all the LCD pixels on (black when normal white LCD is used) in static drive.

The contents in the display RAM are not modiﬁed.

All white mode: Turns all the LCD pixels off (white when normal white LCD is used) in dynamic

drive. The contents in the display RAM are not modiﬁed.

(2) Drive duty and frame frequency

The S1C63616 supports three types of LCD drive duty settings, 1/32, 1/24 and 1/16, and can be switched using the LDUTY2–LDUTY0 register as shown in Table 4.6.3.2. Select an appropriate drive duty according to the LCD panel to be used.

The frame frequency is determined by the selected duty and the clock supplied from the clock manager. The clock to be supplied (8 Hz to 32 Hz) can be selected using the FLCKS0–FLCKS1 register. Selecting a low frame frequency can reduce current consumption.

Display mode

All white mode All black mode

Reverse mode

Normal mode

Note: The frame frequency affects the display quality, therefore, it should be determined after the display

quality is evaluated using the actual LCD panel.

Table 4.6.3.2 Combination of frame frequency and duty

LDUTY2

1 1 1 1 0 0 0 0

LDUTY1

1 1 0 0 1 1 0 0

LDUTY0

1 0 1 0 1 0 1 0

Duty

Prohibited Prohibited Prohibited

1/16 1/24 1/24

Prohibited

1/32

FLCKS = 11B

– – –

8 Hz

5.333 Hz

10.666 Hz –

8 Hz

Frame frequency

FLCKS = 10B

– – –

16 Hz

10.666 Hz

21.333 Hz –

16 Hz

FLCKS = 01B

– – –

21.333 Hz

14.22 Hz

28.44 Hz –

21.333 Hz

FLCKS = 00B

– – –

32 Hz

21.333 Hz

42.666 Hz –

32 Hz

Drive bias

(mask option)

– –

– 1/4 bias 1/5 bias 1/5 bias

– 1/5 bias

Table 4.6.3.3 shows the relationship of the drive duty setting, available SEG/COM terminals and the maximum number of pixels.

Table 4.6.3.3 Drive duty setting, SEG/COM terminals and the maximum number of pixels

Duty

Terminal

1/32 1/24 1/16

SEG0–SEG39

SEG0–SEG39 SEG0–SEG39 SEG0–SEG39

COM31–COM24

SEG40–SEG47 SEG40–SEG47

COM23–COM16

COM23–COM16 COM23–COM16

SEG48–SEG55

COM15–COM0

COM15–COM0 COM15–COM0 COM15–COM0

Number of pixels

1,280 1,152

896

The respective drive waveforms are shown in Figures 4.6.3.1 to 4.6.3.3.

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COM0

10 11 12 13 14 15

16 17 18 19 20 21 22 23

24 25 26 27 28 29 30 31

SIC63616-(Rev. 1.0) NO. P66

32 Hz

31––321031––3210

1 2 3 4 5 6 7

8 9

COM0

COM1

COM2

SEG0

SEG1

123

SEG0

COM0–SEG0

COM0–SEG1

VDD VSS

VC5 VC4 VC3 VC2 VC1 VSS

VC5 VC4 VC3 VC2 VC1 V (GND)SS

-VC1

-VC2

-VC3

-VC4

-VC5

VC5 VC4 VC3 VC2 VC1 V (GND)SS

-VC1

-VC2

-VC3

-VC4

-VC5

Fig. 4.6.3.1 Drive waveform for 1/32 duty (FLCKS = "00B")

3240-0412

Page 74

COM0

10 11 12 13 14 15

16 17 18 19 20 21 22 23

SIC63616-(Rev. 1.0) NO. P67

42 (21) Hz

23––321023––3210

1 2 3 4 5 6 7

8 9

COM0

COM1

COM2

SEG0

123

SEG0

SEG1

COM0–SEG0

COM0–SEG1

VDD VSS

VC5 VC4 VC3 VC2 VC1 VSS

VC5 VC4 VC3 VC2 VC1 V (GND)SS

-VC1

-VC2

-VC3

-VC4

-VC5

VC5 VC4 VC3 VC2 VC1 V (GND)SS

-VC1

-VC2

-VC3

-VC4

-VC5

Fig. 4.6.3.2 Drive waveform for 1/24 duty (FLCKS = "00B")

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COM0

10 11 12 13 14 15

SIC63616-(Rev. 1.0) NO. P68

32 Hz

15––321015––3210

1 2 3 4 5 6 7

8 9

123

SEG0

COM0

COM1

COM2

SEG0

SEG1

VDD VSS

VC5 VC4 VC2=VC3 VC1 VSS

COM0–SEG0

COM0–SEG1

Fig. 4.6.3.3 Drive waveform for 1/16 duty (FLCKS = "00B")

VC5 VC4

VC2=VC3 VC1 VSS (GND)

-VC1

-VC2=-VC3

-VC4

-VC5

VC5 VC4 VC2=VC3 VC1 VSS (GND)

-VC1

-VC2=-VC3

-VC4

-VC5

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SIC63616-(Rev. 1.0) NO. P69

4.6.4 Display memory

The display memory is allocated to F000H–F36FH in the data memory area and the addresses and the data bits correspond to COM and SEG outputs as shown in Figures 4.6.4.1 to 4.6.4.3.

COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7

COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15

COM16 COM17 COM18 COM19 COM20 COM21 COM22 COM23

COM24 COM25 COM26 COM27 COM28 COM29 COM30 COM31

SEG0

■ D0

■ D1

■ D2

■ D3

■ D0

■ D1

■ D2

■ D3

■ D0

■ D1

■ D2

■ D3

■ D0

■ D1

■ D2

■ D3

■ D0

■ D1

■ D2

■ D3

■ D0

■ D1

■ D2

■ D3

■ D0

■ D1

■ D2

■ D3

■ D0

■ D1

■ D2

■ D3

F000H

F001H

F100H

F101H

F200H

F201H

F300H

F301H

SEG1

■ D0

■ D1

■ D2

■ D3

■ D0

■ D1

■ D2

■ D3

■ D0

■ D1

■ D2

■ D3

■ D0

■ D1

■ D2

■ D3

■ D0

■ D1

■ D2

■ D3

■ D0

■ D1

■ D2

■ D3

■ D0

■ D1

■ D2

■ D3

■ D0

■ D1

■ D2

■ D3

F002H

F003H

F102H

F103H

F202H

F203H

F302H

F303H

SEG2

■ D0

■ D1

■ D2

■ D3

■ D0

■ D1

■ D2

■ D3

■ D0

■ D1

■ D2

■ D3

■ D0

■ D1

■ D2

■ D3

■ D0

■ D1

■ D2

■ D3

■ D0

■ D1

■ D2

■ D3

■ D0

■ D1

■ D2

■ D3

■ D0

■ D1

■ D2

■ D3

F004H

F005H

F104H

F105H

F204H

F205H

F304H

F305H

SEG3

■ D0

■ D1

■ D2

■ D3

■ D0

■ D1

■ D2

■ D3

■ D0

■ D1

■ D2

■ D3

■ D0

■ D1

■ D2

■ D3

■ D0

■ D1

■ D2

■ D3

■ D0

■ D1

■ D2

■ D3

■ D0

■ D1

■ D2

■ D3

■ D0

■ D1

■ D2

■ D3

F006H

F007H

F106H

F107H

F206H

F207H

F306H

F307H

. . . . .

SEG39

■

■ D1

■ D2

■ D3

■ D0

■ D1

■ D2

■ D3

■ D0

■ D1

■ D2

■ D3

■ D0

■ D1

■ D2

■ D3

■ D0

■ D1

■ D2

■ D3

■ D0

■ D1

■ D2

■ D3

■ D0

■ D1

■ D2

■ D3

■ D0

■ D1

■ D2

■ D3

F04EH

F04FH

F14EH

F14FH

F24EH

F24FH

F34EH

F34FH

Memory address Data bit

Fig. 4.6.4.1 Correspondence between display memory and LCD dot matrix (1/32 duty)

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SIC63616-(Rev. 1.0) NO. P70

COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7

COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15

COM16 COM17 COM18 COM19 COM20 COM21 COM22 COM23

SEG0

■ D0

■ D1

F000H

■ D2

■ D3

■ D0

■ D1

F001H

■ D2

■ D3

■ D0

■ D1

F100H

■ D2

■ D3

■ D0

■ D1

F101H

■ D2

■ D3

■ D0

■ D1

F200H

■ D2

■ D3

■ D0

■ D1

F201H

■ D2

■ D3

Memory address Data bit

SEG1

■ D0

■ D1

■ D2

■ D3

■ D0

■ D1

■ D2

■ D3

■ D0

■ D1

■ D2

■ D3

■ D0

■ D1

■ D2

■ D3

■ D0

■ D1

■ D2

■ D3

■ D0

■ D1

■ D2

■ D3

F002H

F003H

F102H

F103H

F202H

F203H

SEG2

■ D0

■ D1

■ D2

■ D3

■ D0

■ D1

■ D2

■ D3

■ D0

■ D1

■ D2

■ D3

■ D0

■ D1

■ D2

■ D3

■ D0

■ D1

■ D2

■ D3

■ D0

■ D1

■ D2

■ D3

F004H

F005H

F104H

F105H

F204H

F205H

SEG3

■ D0

■ D1

■ D2

■ D3

■ D0

■ D1

■ D2

■ D3

■ D0

■ D1

■ D2

■ D3

■ D0

■ D1

■ D2

■ D3

■ D0

■ D1

■ D2

■ D3

■ D0

■ D1

■ D2

■ D3

F006H

F007H

F106H

F107H

F206H

F207H

. . . . .

Fig. 4.6.4.2 Correspondence between display memory and LCD dot matrix (1/24 duty)

SEG47

■

■ D1

■ D2

■ D3

■ D0

■ D1

■ D2

■ D3

■ D0

■ D1

■ D2

■ D3

■ D0

■ D1

■ D2

■ D3

■ D0

■ D1

■ D2

■ D3

■ D0

■ D1

■ D2

■ D3

F05EH

F05FH

F15EH

F15FH

F25EH

F25FH

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SIC63616-(Rev. 1.0) NO. P71

LPAGE

= 0

LPAGE

= 1

COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7

COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15

COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7

COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15

SEG0

■ D0

■ D1

■ D2

■ D3

■ D0

■ D1

■ D2

■ D3

■ D0

■ D1

■ D2

■ D3

■ D0

■ D1

■ D2

■ D3

■ D0

■ D1

■ D2

■ D3

■ D0

■ D1

■ D2

■ D3

■ D0

■ D1

■ D2

■ D3

■ D0

■ D1

■ D2

■ D3

F000H

F001H

F100H

F101H

F200H

F201H

F300H

F301H

SEG1

■ D0

■ D1

■ D2

■ D3

■ D0

■ D1

■ D2

■ D3

■ D0

■ D1

■ D2

■ D3

■ D0

■ D1

■ D2

■ D3

■ D0

■ D1

■ D2

■ D3

■ D0

■ D1

■ D2

■ D3

■ D0

■ D1

■ D2

■ D3

■ D0

■ D1

■ D2

■ D3

F002H

F003H

F102H

F103H

F202H

F203H

F302H

F303H

SEG2

■ D0

■ D1

■ D2

■ D3

■ D0

■ D1

■ D2

■ D3

■ D0

■ D1

■ D2

■ D3

■ D0

■ D1

■ D2

■ D3

■ D0

■ D1

■ D2

■ D3

■ D0

■ D1

■ D2

■ D3

■ D0

■ D1

■ D2

■ D3

■ D0

■ D1

■ D2

■ D3

F004H

F005H

F104H

F105H

F204H

F205H

F304H

F305H

SEG3

■ D0

■ D1

■ D2

■ D3

■ D0

■ D1

■ D2

■ D3

■ D0

■ D1

■ D2

■ D3

■ D0

■ D1

■ D2

■ D3

■ D0

■ D1

■ D2

■ D3

■ D0

■ D1

■ D2

■ D3

■ D0

■ D1

■ D2

■ D3

■ D0

■ D1

■ D2

■ D3

F006H

F007H

F106H

F107H

F206H

F207H

F306H

F307H

. . . . .

SEG55

■

■ D1

■ D2

■ D3

■ D0

■ D1

■ D2

■ D3

■ D0

■ D1

■ D2

■ D3

■ D0

■ D1

■ D2

■ D3

■ D0

■ D1

■ D2

■ D3

■ D0

■ D1

■ D2

■ D3

■ D0

■ D1

■ D2

■ D3

■ D0

■ D1

■ D2

■ D3

F06EH

F06FH

F16EH

F16FH

F26EH

F26FH

F36EH

F36FH

Memory address Data bit

Fig. 4.6.4.3 Correspondence between display memory and LCD dot matrix (1/16 duty)

When a bit in the display memory is set to "1", the corresponding LCD pixel goes on, and when it is set to "0", the pixel goes off.

When 1/16 duty is selected, the display memory area can be used for two screen images. Select either F000H–F16FH or F200H–F36FH for the area to be displayed using the LPAGE register. This allows the software to switch the screen in an instant.

At initial reset, the data memory contents become undeﬁned hence, there is need to initialize using the software. The display memory has read/write capability, and the addresses that have not been used for LCD display can be used as general purpose registers.

Note: Whenaprogramthataccessnomemoryimplementedarea(F070H–F0FFH,F170H–F1FFH,F270H

–F2FFH,F370H–F3FFH)ismade,theoperationisnotguaranteed.

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SIC63616-(Rev. 1.0) NO. P72

4.6.5 LCD contrast adjustment

The LCD driver allows the software to adjust the LCD contrast. It is realized by controlling the voltages VC1–VC5 output from the LCD system voltage regulator. The contrast can be adjusted to 16 levels using the LC3–LC0 register.

Table 4.6.5.1 LCD contrast

No.

LC3

LC2

LC1

LC0

Contrast

Light

Dark

At initial reset, the LC3–LC0 register is set to 0000B. The software should initialize the register to get the desired contrast.

3240-0412

Page 80

SIC63616-(Rev. 1.0) NO. P73

4.6.6 I/O memory of LCD driver

Table 4.6.6.1 shows the I/O addresses and the control bits for the LCD driver. Figure 4.6.6.1 shows the display memory map.

Table 4.6.6.1 Control bits of LCD driver

Address Comment

VDSEL VCSEL HLON DBON

FF02H

VCHLMOD VDHLMOD

FF03H

FLCKS1 FLCKS0 VCCKS1 VCCKS0

FF12H

General LPAGE DSPC1 DSPC0

FF50H

General LDUTY2 LDUTY1 LDUTY0

FF51H

FF52H

*1 Initial value at initial reset

*2 Not set in the circuit

*3 Constantly "0" when being read

D3 D2 D1 D0 Name Init

VDSEL VCSEL

R/W

General LPWR

R/W

LC3 LC2 LC1 LC0

R/W

HLON

DBON VCHLMOD VDHLMOD

General

LPWR FLCKS1 FLCKS0 VCCKS1 VCCKS0

General

LPAGE

DSPC1 DSPC0

General

LDUTY2

LDUTY1

LDUTY0

LC3 LC2 LC1 LC0

∗1

1 0

0 0

On 0 0 0 0 0

F200-F36F0F000-F16F

0 0 0

1 0

0 0 0 0

General-purpose register

Power source select for LCD system voltage regulator

Off

Power voltage booster/halver halving mode On/Off

Off

Power voltage booster/halver boost mode On/Off

Heavy load protection mode On/Off for LCD system voltage regulator

Off

Heavy load protection mode On/Off for internal voltage regulator

Off

General-purpose register

LCD system voltage regulator On/Off

Off

Frame frequency selection VC boost frequency selection

General-purpose register

Display memory area (when 1/16 duty is selected)

functions as a general-purpose register when 1/24 or 1/32 is selected

LCD display

mode selection

General-purpose register

LCD

drive duty

selection

LCD contrast adjustment

[LC3—0] Contrast

[FLCKS1, 0] Frequency

[VCCKS1, 0] Frequency

[DSPC1, 0] Display mode

[LDUTY2—0] Duty

Light——15Dark

32 Hz124 Hz216 Hz38 Hz

Off

Normal1Reverse

1/32 (32 Hz)

1/24 (21 Hz)

2 kHz

All lit3All off

Prohibited

1/16 (32 Hz)

2, 3

Prohibited

1/24 (42 Hz)

5—7

Prohibited

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Page 81

SIC63616-(Rev. 1.0) NO. P74

Not implemented

(prohibition of read/write)

F000H

: F04FH F050H F05FH F060H F06FH F070H

F0FFH

SEG0 : : : : : SEG55

SEG0 : : : SEG47

SEG0 : SEG39

SEG0 : : : : : SEG55

SEG0 : : : SEG47

SEG0 : SEG39

SEG0 : : : : : SEG55

SEG0 : : : SEG47

SEG0 : SEG39

SEG0 : : : : : SEG55

SEG0 : : : SEG47

SEG0 : SEG39

1/32 duty

Not implemented

(prohibition of read/write)

1/24 duty

Not implemented

(prohibition of read/write)

1/16 duty

Display data area

(COM0–COM7)

Display data area

(COM0–COM7)

Unused area

Display data area 0

(COM0–COM7)

Not implemented

(prohibition of read/write)

F100H

: F14FH F150H F15FH F160H F16FH F170H

F1FFH

Not implemented

(prohibition of read/write)

Not implemented

(prohibition of read/write)

Display data area

(COM8–COM15)

Display data area

(COM8–COM15)

Unused area

Display data area 0

(COM8–COM15)

Not implemented

(prohibition of read/write)

F200H

: F24FH F250H F25FH F260H F26FH F270H

F2FFH

Not implemented

(prohibition of read/write)

Not implemented

(prohibition of read/write)

Display data area

(COM16–COM23)

Display data area

(COM16–COM23)

Unused area

Display data area 1

(COM0–COM7)

Not implemented

(prohibition of read/write)

F300H

: F34FH F350H F35FH F360H F36FH F370H

F3FFH

Not implemented

(prohibition of read/write)

Not implemented

(prohibition of read/write)

Display data area

(COM24–COM31)

Unused area

Display data area 1

(COM8–COM15)

Fig. 4.6.6.1 Display memory map

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SIC63616-(Rev. 1.0) NO. P75

DBON: Power supply voltage booster/halver boost mode On/Off register (FF02H•D0)

Activates the power supply voltage booster/halver in boost mode.

When "1" is written: Booster On When "0" is written: Booster Off

Reading: Valid

VCSEL: LCD system voltage regulator power source switch register (FF02H•D2)

Selects the power voltage for the LCD system voltage regulator.

When "1" is written: V When "0" is written: V

Reading: Valid

Note: DonotsetDBONto"1"(boostmode)andVCSELto"1"(drivingwithVD2)ifthesupplyvoltageVDD

exceeds2.5V,asitmaycausedamageoftheIC.

LPWR: LCD system voltage regulator On/Off register (FF03H•D0)

Turns the LCD system voltage regulator on and off.

When "1" is written: On When "0" is written: Off

Reading: Valid

VCHLMOD: LCD system voltage regulator heavy load protection On/Off register (FF03H•D3)

Enables heavy load protection function for the LCD system voltage regulator.

When "1" is written: On When "0" is written: Off

Reading: Valid

By writing "1" to VCHLMOD, the LCD system voltage regulator enters heavy load protection mode to minimize degradation in display quality when ﬂuctuations in the supply voltage occurs due to driving a heavy load. The heavy load protection function is effective when the OSC3 clock is used or the buzzer/FOUT signal is being output. However, heavy load protection mode increases current consumption compared with normal operation mode. Therefore, do not set heavy load protection mode unless it is necessary. At initial reset, this register is set to "0".

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SIC63616-(Rev. 1.0) NO. P76

VCCKS0, VCCKS1: VC boost frequency select register (FF12H•D0, D1)

Controls the boost clock supply to the LCD system voltage regulator.

Table 4.6.6.2 Controlling boost clock

VCCKS1

1 0 0

VCCKS0

* 1 0

Boost clock control

Prohibited

On (2 kHz)

Off

The LCD system voltage regulator uses the boost clock supplied from the clock manager for boosting/ reducing the voltage. Use this register to control the clock supply. Set VCCKS to "01B" before writing "1" to LPWR. When LCD display is not necessary, stop the clock supply by setting VCCKS to "00B" to reduce power consumption. At initial reset, this register is set to "00B".

FLCKS0, FLCKS1: Frame frequency select register (FF12H•D2, D3)

Selects the frequency of the frame clock supplied from the clock manager.

Table 4.6.6.3 Selecting frame frequency

FLCKS1

1 1 0 0

FLCKS0

1 0 1 0

Frame frequency

8 Hz 16 Hz 24 Hz 32 Hz

(When f

OSC1 = 32.768 Hz)

See Table 4.6.6.5 for the frame frequency when 1/24 duty is selected by the LDUTY0–LDUTY2 register. At initial reset, this register is set to "00B".

DSPC0, DSPC1: Display mode select register (FF50H•D0, D1)

Sets the display mode.

Table 4.6.6.4 Display mode

DSPC1

1 1 0 0

DSPC0

1 0 1 0

Display mode

All white mode All black mode

Reverse mode

Normal mode

In normal mode, the screen image written in the display RAM is output without being processed. In reverse mode, the screen image written in the display RAM is output in reverse video. All black mode turns all the LCD pixels on (black when normal white LCD is used) in static drive. All white mode turns all the LCD pixels off (white when normal white LCD is used) in dynamic drive. The contents in the display RAM are not modiﬁed by setting this register. At initial reset, this register is set to "00B".

LPAGE: LCD display memory area select register (FF50H•D2)

Selects the display memory area at 1/16 duty drive.

When "1" is written: F200H–F36FH When "0" is written: F000H–F16FH

Reading: Valid

By writing "1" to the LPAGE register, the data set in F200H–F36FH (the second half of the display memory) is displayed, and when "0" is written, the data set in F000H–F16FH (the ﬁrst half of the display memory) is displayed. This function is valid only when 1/16 duty is selected, and when 1/24 or 1/32 duty is selected, this register can be used as a general purpose register. At initial reset, this register is set to "0".

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LDUTY0–LDUTY2: LCD drive duty switching register (FF51H•D0–D2)

Selects the LCD drive duty.

Table 4.6.6.5 Drive duty setting

LDUTY2

1 1 1 1 0 0 0 0

LDUTY1

1 1 0 0 1 1 0 0

LDUTY0

1 0 1 0 1 0 1 0

Duty

Prohibited Prohibited Prohibited

1/16 1/24 1/24

Prohibited

1/32

FLCKS = 11B

– – –

8 Hz

5.333 Hz

10.666 Hz –

8 Hz

Frame frequency

FLCKS = 10B

– – –

16 Hz

10.666 Hz

21.333 Hz –

16 Hz

FLCKS = 01B

21.333 Hz

14.22 Hz

28.44 Hz

21.333 Hz

At initial reset, this register is set to "000B".

LC3–LC0: LCD contrast adjustment register (FF52H)

Adjusts the LCD contrast.

Table 4.6.6.6 LCD contrast

No.

LC3

LC2

LC1

LC0

Contrast

Light

Dark

– – –

–

SIC63616-(Rev. 1.0) NO. P77

FLCKS = 00B

– – –

32 Hz

21.333 Hz

42.666 Hz –

32 Hz

Drive bias

(mask option)

– –

– 1/4 bias 1/5 bias 1/5 bias

– 1/5 bias

Setting this register changes the VC1–VC5 LCD drive voltages. At initial reset, this register is set to "0000B".

3240-0412

Page 85

SIC63616-(Rev. 1.0) NO. P78

4.6.7 Programming notes

(1) When a program that access no memory implemented area (F070H–F0FFH, F170H–F1FFH, F270H–

F2FFH, F370H–F3FFH) is made, the operation is not guaranteed.

(2) When driving the LCD system voltage regulator with VD2, wait at least 1 msec for stabilization of the

voltage before switching the power voltage for the LCD system voltage regulator to VD2 using VCSEL after the power supply voltage booster/halver is turned on.

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4.7 Clock Timer

4.7.1 Conﬁguration of clock timer

The S1C63616 has a built-in clock timer that uses OSC1 (crystal oscillator) as the source oscillator. The clock timer is conﬁgured of an 8-bit binary counter that serves as the input clock, f the prescaler. Timer data (128–16 Hz and 8–1 Hz) can be read out by the software. Figure 4.7.1.1 is the block diagram for the clock timer.

Data bus

OSC1

divided clock output from

OSC1 oscillation circuit (fOSC1)

Clock enable signal

Clock timer RUN/STOP signal

Clock

manager

Clock timer reset signal

fOSC1/128

128 Hz–16 Hz

Clock timer

8 Hz–1 Hz

128 Hz, 64 Hz, 32 Hz, 16 Hz, 8 Hz, 4 Hz, 2 Hz, 1 Hz

Interrupt

control

Interrupt request

Fig. 4.7.1.1 Block diagram for the clock timer

Ordinarily, this clock timer is used for all types of timing functions such as clocks.

4.7.2 Controlling clock manager

The clock manager generates the clock timer operating clock by dividing the OSC1 clock by 128. Before the clock timer can be run, write "1" to the RTCKE register to supply the operating clock to the clock timer.

Table 4.7.2.1 Controlling clock timer operating clock

RTCKE

1 0

Clock timer operating clock

fOSC1 / 128 (256 Hz)

Off

If it is not necessary to run the clock timer, stop the clock supply by setting RTCKE to "0" to reduce current consumption.

4.7.3 Data reading and hold function

The 8 bits timer data are allocated to the address FF41H and FF42H.

<FF41H> D0: TM0 = 128 Hz D1: TM1 = 64 Hz D2: TM2 = 32 Hz D3: TM3 = 16 Hz <FF42H> D0: TM4 = 8 Hz D1: TM5 = 4 Hz D2: TM6 = 2 Hz D3: TM7 = 1 Hz

Since two addresses are allocated for the clock timer data, a carry is generated from the low-order data (TM0 –TM3: 128–16 Hz) to the high-order data (TM4–TM7: 8–1 Hz) during counting. If this carry is generated between readings of the low-order data and the high-order data, the combined data does not represent the correct value (if a carry occurs after the low-order data is read as FFH, the incremented (+1) value is read as the high-order data). To avoid this problem, the clock timer is designed to latch the high-order data at the time the low-order data is read. The latched high-order data will be maintained until the next reading of the low-order data.

Note: The latched value, not the current value, is always read as the high-order data. Therefore, be sure to

read the low-order data ﬁrst.

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4.7.4 Interrupt function

The clock timer can generate an interrupt at the falling edge of 128 Hz, 64 Hz, 32 Hz, 16 Hz, 8 Hz, 4 Hz, 2 Hz and 1 Hz signals. Software can enable or mask any of these frequencies to generate interrupts. Figure 4.7.4.1 is the timing chart of the clock timer.

Address

FF41H

FF42H

Bit

128 Hz interrupt request

64 Hz interrupt request

32 Hz interrupt request

16 Hz interrupt request

8 Hz interrupt request

4 Hz interrupt request

2 Hz interrupt request

Frequency Clock timer timing chart

128 Hz

64 Hz

32 Hz

16 Hz

8 Hz

4 Hz

2 Hz

1 Hz

1 Hz interrupt request

Fig. 4.7.4.1 Timing chart of clock timer

As shown in Figure 4.7.4.1, an interrupt is generated at the falling edge of each frequency signal (128 Hz, 64 Hz, 32 Hz, 16 Hz, 8 Hz, 4 Hz, 2 Hz, 1 Hz). At this time, the corresponding interrupt factor ﬂag (IT0, IT1, IT2, IT3, IT4, IT5, IT6, IT7) is set to "1". The interrupt mask registers (EIT0, EIT1, EIT2, EIT3, EIT4, EIT5, EIT6, EIT7) are used to enable or mask each interrupt factor. However, regardless of the interrupt mask register setting, the interrupt factor ﬂag is set to "1" at the falling edge of the corresponding signal.

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4.7.5 I/O memory of clock timer

Table 4.7.5.1 shows the I/O addresses and the control bits for the clock timer.

Table 4.7.5.1 Control bits of clock timer

Address Comment

MDCKE SGCKE SWCKE RTCKE

FF16H

FF40H

TM3 TM2 TM1 TM0

FF41H

TM7 TM6 TM5 TM4

FF42H

EIT3 EIT2 EIT1 EIT0

FFEEH

EIT7 EIT6 EIT5 EIT4

FFEFH

FFFEH

FFFFH

*1 Initial value at initial reset

*2 Not set in the circuit

*3 Constantly "0" when being read

D3 D2 D1 D0 Name Init

MDCKE

SGCKE

R/W

0 0 TMRST TMRUN

W R/WR

R/W

IT3 IT2 IT1 IT0

R/W

IT7 IT6 IT5 IT4

R/W

SWCKE

RTCKE

0 0

TMRST

TMRUN

TM3 TM2 TM1 TM0 TM7 TM6 TM5 TM4 EIT3 EIT2 EIT1 EIT0 EIT7 EIT6 EIT5 EIT4

IT3 IT2 IT1 IT0 IT7 IT6 IT5 IT4

∗

–

∗

–

∗

Reset0Reset

∗1

1 0

Enable

∗

Run 0 0 0 0 0 0 0 0 0

Enable

(R)

Yes

(W)

Reset

(R)

Yes

(W)

Reset

Integer multiplier clock enable

Disable

Sound generator clock enable

Disable

Stopwatch timer clock enable

Disable

Clock timer clock enable

Disable

Unused

Invalid

Clock timer reset (writing)

Stop

Clock timer Run/Stop

Clock timer data (16 Hz)

Clock timer data (32 Hz)

Clock timer data (64 Hz)

Clock timer data (128 Hz)

Clock timer data (1 Hz)

Clock timer data (2 Hz)

Clock timer data (4 Hz)

Clock timer data (8 Hz)

Interrupt mask register (Clock timer 16 Hz)

Mask

Interrupt mask register (Clock timer 32 Hz)

Mask

Interrupt mask register (Clock timer 64 Hz)

Mask

Interrupt mask register (Clock timer 128 Hz)

Mask

Interrupt mask register (Clock timer 1 Hz)

Mask

Interrupt mask register (Clock timer 2 Hz)

Mask

Interrupt mask register (Clock timer 4 Hz)

Mask

Interrupt mask register (Clock timer 8 Hz)

Mask

Interrupt factor flag (Clock timer 16 Hz)

(R)

Interrupt factor flag (Clock timer 32 Hz)

Interrupt factor flag (Clock timer 64 Hz)

(W)

Interrupt factor flag (Clock timer 128 Hz)

Invalid

Interrupt factor flag (Clock timer 1 Hz)

(R)

Interrupt factor flag (Clock timer 2 Hz)

Interrupt factor flag (Clock timer 4 Hz)

(W)

Interrupt factor flag (Clock timer 8 Hz)

Invalid

SIC63616-(Rev. 1.0) NO. P81

RTCKE: Clock timer clock enable register (FF16H•D0)

Controls the operating clock supply to the clock timer.

When "1" is written: On When "0" is written: Off

Reading: Valid

When "1" is written to RTCKE, the clock timer operating clock is supplied from the clock manager. If it is not necessary to run the clock timer, stop the clock supply by setting RTCKE to "0" to reduce current consumption. At initial reset, this register is set to "0".

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TMRUN: Clock timer Run/Stop control register (FF40H•D0)

Controls run/stop of the clock timer.

When "1" is written: Run When "0" is written: Stop

Reading: Valid

The clock timer starts running when "1" is written to the TMRUN register, and stops when "0" is written. In stop status, the timer data is maintained until the next run status or the timer is reset. Also, when stop status changes to run status, the data that is maintained can be used for resuming the count. At initial reset, this register is set to "0".

TMRST: Clock timer reset (FF40H•D1)

This bit resets the clock timer.

When "1" is written: Clock timer reset When "0" is written: No operation

Reading:

Always "0"

The clock timer is reset by writing "1" to TMRST. When the clock timer is reset in run status, counting restarts immediately. Also, in stop status the reset data is maintained. No operation results when "0" is written to TMRST. This bit is write-only, and so is always "0" at reading.

TM0–TM7: Timer data (FF41H, FF42H)

The 128–1 Hz timer data of the clock timer can be read out with these registers. These eight bits are read only, and writing operations are invalid. By reading the low-order data (FF41H), the high-order data (FF42H) is latched. The latched value, not the current value, is always read as the high-order data. Therefore, be sure to read the low-order data ﬁrst. At initial reset, the timer data is initialized to "00H".

EIT0: 128 Hz interrupt mask register (FFEEH•D0) EIT1: 64 Hz interrupt mask register (FFEEH•D1) EIT2: 32 Hz interrupt mask register (FFEEH•D2) EIT3: 16 Hz interrupt mask register (FFEEH•D3) EIT4: 8 Hz interrupt mask register (FFEFH•D0) EIT5: 4 Hz interrupt mask register (FFEFH•D1) EIT6: 2 Hz interrupt mask register (FFEFH•D2) EIT7: 1 Hz interrupt mask register (FFEFH•D3)

These registers are used to select whether to mask the clock timer interrupt.

When "1" is written: Enabled When "0" is written: Masked

Reading: Valid

The interrupt mask registers (EIT0, EIT1, EIT2, EIT3, EIT4, EIT5, EIT6, EIT7) are used to select whether to mask the interrupt to the separate frequencies (128 Hz, 64 Hz, 32 Hz, 16 Hz, 8 Hz, 4 Hz, 2 Hz, 1 Hz). At initial reset, these registers are set to "0".

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IT0: 128 Hz interrupt factor ag (FFFEH•D0) IT1: 64 Hz interrupt factor ag (FFFEH•D1) IT2: 32 Hz interrupt factor ag (FFFEH•D2) IT3: 16 Hz interrupt factor ag (FFFEH•D3) IT4: 8 Hz interrupt factor ag (FFFFH•D0) IT5: 4 Hz interrupt factor ag (FFFFH•D1) IT6: 2 Hz interrupt factor ag (FFFFH•D2) IT7: 1 Hz interrupt factor ag (FFFFH•D3)

These ﬂags indicate the status of the clock timer interrupt.

When "1" is read: Interrupt has occurred When "0" is read: Interrupt has not occurred

When "1" is written: Flag reset When "0" is written: Invalid

The interrupt factor ﬂags (IT0, IT1, IT2, IT3, IT4, IT5, IT6, IT7) correspond to the clock timer interrupts of the respective frequencies (128 Hz, 64 Hz, 32 Hz, 16 Hz, 8 Hz, 4 Hz, 2 Hz, 1 Hz). The software can judge from these ﬂags whether there is a clock timer interrupt. However, even if the interrupt is masked, the ﬂags are set to "1" at the falling edge of the signal. These ﬂags are reset to "0" by writing "1" to them. After an interrupt occurs, the same interrupt will occur again if the interrupt enabled state (I ﬂag = "1") is set or the RETI instruction is executed unless the interrupt factor ﬂag is reset. Therefore, be sure to reset (write "1" to) the interrupt factor ﬂag in the interrupt service routine before shifting to the interrupt enabled state. At initial reset, these ﬂags are set to "0".

4.7.6 Programming notes

(1) Be sure to read timer data in the order of low-order data (TM0–TM3) then high-order data (TM4–TM7).

(2) The clock timer count clock does not synch with the CPU clock. Therefore, the correct value may not

be obtained depending on the count data read and count-up timings. To avoid this problem, the clock timer count data should be read by one of the procedures shown below.

•Readthecountdatatwiceandverifyifthereisanydifferencebetweenthem.

•Temporarilystoptheclocktimerwhenthecounterdataisreadtoobtainproperdata.

(3) After an interrupt occurs, the same interrupt will occur again if the interrupt enabled state (I ﬂag = "1")

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Clock

manager

[SWCKE]

OSC1

oscillation

circuit

OSC1

)

Data bus

1 Hz interrupt request

1,000 / 1,024

prescaler

1/1,000 sec

counter

1/100 sec

counter

1/10 sec

counter

Capture buffer

SWD0–3 reading

SWD4–7 reading

SWD8–11 reading

[SWRST]

10 Hz interrupt request

Capture

control

circuit

[SWRUN]

[EDIR]

[CRNWF]

[DKM2–0]

[LCURF]

Direct RUN interrupt request Direct LAP interrupt request

(1,000 Hz)

Direct

input

control

[SWDIR]

P11

P10

P12, P13,

P40–P43

4.8 Stopwatch Timer

4.8.1 Conﬁguration of stopwatch timer

The S1C63616 has a 1/1,000 sec stopwatch timer. The stopwatch timer is conﬁgured of a 3-stage, 4-bit BCD counter serving as the input clock of a 1,000 Hz signal output from the prescaler. Data can be read out four bits (1/1,000 sec, 1/100 sec and 1/10 sec) at a time by the software. In addition it has a direct input function that controls the stopwatch timer RUN/STOP and LAP using the input ports P10 and P11. Figure 4.8.1.1 is the block diagram of the stopwatch timer.

Fig. 4.8.1.1 Block diagram of stopwatch timer

The stopwatch timer can be used as a separate timer from the clock timer. In particular, digital watch stopwatch functions can be realized easily with software.

4.8.2 Controlling clock manager

The clock manager generates the stopwatch timer operating clock by dividing the OSC1 clock by 32. Before the stopwatch timer can be run, write "1" to the SWCKE register to supply the operating clock to the stopwatch timer.

Table 4.8.2.1 Controlling stopwatch timer operating clock

SWCKE

1 0

If it is not necessary to run the stopwatch timer, stop the clock supply by setting SWCKE to "0" to reduce current consumption.

Stopwatch timer clock

fOSC1 / 32 (1 kHz)

Off

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4.8.3 Counter and prescaler

The stopwatch timer is conﬁgured of four-bit BCD counters SWD0–3, SWD4–7 and SWD8–11. The counter SWD0–3, at the stage preceding the stopwatch timer, has a 1,000 Hz signal generated by the prescaler for the input clock. It counts up every 1/1,000 sec, and generates 100 Hz signal. The counter SWD4–7 has a 100 Hz signal generated by the counter SWD0–3 for the input clock. It count-up every 1/100 sec, and generated 10 Hz signal. The counter SWD8–11 has an approximated 10 Hz signal generated by the counter SWD4–7 for the input clock. It count-up every 1/10 sec, and generated 1 Hz signal. The prescaler inputs a 1,024 Hz clock dividing f 1,000 Hz counting clock for SWD0–3. To generate a 1,000 Hz clock from 1,024 Hz, 24 pulses from 1,024 pulses that are input to the prescaler every second are taken out. When the counter becomes the value indicated below, one pulse (1,024 Hz) that is input immediately after to the prescaler will be pulled out.

39, 79, 139, 179, 219, 259, 299, 319, 359, 399, 439, 479, 539, 579, 619, 659, 699, 719, 759, 799, 839, 879, 939, 979

Figure 4.8.3.1 shows the operation of the prescaler.

Prescaler input clock (1,024 Hz)

Prescaler output clock

OSC1

(output from the OSC1 oscillation circuit), and outputs

START

Counter data

000 001 002 037 038 039 040 041

Fig. 4.8.3.1 Timing of the prescaler operation

For the above reason, the counting clock is 1,024 Hz (0.9765625 msec) except during pulse correction. Consequently, frequency of the prescaler output clock (1,000 Hz), 100 Hz generated by SWD0–3 and 10 Hz generated by SWD4–7 are approximate values.

4.8.4 Capture buffer and hold function

The stopwatch data, 1/1,000 sec, 1/100 sec and 1/10 sec, can be read from SWD0–3 (FF4BH), SWD4– 7 (FF4CH) and SWD8–11 (FF4DH), respectively. The counter data are latched in the capture buffer when reading, and are held until reading of three words is completed. For this reason, correct data can be read even when a carry from lower digits occurs during reading the three words. Further, three counter data are latched in the capture buffer at the same time when SWD0–3 (1/1,000 sec) is read. The data hold is released when SWD8–11 (1/10 sec) reading is completed. Therefore, data should be read in order of SWD0–3 → SWD4–7 → SWD8–11. If SWD4–7 or SWD8–11 is ﬁrst read when data have not been held, the hold function does not work and data in the counter is directly read out. When data that has not been held is read in the stopwatch timer RUN status, you cannot judge whether it is correct or not.

The stopwatch timer has a LAP function using an external key input (explained later). The capture buffer is also used to hold LAP data. In this case, data is held until SWD8–11 is read. However, when a LAP input is performed before completing the reading, the content of the capture buffer is renewed at that point. Remaining data that have not been read become invalid by the renewal, and the hold status is not released if SWD8–11 is read. When SWD8–11 is read after the capture buffer is updated, the capture renewal ﬂag CRNWF is set to "1" at that point. In this case, it is necessary to read from SWD0–3 again. The capture renewal ﬂag is renewed by reading SWD8–11.

Figure 4.8.4.1 shows the timing for data holding and reading.

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Direct LAP input (P11/P10)

Direct LAP internal signal

Capture renewal flag CRNWF

SWD0–3 reading

SWD4–7 reading

SWD8–11 reading

Data holding

Fig. 4.8.4.1 Timing for data holding and reading

4.8.5 Stopwatch timer RUN/STOP and reset

RUN/STOP control and reset of the stopwatch timer can be done by the software.

Stopwatch timer RUN/STOP

The stopwatch timer enters the RUN status when "1" is written to SWRUN, and the STOP status when "0" is written. In the STOP status, the timer data is maintained until the next RUN status or resets timer. Also, when the STOP status changes to the RUN status, the data that was maintained can be used for resuming the count. The RUN/STOP operation of the stopwatch timer by writing to the SWRUN register is performed in synchronization with the falling edge of the 1,024 Hz same as the prescaler input clock. The SWRUN register can be read, and in this case it indicates the operating status of the stopwatch timer. Figure 4.8.5.1 shows the operating timing when controlling the SWRUN register.

fOSC1/32 (1,024 Hz)

SWRUN writing

SWRUN register

Count clock

Fig. 4.8.5.1 Operating timing when controlling SWRUN

When the direct input function (explained in next section) is set, RUN/STOP control is done by an external key input. In this case, SWRUN becomes read only register that indicates the operating status of the stopwatch timer.

Stopwatch timer reset

The stopwatch timer is reset when "1" is written to SWRST. With this, the counter value is cleared to "000". Since this resetting does not affect the capture buffer, data that has been held in the capture buffer is not cleared and is maintained as is. When the stopwatch timer is reset in the RUN status, counting restarts from count "000". Also, in the STOP status the reset data "000" is maintained until the next RUN.

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4.8.6 Direct input function and key mask

The stopwatch timer has a direct input function that can control the RUN/STOP and LAP operation of the stopwatch timer by external key input. This function is set by writing "1" to the EDIR register. When EDIR is set to "0", only the software control is possible as explained in the previous section.

Input port conﬁguration

In the direct input function, the input ports P10 and P11 are used as the RUN/STOP and LAP input ports. The key assignment can be selected using the SWDIR register.

Table 4.8.6.1 RUN/STOP and LAP input ports

SWDIR

0 1

Direct RUN

When the direct input function is selected, RUN/STOP operation of the stopwatch timer can be controlled by using the key connected to the input port P10/P11 (selected by SWDIR). P10/P11 works as a normal input port, but the input signal is sent to the stopwatch control circuit. The key input signal from the P10/P11 port works as a toggle switch. When it is input in STOP status, the stopwatch timer runs, and in RUN status, the stopwatch timer stops. RUN/STOP status of the stopwatch timer can be checked by reading the SWRUN register. An interrupt is generated by direct RUN input. The sampling for key input signal is performed at the falling edge of 1,024 Hz signal same as the SWRUN control. The chattering judgment is performed at the point where the key turns off, and a chattering less than 46.8–62.5 msec is removed. Therefore, more time is needed for an interval between RUN and STOP key inputs. Figure 4.8.6.1 shows the operating timing for the direct RUN input.

P10

RUN/STOP

LAP

P11

LAP

RUN/STOP

fOSC1/32 (1,024 Hz)

Direct RUN input (P10/P11)

Direct RUN internal signal

SWRUN register

Count clock

Direct RUN interrupt

Fig. 4.8.6.1 Operating timing for direct RUN input

Direct LAP

Control for the LAP can also be done by key input same as the direct RUN. When the direct input function is selected, the input port P11/P10 (selected by SWDIR) becomes the LAP key input port. Sampling for the input signal and the chattering judgment are the same as a direct RUN. By entering the LAP key, the counter data at that point is latched into the capture buffer and is held. The counter continues counting operation. Furthermore, an interrupt occurs by direct LAP input. As stated above, the capture buffer data is held until SWD8–11 is read. If the LAP key is input when data has been already held, it renews the content of the capture buffer. When SWD8–11 is read after renewing, the capture renewal ﬂag is set to "1". In this case, the hold status is not released by reading SWD8–11, and it continues. Normally the LAP data should be read after the interrupt is generated. After that, be sure to check the capture renewal ﬂag. When the capture renewal ﬂag is set, renewed data is held in the capture buffer. So it is necessary to read from SWD0–3 again.

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The stopwatch timer sets the 1 Hz interrupt factor ﬂag ISW1 to "1" when requiring a carry-up to 1-sec digit by an SWD8–11 overﬂow. If the capture buffer shifts into hold status (when SWD0–3 is read or when LAP is input) while the 1 Hz interrupt factor ﬂag ISW1 is set to "1", the lap data carry-up request ﬂag LCURF is set to "1" to indicate that a carry-up to 1-sec digit is required for the processing of LAP input. In normal software processing, LAP processing may take precedence over 1-sec or higher digits processing by a 1 Hz interrupt, therefore carry-up processing using this ﬂag should be used for time display in the LAP processing to prevent the 1-sec digit data decreasing by 1 second. This ﬂag is renewed when the capture buffer shifts into hold status. Figure 4.8.6.2 shows the operating timing for the direct LAP input, and Figure 4.8.6.3 shows the timings for data holding and reading during a direct LAP input and reading.

fOSC1/32 (1,024 Hz)

Direct LAP input (P11/P10)

Direct LAP internal signal

Data holding

SWD8–11 reading

Direct LAP interrupt

Fig. 4.8.6.2 Operating timing for direct LAP input

Direct LAP input (P11/P10)

Capture renewal flag CRNWF

SWD0–3 reading

SWD4–7 reading

SWD8–11 reading

Data holding

1 Hz interrupt factor flag ISW1

Lap data carry-up request flag LCURF

Counter data

999 000

Fig. 4.8.6.3 Timing for data holding and reading during direct LAP input

Key mask

In stopwatch applications, some functions may be controlled by a combination of keys including direct RUN or direct LAP. For instance, the RUN key can be used for other functions, such as reset and setting a watch, by pressing the RUN key with another key. In this case, the direct RUN function or direct LAP function must be invalid so that it does not function. For this purpose, the key mask function is set so that it judges concurrence of input keys and invalidates RUN and LAP functions. A combination of the key inputs for this judgment can be selected using the DKM0–DKM2 registers.

Table 4.8.6.2 Key mask selection

DKM2

DKM1

DKM0

Mask key combination

None (at initial reset)

P12

P12, P13

P12, P13, P40

P40

P40, P41

P40, P41, P42

P40, P41, P42, P43

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RUN or LAP inputs become invalid in the following status.

1. The RUN or LAP key is pressed when one or more keys that are included in the selected combination (here in after referred to as mask) are held down.

2. The RUN or LAP key has been pressed when the mask is released.

fOSC1/32 (1,024 Hz)

Direct RUN/LAP input

Key mask

valid

invalid

Fig. 4.8.6.4 Operation of key mask

RUN or LAP inputs become valid in the following status.

1. Either the RUN or LAP key is pressed independently if no other key is been held down.

2. Both the RUN and LAP keys are pressed at the same time if no other key is held down. (RUN and LAP functions are effective.)

3. The RUN or LAP key is pressed if either is held down. (RUN and LAP functions are effective.)

4. Either the RUN or LAP key and the mask key are pressed at the same time if no other key is held down.

5. Both the RUN and LAP keys and the mask key are pressed at the same time if no other key is held down. (RUN and LAP functions are effective.)

Simultaneous key input is referred to as two or more key inputs are sampled at the same falling

edge of 1,024 Hz clock.

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4.8.7 Interrupt function

10 Hz interrupt request

1 Hz interrupt request

FF4DH

(1/10 sec BCD)

FF4CH

(1/100 sec BCD)

Address Register Stopwatch timer (SWD0–3) timing chart

FF4BH

(1/1,000 sec BCD)

Address Register Stopwatch timer (SWD4–7) timing chart

Address Register Stopwatch timer (SWD8–11) timing chart

10 Hz and 1 Hz interrupts

The 10 Hz and 1 Hz interrupts can be generated through the overﬂow of stopwatch timers SWD4–7 and SWD8–11 respectively. Also, software can set whether to separately mask the frequencies described earlier. Figure 4.8.7.1 is the timing chart for the counters.

SIC63616-(Rev. 1.0) NO. P90

As shown in Figure 4.8.7.1, the interrupts are generated by the overﬂow of their respective counters ("9" changing to "0"). Also, at this time the corresponding interrupt factor ﬂag (ISW10, ISW1) is set to "1". The respective interrupts can be masked separately through the interrupt mask registers (EISW10, EISW1). However, regardless of the setting of the interrupt mask registers, the interrupt factor ﬂags are set to "1" by the overﬂow of their corresponding counters.

Fig. 4.8.7.1 Timing chart for counters

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OSC1

/32 (1,024 Hz)

SWRST writing

EDIR writing

EDIR register

Direct RUN input

SWRUN writing

SWRUN register

Direct LAP input

Counter data

Capture buffer

SWD0–3 reading

SWD4–7 reading

SWD8–11 reading

CRNWF

1 Hz interrupt factor flag ISW1

LCURF

Direct RUN interrupt

Direct LAP interrupt

10 Hz interrupt

1 Hz interrupt

001 002 003 004 005 006 098 099 100 101 102 000 001 002 003 004 005 006 007 993 994000 995 996 997 998 999 000 001 002 003 004 005 006 007

003 005 995 001 006

Direct RUN and direct LAP interrupts

When the direct input function is selected, the direct RUN and direct LAP interrupts can be generated. The respective interrupts occur at the rising edge of the internal signal for direct RUN and direct LAP after sampling the direct input signal in the falling edge of 1,024 Hz signal. Also, at this time the corresponding interrupt factor ﬂag (IRUN, ILAP) is set to "1". The respective interrupts can be masked separately through the interrupt mask registers (EIRUN, EILAP). However, regardless of the setting of the interrupt mask registers, the interrupt factor ﬂags are set to "1" by the inputs of the RUN and LAP.

The direct RUN and LAP functions use the P10 and P11 ports. Therefore, the direct input interrupt and the P10–P13 inputs interrupt may generate at the same time depending on the interrupt condition setting for the input port P10–P13. Consequently, when using the direct input interrupt, set the interrupt select registers SIP10 and SIP11 to "0" so that the input interrupt does not generate by P10 and P11 inputs.

Fig. 4.8.7.2 Timing chart for stopwatch timer

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4.8.8 I/O memory of stopwatch timer

D3 D2 D1 D0 Name Init

∗1

1 0

Address Comment

FF16H

MDCKE SGCKE SWCKE RTCKE

R/W

MDCKE SGCKE

SWCKE

RTCKE

0 0 0 0

Enable Enable Enable Enable

Disable Disable Disable Disable

Integer multiplier clock enable

Sound generator clock enable

Stopwatch timer clock enable

Clock timer clock enable

None1P122P12–133P12–13,40

[DKM2–0] Key mask

P405P40–416P40–427P40–43

[DKM2–0] Key mask

Unused

Key mask

selection

FF48H

R R/W

FF49H

0 DKM2 DKM1 DKM0

∗

DKM2 DKM1 DKM0

–

∗

0 0 0

R/W WR

FF4AH

LCURF CRNWF SWRUN SWRST

LCURF CRNWF SWRUN

SWRST

∗

0 0 0

Reset

Request Renewal

Run

Reset

No No

Stop

Invalid

Lap data carry-up request flag

Capture renewal flag

Stopwatch timer Run/Stop

Stopwatch timer reset (writing)

SWD7 SWD6 SWD5 SWD4

0 0 0 0

Stopwatch timer data

BCD (1/100 sec)

FF4CH

SWD7 SWD6 SWD5 SWD4

SWD11 SWD10

SWD9 SWD8

0 0 0 0

Stopwatch timer data

BCD (1/10 sec)

FF4DH

SWD11 SWD10 SWD9 SWD8

FF4BH

SWD3 SWD2 SWD1 SWD0

0 0 0 0

Stopwatch timer data

BCD (1/1000 sec)

0 0 SWDIR EDIR

R R/W

∗

SWDIR

EDIR

–

∗

–

∗

0 Enable Disable

Unused

Stopwatch direct input switch

0: P10=Run/Stop, P11=Lap 1: P10=Lap, P11=Run/Stop

Direct input enable

FFEDH

EIRUN EILAP EISW1 EISW10

R/W

EIRUN

EILAP

EISW1 EISW10

0 0 0 0

Enable Enable Enable Enable

Mask Mask Mask Mask

Interrupt mask register (Stopwatch direct RUN)

Interrupt mask register (Stopwatch direct LAP)

Interrupt mask register (Stopwatch timer 1 Hz)

Interrupt mask register (Stopwatch timer 10 Hz)

FFFDH

IRUN ILAP ISW1 ISW10

R/W

IRUN ILAP ISW1

ISW10

0 0 0 0

(R) Yes (W)

Reset

(R) No

(W)

Invalid

Interrupt factor flag (Stopwatch direct RUN)

Interrupt factor flag (Stopwatch direct LAP)

Interrupt factor flag (Stopwatch timer 1 Hz)

Interrupt factor flag (Stopwatch timer 10 Hz)

Table 4.8.8.1 shows the I/O addresses and the control bits for the stopwatch timer.

Table 4.8.8.1 Control bits of stopwatch timer

SIC63616-(Rev. 1.0) NO. P92

*1 Initial value at initial reset

*2 Not set in the circuit

*3 Constantly "0" when being read

SWCKE: Stopwatch timer clock enable register (FF16H•D1)

Controls the operating clock supply to the stopwatch timer.

When "1" is written: On When "0" is written: Off

When "1" is written to SWCKE, the stopwatch timer operating clock is supplied from the clock manager. If it is not necessary to run the stopwatch timer, stop the clock supply by setting SWCKE to "0" to reduce current consumption. At initial reset, this register is set to "0".

Reading: Valid

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SIC63616-(Rev. 1.0) NO. P93

EDIR: Direct input function enable register (FF48H•D0)

Enables the direct input (RUN/LAP) function.

When "1" is written: Enabled When "0" is written: Disabled

Reading: Valid

The direct input function is enabled by writing "1" to EDIR, and then RUN/STOP and LAP control can be done by external key input. When "0" is written, the direct input function is disabled, and the stopwatch timer is controlled by the software only. Further the function switching is actually done by synchronizing with the falling edge of f

OSC1

/32 (1,024 Hz) after the data is written to this register (after 977 µsec maximum). At initial reset, this register is set to "0".

SWDIR: Direct input switch register (FF48H•D1)

Switches the direct-input key assignment for the P10 and P11 ports.

When "1" is written: P10 = LAP, P11 = RUN/STOP When "0" is written: P10 = RUN/STOP, P11 = LAP

Reading: Valid

The direct-input key assignment is selected using this register. The P10 and P11 port statuses are input to the stopwatch timer as the RUN/STOP and LAP inputs according to this selection. At initial reset, this register is set to "0".

DKM0–DKM2: Direct key mask select register (FF49H•D0–D2)

Selects a combination of the key inputs for concurrence judgment with RUN and LAP inputs when the direct input function is set.

Table 4.8.8.2 Key mask selection

DKM2

DKM1

DKM0

Mask key combination

None (at initial reset)

P12

P12, P13

P12, P13, P40

P40

P40, P41

P40, P41, P42

P40, P41, P42, P43

When the concurrence is detected, RUN and LAP inputs cannot be accepted until the concurrence is released. At initial reset, this register is set to "0".

SWRST: Stopwatch timer reset (FF4AH•D0)

This bit resets the stopwatch timer.

When "1" is written: Stopwatch timer reset When "0" is written: No operation

Reading: Always "0"

The stopwatch timer is reset when "1" is written to SWRST. When the stopwatch timer is reset in the RUN status, operation restarts immediately. Also, in the STOP status the reset data is maintained. Since this reset does not affect the capture buffer, the capture buffer data in hold status is not cleared and is maintained. This bit is write-only, and is always "0" at reading.

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