Epson S1C63558 User Manual

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MF1153-03

CMOS 4-BIT SINGLE CHIP MICROCOMPUTER

S1C63558

Technical Manual

S1C63558 Technical Hardware

NOTICE

No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no representation that this material is applicable to products requiring high level reliability, such as medical products. Moreover, no license to any intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright infringement of a third party. This material or portions thereof may contain technology or the subject relating to strategic products under the control of the Foreign Exchange and Foreign Trade Law of Japan and may require an export license from the Ministry of International Trade and Industry or other approval from another government agency.

Revisions and Additions for this manual

Chapter

Section

2.1.2

4.7.3

Page

Item

Table 2.1.2.1 LCD drive voltage when generated internally Table 4.7.3.1 LCD drive voltage when generated internally

Contents

The table was revised.

The information of the product number change

Starting April 1, 2001, the product number has been changed as listed below. Please use the new product number when you place an order. For further information, please contact Epson sales representative.

Configuration of product number

Devices

S1 C 63158 F 0A01

Development tools

S5U1

∗1: For details about tool types, see the tables below. (In some manuals, tool types are represented by one digit.) ∗2: Actual versions are not written in the manuals.

C 63000 A1 1

Packing specification Specification Package (D: die form; F: QFP) Model number Model name (C: microcomputer, digital products) Product classification (S1: semiconductor)

Packing specification Version (1: Version 1 ∗2) Tool type (A1: Assembler Package ∗1) Corresponding model number (63000: common to S1C63 Family) Tool classification (C: microcomputer use) Product classification (S5U1: development tool for semiconductor products)

Comparison table between new and previous number

S1C63 Family processors

Previous No.

E0C63158 E0C63256 E0C63358 E0C63P366 E0C63404 E0C63406 E0C63408 E0C63F408 E0C63454 E0C63455 E0C63458 E0C63466 E0C63P466

New No.

S1C63158 S1C63256 S1C63358 S1C6P366 S1C63404 S1C63406 S1C63408 S1C6F408 S1C63454 S1C63455 S1C63458 S1C63466 S1C6P466

Previous No.

E0C63467 E0C63557 E0C63558 E0C63567 E0C63F567 E0C63658 E0C63666 E0C63F666 E0C63A08 E0C63B07 E0C63B08 E0C63B58

New No.

S1C63467 S1C63557 S1C63558 S1C63567 S1C6F567 S1C63658 S1C63666 S1C6F666 S1C63A08 S1C63B07 S1C63B08 S1C63B58

S1C63 Family peripheral products

Previous No.

E0C5250 E0C5251

New No.

S1C05250 S1C05251

Comparison table between new and previous number of development tools

Development tools for the S1C63 Family Development tools for the S1C63/88 Family

Previous No.

ADP63366 ADP63466 ASM63 GAM63001 ICE63 PRC63001 PRC63002 PRC63004 PRC63005 PRC63006 PRC63007 URS63366

New No.

S5U1C63366X S5U1C63466X S5U1C63000A S5U1C63000G S5U1C63000H1 S5U1C63001P S5U1C63002P S5U1C63004P S5U1C63005P S5U1C63006P S5U1C63007P S5U1C63366Y

Previous No.

ADS00002 GWH00002 URM00002

New No.

S5U1C88000X1 S5U1C88000W2 S5U1C88000W1

CONTENTS

CHAPTER

1OUTLINE ________________________________________________ 1

1.1 Features ........................................................................................................ 1

1.2 Block Diagram ..............................................................................................2

1.3 Pin Layout Diagram ..................................................................................... 3

1.4 Pin Description .............................................................................................4

1.5 Mask Option.................................................................................................. 5

CHAPTER 2POWER SUPPLY AND INITIAL RESET ____________________________ 8

2.1 Power Supply ................................................................................................ 8

2.1.1 Voltage <VD1> for oscillation circuit and internal circuits...................... 8

2.1.2 Voltage <VC1–VC5> for LCD driving ........................................................ 8

2.2 Initial Reset ...................................................................................................9

2.2.1 Reset terminal (RESET) ............................................................................. 9

2.2.2 Simultaneous low input to terminals K00–K03 ........................................ 10

2.2.3 Internal register at initial resetting .......................................................... 10

2.2.4 Terminal settings at initial resetting ......................................................... 11

2.3 Test Terminal (TEST) ................................................................................... 11

CHAPTER 3 CPU, ROM, RAM________________________________________ 12

3.1 CPU..............................................................................................................12

3.2 Code ROM ................................................................................................... 12

3.3 RAM .............................................................................................................12

3.4 Data ROM .................................................................................................... 13

CHAPTER 4PERIPHERAL CIRCUITS AND OPERATION__________________________ 14

4.1 Memory Map................................................................................................ 14

4.2 Watchdog Timer ........................................................................................... 23

4.2.1 Configuration of watchdog timer.............................................................. 23

4.2.2 Interrupt function ...................................................................................... 23

4.2.3 I/O memory of watchdog timer ................................................................. 24

4.2.4 Programming notes................................................................................... 24

4.3 Oscillation Circuit ....................................................................................... 25

4.3.1 Configuration of oscillation circuit .......................................................... 25

4.3.2 OSC1 oscillation circuit............................................................................ 25

4.3.3 OSC3 oscillation circuit............................................................................ 26

4.3.4 Switching the CPU operating clock.......................................................... 26

4.3.5 Clock frequency and instruction execution time ...................................... 26

4.3.6 I/O memory of oscillation circuit.............................................................. 27

4.3.7 Programming notes................................................................................... 27

4.4 Input Ports (K00–K03 and K10–K13).........................................................28

4.4.1 Configuration of input ports ..................................................................... 28

4.4.2 Interrupt function ...................................................................................... 28

4.4.3 Mask option ............................................................................................... 29

4.4.4 I/O memory of input ports......................................................................... 30

4.4.5 Programming notes................................................................................... 32

4.5 Output Ports (R00–R03, R10–R13 and R20–R23)...................................... 33

4.5.1 Configuration of output ports ................................................................... 33

4.5.2 Mask option ............................................................................................... 33

S1C63558 TECHNICAL MANUAL EPSON i

CONTENTS

4.5.3 High impedance control............................................................................ 34

4.5.4 Special output ............................................................................................ 34

4.5.5 I/O memory of output ports....................................................................... 37

4.5.6 Programming notes................................................................................... 40

4.6 I/O Ports (P00–P03, P10–P13, P20–P23 and P30–P33) .......................... 41

4.6.1 Configuration of I/O ports ........................................................................ 41

4.6.2 Mask option ............................................................................................... 42

4.6.3 I/O control registers and input/output mode ............................................ 42

4.6.4 Pull-up during input mode ........................................................................ 42

4.6.5 Special outputs (CL, FR)........................................................................... 43

4.6.6 I/O memory of I/O ports............................................................................ 44

4.6.7 Programming notes................................................................................... 48

4.7 LCD Driver (COM0–COM16, SEG0–SEG39) ........................................... 49

4.7.1 Configuration of LCD driver .................................................................... 49

4.7.2 Mask option ............................................................................................... 49

4.7.3 Power supply for LCD driving.................................................................. 49

4.7.4 LCD display control (ON/OFF) and switching of duty............................ 49

4.7.5 Display memory......................................................................................... 51

4.7.6 LCD contrast adjustment .......................................................................... 53

4.7.7 I/O memory of LCD driver........................................................................ 54

4.7.8 Programming notes................................................................................... 56

4.8 Clock Timer.................................................................................................. 57

4.8.1 Configuration of clock timer..................................................................... 57

4.8.2 Data reading and hold function................................................................ 57

4.8.3 Interrupt function ...................................................................................... 58

4.8.4 I/O memory of clock timer ........................................................................ 59

4.8.5 Programming notes................................................................................... 60

4.9 Stopwatch T imer .......................................................................................... 61

4.9.1 Configuration of stopwatch timer ............................................................. 61

4.9.2 Count-up pattern ....................................................................................... 61

4.9.3 Interrupt function ...................................................................................... 62

4.9.4 I/O memory of stopwatch timer ................................................................ 63

4.9.5 Programming notes................................................................................... 64

4.10 Programmable Timer................................................................................... 65

4.10.1 Configuration of programmable timer ................................................... 65

4.10.2 Setting of initial value and counting down ............................................. 66

4.10.3 Counter mode .......................................................................................... 67

4.10.4 Setting of input clock in timer mode ....................................................... 68

4.10.5 Interrupt function .................................................................................... 69

4.10.6 Setting of TOUT output ........................................................................... 69

4.10.7 Transfer rate setting for serial interface ................................................ 70

4.10.8 I/O memory of programmable timer....................................................... 71

4.10.9 Programming notes................................................................................. 76

4.11 Serial Interface ............................................................................................77

4.11.1 Configuration of serial interface ............................................................ 77

4.11.2 Mask option ............................................................................................. 78

4.11.3 Transfer modes ........................................................................................ 78

4.11.4 Clock source ............................................................................................ 80

4.11.5 Transmit-receive control ......................................................................... 81

4.11.6 Operation of clock synchronous transfer................................................ 82

4.11.7 Operation of asynchronous transfer ....................................................... 86

4.11.8 Interrupt function .................................................................................... 90

4.11.9 I/O memory of serial interface ................................................................ 92

4.11.10 Programming notes ............................................................................... 99

4.12 Sound Generator......................................................................................... 100

4.12.1 Configuration of sound generator ......................................................... 100

4.12.2 Buzzer output circuit .............................................................................. 100

ii EPSON S1C63558 TECHNICAL MANUAL

CONTENTS

4.12.3 Control of buzzer output......................................................................... 101

4.12.4 Setting of buzzer frequency and sound level.......................................... 102

4.12.5 Digital envelope ..................................................................................... 103

4.12.6 One-shot output ...................................................................................... 104

4.12.7 I/O memory of sound generator............................................................. 105

4.12.8 Programming notes................................................................................ 108

4.13 SVD (Supply Voltage Detection) Circuit .................................................... 109

4.13.1 Configuration of SVD circuit ................................................................. 109

4.13.2 Mask option ............................................................................................ 109

4.13.3 SVD operation ........................................................................................ 109

4.13.4 I/O memory of SVD circuit..................................................................... 110

4.13.5 Programming notes................................................................................ 111

4.14 Telephone Function (Tone/Pulse Dialer) ................................................... 112

4.14.1 Configuration of tone/pulse dialer ........................................................ 112

4.14.2 Mask option ............................................................................................ 113

4.14.3 Operation of telephone function ............................................................ 113

4.14.4 Tone mode (DTMF) ................................................................................ 116

4.14.5 Pulse mode (DP) .................................................................................... 119

4.14.6 Pause ...................................................................................................... 122

4.14.7 Flash ....................................................................................................... 124

4.14.8 Hold-line................................................................................................. 125

4.14.9 Interrupt.................................................................................................. 126

4.14.10 I/O memory of telephone function ....................................................... 127

4.14.11 Programming notes .............................................................................. 135

4.15 FSK Demodulator .......................................................................................136

4.15.1 Configuration of FSK demodulator ....................................................... 136

4.15.2 Mask option ............................................................................................ 138

4.15.3 Ring/carrier detection and interrupt ..................................................... 139

4.15.4 Inputting FSK data ................................................................................. 140

4.15.5 I/O memory of FSK demodulator .......................................................... 142

4.15.6 Programming notes................................................................................ 144

4.16 Interrupt and HALT .................................................................................... 145

4.16.1 Interrupt factor....................................................................................... 147

4.16.2 Interrupt mask ........................................................................................ 148

4.16.3 Interrupt vector ...................................................................................... 148

4.16.4 I/O memory of interrupt ......................................................................... 149

4.16.5 Programming notes................................................................................ 151

CHAPTER 5SUMMARY OF NOTES ______________________________________ 152

5.1 Notes for Low Current Consumption.......................................................... 152

5.2 Summary of Notes by Function...................................................................153

5.3 Precautions on Mounting ........................................................................... 157

CHAPTER 6BASIC EXTERNAL WIRING DIAGRAM ___________________________ 159 CHAPTER 7ELECTRICAL CHARACTERISTICS _______________________________ 160

7.1 Absolute Maximum Rating..........................................................................160

7.2 Recommended Operating Conditions......................................................... 160

7.3 DC Characteristics ..................................................................................... 161

7.4 Analog Circuit Characteristics and Power Current Consumption............ 162

7.5 Oscillation Characteristics......................................................................... 163

7.6 Serial Interface (1), (2) AC Characteristics...............................................164

7.7 FSK Demodulator Characteristics .............................................................165

S1C63558 TECHNICAL MANUAL EPSON iii

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7.8 Telephone Function Characteristics...........................................................166

7.9 Timing Chart............................................................................................... 166

7.10 Characteristic Curves (reference value) .................................................... 167

CHAPTER 8PACKAGE _______________________________________________ 169

8.1 Plastic Package...........................................................................................169

8.2 Ceramic Package for Test Samples ............................................................170

CHAPTER 9PAD LAYOUT ____________________________________________ 171

9.1 Diagram of Pad Layout .............................................................................. 171

9.2 Pad Coordinates ......................................................................................... 172

iv EPSON S1C63558 TECHNICAL MANUAL

CHAPTER 1: OUTLINE

CHAPTER 1OUTLINE

The S1C63558 is a microcomputer which has a high-performance 4-bit CPU S1C63000 as the core

CPU, ROM (8,192 words × 13 bits), RAM (5,120 words × 4 bits), serial interface, watchdog timer, programmable timer, time base counters (2 systems), SVD circuit, a dot-matrix LCD driver that can drive a maximum 40 segments × 17 commons, DTMF/DP generator, FSK demodulator and sound generator built-in. The S1C63558 features high speed operation and low current consumption in an operating voltage range (2.2 V to 5.5 V), this makes it suitable for applications working with batteries. It is also suitable for caller ID and portable data bank systems because it has a large capacity of RAM built-in.

1.1 Features

OSC1 oscillation circuit ......................

OSC3 oscillation circuit ...................... 3.58 MHz (Typ.) ceramic oscillation circuit

Instruction set ..................................... Basic instruction: 46 types (411 instructions with all)

Instruction execution time................... During operation at 32.768 kHz: 61 µsec 122 µsec 183 µsec

ROM capacity ..................................... Code ROM: 8,192 words × 13 bits

RAM capacity...................................... Data memory: 5,120 words × 4 bits

Input port............................................. 8 bits (Pull-up resistors may be supplemented ∗1)

Output port .......................................... 12 bits (It is possible to switch the 8 bits to special output ∗2)

I/O port ................................................ 16 bits (It is possible to switch the 2 bits to special output and

Serial interface .................................... 2 ch.

LCD driver...........................................

Time base counter .............................. 2 systems (Clock timer, stopwatch timer)

Programmable timer ........................... Built-in, 2 inputs × 8 bits, with event counter function

Watchdog timer................................... Built-in

DTMF generator ................................. Built-in

DP generator ...................................... Built-in

FSK demodulator ................................ Built-in (Compatible with ITU-T V.23/Bell 202)

Sound generator ................................. With envelope and 1-shot output functions

Supply voltage detection (SVD) circuit ..

External interrupt ................................ Input port interrupt: 2 systems

Internal interrupt ................................. Clock timer interrupt: 4 systems

Power supply voltage ......................... 2.2 V to 5.5 V

Operating temperature range ............. -20°C to 70°C

Current consumption (Typ.) ................ Low-speed operation (OSC1: crystal oscillation):

Package .............................................. QFP15-128pin (plastic) or chip

32.768 kHz (Typ.) crystal oscillation circuit

Addressing mode: 8 types

During operation at 3.58 MHz: 0.56 µsec 1.12 µsec 1.68 µsec

Data ROM: 2,048 words × 4 bits (= 8K bits)

Display memory: 816 bits (192 words × 4 bits + 48 × 1 bit)

the 4 bits to serial I/F input/output ∗2) (8-bit clock synchronous or asynchronous system is selectable)

40 segments × 8, 16 or 17 commons (∗2)/48 segments × 8 commons (∗1)

12 values, programmable (2.20 V to 3.30 V) (It is possible to switch 1 value to the external voltage detection ∗1)

Stopwatch timer interrupt: 2 systems Programmable timer interrupt: 2 systems Serial interface interrupt: 6 systems Dialer interrupt: 1 system FSK interrupt: 2 systems

During HALT (32 kHz) 3.0 V (LCD power OFF) 1.5 µA

3.0 V (LCD power ON) 4 µA During operation (32 kHz) 3.0 V (LCD power ON) 10 µA High-speed operation (OSC3: ceramic oscillation): During operation (3.58 MHz) 3.0 V (LCD power ON) 600 µA During FSK operation 5.5 V (LCD power ON) 1,800 µA

∗1: Can be selected with mask option ∗2: Can be selected with software

S1C63558 TECHNICAL MANUAL EPSON 1

CHAPTER 1: OUTLINE

1.2 Block Diagram

OSC1 OSC2 OSC3 OSC4

COM0–7

SEG0–39

(SEG47–40∗1) COM8–16

VDD

VC1–5

CA–CC

VD1 VSS

SVD

ROM

8,192 words × 13 bits

OSC

RAM

5,120 words × 4 bits

Data ROM

2,048 words × 4 bits

LCD Driver

40 SEG × 17 COM

Power

Controller

SVD

System Reset

Core CPU S1C63000

Control

Interrupt

Generator

Stopwatch

Timer

Clock Timer

Programmable

Timer/Counter

Input Port

Output Port

RESET

K00–K03 K10–K13

TEST

R00–R03 R10–R13 R20–R23

TONE

AVDD

AVSS

TIP

RING

BPOUT

CDIN RDIN

RDRC

VREF

Telephone

Function

Demodulator

∗1: Mask option

FSK

Fig. 1.2.1 Block diagram

Sound

Generator

I/O Port

Serial

Interface (1)

Serial

Interface (2)

P00–P03 P10–P13 P20–P23 P30–P33

2 EPSON S1C63558 TECHNICAL MANUAL

1.3 Pin Layout Diagram

QFP15-128pin

CHAPTER 1: OUTLINE

6596

No.

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

128

Pin name

N.C. SEG34 SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10

SEG9 SEG8 SEG7 SEG6 SEG5

N.C.

S1C63558

INDEX

No.

Pin name

SEG4

SEG3

SEG2

SEG1

SEG0

COM7

COM6

COM5

COM4

COM3

COM2

COM1

COM0

VSS

OSC1

OSC2

VD1

OSC3

OSC4

VDD

RESET

TEST

TONE 56 57

R23

R22

R21

R20

R13

R12

R11

N.C.

Fig. 1.3.1 Pin layout diagram

No.

65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96

Pin name

BPOUT

RDRC

N.C.

R10 R03 R02 R01 R00

CDIN

RDIN

VREF

AVSS

RING

TIP

AVDD

P33 P32 P31 P30 P23 P22 P21 P20 P13 P12 P11 P10 P03 P02 P01

N.C.

321

No.

97 98

99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115

COM8/SEG47

116

COM9/SEG47

117

COM10/SEG46

118

COM11/SEG45

119

COM12/SEG44

120

COM13/SEG43

121

COM14/SEG42

122

COM15/SEG41

123

COM16/SEG40 124 125 126 127 128

N.C. : No Connection∗1: Mask option

Pin name

N.C.

P00 K13 K12 K11 K10 K03 K02 K01 K00

SVD

VC1

VC23

VC4 VC5

CC CB CA

∗1 ∗1

∗1 ∗1 ∗1 ∗1 ∗1 ∗1 ∗1

SEG39 SEG38 SEG37 SEG36 SEG35

S1C63558 TECHNICAL MANUAL EPSON 3

CHAPTER 1: OUTLINE

1.4 Pin Description

Pin name

VC1–V

CA–CC OSC1 OSC2 OSC3 OSC4 K00–K03 K10–K13 P00–P03 P10–P13 P20 P21 P22 P23 P30–P33 R00 R01 R02 R03 R10 R11 R12 R13 R20–R23 COM0–COM7 COM8–COM16 (SEG47–SEG40) SEG0–SEG39 SVD DP TONE RESET TEST AV

RDIN TIP RING FB BPOUT CDIN RDRC V

REF

Pin No.

52 46

49 108–111 114–112

51 106–103

102–99

98, 95–93

92–89

84–81

60–57 45–38

115–123

37–33, 31–2, 128–124

107

Table 1.4.1 Pin description

I/O

Power (+) supply pin

–

Power (–) supply pin

–

Oscillation system regulated voltage output pin

–

LCD system power supply pin (1/4 bias generated internally)

–

LCD system boosting/reducing capacitor connecting pin

–

Crystal oscillation input pin

Crystal oscillation output pin

Ceramic oscillation input pin

Ceramic oscillation output pin

Input port

I/O port

I/O

I/O port (switching to serial I/F (1) input/output is possible by software)

I/O

I/O port

I/O

I/O port

I/O

I/O port (switching to CL signal output is possible by software)

I/O

I/O port (switching to FR signal output is possible by software)

I/O

I/O port (switching to serial I/F (2) input/output is possible by software)

I/O

Output port (switching to XBZ signal output is possible by software)

Output port (switching to BZ signal output is possible by software)

Output port (switching to TOUT signal output is possible by software)

Output port (switching to FOUT signal output is possible by software)

Output port (switching to XTMUTE signal output is possible by software)

Output port (switching to XRMUTE signal output is possible by software)

Output port (switching to HDO signal output is possible by software)

Output port (switching to HFO signal output is possible by software)

Output port

LCD common output pin (1/8, 1/16, 1/17 duty can be selected by software)

LCD common output pin

or LCD segment output pin (mask option) LCD segment output pin

SVD external voltage input pin

Dial pulse output pin

DTMF output pin

Initial reset input pin

Testing input pin

Power (+) supply pin for FSK demodulator

–

Power (-) supply pin for FSK demodulator

–

Ring detection input pin

TIP input pin

RING input pin

Input amplifier output pin

Band-pass filter output pin

Carrier detection input pin

I/O pin for connecting RC network

I/O

Reference voltage output pin (1/2 V

Function

)

4 EPSON S1C63558 TECHNICAL MANUAL

CHAPTER 1: OUTLINE

1.5 Mask Option

Mask options shown below are provided for the S1C63558. Several hardware specifications are prepared in each mask option, and one of them can be selected according to the application. The function option generator FOG63558, that has been prepared as the development software tool of S1C63558, is used for this selection. Mask pattern of the IC is finally generated based on the data created by the FOG63558. Refer to the "S5U1C63558D Manual" for the FOG63558.

(1) External reset by simultaneous LOW input to the input port (K00–K03)

This function resets the IC when several keys are pressed simultaneously. The mask option is used to select whether this function is used or not. Further when the function is used, a combination of the input ports (K00–K03), which are connected to the keys to be pressed simultaneously, can be selected. Refer to Section 2.2.2, "Simultaneous low input to terminals K00–K03", for details.

(2) Time authorize circuit for the simultaneous LOW input reset function

When using the external reset function (shown in 1 above), using the time authorize circuit or not can be selected by the mask option. The reset function works only when the input time of simultaneous LOW is more than the rule time if the time authorize circuit is being used. Refer to Section 2.2.2, "Simultaneous low input to terminals K00–K03", for details.

(3) Input port pull-up resistor

The mask option is used to select whether the pull-up resistor is supplemented to the input ports or not. It is possible to select for each bit of the input ports. Refer to Section 4.4.3, "Mask option", for details.

(4) Output specification of the output port

Either complementary output or N-channel open drain output can be selected as the output specification for the output ports. The selection is done in 1-bit units. Refer to Section 4.5.2, "Mask option", for details.

(5) Output specification / pull-up resistor of the I/O ports

Either complementary output or N-channel open drain output can be selected as the output specification when the I/O ports are in the output mode. The selection is done in 1-bit units.

Further, whether or not the pull-up resistors working in the input mode are supplemented can be selected. The selection is done in 1-bit units or 4-bit units depending on the I/O port. 1-bit unit: P20, P21, P22, P23 4-bit unit: P00–P03, P10–P13, P30–P33

Refer to Section 4.6.2, "Mask option", for details.

(6) Configuration of the LCD segment

The COM8–COM16 terminals allow selection of terminal specification between COM outputs and SEG45–SEG40 outputs. Refer to Section 4.7.2, "Mask option", for details.

(7) External voltage detection of SVD circuit

External voltage (SVD terminal–V (V

DD terminal–VSS terminal) detection. The SVD terminal is used to input the external voltage to be

SS terminal) detection can be selected in addition to supply voltage

detected. Refer to Section 4.13.2, "Mask option", for details.

S1C63558 TECHNICAL MANUAL EPSON 5

CHAPTER 1: OUTLINE

(8) Output specification of the DP terminal

Either complementary output or N-channel open drain output can be selected as the output specification for the DP (dial pulse output) terminal. Refer to Section 4.14.2, "Mask option", for details.

(9) Gain of FSK demodulator input amplifier

The gain of the FSK demodulator input amplifier can be either fixed at 1 using the internal feedback resistor or varied using external resistors. Refer to Section 4.15.2, "Mask option", for details.

(10)Output specification of other special output terminals

The following special output terminals are shared with the output (R) terminals or the I/O (P) terminals. Consequently, the output specification (complementary output or N-channel open drain output) of the shared terminal applies to the special output.

Special output signal Shared port

XBZ, BZ, TOUT, FOUT Output ports R00–R03 XRMUTE, XTMUTE, HDO, HFO Output ports R10–R13 Serial interface input/output I/O ports P10–P13 CL, FR I/O ports P22, P23

The following is the option list for the S1C63558. Multiple selections are available in each option item as indicated in the option list. Refer to Chapter 4, "Peripheral Circuits and Operation", to select the specifications that meet the application system. Be sure to select the specifications for unused functions too, according to the instruction provided. Use fog63558 in the S5U1C63000A package for this selection. Refer to the "S5U1C63558D Manual" for details.

1. MULTIPLE KEY ENTRY RESET COMBINATION

■■ 1. Not Use

■■ 2. Use <K00, K01, K02, K03>

■■ 3. Use <K00, K01, K02>

■■ 4. Use <K00, K01>

2. MULTIPLE KEY ENTRY RESET TIME AUTHORIZE

■■ 1. Not Use

■■ 2. Use

3. INPUT PORT PULL UP RESISTOR

• K00 ■■ 1. With Resistor ■■ 2. Gate Direct

• K01 ■■ 1. With Resistor ■■ 2. Gate Direct

• K02 ■■ 1. With Resistor ■■ 2. Gate Direct

• K03 ■■ 1. With Resistor ■■ 2. Gate Direct

• K10 ■■ 1. With Resistor ■■ 2. Gate Direct

• K11 ■■ 1. With Resistor ■■ 2. Gate Direct

• K12 ■■ 1. With Resistor ■■ 2. Gate Direct

• K13 ■■ 1. With Resistor ■■ 2. Gate Direct

4. OUTPUT PORT OUTPUT SPECIFICATION

• R00 ■■ 1. Complementary ■■ 2. Nch-OpenDrain

• R01 ■■ 1. Complementary ■■ 2. Nch-OpenDrain

• R02 ■■ 1. Complementary ■■ 2. Nch-OpenDrain

• R03 ■■ 1. Complementary ■■ 2. Nch-OpenDrain

• R10 ■■ 1. Complementary ■■ 2. Nch-OpenDrain

• R11 ■■ 1. Complementary ■■ 2. Nch-OpenDrain

• R12 ■■ 1. Complementary ■■ 2. Nch-OpenDrain

• R13 ■■ 1. Complementary ■■ 2. Nch-OpenDrain

• R20 ■■ 1. Complementary ■■ 2. Nch-OpenDrain

• R21 ■■ 1. Complementary ■■ 2. Nch-OpenDrain

• R22 ■■ 1. Complementary ■■ 2. Nch-OpenDrain

• R23 ■■ 1. Complementary ■■ 2. Nch-OpenDrain

6 EPSON S1C63558 TECHNICAL MANUAL

5. I/O PORT OUTPUT SPECIFICATION

• P00 ■■ 1. Complementary ■■ 2. Nch-OpenDrain

• P01 ■■ 1. Complementary ■■ 2. Nch-OpenDrain

• P02 ■■ 1. Complementary ■■ 2. Nch-OpenDrain

• P03 ■■ 1. Complementary ■■ 2. Nch-OpenDrain

• P10 ■■ 1. Complementary ■■ 2. Nch-OpenDrain

• P11 ■■ 1. Complementary ■■ 2. Nch-OpenDrain

• P12 ■■ 1. Complementary ■■ 2. Nch-OpenDrain

• P13 ■■ 1. Complementary ■■ 2. Nch-OpenDrain

• P20 ■■ 1. Complementary ■■ 2. Nch-OpenDrain

• P21 ■■ 1. Complementary ■■ 2. Nch-OpenDrain

• P22 ■■ 1. Complementary ■■ 2. Nch-OpenDrain

• P23 ■■ 1. Complementary ■■ 2. Nch-OpenDrain

• P30 ■■ 1. Complementary ■■ 2. Nch-OpenDrain

• P31 ■■ 1. Complementary ■■ 2. Nch-OpenDrain

• P32 ■■ 1. Complementary ■■ 2. Nch-OpenDrain

• P33 ■■ 1. Complementary ■■ 2. Nch-OpenDrain

6. I/O PORT PULL UP RESISTOR

• P0x ■■ 1. With Resistor ■■ 2. Gate Direct

• P1x ■■ 1. With Resistor ■■ 2. Gate Direct

• P20 ■■ 1. With Resistor ■■ 2. Gate Direct

• P21 ■■ 1. With Resistor ■■ 2. Gate Direct

• P22 ■■ 1. With Resistor ■■ 2. Gate Direct

• P23 ■■ 1. With Resistor ■■ 2. Gate Direct

• P3x ■■ 1. With Resistor ■■ 2. Gate Direct

CHAPTER 1: OUTLINE

7. DP PORT OUTPUT SPECIFICATION

■■ 1. Complementary ■■ 2. Nch-OpenDrain

8. SVD EXTERNAL VOLTAGE DETECTION

■■ 1. Not Use

■■ 2. Use

9. LCD DRIVER SPECIFICATION

■■ 1. 40 seg ∗ 17 com

■■ 2. 48 seg ∗ 8 com

10. FSK INTERNAL FEEDBACK RESISTOR

■■ 1. Use

■■ 2. Not Use

S1C63558 TECHNICAL MANUAL EPSON 7

CHAPTER 2: POWER SUPPLY AND INITIAL RESET

CHAPTER

OWER SUPPLY AND INITIAL

ESET

2.1 P ower Supply

The S1C63558 operating power voltage is as follows:

Supply voltage V

The S1C63558 operates by applying a single power supply within the above range between V The S1C63558 itself generates the voltage necessary for all the internal circuits by the built-in power supply circuits shown in Table 2.1.1.

Note: • Do not drive external loads with the output voltage from the internal power supply circuits.

• See Chapter 7, "Electrical Characteristics", for voltage values and drive capability.

DD = 2.2 V to 5.5 V

Oscillation and internal circuits LCD driver FSK demodulator

External power supply

Circuit

AVDD

VC23

AVSS

Table 2.1.1 Power supply circuits

Power supply circuit

Oscillation system voltage regulator LCD system voltage circuit Analog system power supply

VDD

VC1

VC4 VC5

CA CB

VSS

Oscillation system

voltage regulator

LCD system

voltage circuit

VD1

VC1 ~ VC5

Output voltage

AVDD, AV

Internal

circuits

Oscillation

circuit

LCD driver

VC1–V

DD and VSS.

OSC1~4

COM0~16 SEG0~39

Fig. 2.1.1 Configuration of power supply

2.1.1 V oltage <VD1> for oscillation circuit and internal circuits

VD1 is a voltage for the oscillation circuit and the internal logic circuits, and is generated by the oscillation system voltage regulator for stabilizing the oscillation. The V

D1 voltage is fixed at 2.1 V, so it is not

necessary to control by software.

2.1.2 V oltage <VC1–VC5> for LCD driving

VC1, VC23, VC4 and VC5 are the LCD (1/4 bias) drive voltages generated by the LCD system voltage circuit. These four output voltages can only be supplied to the externally expanded LCD driver. The LCD system voltage circuit generates V other voltages by boosting or reducing the voltage of V voltage values and boost/reduce status.

Table 2.1.2.1 LCD drive voltage when generated internally

LCD drive voltage

C23

Boost/reduce status

VC2 × 0.5

(standard)

Refer to Section 4.7, "LCD Driver", for control of the LCD drive voltage.

8 EPSON S1C63558 TECHNICAL MANUAL

C23 with the voltage regulator built-in, and generates three

C23. Table 2.1.2.1 shows the VC1, VC23, VC4 and VC5

Voltage value [V]

× 1.5

× 2

1.13

2.25

3.38

4.50

Note: The LCD drive voltage can

be adjusted by the software (see Section 4.7.5). Values in the above table are

typical values.

CHAPTER 2: POWER SUPPLY AND INITIAL RESET

2.2 Initial Reset

To initialize the S1C63558 circuits, initial reset must be executed. There are two ways of doing this.

(1) External initial reset by the RESET terminal (2) External initial reset by simultaneous low input to terminals K00–K03 (mask option setting)

The circuits are initialized by either (1) or (2). When the power is turned on, be sure to initialize using the reset function. It is not guaranteed that the circuits are initialized by only turning the power on.

Figure 2.2.1 shows the configuration of the initial reset circuit.

OSC1

OSC2

oscillation

Mask option

OSC1

circuit

Divider

1 Hz 2 Hz

K00

K01

K02

K03

RESET

authorize

Time

circuit

Mask option

Noise

reject

circuit

Internal initial reset

Fig. 2.2.1 Configuration of initial reset circuit

2.2.1 Reset terminal (RESET)

Initial reset can be executed externally by setting the reset terminal to a low level (VSS). After that the initial reset is released by setting the reset terminal to a high level (V The reset input signal is maintained by the RS latch and becomes the internal initial reset signal. The RS latch is designed to be released by a 2 Hz signal (high) that is divided by the OSC1 clock. Therefore in normal operation, a maximum of 250 msec (when f

OSC1 = 32.768 kHz) is needed until the internal initial

reset is released after the reset terminal goes to high level. Be sure to maintain a reset input of 0.1 msec or more. However, when turning the power on, the reset terminal should be set at a low level as in the timing shown in Figure 2.2.1.1.

DD) and the CPU starts operating.

2.2 V

2.0 msec or more

RESET

Power on

0.5•V

0.1•VDD or less (low level)

Fig. 2.2.1.1 Initial reset at power on

The reset terminal should be set to 0.1•V more. After that, a level of 0.5•V

S1C63558 TECHNICAL MANUAL EPSON 9

DD or less should be maintained more than 2.0 msec.

DD or less (low level) until the supply voltage becomes 2.2 V or

CHAPTER 2: POWER SUPPLY AND INITIAL RESET

2.2.2 Simultaneous low input to terminals K00–K03

Another way of executing initial reset externally is to input a low signal simultaneously to the input ports (K00–K03) selected with the mask option. Since this initial reset passes through the noise reject circuit, maintain the specified input port terminals at low level for at least 1.5 msec (when the oscillation frequency f tion. The noise reject circuit does not operate immediately after turning the power on until the oscillation circuit starts oscillating. Therefore, maintain the specified input port terminals at low level for at least 1.5 msec (when the oscillation frequency f

OSC1 is 32.768 kHz) after oscillation starts.

Table 2.2.2.1 shows the combinations of input ports (K00–K03) that can be selected with the mask option.

Table 2.2.2.1 Combinations of input ports

Not use

K00∗K01∗K02∗K03

K00∗K01∗K02

K00∗K01

When, for instance, mask option 2 (K00∗K01∗K02∗K03) is selected, initial reset is executed when the signals input to the four ports K00–K03 are all low at the same time. When 3 or 4 is selected, the initial reset is done when a key entry including a combination of selected input ports is made. Further, the time authorize circuit can be selected with the mask option. The time authorize circuit checks the input time of the simultaneous low input and performs initial reset if that time is the defined time (1 to 2 sec) or more. If using this function, make sure that the specified ports do not go low at the same time during ordinary operation.

OSC1 is 32.768 kHz) during normal opera-

2.2.3 Internal register at initial resetting

Initial reset initializes the CPU as shown in Table 2.2.3.1.

The registers and flags which are not initialized by initial reset should be initialized in the program if necessary. In particular, the stack pointers SP1 and SP2 must be set as a pair because all the interrupts including NMI are masked after initial reset until both the SP1 and SP2 stack pointers are set with software.

When data is written to the EXT register, the E flag is set and the following instruction will be executed in the extended addressing mode. If an instruction which does not permit extended operation is used as the following instruction, the operation is not guaranteed. Therefore, do not write data to the EXT register for initialization only. Refer to the "S1C63000 Core CPU Manual" for extended addressing and usable instructions.

Table 2.2.3.1 Initial values

Name

Data register A Data register B Extension register EXT Index register X Index register Y Program counter Stack pointer SP1 Stack pointer SP2 Zero flag Carry flag Interrupt flag Extension flag Queue register

CPU core

Symbol

A B

EXT

X Y

PC SP1 SP2

I E

Number of bits

4 4

8 16 16 16

1 16

Setting value

Undefined Undefined Undefined Undefined Undefined

0110H Undefined Undefined Undefined Undefined

0 0

Undefined

Name

RAM Display memory Other pheripheral circuits

∗ See Section 4.1, "Memory Map".

Peripheral circuits

Number of bits

4 4 –

Setting value

Undefined Undefined

∗

10 EPSON S1C63558 TECHNICAL MANUAL

CHAPTER 2: POWER SUPPLY AND INITIAL RESET

2.2.4 Terminal settings at initial resetting

The output port (R) terminals and I/O port (P) terminals are shared with special output terminals and input/output terminals of the serial interface. These functions are selected by the software. At initial reset, these terminals are set to the general purpose output port terminals and I/O port terminals. Set them according to the system in the initial routine. In addition, take care of the initial status of output terminals when designing a system. Table 2.2.4.1 shows the list of the shared terminal settings.

Table 2.2.4.1(a) List of shared terminal settings (Rxx)

Terminal

name

R00 R01 R02 R03 R10 R11 R12 R13

R20–R23

at initial reset

R00 (HIGH output) R01 (HIGH output) R02 (HIGH output) R03 (HIGH output) R10 (HIGH output) R11 (HIGH output) R12 (HIGH output) R13 (HIGH output) R20–R23 (HIGH output)

FOUT

TOUT

Table 2.2.4.1(b) List of shared terminal settings (Pxx)

Terminal

name

P00–P03

P10 P11 P12 P13 P20 P21 P22 P23 P30 P31 P32 P33

∗1 When "with pull-up" is selected by mask option (high impedance when "gate direct" is selected) ∗2 The P10–P13 I/O terminals are used for serial I/F (1) and the P30–P33 I/O terminals are for serial I/F (2).

at initial reset

P00–P03 (Input & Pull-up *1) P10 (Input & Pull-up *1) P11 (Input & Pull-up *1) P12 (Input & Pull-up *1) P13 (Input & Pull-up *1) P20 (Input & Pull-up *1) P21 (Input & Pull-up *1) P22 (Input & Pull-up *1) P23 (Input & Pull-up *1) P30 (Input & Pull-up *1) P31 (Input & Pull-up *1) P32 (Input & Pull-up *1) P33 (Input & Pull-up *1)

Special output Serial I/F *2 Terminal status

FRFRAsync.

For setting procedure of the functions, see explanations for each of the peripheral circuits.

Special outputTerminal status

BZBZXBZ

XBZ

SIN(I)

SOUT(O)

SIN(I)

SOUT(O)

HDO

SIN(I)

XRMUTE

HFO

Clk-sync. Master

SOUT(O)

SCLK(O)

SOUT(O)

SCLK(O)

XTMUTE

Clk-sync. Slave

SIN(I)

SOUT(O)

SCLK(I)

SRDY(O)

SIN(I)

SOUT(O)

SCLK(I)

SRDY(O)

2.3 Test Terminal (TEST)

This is the terminal used for the factory inspection of the IC. During normal operation, connect the TEST terminal to V

S1C63558 TECHNICAL MANUAL EPSON 11

DD.

CHAPTER 3: CPU, ROM, RAM

CHAPTER 3 CPU, R OM, RAM

3.1 CPU

The S1C63558 has a 4-bit core CPU S1C63000 built-in as its CPU part. Refer to the "S1C63000 Core CPU Manual" for the S1C63000.

Note:

The SLP instruction cannot be used because the SLEEP operation is not assumed in the S1C63558.

3.2 Code ROM

The built-in code ROM is a mask ROM for loading programs, and has a capacity of 8,192 steps × 13 bits. The core CPU can linearly access the program space up to step FFFFH from step 0000H, however, the program area of the S1C63558 is step 0000H to step 1FFFH. The program start address after initial reset is assigned to step 0110H. The non-maskable interrupt (NMI) vector and hardware interrupt vectors are allocated to step 0100H and steps 0104H–010EH, respectively.

0000H

1FFFH

2000H

FFFFH

ROM

Unused area

13 bits

S1C63558 program area

S1C63000 core CPU program space

0000H

0100H

0104H

010EH

0110H

Program area

NMI vector

Hardware

interrupt vectors

Program start address

Program area

Fig. 3.2.1 Configuration of code ROM

3.3 RAM

The RAM is a data memory for storing various kinds of data, and has a capacity of 5,120 words × 4 bits. The RAM area is assigned to addresses 0000H to 13FFH on the data memory map. Addresses 0100H to 01FFH are 4-bit/16-bit data accessible areas and in other areas it is only possible to access 4-bit data. When programming, keep the following points in mind.

(1) Part of the RAM area is used as a stack area for subroutine call and register evacuation, so pay

attention not to overlap the data area and stack area.

(2) The S1C63000 core CPU handles the stack using the stack pointer for 4-bit data (SP2) and the stack

pointer for 16-bit data (SP1). 16-bit data are accessed in stack handling by SP1, therefore, this stack area should be allocated to the area where 4-bit/16-bit access is possible (0100H to 01FFH). The stack pointers SP1 and SP2 change cyclically within their respective range: the range of SP1 is 0000H to 03FFH and the range of SP2 is 0000H to 00FFH. Therefore, pay attention to the SP1 value because it may be set to 0200H or more exceeding the 4-bit/16-bit accessible range in the S1C63558 or it may be set to 00FFH or less. Memory accesses except for stack operations by SP1 are 4-bit data access. After initial reset, all the interrupts including NMI are masked until both the stack pointers SP1 and SP2 are set by software. Further, if either SP1 or SP2 is re-set when both are set already, the interrupts including NMI are masked again until the other is re-set. Therefore, the settings of SP1 and SP2 must be done as a pair.

12 EPSON S1C63558 TECHNICAL MANUAL

CHAPTER 3: CPU, ROM, RAM

(3) Subroutine calls use 4 words (for PC evacuation) in the stack area for 16-bit data (SP1). Interrupts use

4 words (for PC evacuation) in the stack area for 16-bit data (SP1) and 1 word (for F register evacuation) in the stack area for 4-bit data.

0000H

00FFH

0100H

01FFH

0200H

13FFH

4 bits

4-bit access area (SP2 stack area)

4/16-bit access area (SP1 stack area)

4-bit access area (Data area)

Fig. 3.3.1 Configuration of data RAM

3.4 Data ROM

The data ROM is a mask ROM for loading various static data such as a character generator, and has a capacity of 2,048 words × 4 bits. The data ROM is assigned to addresses 8000H to 87FFH on the data memory map, and the data can be read using the same data memory access instructions as the RAM.

S1C63558 TECHNICAL MANUAL EPSON 13

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map)

CHAPTER 4

The peripheral circuits of S1C63558 (timer, I/O, etc.) are interfaced with the CPU in the memory mapped I/O method. Thus, all the peripheral circuits can be controlled by accessing the I/O memory on the memory map using the memory operation instructions. The following sections explain the detailed operation of each peripheral circuit.

ERIPHERAL

IRCUITS AND

PERA TION

4.1 Memory Map

The S1C63558 data memory consists of 5,120-word RAM, 2,048-word data ROM, 816-bit display memory and 97-word peripheral I/O memory. Figure 4.1.1 shows the overall memory map of the S1C63558, and Tables 4.1.1(a)–(h) the peripheral circuits' (I/O space) memory maps.

0000H

RAM area

1400H

F000H

Display memory area

F25EH

Unused area

FF00H

Peripheral I/O area

FFFFH

8000H

8800H

F000H

FF00H

FFFFH

Unused area

Data ROM area

Unused area

I/O memory area

Fig. 4.1.1 Memory map

Note: Memory is not implemented in unused areas within the memory map. Further, some non-imple-

mentation areas and unused (access prohibition) areas exist in the display memory area and the

peripheral I/O area. If the program that accesses these areas is generated, its operation cannot be

guaranteed. Refer to Section 4.7.5, "Display memory", for the display memory, and the I/O

memory maps shown in Tables 4.1.1 (a)–(h) for the peripheral I/O area.

14 EPSON S1C63558 TECHNICAL MANUAL

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map)

Table 4.1.1 (a) I/O memory map (FF00H–FF18H)

Address Comment

CLKCHG OSCC 0 Dummy

FF00H

SVDS3 SVDS2 SVDS1 SVDS0

FF04H

FF05H

FOUTE 0 FOFQ1 FOFQ0

FF06H

FF07H

FF10H

PTS3 PTS2 PTS1 PTS0

FF11H

FTS3 FTS2 FTS1 FTS0

FF12H

CHFO CHDO CRMO CTMO

FF13H

FF14H

IDP3 IDP2 IDP1 IDP0

FF15H

CTO 0 SINR SINC

FF16H

R/W R R/W

TCD3 TCD2 TCD1 TCD0

FF17H

HSON 0 CRMUT CTMUT

FF18H

R/W R R/W

D3 D2

D1 D0 Name Init

R R/WR/W

R/W

00SVDDT SVDON

R R/W

R/W R R/W

00WDEN WDRST

R/W WR

TPS 0 MB DRS

R/W R R/W

R/W

HF HOLD PAUSE FLASH

R/W W

R/W

CLKCHG

OSCC

∗

0 Dummy SVDS3 SVDS2 SVDS1 SVDS0

∗

0 SVDDT SVDON FOUTE

∗

0 FOFQ1 FOFQ0

∗

WDEN

∗

WDRST

TPS

∗

DRS PTS3 PTS2 PTS1 PTS0

FTS3

FTS2

FTS1

FTS0 CHFO CHDO

CRMO

CTMO

HOLD

∗

PAUSE

∗

FLASH

IDP3

IDP2

IDP1

IDP0

CTO

∗

SINR

SINC TCD3

TCD2

TCD1

TCD0

HSON

∗

0 CRMUT CTMUT

∗1

OSC3OnOSC1

∗

–

0 0 0 0 0

∗

–

∗

–

00LowOnNormal

FOUT DC

∗

–

0 0

∗

–

∗

–

Reset

–

0 0

∗

33.3:66.6

Enable

Reset Pulse

20pps

0 1 0 0 0 1 1 0 0

HFO

HDO

XRMUTE

XTMUTE

0 0

Yes

Yes 1 0 0 0 0

∗

–

Enable

Off

∗

–

Mute

CPU clock switch

Off

OSC3 oscillation On/Off Unused General-purpose register

SVD criteria voltage setting

[SVDS3–0] Voltage(V) [SVDS3–0] Voltage(V)

2.20/1.05 8

2.60

2.20

2.70

2.20

2.80

2.90

2.20

3.00 Unused Unused SVD evaluation data

Off

SVD circuit On/Off R03 output selection (R03 should be fixed at "1".)

Unused FOUT frequency selection

[FOFQ1, 0] Frequency

OSC1

/641f

Unused Unused

Disable

Watchdog timer enable

Invalid

Watchdog timer reset (writing) Tone / pulse mode selection

Tone

Unused

40:60

Make : Break ratio selection

10pps

Dialing pulse rate selection Pause time selection (initial value: 4 sec)

[PTS3–0] Time(sec) [PTS3–0] Time(sec)

Flash time selection (initial value: 563 ms)

[FTS3–0] Time(ms) [FTS3–0] Time(ms)

R13 output selection (R13 should be fixed at "1".)

R12 output selection (R12 should be fixed at "1".)

R11 output selection (R11 should be fixed at "1".)

R10 output selection (R10 should be fixed at "1".) Hand free

Hold-line function

Off

Pause function

Flash function

Inter-digit pause selection for dial pulse (initial value: 750 ms)

[IDP3–0] Time(ms) [IDP3–0] Time(ms)

Continuous tone output On/Off

Off

750

844

188

938

188

938

8 8

3 11 11

281

1031

281

1031

4 12 12

375

1125

375

1125

Unused

Disable

DTMF row frequency output enable

Disable

DTMF column frequency output enable Telephone code for dialing

[TCD3–0] DTMF DP [TCD3–0] DTMF DP

Hook switch On/Off

(R1C4)

(R3C2)

(R1C1)

1 9

(R3C3)

(R1C2)

(R4C2)

(R1C3)

(R4C3)

(R2C1)

(R4C1)

Unused

Receive mute control

Transmit mute control

Remarks

∗1 Initial value at initial reset ∗3 Constantly "0" when being read ∗2 Not set in the circuit ∗4 Depends on the input status of the RDIN terminal

OSC1

1219

(R2C2)

(R2C4)

2.30

3.10

13 13

469

/82f

5 5

2.40 14

3.20

OSC1

6 14 14

563

1313

563

1313

(R2C3)

6 14

(R4C4)

2.50 15

3.30

OSC3

7 15 15

656

1406

656

1406

(R3C1)

7 15

(R3C4)

S1C63558 TECHNICAL MANUAL EPSON 15

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map)

Table 4.1.1 (b) I/O memory map (FF20H–FF42H)

Address Comment

SIK03 SIK02 SIK01 SIK00

FF20H

FF21H

KCP03 KCP02 KCP01 KCP00

FF22H

SIK13 SIK12 SIK11 SIK10

FF24H

(EVIN)

FF25H

KCP13 KCP12 KCP11 KCP10

FF26H

R03HIZ R02HIZ R01HIZ R00HIZ

FF30H

(FOUT)

FF31H

R13HIZ R12HIZ R11HIZ R10HIZ

FF32H

(HFO)

FF33H

R23HIZ R22HIZ R21HIZ R20HIZ

FF34H

FF35H

IOC03 IOC02 IOC01 IOC00

FF40H

PUL03 PUL02 PUL01 PUL00

FF41H

FF42H

D3 D2

D1 D0 Name Init

R/W

K03 K02 K01 K00

R/W

K13

K12 K11 K10

R/W

R03

R02

R01

(BZ)

R00

(XBZ)

(TOUT)

R/W

R13

R12

R11

(XRMUTE)

(XTMUTE)

R10

(HDO)

R/W

R23 R22 R21 R20

R/W

P03 P02 P01 P00

R/W

SIK03 SIK02 SIK01 SIK00

K03 K02 K01

K00 KCP03 KCP02 KCP01 KCP00

SIK13 SIK12 SIK11 SIK10

K13

K12

K11

K10 KCP13 KCP12 KCP11 KCP10 R03HIZ R02HIZ R01HIZ R00HIZ

R03

R02

R01

R00 R13HIZ R12HIZ R11HIZ R10HIZ

R13

R12

R11

R10 R23HIZ R22HIZ R21HIZ R20HIZ

R23

R22

R21

R20

IOC03 IOC02 IOC01 IOC00 PUL03 PUL02 PUL01 PUL00

P03

P02

P01

P00

0 0 0

0 – – – –

1 – – – –

∗1

10 Enable Enable Enable Enable

∗

High

∗

High

∗

High

∗

High

Enable Enable Enable Enable

∗

High

∗

High

∗

High

∗

High

Hi-Z Hi-Z Hi-Z Hi-Z High High High High Hi-Z Hi-Z Hi-Z Hi-Z High High High High Hi-Z Hi-Z Hi-Z Hi-Z High High High

High Output Output Output Output

On On On On

∗

High

∗

High

∗

High

∗

High

Disable Disable

K00–K03 interrupt selection register

Disable Disable

Low Low

K00–K03 input port data

Low Low

K00–K03 input comparison register

Disable Disable

K10–K13 interrupt selection register

Disable Disable

Low Low

K10–K13 input port data

Low Low

K10–K13 input comparison register

R03 (FOUTE=0)/FOUT (FOUTE=1) Hi-z control

Output

R02 (PTOUT=0)/TOUT (PTOUT=1) Hi-z control

Output

R01 (BZOUT=0)/BZ (BZOUT=1) Hi-z control

Output

R00 (XBZOUT=0)/XBZ (XBZOUT=1) Hi-z control

Output

R03

Low Low Low

Low Output Output Output Output

Low

output port data (

R02

output port data (

R01

output port data (

R00

output port data ( R13 (CHFO=0)/HFO (CHFO=1) Hi-z control R12 (CHDO=0)/HDO (CHDO=1) Hi-z control R11 (CRMO=0)/XRMUTE (CRMO=1) Hi-z control R10 (CTMO=0)/XTMUTE (CTMO=1) Hi-z control R13 output port data (CHFO=0) Fix at "1" when HFO is used. R12 output port data (CHDO=0) Fix at "1" when HDO is used. R11 output port data (CRMO=0) Fix at "1" when XRMUTE is used. R10 output port data (CTMO=0) Fix at "1" when XTMUTE is used.

FOUTE=0 PTOUT=0 BZOUT=0 XBZOUT=0

Output Output

R20–R23 Hi-z control

Output Output

Low Low

R20–R23 output port data

Low

Low Input Input

P00–P03 I/O control register

Input Input

Off Off

P00–P03 pull-up control register

Off

Off Low Low

P00–P03 I/O port data

Low Low

) Fix at "1" when ) Fix at "1" when ) Fix at "1" when

) Fix at "1" when

FOUT TOUT BZ

is used.

XBZ

is used. is used.

is used.

16 EPSON S1C63558 TECHNICAL MANUAL

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map)

Table 4.1.1 (c) I/O memory map (FF44H–FF4DH)

Address Comment

IOC13 IOC12 IOC11 IOC10

FF44H

PUL13 PUL12 PUL11 PUL10

FF45H

P13

(XSRDY)

FF46H

IOC23 IOC22 IOC21 IOC20

FF48H

PUL23 PUL22 PUL21 PUL20

FF49H

P23 (FR)

FF4AH

IOC33 IOC32 IOC31 IOC30

FF4CH

PUL33 PUL32 PUL31 PUL30

FF4DH

D3 D2

P12

(XSCLK)

P22

(CL)

D1 D0 Name Init

R/W

P11

(SOUT)

P10

(SIN)

R/W

P21 P20

R/W

IOC13

IOC12

IOC11

IOC10

PUL13

PUL12

PUL11

PUL10

P13

P12

P11

P10

IOC23

IOC22

IOC21 IOC20 PUL23

PUL22

PUL21 PUL20

P23

P22

P21 P20

IOC33

IOC32

IOC31

IOC30

PUL33

PUL32

PUL31

PUL30

–

– –

∗1

∗

0 0 1

1 1

∗

Input

Output

Input

Output

Input

Output

Input

Output

Off

Low

High

Low

High

Low

High

Low

High

Input

Output

Input

Output

Input

Output

Input

Output

Off

Low

High

Low

High

Low

High

Low

High

Input

Output

Input

Output

Input

Output

Input

Output

Off

P13 I/O control register General-purpose register when SIF (clock sync. slave) is selected P12 I/O control register General-purpose register when SIF (clock sync.) is selected P11 I/O control register (ESIF=0) General-purpose register when SIF is selected P10 I/O control register (ESIF=0) General-purpose register when SIF is selected P13 pull-up control register General-purpose register when SIF (clock sync. slave) is selected P12 pull-up control register General-purpose register when SIF (clock sync. master) is selected SCLK (I) pull-up control register when SIF (clock sync. slave) is selected P11 pull-up control register (ESIF=0) General-purpose register when SIF is selected P10 pull-up control register (ESIF=0) SIN pull-up control register when SIF is selected P13 I/O port data General-purpose register when SIF (clock sync. slave) is selected P12 I/O port data General-purpose register when SIF (clock sync.) is selected P11 I/O port data (ESIF=0) General-purpose register when SIF is selected P10 I/O port data (ESIF=0) General-purpose register when SIF is selected P23 I/O control register (EXLCDC=0) General-purpose register when FR output is selected P22 I/O control register (EXLCDC=0) General-purpose register when CL output is selected P21 I/O control register P20 I/O control register P23 pull-up control register (EXLCDC=0) General-purpose register when FR output is selected P22 pull-up control register (EXLCDC=0) General-purpose register when CL output is selected P21 pull-up control register P20 pull-up control register P23 I/O port data (EXLCDC=0) General-purpose register when FR output is selected P22 I/O port data (EXLCDC=0) General-purpose register when CL output is selected P21 I/O port data P20 I/O port data P33 I/O control register General-purpose register when SIF (clock sync. slave) is selected P32 I/O control register General-purpose register when SIF (clock sync.) is selected P31 I/O control register (ESIFS=0) General-purpose register when SIF is selected P30 I/O control register (ESIFS=0) General-purpose register when SIF is selected P33 pull-up control register General-purpose register when SIF (clock sync. slave) is selected P32 pull-up control register General-purpose register when SIF (clock sync. master) is selected SCLK (I) pull-up control register when SIF (clock sync. slave) is selected P31 pull-up control register (ESIFS=0) General-purpose register when SIF is selected P30 pull-up control register (ESIFS=0) SIN pull-up control register when SIF is selected

S1C63558 TECHNICAL MANUAL EPSON 17

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map)

Table 4.1.1 (d) I/O memory map (FF4EH–FF67H)

Address Comment

(XSRDYS)

FF4EH

FF58H

EPRS PMDS SCS1S SCS0S

FF59H

RXTRGS RXENS TXTRGS TXENS

FF5AH

FF5BH

TRXD3S TRXD2S TRXD1S TRXD0S

FF5CH

TRXD7S TRXD6S TRXD5S TRXD4S

FF5DH

LDUTY1 LDUTY0 Dummy LPWR

FF60H

EXLCDC ALOFF ALON LPAGE

FF61H

FF62H

FF65H

FSKON 0 RDET CDET

FF66H

FF67H

D3 D2

P33

(XSCLKS)

D1 D0 Name Init

P32

P31

(SINS)

(SOUTS)

P30

R/W

SMD1S SMD0S ESIFS

R R/W

R/W

0 FERS PERS OERS

R R/W

R/W

LC3 LC2 LC1 LC0

R/W

00BZOUT XBZOUT

R R/W

R/W R

00RDETCP CDETCP

R R/W

P33

P32

P31

P30

∗

0 SMD1S SMD0S

ESIFS EPRS

PMDS SCS1S SCS0S

RXTRGS

RXENS

TXTRGS

TXENS

∗

FERS

PERS

OERS

TRXD3S TRXD2S TRXD1S TRXD0S TRXD7S TRXD6S TRXD5S TRXD4S

LDUTY1 LDUTY0

Dummy

LPWR

EXLCDC

ALOFF

ALON LPAGE

LC3 LC2 LC1 LC0

∗

BZOUT

XBZOUT

FSKON

∗

RDET

CDET

∗

0 RDETCP CDETCP

∗1

∗

High

–

∗

High

–

∗

High

–

∗

High

–

∗

–

0 0 0 SIF I/O 0

Enable

Odd 0 0

Run

Trigger

Enable

Run

Trigger

Enable

∗

–

Error

Reset

Error

Reset

Error

Reset

∗

–

High

∗

–

High

∗

–

High

∗

–

High

∗

–

High

∗

–

High

∗

–

High

∗

–

High 0 0 0 0OnOff 0

Enable

All Off

All On

F100-F15F

∗

–

∗

–

∗

–

∗

–

∗

–

∗

–

0 0BZXBZDCDC

∗

–

∗

Ring

–

Carrier

∗

–

∗

–

0 0

Low

P33 I/O port data General-purpose register when SIF (clock sync. slave) is selected

Low

P32 I/O port data General-purpose register when SIF (clock sync.) is selected

Low

P31 I/O port data (ESIFS=0) General-purpose register when SIF is selected

Low

P30 I/O port data (ESIFS=0) General-purpose register when SIF is selected Unused Serial I/F (2) mode selection Serial I/F (2) enable (P3x port function selection) Serial I/F (2) parity enable register

Disable

Serial I/F (2) parity mode selection

Even

SIF (2) clock source selection

Stop

Serial I/F (2) receive status (reading)

–

Serial I/F (2) receive trigger (writing)

Disable

Serial I/F (2) receive enable

Stop

Serial I/F (2) transmit status (reading)

–

Serial I/F (2) transmit trigger (writing)

Disable

Serial I/F (2) transmit enable

[SMD1S, 0S]

Clk-sync. master

Mode [SMD1S, 0S] Mode

[SCS1S, 0S]

1200bps1600bps22400bps3PT

Mode

Unused

No error

Serial I/F (2) framing error flag status (reading)

–

Serial I/F (2) framing error flag reset (writing)

No error

Serial I/F (2) parity error flag status (reading)

–

Serial I/F (2) parity error flag reset (writing)

No error

Serial I/F (2) overrun error flag status (reading)

–

Serial I/F (2) overrun error flag reset (writing)

Low Low Low Low Low Low Low

Serial I/F (2) t LSB

MSB Serial I/F (2) t

ransmit/receive data

Low

LCD drive duty switch

[LDUTY1, 0] Duty

General-purpose register LCD power On/Off

Disable

Expanded LCD driver signal control

Normal

LCD all Off control

Normal

LCD all On control

F000-F05F

Display memory area selection (when 1/8 duty is selected) General-purpose register when 1/16, 1/17 duty is selected LCD contrast adjustment

[LC3–0] Contrast

Light––15Dark

Unused Unused R01 output selection (R01 should be fixed at "1".) R00 output selection (R00 should be fixed at "1".)

Off

FSK demodulator On/Off Unused

No Ring

Ring detection bit

No Carrier

Carrier detection bit Unused Unused RDET comparison register CDET comparison register

Async. 7-bit

(low-order 4 bits)

(high-order 4 bits)

Clk-sync. slave

Async. 8-bit

1/1711/16

2, 3

1/8

18 EPSON S1C63558 TECHNICAL MANUAL

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map)

Table 4.1.1 (e) I/O memory map (FF6CH–FF7AH)

Address Comment

ENRTM ENRST ENON BZE

FF6CH

R/W W R/W

FF6DH

FF6EH

FF6FH

FF70H

EPR PMD SCS1 SCS0

FF71H

RXTRG RXEN TXTRG TXEN

FF72H

FF73H

TRXD3 TRXD2 TRXD1 TRXD0

FF74H

TRXD7 TRXD6 TRXD5 TRXD4

FF75H

FF76H

FF78H

TM3 TM2 TM1 TM0

FF79H

TM7 TM6 TM5 TM4

FF7AH

D3 D2

D1 D0 Name Init

0 BZSTP BZSHT SHTPW

RW R/W

0 BZFQ2 BZFQ1 BZFQ0

R R/W

0 BDTY2 BDTY1 BDTY0

R R/W

0 SMD1 SMD0 ESIF

R R/W

R/W

0 FER PER OER

R R/W

R/W

000SIFTM

R R/W

00TMRST TMRUN

W R/WR

ENRTM

∗

ENRST

ENON

BZE

∗

BZSTP

BZSHT

SHTPW

∗

0 BZFQ2 BZFQ1 BZFQ0

∗

0 BDTY2 BDTY1 BDTY0

∗

SMD1 SMD0

ESIF EPR

PMD SCS1 SCS0

RXTRG

RXEN

TXTRG

TXEN

∗

FER

PER

OER

TRXD3 TRXD2 TRXD1 TRXD0 TRXD7 TRXD6 TRXD5 TRXD4

∗

SIFTM

∗

0 TMRST TMRUN

TM3 TM2 TM1 TM0 TM7 TM6 TM5 TM4

∗1

Reset

0 0

∗

–

0 0

–

∗

125msec

0 0 0

∗

–

0 0 0

∗

–

0 0 0 SIF I/O 0 0 0 0 0

0 0

∗

–

∗

–

∗

–

∗

–

∗

–

∗

–

∗

–

∗

–

∗

–

∗

–

∗

–

∗

–

∗

–

∗

–

∗

Reset0Reset

0 0 0 0 0 0 0 0

1sec

0.5sec

Reset

Invalid

Stop

Busy

Off

Disable

Invalid Invalid Ready

Enable

Trigger

31.25msec

Enable

Disable

Odd

Even

Run

Stop Trigger Enable

Trigger Enable

Error

Reset

Error

Reset

Error

Reset

Run

High High High High High High High High

–

Disable

Stop

–

Disable

No error

–

No error

–

No error

– Low Low Low Low Low Low Low Low

Invalid

Run

Stop

Envelope releasing time selection Envelope reset (writing) Envelope On/Off Buzzer output enable Unused 1-shot buzzer stop (writing) 1-shot buzzer trigger (writing) 1-shot buzzer status (reading) 1-shot buzzer pulse width setting Unused Buzzer frequency selection

[BZFQ2, 1, 0] Frequency (Hz) [BZFQ2, 1, 0] Frequency (Hz)

4096.013276.822730.732340.6

2048.051638.461365.371170.3

Unused Buzzer signal duty ratio selection

(refer to main manual)

Unused Serial I/F (1) mode selection Serial I/F (1) enable (P1x port function selection)

[SMD1, 0] Mode [SMD1, 0] Mode

Clk-sync. master

Async. 7-bit

Serial I/F (1) parity enable register Serial I/F (1) parity mode selection SIF (1) clock source selection

[SCS1, 0] Mode

1200bps1600bps22400bps3PT Serial I/F (1) receive status (reading) Serial I/F (1) receive trigger (writing) Serial I/F (1) receive enable Serial I/F (1) transmit status (reading) Serial I/F (1) transmit trigger (writing) Serial I/F (1) transmit enable Unused Serial I/F (1) framing error flag status (reading) Serial I/F (1) framing error flag reset (writing) Serial I/F (1) parity error flag status (reading) Serial I/F (1) parity error flag reset (writing) Serial I/F (1) overrun error flag status (reading) Serial I/F (1) overrun error flag reset (writing)

Serial I/F (1) t

ransmit/receive data

LSB MSB

Serial I/F (1) t

ransmit/receive data

Unused Unused Unused Serial I/F test mode (disabled. Do not change.) Unused Unused Clock timer reset (writing) Clock timer Run/Stop Clock timer data (16 Hz) Clock timer data (32 Hz) Clock timer data (64 Hz) Clock timer data (128 Hz) Clock timer data (1 Hz) Clock timer data (2 Hz) Clock timer data (4 Hz) Clock timer data (8 Hz)

(low-order 4 bits)

(high-order 4 bits)

Clk-sync. slave

Async. 8-bit

S1C63558 TECHNICAL MANUAL EPSON 19

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map)

Table 4.1.1 (f) I/O memory map (FF7CH–FFCBH)

Address Comment

FF7CH

SWD3 SWD2 SWD1 SWD0

FF7DH

SWD7 SWD6 SWD5 SWD4

FF7EH

FFC0H

CHSEL PTOUT CKSEL1 CKSEL0

FFC1H

PTPS01 PTPS00 PTRST0 PTRUN0

FFC2H

PTPS11 PTPS10 PTRST1 PTRUN1

FFC3H

RLD03 RLD02 RLD01 RLD00

FFC4H

RLD07 RLD06 RLD05 RLD04

FFC5H

RLD13 RLD12 RLD11 RLD10

FFC6H

RLD17 RLD16 RLD15 RLD14

FFC7H

PTD03 PTD02 PTD01 PTD00

FFC8H

PTD07 PTD06 PTD05 PTD04

FFC9H

PTD13 PTD12 PTD11 PTD10

FFCAH

PTD17 PTD16 PTD15 PTD14

FFCBH

D3 D2

D1 D0 Name Init

00SWRST SWRUN

W R/WR

0 EVCNT FCSEL PLPOL

R R/W

R/W

W R/WR/W

R/W

∗

SWRST

SWRUN

SWD3 SWD2 SWD1 SWD0 SWD7 SWD6 SWD5 SWD4

∗

EVCNT

FCSEL PLPOL CHSEL

PTOUT CKSEL1 CKSEL0 PTPS01 PTPS00

∗

PTRST0 PTRUN0

PTPS11 PTPS10

∗

PTRST1 PTRUN1

RLD03 RLD02 RLD01 RLD00 RLD07 RLD06 RLD05 RLD04 RLD13 RLD12 RLD11 RLD10 RLD17 RLD16 RLD15 RLD14 PTD03 PTD02 PTD01 PTD00 PTD07 PTD06 PTD05 PTD04 PTD13 PTD12 PTD11 PTD10 PTD17 PTD16 PTD15 PTD14

∗1

∗

–

∗

–

Reset0Reset

0 0 0 0 0 0 0 0

∗

–

0 0 0 0 0 0 0 0 0

∗

–

0 0 0

∗

–

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Invalid

Run

Stop

Event ct.

Timer

With NR

No NR

Timer1

Timer0

Off

OSC3

OSC1

OSC3

OSC1

Reset

Invalid

Run

Stop

Reset

Invalid

Run

Stop

Unused Unused Stopwatch timer reset (writing) Stopwatch timer Run/Stop

Stopwatch timer data BCD (1/100 sec)

Stopwatch timer data BCD (1/10 sec)

Unused Timer 0 counter mode selection Timer 0 function selection (for event counter mode) Timer 0 pulse polarity selection (for event counter mode) TOUT output channel selection TOUT output control Prescaler 1 source clock selection Prescaler 0 source clock selection Prescaler 0

division ratio selection

[PTPS01, 00] Division ratio

Timer 0 reset (reload) Timer 0 Run/Stop Prescaler 1

division ratio selection

[PTPS11, 10] Division ratio

Timer 1 reset (reload) Timer 1 Run/Stop MSB

Programmable timer 0 reload data (low-order 4 bits) LSB

MSB Programmable timer 0 reload data (high-order 4 bits) LSB

MSB Programmable timer 1 reload data (low-order 4 bits) LSB

MSB Programmable timer 1 reload data (high-order 4 bits) LSB

MSB Programmable timer 0 data (low-order 4 bits) LSB

MSB Programmable timer 0 data (high-order 4 bits) LSB

MSB Programmable timer 1 data (low-order 4 bits) LSB

MSB Programmable timer 1 data (high-order 4 bits) LSB

1/111/421/3231/256

20 EPSON S1C63558 TECHNICAL MANUAL

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map)

Table 4.1.1 (g) I/O memory map (FFE2H–FFF7H)

Address Comment

FFE2H

FFE3H

FFE4H

FFE5H

EIT3 EIT2 EIT1 EIT0

FFE6H

FFE7H

FFE8H

FFE9H

FFEAH

FFF2H

FFF3H

FFF4H

FFF5H

FFF6H

FFF7H

D3 D2

00EIPT1 EIPT0

R R/W

0 EISER EISTR EISRC

R R/W

000EIK0

000EIK1

D1 D0 Name Init

R R/W

0 0

EIPT1

EIPT0 0 EISER

EISTR EISRC 0 0 0

0 0 0

R/W

00EISW1 EISW10

R R/W

0 EISERS EISTRS EISRCS

R R/W

000EID

R R/W

00EIRDET EICDET

R R/W

00IPT1 IPT0

0 0 EISW1

EISW10

EISERS

EISTRS

EISRCS

0 0 0

0 0

EIRDET EICDET

0 0

R R/W

0 ISER ISTR ISRC

R R/W

000IK0

R R/W

000IK1

R R/W

0 0 0

IT3 IT2 IT1 IT0

R/W

00ISW1 ISW10

R R/W

0 0

ISW10

EIK0

EIK1 EIT3 EIT2 EIT1 EIT0

EID

IPT1 IPT0

ISER ISTR ISRC

IK0

IK1 IT3 IT2 IT1 IT0

ISW1

∗

–

∗

–

∗

–

∗

–

∗

–

∗

–

∗

–

∗

–

∗

–

∗

–

∗

–

∗

–

∗

–

∗

–

∗

–

∗

–

∗

–

∗

–

∗

–

∗

–

∗

–

∗

–

∗

–

∗

–

∗

–

∗

–

∗

–

∗

–

∗1

∗

00Enable

∗

0 0 0

∗

Enable

Enable Enable Enable

Mask Mask

Mask Mask Mask

0 Enable Mask

∗

0 Enable Mask 0

Enable Enable Enable Enable

Enable

Enable Enable Enable

Mask Mask Mask Mask

Mask Mask

Mask Mask Mask

0 0 0

∗

00Enable

∗

0 0 0

∗

0 Enable Mask

∗

00Enable

∗

0 0

∗

0 0 0

∗

0 0 0 0 0

∗

0 0

Enable

(R) Yes (W)

Reset

(R) Yes (W)

Reset

(R) Yes (W)

Reset

(R) Yes (W)

Reset

(R) Yes (W)

Reset

(R) Yes (W)

Reset

Mask Mask

(R) No (W)

Invalid

(R) No (W)

Invalid

(R) No (W)

Invalid

(R) No (W)

Invalid

(R) No (W)

Invalid

(R) No (W)

Invalid

Unused Unused Interrupt mask register (Programmable timer 1) Interrupt mask register (Programmable timer 0) Unused Interrupt mask register (Serial I/F (1) error) Interrupt mask register (Serial I/F (1) transmit completion) Interrupt mask register (Serial I/F (1) receive completion) Unused Unused Unused Interrupt mask register (K00–K03) Unused Unused Unused Interrupt mask register (K10–K13) Interrupt mask register (Clock timer 1 Hz) Interrupt mask register (Clock timer 2 Hz) Interrupt mask register (Clock timer 8 Hz) Interrupt mask register (Clock timer 32 Hz) Unused Unused Interrupt mask register (Stopwatch timer 1 Hz) Interrupt mask register (Stopwatch timer 10 Hz) Unused Interrupt mask register (Serial I/F (2) error) Interrupt mask register (Serial I/F (2) transmit completion) Interrupt mask register (Serial I/F (2) receive completion) Unused Unused Unused Interrupt mask register (Dialer) Unused Unused Interrupt mask register (FSK demodulator ring detection) Interrupt mask register (FSK demodulator carrier detection) Unused Unused Interrupt factor flag (Programmable timer 1) Interrupt factor flag (Programmable timer 0) Unused Interrupt factor flag (Serial I/F (1) error) Interrupt factor flag (Serial I/F (1) transmit completion) Interrupt factor flag (Serial I/F (1) receive completion) Unused Unused Unused Interrupt factor flag (K00–K03) Unused Unused Unused Interrupt factor flag (K10–K13) Interrupt factor flag (Clock timer 1 Hz) Interrupt factor flag (Clock timer 2 Hz) Interrupt factor flag (Clock timer 8 Hz) Interrupt factor flag (Clock timer 32 Hz) Unused Unused Interrupt factor flag (Stopwatch timer 1 Hz) Interrupt factor flag (Stopwatch timer 10 Hz)

S1C63558 TECHNICAL MANUAL EPSON 21

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map)

Table 4.1.1 (h) I/O memory map (FFF8H–FFFAH)

Address Comment

FFF8H

FFF9H

FFFAH

D3 D2

0 ISERS ISTRS ISRCS

R R/W

000ID

00IRDET ICDET

R R/W

D1 D0 Name Init

R R/W

ISERS

ISTRS ISRCS 0 0 0

0 0

IRDET

ICDET

∗1 ∗

0 0 0

∗

0 0

(R)

Yes

(W)

Reset

Invalid

(R)

Yes

(W)

Reset

Invalid

(R)

Yes

(W)

Reset

Invalid

Unused Interrupt factor flag (Serial I/F (2) error) Interrupt factor flag (Serial I/F (2) transmit completion) Interrupt factor flag (Serial I/F (2) receive completion) Unused Unused Unused Interrupt factor flag (Dialer) Unused Unused Interrupt factor flag (FSK demodulator ring detection) Interrupt factor flag (FSK demodulator carrier detection)

∗

–

∗

–

∗

–

∗

–

∗

–

∗

–

22 EPSON S1C63558 TECHNICAL MANUAL

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Watchdog Timer)

4.2 Watchdog Timer

4.2.1 Configuration of watchdog timer

The S1C63558 has a built-in watchdog timer that operates with a 256 Hz divided clock from the OSC1 as the source clock. The watchdog timer starts operating after initial reset, however, it can be stopped by the software. The watchdog timer must be reset cyclically by the software while it operates. If the watchdog timer is not reset in at least 3–4 seconds, it generates a non-maskable interrupt (NMI) to the CPU. Figure 4.2.1.1 is the block diagram of the watchdog timer.

OSC1 dividing signal 256 Hz

Watchdog timer enable signal

Watchdog timer reset signal

Fig. 4.2.1.1 Watchdog timer block diagram

The watchdog timer contains a 10-bit binary counter, and generates the non-maskable interrupt when the last stage of the counter (0.25 Hz) overflows. Watchdog timer reset processing in the program's main routine enables detection of program overrun, such as when the main routine's watchdog timer processing is bypassed. Ordinarily this routine is incorporated where periodic processing takes place, just as for the timer interrupt routine. The watchdog timer operates in the HALT mode. If a HALT status continues for 3–4 seconds, the nonmaskable interrupt releases the HALT status.

Watchdog timer

Non-maskable interrupt (NMI)

4.2.2 Interrupt function

If the watchdog timer is not reset periodically, the non-maskable interrupt (NMI) is generated to the core CPU. Since this interrupt cannot be masked, it is accepted even in the interrupt disable status (I flag = "0"). However, it is not accepted when the CPU is in the interrupt mask state until SP1 and SP2 are set as a pair, such as after initial reset or during re-setting the stack pointer. The interrupt vector of NMI is assigned to 0100H in the program memory.

S1C63558 TECHNICAL MANUAL EPSON 23

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Watchdog Timer)

4.2.3 I/O memory of watchdog timer

Table 4.2.3.1 shows the I/O address and control bits for the watchdog timer.

Table 4.2.3.1 Control bits of watchdog timer

Address Comment

FF07H

*1 Initial value at initial reset *2 Not set in the circuit *3 Constantly "0" when being read

WDEN: Watchdog timer enable register (FF07H•D1)

Selects whether the watchdog timer is used (enabled) or not (disabled).

When "1" is written: Enabled When "0" is written: Disabled

When "1" is written to the WDEN register, the watchdog timer starts count operation. When "0" is written, the watchdog timer does not count and does not generate the interrupt (NMI). At initial reset, this register is set to "1".

D3 D2

00WDEN WDRST

D1 D0 Name Init

R/W WR

Reading: Valid

∗

WDEN

WDRST

∗1

∗

Enable

Disable

Reset

Invalid

Unused Unused Watchdog timer enable Watchdog timer reset (writing)

–

∗

Reset

WDRST: Watchdog timer reset (FF07H•D0)

Resets the watchdog timer.

When "1" is written: Watchdog timer is reset When "0" is written: No operation

Reading: Always "0"

When "1" is written to WDRST, the watchdog timer is reset and restarts immediately after that. When "0" is written, no operation results. This bit is dedicated for writing, and is always "0" for reading.

4.2.4 Programming notes

(1) When the watchdog timer is being used, the software must reset it within 3-second cycles.

(2) Because the watchdog timer is set in operation state by initial reset, set the watchdog timer to disabled

state (not used) before generating an interrupt (NMI) if it is not used.

24 EPSON S1C63558 TECHNICAL MANUAL

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Oscillation Circuit)

4.3 Oscillation Circuit

4.3.1 Configuration of oscillation circuit

The S1C63558 has two oscillation circuits (OSC1 and OSC3). OSC1 is a crystal oscillation circuit that supplies the operating clock to the CPU and peripheral circuits. OSC3 is a ceramic oscillation circuit. When processing with the S1C63558 requires high-speed operation, the CPU operating clock can be switched from OSC1 to OSC3 by the software. Figure 4.3.1.1 is the block diagram of this oscillation system.

OSC1 oscillation circuit

Divider

To peripheral circuits

OSC3 oscillation circuit

Oscillation system

voltage regulator

Clock

switch

To CPU

CPU clock selection signal

Oscillation circuit control signal

Fig. 4.3.1.1 Oscillation system block diagram

4.3.2 OSC1 oscillation circuit

The OSC1 crystal oscillation circuit generates the main clock for the CPU and the peripheral circuits. The oscillation frequency is 32.768 kHz (Typ.). Figure 4.3.2.1 is the block diagram of the OSC1 oscillation circuit.

OSC1

X'tal

OSC2

Fig. 4.3.2.1 OSC1 oscillation circuit

As shown in Figure 4.3.2.1, the crystal oscillation circuit can be configured simply by connecting the crystal oscillator (X'tal) of 32.768 kHz (Typ.) between the OSC1 and OSC2 terminals and the trimmer capacitor (C

GX) between the OSC1 and VSS terminals.

To CPU (and peripheral circuits)

S1C63558 TECHNICAL MANUAL EPSON 25

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Oscillation Circuit)

4.3.3 OSC3 oscillation circuit

The S1C63558 has built-in the OSC3 oscillation circuit that generates the CPU's sub-clock (3.58 MHz) for high speed operation and the source clock for peripheral circuits needing a high speed clock (programmable timer, FOUT output). To configure a ceramic oscillation circuit, a ceramic oscillator and two capacitors (gate and drain capacitance) are required. Figure 4.3.3.1 is the block diagram of the OSC3 oscillation circuit.

OSC3

Ceramic

OSC4

To CPU

(and some peripheral circuits)

Oscillation circuit control signal

Fig. 4.3.3.1 OSC3 oscillation circuit

As shown in Figure 4.3.3.1, the ceramic oscillation circuit can be configured by connecting the ceramic oscillator (3.58 MHz) between the OSC3 and OSC4 terminals, capacitor CGC between the OSC3 and OSC4 terminals, and capacitor C

DC between the OSC4 and VSS terminals. For both CGC and CDC, connect

capacitors that are about 30 pF. To reduce current consumption of the OSC3 oscillation circuit, oscillation can be stopped by the software (OSCC register).

4.3.4 Switching the CPU operating clock

The CPU system clock is switched to OSC1 or OSC3 by the software (CLKCHG register). When OSC3 is to be used as the CPU system clock, first turn the OSC3 oscillation ON and switch the clock after waiting 5 msec or more for oscillation stabilization. When switching from OSC3 to OSC1, turn the OSC3 oscillation circuit OFF after switching the clock.

OSC1

→

OSC3 OSC3 → OSC1

1. Set OSCC to "1" (OSC3 oscillation ON). 1. Set CLKCHG to "0" (OSC3 → OSC1).

2. Maintain 5 msec or more. 2. Set OSCC to "0" (OSC3 oscillation OFF).

3. Set CLKCHG to "1" (OSC1 → OSC3).

Note: When switching the clock form OSC3 to OSC1, use a separate instruction for switching the OSC3

oscillation OFF. An error in the CPU operation can result if this processing is performed at the same time by the one instruction.

4.3.5 Clock frequency and instruction execution time

Table 4.3.5.1 shows the instruction execution time according to each frequency of the system clock.

Table 4.3.5.1 Clock frequency and instruction execution time

Clock frequency

OSC1: 32.768 kHz OSC3: 3.58 MHz

26 EPSON S1C63558 TECHNICAL MANUAL

1-cycle instruction 2-cycle instruction 3-cycle instruction

Instruction execution time (µsec)

61 122 183

0.56 1.12 1.68

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Oscillation Circuit)

4.3.6 I/O memory of oscillation circuit

Table 4.3.6.1 shows the I/O address and the control bits for the oscillation circuit.

Table 4.3.6.1 Control bits of oscillation circuit

Address Comment

CLKCHG OSCC 0 Dummy

FF00H

*1 Initial value at initial reset *2 Not set in the circuit *3 Constantly "0" when being read

OSCC: OSC3 oscillation control register (FF00H•D2)

Controls oscillation ON/OFF for the OSC3 oscillation circuit.

When "1" is written: OSC3 oscillation ON When "0" is written: OSC3 oscillation OFF

When it is necessary to operate the CPU at high speed, set OSCC to "1". At other times, set it to "0" to reduce current consumption. At initial reset, this register is set to "0".

D3 D2

Reading: Valid

D1 D0 Name Init

CLKCHG

OSCC

∗

R R/WR/W

–

Dummy

∗1

0 0

∗

OSC3OnOSC1

Off

CPU clock switch OSC3 oscillation On/Off Unused General-purpose register

CLKCHG: CPU system clock switching register (FF00H•D3)

The CPU's operation clock is selected with this register.

When "1" is written: OSC3 clock is selected When "0" is written: OSC1 clock is selected

Reading: Valid

When the CPU clock is to be OSC3, set CLKCHG to "1"; for OSC1, set CLKCHG to "0". After turning the OSC3 oscillation ON (OSCC = "1"), switching of the clock should be done after waiting 5 msec or more. At initial reset, this register is set to "0".

4.3.7 Programming notes

(1) It takes at least 5 msec from the time the OSC3 oscillation circuit goes ON until the oscillation stabi-

lizes. Consequently, when switching the CPU operation clock from OSC1 to OSC3, do this after a minimum of 5 msec have elapsed since the OSC3 oscillation went ON. Further, the oscillation stabilization time varies depending on the external oscillator characteristics and conditions of use, so allow ample margin when setting the wait time.

(2) When switching the clock form OSC3 to OSC1, use a separate instruction for switching the OSC3

oscillation OFF. An error in the CPU operation can result if this processing is performed at the same time by the one instruction.

(3) The internal operating voltage of V

voltage regardless of the operating clock selected.

D1 is fixed at 2.2 V. So it is not necessary to control the operating

S1C63558 TECHNICAL MANUAL EPSON 27

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports)

4.4 Input Ports (K00–K03 and K10–K13)

4.4.1 Configuration of input ports

The S1C63558 has eight bits general-purpose input ports. Each of the input port terminals (K00–K03, K10–K13) provides internal pull-up resistor. Pull-up resistor can be selected for each bit with the mask option. Figure 4.4.1.1 shows the configuration of input port.

VDD

Interrupt request

Kxx

Data bus

Address

VSS

Mask option

Fig. 4.4.1.1 Configuration of input port

Selection of "With pull-up resistor" with the mask option suits input from the push switch, key matrix, and so forth. When "Gate direct" is selected, the port can be used for slide switch input and interfacing with other LSIs.

4.4.2 Interrupt function

All eight bits of the input ports (K00–K03, K10–K13) provide the interrupt function. The conditions for issuing an interrupt can be set by the software. Further, whether to mask the interrupt function can be selected by the software. Figure 4.4.2.1 shows the configuration of K00–K03 (K10–K13) interrupt circuit.

K00, 10

Input comparison register (KCP00, 10)

Interrupt selection register (SIK00, 10)

Data bus

Address

K01, 11

K02, 12

K03, 13

Address

Interrupt factor flag (IK0, 1)

Address

Interrupt mask register (EIK0, 1)

Interrupt request

Address

Fig. 4.4.2.1 Input interrupt circuit configuration

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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports)

The interrupt selection register (SIK) and input comparison register (KCP) are individually set for the input ports K00–K03 and K10–K13, and can specify the terminals for generating interrupt and interrupt timing. The interrupt selection registers (SIK00–SIK03, SIK10–SIK13) select what input of K00–K03 and K10–K13 to use for the interrupt. Writing "1" into an interrupt selection register incorporates that input port into the interrupt generation conditions. The changing the input port where the interrupt selection register has been set to "0" does not affect the generation of the interrupt. The input interrupt timing can select that the interrupt be generated at the rising edge of the input or that it be generated at the falling edge according to the set value of the input comparison registers (KCP00– KCP03, KCP10–KCP13). By setting these two conditions, the interrupt for K00–K03 or K10–K13 is generated when input ports in which an interrupt has been enabled by the input selection registers and the contents of the input comparison registers have been changed from matching to no matching. The interrupt mask registers (EIK0, EIK1) enable the interrupt mask to be selected for K00–K03 and K10– K13. When the interrupt is generated, the interrupt factor flag (IK0, IK1) is set to "1". Figure 4.4.2.2 shows an example of an interrupt for K00–K03.

Interrupt selection register

SIK031SIK021SIK011SIK00

With the above setting, the interrupt of K00–K03 is generated under the following condition:

Input comparison register

KCP031KCP020KCP011KCP00

Input port

K031K020K011K00

(1)

(Initial value)

K031K020K011K00

(2)

K030K020K011K00

(3)

K030K021K011K00

(4)

Interrupt generation

Because K00 interrupt is set to disable, interrupt will be generated when no matching occurs between the contents of the 3 bits K01–K03 and the 3 bits input comparison register KCP01–KCP03.

Fig. 4.4.2.2 Example of interrupt of K00–K03

K00 interrupt is disabled by the interrupt selection register (SIK00), so that an interrupt does not occur at (2). At (3), K03 changes to "0"; the data of the terminals that are interrupt enabled no longer match the data of the input comparison registers, so that interrupt occurs. As already explained, the condition for the interrupt to occur is the change in the port data and contents of the input comparison registers from matching to no matching. Hence, in (4), when the no matching status changes to another no matching status, an interrupt does not occur. Further, terminals that have been masked for interrupt do not affect the conditions for interrupt generation.

4.4.3 Mask option

Internal pull-up resistor can be selected for each of the eight bits of the input ports (K00–K03, K10–K13) with the input port mask option. When "Gate direct" is selected, take care that the floating status does not occur for the input. Select "With pull-up resistor" for input ports that are not being used.

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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports)

4.4.4 I/O memory of input ports

Table 4.4.4.1 shows the I/O addresses and the control bits for the input ports.

Table 4.4.4.1 Control bits of input ports

Address Comment

SIK03 SIK02 SIK01 SIK00

FF20H

FF21H

KCP03 KCP02 KCP01 KCP00

FF22H

SIK13 SIK12 SIK11 SIK10

FF24H

FF25H

KCP13 KCP12 KCP11 KCP10

FF26H

FFE4H

FFE5H

FFF4H

FFF5H

*1 Initial value at initial reset *2 Not set in the circuit *3 Constantly "0" when being read

D3 D2

D1 D0 Name Init

R/W

K03 K02 K01 K00

KCP03 KCP02

R/W

KCP01 KCP00

R/W

K13 K12 K11 K10

KCP13 KCP12

R/W

000EIK0

R R/W

000EIK1

R R/W

000IK0

R R/W

000IK1

R R/W

KCP11 KCP10 0 0 0

0 0 0

SIK03

SIK02

SIK01

SIK00

K03 K02 K01 K00

SIK13

SIK12

SIK11

SIK10

K13 K12 K11 K10

EIK0

EIK1

IK0

IK1

∗1

0 0 0 0

∗

–

∗

–

∗

–

∗

–

1 1 1 1 0 0 0 0

∗

–

∗

–

∗

–

∗

–

1 1 1 1

∗

–

∗

–

∗

–

0 Enable Mask

∗

–

∗

–

∗

–

0 Enable Mask

∗

–

∗

–

∗

–

∗

–

∗

–

∗

–

Enable

Disable

Enable

Disable

Enable

Disable

Enable

Disable

High

Low

High

Low

High

Low

High

Low

Enable

Disable

Enable

Disable

Enable

Disable

Enable

Disable

High

Low

High

Low

High

Low

High

Low

(R)

Yes

(W)

Reset

Invalid

(R)

Yes

(W)

Reset

Invalid

K00–K03 interrupt selection register

K00–K03 input port data

K00–K03 input comparison register

K10–K13 interrupt selection register

K10–K13 input port data

K10–K13 input comparison register

Unused Unused Unused Interrupt mask register (K00–K03) Unused Unused Unused Interrupt mask register (K10–K13) Unused Unused Unused Interrupt factor flag (K00–K03) Unused Unused Unused Interrupt factor flag (K10–K13)

K00–K03: K0 port input port data (FF21H) K10–K13: K1 port input port data (FF25H)

Input data of the input port terminals can be read with these registers.

When "1" is read: High level When "0" is read: Low level

Writing: Invalid

The reading is "1" when the terminal voltage of the eight bits of the input ports (K00–K03, K10–K13) goes high (V

DD), and "0" when the voltage goes low (VSS).

These bits are dedicated for reading, so writing cannot be done.

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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports)

SIK00–SIK03: K0 port interrupt selection register (FF20H) SIK10–SIK13: K1 port interrupt selection register (FF24H)

Selects the ports to be used for the K00–K03 and K10–K13 input interrupts.

When "1" is written: Enable When "0" is written: Disable

Reading: Valid

Enables the interrupt for the input ports (K00–K03, K10–K13) for which "1" has been written into the interrupt selection registers (SIK00–SIK03, SIK10–SIK13). The input port set for "0" does not affect the interrupt generation condition. At initial reset, these registers are set to "0".

KCP00–KCP03: K0 port input comparison register (FF22H) KCP10–KCP13: K1 port input comparison register (FF26H)

Interrupt conditions for terminals K00–K03 and K10–K13 can be set with these registers.

When "1" is written: Falling edge When "0" is written: Rising edge

Reading: Valid

The interrupt conditions can be set for the rising or falling edge of input for each of the eight bits (K00– K03 and K10–K13), through the input comparison registers (KCP00–KCP03 and KCP10–KCP13). For KCP00–KCP03, a comparison is done only with the ports that are enabled by the interrupt among K00–K03 by means of the SIK00–SIK03 registers. For KCP10–KCP13, a comparison is done only with the ports that are enabled by the interrupt among K10–K13 by means of the SIK10–SIK13 registers. At initial reset, these registers are set to "0".

EIK0: K0 input interrupt mask register (FFE4H•D0) EIK1: K1 input interrupt mask register (FFE5H•D0)

Masking the interrupt of the input port can be selected with these registers.

When "1" is written: Enable When "0" is written: Mask

Reading: Valid

With these registers, masking of the input port interrupt can be selected for each of the two systems (K00– K03, K10–K13). At initial reset, these registers are set to "0".

IK0: K0 input interrupt factor flag (FFF4H•D0) IK1: K1 input interrupt factor flag (FFF5H•D0)

These flags indicate the occurrence of input interrupt.

When "1" is read: Interrupt has occurred When "0" is read: Interrupt has not occurred

When "1" is written: Flag is reset When "0" is written: Invalid

The interrupt factor flags IK0 and IK1 are associated with K00–K03 and K10–K13, respectively. From the status of these flags, the software can decide whether an input interrupt has occurred. The interrupt factor flag is set to "1" when the interrupt condition is established regardless of the interrupt mask register setting. However, the interrupt does not occur to the CPU when the interrupt is masked. These flags are reset to "0" by writing "1" to them. After an interrupt occurs, the same interrupt will occur again if the interrupt enabled state (I flag = "1") is set or the RETI instruction is executed unless the interrupt factor flag is reset. Therefore, be sure to reset (write "1" to) the interrupt factor flag in the interrupt service routine before shifting to the interrupt enabled state. At initial reset, these flags are set to "0".

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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports)

4.4.5 Programming notes

(1) When input ports are changed from low to high by pull-up resistors, the rise of the waveform is

delayed on account of the time constant of the pull-up resistor and input gate capacitance. Hence, when fetching input ports, set an appropriate waiting time. Particular care needs to be taken of the key scan during key matrix configuration. Make this waiting time the amount of time or more calculated by the following expression. 10 × C × R

C: terminal capacitance 5 pF + parasitic capacitance ? pF R: pull-up resistance 330 kΩ

(2) The K13 terminal functions as the clock input terminal for the programmable timer, and the input

signal is shared with the input port and the programmable timer. Therefore, when the K13 terminal is set to the clock input terminal for the programmable timer, take care of the interrupt setting.

(3) After an interrupt occurs, the same interrupt will occur again if the interrupt enabled state (I flag =

"1") is set or the RETI instruction is executed unless the interrupt factor flag is reset. Therefore, be sure to reset (write "1" to) the interrupt factor flag in the interrupt service routine before shifting to the interrupt enabled state.

32 EPSON S1C63558 TECHNICAL MANUAL

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports)

4.5 Output Ports (R00–R03, R10–R13 and R20–R23)

4.5.1 Configuration of output ports

The S1C63558 has 12 bits general output ports. Output specifications of the output ports can be selected individually with the mask option. Two kinds of output specifications are available: complementary output and N-channel open drain output. Figure 4.5.1.1 shows the configuration of the output port.

Address

VDD

High impedance

control register

Mask option

Data register

Rxx

Data bus

Address

VSS

Fig. 4.5.1.1 Configuration of output port

The R00 to R03 output terminals are shared with the buzer/clock outputs (XBZ, BZ, TOUT, FOUT). The R10 to R13 output terminals are shared with the tone/pulse dialer outputs (XTMUTE, XRMUTE, HDO, HFO). These functions are selected by the software. At initial reset, these are all set to the general purpose output port. Table 4.5.1.1 shows the setting of the output terminals by function selection.

Table 4.5.1.1 Function setting of output terminals

Terminal

name

R00 R01 R02 R03 R10 R11 R12 R13

R20–R23

at initial reset

R00 (HIGH output) R01 (HIGH output) R02 (HIGH output) R03 (HIGH output) R10 (HIGH output) R11 (HIGH output) R12 (HIGH output) R13 (HIGH output) R20–R23 (HIGH output)

FOUT

R00 R01 R02

FOUT

R10 R11 R12 R13

R20–R23

TOUT

R00 R01

TOUT

R03 R10 R11 R12 R13

R20–R23

R00

BZ R02 R03 R10 R11 R12 R13

R20–R23

Special outputTerminal status

XBZ

R01 R02 R03 R10 R11 R12 R13

R20–R23

HFO

R00 R01 R02 R03 R10 R11 R12

HFO

R20–R23

HDO

R00 R01 R02 R03 R10 R11

HDO

R13

R20–R23

XRMUTE

R00 R01 R02 R03 R10

XRMUTE

R12 R13

R20–R23

XTMUTE

R00 R01 R02 R03

XTMUTE

R11 R12 R13

R20–R23

When using the output port as the special output port, the data register must be fixed at "1" and the high impedance control register must be fixd at "0" (data output).

4.5.2 Mask option

Output specifications of the output ports can be selected with the mask option. Either complementary output or N-channel open drain output can be selected individually (1-bit units). However, when N-channel open drain output is selected, do not apply a voltage exceeding the power supply voltage to the output port.

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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports)

4.5.3 High impedance control

The terminal output status of the output ports can be set to a high impedance status. This control is done using the high impedance control register (RxxHIZ) corresponding to each output port (Rxx). When "1" is written to the high impedance control register, the corresponding output port terminal goes into high impedance status. When "0" is written, the port outputs a signal according to the data register.

4.5.4 Special output

In addition to the regular DC output, special output can be selected for the output ports R00–R03 and R10–R13 as shown in Table 4.5.4.1 with the software. Figure 4.5.4.1 shows the configuration of the R00–R03 and R10–R13 output ports.

Table 4.5.4.1 Special output

Terminal

R13 R12 R11 R10 R03 R02 R01 R00

Special output

HFO

HDO XRMUTE XTMUTE

FOUT TOUT

XBZ

Output control register

CHFO

CHDO

CRMO

CTMO FOUTE PTOUT BZOUT

XBZOUT

Data bus

FOUT

FOUTE

R03

TOUT

PTOUT

R02

BZOUT

R01

XBZ

XBZOUT

R00

R03 (FOUT)

R02 (TOUT)

R01 (BZ)

R00 (XBZ)

Data bus

HFO

CHFO

R13

R13HIZ

HDO

CHDO

R12

R12HIZ XRMUTE

CRMO

R11

R11HIZ XTMUTE

CTMO

R10

R10HIZ

R13 (HFO)

R12 (HDO)

R11 (XRMUTE)

R10 (XTMUTE)

Fig. 4.5.4.1(a) Configuration of R00–R03 output ports Fig. 4.5.4.1(b) Configuration of R10–R13 output ports

At initial reset, the output port data register is set to "1" and the high impedance control register is set to "0". Consequently, the output terminal goes high (V

DD).

When using the output port (R00–R03, R10–R13) as the special output port, fix the data register (R00–R03, R10–R13) at "1" and the high impedance control register (R00HIZ–R03HIZ, R10HIZ–R13HIZ) at "0" (data output). The respective signal should be turned ON and OFF using the special output control register.

34 EPSON S1C63558 TECHNICAL MANUAL

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports)

Note: • Be aware that the output terminal is fixed at a low (VSS) level the same as the DC output if "0" is

written to the R00–R03 and R10–R13 registers when the special output has been selected.

• Be aware that the output terminal shifts into high impedance status when "1" is written to the high impedance control register (R00HIZ–R03HIZ, R10HIZ–R13HIZ).

•A hazard may occur when the special output signal is turned ON and OFF by software.

• XBZ (R00)

The R00 terminal can output an XBZ signal. The XBZ signal is the buzzer inverted signal that is output from the sound generator, and can be used to drive a piezoelectric buzzer with the BZ signal. To output the XBZ signal, set the R00 port as the XBZ output by writing "1" to the XBZOUT register and fix the R00 register at "1" and the R00HIZ register at "0". Use the BZE register for controlling (ON/OFF) the XBZ signal output. Refer to Section 4.12, "Sound Generator" for details of the buzzer signal and controlling method.

• BZ (R01)

The R01 terminal can output a BZ signal. The BZ signal is the buzzer signal that is output from the sound generator. To output the BZ signal, set the R01 port as the BZ output by writing "1" to the BZOUT register and fix the R01 register at "1" and the R01HIZ register at "0". Use the BZE register for controlling (ON/OFF) the BZ signal output. Refer to Section 4.12, "Sound Generator" for details of the buzzer signal and controlling method.

•TOUT (R02)

The R02 terminal can output a TOUT signal. The TOUT signal is the clock that is output from the programmable timer, and can be used to provide a clock signal to an external device. To output the TOUT signal, fix the R02 register at "1" and the R02HIZ register at "0", and turn the signal ON and OFF using the PTOUT register. It is, however, necessary to control the programmable timer. Refer to Section 4.10, "Programmable Timer" for details of the TOUT signal and controlling method.

• FOUT (R03)

The R03 terminal can output an FOUT signal. The FOUT signal is a clock (f f

OSC1 clock has divided in the internal circuit, and can be used to provide a clock signal to an external

device. To output the FOUT signal, fix the R03 register at "1" and the R03HIZ register at "0", and turn the signal ON and OFF using the FOUTE register. The frequency of the output clock may be selected from among 4 types shown in Table 4.5.4.2 by setting the FOFQ0 and FOFQ1 registers.

When fOSC3 is selected for the FOUT signal frequency, it is necessary to control the OSC3 oscillation circuit before output. Refer to Section 4.3, "Oscillation Circuit", for the control and notes. Figure 4.5.4.2 shows the output waveform of the FOUT signal.

OSC1 or fOSC3) that is output from the oscillation circuit or a clock that the

Table 4.5.4.2 FOUT clock frequency

FOFQ1

fOSC1: Clock that is output from the OSC1 oscillation circuit fOSC3: Clock that is output from the OSC3 oscillation circuit

FOFQ0

1 1 0 0

1 0 1 0

Clock frequency

OSC3

OSC1

× 1/8

OSC1

× 1/64

S1C63558 TECHNICAL MANUAL EPSON 35

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports)

R03HIZ register

R03 register

FOUTE register

FOUT output

Fix at "0"

Fix at "1"

"1""0" "0"

Fig. 4.5.4.2 Output waveform of FOUT signal

• XTMUTE (R10)

The R10 terminal can output an XTMUTE signal. The XTMUTE signal is the transmitter mute signal used for the telephone function. To output the XTMUTE signal, set the R10 port as the XTMUTE output by writing "1" to the CTMO register and fix the R10 register at "1" and the R10HIZ register at "0". Use the CTMUTE register for controlling the XTMUTE signal output. Refer to Section 4.14, "Telephone Function" for details of the signal and controlling method.

• XRMUTE (R11)

The R11 terminal can output an XRMUTE signal. The XRMUTE signal is the receiver mute signal used for the telephone function. To output the XRMUTE signal, set the R11 port as the XRMUTE output by writing "1" to the CRMO register and fix the R11 register at "1" and the R11HIZ register at "0". Use the CRMUTE register for controlling the XRMUTE signal output. Refer to Section 4.14, "Telephone Function" for details of the signal and controlling method.

• HDO (R12)

The R12 terminal can output a HDO signal. The HDO signal is the hold line signal used for the telephone function. To output the HDO signal, set the R12 port as the HDO output by writing "1" to the CHDO register and fix the R12 register at "1" and the R12HIZ register at "0". Use the HOLD register for controlling the HDO signal output. Refer to Section 4.14, "Telephone Function" for details of the signal and controlling method.

• HFO (R13)

The R13 terminal can output a HFO signal. The HFO signal is the hand free signal used for the telephone function. To output the HFO signal, set the R13 port as the HFO output by writing "1" to the CHFO register and fix the R13 register at "1" and the R13HIZ register at "0". Use the HF register for controlling the HFO signal output. Refer to Section 4.14, "Telephone Function" for details of the signal and controlling method.

36 EPSON S1C63558 TECHNICAL MANUAL

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports)

4.5.5 I/O memory of output ports

Table 4.5.5.1 shows the I/O addresses and control bits for the output ports.

Table 4.5.5.1 Control bits of output ports

Address Comment

FOUTE 0 FOFQ1 FOFQ0

FF06H

CHFO CHDO CRMO CTMO

FF13H

R03HIZ R02HIZ R01HIZ R00HIZ

FF30H

(FOUT)

FF31H

R13HIZ R12HIZ R11HIZ R10HIZ

FF32H

FF33H

(HFO)

R23HIZ R22HIZ R21HIZ R20HIZ

FF34H

FF35H

FF65H

CHSEL PTOUT CKSEL1 CKSEL0

FFC1H

*1 Initial value at initial reset *2 Not set in the circuit *3 Constantly "0" when being read

D3 D2

D1 D0 Name Init

R/W R R/W

R/W

R03

R02

R01 (BZ)

R00

(XBZ)

(TOUT)

R/W

R13

R12

R11

(HDO)

(XRMUTE)

R10

(XTMUTE)

R/W

R23 R22 R21 R20

R/W

00BZOUT XBZOUT

R R/W

R/W

FOUTE

∗

0 FOFQ1 FOFQ0

CHFO CHDO CRMO

CTMO R03HIZ R02HIZ R01HIZ R00HIZ

R03 R02 R01

R00 R13HIZ R12HIZ R11HIZ R10HIZ

R13

R12

R11

R10 R23HIZ R22HIZ R21HIZ R20HIZ

R23

R22

R21

R20

∗

0 BZOUT

XBZOUT

CHSEL PTOUT

CKSEL1 CKSEL0

∗1

FOUT DC

∗

–

0 0 0

HFO

HDO

XRMUTE

XTMUTE

0 0

Hi-Z

High

Hi-Z

High

Hi-Z

High

∗

–

∗

–

0 0BZXBZDCDC 0

Timer1

OSC3

R03 output selection (R03 should be fixed at "1".) Unused

FOUT frequency selection

R13 output selection (R13 should be fixed at "1".)

R12 output selection (R12 should be fixed at "1".)

R11 output selection (R11 should be fixed at "1".)

R10 output selection (R10 should be fixed at "1".) R03 (FOUTE=0)/FOUT (FOUTE=1) Hi-z control

Output

R02 (PTOUT=0)/TOUT (PTOUT=1) Hi-z control

Output

R01 (BZOUT=0)/BZ (BZOUT=1) Hi-z control

Output

R00 (XBZOUT=0)/XBZ (XBZOUT=1) Hi-z control

Output

R03

Low Low Low

Low Output Output Output Output

Low

output port data (

R02

output port data (

R01

output port data (

R00

[FOFQ1, 0] Frequency

FOUTE=0 PTOUT=0 BZOUT=0 XBZOUT=0

Output Output

R20–R23 Hi-z control

Output Output

Low Low

R20–R23 output port data

Low Low

Unused Unused R01 output selection (R01 should be fixed at "1".) R00 output selection (R00 should be fixed at "1".) TOUT output channel selection

Timer0

TOUT output control

Off

Prescaler 1 source clock selection

OSC1

Prescaler 0 source clock selection

OSC1

/641f

OSC1

) Fix at "1" when ) Fix at "1" when ) Fix at "1" when

) Fix at "1" when

/82f

FOUT TOUT

is used.

XBZ

OSC1

is used. is used.

OSC3

is used.

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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports)

R00HIZ–R03HIZ: R0 port high impedance control register (FF30H) R10HIZ–R13HIZ: R1 port high impedance control register (FF32H) R20HIZ–R23HIZ: R2 port high impedance control register (FF34H)

Controls high impedance output of the output port.

When "1" is written: High impedance When "0" is written: Data output

Reading: Valid

By writing "0" to the high impedance control register, the corresponding output terminal outputs according to the data register. When "1" is written, it shifts into high impedance status. When an output port (R00–R03, R10–R13) is used for special output, fix the corresponding high impedance control register at "0" (data output). At initial reset, these registers are set to "0".

R00–R03: R0 output port data register (FF31H) R10–R13: R1 output port data register (FF33H) R20–R23: R2 output port data register (FF35H)

Set the output data for the output ports.

When "1" is written: High level output When "0" is written: Low level output

Reading: Valid

The output port terminals output the data written in the corresponding data registers without changing it. When "1" is written to the register, the output port terminal goes high (V the output port terminal goes low (V

SS).

DD), and when "0" is written,

When an output port (R00–R03, R10–R13) is used for special output, fix the corresponding data register at "1". At initial reset, these registers are all set to "1".

XBZOUT: R00 output selection register (FF65H•D0)

Selects the R00 terminal function.

When "1" is written: XBZ output When "0" is written: General-purpose DC output

Reading: Valid

When using the R00 terminal for the XBZ output, write "1" to this register. Furthermore, fix the R00 register at "1" and the R00HIZ register at "0". Refer to Section 4.12, "Sound Generator", for controlling the XBZ output. When using the R00 output port for a general-purpose output, fix this register at "0". At initial reset, this register is set to "0".

BZOUT: R01 output selection register (FF65H•D1)

Selects the R01 terminal function.

When "1" is written: BZ output When "0" is written: General-purpose DC output

Reading: Valid

When using the R01 terminal for the BZ output, write "1" to this register. Furthermore, fix the R01 register at "1" and the R01HIZ register at "0". Refer to Section 4.12, "Sound Generator", for controlling the BZ output. When using the R01 output port for a general-purpose output, fix this register at "0". At initial reset, this register is set to "0".

38 EPSON S1C63558 TECHNICAL MANUAL

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports)

PTOUT: TOUT output control register (FFC1H•D2)

Controls the TOUT output.

When "1" is written: TOUT output ON When "0" is written: TOUT output OFF

Reading: Valid

By writing "1" to the PTOUT register when the R02 register has been set to "1" and the R02HIZ register has been set to "0", the TOUT signal is output from the R02 terminal. When "0" is written, the R02 terminal goes high (V

DD).

When using the R02 output port for general-purpose output, fix this register at "0". At initial reset, this register is set to "0".

FOUTE: FOUT output control register (FF06H•D3)

Controls the FOUT output.

When "1" is written: FOUT output ON When "0" is written: FOUT output OFF

Reading: Valid

By writing "1" to the FOUTE register when the R03 register has been set to "1" and the R03HIZ register has been set to "0", an FOUT signal is output from the R03 terminal. When "0" is written, the R03 terminal goes high (V

DD).

When using the R03 output port for general-purpose output, fix this register at "0". At initial reset, this register is set to "0".

FOFQ0, FOFQ1: FOUT frequency selection register (FF06H•D0, D1)

Selects a frequency of the FOUT signal.

Table 4.5.5.2 FOUT clock frequency

FOFQ1

FOFQ0

1 1 0 0

1 0 1 0

Clock frequency

OSC3

OSC1

× 1/8

OSC1

× 1/64

At initial reset, this register is set to "0".

CTMO: R10 output selection register (FF13H•D0)

Selects the R10 terminal function.

When "1" is written: XTMUTE output When "0" is written: General-purpose DC output

Reading: Valid

When using the R10 terminal for the XTMUTE output, write "1" to this register. Furthermore, fix the R10 register at "1" and the R10HIZ register at "0". Refer to Section 4.14, "Telephone Function", for controlling the XTMUTE output. When using the R10 output port for a general-purpose output, fix this register at "0". At initial reset, this register is set to "0".

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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports)

CRMO: R11 output selection register (FF13H•D1)

Selects the R11 terminal function.

When "1" is written: XRMUTE output When "0" is written: General-purpose DC output

Reading: Valid

When using the R11 terminal for the XRMUTE output, write "1" to this register. Furthermore, fix the R11 register at "1" and the R11HIZ register at "0". Refer to Section 4.14, "Telephone Function", for controlling the XRMUTE output. When using the R11 output port for a general-purpose output, fix this register at "0". At initial reset, this register is set to "0".

CHDO: R12 output selection register (FF13H•D2)

Selects the R12 terminal function.

When "1" is written: HDO output When "0" is written: General-purpose DC output

Reading: Valid

When using the R12 terminal for the HDO output, write "1" to this register. Furthermore, fix the R12 register at "1" and the R12HIZ register at "0". Refer to Section 4.14, "Telephone Function", for controlling the HDO output. When using the R12 output port for a general-purpose output, fix this register at "0". At initial reset, this register is set to "0".

CHFO: R13 output selection register (FF13H•D3)

Selects the R13 terminal function.

When "1" is written: HFO output When "0" is written: General-purpose DC output

Reading: Valid

When using the R13 terminal for the HFO output, write "1" to this register. Furthermore, fix the R13 register at "1" and the R13HIZ register at "0". Refer to Section 4.14, "Telephone Function", for controlling the HFO output. When using the R13 output port for a general-purpose output, fix this register at "0". At initial reset, this register is set to "0".

4.5.6 Programming notes

(1) When using an output port (R00–R03, R10–R13) for special output, fix the corresponding data register

(R00–R03, R10–R13) at "1" and the high impedance control register (R00HIZ–R03HIZ, R10HIZ– R13HIZ) at "0" (data output). Be aware that the output terminal is fixed at a low (V written to the data registers when the special output has been selected. Be aware that the output terminal shifts into high impedance status when "1" is written to the high impedance control register.

(2) A hazard may occur when the TOUT, FOUT , BZ or XBZ signal is turned ON and OFF.

(3) When f

OSC3 is selected for the FOUT signal frequency, it is necessary to control the OSC3 oscillation

circuit before output. Refer to Section 4.3, "Oscillation Circuit", for the control and notes.

SS) level the same as the DC output if "0" is

40 EPSON S1C63558 TECHNICAL MANUAL

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (I/O Ports)

4.6 I/O Ports (P00–P03, P10–P13, P20–P23 and P30–P33)

4.6.1 Configuration of I/O ports

The S1C63558 has 16 bits general-purpose I/O ports. Figure 4.6.1.1 shows the configuration of the I/O port.

VDD

PXX

Address

Data bus

Address

Pull-up control register (PUL)

Address

Data

I/O control

Mask option

Fig. 4.6.1.1 Configuration of I/O port

The I/O port terminals P10– P13, P30–P33 are shared with the input/output terminals of the serial interface (1) and (2). The P22 and P23 terminals are shared with the special output (CL, FR) terminals. The software can select these functions to be used. At initial reset, these are all set to the I/O port. Table 4.6.1.1 shows the setting of the input/output terminals by function selection.

Table 4.6.1.1 Function setting of input/output terminals

Terminal

name

P00–P03

P10 P11 P12 P13 P20 P21 P22 P23 P30 P31 P32 P33

P00–P03 (Input & Pull-up *)

at initial reset

P10 (Input & Pull-up *) P11 (Input & Pull-up *) P12 (Input & Pull-up *) P13 (Input & Pull-up *) P20 (Input & Pull-up *) P21 (Input & Pull-up *) P22 (Input & Pull-up *) P23 (Input & Pull-up *) P30 (Input & Pull-up *) P31 (Input & Pull-up *) P32 (Input & Pull-up *) P33 (Input & Pull-up *)

∗ When "with pull-up resistor" is selected by the mask option (high impedance when "gate direct" is set)

Special output Serial I/F (1), (2)Terminal status CL

P00–P03

P10 P11 P12 P13 P20 P21

CL P23 P30 P31 P32 P33

P00–P03

P10 P11 P12 P13 P20 P21 P22

FR P30 P31 P32 P33

Async.

P00–P03

SIN(I)

SOUT(O)

P12 P13 P20 P21 P22 P23

SIN(I)

SOUT(O)

P32 P33

Clk-sync. Master

P00–P03

SIN(I) SOUT(O) SCLK(O)

P13 P20 P21 P22 P23

SIN(I) SOUT(O) SCLK(O)

P33

Clk-sync. Slave

P00–P03

SIN(I)

SOUT(O)

SCLK(I)

SRDY(O)

P20 P21 P22 P23

SIN(I)

SOUT(O)

SCLK(I)

SRDY(O)

When these ports are used as I/O ports, the ports can be set to either input mode or output mode individually (in 1-bit unit). Modes can be set by writing data to the I/O control registers. Refer to Section 4.11, "Serial Interface", for control of the serial interface.

S1C63558 TECHNICAL MANUAL EPSON 41

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (I/O Ports)

4.6.2 Mask option

In the I/O ports, the output specification during output mode can be selected from complementary output and N-channel open drain output by mask option. They are selected in 1-bit units. When N-channel open drain output is selected, do not apply a voltage exceeding the power supply voltage to the port.

The mask option also allows selection of whether the pull-up resistor is used or not during input mode. They are selected in 1-bit units or 4-bit units depending on the terminal group. Ports to be selected in 1-bit units: P20, P21, P22, P23 Ports to be selected in 4-bit units: P00–P03, P10–P13, P30–P33 When "without pull-up" during the input mode is selected, take care that the floating status does not occur.

This option is effective even when I/O ports are used for special output or input/output of the serial interface.

4.6.3 I/O control registers and input/output mode

Input or output mode can be set for the I/O ports by writing data into the corresponding I/O control registers IOCxx.

To set the input mode, write "0" to the I/O control register. When an I/O port is set to input mode, it becomes high impedance status and works as an input port. However, when the pull-up explained in the following section has been set by software, the input line is pulled up only during this input mode.

To set the output mode, write "1" is to the I/O control register. When an I/O port is set to output mode , it works as an output port, it outputs a high level (V (V

SS) when the port output data is "0".

If perform the read out in each mode; when output mode, the register value is read out, and when input mode, the port value is read out.

DD) when the port output data is "1", and a low level

At initial reset, the I/O control registers are set to "0", and the I/O ports enter the input mode.

The I/O control registers of the ports that are set as special output or input/output for the serial interface can be used as general purpose registers that do not affect the I/O control. (See Table 4.6.1.1.)

4.6.4 Pull-up during input mode

A pull-up resistor that operates during the input mode is built into each I/O port of the S1C63558. Mask option can set the use or non-use of this pull-up.

The pull-up resistor becomes effective by writing "1" to the pull-up control register PULxx that corresponds to each port, and the input line is pulled up during the input mode. When "0" has been written, no pull-up is done. At initial reset, the pull-up control registers are set to "1".

The pull-up control registers of the ports in which "without pull-up" have been selected can be used as general purpose registers. Even when "with pull-up" has been selected, the pull-up control registers of the ports, that are set as special output or output for the serial interface, can be used as general purpose registers that do not affect the pull-up control. (See Table 4.6.1.1.) The pull-up control registers of the port, that are set as input for the serial interface, function the same as the I/O port.

42 EPSON S1C63558 TECHNICAL MANUAL

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (I/O Ports)

4.6.5 Special outputs (CL, FR)

The I/O ports P22 and P23 can be used as special output ports that output CL and FR signals by switching the function with software. Since P22 and P23 are set to I/O port (input mode) at initial reset, when using the special outputs, select the special output function using the EXLCDC register. The data registers, I/O control registers and pull-up control registers of the ports set in the special output can be used as general purpose registers that do not affect the output.

When "1" is written to the EXLCDC register, P22 is set to the CL output port and P23 is set to the FR output port. The CL and FR signals are LCD synchronous signal (CL) and LCD flame signal (FR) for externally expanded LCD driver, and are output from the P22 terminal and P23 terminal when the functions are switched by the EXLCDC register. The following tables show the frequencies of the CL and FR signals.

Table 4.6.5.1 CL signal frequency

OSC1 oscillation

frequency

32.768 kHz

OSC1 oscillation

frequency

32.768 kHz

Refer to Section 4.7, "LCD Driver", for control of the LCD drive duty.

When 1/8 duty

is selected

512 Hz

When 1/16 duty

is selected

1,024 Hz

Table 4.6.5.2 FR signal frequency

When 1/8 duty

is selected

32 Hz

When 1/16 duty

is selected

32 Hz

When 1/17 duty

is selected

1,024 Hz

When 1/17 duty

is selected

30.12 Hz

Note: A hazard may occur when the CL signal or FR signal is turned ON or OFF (when the port function

is switched).

Figure 4.6.5.1 shows the output waveforms of CL and FR signals.

CL output (P22 terminal)

FR output (P23 terminal)

When 1/17 duty is selected

CL output (P22 terminal)

FR output (P23 terminal)

When 1/16 duty is selected

CL output (P22 terminal)

FR output (P23 terminal)

When 1/8 duty is selected

Fig. 4.6.5.1 Output waveforms of CL and FR signals

S1C63558 TECHNICAL MANUAL EPSON 43

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (I/O Ports)

4.6.6 I/O memory of I/O ports

Tables 4.6.6.1(a) and (b) show the I/O addresses and the control bits for the I/O ports.

Table 4.6.6.1(a) Control bits of I/O ports

Address Comment

IOC03 IOC02 IOC01 IOC00

FF40H

PUL03 PUL02 PUL01 PUL00

FF41H

FF42H

IOC13 IOC12 IOC11 IOC10

FF44H

PUL13 PUL12 PUL11 PUL10

FF45H

(XSRDY)

FF46H

IOC23 IOC22 IOC21 IOC20

FF48H

PUL23 PUL22 PUL21 PUL20

FF49H

FF4AH

*1 Initial value at initial reset *3 Constantly "0" when being read *2 Not set in the circuit

44 EPSON S1C63558 TECHNICAL MANUAL

D3 D2

D1 D0 Name Init

R/W

P03 P02 P01 P00

R/W

P13

P12

P11

(SOUT)

P10

(SIN)

(XSCLK)

R/W

P23

P22

(CL)

P21 P20

(FR)

R/W

IOC03 IOC02 IOC01 IOC00 PUL03 PUL02 PUL01 PUL00

P03 P02 P01 P00

IOC13

IOC12

IOC11

IOC10

PUL13

PUL12

PUL11

PUL10

P13

P12

P11

P10

IOC23

IOC22

IOC21 IOC20 PUL23

PUL22

PUL21 PUL20

P23

P22

P21 P20

0 0 0 0 1 1 1

1 – – – –

–

1 –

–

– –

∗1

10 Output Output Output Output

On On On On

∗

High

∗

High

∗

High

∗

High

Output

∗

High

∗

High

∗

High

∗

High

Output

Output Output

On On

∗

High

∗

High

∗

High

∗

High

Input Input

P00–P03 I/O control register

Input Input

Off Off

P00–P03 pull-up control register

Off

Off Low Low

P00–P03 I/O port data

Low Low

Input

P13 I/O control register General-purpose register when SIF (clock sync. slave) is selected

Input

P12 I/O control register General-purpose register when SIF (clock sync.) is selected

Input

P11 I/O control register (ESIF=0) General-purpose register when SIF is selected

Input

P10 I/O control register (ESIF=0) General-purpose register when SIF is selected

Off

P13 pull-up control register General-purpose register when SIF (clock sync. slave) is selected

Off

P12 pull-up control register General-purpose register when SIF (clock sync. master) is selected SCLK (I) pull-up control register when SIF (clock sync. slave) is selected

Off

P11 pull-up control register (ESIF=0) General-purpose register when SIF is selected

Off

P10 pull-up control register (ESIF=0) SIN pull-up control register when SIF is selected

Low

P13 I/O port data General-purpose register when SIF (clock sync. slave) is selected

Low

P12 I/O port data General-purpose register when SIF (clock sync.) is selected

Low

P11 I/O port data (ESIF=0) General-purpose register when SIF is selected

Low

P10 I/O port data (ESIF=0) General-purpose register when SIF is selected

Input

P23 I/O control register (EXLCDC=0) General-purpose register when FR output is selected

Input

P22 I/O control register (EXLCDC=0) General-purpose register when CL output is selected

Input

P21 I/O control register

Input

P20 I/O control register

Off

P23 pull-up control register (EXLCDC=0) General-purpose register when FR output is selected

Off

P22 pull-up control register (EXLCDC=0) General-purpose register when CL output is selected

Off

P21 pull-up control register

Off

P20 pull-up control register

Low

P23 I/O port data (EXLCDC=0) General-purpose register when FR output is selected

Low

P22 I/O port data (EXLCDC=0) General-purpose register when CL output is selected

Low

P21 I/O port data

Low

P20 I/O port data

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (I/O Ports)

Table 4.6.6.1(b) Control bits of I/O ports

Address Comment

IOC33 IOC32 IOC31 IOC30

FF4CH

PUL33 PUL32 PUL31 PUL30

FF4DH

(XSRDYS)

FF4EH

FF58H

EXLCDC ALOFF ALON LPAGE

FF61H

FF70H

*1 Initial value at initial reset *2 Not set in the circuit *3 Constantly "0" when being read

D3 D2

P33

(XSCLKS)

0 SMD1S SMD0S ESIFS

R R/W

0 SMD1 SMD0 ESIF

R R/W

D1 D0 Name Init

R/W

P32

P31

(SINS)

(SOUTS)

R/W

P30

IOC33

IOC32

IOC31

IOC30

PUL33

PUL32

PUL31

PUL30

P33

P32

P31

P30

∗

0 SMD1S SMD0S

ESIFS

EXLCDC

ALOFF

ALON

LPAGE

∗

SMD1 SMD0

ESIF

∗1

Output

∗

–

High

∗

High

–

∗

High

–

∗

High

–

∗

–

0 0 0 SIF I/O 0

Enable

All Off

All On

F100-F15F

∗

–

0 0 0 SIF I/O

Input

P33 I/O control register General-purpose register when SIF (clock sync. slave) is selected

Input

P32 I/O control register General-purpose register when SIF (clock sync.) is selected

Input

P31 I/O control register (ESIFS=0) General-purpose register when SIF is selected

Input

P30 I/O control register (ESIFS=0) General-purpose register when SIF is selected

Off

P33 pull-up control register General-purpose register when SIF (clock sync. slave) is selected

Off

P32 pull-up control register General-purpose register when SIF (clock sync. master) is selected SCLK (I) pull-up control register when SIF (clock sync. slave) is selected

Off

P31 pull-up control register (ESIFS=0) General-purpose register when SIF is selected

Off

P30 pull-up control register (ESIFS=0) SIN pull-up control register when SIF is selected

Low

P33 I/O port data General-purpose register when SIF (clock sync. slave) is selected

Low

P32 I/O port data General-purpose register when SIF (clock sync.) is selected

Low

P31 I/O port data (ESIFS=0) General-purpose register when SIF is selected

Low

P30 I/O port data (ESIFS=0) General-purpose register when SIF is selected Unused Serial I/F (2) mode selection Serial I/F (2) enable (P3x port function selection)

Disable

Expanded LCD driver signal control

Normal

LCD all Off control

Normal

LCD all On control

F000-F05F

Display memory area selection (when 1/8 duty is selected) General-purpose register when 1/16, 1/17 duty is selected Unused Serial I/F (1) mode selection Serial I/F (1) enable (P1x port function selection)

[SMD1S, 0S]

Clk-sync. master

Mode [SMD1S, 0S] Mode

[SMD1, 0]

Clk-sync. master

Mode [SMD1, 0] Mode

Async. 7-bit

Clk-sync. slave

Async. 8-bit

Clk-sync. slave

Async. 8-bit

(1) Selection of port function

EXLCDC: Expanded LCD driver signal control register (FF61H•D3)

Sets P22 and P23 to the CL signal and the FR signal output ports.

When "1" is written: CL/FR signal output When "0" is written: I/O port

Reading: Valid

When setting P22 to the CL (LCD synchronous signal) output and P23 to the FR (LCD frame signal) output, write "1" to this register and when they are used as I/O ports, write "0". The CL and FR signals are output from the P22 terminal and P23 terminal immediately after the functions are switched by the EXLCDC register. In this case, the control registers for P22 and P23 can be used as general purpose registers that do not affect the output. At initial reset, this register is set to "0".

S1C63558 TECHNICAL MANUAL EPSON 45

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (I/O Ports)

ESIF: Serial interface (1) enable register (FF70H•D0)

Selects function for P10–P13.

When "1" is written: Serial interface (1) input/output port When "0" is written: I/O port

Reading: Valid

When using the serial interface (1), write "1" to this register and when P10–P13 are used as the I/O port, write "0". The terminal configuration within P10–P13 that are used for the serial interface (1) is decided by the transfer mode (7-bit asynchronous, 8-bit asynchronous, clock synclonous slave, clock synchronous master) selected with the SMD1 and SMD0 registers. In the clock synchronous slave mode, all the P10–P13 ports are set to the serial interface (1) input/output port. In the clock synchronous master mode, P10–P12 are set to the serial interface (1) input/output port and P13 can be used as the I/O port. In the 8/7-bit asynchronous mode, P10 and P11 are set to the serial interface (1) input/output port and P12 and P13 can be used as the I/O port. At initial reset, this register is set to "0".

ESIFS: Serial interface (2) enable register (FF58H•D0)

Selects function for P30–P33.

When "1" is written: Serial interface (2) input/output port When "0" is written: I/O port

Reading: Valid

When using the serial interface (2), write "1" to this register and when P30–P33 are used as the I/O port, write "0". The terminal configuration within P30–P33 that are used for the serial interface (2) is decided by the transfer mode (7-bit asynchronous, 8-bit asynchronous, clock synclonous slave, clock synchronous master) selected with the SMD1S and SMD0S registers. In the clock synchronous slave mode, all the P30–P33 ports are set to the serial interface (2) input/output port. In the clock synchronous master mode, P30–P32 are set to the serial interface (2) input/output port and P33 can be used as the I/O port. In the 8/7-bit asynchronous mode, P30 and P31 are set to the serial interface (2) input/output port and P32 and P33 can be used as the I/O port. At initial reset, this register is set to "0".

(2) I/O port control

P00–P03: P0 I/O port data register (FF42H) P10–P13: P1 I/O port data register (FF46H) P20–P23: P2 I/O port data register (FF4AH) P30–P33: P3 I/O port data register (FF4EH)

I/O port data can be read and output data can be set through these registers.

• When writing data

When "1" is written: High level When "0" is written: Low level

When an I/O port is set to the output mode, the written data is output unchanged from the I/O port terminal. When "1" is written as the port data, the port terminal goes high (V the terminal goes low (V

SS).

Port data can be written also in the input mode.

• When reading data

When "1" is read: High level When "0" is read: Low level

The terminal voltage level of the I/O port is read out. When the I/O port is in the input mode the voltage level being input to the port terminal can be read out; in the output mode the register value can be read.

46 EPSON S1C63558 TECHNICAL MANUAL

DD), and when "0" is written,

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (I/O Ports)

When the terminal voltage is high (VDD) the port data that can be read is "1", and when the terminal voltage is low (V

SS) the data is "0".

When "with pull-up resistor" has been selected with the mask option and the PUL register is set to "1", the built-in pull-up resister goes ON during input mode, so that the I/O port terminal is pulled up.

The data registers of the port, which are set for the special output (P22, P23) or input/output of the serial interface (P10–P13 or P30–P33), become general-purpose registers that do not affect the input/output.

Note: When in the input mode, I/O ports are changed from low to high by pull-up resistor, the rise of the

waveform is delayed on account of the time constant of the pull-up resistor and input gate capacitance. Hence, when fetching input ports, set an appropriate wait time. Particular care needs to be taken of the key scan during key matrix configuration. Make this waiting time the amount of time or more calculated by the following expression. 10

C × R C: terminal capacitance 5 pF + parasitic capacitance ? pF R: pull-up resistance 330 k

Ω

IOC00–IOC03: P0 port I/O control register (FF40H) IOC10–IOC13: P1 port I/O control register (FF44H) IOC20–IOC23: P2 port I/O control register (FF48H) IOC30–IOC33: P3 port I/O control register (FF4CH)

The input and output modes of the I/O ports are set with these registers.

When "1" is written: Output mode When "0" is written: Input mode

Reading: Valid

The input and output modes of the I/O ports are set in 1-bit unit. Writing "1" to the I/O control register makes the corresponding I/O port enter the output mode, and writing "0" induces the input mode. At initial reset, these registers are all set to "0", so the I/O ports are in the input mode. The I/O control registers of the port, which are set for the special output (P22, P23) or input/output of the serial interface (P10–P13 or P30–P33), become general-purpose registers that do not affect the input/ output.

PUL00–PUL03: P0 port pull-up control register (FF41H) PUL10–PUL13: P1 port pull-up control register (FF45H) PUL20–PUL23: P2 port pull-up control register (FF49H) PUL30–PUL33: P3 port pull-up control register (FF4DH)

The pull-up during the input mode are set with these registers.

When "1" is written: Pull-up ON When "0" is written: Pull-up OFF

Reading: Valid

The built-in pull-up resistor which is turned ON during input mode is set to enable in 1-bit units. (The pull-up resistor is included into the ports selected by the mask option.) By writing "1" to the pull-up control register, the corresponding I/O ports are pulled up (during input mode), while writing "0" turns the pull-up function OFF. At initial reset, these registers are all set to "1", so the pull-up function is set to ON.

The pull-up control registers of the ports in which the pull-up resistor is not included become the general purpose register. The registers of the ports that are set as special output or output for the serial interface can also be used as general purpose registers that do not affect the pull-up control. The pull-up control registers of the port that are set as input for the serial interface function the same as the I/O port.

S1C63558 TECHNICAL MANUAL EPSON 47

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (I/O Ports)

4.6.7 Programming notes

(1) When in the input mode, I/O ports are changed from low to high by pull-up resistor, the rise of the

C: terminal capacitance 5 pF + parasitic capacitance ? pF R: pull-up resistance 330 kΩ

(2) When special output (CL, FR) has been selected, a hazard may occur when the signal is turned ON or

OFF.

48 EPSON S1C63558 TECHNICAL MANUAL

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)

4.7 LCD Driver (COM0–COM16, SEG0–SEG39)

4.7.1 Configuration of LCD driver

The S1C63558 has 17 common terminals (COM0–COM16) and 40 segment terminals (SEG0–SEG39), so that it can drive a dot matrix type LCD with a maximum of 680 (40 × 17) dots. The driving method is 1/17 duty, 1/16 duty or 1/8 duty dynamic drive with four voltages (1/4 bias), V

C1, VC23, VC4 and VC5.

LCD display ON/OFF can be controlled by the software.

4.7.2 Mask option

The COM8–COM16 terminals can be set as the SEG47–SEG40 terminals by mask option. In this case, only 1/8 drive duty can be selected, so a dot matrix type LCD with a maximum of 384 (48 × 8) dots can be driven. When 48 segments × 8 commons is selected, COM terminals change to SEG terminals as follows: COM16 → SEG40 COM15 → SEG41 COM14 → SEG42 COM13 → SEG43 COM12 → SEG44 COM11 → SEG45 COM10 → SEG46 COM9 → SEG47 COM8 → SEG47

This option is valid on the PRC board, however, the SEG47–SEG40 terminals are separately provided. Therefore, be aware that the COM8–COM16 terminals cannot be changed to the SEG47–SEG40.

4.7.3 Power supply for LCD driving

VC1, VC23, VC4 and VC5 are the LCD (1/4 bias) drive voltages generated by the LCD system voltage circuit. These four output voltages can only be supplied to the externally expanded LCD driver. Turning the LCD system voltage circuit ON or OFF is controlled with the LPWR register. When LPWR is set to "1", the LCD system voltage circuit outputs the LCD drive voltages V LCD driver.

The LCD system voltage circuit generates VC23 with the voltage regulator incorporated in itself, and generates three other voltages by boosting or reducing the voltage V V

C23, VC4 and VC5 voltage values and boost/reduce status.

Table 4.7.3.1 LCD drive voltage when generated internally

LCD drive voltage

VC1

VC23

VC4 VC5

Boost/reduce status

VC2 × 0.5

VC2 (standard)

C2 × 1.5

VC2 × 2

Voltage value [V]

C1, VC23, VC4 and VC5 to the

C23. Table 4.7.3.1 shows the VC1,

1.13

2.25

3.38

4.50

Note: The LCD drive voltage can be adjusted by the software (see Section 4.7.6). Values in the table are

typical values.

4.7.4 LCD display control (ON/OFF) and switching of duty

(1)Display ON/OFF control

The S1C63558 incorporates the ALON and ALOFF registers to blink display. When "1" is written to ALON, all the dots go ON, and when "1" is written to ALOFF, all the dots go OFF. At such a time, an ON waveform or an OFF waveform is output from SEG terminals. When "0" is written to these registers, normal display is performed. Furthermore, when "1" is written to both of the ALON and ALOFF, ALON (all ON) has priority over the ALOFF (all OFF).

S1C63558 TECHNICAL MANUAL EPSON 49

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)

(2)Switching of drive duty

In the S1C63558, the drive duty can be set to 1/17, 1/16 or 1/8 by the software. This setting is done using the LDUTY1 and LDUTY0 registers as shown in Table 4.7.4.1.

Table 4.7.4.1 LCD drive duty setting

Drive

LDUTY1

1 0 0

LDUTY0

∗

1 0

Common terminal

duty

1/8 1/16 1/17

used

COM0–COM7 COM0–COM15 COM0–COM16

When 48 segments × 8 commons is selected by mask option, COM8–COM16 are changed to SEG47– SEG40. Therefore, COM8–COM16 cannot be used. In this case, be sure to set the drive duty to 1/8 by the software.

Table 4.7.4.2 shows the frame frequencies corresponding to the OSC1 oscillation frequency and drive duty.

Table 4.7.4.2 Frame frequency

OSC1 oscillation

frequency

32.768 kHz

When 1/8 duty

is selected

32 Hz

Figure 4.7.4.1 shows the dynamic drive waveform for 1/4 bias.

Maximum segment

number

320 (40 × 8) 640 (40 × 16) 680 (40 × 17)

When 1/16 duty

is selected

32 Hz

When 48 × 8 mask option

is selected

384 (48 × 8)

Invalid Invalid

When 1/17 duty

is selected

30.12 Hz

Drive duty

Frame signal

COM0

COM1

COM2

SEG0

SEG1

1/8 1/16 1/17

. . . . .

15 16

32 Hz ∗

. . . . .

15 16

(LPAGE = 0)

∗ When f

C23 (VC2 = VC3

V V

C23 (VC2 = VC3

V V

C23 (VC2 = VC3

OSC1

= 32.768 kHz

)

Fig. 4.7.4.1 Drive waveform for 1/4 bias

50 EPSON S1C63558 TECHNICAL MANUAL

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)

4.7.5 Display memory

The display memory is allocated to F000H–F25EH in the data memory area and the addresses and the data bits correspond to COM and SEG outputs as shown in Figure 4.7.5.1.

1/17 duty

LPAGE

COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7

COM8

1/16 duty

COM9 COM10 COM11 COM12 COM13 COM14 COM15

COM16

COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7

SEG0

■ D0

■ D1

F000H

■ D2

■ D3

■ D0

■ D1

F001H

■ D2

■ D3

■ D0

■ D1

F100H

■ D2

■ D3

■ D0

■ D1

F101H

■ D2

■ D3

■ D0

F200H

Memory address

SEG0

■ D0

■ D1

F000H

■ D2

■ D3

■ D0

■ D1

F001H

■ D2

■ D3

SEG1

■ D0

■ D1

■ D2

■ D3

■ D0

■ D1

■ D2

■ D3

■ D0

■ D1

■ D2

■ D3

■ D0

■ D1

■ D2

■ D3

■ D0

F002H

F003H

F102H

F103H

F202H

SEG2

■ D0

■ D1

■ D2

■ D3

■ D0

■ D1

■ D2

■ D3

■ D0

■ D1

■ D2

■ D3

■ D0

■ D1

■ D2

■ D3

■ D0

Data bit

F004H

F005H

F104H

F105H

F204H

SEG3

■ D0

■ D1

■ D2

■ D3

■ D0

■ D1

■ D2

■ D3

■ D0

■ D1

■ D2

■ D3

■ D0

■ D1

■ D2

■ D3

■ D0

(a) When 1/17 or 1/16 duty is selected

SEG1

■ D0

■ D1

■ D2

■ D3

■ D0

■ D1

■ D2

■ D3

F002H

F003H

SEG2

■ D0

■ D1

■ D2

■ D3

■ D0

■ D1

■ D2

■ D3

F004H

F005H

SEG3

■ D0

■ D1

■ D2

■ D3

■ D0

■ D1

■ D2

■ D3

F006H

F007H

F106H

F107H

F206H

F006H

F007H

. . . . .

SEG39

■ D0

■ D1

■ D2

■ D3

■ D0

■ D1

■ D2

■ D3

■ D0

■ D1

■ D2

■ D3

■ D0

■ D1

■ D2

■ D3

■ D0

SEG39

■ D0

■ D1

■ D2

■ D3

■ D0

■ D1

■ D2

■ D3

F04EH

F04FH

F14EH

F14FH

F24EH

F04EH

F04FH

LPAGE

COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7

Unused

■ D0

■ D1

■ D2

■ D3

■ D0

■ D1

■ D2

■ D3

■ D0

F100H

F101H

F200H

■ D0

■ D1

■ D2

■ D3

■ D0

■ D1

■ D2

■ D3

■ D0

F102H

F103H

F202H

■ D0

■ D1

■ D2

■ D3

■ D0

■ D1

■ D2

■ D3

■ D0

F104H

F105H

F204H

■ D0

■ D1

■ D2

■ D3

■ D0

■ D1

■ D2

■ D3

■ D0

F106H

F107H

F206H

. . . . .

■ D0

■ D1

■ D2

■ D3

■ D0

■ D1

■ D2

■ D3

■ D0

F14EH

F14FH

F24EH

(b) When 1/8 duty is selected

S1C63558 TECHNICAL MANUAL EPSON 51

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)

LPAGE

COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7

Unused

SEG0

■ D0

■ D1

■ D2

■ D3

■ D0

■ D1

■ D2

■ D3

■ D0

■ D1

■ D2

■ D3

■ D0

■ D1

■ D2

■ D3

■ D0

F000H

F001H

F100H

F101H

F200H

SEG1

■ D0

■ D1

■ D2

■ D3

■ D0

■ D1

■ D2

■ D3

■ D0

■ D1

■ D2

■ D3

■ D0

■ D1

■ D2

■ D3

■ D0

F002H

F003H

F102H

F103H

F202H

SEG2

■ D0

■ D1

■ D2

■ D3

■ D0

■ D1

■ D2

■ D3

■ D0

■ D1

■ D2

■ D3

■ D0

■ D1

■ D2

■ D3

■ D0

F004H

F005H

F104H

F105H

F204H

SEG3

■ D0

■ D1

■ D2

■ D3

■ D0

■ D1

■ D2

■ D3

■ D0

■ D1

■ D2

■ D3

■ D0

■ D1

■ D2

■ D3

■ D0

F006H

F007H

F106H

F107H

F206H

. . . . .

SEG47

■ D0

■ D1

■ D2

■ D3

■ D0

■ D1

■ D2

■ D3

■ D0

■ D1

■ D2

■ D3

■ D0

■ D1

■ D2

■ D3

■ D0

F05EH

F05FH

F15EH

F15FH

F25EH

Fig. 4.7.5.1 Correspondence between display memory and LCD dot matrix

When a bit in the display memory is set to "1", the corresponding LCD dot goes ON, and when it is set to "0", the dot goes OFF. At 1/17 (1/16) duty drive, all data of COM0–COM16 (15) is output. At 1/8 duty drive, data only corresponding to COM0–COM7 is output. However, since the display memory has capacity for two screens, it is designed so that the memory for COM8–COM15 shown in Figure 4.7.5.1 (a) can also be used as COM0–COM15. Select either F000H–F05FH or F100H–F15FH for the area to be displayed (to be output from COM0–COM7 terminals) using the LPAGE register. It can switch the screen in an instant. At initial reset, the data memory content becomes undefined hence, there is need to initialize using the software. The display memory has read/write capability, and the addresses that have not been used for LCD display can be used as general purpose registers. F050H–F05FH, F150H–F15FH, F250H, F252H, F254H,

· · ·, F25EH can be used as general purpose registers except when 48 × 8 is selected by mask option.

Note: When a program that access no memory mounted area (F060H–F0FFH, F160H–F1FFH, F201H,

F203H, · · ·, F25FH) is made, the operation is not guaranteed.

52 EPSON S1C63558 TECHNICAL MANUAL

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)

4.7.6 LCD contrast adjustment

In the S1C63558, the LCD contrast can be adjusted by the software. It is realized by controlling the voltages V circuit. When these voltages are supplied to the externally expanded LCD driver, the expanded LCD contrast is adjusted at the same time. The contrast can be adjusted to 16 levels as shown in Table 4.7.6.1.

No.

LC3

C1, VC23, VC4 and VC5 output from the LCD system voltage

Table 4.7.6.1 LCD contrast

LC2

LC1

LC0

0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

Contrast

light

dark

Setting the LC3–LC0 register affects the VC23 voltage, and other voltages change according to the VC23. As a result, the LCD contrast is adjusted. The supply voltage V V (when V V

C23 will be VDD - 0.1 V when VDD = 2.2 to 2.5 V.

DD = 2.5 to 5.5 V) in the highest-contrast setting (No. 15 in Table 4.7.6.1), note, however, that

DD within the range from 2.2 to 2.5 V affects the VC23 voltage. Ordinarily, VC23 is 2.4

At room temperature, use setting number 7 or 8 as standard. Since the contents of LC0–LC3 are undefined at initial reset, initialize it by the software.

S1C63558 TECHNICAL MANUAL EPSON 53

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)

4.7.7 I/O memory of LCD driver

Table 4.7.7.1 shows the I/O addresses and the control bits for the LCD driver. Figure 4.7.7.1 shows the display memory map.

Table 4.7.7.1 LCD driver control bits

Address Comment

LDUTY1 LDUTY0 Dummy LPWR

FF60H

EXLCDC ALOFF ALON LPAGE

FF61H

FF62H

*1 Initial value at initial reset *2 Not set in the circuit *3 Constantly "0" when being read

(a) When 40 × 17 is selected

COM0–COM7

F000H

COM3

F001H

COM7

F002H

COM3

F003H

COM7

F004H

COM3

F04DH

COM7

F04EH

COM3

F04FH

COM7

F060H

F0FFH

(b) When 48 × 8 is selected

COM0–COM7

F000H

COM3

F001H

COM7

F002H

COM3

F003H

COM7

F004H

COM3

F05DH

COM7

F05EH

COM3

F05FH

COM7

F060H

F0FFH

D3 D2

D1 D0 Name Init

R/W

LC3 LC2 LC1 LC0

R/W

D1 COM1 COM5 COM1 COM5 COM1

COM5 COM1 COM5

D1 COM1 COM5 COM1 COM5 COM1

COM5 COM1 COM5

D0 COM0 COM4 COM0 COM4 COM0

COM4 COM0 COM4

D0 COM0 COM4 COM0 COM4 COM0

COM4 COM0 COM4

SEG0 SEG0 SEG1 SEG1 SEG2

SEG38 SEG39 SEG39

Notimplemented

SEG0 SEG0 SEG1 SEG1 SEG2

SEG46 SEG47 SEG47

Notimplemented

COM2 COM6 COM2 COM6 COM2

COM6 COM2 COM6

D2 COM2 COM6 COM2 COM6 COM2

COM6 COM2 COM6

∗1

LDUTY1 LDUTY0

Dummy

LPWR

EXLCDC

ALOFF

ALON

LPAGE

10 0 0 0 0OnOff 0

Enable

All Off

All On

F100-F15F

LCD drive duty switch General-purpose register LCD power On/Off

Disable

Expanded LCD driver signal control

Normal

LCD all Off control

Normal

LCD all On control

F000-F05F

Display memory area selection (when 1/8 duty is selected) General-purpose register when 1/16, 1/17 duty is selected

LC3 LC2 LC1 LC0

F100H F101H F102H F103H F104H

: F14DH F14EH

F14FH

F160H

: F1FFH

F100H F101H F102H F103H F104H

: F15DH F15EH

F15FH F160H

: F1FFH

∗

–

∗

–

∗

–

∗

–

COM8–COM15

COM11

COM10

COM15

COM14

COM11

COM10

COM15

COM14

COM11

COM10

COM15

COM14

COM11

COM10

COM15

COM14

COM0–COM7

COM3

COM2

COM7

COM6

COM3

COM2

COM7

COM6

COM3

COM2

COM7

COM6

COM3

COM2

COM7

COM6

COM09 COM13 COM09 COM13

COM9

COM13

COM9

COM13

COM1 COM5 COM1 COM5 COM1

COM5 COM1 COM5

LCD contrast adjustment

COM8

COM12

COM8

COM12

COM8

COM12

COM8

COM12

D0 COM0 COM4 COM0 COM4 COM0

COM4 COM0 COM4

Fig. 4.7.7.1 Display memory map

[LC3–0] Contrast

SEG0 SEG0 SEG1 SEG1 SEG2

SEG38 SEG39 SEG39

Notimplemented

SEG0 SEG0 SEG1 SEG1 SEG2

SEG46 SEG47 SEG47

Notimplemented

[LDUTY1, 0] Duty

Light––15Dark

COM16

D3 F200H F201H F202H F203H

: F24CH F24DH F24EH F24FH

Non-implementation area Read/write disabled

Unused area Always "0"

1/1711/16

Reading: Writing:

COM16

No Operation

SEG0

SEG1

SEG38

SEG39

2, 3

1/8

54 EPSON S1C63558 TECHNICAL MANUAL

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)

LPWR: LCD power control (ON/OFF) register (FF60H•D0)

Turns the LCD system voltage circuit ON and OFF.

When "1" is written: ON When "0" is written: OFF

Reading: Valid

When "1" is written to the LPWR register, the LCD system voltage circuit goes ON and generates the LCD drive voltage. When "0" is written, all the LCD drive voltages go to V

SS level.

It takes about 100 msec for the LCD drive voltage to stabilize after starting up the LCD system voltage circuit by writing "1" to the LPWR register. At initial reset, this register is set to "0".

LDUTY0, LDUTY1: LCD drive duty switching register (FF60H•D2, D3)

Selects the LCD drive duty.

Table 4.7.7.2 Drive duty setting

LDUTY1

1 0 0

LDUTY0

∗

1 0

Common terminal

duty

1/8 1/16 1/17

used

COM0–COM7 COM0–COM15 COM0–COM16

Maximum segment

number

320 (40 × 8) 640 (40 × 16) 680 (40 × 17)

When 48 × 8 mask option

is selected

384 (48 × 8)

Invalid Invalid

Drive

At initial reset, this register is set to "0". When 48 × 8 is selected by mask option, reset to 1/8 duty.

ALON: LCD all ON control register (FF61H•D1)

Displays the all LCD dots ON.

When "1" is written: All LCD dots displayed When "0" is written: Normal display

Reading: Valid

By writing "1" to the ALON register, all the LCD dots goes ON, and when "0" is written, it returns to normal display. This function outputs an ON waveform to the SEG terminals, and does not affect the content of the display memory. ALON has priority over ALOFF. At initial reset, this register is set to "0".

ALOFF: LCD all OFF control register (FF61H•D2)

Fade outs the all LCD dots.

When "1" is written: All LCD dots fade out When "0" is written: Normal display

Reading: Valid

By writing "1" to the ALOFF register, all the LCD dots goes OFF, and when "0" is written, it returns to normal display. This function outputs an OFF waveform to the SEG terminals, and does not affect the content of the display memory. At initial reset, this register is set to "1".

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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)

LPAGE: LCD display memory selection register (FF61H•D0)

Selects the display memory area at 1/8 duty drive.

When "1" is written: F100H–F14FH (when 40 × 17 is selected), F100H–F15FH (when 48 × 8 is selected) When "0" is written: F000H–F04FH (when 40 × 17 is selected), F000H–F05FH (when 48 × 8 is selected)

Reading: Valid

By writing "1" to the LPAGE register, the data set in F100H–F14FH/F15FH (the second half of the display memory) is displayed, and when "0" is written, the data set in F000H–F04FH/F05FH (the first half of the display memory) is displayed. This function is valid only when 1/8 duty is selected, and when 1/16 or 1/17 duty is selected, this register can be used as a general purpose register. At initial reset, this register is set to "0".

LC3–LC0: LCD contrast adjustment register (FF62H)

Adjusts the LCD contrast.

LC3–LC0 = 0000B light

LC3–LC0 = 1111B dark

At room temperature, use setting number 7 or 8 as standard. At initial reset, LC3–LC0 are undefined.

4.7.8 Programming notes

(1) When a program that access no memory mounted area (F060H–F0FFH, F160H–F1FFH, F201H, F203H,

· · ·, F25FH) is made, the operation is not guaranteed.

(2) Because at initial reset, the contents of display memory and LC3–LC0 (LCD contrast) are undefined,

there is need to initialize by the software. Furthermore, take care of the registers LPWR and ALOFF because these are set so that the display goes OFF.

(3) The COM8–COM16 terminals can be set as the SEG47–SEG40 terminals by mask option. In this case,

only 1/8 drive duty can be selected, so a dot matrix type LCD with a maximum of 384 (48 × 8) dots can be driven. When 48 segments × 8 commons is selected, COM terminals change to SEG terminals as follows: COM16 → SEG40 COM15 → SEG41 COM14 → SEG42 COM13 → SEG43 COM12 → SEG44 COM11 → SEG45 COM10 → SEG46 COM9 → SEG47 COM8 → SEG47

This option is valid on the PRC board, however, the SEG47–SEG40 terminals are separately provided. Therefore, be aware that the COM8–COM16 terminals cannot be changed to the SEG47–SEG40.

56 EPSON S1C63558 TECHNICAL MANUAL

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Clock Timer)

4.8 Clock Timer

4.8.1 Configuration of clock timer

The S1C63558 has a built-in clock timer that uses OSC1 (crystal oscillator) as the source oscillator. The clock timer is configured of an 8-bit binary counter that serves as the input clock, f output from the prescaler. Timer data (128–16 Hz and 8–1 Hz) can be read out by the software. Figure 4.8.1.1 is the block diagram for the clock timer.

Data bus

Clock timer OSC1 oscillation circuit (f

OSC1

)

Divider

256 Hz

128 Hz–16 Hz

8 Hz–1 Hz

32 Hz, 8 Hz, 2 Hz, 1 Hz

OSC1 divided clock

Clock timer reset signal

Clock timer RUN/STOP signal

Fig. 4.8.1.1 Block diagram for the clock timer

Ordinarily, this clock timer is used for all types of timing functions such as clocks.

Interrupt

control

Interrupt request

4.8.2 Data reading and hold function

The 8 bits timer data are allocated to the address FF79H and FF7AH.

<FF79H> D0: TM0 = 128 Hz D1: TM1 = 64 Hz D2: TM2 = 32 Hz D3: TM3 = 16 Hz <FF7AH> D0: TM4 = 8 Hz D1: TM5 = 4 Hz D2: TM6 = 2 Hz D3: TM7 = 1 Hz

Since the clock timer data has been allocated to two addresses, a carry is generated from the low-order data within the count (TM0–TM3: 128–16 Hz) to the high-order data (TM4–TM7: 8–1 Hz). When this carry is generated between the reading of the low-order data and the high-order data, a content combining the two does not become the correct value (the low-order data is read as FFH and the high-order data becomes the value that is counted up 1 from that point). The high-order data hold function in the S1C63558 is designed to operate to avoid this. This function temporarily stops the counting up of the high-order data (by carry from the low-order data) at the point where the low-order data has been read and consequently the time during which the high-order data is held is the shorter of the two indicated here following.

1. Period until it reads the high-order data.

2. 0.48–1.5 msec (Varies due to the read timing.)

Note: Since the low-order data is not held when the high-order data has previously been read, the low-

order data should be read first.

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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Clock Timer)

4.8.3 Interrupt function

The clock timer can cause interrupts at the falling edge of 32 Hz, 8 Hz, 2 Hz and 1 Hz signals. Software can set whether to mask any of these frequencies. Figure 4.8.3.1 is the timing chart of the clock timer.

Address

FF79H

FF7AH

Bit

Frequency Clock timer timing chart

128 Hz

32 Hz interrupt request

8 Hz interrupt request

2 Hz interrupt request

1 Hz interrupt request

64 Hz

32 Hz

16 Hz

8 Hz

4 Hz

2 Hz

1 Hz

Fig. 4.8.3.1 Timing chart of clock timer

As shown in Figure 4.8.3.1, interrupt is generated at the falling edge of the frequencies (32 Hz, 8 Hz, 2 Hz, 1 Hz). At this time, the corresponding interrupt factor flag (IT0, IT1, IT2, IT3) is set to "1". Selection of whether to mask the separate interrupts can be made with the interrupt mask registers (EIT0, EIT1, EIT2, EIT3). However, regardless of the interrupt mask register setting, the interrupt factor flag is set to "1" at the falling edge of the corresponding signal.

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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Clock Timer)

4.8.4 I/O memory of clock timer

Table 4.8.4.1 shows the I/O addresses and the control bits for the clock timer.

Table 4.8.4.1 Control bits of clock timer

Address Comment

FF78H

FF79H

FF7AH

EIT3 EIT2 EIT1 EIT0

FFE6H

FFF6H

*1 Initial value at initial reset *2 Not set in the circuit *3 Constantly "0" when being read

D3 D2

00TMRST TMRUN

TM3 TM2 TM1 TM0

TM7 TM6 TM5 TM4

IT3 IT2 IT1 IT0

D1 D0 Name Init

W R/WR

R/W

∗

TMRST

TMRUN

TM3 TM2 TM1 TM0 TM7 TM6 TM5 TM4 EIT3 EIT2 EIT1 EIT0

IT3 IT2 IT1 IT0

∗1

∗

–

∗

–

∗

Reset0Reset

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

2 2

Run

Enable Enable Enable Enable

(R) Yes (W)

Reset

Unused Unused

Invalid

Clock timer reset (writing)

Stop

Clock timer Run/Stop Clock timer data (16 Hz) Clock timer data (32 Hz) Clock timer data (64 Hz) Clock timer data (128 Hz) Clock timer data (1 Hz) Clock timer data (2 Hz) Clock timer data (4 Hz) Clock timer data (8 Hz) Interrupt mask register (Clock timer 1 Hz)

Mask

Interrupt mask register (Clock timer 2 Hz)

Mask

Interrupt mask register (Clock timer 8 Hz)

Mask

Interrupt mask register (Clock timer 32 Hz)

Mask

Interrupt factor flag (Clock timer 1 Hz)

(R)

Interrupt factor flag (Clock timer 2 Hz)

Interrupt factor flag (Clock timer 8 Hz)

(W)

Interrupt factor flag (Clock timer 32 Hz)

Invalid

TM0–TM7: Timer data (FF79H, FF7AH)

The 128–1 Hz timer data of the clock timer can be read out with these registers. These eight bits are read only, and writing operations are invalid. By reading the low-order data (FF79H), the high-order data (FF7AH) is held until reading or for 0.48–1.5 msec (one of shorter of them). At initial reset, the timer data is initialized to "00H".

TMRST: Clock timer reset (FF78H•D1)

This bit resets the clock timer.

When "1" is written: Clock timer reset When "0" is written: No operation

Reading: Always "0"

The clock timer is reset by writing "1" to TMRST. When the clock timer is reset in the RUN status, operation restarts immediately. Also, in the STOP status the reset data is maintained. No operation results when "0" is written to TMRST. This bit is write-only, and so is always "0" at reading.

TMRUN: Clock timer RUN/STOP control register (FF78H•D0)

Controls RUN/STOP of the clock timer.

When "1" is written: RUN When "0" is written: STOP

Reading: Valid

The clock timer enters the RUN status when "1" is written to the TMRUN register, and the STOP status when "0" is written. In the STOP status, the timer data is maintained until the next RUN status or the timer is reset. Also, when the STOP status changes to the RUN status, the data that is maintained can be used for resuming the count. At initial reset, this register is set to "0".

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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Clock Timer)

EIT0: 32 Hz interrupt mask register (FFE6H•D0) EIT1: 8 Hz interrupt mask register (FFE6H•D1) EIT2: 2 Hz interrupt mask register (FFE6H•D2) EIT3: 1 Hz interrupt mask register (FFE6H•D3)

These registers are used to select whether to mask the clock timer interrupt.

When "1" is written: Enabled When "0" is written: Masked

Reading: Valid

The interrupt mask registers (EIT0, EIT1, EIT2, EIT3) are used to select whether to mask the interrupt to the separate frequencies (32 Hz, 8 Hz, 2 Hz, 1 Hz). At initial reset, these registers are set to "0".

IT0: 32 Hz interrupt factor flag (FFF6H•D0) IT1: 8 Hz interrupt factor flag (FFF6H•D1) IT2: 2 Hz interrupt factor flag (FFF6H•D2) IT3: 1 Hz interrupt factor flag (FFF6H•D3)

These flags indicate the status of the clock timer interrupt.

When "1" is read: Interrupt has occurred When "0" is read: Interrupt has not occurred

When "1" is written: Flag is reset When "0" is written: Invalid

The interrupt factor flags (IT0, IT1, IT2, IT3) correspond to the clock timer interrupts of the respective frequencies (32 Hz, 8 Hz, 2 Hz, 1 Hz). The software can judge from these flags whether there is a clock timer interrupt. However, even if the interrupt is masked, the flags are set to "1" at the falling edge of the signal. These flags are reset to "0" by writing "1" to them. After an interrupt occurs, the same interrupt will occur again if the interrupt enabled state (I flag = "1") is set or the RETI instruction is executed unless the interrupt factor flag is reset. Therefore, be sure to reset (write "1" to) the interrupt factor flag in the interrupt service routine before shifting to the interrupt enabled state. At initial reset, these flags are set to "0".

4.8.5 Programming notes

(1) Be sure to read timer data in the order of low-order data (TM0–TM3) then high-order data (TM4–

TM7).

(2) After an interrupt occurs, the same interrupt will occur again if the interrupt enabled state (I flag =

60 EPSON S1C63558 TECHNICAL MANUAL

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Stopwatch Timer)

4.9 Stopwatch Timer

4.9.1 Configuration of stopwatch timer

The S1C63558 has 1/100 sec unit and 1/10 sec unit stopwatch timer built-in. The stopwatch timer is configured with a 2 levels 4-bit BCD counter which has an input clock approximating 100 Hz signal (signal divided from OSC1 to the closest 100 Hz) and data can be read in units of 4 bits by software. Figure 4.9.1.1 shows the configuration of the stopwatch timer.

Data bus

OSC1 oscillation circuit (f

OSC1

)

Divider

256 Hz 10 Hz

Stopwatch timer

SWD0–3

SWD4–7

10 Hz, 1 Hz

Stopwatch timer reset signal

Stopwatch timer RUN/STOP signal

Interrupt

control

Interrupt request

Fig. 4.9.1.1 Configuration of stopwatch timer

The stopwatch timer can be used as a separate timer from the clock timer. In particular, digital watch stopwatch functions can be realized easily with software.

4.9.2 Count-up pattern

The stopwatch timer is configured of 4-bit BCD counters SWD0–SWD3 and SWD4–SWD7. The counter SWD0–SWD3, at the stage preceding the stopwatch timer, has an approximated 100 Hz signal for the input clock. It counts up every 1/100 sec, and generates an approximated 10 Hz signal. The counter SWD4–SWD7 has an approximated 10 Hz signal generated by the counter SWD0–SWD3 for the input clock. In count-up every 1/10 sec, and generated 1 Hz signal. Figure 4.9.2.1 shows the count-up pattern of the stopwatch timer.

SWD4–7 count-up pattern

SWD4–7 count value

Counting time (sec)

SWD0–3 count-up pattern 1

SWD0–3 count value

Counting time (sec)

0 1 2 3 4 5 6 7 8 9 0

26 256

256

0 1 2 3 4 5 6 7 8 9 0

3 256

25 256

26 256

2 256

26 256

x 6 +

3 256

256

25 256

2 256

256

x 4 = 1 (sec)

256

(sec)

256

26 256

3 256

26 256

2 256

3 256

2 256

1 Hz signal generation

Approximate 10 Hz signal generation

SWD0–3 count-up pattern 2

SWD0–3 count value

Counting time (sec)

0 1 2 3 4 5 6 7 8 9 0

3 256

2 256

3 256

26 256

2 256

(sec)

3 256

2 256

3 256

2 256

Approximate 10 Hz signal generation

Fig. 4.9.2.1 Count-up pattern of stopwatch timer

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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Stopwatch Timer)

SWD0–SWD3 generates an approximated 10 Hz signal from the basic 256 Hz signal (fOSC1 dividing clock). The count-up intervals are 2/256 sec and 3/256 sec, so that finally two patterns are generated: 25/ 256 sec and 26/256 sec intervals. Consequently, these patterns do not amount to an accurate 1/100 sec. SWD4–SWD7 counts the approximated 10 Hz signals generated by the 25/256 sec and 26/256 sec intervals in the ratio of 4 : 6, to generate a 1 Hz signal. The count-up intervals are 25/256 sec and 26/256 sec, which do not amount to an accurate 1/10 sec.

4.9.3 Interrupt function

The stopwatch timers SWD0–SWD3 and SWD4–SWD7, through their respective overflows, can generate 10 Hz (approximate 10 Hz) and 1 Hz interrupts. Figure 4.9.3.1 shows the timing chart for the stopwatch timer.

Address

FF7DH

1/100sec

(BCD)

10 Hz Interrupt request

Address

FF7EH

1/10sec

(BCD)

1 Hz Interrupt request

Bit

Stopwatch timer (SWD0–3) timing chart

Stopwatch timer (SWD4–7) timing chart

Fig. 4.9.3.1 Timing chart for stopwatch timer

The stopwatch interrupts are generated by the overflow of their respective counters SWD0–SWD3 and SWD4–SWD7 (changing "9" to "0"). At this time, the corresponding interrupt factor flags (ISW10 and ISW1) are set to "1". The respective interrupts can be masked separately using the interrupt mask registers (EISW10 and EISW1). However, regardless of the setting of the interrupt mask registers, the interrupt factor flags are set to "1" by the overflow of their corresponding counters.

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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Stopwatch Timer)

4.9.4 I/O memory of stopwatch timer

Table 4.9.4.1 shows the I/O addresses and the control bits for the stopwatch timer.

Table 4.9.4.1 Control bits of stopwatch timer

Address Comment

FF7CH

SWD3 SWD2 SWD1 SWD0

FF7DH

SWD7 SWD6 SWD5 SWD4

FF7EH

FFE7H

FFF7H

*1 Initial value at initial reset *2 Not set in the circuit *3 Constantly "0" when being read

D3 D2

00SWRST SWRUN

00EISW1 EISW10

R R/W

00ISW1 ISW10

R R/W

D1 D0 Name Init

W R/WR

∗

SWRST

SWRUN

SWD3 SWD2 SWD1 SWD0 SWD7 SWD6 SWD5 SWD4

∗

EISW1

EISW10

∗

ISW1

ISW10

∗1

∗

–

∗

–

∗

Reset0Reset

0 0 0 0 0 0 0 0

∗

–

∗

–

00Enable

∗

–

∗

–

0 0

2 2

Run

2 2

Enable

(R)

Yes (W)

Reset

Unused Unused

Invalid

Stopwatch timer reset (writing)

Stop

Stopwatch timer Run/Stop

Stopwatch timer data BCD (1/100 sec)

Stopwatch timer data BCD (1/10 sec)

Unused Unused

Mask

Interrupt mask register (Stopwatch timer 1 Hz)

Mask

Interrupt mask register (Stopwatch timer 10 Hz) Unused

(R)

Unused

Interrupt factor flag (Stopwatch timer 1 Hz)

(W)

Interrupt factor flag (Stopwatch timer 10 Hz)

Invalid

SWD0–SWD7: Stopwatch timer data (FF7DH, FF7EH)

The 1/100 sec and the 1/10 sec data (BCD) can be read from SWD0–SWD3 and SWD4–SWD7, respectively. These eight bits are read only, and writing operations are invalid. At initial reset, the timer data is initialized to "00H".

SWRST: Stopwatch timer reset (FF7CH•D1)

When "1" is written: Stopwatch timer reset When "0" is written: No operation

Reading: Always "0"

The stopwatch timer is reset by writing "1" to SWRST. All timer data is set to "0". When the stopwatch timer is reset in the RUN status, operation restarts immediately. Also, in the STOP status the reset data is maintained. No operation results when "0" is written to SWRST. This bit is write-only, and so is always "0" at reading.

SWRUN: Stopwatch timer RUN/STOP control register (FF7CH•D0)

Controls RUN/STOP of the stopwatch timer.

When "1" is written: RUN When "0" is written: STOP

Reading: Valid

The stopwatch timer enters the RUN status when "1" is written to the SWRUN register, and the STOP status when "0" is written. In the STOP status, the timer data is maintained until the next RUN status or the timer is reset. Also, when the STOP status changes to the RUN status, the data that is maintained can be used for resuming the count.

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When data of the counter is read at run mode, proper reading may not be obtained due to the carry from low-order digits (SWD0–SWD3) into high-order digits (SWD4–SWD7) (i.e., in case SWD0–SWD3 and SWD4–SWD7 reading span the timing of the carry). To avoid this occurrence, perform the reading after suspending the counter once and then set the SWRUN to "1" again. Moreover, it is required that the suspension period not exceed 976 µsec (1/4 cycle of 256 Hz). At initial reset, this register is set to "0".

EISW10: 10Hz interrupt mask register (FFE7H•D0) EISW1: 1Hz interrupt mask register (FFE7H•D1)

These registers are used to select whether to mask the stopwatch timer interrupt.

When "1" is written: Enabled When "0" is written: Masked

Reading: Valid

The interrupt mask registers (EISW10, EISW1) are used to select whether to mask the interrupt to the separate frequencies (10 Hz, 1 Hz). At initial reset, these registers are set to "0".

ISW10: 10 Hz interrupt factor flag (FFF7H•D0) ISW1: 1 Hz interrupt factor flag (FFF7H•D1)

These flags indicate the status of the stopwatch timer interrupt.

When "1" is read: Interrupt has occurred When "0" is read: Interrupt has not occurred

When "1" is written: Flag is reset When "0" is written: Invalid

The interrupt factor flags ISW10 and ISW1 correspond to 10 Hz and 1 Hz stopwatch timer interrupts, respectively. The software can judge from these flags whether there is a stopwatch timer interrupt. However, even if the interrupt is masked, the flags are set to "1" by the overflow of the corresponding counters. These flags are reset to "0" by writing "1" to them. After an interrupt occurs, the same interrupt will occur again if the interrupt enabled state (I flag = "1") is set or the RETI instruction is executed unless the interrupt factor flag is reset. Therefore, be sure to reset (write "1" to) the interrupt factor flag in the interrupt service routine before shifting to the interrupt enabled state. At initial reset, these flags are set to "0".

4.9.5 Programming notes

(1) When data of the counter is read at run mode, perform the reading after suspending the counter once

and then set SWRUN to "1" again. Moreover, it is required that the suspension period not exceed 976 µsec (1/4 cycle of 256 Hz).

(2) After an interrupt occurs, the same interrupt will occur again if the interrupt enabled state (I flag =

64 EPSON S1C63558 TECHNICAL MANUAL

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Programmable Timer)

4.10 Programmable Timer

4.10.1 Configuration of programmable timer

The S1C63558 has two 8-bit programmable timer systems (timer 0 and timer 1) built-in. Timer 0 and timer 1 are composed of 8-bit presettable down counters and they can be used as 8-bit × 2 channel programmable timers. Timer 0 also has an event counter function using the K13 input port terminal. Figure 4.10.1.1 shows the configuration of the programmable timer.

The programmable timer is designed to count down from the initial value set in the counter with software. An underflow according to the initial value occurs by counting down and is used for the following functions:

•Presetting the initial value to the counter to generate the periodical underflow signal

• Generating an interrupt

• Generating a TOUT signal output from the R02 output port terminal

• Generating the synchronous clock source for the serial interface (timer 1 underflow is used, and it is possible to set the transfer rate)

Interrupt request

TOUT (R02)

Serial interface

OSC1 oscillation circuit

OSC3 oscillation circuit

Interrupt control circuit

Output port

R02

OSC1

OSC3

K13

Timer 0 Run/Stop

PTRUN0

Selector

CKSEL0

Timer 1 Run/Stop

PTRUN1

Selector

CKSEL1

Input port

K13

Divider

Programmable timer 0

Prescaler

2,048

setting

PTPS00 PTPS01

Timer function setting

FCSEL PLPOL

Pulse polarity setting

Programmable timer 1

1/2

Selector

PTOUT

CHSEL

1/2

Prescaler

Prescaler setting

PTPS10 PTPS11

Fig. 4.10.1.1 Configuration of programmable timer

PTRST0

Timer 0 reset

Clock control circuit

PTRST1

Timer 1 reset

Clock control circuit

Reload data register

RLD00–RLD07

8-bit

down counter

Data buffer

PTD00–PTD07

EVCNT

Event counter mode setting

Reload data register

RLD10–RLD17

8-bit

down counter

Data buffer

PTD10–PTD17

Underflow signal

Data bus

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4.10.2 Setting of initial value and counting down

Timers 0 and 1 each have a down counter and reload data register.

The reload data registers RLD00–RLD07 (timer 0) and RLD10–RLD17 (timer 1) are used to set the initial value to the down counter. By writing "1" to the timer reset bit PTRST0 (timer 0) or PTRST1 (timer 1), the down counter loads the initial value set in the reload register RLD. Therefore, down-counting is executed from the stored initial value by the input clock.

The registers PTRUN0 (timer 0) and PTRUN1 (timer 1) are provided to control the RUN/STOP for timers 0 and 1. By writing "1" to the register after presetting the reload data to the down counter, the down counter starts counting down. Writing "0" stops the input count clock and the down counter stops counting. This control (RUN/STOP) does not affect the counter data. The counter maintains its data while stopped, and can restart counting continuing from that data.

The counter data can be read via the data buffers PTD00–PTD07 (timer 0) and PTD10–PTD17 (timer 1) in optional timing. However, the counter has the data hold function the same as the clock timer, that holds the high-order data when the low-order data is read in order to prevent the borrowing operation between low- and high-order reading, therefore be sure to read the low-order data first.

The counter reloads the initial value set in the reload data register RLD when an underflow occurs through the count down. It continues counting down from the initial value after reloading. In addition to reloading the counter, this underflow signal controls the interrupt generation, pulse (TOUT signal) output and clock supplying to the serial interface.

PTRUN0 (1)

PTRST0 (1)

RLD00–07 (10–17)

Input clock

PTD07 (17)

PTD06 (16)

PTD05 (15)

PTD04 (14)

PTD03 (13)

PTD02 (12)

PTD01 (11)

PTD00 (10)

A6H F3H

Preset Reload &

Interrupt generation

Fig. 4.10.2.1 Basic operation timing of down counter

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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Programmable Timer)

4.10.3 Counter mode

The programmable timer can operate in two counter modes, timer mode and event counter mode. It can be selected by software.

(1)Timer mode

The timer mode counts down using the prescaler output as an input clock. In this mode, the programmable timer operates as a periodical timer using the OSC1 or OSC3 oscillation clock as a clock source. Timer 0 can operate in both the timer mode and the event counter mode. The mode can be switched using the timer 0 counter mode selection register EVCNT. When the EVCNT register is set to "0", timer 0 operates in the timer mode. Timer 1 operates only in the timer mode. At initial reset, this mode is set.

Refer to Section 4.10.2, "Setting of initial value and counting down" for basic operation and control.

The input clock in the timer mode is generated by the prescaler built into the programmable timer. The prescaler generates the input clock by dividing the OSC1 or OSC3 oscillation clock. Refer to the next section for setting the input clock.

(2)Event counter mode

The timer 0 has an event counter function that counts an external clock input to the input port K13. This function is selected by writing "1" to the timer 0 counter mode selection register EVCNT. The timer 1 operates only in the timer mode, and cannot be used as an event counter.

In the event counter mode, the clock is supplied to timer 0 from outside of the IC, therefore, the settings of the timer 0 prescaler division ratio selection registers PTPS00 and PTPS01 and the settings of the timer 0 source clock selection register CKSEL0 become invalid.

Count down timing can be selected from either the falling or rising edge of the input clock using the timer 0 pulse polarity selection register PLPOL. When "0" is written to the PLPOL register, the falling edge is selected, and when "1" is written, the rising edge is selected. The count down timing is shown in Figure 4.10.3.1.

EVCNT

PTRUN0

PLPOL

K13 input

Count data

n n-1 n-2 n-3 n-4 n-5 n-6

Fig. 4.10.3.1 Timing chart in event counter mode

The event counter mode also includes a noise reject function to eliminate noise such as chattering on the external clock (K13 input signal). This function is selected by writing "1" to the timer 0 function selection register FCSEL. When "with noise rejector" is selected, an input pulse width for both low and high levels must be 0.98 msec* or more to count reliably. The noise rejecter allows the counter to input the clock at the second falling edge of the internal 2,048 Hz* signal after changing the input level of the K13 input port terminal. Consequently, the pulse width of noise that can reliably be rejected is 0.48 msec* or less. (∗: f

OSC1 = 32.768 kHz).

Figure 4.10.3.2 shows the count down timing with noise rejecter.

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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Programmable Timer)

2,048 Hz ∗

K13 input Counter

input clock ∗ Counter data n n-1 n-2 n-3

∗

1 When f

OSC1

∗

2 When PLPOL register is set to "0"

is 32.768 kHz

Fig. 4.10.3.2 Count down timing with noise rejecter

The operation of the event counter mode is the same as the timer mode except it uses the K13 input as the clock. Refer to Section 4.10.2, "Setting of initial value and counting down" for basic operation and control.

4.10.4 Setting of input clock in timer mode

Timer 0 and timer 1 each include a prescaler. The prescalers generate the input clock for each timer by dividing the source clock supplied from the OSC1 or OSC3 oscillation circuit. The source clock (OSC1 or OSC3) and the division ratio of the prescaler can be selected with software for timer 0 and timer 1 individually. The set input clock is used for the count clock during operation in the timer mode. When the timer 0 is used in the event counter mode, the following settings become invalid.

The input clock is set in the following sequence.

(1)Selection of source clock

Select the source clock input to each prescaler from either OSC1 or OSC3. This selection is done using the source clock selection registers CKSEL0 (timer 0) and CKSEL1 (timer 1); when "0" is written to the register, OSC1 is selected and when "1" is written, OSC3 is selected. When the OSC3 oscillation clock is selected for the clock source, it is necessary to turn the OSC3 oscillation ON, prior to using the programmable timer. However the OSC3 oscillation circuit requires a time at least 5 msec from turning the circuit ON until the oscillation stabilizes. Therefore, allow an adequate interval from turning the OSC3 oscillation circuit ON to starting the programmable timer. Refer to Section 4.3, "Oscillation Circuit", for the control and notes of the OSC3 oscillation circuit. At initial reset, the OSC3 oscillation circuit is set in the OFF state.

(2)Selection of prescaler division ratio

Select the division ratio for each prescaler from among 4 types. This selection is done using the prescaler division ratio selection registers PTPS00/PTPS01 (timer 0) and PTPS10/PTPS11 (timer 1). Table 4.10.4.1 shows the correspondence between the setting value and the division ratio.

Table 4.10.4.1 Selection of prescaler division ratio

PTPS11 PTPS01

By writing "1" to the register PTRUN0 (timer 0) or PTRUN1 (timer 1), the prescaler inputs the source clock and outputs the clock divided by the selected division ratio. The counter starts counting down by inputting the clock.

68 EPSON S1C63558 TECHNICAL MANUAL

PTPS10 PTPS00

1 1 0 0

Prescaler division ratio

1 0 1 0

Source clock / 256 Source clock / 32 Source clock / 4 Source clock / 1

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Programmable Timer)

4.10.5 Interrupt function

The programmable timer can generate an interrupt due to an underflow of the timer 0 and timer 1. See Figure 4.10.2.1 for the interrupt timing.

An underflow of timer 0 and timer 1 sets the corresponding interrupt factor flag IPT0 (timer 0) or IPT1 (timer 1) to "1", and generates an interrupt. The interrupt can also be masked by setting the corresponding interrupt mask register EIPT0 (timer 0) or EIPT1 (timer 1). However, the interrupt factor flag is set to "1" by an underflow of the corresponding timer regardless of the interrupt mask register setting.

4.10.6 Setting of TOUT output

The programmable timer can generate a TOUT signal due to an underflow of timer 0 or timer 1. The TOUT signal is generated by dividing the underflows in 1/2. It is possible to select which timer's underflow is to be used by the TOUT output channel selection register CHSEL. When "0" is written to the CHSEL register, timer 0 is selected and when "1" is written, timer 1 is selected. Figure 4.10.6.1 shows the TOUT signal waveform when the channel is changed.

CHSEL 0 1

Timer 0 underflow Timer 1 underflow

TOUT output (R02)

Fig. 4.10.6.1 TOUT signal waveform at channel change

The TOUT signal can be output from the R02 output port terminal. Programmable clocks can be supplied to external devices. Figure 4.10.6.2 shows the configuration of the output port R02.

TOUT

PTOUT

R02 (TOUT)

Data bus

R02

R02HIZ

Fig. 4.10.6.2 Configuration of R02

The output of a TOUT signal is controlled by the PTOUT register. When "1" is written to the PTOUT register, the TOUT signal is output from the R02 output port terminal and when "0" is written, the terminal goes to a high (V

DD) level. However, the data register R02 must always be "1" and the high

impedance control register R02HIZ must always be "0" (data output state).

Since the TOUT signal is generated asynchronously from the PTOUT register, a hazard within 1/2 cycle is generated when the signal is turned ON and OFF by setting the register. Figure 4.10.6.3 shows the output waveform of the TOUT signal.

R02HIZ register

Fix at "0"

R02 register

PTOUT register

TOUT output

Fix at "1"

"1""0" "0"

Fig. 4.10.6.3 Output waveform of the TOUT signal

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4.10.7 Transfer rate setting for serial interface

The signal that is made from underflows of timer 1 by dividing them in 1/2, can be used as the clock source for the serial interface. The programmable timer outputs the clock to the serial interface by setting timer 1 into RUN state (PTRUN = "1"). It is not necessary to control with the PTOUT register.

PTRUN1

Timer 1 underflow

Source clock for serial I/F

Fig. 4.10.7.1 Synchronous clock of serial interface

A setting value for the RLD1X register according to a transfer rate is calculated by the following expression:

RLD1X = fosc / (32 ∗ bps ∗ division ratio of the prescaler) - 1

fosc: Oscillation frequency (OSC1/OSC3) bps:Transfer rate

(00H can be set to RLD1X)

Be aware that the maximum clock frequency for the serial interface is limited to 1 MHz when OSC3 is used as the clock source.

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4.10.8 I/O memory of programmable timer

Table 4.10.8.1 shows the I/O addresses and the control bits for the programmable timer.

Table 4.10.8.1 Control bits of programmable timer

Address Comment

FFC0H

CHSEL PTOUT CKSEL1 CKSEL0

FFC1H

PTPS01 PTPS00 PTRST0 PTRUN0

FFC2H

PTPS11 PTPS10 PTRST1 PTRUN1

FFC3H

RLD03 RLD02 RLD01 RLD00

FFC4H

RLD07 RLD06 RLD05 RLD04

FFC5H

RLD13 RLD12 RLD11 RLD10

FFC6H

RLD17 RLD16 RLD15 RLD14

FFC7H

PTD03 PTD02 PTD01 PTD00

FFC8H

PTD07 PTD06 PTD05 PTD04

FFC9H

PTD13 PTD12 PTD11 PTD10

FFCAH

PTD17 PTD16 PTD15 PTD14

FFCBH

FFE2H

FFF2H

*1 Initial value at initial reset *2 Not set in the circuit *3 Constantly "0" when being read

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D3 D2

D1 D0 Name Init

0 EVCNT FCSEL PLPOL

R R/W

R/W

W R/WR/W

R/W

00EIPT1 EIPT0

R R/W

00IPT1 IPT0

R R/W

∗

0 EVCNT FCSEL PLPOL CHSEL

PTOUT CKSEL1 CKSEL0 PTPS01 PTPS00

∗

PTRST0 PTRUN0

PTPS11 PTPS10

∗

PTRST1 PTRUN1

RLD03 RLD02 RLD01 RLD00 RLD07 RLD06 RLD05 RLD04 RLD13 RLD12 RLD11 RLD10 RLD17 RLD16 RLD15 RLD14 PTD03 PTD02 PTD01 PTD00 PTD07 PTD06 PTD05 PTD04 PTD13 PTD12 PTD11 PTD10 PTD17 PTD16 PTD15 PTD14

∗

EIPT1 EIPT0

∗

IPT1 IPT0

–

0 0 0 0 0 0 0 0 0

–

0 0 0

–

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0 – –

00Enable

– –

∗1

∗

Event ct.

With NR

Timer1

On OSC3 OSC3

Reset

Run

Reset

Run

Enable

(R)

Yes (W)

Reset

Timer

No NR

Timer0

Off OSC1 OSC1

Invalid

Stop

Invalid

Stop

Mask Mask

(R)

(W)

Invalid

division ratio selection

Timer 0 reset (reload)

[PTPS01, 00] Division ratio

1/111/421/3231/256

Timer 0 Run/Stop Prescaler 1

division ratio selection

Timer 1 reset (reload)

[PTPS11, 10] Division ratio

1/111/421/3231/256

Timer 1 Run/Stop MSB

Programmable timer 0 reload data (low-order 4 bits) LSB

MSB Programmable timer 0 reload data (high-order 4 bits) LSB

MSB Programmable timer 1 reload data (low-order 4 bits) LSB

MSB Programmable timer 1 reload data (high-order 4 bits) LSB

MSB Programmable timer 0 data (low-order 4 bits) LSB

MSB Programmable timer 0 data (high-order 4 bits) LSB

MSB Programmable timer 1 data (low-order 4 bits) LSB

MSB Programmable timer 1 data (high-order 4 bits) LSB

Unused Unused Interrupt mask register (Programmable timer 1) Interrupt mask register (Programmable timer 0) Unused Unused Interrupt factor flag (Programmable timer 1) Interrupt factor flag (Programmable timer 0)

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Programmable Timer)

CKSEL0: Prescaler 0 source clock selection register (FFC1H•D0) CKSEL1: Prescaler 1 source clock selection register (FFC1H•D1)

Selects the source clock of the prescaler.

When "1" is written: OSC3 clock When "0" is written: OSC1 clock

Reading: Valid

The source clock for the prescaler is selected from OSC1 or OSC3. When "0" is written to the CKSEL0 register, the OSC1 clock is selected as the input clock for the prescaler 0 (for timer 0) and when "1" is written, the OSC3 clock is selected. Same as above, the source clock for prescaler 1 is selected by the CKSEL1 register. When the event counter mode is selected to timer 0, the setting of the CKSEL0 register becomes invalid. At initial reset, these registers are set to "0".

PTPS00, PTPS01: Timer 0 prescaler division ratio selection register (FFC2H•D2, D3) PTPS10, PTPS11: Timer 1 prescaler division ratio selection register (FFC3H•D2, D3)

Selects the division ratio of the prescaler. Two bits of PTPS00 and PTPS01 are the prescaler division ratio selection register for timer 0, and two bits of PTPS10 and PTPS11 are for timer 1. The prescaler division ratios that can be set by these registers are shown in Table 4.10.8.2.

Table 4.10.8.2 Selection of prescaler division ratio

PTPS11 PTPS01

PTPS10 PTPS00

1 1 0 0

Prescaler division ratio

1 0 1 0

Source clock / 256 Source clock / 32 Source clock / 4 Source clock / 1

When the event counter mode is selected to timer 0, the setting of the PTPS00 and PTPS01 becomes invalid. At initial reset, these registers are set to "0".

EVCNT: Timer 0 counter mode selection register (FFC0H•D2)

Selects a counter mode for timer 0.

When "1" is written: Event counter mode When "0" is written: Timer mode

Reading: Valid

The counter mode for timer 0 is selected from either the event counter mode or timer mode. When "1" is written to the EVCNT register, the event counter mode is selected and when "0" is written, the timer mode is selected. At initial reset, this register is set to "0".

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FCSEL: Timer 0 function selection register (FFC0H•D1)

Selects whether the noise rejector of the clock input circuit will be used or not in the event counter mode.

When "1" is written: With noise rejecter When "0" is written: Without noise rejecter

Reading: Valid

When "1" is written to the FCSEL register, the noise rejecter is used and counting is done by an external clock (K13) with 0.98 msec* or more pulse width. The noise rejecter allows the counter to input the clock at the second falling edge of the internal 2,048 Hz* signal after changing the input level of the K13 input port terminal. Consequently, the pulse width of noise that can reliably be rejected is 0.48 msec* or less. (∗: f

OSC1 = 32.768 kHz).

When "0" is written to the FCSEL register, the noise rejector is not used and the counting is done directly by an external clock input to the K13 input port terminal. Setting of this register is effective only when timer 0 is used in the event counter mode. At initial reset, this register is set to "0".

PLPOL: Timer 0 pulse polarity selection register (FFC0H•D0)

Selects the count pulse polarity in the event counter mode.

When "1" is written: Rising edge When "0" is written: Falling edge

Reading: Valid

The count timing in the event counter mode (timer 0) is selected from either the falling edge of the external clock input to the K13 input port terminal or the rising edge. When "0" is written to the PLPOL register, the falling edge is selected and when "1" is written, the rising edge is selected. Setting of this register is effective only when timer 0 is used in the event counter mode. At initial reset, this register is set to "0".

RLD00–RLD07: Timer 0 reload data register (FFC4H, FFC5H) RLD10–RLD17: Timer 1 reload data register (FFC6H, FFC7H)

Sets the initial value for the counter. The reload data written in this register is loaded to the respective counters. The counter counts down using the data as the initial value for counting. Reload data is loaded to the counter when the counter is reset by writing "1" to the PTRST0 or PTRST1 register, or when counter underflow occurs. At initial reset, these registers are set to "00H".

PTD00–PTD07: Timer 0 counter data (FFC8H, FFC9H) PTD10–PTD17: Timer 1 counter data (FFCAH, FFCBH)

Count data in the programmable timer can be read from these latches. The low-order 4 bits of the count data in timer 0 can be read from PTD00–PTD03, and the high-order data can be read from PTD04–PTD07. Similarly, for timer 1, the low-order 4 bits can be read from PTD10– PTD13, and the high-order data can be read from PTD14–PTD17. Since the high-order 4 bits are held by reading the low-order 4 bits, be sure to read the low-order 4 bits first. Since these latches are exclusively for reading, the writing operation is invalid. At initial reset, these counter data are set to "00H".

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PTRST0: Timer 0 reset (reload) (FFC2H•D1) PTRST1: Timer 1 reset (reload) (FFC3H•D1)

Resets the timer and presets reload data to the counter.

When "1" is written: Reset When "0" is written: No operation

Reading: Always "0"

By writing "1" to PTRST0, the reload data in the reload register PLD00–PLD07 is preset to the counter in timer 0. Similarly, the reload data in PLD10–PLD17 is preset to the counter in timer 1 by PTRST1. When the counter is preset in the RUN status, the counter restarts immediately after presetting. In the case of STOP status, the reload data is preset to the counter and is maintained. No operation results when "0" is written. Since these bits are exclusively for writing, always set to "0" during reading.

PTRUN0: Timer 0 RUN/STOP control register (FFC2H•D0) PTRUN1: Timer 1 RUN/STOP control register (FFC3H•D0)

Controls the RUN/STOP of the counter.

When "1" is written: RUN When "0" is written: STOP

Reading: Valid

The counter in timer 0 starts counting down by writing "1" to the PTRUN0 register and stops by writing "0". In STOP status, the counter data is maintained until the counter is reset or is set in the next RUN status. When STOP status changes to RUN status, the data that has been maintained can be used for resuming the count. Same as above, the timer 1 counter is controlled by the PTRUN1 register. At initial reset, these registers are set to "0".

CHSEL: TOUT output channel selection register (FFC1H•D3)

Selects the channel used for TOUT signal output.

When "1" is written: Timer 1 When "0" is written: Timer 0

Reading: Valid

This register selects which timer's underflow (timer 0 or timer 1) is used to generate a TOUT signal. When "0" is written to the CHSEL register, timer 0 is selected and when "1" is written, timer 1 is selected. At initial reset, this register is set to "0".

PTOUT: TOUT output control register (FFC1H•D2)

Turns TOUT signal output ON and OFF.

When "1" is written: ON When "0" is written: OFF

Reading: Valid

PTOUT is the output control register for the TOUT signal. When "1" is written to the register, the TOUT signal is output from the output port terminal R02 and when "0" is written, the terminal goes to a high (V

DD) level. However, the data register R02 must always be "1" and the high impedance control register

R02HIZ must always be "0" (data output state). At initial reset, this register is set to "0".

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EIPT0: Timer 0 interrupt mask register (FFE2H•D0) EIPT1: Timer 1 interrupt mask register (FFE2H•D1)

These registers are used to select whether to mask the programmable timer interrupt or not.

When "1" is written: Enabled When "0" is written: Masked

Reading: Valid

Timer 0 and timer 1 interrupts can be masked individually by the interrupt mask registers EIPT0 (timer 0) and EIPT1 (timer 1). At initial reset, these registers are set to "0".

IPT0: Timer 0 interrupt factor flag (FFF2H•D0) IPT1: Timer 1 interrupt factor flag (FFF2H•D1)

These flags indicate the status of the programmable timer interrupt.

When "1" is read: Interrupt has occurred When "0" is read: Interrupt has not occurred

When "1" is written: Flag is reset When "0" is written: Invalid

The interrupt factor flags IPT0 and IPT1 correspond to timer 0 and timer 1 interrupts, respectively. The software can judge from these flags whether there is a programmable timer interrupt. However, even if the interrupt is masked, the flags are set to "1" by the underflows of the corresponding counters. These flags are reset to "0" by writing "1" to them. After an interrupt occurs, the same interrupt will occur again if the interrupt enabled state (I flag = "1") is set or the RETI instruction is executed unless the interrupt factor flag is reset. Therefore, be sure to reset (write "1" to) the interrupt factor flag in the interrupt service routine before shifting to the interrupt enabled state. At initial reset, these flags are set to "0".

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4.10.9 Programming notes

(1) When reading counter data, be sure to read the low-order 4 bits (PTD00–PTD03, PTD10–PTD13) first.

Furthermore, the high-order 4 bits (PTD04–PTD07, PTD14–PTD17) should be read within 0.73 msec (when f

(2) The programmable timer actually enters RUN/STOP status in synchronization with the falling edge

of the input clock after writing to the PTRUN0/PTRUN1 register. Consequently, when "0" is written to the PTRUN0/PTRUN1 register, the timer enters STOP status at the point where the counter is decremented (-1). The PTRUN0/PTRUN1 register maintains "1" for reading until the timer actually stops. Figure 4.10.9.1 shows the timing chart for the RUN/STOP control.

OSC1 is 32.768 kHz) of reading the low-order 4 bits (PTD00–PTD03, PTD10–PTD13).

Input clock

PTRUN0/PTRUN1 (RD)

PTRUN0/PTRUN1 (WR)

PTD0X/PTD1X 42H 41H 40H 3FH 3EH 3DH

"1" (RUN) writing

"0" (STOP) writing

Fig. 4.10.9.1 Timing chart for RUN/STOP control

It is the same even in the event counter mode. Therefore, be aware that the counter does not enter RUN/STOP status if a clock is not input after setting the RUN/STOP control register (PTRUN0).

(3) Since the TOUT signal is generated asynchronously from the PTOUT register, a hazard within 1/2

cycle is generated when the signal is turned ON and OFF by setting the register.

(4) When the OSC3 oscillation clock is selected for the clock source, it is necessary to turn the OSC3

oscillation ON, prior to using the programmable timer. However the OSC3 oscillation circuit requires a time at least 5 msec from turning the circuit ON until the oscillation stabilizes. Therefore, allow an adequate interval from turning the OSC3 oscillation circuit ON to starting the programmable timer. Refer to Section 4.3, "Oscillation Circuit", for the control and notes of the OSC3 oscillation circuit. At initial reset, the OSC3 oscillation circuit is set in the OFF state.

(5) After an interrupt occurs, the same interrupt will occur again if the interrupt enabled state (I flag =

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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface)

4.11 Serial Interface

4.11.1 Configuration of serial interface

The S1C63558 incorporates 2 channels (SIF (1), SIF (2)) of full duplex serial interface circuits (when asynchronous system is selected) that allows the user to select either clock synchronous system or asynchronous system. The data transfer method can be selected in software. When the clock synchronous system is selected, 8-bit data transfer is possible. When the asynchronous system is selected, either 7-bit or 8-bit data transfer is possible, and a parity check of received data and the addition of a parity bit for transmitting data can automatically be done by selecting in software.

Differences between SIF (1) and SIF (2)

SIF (1) and SIF (2) are independently separated serial interface blocks that have the same functions and circuit configurations. The serial I/O terminals and control registers are assigned as follows: Serial I/O terminals: SIF (1) → P10–P13

SIF (2) → P30–P33

Control register addresses: SIF (1) → FF70H–FF75H, FFE3H, FFF3H

SIF (2) → FF58H–FF5DH, FFE8H, FFF8H

To distinguish the control bits of SIF (1) from SIF (2), "S" is added to the end of the name for the SIF (2) control bits. Example: SIF (1) → ESIF, SIF (2) → ESIFS

When using the FSK demodulator, SIF (2) is used for data input. SIF (1) cannot be used for this purpose.

Note: Explanation made in this section is only for SIF (1). Be aware that "S" for the SIF (2) control bits is

omitted. Further, the serial I/O terminal names are explained using P10–P13.

Figure 4.11.1.1 shows the configuration of the serial interface (1). The serial interface (2) has the same configuration except for the terminals.

Data bus

SIN(P10)

SCLK(P12)

Serial I/O control & status register

Serial input control circuit

Start bit detection circuit

Received data buffer

Received data shift register

Clock control circuit

Error detection circuit

OSC3

Interrupt control circuit

Transmitting data shift register

OSC3 oscillation circuit

Programmable timer 1 underflow signal

Serial output control circuit

READY output control circuit

Interrupt request

SOUT(P11)

SRDY(P13)

Fig. 4.11.1.1 Configuration of serial interface

Serial interface input/output terminals, SIN, SOUT, SCLK and SRDY are shared with the I/O ports P10– P13. In order to utilize these terminals for the serial interface input/output terminals, proper settings have to be made with registers ESIF, SMD0 and SMD1. (At initial reset, these terminals are set as I/O port terminals.) The direction of I/O port terminals set for serial interface input/output terminals are determined by the signal and transfer mode for each terminal. Furthermore, the settings for the corresponding I/O control registers for the I/O ports become invalid.

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Table 4.11.1.1 Configuration of input/output terminals

Terminal When serial interface is selected

P10 P11 P12 P13

SIN

SOUT SCLK SRDY

* The terminals used may vary depending on the transfer mode.

SIN and SOUT are serial data input and output terminals which function identically in clock synchronous system and asynchronous system. SCLK is exclusively for use with clock synchronous system and functions as a synchronous clock input/output terminal. SRDY is exclusively for use in clock synchronous slave mode and functions as a send-receive ready signal output terminal. When asynchronous system is selected, since SCLK and SRDY are superfluous, the I/O port terminals P12 and P13 can be used as I/O ports. In the same way, when clock synchronous master mode is selected, since SRDY is superfluous, the I/O port terminal P13 can be used as I/O port.

4.11.2 Mask option

Since the input/output terminals of the serial interface is shared with the I/O ports (P10–P13), the mask option that selects the output specification for the I/O port is also applied to the serial interface. The output specification of the terminals SOUT, SCLK (for clock synchronous master mode) and SRDY (for clock synchronous slave mode) that are used as output in the input/output port of the serial interface is respectively selected by the mask options of P11, P12 and P13. Either complementary output or Nchannel open drain output can be selected as the output specification. However, when N-channel open drain output is selected, do not apply a voltage exceeding the power supply voltage to the terminal.

Furthermore, the pull-up resistor for the SIN terminal and the SCLK terminal (for clock synchronous slave mode) that are used as input terminals can be selected by the mask options of P10 and P12. When "without pull-up" is selected, take care that the floating status does not occur.

4.11.3 Transfer modes

There are four transfer modes for the serial interface and mode selection is made by setting the two bits of the mode selection registers SMD0 and SMD1 as shown in the table below.

Table 4.11.3.1 Transfer modes

SMD1/SMD1S SMD0/SMD0S Mode

1 1 0 0

Table 4.11.3.2 Terminal settings corresponding to each transfer mode

Mode SIN

Asynchronous 8-bit Asynchronous 7-bit Clock synchronous slave Clock synchronous master

At initial reset, transfer mode is set to clock synchronous master mode.

1 0 1 0

8-bit asynchronous 7-bit asynchronous Clock synchronous slave Clock synchronous master

SOUT SCLK SRDY

Input Input Input Input

Output Output Output Output

P12 P12

Input

Output

P13 P13

Output

P13

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Clock synchronous master mode

In this mode, the internal clock is utilized as a synchronous clock for the built-in shift registers, and 8bit clock synchronous serial transfers can be performed with this serial interface as the master. The synchronous clock is also output from the SCLK terminal which enables control of the external (slave side) serial I/O device. Since the SRDY terminal is not utilized in this mode, it can be used as an I/O port. Figure 4.11.3.1(a) shows the connection example of input/output terminals in the clock synchronous master mode.

Clock synchronous slave mode

In this mode, a synchronous clock from the external (master side) serial input/output device is utilized and 8-bit clock synchronous serial transfers can be performed with this serial interface as the slave. The synchronous clock is input to the SCLK terminal and is utilized by this interface as the synchronous clock. Furthermore, the SRDY signal indicating the transmit-receive ready status is output from the SRDY terminal in accordance with the serial interface operating status. In the slave mode, the settings for registers SCS0 and SCS1 used to select the clock source are invalid. Figure 4.11.3.1(b) shows the connection example of input/output terminals in the clock synchronous slave mode.

7-bit asynchronous mode

In this mode, 7-bit asynchronous transfer can be performed. Parity check during data reception and addition of parity bit (odd/even/none) during transmitting can be specified and data processed in 7 bits with or without parity. Since this mode employs the internal clock, the SCLK terminal is not used. Furthermore, since the SRDY terminal is not utilized either, both of these terminals can be used as I/O ports. Figure 4.11.3.1(c) shows the connection example of input/output terminals in the asynchronous mode.

8-bit asynchronous 8-bit mode

In this mode, 8-bit asynchronous transfer can be performed. Parity check during data reception and addition of parity bit (odd/even/none) during transmitting can be specified and data processed in 8 bits with or without parity. Since this mode employs the internal clock, the SCLK terminal is not used. Furthermore, since the SRDY terminal is not utilized either, both of these terminals can be used as I/O ports. Figure 4.11.3.1(c) shows the connection example of input/output terminals in the asynchronous mode.

S1C63558

SIN(P10)

SOUT(P11)

SCLK(P12)

Input port(Kxx)

(a) Clock synchronous master mode

External serial device

Data input

Data output

CLOCK input

READY output

S1C63558

SIN(P10)

SOUT(P11)

S1C63558

SIN(P10)

SOUT(P11)

SCLK(P12)

SRDY(P13)

(b) Clock synchronous slave mode

External serial device

Data input

Data output

External serial device

Data input

Data output

CLOCK output

READY input

Fig. 4.11.3.1 Connection examples of serial interface I/O terminals

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4.11.4 Clock source

There are four clock sources and selection is made by setting the two bits of the clock source selection register SCS0 and SCS1 as shown in table below.

Table 4.11.4.1 Clock source

SCS1

1 1 0 0

This register setting is invalid in clock synchronous slave mode and the external clock input from the SCLK terminal is used. When the "programmable timer" is selected, the programmable timer 1 underflow signal is divided by 1/ 2 and this signal used as the clock source. With respect to the transfer rate setting, see "4.10 Programmable Timer". At initial reset, the synchronous clock is set to "f

Whichever clock is selected, the signal is further divided by 1/16 and then used as the synchronous clock. Furthermore, external clock input is used as is for SCLK in clock synchronous slave mode.

SCS0

1 0 1 0

Clock source

Programmable timer

OSC3 / 93 (2400 bps)

OSC3 / 372 (600 bps)

f fOSC3 / 186 (1200 bps)

OSC3/186".

OSC3 oscillation circuit

Programmable timer 1 underflow signal

fOSC3

SCLK

1/93

1/372

Divider Selector Selector

1/186

1/2

(Clock synchronous slave mode)

1/16

Synchronous clock

Fig. 4.11.4.1 Division of the synchronous clock

Table 4.11.4.2 shows an examples of transfer rates and OSC3 oscillation frequencies when the clock source is set to programmable timer.

Table 4.11.4.2 OSC3 oscillation frequencies and transfer rates

Transfer rate

(bps)

9,600 4,800 2,400 1,200

600 300 150

OSC3

PSC1X

0 (1/1) 0 (1/1) 0 (1/1) 0 (1/1) 0 (1/1) 1 (1/4) 1 (1/4)

= 3.580 MHz

RLD1X

0CH

17H

2FH 5DH BAH 5DH BAH

When the demultiplied signal of the OSC3 oscillation circuit is made the clock source, it is necessary to turn the OSC3 oscillation ON, prior to using the serial interface. A time interval of several msec to several 10 msec, from the turning ON of the OSC3 oscillation circuit to until the oscillation stabilizes, is necessary, due to the oscillation element that is used. Consequently, you should allow an adequate waiting time after turning ON of the OSC3 oscillation, before starting transmitting/receiving of serial interface. (The oscillation start time will vary somewhat depending on the oscillator and on the externally attached parts. Refer to the oscillation start time example indicated in Chapter 7, "Electrical Characteristics".) At initial reset, the OSC3 oscillation circuit is set to OFF status.

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4.11.5 Transmit-receive control

Below is a description of the registers which handle transmit-receive control. With respect to transmitreceive control procedures and operations, please refer to the following sections in which these are discussed on a mode by mode basis.

Shift register and receive data buffer

Exclusive shift registers for transmitting and receiving are installed in this serial interface. Consequently, duplex communication simultaneous transmit and receive is possible when the asynchronous system is selected.

Data being transmitted are written to TRXD0–TRXD7 and converted to serial through the shift register and is output from the SOUT terminal.

In the reception section, a receive data buffer is installed separate from the shift register. Data being received are input to the SIN terminal and is converted to parallel through the shift register and written to the receive data buffer. Since the receive data buffer can be read even during serial input operation, the continuous data is received efficiently. However, since buffer functions are not used in clock synchronous mode, be sure to read out data before the next data reception begins.

Transmit enable register and transmit control bit

For transmit control, use the transmit enable register TXEN and transmit control bit TXTRG.

The transmit enable register TXEN is used to set the transmit enable/disable status. When "1" is written to this register to set the transmitting enable status, clock input to the shift register is enabled and the system is ready to transmit data. In the clock synchronous mode, synchronous clock input/ output from the SCLK terminal is also enabled.

The transmit control bit TXTRG is used as the trigger to start transmitting data. Data to be transmitted is written to the transmit data shift register, and when transmitting preparations a recomplete, "1" is written to TXTRG whereupon data transmitting begins. When interrupt has been enabled, an interrupt is generated when the transmission is completed. If there is subsequent data to be transmitted it can be sent using this interrupt. In addition, TXTRG can be read as a status bit. When set to "1", it indicates transmitting operation, and "0" indicates transmitting stop. For details on timing, see the timing chart which gives the timing for each mode.

When not transmitting, set TXEN to "0" to disable transmition.

Receive enable register, receive control bit

For receiving control, use the receive enable register RXEN and receive control bit RXTRG. Receive enable register RXEN is used to set receiving enable/disable status. When "1" is written into this register to set the receiving enable status, clock input to the shift register is enabled and the system is ready to receive data. In the clock synchronous mode, synchronous clock input/output from the SCLK terminal is also enabled. With the above setting, receiving begins and serial data input from the SIN terminal goes to the shift register. The operation of the receive control bit RXTRG is slightly different depending on whether a clock synchronous system or an asynchronous system is being used. In the clock synchronous system, the receive control bit TXTRG is used as the trigger to start receiving data. When received data has been read and the preparation for next data receiving is completed, write "1" into RXTRG to start receiving. (When "1" is written to RXTRG in slave mode, SRDY switches to "0".)

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In an asynchronous system, RXTRG is used to prepare for next data receiving. After reading the received data from the receive data buffer, write "1" into RXTRG to signify that the receive data buffer is empty. If "1" is not written into RXTRG, the overrun error flag OER will be set to "1" when the next receiving operation is completed. (An overrun error will be generated when receiving is completed between reading the received data and the writing of "1" to RXTRG.) In addition, RXTRG can be read as a status bit. In either clock synchronous mode or asynchronous mode, when RXTRG is set to "1", it indicates receiving operation and when set to "0", it indicates that receiving has stopped. For details on timing, see the timing chart which gives the timing for each mode.

When you do not receive, set RXEN to "0" to disable receiving.

4.11.6 Operation of clock synchronous transfer

Clock synchronous transfer involves the transfer of 8-bit data by synchronizing it to eight clocks. The same synchronous clock is used by both the transmitting and receiving sides. When the serial interface is used in the master mode, the clock signal selected using SCS0 and SCS1 is further divided by 1/16 and employed as the synchronous clock. This signal is then sent via the SCLK terminal to the slave side (external serial I/O device). When used in the slave mode, the clock input to the SCLK terminal from the master side (external serial input/output device) is used as the synchronous clock.

In the clock synchronous mode, since one clock line (SCLK) is shared for both transmitting and receiving, transmitting and receiving cannot be performed simultaneously. (Half duplex only is possible in clock synchronous mode.)

Transfer data is fixed at 8 bits and both transmitting and receiving are conducted with the LSB (bit 0) coming first.

SCLK

Data D0 D1 D2 D3 D4 D5 D6 D7

Fig. 4.11.6.1 Transfer data configuration using clock synchronous mode

LSB MSB

Below is a description of initialization when performing clock synchronous transfer, transmit-receive control procedures and operations. With respect to serial interface interrupt, see "4.11.8 Interrupt function".

Initialization of serial interface

When performing clock synchronous transfer, the following initial settings must be made.

(1) Setting of transmitting/receiving disable

To set the serial interface into a status in which both transmitting and receiving are disabled, "0" must be written to both the transmit enable register TXEN and the receive enable register RXEN. Fix these two registers to a disable status until data transfer actually begins.

(2) Port selection

Because serial interface input/output ports SIN, SOUT, SCLK and SRDY are set as I/O port terminals P10–P13 at initial reset, "1" must be written to the serial interface enable register ESIF in order to set these terminals for serial interface use.

(3) Setting of transfer mode

Select the clock synchronous mode by writing the data as indicated below to the two bits of the mode selection registers SMD0 and SMD1.

Master mode: SMD0 = "0", SMD1 = "0" Slave mode: SMD0 = "1", SMD1 = "0"

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(4) Clock source selection

In the master mode, select the synchronous clock source by writing data to the two bits of the clock source selection registers SCS0 and SCS1. (See Table 4.11.4.1.) This selection is not necessary in the slave mode.

The parity enable register EPR is also assigned to this address, however, since parity is not necessary in the clock synchronous mode, parity check will not take place regardless of how they are set.

(5) Clock source control

When the master mode is selected and programmable timer for the clock source is selected, set transfer rate on the programmable timer side. (See "4.10 Programmable Timer".) When the divided signal of OSC3 oscillation circuit is selected for the clock source, be sure that the OSC3 oscillation circuit is turned ON prior to commencing data transfer. (See "4.3 Oscillation Circuit".) Note that the frequency of the serial interface clock is limited to a maximum of 1 MHz.

Data transmit procedure

The control procedure and operation during transmitting is as follows.

(1) Write "0" in the transmit enable register TXEN and the receive enable register RXEN to reset the

serial interface.

(2) Write "1" in the transmit enable register TXEN to set into the transmitting enable status.

(3) Write the transmitting data into TRXD0–TRXD7.

(4) In case of the master mode, confirm the receive

ready status on the slave side (external serial input/ output device), if necessary. Wait until it reaches the receive ready status.

(5) Write "1" in the transmit control bit TXTRG and

start transmitting.

In the master mode, this control causes the synchronous clock to change to enable and to be provided to the shift register for transmitting and output from the SCLK terminal. In the slave mode, it waits for the synchronous clock to be input from the SCLK terminal. The transmitting data of the shift register shifts one bit at a time at each falling edge of the synchronous clock and is output from the SOUT terminal. When the final bit (MSB) is output, the SOUT terminal is maintained at that level, until the next transmitting begins.

The transmitting complete interrupt factor flag ISTR is set to "1" at the point where the data transmitting of the shift register is completed. When interrupt has been enabled, a transmitting complete interrupt is generated at this point. Set the following transmitting data using this interrupt.

(6) Repeat steps (3) to (5) for the number of bytes of

transmitting data, and then set the transmit disable status by writing "0" to the transmit enable register TXEN, when the transmitting is completed.

Data transmitting

TXEN ← 0, RXEN ← 0

TXEN ← 1

Set transmitting data to TRXD0–TRXD7

Receiver ready ?

TXTRG ← 1

Transmit complete ?

Yes

ISTR = 1 ?

Yes

TXEN ← 0

In case of master mode

End

Fig. 4.11.6.2 Transmit procedure in clock

synchronous mode

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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface)

Data receive procedure

The control procedure and operation during receiving is as follows.

(1) Write "0" in the receive enable register RXEN and

transmit enable register TXEN to reset the serial interface.

(2) Write "1" in the receive enable register RXEN to set

into the receiving enable status.

(3) In case of the master mode, confirm the transmit ready

status on the slave side (external serial input/output device), if necessary. Wait until it reaches the transmit ready status.

(4) Write "1" in the receive control bit RXTRG and start

receiving.

In the master mode, this control causes the synchronous clock to change to enable and is provided to the shift register for receiving and output from the SCLK terminal. In the slave mode, it waits for the synchronous clock to be input from the SCLK terminal. The received data input from the SIN terminal is successively incorporated into the shift register in synchronization with the rising edge of the synchronous clock. At the point where the data of the 8th bit has been incorporated at the final (8th) rising edge of the synchronous clock, the content of the shift register is sent to the receive data buffer and the receiving complete interrupt factor flag ISRC is set to "1". When interrupt has been enabled, a receiving complete interrupt is generated at this point.

(5) Read the received data from TRXD0–TRXD7 using

receiving complete interrupt.

(6) Repeat steps (3) to (5) for the number of bytes of

receiving data, and then set the receive disable status by writing "0" to the receive enable register RXEN, when the receiving is completed.

Data receiving

RXEN ← 0, TXEN ← 0

RXEN ← 1

Transmitter ready ?

RXTRG ← 1

ISRC = 1 ?

Received data reading from TRXD0–TRXD7

Receiving complete ?

RXEN ← 0

Yes

In case of master mode

End

Fig. 4.11.6.3 Receiving procedure in clock

synchronous mode

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Transmit/receive ready (SRDY) signal

When this serial interface is used in the clock synchronous slave mode (external clock input), an SRDY signal is output to indicate whether or not this serial interface can transmit/receive to the master side (external serial input/output device). This signal is output from the SRDY terminal and when this interface enters the transmit or receive enable (READY) status, it becomes "0" (Low level) and becomes "1" (High level) when there is a BUSY status, such as during transmit/receive operation. The SRDY signal changes the "1" to "0," immediately after writing "1" into the transmit control bit TXTRG or the receive control bit RXTRG and returns from "0" to "1", at the point where the first synchronous clock has been input (falling edge). When you have set in the master mode, control the transfer by inputting the same signal from the slave side using the input port or I/O port. At this time, since the SRDY terminal is not set and instead P13 functions as the I/O port, you can apply this port for said control.

Timing chart

The timing chart for the clock synchronous system transmission is shown in Figure 4.11.6.4.

TXEN

RXEN

TXTRG (RD)

TXTRG (WR)

SCLK

SOUT D0 D1 D2 D3 D4 D5 D6 D7

Interrupt

(a) Transmit timing for master mode

TXEN

TXTRG (RD)

TXTRG (WR)

SCLK

SOUT D0 D1 D2 D3 D4 D5 D6 D7

SRDY

Interrupt

(b) Transmit timing for slave mode

Fig. 4.11.6.4 Timing chart (clock synchronous system transmission)

RXTRG (RD)

RXTRG (WR)

SCLK

SIN D0 D1 D2 D3 D4 D5 D6 D7

TRXD 7F 1st data

Interrupt

RXEN

RXTRG (RD)

RXTRG (WR)

SCLK

SIN D0 D1 D2 D3 D4 D5 D6 D7

TRXD 7F 1st data

SRDY

Interrupt

(d) Receive timing for slave mode

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4.11.7 Operation of asynchronous transfer

Asynchronous transfer is a mode that transfers by adding a start bit and a stop bit to the front and the back of each piece of serial converted data. In this mode, there is no need to use a clock that is fully synchronized clock on the transmit side and the receive side, but rather transmission is done while adopting the synchronization at the start/stop bits that have attached before and after each piece of data. The RS-232C interface functions can be easily realized by selecting this transfer mode. This interface has separate transmit and receive shift registers and is designed to permit full duplex transmission to be done simultaneously for transmitting and receiving.

For transfer data in the 7-bit asynchronous mode, either 7 bits data (no parity) or 7 bits data + parity bit can be selected. In the 8-bit asynchronous mode, either 8 bits data (no parity) or 8 bits data + parity bit can be selected. Parity can be even or odd, and parity checking of received data and adding a party bit to transmitting data will be done automatically. Thereafter, it is not necessary to be conscious of parity itself in the program. The start bit and stop bit are respectively fixed at one bit and data is transmitted and received by placing the LSB (bit 0) at the front.

Sampling clock

7bit data D0

7bit data +parity

8bit data 8bit data

+parity

Fig. 4.11.7.1 Transfer data configuration for asynchronous system

Here following, we will explain the control sequence and operation for initialization and transmitting / receiving in case of asynchronous data transfer. See "4.11.8 Interrupt function" for the serial interface interrupts.

D1 D2 D3 D4 D5 D6s1 s2

D1 D2 D3 D4 D5 D6 ps1 s2

D1 D2 D3 D4 D5 D6 D7s1 s2

D0 D1 D2 D3 D4 D5 D6 D7s1 p s2

: Start bit (Low level, 1 bit)

: Stop bit (High level, 1 bit)

bit

: Parit

Initialization of serial interface

The below initialization must be done in cases of asynchronous system transfer.

(1) Setting of transmitting/receiving disable

(2) Port selection

Because serial interface input/output terminals SIN and SOUT are set as I/O port terminals P10 and P11 at initial reset, "1" must be written to the serial interface enable register ESIF in order to set these terminals for serial interface use. SCLK and SRDY terminals set in the clock synchronous mode are not used in the asynchronous mode. These terminals function as I/O port terminals P12 and P13.

(3) Setting of transfer mode

Select the asynchronous mode by writing the data as indicated below to the two bits of the mode selection registers SMD0 and SMD1.

7-bit mode: SMD0 = "0", SMD1 = "1" 8-bit mode: SMD0 = "1", SMD1 = "1"

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(4) Parity bit selection

When checking and adding parity bits, write "1" into the parity enable register EPR to set to "with parity check". As a result of this setting, in the 7-bit asynchronous mode, it has a 7 bits data + parity bit configuration and in the 8-bit asynchronous mode it has an 8 bits data + parity bit configuration.In this case, parity checking for receiving and adding a party bit for transmitting is done automatically in hardware. Moreover, when "with parity check" has been selected, "odd" or "even" parity must be further selected in the parity mode selection register PMD. When "0" is written to the PMD register to select "without parity check" in the 7-bit asynchronous mode, data configuration is set to 7 bits data (no parity) and in the 8-bit asynchronous mode (no parity) it is set to 8 bits data (no parity) and parity checking and parity bit adding will not be done.

(5) Clock source selection

Select the clock source by writing data to the two bits of the clock source selection registers SCS0 and SCS1. (See Table 4.11.4.1.)

(6) Clock source control

When the programmable timer is selected for the clock source, set transfer rate on the programmable timer side. (See "4.10 Programmable Timer".) When the divided signal of OSC3 oscillation circuit is selected for the clock source, be sure that the OSC3 oscillation circuit is turned ON prior to commencing data transfer. (See "4.3 Oscillation Circuit".)

Data transmit procedure

The control procedure and operation during transmitting is as follows.

(1) Write "0" in the transmit enable register TXEN to reset the

serial interface.

Data transmitting

(2) Write "1" in the transmit enable register TXEN to set into

the transmitting enable status.

(3)

Write the transmitting data into TRXD0–TRXD7. Also, when 7-bit data is selected, the TRXD7 data becomes invalid.

(4) Write "1" in the transmit control bit TXTRG and start

transmitting. This control causes the shift clock to change to enable and a start bit (LOW) is output to the SOUT terminal in synchronize to its rising edge. The transmitting data set to the shift register is shifted one bit at a time at each rising edge of the clock thereafter and is output from the SOUT terminal. After the data output, it outputs a stop bit (HIGH) and HIGH level is maintained until the next start bit is output.

The transmitting complete interrupt factor flag ISTR is set to "1" at the point where the data transmitting is completed. When interrupt has been enabled, a transmitting complete interrupt is generated at this point. Set the following transmitting data using this interrupt.

(5) Repeat steps (3) to (4) for the number of bytes of trans-

mitting data, and then set the transmit disable status by writing "0" to the transmit enable register TXEN, when the transmitting is completed.

TXEN ← 0

TXEN ← 1

Set transmitting data to TRXD0–TRXD7

TXTRG ← 1

Transmit complete ?

ISTR = 1 ?

Yes

TXEN ← 0

End

Fig. 4.11.7.2 Transmit procedure in

asynchronous mode

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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface)

Data receive procedure

The control procedure and operation during receiving is as follows. (1)

Write "0" in the receive enable register RXEN to set the receiving disable status

Data receiving

and to reset the respective PER, OER, FER flags that indicate parity, overrun and framing errors.

(2)

Write "1" in the receive enable register

RXEN ← 0

Resets error flags

PER, OER and FER

RXEN to set into the receiving enable status.

(3)

The shift clock will change to enable from the point where the start bit (LOW) has been input from the SIN terminal and the receive data will be synchronized to the rising edge following the second clock, and will thus be successively incorporated into the shift register. After data bits have been incorporated, the stop bit is checked and, if it is not HIGH, it becomes a framing error and the error interrupt factor flag ISER is set to

RXEN ← 1

Error generated ?

Receiving interrupt ?

Yes Received data reading from TRXD0–TRXD7

RXTRG ← 1

Yes

Error processing

"1". When interrupt has been enabled, an error interrupt is generated at this point. When receiving is completed, data in the shift register is transferred to the

Receiving complete ?

Yes

receive data buffer and the receiving complete interrupt flag ISRC is set to

RXEN ← 0

"1". When interrupt has been enabled, a receiving complete interrupt is generated at this point. (When an overrun error is generated, the interrupt factor flag ISRC is not set to "1" and a receiv-

Fig. 4.11.7.3 Receiving procedure in asynchronous mode

End

ing complete interrupt is not generated.) If "with parity check" has been selected, a parity check is executed when data is transferred into the receive data buffer from the shift register and if a parity error is detected, the error interrupt factor flag is set to "1". When the interrupt has been enabled, an error interrupt is generated at this point just as in the framing error mentioned above.

(4)

Read the received data from TRXD0–TRXD7 using receiving complete interrupt.

(5)

Write "1" to the receive control bit RXTRG to inform that the receive data has been read out. When the following data is received prior to writing "1" to RXTRG, it is recognized as an overrun error and the error interrupt factor flag is set to "1". When the interrupt has been enabled, an error interrupt is generated at this point just as in the framing error and parity error mentioned above.

(6)

Repeat steps (3) to (5) for the number of bytes of receiving data, and then set the receive disable status by writing "0" to the receive enable register RXEN, when the receiving is completed.

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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface)

Receive error

During receiving the following three types of errors can be detected by an interrupt.

(1) Parity error

When writing "1" to the EPR register to select "with parity check", a parity check (vertical parity check) is executed during receiving. After each data bit is sent a parity check bit is sent. The parity check bit is a "0" or a "1". Even parity checking will cause the sum of the parity bit and the other bits to be even. Odd parity causes the sum to be odd. This is checked on the receiving side. The parity check is performed when data received in the shift register is transferred to the receive data buffer. It checks whether the parity check bit is a "1" or a "0" (the sum of the bits including the parity bit) and the parity set in the PMD register match. When it does not match, it is recognized as an parity error and the parity error flag PER and the error interrupt factor flag ISER is set to "1". When interrupt has been enabled, an error interrupt is generated at this point. The PER flag is reset to "0" by writing "1". Even when this error has been generated, the received data corresponding to the error is transferred in the receive data buffer and the receive operation also continues. The received data at this point cannot assured because of the parity error.

(2) Framing error

In asynchronous transfer, synchronization is adopted for each character at the start bit ("0") and the stop bit ("1"). When receiving has been done with the stop bit set at "0", the serial interface judges the synchronization to be off and a framing error is generated. When this error is generated, the framing error flag FER and the error interrupt factor flag ISER are set to "1". When interrupt has been enabled, an error interrupt is generated at this point. The FER flag is reset to "0" by writing "1". Even when this error has been generated, the received data for it is loaded into the receive data buffer and the receive operation also continues. However, even when it does not become a framing error with the following data receipt, such data cannot be assured. Even when this error has been generated, the received data corresponding to the error is transferred in the receive data buffer and the receive operation also continues. However, even when it does not become a framing error with the following data receiving, such data cannot be assured.

(3) Overrun error

When the next data is received before "1" is written to RXTRG, an overrun error will be generated, because the previous receive data will be overwritten. When this error is generated, the overrun error flag OER and the error interrupt factor flag ISER are set to "1". When interrupt has been enabled, an error interrupt is generated at this point. The OER flag is reset to "0" by writing "1" into it. Even when this error has been generated, the received data corresponding to the error is transferred in the receive data buffer and the receive operation also continues. Furthermore, when the timing for writing "1" to RXTRG and the timing for the received data transfer to the receive data buffer overlap, it will be recognized as an overrun error.

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Timing chart

Figure 4.11.7.4 show the asynchronous transfer timing chart.

TXEN

TXTRG(RD)

TXTRG(WR) Sumpling

clock

SOUT (In 8-bit mode/Non parity) Interrupt

D0 D1 D2 D3 D4 D5 D6 D7

(a) Transmit timing

RXEN

RXTRG(RD)

RXTRG(WR)

Sumpling clock

SIN (In 8-bit mode/Non parity) TRXD

D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7D2 D3 D4 D5

1st data 2st data

OER control signal

OER

Interrupt

(b) Receive timing

Fig. 4.11.7.4 Timing chart (asynchronous transfer)

4.11.8 Interrupt function

This serial interface includes a function that generates the below indicated three types of interrupts.

• Transmitting complete interrupt

• Receiving complete interrupt

• Error interrupt

The interrupt factor flag ISxx and the interrupt mask register EISxx for the respective interrupt factors are provided and then the interrupt can be disabled/enabled by the software. Figure 4.11.8.1 shows the configuration of the serial interface interrupt circuit.

90 EPSON S1C63558 TECHNICAL MANUAL

Epson S1C63558 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

1.1 Features

1.2 Block Diagram

1.3 Pin Layout Diagram

1.4 Pin Description

1.5 Mask Option

2.1 P ower Supply

2.1.1 V oltage <VD1> for oscillation circuit and internal circuits

2.1.2 V oltage <VC1–VC5> for LCD driving

2.2 Initial Reset

2.2.1 Reset terminal (RESET)

2.2.2 Simultaneous low input to terminals K00–K03

2.2.3 Internal register at initial resetting

2.2.4 Terminal settings at initial resetting

2.3 Test Terminal (TEST)

CHAPTER 3 CPU, R OM, RAM

3.1 CPU

3.2 Code ROM

3.3 RAM

3.4 Data ROM

4.1 Memory Map

4.2 Watchdog Timer

4.2.1 Configuration of watchdog timer

4.2.2 Interrupt function

4.2.3 I/O memory of watchdog timer

4.2.4 Programming notes

4.3 Oscillation Circuit

4.3.1 Configuration of oscillation circuit

4.3.2 OSC1 oscillation circuit

4.3.3 OSC3 oscillation circuit

4.3.4 Switching the CPU operating clock

4.3.5 Clock frequency and instruction execution time

4.3.6 I/O memory of oscillation circuit

4.3.7 Programming notes

4.4 Input Ports (K00–K03 and K10–K13)

4.4.1 Configuration of input ports

4.4.2 Interrupt function

4.4.3 Mask option

4.4.4 I/O memory of input ports

4.4.5 Programming notes

4.5 Output Ports (R00–R03, R10–R13 and R20–R23)

4.5.1 Configuration of output ports

4.5.2 Mask option

4.5.3 High impedance control

4.5.4 Special output

4.5.5 I/O memory of output ports

4.5.6 Programming notes

4.6 I/O Ports (P00–P03, P10–P13, P20–P23 and P30–P33)

4.6.1 Configuration of I/O ports

4.6.2 Mask option

4.6.3 I/O control registers and input/output mode

4.6.4 Pull-up during input mode

4.6.5 Special outputs (CL, FR)

4.6.6 I/O memory of I/O ports

4.6.7 Programming notes

4.7 LCD Driver (COM0–COM16, SEG0–SEG39)

4.7.1 Configuration of LCD driver

4.7.2 Mask option

4.7.3 Power supply for LCD driving

4.7.4 LCD display control (ON/OFF) and switching of duty

4.7.5 Display memory

4.7.6 LCD contrast adjustment

4.7.7 I/O memory of LCD driver

4.7.8 Programming notes

4.8 Clock Timer

4.8.1 Configuration of clock timer

4.8.2 Data reading and hold function

4.8.3 Interrupt function

4.8.4 I/O memory of clock timer

4.8.5 Programming notes

4.9 Stopwatch Timer

4.9.1 Configuration of stopwatch timer

4.9.2 Count-up pattern

4.9.3 Interrupt function

4.9.4 I/O memory of stopwatch timer

4.9.5 Programming notes

4.10 Programmable Timer