Epson S1C33210 User Manual

MF1517-01

CMOS 32-BIT SINGLE CHIP MICROCOMPUTER

S1C33210

Technical Manual

S1C33210 PRODUCT PART S1C33210 FUNCTION PART

NOTICE

No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no representation that this material is applicable to products requiring high level reliability, such as medical products. Moreover, no license to any intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright infringement of a third party. This material or portions thereof may contain technology or the subject relating to strategic products under the control of the Foreign Exchange and Foreign Trade Law of Japan and may require an export license from the Ministry of International Trade and Industry or other approval from another government agency.

S1C33210 Technical Manual

This manual describes the hardware specifications of the Seiko Epson original 32-bit microcomputer S1C33210.

S1C33210 PRODUCT PART

Describes the hardware specifications of the S1C33210 except for details of the peripheral circuits.

S1C33210 FUNCTION PART

Describes details of all the peripheral circuit blocks for the S1C33 Family microcomputers.

R e f e r t o t he " S 1C 33 000 C or e C P U M a nua l " f or de t a i l s of t he S 1C 330 00 32- bi t R I S C C P U .

New configuration of product number

Starting April 1, 2001, the configuration of product number descriptions will be changed as listed below. To order from April 1, 2001 please use these product numbers. For further information, please contact Epson sales representative.

Devices

S1

C 33104 F 0A01

Development tools

S5U1

C 33L01 D1 1

00

Packing specification Specification Package (D: die form; F: QFP) Model number Model name (C: microcomputer, digital products) Product classification (S1: semiconductor)

00

Packing specification Version (1: Version 1) Tool type (D1: Development Tool) Corresponding model number (33L01: for S1C33L01) Tool classification (C: microcomputer use) Product classification (S5U1: development tool for semiconductor products)

The S1C33210 is a Seiko Epson original 32-bit microcomputer. It features high speed, low power consumption, and low-voltage operation, and is ideal for portable products that require high-speed data processing. The S1C33210 consists of an S1C33000 32-bit RISC type CPU as its core, peripheral circuits including a bus control unit, DMA controller, interrupt controller, timers, serial interface, and A/D converter, and also mobile access interface and RAM. A high-speed oscillation circuit and PLL, and a low-speed clock input circuit, are also included, supporting advanced operation, power-saving operation, and high-speed realtime clock functions. Use of the internal MAC (multiplication and accumulation) function in combination with the A/D converter also facilitates the design of systems requiring DSP functions, such as speech recognition and synthesis applications.

Table 1.1 shows the various models. The package and data bus interface vary according to the model.

Table 1.1 Model Lineup

Package Internal RAM Internal ROM Data bus I/F

QFP15-128pin 8K bytes None CMOS/LVTTL

Notes: • The end of the S1C33210 subcode is not related to model identification.

1.1 Features

Core CPU

Seiko Epson original 32-bit RISC CPU S1C33000 built-in

• Basic instruction set: 105 instructions (16-bit fixed size)

• Sixteen 32-bit general-purpose register

• 32-bit ALU and 8-bit shifter

• Multiplication/division instructions and MAC (multiplication and accumulation) instruction are available

• 20.0 ns of minimum instruction execution time at 50 MHz operation

Internal memory

ROM: None RAM: 8K bytes

Internal peripheral circuits

Oscillation circuit: High-speed (OSC3) oscillation circuit 33 MHz max.

Crystal/ceramic oscillator or external clock input

Low-speed (OSC1) oscillation circuit 32.768 kHz typ.

Crystal oscillator or external clock input

Timers: 8-bit timer 6 channels

16-bit timer 6 channels Watchdog timer (16-bit timer 0's function) Clock timer 1 channel (with alarm function)

Serial interface: 4 channels (clock-synchronous system, asynchronous system and IrDA

interface are selectable. Interfaces 1 and 3 support only asynchronous operation.)

A/D converter: 10 bits × 4 channels DMA controller: High-speed DMA 4 channels (Only two channels support external

requests.)

Intelligent DMA 128 channels

Interrupt controller: Possible to invoke DMA

Input interrupt 10 types (programmable) DMA controller interrupt 5 types 16-bit programmable timer interrupt 12 types 8-bit programmable timer interrupt 4 types Serial interface interrupt 6 types A/D converter interrupt 1 type Clock timer interrupt 1 type

S1C33210 PRODUCT PART EPSON A-1

1 OUTLINE

General-purpose input Shared with the I/O pins for internal peripheral circuits and output ports: Input port 7 bits

I/O port 27 bits

Mobile access interfaces One PHS, PDC, and HDLC channel each

External bus interface

BCU (bus control unit) built-in

• 24-bit address bus (internal 28-bit processing)

• 16-bit data bus Data size is selectable from 8 bits and 16 bits in each area.

• Little-endian memory access; big-endian may be set in each area.

• Memory mapped I/O

• Chip enable and wait control circuits built-in

• DRAM direct interface function built-in Supports fast page mode and EDO page mode. Supports self-refresh and CAS-before RAS refresh.

• Supports burst ROM.

Operating conditions and power consumption

Operating voltage: VDD 2.7 V to 3.6 V Operating clock frequency: CPU

50 MHz max. 25 MHz max. (Mobile access interfaces)

Operating temperature: -40 to 85°C Power consumption: During SLEEP 4 µW typ.

During HALT 122 mW typ.

(3.3 V, 50 MHz)

During execution 238 mW typ.

(3.3 V, 50 MHz)

Supply form

QFP15-128 pin plastic package.

Note: • The values of power consumption during execution were measured when a test

program that consisted of 55% load instructions, 23% arithmetic operation instructions, 1% mac instruction, 12% branch instructions and 9% ext instruction was being continuously executed.

A-2 EPSON S1C33210 PRODUCT PART

1.2 Block Diagram

VDD VSS

1 OUTLINE

S1C33210

A[23:0] D[15:0]

#WRL/#WR/#WE

#CE10EX #CE[9:4]

#DMAREQx(K50, K51)

#DMAACKx(P32, P33)

#DMAENDx(P15, P16)

#RD

#WRH/#BSH

#HCAS

#LCAS

#WAIT(P30)

#DRD(P20)

#DWE(P21)

#GAAS(P21)

#GARD(P31)

OSC3 OSC4

PLLS[1:0]

PLLC

OSC1 OSC2

FOSC1(P14)

OSC3/PLL

Prescaler

OSC1

Clock Timer

Intelligent

DMA (128 ch.)

High-speed DMA (4 ch.)

RAM

8KB

S1C33000

CPU Core

Bus Control Unit

Interrupt

Controller

16-bit

Programmable

Timer (6 ch.)

8-bit

Programmable

Timer (6 ch.)

Serial Interface

(4 ch.)

A/D Converter

(4 ch.)

Input Port

I/O Port

Mobile Access

Interface

#RESET #NMI #X2SPD TST DSIO EA10MD[1:0] BCLK #BUSREQ(P34) #BUSACK(P35) #BUSGET(P31) DST[2:0](P10–12) DPCO(P13) DCLK(P14)

EXCLx(P10–13, P15, P16) TMx(P22–27)

T8UFx(P10–13)

SINx(P00, P04, P27, RXD) SOUTx(P01, P05, P26, TXD) #SCLKx(P02, P25) #SRDYx(P03, P24)

AD0–3(K60–63) #ADTRG(K52)

DD

AV

K50–52 K60–63

P00–05 P10–16 P20–27 P30–35

DTR RTS TXD RI CTS DCD DSR RXD CNT1 CNT2 MSEL GOUT

Figure 1.2.1 S1C33210 Block Diagram

S1C33210 PRODUCT PART EPSON A-3

1 OUTLINE

1.3 Pin Description

1.3.1 Pin Layout Diagram (plastic package)

QFP15-128pin

6596

No.

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

Pin name

P26/TM4/SOUT2 P27/TM5/SIN2

SS

V BCLK P00/SIN0 P01/SOUT0 D15

DD

V P03/#SRDY0 D14 P31/#BUSGET/#GARD D13 P32/#DMAACK0 D12 P33/#DMAACK1 D11 P02/#SCLK0 D10 K50/#DMAREQ0 #WRL/#WR/#WE #WRH/#BSH VSS K51/#DMAREQ1 #RD D9 D8

DD

V K63/AD3 K62/AD2 AVDD K61/AD1 K60/AD0

97

INDEX

128

No.

33

K52/#ADTRG

34

#CE10EX/#CE9&10EX

35

#CE4/#CE11/#CE11&12

36

D7

37

D6

38

D5

39

V D4

40

D3

41

D2

42

#RESET

43

#NMI

44

D1

45

D0

46

V

47

#CE9/#CE17/#CE17&18

48

#CE7/#RAS0/#CE13/#RAS2

49

OSC2

50

OSC1

51

#CE6/#CE7&8

52

#CE8/#RAS1/#CE14/#RAS3

53

V

54

A0/#BSL

55

A1

56

A2

57

A3

58

P35/#BUSACK

59

#HCAS

60

#LCAS

61

P34/#BUSREQ/#CE6

62

A4

63

A5

64

Pin name

SS

DD

SS

No.

65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96

Pin name

A6 A7

SS

V P30/#WAIT/#CE4&5 A8 A9 #CE5/#CE15/#CE15&16 A10 A20

DD

V A11 A21 P16/EXCL5/#DMAEND1 A12 A22 TST A13 A23 P04/SIN1 A14 A15 P05/SOUT1 A16 A17 A18

SS

V A19 P20/#DRD

DD

V RTS DTR DSR

Figure 1.3.1 Pin Layout Diagram (QFP15-128pin)

64

33

321

No.

97 98

99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128

Pin name

RI CNT2 CNT1 TXD/SOUT3 CTS

SS

V PLLC V

SS

PLLS1 PLLS0 RXD/SIN3 DCD MSEL GOUT

DD

V OSC3 OSC4 EA10MD0 EA10MD1 #X2SPD P21/#DWE/#GAAS P22/TM0 P23/TM1 DSIO P10/EXCL0/T8UF0/DST0 P11/EXCL1/T8UF1/DST1 P12/EXCL2/T8UF2/DST2 P13/EXCL3/T8UF3/DPC0 P14/FOSC1/DCLK P24/TM2/#SRDY2 P25/TM3/#SCLK2 P15/EXCL4/#DMAEND0

A-4 EPSON S1C33210 PRODUCT PART

1.3.2 Pin Functions

Table 1.3.1 List of Pins for Power Supply System

Pin name Pin No. I/O Pull-up Function

QFP15-128

VDD 8, 27, 47, 74, 93, 111 ––Power supply (+) VSS 3, 22, 39, 54, 67, 90,

102, 104

AVDD 30 ––Analog system power supply (+); AVDD = VDD

Table 1.3.2 List of Pins for External Bus Interface Signals

Pin name Pin No. I/O Pull-up Function

QFP15-128

A0 #BSL

A[23:1] 56-58, 63-66, 69, 70, 72,

75, 78, 81, 84, 85, 87-89,

D[15:0] 7, 10, 12, 14, 16, 18, 25, 26,

#CE10EX #CE9&10EX

#CE9 #CE17

#CE17&18

#CE8 #RAS1 #CE14 #RAS3

#CE7 #RAS0 #CE13 #RAS2

#CE6 #CE7&8

#CE5 #CE15 #CE15&16

55 O – A0: Address bus (A0) when SBUSST(D3/0x4812E) = "0" (default)

91, 73, 76, 79, 82

36-38, 40-42, 45, 46

34 O – Area 10 chip enable for external memory

48 O – #CE9: Area 9 chip enable when CEFUNC[1:0](D[A:9])/0x48130) = "00"

53 O – #CE8: Area 8 chip enable when CEFUNC[1:0](D[A:9])/0x48130) = "00"

49 O – #CE7: Area 7 chip enable when CEFUNC[1:0](D[A:9])/0x48130) = "00"

52 O – Area 6 chip enable

71 O – #CE5: Area 5 chip enable when CEFUNC[1:0](D[A:9])/0x48130) = "00"

– (104

O – Address bus (A1 to A23)

I/O – Data bus (D0 to D15)

Power supply (-); GND

Pull-

down)

#BSL: Bus strobe (low byte) signal when SBUSST(D3/0x4812E) = "1"

* When CEFUNC[1:0] = "1x", this pin outputs #CE9+#CE10EX signal.

(default) #CE17: Area 17 chip enable when CEFUNC[1:0](D[A:9])/0x48130) = "01" * When CEFUNC[1:0] = "1x", this pin outputs #CE17+#CE18 signal.

and A8DRA(D8/0x48128) = "0" (default) #RAS1: Area 8 DRAM row strobe when CEFUNC[1:0](D[A:9])/0x48130) =

"00" and A8DRA(D8/0x48128) = "1" #CE14: Area 14 chip enable when CEFUNC[1:0](D[A:9])/0x48130) = "01"

or "1x" and A14DRA(D8/0x48122) = "0" #RAS3: Area 14 DRAM row strobe when CEFUNC[1:0](D[A:9])/0x48130)

= "01"or "1x" and A14DRA(D8/0x48122) = "1"

and A7DRA(D7/0x48128) = "0" (default) #RAS0: Area 7 DRAM row strobe when CEFUNC[1:0](D[A:9])/0x48130) =

"00" and A7DRA(D7/0x48128) = "1" #CE13: Area 13 chip enable when CEFUNC[1:0](D[A:9])/0x48130) = "01"

or "1x" and A13DRA(D7/0x48122) = "0" #RAS2: Area 13 DRAM row strobe when CEFUNC[1:0](D[A:9])/0x48130)

= "01" or "1x" and A13DRA(D7/0x48122) = "1"

* When CEFUNC[1:0] = "1x", this pin outputs #CE7+#CE8 signal.

(default) #CE15: Area 15 chip enable when CEFUNC[1:0](D[A:9])/0x48130) = "01" * When CEFUNC[1:0] = "1x", this pin outputs #CE15+#CE16 signal.

1 OUTLINE

S1C33210 PRODUCT PART EPSON A-5

1 OUTLINE

Pin name Pin No. I/O Pull-up Function

QFP15-128

#CE4 #CE11 #CE11&12

#RD 24 O – Read signal #WRL

#WR #WE

#WRH #BSH

#HCAS 60 O – #HCAS: DRAM column address strobe (high byte) signal #LCAS 61 O – #LCAS: DRAM column address strobe (low byte) signal BCLK 4 O – Bus clock output P34

#BUSREQ #CE6

P35 #BUSACK

P30 #WAIT #CE4&5

P20 #DRD

P21 #DWE #GAAS

P31 #BUSGET #GARD

EA10MD1 115 I Pull-up Area 10 boot mode selection

EA10MD0 114 I – 10–

35 O – #CE4: Area 4 chip enable when CEFUNC[1:0](D[A:9])/0x48130) = "00"

(default) #CE11: Area 11 chip enable when CEFUNC[1:0](D[A:9])/0x48130) = "01" * When CEFUNC[1:0] = "1x", this pin outputs #CE11+#CE12 signal.

20 O – #WRL: Write (low byte) signal when SBUSST(D3/0x4812E) = "0" (default)

#WR: Write signal when SBUSST(D3/0x4812E) = "1" #WE: DRAM write signal

21 O – #WRH: Write (high byte) signal when SBUSST(D3/0x4812E) = "0"

(default) #BSH: Bus strobe (high byte) signal when SBUSST(D3/0x4812E) = "1"

62 I/O – P34: I/O port when CFP34(D4/0x402DC) = "0" (default)

#BUSREQ: Bus release request input when CFP34(D4/0x402DC) = "1" #CE6: Area 6 chip enable when CFP34(D4/0x402DC) = "1" and

IOC34(D4/0x402DE) = "1"

59 I/O – P35: I/O port when CFP35(D5/0x402DC) = "0" (default)

#BUSACK: Bus acknowledge output when CFP35(D5/0x402DC) = "1"

68 I/O – P30: I/O port when CFP30(D0/0x402DC) = "0" (default)

#WAIT: Wait cycle request input when CFP30(D0/0x402DC) = "1" #CE4&5: Areas 4&5 chip enable when CFP30(D0/0x402DC) = "1" and

IOC30(D0/0x402DE) = "1"

92 I/O – P20: I/O port when CFP20(D0/0x402D8) = "0" (default)

#DRD: DRAM read signal output for successive RAS mode when

CFP20(D0/0x402D8) = "1"

117 I/O – P21: I/O port when CFP21(D1/0x402D8) = "0" and

CFEX2(D2/0x402DF) = "0" (default) #DWE: DRAM read signal output for successive RAS mode when

CFP21(D1/0x402D8) = "1" and CFEX2(D2/0x402DF) = "0" #GAAS: Area address strobe for GA when CFEX2(D2/0x402DF) = "1"

11 I/O – P31: I/O port when CFP31(D1/0x402DC) = "0" and

CFEX3(D3/0x402DF) = "0" (default) #BUSGET: Bus status monitor signal output when CFP31(D1/0x402DC) = "1"

and CFEX3(D3/0x402DF) = "0" #GARD: Area read signal output for GA when CFEX3(D3/0x402DF) = "1"

EA10MD1 EA10MD0 Mode

1 1 External ROM mode

01– 00–

A-6 EPSON S1C33210 PRODUCT PART

Table 1.3.3 List of Pins for HSDMA Control Signals

Pin name Pin No. I/O Pull-up Function

QFP15-128

K50 #DMAREQ0

K51 #DMAREQ1

P32 #DMAACK0

P33 #DMAACK1

P04 SIN1

P15 EXCL4 #DMAEND0

P16 EXCL5 #DMAEND1

P05 SOUT1

19 I Pull-up K50: Input port when CFK50(D0/0x402C0) = "0" (default)

#DMAREQ0: HSDMA Ch. 0 request input when CFK50(D0/0x402C0) = "1"

23 I Pull-up K51: Input port when CFK51(D1/0x402C0) = "0" (default)

#DMAREQ1: HSDMA Ch. 1 request input when CFK51(D1/0x402C0) = "1"

13 I/O – P32: I/O port when CFP32(D2/0x402DC) = "0" (default)

#DMAACK0: HSDMA Ch. 0 acknowledge output when CFP32(D2/0x402DC)

= "1"

15 I/O – P33: I/O port when CFP33(D3/0x402DC) = "0" (default)

#DMAACK1: HSDMA Ch. 1 acknowledge output when CFP33(D3/0x402DC)

= "1"

83 I/O – P04: I/O port when CFP04(D4/0x402D0) = "0" and

CFEX4(D4/0x402DF) = "0" (default)

SIN1: S erial I/F Ch. 1 data input when CFP04(D4/0x402D0) = "1" and

CFEX4(D4/0x402DF) = "0"

128 I/O – P15: I/O port when CFP15(D5/0x402D4) = "0" (default)

EXCL4: 16-bit timer 4 event counter input when CFP15(D5/0x402D4) =

"1" and IOC15(D5/0x402D6) = "0"

#DMAEND0: HSDMA Ch. 0 end-of-transfer signal output when

CFP15(D5/0x402D4) = "1" and IOC15(D5/0x402D6) = "1"

77 I/O – P16: I/O port when CFP16(D6/0x402D4) = "0" (default)

EXCL5: 16-bit timer 5 event counter input when CFP16(D6/0x402D4) =

"1" and IOC16(D6/0x402D6) = "0"

#DMAEND1: HSDMA Ch. 1 end-of-transfer signal output when

CFP16(D6/0x402D4) = "1" and IOC16(D6/0x402D6) = "1"

86 I/O – P05: I/O port when CFP05(D5/0x402D0) = "0" and

CFEX5(D5/0x402DF) = "0" (default)

SOUT1: Serial I/F Ch. 1 data output when CFP05(D5/0x402D0) = "1" and

CFEX5(D5/0x402DF) = "0"

1 OUTLINE

S1C33210 PRODUCT PART EPSON A-7

1 OUTLINE

Table 1.3.4 List of Pins for Internal Peripheral Circuits

Pin name Pin No. I/O Pull-up Function

QFP15-128

K52 #ADTRG

K60 AD0

K61 AD1

K62 AD2

K63 AD3

P00 SIN0

P01 SOUT0

P02 #SCLK0

P03 #SRDY0

P04 SIN1

P05 SOUT1

P10 EXCL0 T8UF0 DST0

P11 EXCL1 T8UF1 DST1

P12 EXCL2 T8UF2 DST2

33 I Pull-up K52: Input port when CFK52(D2/0x402C0) = "0" (default)

#ADTRG: A/D converter trigger input when CFK52(D2/0x402C0) = "1"

32 I – K60: Input port when CFK60(D0/0x402C3) = "0" (default)

AD0: A/D converter Ch. 0 input when CFK60(D0/0x402C3) = "1"

31 I – K61: Input port when CFK61(D1/0x402C3) = "0" (default)

AD1: A/D converter Ch. 1 input when CFK61(D1/0x402C3) = "1"

29 I – K62: Input port when CFK62(D2/0x402C3) = "0" (default)

AD2: A/D converter Ch. 2 input when CFK62(D2/0x402C3) = "1"

28 I – K63: Input port when CFK63(D3/0x402C3) = "0" (default)

AD3: A/D converter Ch. 3 input when CFK63(D3/0x402C3) = "1"

5 I/O – P00: I/O port when CFP00(D0/0x402D0) = "0" (default)

SIN0: Serial I/F Ch. 0 data input when CFP00(D0/0x402D0) = "1"

6 I/O – P01: I/O port when CFP01(D1/0x402D0) = "0" (default)

SOUT0: Serial I/F Ch. 0 data output when CFP01(D1/0x402D0) = "1"

17 I/O – P02: I/O port when CFP02(D2/0x402D0) = "0" (default)

#SCLK0: Serial I/F Ch. 0 clock input/output when CFP02(D2/0x402D0) =

"1"

9 I/O – P03: I/O port when CFP03(D3/0x402D0) = "0" (default)

#SRDY0: Serial I/F Ch. 0 ready signal input/output when

CFP03(D3/0x402D0) = "1"

83 I/O – P04: I/O port when CFP04(D4/0x402D0) = "0" and

CFEX4(D4/0x402DF) = "0" (default)

SIN1: S erial I/F Ch. 1 data input when CFP04(D4/0x402D0) = "1" and

CFEX4(D4/0x402DF) = "0"

86 I/O – P05: I/O port when CFP05(D5/0x402D0) = "0" and

CFEX5(D5/0x402DF) = "0"(default)

SOUT1: Serial I/F Ch. 1 data output when CFP05(D5/0x402D0) = "1" and

CFEX5(D5/0x402DF) = "0"

121 I/O – P10: I/O port when CFP10(D0/0x402D4) = "0" and

CFEX1(D1/0x402DF) = "0"

EXCL0: 16-bit timer 0 event counter input when CFP10(D0/0x402D4) =

"1", IOC10(D0/0x402D6) = "0" and CFEX1(D1/0x402DF) = "0"

T8UF0: 8-bit timer 0 output when CFP10(D0/0x402D4) = "1",

IOC10(D0/0x402D6) = "1" and CFEX1(D1/0x402DF) = "0"

DST0: DST0 signal output when CFEX1(D1/0x402DF) = "1" (default)

122 I/O – P11: I/O port when CFP11(D1/0x402D4) = "0" and

CFEX1(D1/0x402DF) = "0"

EXCL1: 16-bit timer 1 event counter input when CFP11(D1/0x402D4) =

"1", IOC11(D1/0x402D6) = "0" and CFEX1(D1/0x402DF) = "0"

T8UF1: 8-bit timer 1 output when CFP11(D1/0x402D4) = "1",

IOC11(D1/0x402D6) = "1" and CFEX1(D1/0x402DF) = "0"

DST1: DST1 signal output when CFEX1(D1/0x402DF) = "1" (default)

123 I/O – P12: I/O port when CFP12(D2/0x402D4) = "0" and

CFEX0(D0/0x402DF) = "0"

EXCL2: 16-bit timer 2 event counter input when CFP12(D2/0x402D4) =

"1", IOC12(D2/0x402D6) = "0" and CFEX0(D0/0x402DF) = "0"

T8UF2: 8-bit timer 2 output when CFP12(D2/0x402D4) = "1",

IOC12(D2/0x402D6) = "1" and CFEX0(D0/0x402DF) = "0"

DST2: DST2 signal output when CFEX0(D0/0x402DF) = "1" (default)

A-8 EPSON S1C33210 PRODUCT PART

Pin name Pin No. I/O Pull-up Function

QFP15-128

P13 EXCL3 T8UF3 DPCO

P14 FOSC1 DCLK

P15 EXCL4 #DMAEND0

P16 EXCL5 #DMAEND1

P20 #DRD

P21 #DWE #GAAS

P22 TM0

P23 TM1

P24 TM2 #SRDY2

P25 TM3 #SCLK2

P26 TM4 SOUT2

P27 TM5 SIN2

124 I/O – P13: I/O port when CFP13(D3/0x402D4) = "0" and

CFEX1(D1/0x402DF) = "0"

EXCL3: 16-bit timer 3 event counter input when CFP13(D3/0x402D4) =

"1", IOC13(D3/0x402D6) = "0" and CFEX1(D1/0x402DF) = "0"

T8UF3: 8-bit timer 3 output when CFP13(D3/0x402D4) = "1",

IOC13(D3/0x402D6) = "1" and CFEX1(D1/0x402DF) = "0"

DPCO: DPCO signal output when CFEX1(D1/0x402DF) = "1" (default)

125 I/O – P14: I/O port when CFP14(D4/0x402D4) = "0" and

CFEX0(D0/0x402DF) = "0"

FOSC1: OSC1 clock output when CFP14(D4/0x402D4) = "1" and

CFEX0(D0/0x402DF) = "0"

DCLK: DCLK signal output when CFEX0(D0/0x402DF) = "1" (default)

128 I/O – P15: I/O port when CFP15(D5/0x402D4) = "0" (default)

EXCL4: 16-bit timer 4 event counter input when CFP15(D5/0x402D4) =

"1" and IOC15(D5/0x402D6) = "0"

#DMAEND0: HSDMA Ch. 0 end-of-transfer signal output when

CFP15(D5/0x402D4) = "1" and IOC15(D5/0x402D6) = "1"

77 I/O – P16: I/O port when CFP16(D6/0x402D4) = "0" (default)

EXCL5: 16-bit timer 5 event counter input when CFP16(D6/0x402D4) =

"1" and IOC16(D6/0x402D6) = "0"

#DMAEND1: HSDMA Ch. 1 end-of-transfer signal output when

CFP16(D6/0x402D4) = "1" and IOC16(D6/0x402D6) = "1"

92 I/O – P20: I/O port when CFP20(D0/0x402D8) = "0" (default)

#DRD: DRAM read signal output for successive RAS mode when

CFP20(D0/0x402D8) = "1"

117 I/O – P21: I/O port when CFP21(D1/0x402D8) = "0" and

CFEX2(D2/0x402DF) = "0" (default)

#DWE: DRAM read signal output for successive RAS mode when

CFP21(D1/0x402D8) = "1" and CFEX2(D2/0x402DF) = "0"

#GAAS: Area address strobe for GA when CFEX2(D2/0x402DF) = "1"

118 I/O – P22: I/O port when CFP22(D2/0x402D8) = "0" (default)

TM0: 16-bit timer 0 output when CFP22(D2/0x402D8) = "1"

119 I/O – P23: I/O port when CFP23(D3/0x402D8) = "0" (default)

TM1: 16-bit timer 1 output when CFP23(D3/0x402D8) = "1"

126 I/O – P24: I/O port when CFP24(D4/0x402D8) = "0" (default)

TM2: 16-bit timer 2 output when CFP24(D4/0x402D8) = "1" #SRDY2: Serial I/F Ch.2 ready signal input/output when

SSRDY2(D3/0x402DB) = "1" and CFP24 (D4/0x402D8) = "0"

127 I/O – P25: I/O port when CFP25(D5/0x402D8) = "0" (default)

TM3: 16-bit timer 3 output when CFP25(D5/0x402D8) = "1" #SCLK2: Serial I/F Ch.2 clock input/output when SSCLK2(D2/0x402DB) =

"1" and CFP25(D5/0x402D8) = "0"

1I/O– P26: I/O port when CFP26(D6/0x402D8) = "0" (default)

TM4: 16-bit timer 4 output when CFP26(D6/0x402D8) = "1" SOUT2: Serial I/F Ch.2 data output when SSOUT2(D1/0x402DB) = "1"

and CFP26(D6/0x402D8) = "0"

2I/O– P27: I/O port when CFP27(D7/0x402D8) = "0" (default)

TM5: 16-bit timer 5 output when CFP27(D7/0x402D8) = "1" SIN2: S erial I/F Ch.2 data input when SSIN2(D0/0x402DB) = "1" and

CFP27(D7/0x402D8) = "0"

1 OUTLINE

S1C33210 PRODUCT PART EPSON A-9

1 OUTLINE

Pin name Pin No. I/O Pull-up Function

QFP15-128

DTR 95 O – DTR output *1 RTS 94 O – RTS output*1 TXD

SOUT3 RI 97 I – RI input *1 CTS 101 I – CTS input *1 DCD 108 I – DCD input *1 DSR 96 I – DSR input *1 RXD

SIN3 CNT1 99 O – Mobile access control output #1 CNT2 98 O – Mobile access control output #2 MSEL 109 I Pull-up Serial I/O interface Ch. 3 configuration input. Normally drive this at High level. GOUT 110 O – NMI interrupt request output

100 O – TXD: TXD output*1 when MSEL pin input is at High level

SOUT3: SOUT3 output when MSEL pin input is at Low level

107 I – RXD: RXD input when MSEL pin input is at High level

SIN3: SIN3 input when MSEL pin input is at Low level

Note: *1 The communications macro select (MCRS) register (D[1:0]/0x200000) configures the I/O

signals to match the target mobile device.

Table 1.3.5 List of Pins for Clock Generator

Pin name Pin No. I/O Pull-up Function

QFP15-128

OSC1 51 I – Low-speed (OSC1) oscillation input (32 kHz crystal oscillator or external clock

input)

OSC2 50 O – Low-speed (OSC1) oscillation output OSC3 112 I – High-speed (OSC3) oscillation input (crystal/ceramic oscillator or external clock

input)

OSC4 113 O – High-speed (OSC3) oscillation output PLLS[1:0] 105,106 I – PLL set-up pins

PLLS1 PLLS0 fin (f OSC3) fout (fPSCIN)

1110–25MHz 20–50MHz 0110–12.5MHz 40–50MHz 0 0 PLL is not

used

L

PLLC 103 ––Capasitor connecting pin for PLL

Table 1.3.6 List of Other Pins

Pin name Pin No. I/O Pull-up Function

QFP15-128 /down

TST 80 I Pull-

DSIO 120 I/O Pull-up Serial I/O pin for debugging

#X2SPD 116 I – Clock doubling mode set-up pin1: CPU clock = bus clock × 1, 0: CPU clock = bus

#NMI 44 I Pull-up NMI request input pin #RESET 43 I Pull-up Initial reset input pin

Test mode input. This pin is used for testing this chip. For further details, refer

down

to the S1C33 ASIC Design Guide.

This pin is used to communicate with the debugging tool S5U1C33000H.

clock × 2

Note:"#" in the pin names indicates that the signal is low active.

A-10 EPSON S1C33210 PRODUCT PART

2 Power Supply

This chapter explains the operating voltage of the S1C33210.

2.1 Power Supply Pins

The S1C33210 has the power supply pins shown in Table 2.1.1.

Table 2.1.1 Power Supply Pins

Pin name Pin No. Function

QFP15-128

VDD 8, 27, 47, 74, 93, 111 Power supply (+) VSS 3, 22, 39, 54, 67, 90,

102, 104

AVDD 30 Analog system power supply (+); AVDD = VDD

Power supply (-); GND

2 POWER SUPPLY

2.7 to 3.6 V

GND

VDD

CPU core

I/O

interface circuit

AVDD

Analog circuits

(A/D converter)

VSS

Figure 2.1.1 Power Supply System

Internal

peripheral

circuit

I/O pins

2.2 Operating Voltage (VDD, VSS)

The core CPU, internal peripheral circuits, and external signal interfaces operate on the voltage difference between the V

DD and VSS pins. The following operating voltage can be used:

DD = 2.7 V to 3.6 V (VSS = GND)

V

Note: The S1C33210 has 6 V

pins. Do not open any of them.

The operating clock frequency range (OSC3) is 5 MHz to 50 MHz with this voltage.

DD pins and 8 VSS pins. Be sure to supply the operating voltage to all the

S1C33210 PRODUCT PART EPSON A-11

2 POWER SUPPLY

2.3 Power Supply for Analog Circuits (AVDD)

The analog power supply pin (AVDD) is provided separately from the V DD and VDD pins in order that the digital circuits do not affect the analog circuit (A/D converter). The AV the V

SS pin is used as the analog ground.

Supply the same voltage level as the V

DD = V DD, V SS = GND

AV

Note: Be sure to supply V

DD to the AVDD pin even if the analog circuit is not used.

DD to the AVDD pin.

Noise on the analog power lines decrease the A/D converting precision, so use a stabilized power supply and make the board pattern with consideration given to that.

DD pin is used to supply an analog power voltage and

A-12 EPSON S1C33210 PRODUCT PART

3 INTERNAL MEMORY

3 Internal Memory

This chapter explains the internal memory configuration.

Figure 3.1 shows the S1C33210 memory map.

Area Address

Areas 18–11

Area 10

Areas 9

Area 6

Area 5

Area 4 0x01FFFFF

Area 3

Area 2

Area 1

Area 0

–7

0xFFFFFFF 0x1000000

0x0FFFFFF 0x0C00000

0x0BFFFFF 0x0400000

0x03FFFFF 0x0380000

0x037FFFF 0x0300000

0x02FFFFF 0x0200000

0x0100000 0x00FFFFF

0x0080000 0x007FFFF

0x0060000 0x005FFFF

0x0050000 0x004FFFF

0x0040000 0x003FFFF

0x0030000 0x002FFFF

0x0002000 0x0001FFF

0x0000000

Figure 3.1 Memory Map

Area 2 is used in debug mode only and it cannot be accessed in user mode (normal program execution status).

S1C33210

External Memory

External I/O (16-bit device)

External I/O (8-bit device)

Internal peripheral circuits

External Memory

(Reserved)

For middleware use

(Reserved)

For CPU, debug mode

(Mirror of internal

peripheral circuits)

Internal peripheral circuits

(Mirror of internal

peripheral circuits)

(Mirror of internal RAM)

Internal RAM (8KB)

3.1 ROM and Boot Address

The S1C33210 does not have a built-in ROM. The boot address is fixed at 0x0C00000, and so external ROM/Flash should be used in Area 10.

For setting up Area 10, refer to the "BCU (Bus Controller Unit)" in "S1C33210 FUNCTION PART" in this manual.

3.2 RAM

The S1C33210 has a built-in 8KB RAM. The RAM is allocated to Area 0, address 0x0000000 to address 0x0001FFF. The internal RAM is a 32-bit sized device and data can be read/written in 1 cycle regardless of data size (byte, halfword or word).

S1C33210 PRODUCT PART EPSON A-13

4 PERIPHERAL CIRCUITS

4 Peripheral Circuits

This chapter lists the built-in peripheral circuits and the I/O memory map. For details of the circuits, refer to the

"S1C33210 FUNCTION PART".

4.1 List of Peripheral Circuits

The S1C33210 consists of the C33 Core Block, C33 Peripheral Block, C33 DMA Block and C33 Analog Block.

C33 Core Block

CPU S1C33000 32-bit RISC type CPU BCU (Bus Control Unit) 24-bit external address bus and 16-bit data bus

All the BCU functions can be used. ITC (Interrupt Controller) 39 types of interrupts are available. CLG (Clock Generator) OSC3 oscillation circuit (33 MHz Max.), PLL and OSC1 oscillation circuit

(32.768 kHz Typ.) built-in DBG (Debug Unit) Functional block for debugging with the S5U1C33000H (In-Circuit Debugger

for S1C33 Family)

C33 Peripheral Block

Prescaler Programmable clock generator for peripheral circuits 8-bit programmable timer 6 channels with clock output function 16-bit programmable timer 6 channels with event counter, clock output and watchdog timer functions Serial interface 4 channels (asynchronous mode, clock synchronous mode and IrDA are

selectable. Interfaces 1 and 3 support only asynchronous operation.) Input and I/O ports 7 bits of input ports and 27 bits of I/O ports (used for peripheral I/O) Clock timer 1 channel with alarm function Mobile access interfaces One PHS, PDC, and HDLC interface each

C33 DMA Block

HSDMA (High-Speed DMA) 4 channels (Only two interfaces support external requests.) IDMA (Intelligent DMA) 128 channels

C33 Analog Block

A/D converter 10-bit A/D converter with 4 input channels

A-14 EPSON S1C33210 PRODUCT PART

4.2 I/O Memory Map

NameAddressRegister name Bit Function Setting Init. R/W Remarks

–

8-bit timer 4/5 clock select register

8-bit timer 4/5 clock control register

8-bit timer clock select register

16-bit timer 0 clock control register

16-bit timer 1 clock control register

16-bit timer 2 clock control register

0040140

0040145

0040146

0040147

0040148

0040149

(B)

D7–2

D1 D0

D7 D6 D5 D4

D3 D2 D1 D0

D7–4

D3 D2 D1 D0

D7–4

D3 D2 D1 D0

D7–4

D3 D2 D1 D0

D7–4

D3 D2 D1 D0

P8TPCK5 P8TPCK4

P8TS52 P8TS51 P8TS50

P8TON4 P8TS42 P8TS41 P8TS40

P8TPCK3 P8TPCK2 P8TPCK1 P8TPCK0

P16TON0 P16TS02 P16TS01 P16TS00

P16TON1 P16TS12 P16TS11 P16TS10

P16TON2 P16TS22 P16TS21 P16TS20

Table 4.2.1 I/O Memory Map

reserved 8-bit timer 5 clock selection 8-bit timer 4 clock selection

8-bit timer 5 clock control 8-bit timer 5 clock division ratio selection

8-bit timer 4 clock control 8-bit timer 4 clock division ratio selection

reserved 8-bit timer 3 clock selection 8-bit timer 2 clock selection 8-bit timer 1 clock selection 8-bit timer 0 clock selection

reserved 16-bit timer 0 clock control 16-bit timer 0 clock division ratio selection

reserved 16-bit timer 1 clock control 16-bit timer 1 clock division ratio selection

reserved 16-bit timer 2 clock control 16-bit timer 2 clock division ratio selection

1 θ/1 0 Divided clk. 1 θ/1 0 Divided clk.

1 On 0 OffP8TON5

1 1 1 1 0 0 0 0

1 On 0 Off

1 1 1 1 0 0 0 0

1 θ/1 0 Divided clk. 1 θ/1 0 Divided clk. 1 θ/1 0 Divided clk. 1 θ/1 0 Divided clk.

1 On 0 Off

P16TS0[2:0] Division ratio

1 1 1 1 0 0 0 0

1 On 0 Off

P16TS1[2:0] Division ratio

1 1 1 1 0 0 0 0

1 On 0 Off

P16TS2[2:0] Division ratio

1 1 1 1 0 0 0 0

–

1

1 1 0 0 1 1 0 0

θ/256

0

θ/128

1

θ/64

0

θ/32

1

θ/16

0

θ/8

1

θ/4

0

θ/2

1

θ/4096

0

θ/2048

1

θ/64

0

θ/32

1

θ/16

0

θ/8

1

θ/4

0

θ/2

––

1

θ/4096

0

θ/1024

1

θ/256

0

θ/64

1

θ/16

0

θ/4

1

θ/2

0

θ/1

––

1

θ/4096

0

θ/1024

1

θ/256

0

θ/64

1

θ/16

0

θ/4

1

θ/2

0

θ/1

––

1

θ/4096

0

θ/1024

1

θ/256

0

θ/64

1

θ/16

0

θ/4

1

θ/2

0

θ/1

4 PERIPHERAL CIRCUITS

–

0 when being read.

0

R/W

θ: selected by

0

R/W

Prescaler clock select register (0x40181)

0

R/W

θ: selected by

0

R/W

Prescaler clock select

0

R/W

register (0x40181)

0

R/W

8-bit timer 5 can generate the clock for the serial I/F Ch.3.

0

R/W

θ: selected by

0

R/W

Prescaler clock select

0

R/W

register (0x40181)

0

R/W

8-bit timer 4 can generate the clock for the serial I/F Ch.2.

–

0 when being read.

0

R/W

θ: selected by

0

R/W

Prescaler clock select

0

R/W

register (0x40181)

0

R/W

–

0 when being read.

0

R/W

θ: selected by

0

R/W

Prescaler clock select

0

register (0x40181)

0

16-bit timer 0 can be used as a watchdog timer.

–

0 when being read.

0

R/W

θ: selected by

0

R/W

Prescaler clock select

0

register (0x40181)

0

–

0 when being read.

0

R/W

θ: selected by

0

R/W

Prescaler clock select

0

register (0x40181)

0

(B) in [Address] indicates an 8-bit register and (HW) indicates a 16-bit register. The meaning of the symbols described in [Init.] are listed below:

0, 1: Initial values that are set at initial reset.

(However, the registers for the bus and input/output ports are not initialized at hot start.) X: Not initialized at initial reset. –: Not set in the circuit.

S1C33210 PRODUCT PART EPSON A-15

4 PERIPHERAL CIRCUITS

16-bit timer 3 clock control register

16-bit timer 4 clock control register

16-bit timer 5 clock control register

8-bit timer 0/1 clock control register

004014A

004014B

004014C

004014D

(B)

D7–4

D3 D2 D1 D0

D7–4

D3 D2 D1 D0

D7–4

D3 D2 D1 D0

D7 D6 D5 D4

D3 D2 D1 D0

NameAddressRegister name Bit Function Setting Init. R/W Remarks

P16TON3 P16TS32 P16TS31 P16TS30

P16TON4 P16TS42 P16TS41 P16TS40

P16TON5 P16TS52 P16TS51 P16TS50

P8TS12 P8TS11 P8TS10

P8TON0 P8TS02 P8TS01 P8TS00

reserved 16-bit timer 3 clock control 16-bit timer 3 clock division ratio selection

reserved 16-bit timer 4 clock control 16-bit timer 4 clock division ratio selection

reserved 16-bit timer 5 clock control 16-bit timer 5 clock division ratio selection

8-bit timer 1 clock control 8-bit timer 1 clock division ratio selection

8-bit timer 0 clock control 8-bit timer 0 clock division ratio selection

1 On 0 Off

P16TS3[2:0] Division ratio

1 1 1 1 0 0 0 0

1 On 0 Off

P16TS4[2:0] Division ratio

1 1 1 1 0 0 0 0

1 On 0 Off

P16TS5[2:0] Division ratio

1 1 1 1 0 0 0 0

1 On 0 OffP8TON1 P8TS1[2:0] Division ratio

1 1 1 1 0 0 0

0 1 On 0 Off P8TS0[2:0] Division ratio

1

0

––

1

1 1 0 0 1 1 0 0

θ/4096

0

θ/1024

1

θ/256

0

θ/64

1

θ/16

0

θ/4

1

θ/2

0

θ/1

––

1

θ/4096

0

θ/1024

1

θ/256

0

θ/64

1

θ/16

0

θ/4

1

θ/2

0

θ/1

––

1

θ/4096

0

θ/1024

1

θ/256

0

θ/64

1

θ/16

0

θ/4

1

θ/2

0

θ/1

1

θ/4096

0

θ/2048

1

θ/1024

0

θ/512

1

θ/256

0

θ/128

1

θ/64

0

θ/32

1

θ/256

0

θ/128

1

θ/64

0

θ/32

1

θ/16

0

θ/8

1

θ/4

0

θ/2

–

0

R/W

0

R/W 0 0

–

0

R/W 0

R/W 0 0

–

0

R/W 0

R/W 0 0

0

R/W 0

R/W 0 0

R/W

0

R/W

0 0 0

0 when being read.

θ: selected by Prescaler clock select register (0x40181)

0 when being read.

θ: selected by Prescaler clock select register (0x40181)

0 when being read.

θ: selected by Prescaler clock select register (0x40181)

8-bit timer 1 can generate the OSC3 oscillation-stabilize waiting period.

θ: selected by Prescaler clock select register (0x40181)

8-bit timer 0 can generate the DRAM refresh clock.

A-16 EPSON S1C33210 PRODUCT PART

8-bit timer 2/3 clock control register

A/D clock control register

Run/Stop register

Clock timer interrupt control register

Clock timer divider register

Clock timer second register

004014E

(B)

004014F

(B)

0040151

(B)

0040152

(B)

0040153

(B)

4 PERIPHERAL CIRCUITS

NameAddressRegister name Bit Function Setting Init. R/W Remarks

D7 D6 D5 D4

D3 D2 D1 D0

D7–4

D3 D2 D1 D0

D7–2

D1 D0

D7 D6 D5

D4 D3 D2

D1 D0

D7 D6 D5 D4 D3 D2 D1 D0

D7–6

D5 D4 D3 D2 D1 D0

P8TS32 P8TS31 P8TS30

P8TON2 P8TS22 P8TS21 P8TS20

–

PSONAD PSAD2 PSAD1 PSAD0

–

TCRST TCRUN

TCISE2 TCISE1 TCISE0

TCASE2 TCASE1 TCASE0

TCIF TCAF

TCD7 TCD6 TCD5 TCD4 TCD3 TCD2 TCD1 TCD0

–

TCMD5 TCMD4 TCMD3 TCMD2 TCMD1 TCMD0

8-bit timer 3 clock control 8-bit timer 3 clock division ratio selection

8-bit timer 2 clock control 8-bit timer 2 clock division ratio selection

reserved A/D converter clock control A/D converter clock division ratio selection

reserved Clock timer reset Clock timer Run/Stop control

Clock timer interrupt factor selection

Clock timer alarm factor selection

Interrupt factor generation flag Alarm factor generation flag

Clock timer data 1 Hz Clock timer data 2 Hz Clock timer data 4 Hz Clock timer data 8 Hz Clock timer data 16 Hz Clock timer data 32 Hz Clock timer data 64 Hz Clock timer data 128 Hz

reserved Clock timer second counter data TCMD5 = MSB TCMD0 = LSB

1 On 0 OffP8TON3 P8TS3[2:0] Division ratio

1

0

1

0

1

0

1

0

0 1 On 0 Off P8TS2[2:0] Division ratio

1

0

1

0

1

0

1

0

θ/256

0

θ/128

1

θ/64

0

θ/32

1

θ/16

0

θ/8

1

θ/4

0

θ/2

1

θ/4096

0

θ/2048

1

θ/64

0

θ/32

1

θ/16

0

θ/8

1

θ/4

0

θ/2

–

1 On 0 Off P8TS0[2:0] Division ratio

1

0

1

0

1

0

1

0

1 Reset 0 Invalid 1 Run 0 Stop

θ/256

0

θ/128

1

θ/64

0

θ/32

1

θ/16

0

θ/8

1

θ/4

0

θ/2

–Clock timer

TCISE[2:0] Interrupt factor

1

0

1

0

1

0

1

0

None

0

Day

1

Hour

0

Minute

1

1 Hz

0

2 Hz

1

8 Hz

0

32 Hz

TCASE[2:0] Alarm factor

1

X

X X 1 0

Day Hour Minute None Not generated Not generated

–

X

1

X

0

1 Generated 0 1 Generated 0

1 High 0 Low 1 High 0 Low 1 High 0 Low 1 High 0 Low 1 High 0 Low 1 High 0 Low 1 High 0 Low 1 High 0 Low

0 to 59 seconds

0 0 0 0

–

0 0 0 0

–

X X

X X X

X X

X X X X X X X X

–

X X X X X X

R/W

θ: selected by

R/W

Prescaler clock select register (0x40181)

8-bit timer 3 can generate the clock for the serial I/F Ch.1.

R/W R/W

θ: selected by Prescaler clock select register (0x40181)

8-bit timer 2 can generate the clock for the serial I/F Ch.0.

–

0 when being read.

R/W

θ: selected by

R/W

Prescaler clock select register (0x40181)

–

0 when being read.

W

0 when being read.

R/W

Reset by writing 1.

R/W

Reset by writing 1.

R R R R R R R R

–R0 when being read.0040154

S1C33210 PRODUCT PART EPSON A-17

4 PERIPHERAL CIRCUITS

Clock timer minute register

Clock timer hour register

Clock timer day (low-order) register

Clock timer day (highorder) register

minute comparison register

hour comparison register

day comparison register

0040158

004015B

(B)

D7–6

D5 D4 D3 D2 D1 D0

D7–5

D4 D3 D2 D1 D0

D7 D6 D5 D4 D3 D2 D1 D0

D7–6

D5 D4 D3 D2 D1 D0

D7–5

D4 D3 D2 D1 D0

D7–5

D4 D3 D2 D1 D0

NameAddressRegister name Bit Function Setting Init. R/W Remarks

–

TCHD5 TCHD4 TCHD3 TCHD2 TCHD1 TCHD0

–

TCDD4 TCDD3 TCDD2 TCDD1 TCDD0

TCND7 TCND6 TCND5 TCND4 TCND3 TCND2 TCND1 TCND0

TCND14 TCND13 TCND12 TCND11 TCND10 TCND9 TCND8

–

TCCH5 TCCH4 TCCH3 TCCH2 TCCH1 TCCH0

–

TCCD4 TCCD3 TCCD2 TCCD1 TCCD0

–

TCCN4 TCCN3 TCCN2 TCCN1 TCCN0

reserved Clock timer minute counter data TCHD5 = MSB TCHD0 = LSB

reserved Clock timer hour counter data TCDD4 = MSB TCDD0 = LSB

Clock timer day counter data (low-order 8 bits) TCND0 = LSB

Clock timer day counter data (high-order 8 bits) TCND15 = MSB

reserved Clock timer minute comparison data TCCH5 = MSB TCCH0 = LSB

reserved Clock timer hour comparison data TCCD4 = MSB TCCD0 = LSB

reserved Clock timer day comparison data TCCN4 = MSB TCCN0 = LSB

–

0 to 59 minutes

–

0 to 23 hours

0 to 65535 days

(low-order 8 bits)

0 to 65535 days

(high-order 8 bits)

–Clock timer

0 to 59 minutes

(Note) Can be set within 0–63.

–Clock timer

0 to 23 hours

(Note) Can be set within 0–31.

–Clock timer

0 to 31 days

–

X

R/W X X X X X

–

X

R/W X X X X

X

R/W0040157 X X X X X X X

X

R/WTCND15 X X X X X X X

–

X

R/W X X X X X

–

X

R/W X X X X

–

X

R/W X X X X

–

0 when being read.0040155

–

0 when being read.0040156

–

0 when being read.0040159

–

0 when being read.004015A

–

0 when being read. Compared with TCND[4:0].

A-18 EPSON S1C33210 PRODUCT PART

8-bit timer 0 control register

8-bit timer 0 reload data register

8-bit timer 0 counter data register

8-bit timer 1 control register

8-bit timer 1 reload data register

8-bit timer 1 counter data register

8-bit timer 2 control register

8-bit timer 2 reload data register

8-bit timer 2 counter data register

0040160

(B)

0040164

(B)

0040168

(B)

4 PERIPHERAL CIRCUITS

NameAddressRegister name Bit Function Setting Init. R/W Remarks

–

D7–3

D2 D1 D0

D7 D6 D5 D4 D3 D2 D1 D0

D7–3

D2 D1 D0

D7 D6 D5 D4 D3 D2 D1 D0

D7–3

D2 D1 D0

D7 D6 D5 D4 D3 D2 D1 D0

PTOUT0 PSET0 PTRUN0

RLD06 RLD05 RLD04 RLD03 RLD02 RLD01 RLD00

PTD06 PTD05 PTD04 PTD03 PTD02 PTD01 PTD00

–

PTOUT1 PSET1 PTRUN1

RLD16 RLD15 RLD14 RLD13 RLD12 RLD11 RLD10

PTD16 PTD15 PTD14 PTD13 PTD12 PTD11 PTD10

–

PTOUT2 PSET2 PTRUN2

RLD26 RLD25 RLD24 RLD23 RLD22 RLD21 RLD20

PTD26 PTD25 PTD24 PTD23 PTD22 PTD21 PTD20

reserved 8-bit timer 0 clock output control 8-bit timer 0 preset 8-bit timer 0 Run/Stop control

8-bit timer 0 reload data RLD07 = MSB RLD00 = LSB

8-bit timer 0 counter data PTD07 = MSB PTD00 = LSB

reserved 8-bit timer 1 clock output control 8-bit timer 1 preset 8-bit timer 1 Run/Stop control

8-bit timer 1 reload data RLD17 = MSB RLD10 = LSB

8-bit timer 1 counter data PTD17 = MSB PTD10 = LSB

reserved 8-bit timer 2 clock output control 8-bit timer 2 preset 8-bit timer 2 Run/Stop control

8-bit timer 2 reload data RLD27 = MSB RLD20 = LSB

8-bit timer 2 counter data PTD27 = MSB PTD20 = LSB

1 On 0 Off

–

1 Preset 0 Invalid 1 Run 0 Stop

0 to 255RLD07

0 to 255PTD07

–

1 On 0 Off 1 Preset 0 Invalid 1 Run 0 Stop

0 to 255RLD17

0 to 255PTD17

–

1 On 0 Off 1 Preset 0 Invalid 1 Run 0 Stop

0 to 255RLD27

0 to 255PTD27

–

0

–

0

X

–

0

–

0

X

–

0

–

0

X

–

0 when being read.

R/W

W

0 when being read.

R/W

R/W0040161

R0040162

–

0 when being read.

R/W

0 when being read.

W

R/W

R/W0040165

R0040166

–

0 when being read.

R/W

0 when being read.

W

R/W

R/W0040169

R004016A

S1C33210 PRODUCT PART EPSON A-19

4 PERIPHERAL CIRCUITS

8-bit timer 3 control register

8-bit timer 3 reload data register

8-bit timer 3 counter data register

8-bit timer 4 control register

8-bit timer 4 reload data register

8-bit timer 4 counter data register

8-bit timer 5 control register

8-bit timer 5 reload data register

8-bit timer 5 counter data register

004016C

0040174

0040178

(B)

D7–3

D2 D1 D0

D7 D6 D5 D4 D3 D2 D1 D0

D7–3

D2 D1 D0

D7 D6 D5 D4 D3 D2 D1 D0

D7–3

D2 D1 D0

D7 D6 D5 D4 D3 D2 D1 D0

NameAddressRegister name Bit Function Setting Init. R/W Remarks

–

PTOUT3 PSET3 PTRUN3

RLD36 RLD35 RLD34 RLD33 RLD32 RLD31 RLD30

PTD36 PTD35 PTD34 PTD33 PTD32 PTD31 PTD30

–

PTOUT4 PSET4 PTRUN4

RLD46 RLD45 RLD44 RLD43 RLD42 RLD41 RLD40

PTD46 PTD45 PTD44 PTD43 PTD42 PTD41 PTD40

–

PTOUT5 PSET5 PTRUN5

RLD56 RLD55 RLD54 RLD53 RLD52 RLD51 RLD50

PTD56 PTD55 PTD54 PTD53 PTD52 PTD51 PTD50

reserved 8-bit timer 3 clock output control 8-bit timer 3 preset 8-bit timer 3 Run/Stop control

8-bit timer 3 reload data RLD37 = MSB RLD30 = LSB

8-bit timer 3 counter data PTD37 = MSB PTD30 = LSB

reserved 8-bit timer 4 clock output control 8-bit timer 4 preset 8-bit timer 4 Run/Stop control

8-bit timer 4 reload data RLD47 = MSB RLD40 = LSB

8-bit timer 4 counter data PTD47 = MSB PTD40 = LSB

reserved 8-bit timer 5 clock output control 8-bit timer 5 preset 8-bit timer 5 Run/Stop control

8-bit timer 5 reload data RLD57 = MSB RLD50 = LSB

8-bit timer 5 counter data PTD57 = MSB PTD50 = LSB

1 On 0 Off

–

1 Preset 0 Invalid 1 Run 0 Stop

0 to 255RLD37

0 to 255PTD37

–

1 On 0 Off 1 Preset 0 Invalid 1 Run 0 Stop

0 to 255RLD47

0 to 255PTD47

–

1 On 0 Off 1 Preset 0 Invalid 1 Run 0 Stop

0 to 255RLD57

0 to 255PTD57

–

0

R/W

–

0

R/W

X

R/W004016D X X X X X X X

X X X X X X X X

–

0

R/W

–

0

R/W

X

R/W0040175 X X X X X X X

X X X X X X X X

–

0

R/W

–

0

R/W

X

R/W0040179 X X X X X X X

X X X X X X X X

–

0 when being read.

W

0 when being read.

R004016E

–

0 when being read.

W

R0040176

–

0 when being read.

W

R004017A

A-20 EPSON S1C33210 PRODUCT PART

Watchdog timer writeprotect register

Watchdog timer enable register

0040170

(B)

0040171

(B)

4 PERIPHERAL CIRCUITS

NameAddressRegister name Bit Function Setting Init. R/W Remarks

WRWD

D7

D6–0

D7–2

D1 D0

–

EWD

–

EWD write protection

–

Watchdog timer enable

–

1

Write enabled0Write-protect

1

NMI enabled0NMI disabled

–

0–R/W

–

0

–

0 when being read.

–

0 when being read.

R/W

0 when being read.

–

S1C33210 PRODUCT PART EPSON A-21

4 PERIPHERAL CIRCUITS

Power control register

select register

Clock option register

Power control protect register

0040180

0040181

0040190

(B)

D7 D6

D5

D4–3

D2 D1 D0

D7–1

D0

D7–4

D3 D2 D1 D0

D7 D6 D5 D4 D3 D2 D1 D0

NameAddressRegister name Bit Function Setting Init. R/W Remarks

CLKDT1 CLKDT0

PSCON

–

CLKCHG SOSC3 SOSC1

–

PSCDT0

–

HLT2OP 8T1ON

–

PF1ON

CLGP7 CLGP6 CLGP5 CLGP4 CLGP3 CLGP2 CLGP1 CLGP0

System clock division ratio selection

Prescaler On/Off control reserved CPU operating clock switch High-speed (OSC3) oscillation On/Off Low-speed (OSC1) oscillation On/Off

reserved Prescaler clock selection

–

HALT clock option OSC3-stabilize waiting function reserved OSC1 external output control

Power control register protect flag 0

CLKDT[1:0] Division ratio

1

0

1

0

1 On 0 Off

1 OSC3 0 OSC1 1 On 0 Off 1 On 0 Off

1 OSC1 0 OSC3/PLL

1/8 1/4 1/2 1/1

–

–Prescaler clock

–

1 On 0 Off 1 Off 0 On

–

1 On 0 Off

Writing 10010110 (0x96) removes the write protection of the power control register (0x40180) and the clock option register (0x40190). Writing another value set the write protection.

0 0

1 0 1 1 1

00–

–

0 1 0 0

0 0 0 0 0 0 0

R/W

–

R/W

–

R/W

–

R/W

R/W004019E

Writing 1 not allowed.

0 when being read.

Do not write 1.

A-22 EPSON S1C33210 PRODUCT PART

Serial I/F Ch.0 transmit data register

Serial I/F Ch.0 receive data register

Serial I/F Ch.0 status register

Serial I/F Ch.0 control register

Serial I/F Ch.0 IrDA register

00401E0

(B)

00401E1

(B)

00401E2

(B)

00401E3

(B)

00401E4

(B)

4 PERIPHERAL CIRCUITS

NameAddressRegister name Bit Function Setting Init. R/W Remarks

D7 D6 D5 D4 D3 D2 D1 D0

D7–6

D5 D4 D3 D2 D1 D0

D7 D6 D5 D4 D3 D2 D1 D0

D7–5

D4 D3 D2 D1 D0

TXD06 TXD05 TXD04 TXD03 TXD02 TXD01 TXD00

RXD06 RXD05 RXD04 RXD03 RXD02 RXD01 RXD00

–

TEND0 FER0 PER0 OER0 TDBE0 RDBF0

TXEN0 RXEN0 EPR0 PMD0 STPB0 SSCK0 SMD01 SMD00

–

DIVMD0 IRTL0 IRRL0 IRMD01 IRMD00

Serial I/F Ch.0 transmit data TXD07(06) = MSB TXD00 = LSB

Serial I/F Ch.0 receive data RXD07(06) = MSB RXD00 = LSB

–

Ch.0 transmit-completion flag Ch.0 flaming error flag Ch.0 parity error flag Ch.0 overrun error flag Ch.0 transmit data buffer empty Ch.0 receive data buffer full

Ch.0 transmit enable Ch.0 receive enable Ch.0 parity enable Ch.0 parity mode selection Ch.0 stop bit selection Ch.0 input clock selection Ch.0 transfer mode selection

–

Ch.0 async. clock division ratio Ch.0 IrDA I/F output logic inversion Ch.0 IrDA I/F input logic inversion Ch.0 interface mode selection

0x0 to 0xFF(0x7F)TXD07

0x0 to 0xFF(0x7F)RXD07

1

Transmitting 1 Error 0 Normal 1 Error 0 Normal 1 Error 0 Normal 1 Empty 0 Buffer full 1 Buffer full 0 Empty

–

0 End

1 Enabled 0 Disabled 1 Enabled 0 Disabled 1 With parity 0 No parity 1 Odd 0 Even 1 2 bits 0 1 bit 1 #SCLK0 0

Internal clock

SMD0[1:0] Transfer mode

1

1 1 0 0

1 1/8 0 1/16 1 Inverted 0 Direct 1 Inverted 0 Direct

IRMD0[1:0]–I/F mode

1 1 0 0

8-bit asynchronous

0

7-bit asynchronous

Clock sync. Slave

1

Clock sync. Master

0

1

reserved

0

IrDA 1.0

1

reserved

0

General I/F

X X X X X X X X

–

0 0 0 0 1 0

0 0 X X X X X X

–

X X X X X

R/W 7-bit asynchronous

mode does not use TXD07.

R 7-bit asynchronous

mode does not use RXD07 (fixed at 0).

–

0 when being read.

R

Reset by writing 0.

R/W

Reset by writing 0.

R/W

Reset by writing 0.

R/W

R R

R/W R/W

Valid only in

R/W

asynchronous mode.

R/W R/W R/W R/W

–

0 when being read.

R/W

Valid only in

R/W

asynchronous mode.

R/W R/W

S1C33210 PRODUCT PART EPSON A-23

4 PERIPHERAL CIRCUITS

Serial I/F Ch.1 transmit data register

Serial I/F Ch.1 receive data register

Serial I/F Ch.1 status register

Serial I/F Ch.1 control register

Serial I/F Ch.1 IrDA register

Serial I/F Ch.2 transmit data register

Serial I/F Ch.2 receive data register

Serial I/F Ch.2 status register

00401E5

00401E6

00401E7

00401E8

00401F2

(B)

D7 D6 D5 D4 D3 D2 D1 D0

D7–6

D5 D4 D3 D2 D1 D0

D7 D6 D5 D4 D3 D2 D1 D0

D7–5

D4 D3 D2 D1 D0

D7 D6 D5 D4 D3 D2 D1 D0

D7–6

D5 D4 D3 D2 D1 D0

NameAddressRegister name Bit Function Setting Init. R/W Remarks

TXD16 TXD15 TXD14 TXD13 TXD12 TXD11 TXD10

RXD16 RXD15 RXD14 RXD13 RXD12 RXD11 RXD10

–

TEND1 FER1 PER1 OER1 TDBE1 RDBF1

TXEN1 RXEN1 EPR1 PMD1 STPB1 SSCK1 SMD11 SMD10

–

DIVMD1 IRTL1 IRRL1 IRMD11 IRMD10

TXD26 TXD25 TXD24 TXD23 TXD22 TXD21 TXD20

RXD26 RXD25 RXD24 RXD23 RXD22 RXD21 RXD20

–

TEND2 FER2 PER2 OER2 TDBE2 RDBF2

Serial I/F Ch.1 transmit data TXD17(16) = MSB TXD10 = LSB

Serial I/F Ch.1 receive data RXD17(16) = MSB RXD10 = LSB

–

Ch.1 transmit-completion flag Ch.1 flaming error flag Ch.1 parity error flag Ch.1 overrun error flag Ch.1 transmit data buffer empty Ch.1 receive data buffer full

Ch.1 transmit enable Ch.1 receive enable Ch.1 parity enable Ch.1 parity mode selection Ch.1 stop bit selection Ch.1 input clock selection Ch.1 transfer mode selection

–

Ch.1 async. clock division ratio Ch.1 IrDA I/F output logic inversion Ch.1 IrDA I/F input logic inversion Ch.1 interface mode selection

Serial I/F Ch.2 transmit data TXD27(26) = MSB TXD20 = LSB

Serial I/F Ch.2 receive data RXD27(26) = MSB RXD20 = LSB

reserved Ch.2 transmit-completion flag Ch.2 flaming error flag Ch.2 parity error flag Ch.2 overrun error flag Ch.2 transmit data buffer empty Ch.2 receive data buffer full

0x0 to 0xFF(0x7F)TXD17

0x0 to 0xFF(0x7F)RXD17

1

Transmitting 1 Error 0 Normal 1 Error 0 Normal 1 Error 0 Normal 1 Empty 0 Buffer full 1 Buffer full 0 Empty

–

0 End

1 Enabled 0 Disabled 1 Enabled 0 Disabled 1 With parity 0 No parity 1 Odd 0 Even 1 2 bits 0 1 bit 1 – 0

Internal clock

SMD1[1:0] Transfer mode

111

8-bit asynchronous

0

7-bit asynchronous

1 1/8 0 1/16 1 Inverted 0 Direct 1 Inverted 0 Direct IRMD1[1:0]–I/F mode

1

1 0 1 0

reserved

IrDA 1.0

reserved

General I/F

–

0 End

1 0 0

0x0 to 0xFF(0x7F)TXD27

0x0 to 0xFF(0x7F)RXD27

1

Transmitting 1 Error 0 Normal 1 Error 0 Normal 1 Error 0 Normal 1 Empty 0 Buffer full 1 Buffer full 0 Empty

X

R/W 7-bit asynchronous

X

mode does not use

X

TXD17. X X X X X

X

R 7-bit asynchronous

X

mode does not use X

RXD17 (fixed at 0). X X X X X

–

0 when being read. 0

R

Reset by writing 0.

0

R/W

Reset by writing 0.

0

R/W

Reset by writing 0.

0

R/W

1

R

0

R

0

R/W

0

R/W

X

R/W

X

R/W

X

R/W

Always set to 0

X

R/W

Always set SMD11 to

X

R/W

1

X

–

X X X X

0 when being read.00401E9 R/W R/W R/W R/W

X

R/W00401F0

X X X X X X X

X

R00401F1 X X X X X X X

–

0 when being read.

0

R

Reset by writing 0.

0

R/W

Reset by writing 0.

0

R/W

Reset by writing 0.

0

R/W

1

R

0

R

A-24 EPSON S1C33210 PRODUCT PART

Serial I/F Ch.2 control register

Serial I/F Ch.2 IrDA register

Serial I/F Ch.3 transmit data register

Serial I/F Ch.3 receive data register

Serial I/F Ch.3 status register

Serial I/F Ch.3 control register

Serial I/F Ch.3 IrDA register

00401F3

(B)

00401F4

(B)

00401F7

(B)

00401F8

(B)

4 PERIPHERAL CIRCUITS

NameAddressRegister name Bit Function Setting Init. R/W Remarks

TXEN2

D7 D6 D5 D4 D3 D2 D1 D0

D7–5

D4 D3 D2 D1 D0

D7 D6 D5 D4 D3 D2 D1 D0

D7–6

D5 D4 D3 D2 D1 D0

D7 D6 D5 D4 D3 D2 D1 D0

D7–5

D4 D3 D2 D1 D0

RXEN2 EPR2 PMD2 STPB2 SSCK2 SMD21 SMD20

–

DIVMD2 IRTL2 IRRL2 IRMD21 IRMD20

TXD36 TXD35 TXD34 TXD33 TXD32 TXD31 TXD30

RXD36 RXD35 RXD34 RXD33 RXD32 RXD31 RXD30

–

TEND3 FER3 PER3 OER3 TDBE3 RDBF3

TXEN3 RXEN3 EPR3 PMD3 STPB3 SSCK3 SMD31 SMD30

–

DIVMD3 IRTL3 IRRL3 IRMD31 IRMD30

Ch.2 transmit enable Ch.2 receive enable Ch.2 parity enable Ch.2 parity mode selection Ch.2 stop bit selection Ch.2 input clock selection Ch.2 transfer mode selection

reserved Ch.2 async. clock division ratio Ch.2 IrDA I/F output logic inversion Ch.2 IrDA I/F input logic inversion Ch.2 interface mode selection

Serial I/F Ch.3 transmit data TXD37(36) = MSB TXD30 = LSB

Serial I/F Ch.3 receive data RXD37(36) = MSB RXD30 = LSB

reserved Ch.3 transmit-completion flag Ch.3 flaming error flag Ch.3 parity error flag Ch.3 overrun error flag Ch.3 transmit data buffer empty Ch.3 receive data buffer full

Ch.3 transmit enable Ch.3 receive enable Ch.3 parity enable Ch.3 parity mode selection Ch.3 stop bit selection Ch.3 input clock selection Ch.3 transfer mode selection

reserved Ch.3 async. clock division ratio Ch.3 IrDA I/F output logic inversion Ch.3 IrDA I/F input logic inversion Ch.3 interface mode selection

1 Enabled 0 Disabled 1 Enabled 0 Disabled 1 With parity 0 No parity 1 Odd 0 Even 1 2 bits 0 1 bit 1 #SCLK2 0

Internal clock

SMD2[1:0] Transfer mode

1

1 0 1 0

0x0 to 0xFF(0x7F)TXD37

0x0 to 0xFF(0x7F)RXD37

Transmitting

111

0

1

0

1

0

8-bit asynchronous 7-bit asynchronous

Clock sync. Slave

Clock sync. Master

reserved

IrDA 1.0

reserved

General I/F

–

0 End

Internal clock

8-bit asynchronous 7-bit asynchronous

reserved IrDA 1.0 reserved

General I/F

1 0 0

1 1/8 0 1/16 1 Inverted 0 Direct 1 Inverted 0 Direct

IRMD2[1:0]–I/F mode

1 1 0 0

1 1 Error 0 Normal 1 Error 0 Normal 1 Error 0 Normal 1 Empty 0 Buffer full 1 Buffer full 0 Empty

1 Enabled 0 Disabled 1 Enabled 0 Disabled 1 With parity 0 No parity 1 Odd 0 Even 1 2 bits 0 1 bit 1 – 0

SMD3[1:0] Transfer mode

1 1/8 0 1/16 1 Inverted 0 Direct 1 Inverted 0 Direct IRMD3[1:0]–I/F mode

0 0 X X X X X X

–

X X X X X

X X X X X X X X

–

0 0 0 0 1 0

0 0 X X X X X X

–

X X X X X

R/W R/W

Valid only in

R/W

asynchronous mode.

R/W R/W R/W R/W

–

0 when being read.

R/W

Valid only in

R/W

asynchronous mode.

R/W R/W

R/W00401F5

R00401F6

–

0 when being read.

R

Reset by writing 0.

R/W

Reset by writing 0.

R/W

Reset by writing 0.

R/W

R R

R/W R/W R/W R/W R/W

Always set to 0

R/W

Always set SMD31 to

R/W

1

–

0 when being read.00401F9 R/W R/W R/W R/W

S1C33210 PRODUCT PART EPSON A-25

4 PERIPHERAL CIRCUITS

A/D conversion result (loworder) register

A/D conversion result (highorder) register

A/D trigger register

A/D channel register

A/D enable register

A/D sampling register

0040242

0040243

0040244

0040245

(B)

D7 D6 D5 D4 D3 D2 D1 D0

D7–2

D1 D0

D7–6

D5 D4 D3

D2 D1 D0

D7–6

D5 D4 D3

D2 D1 D0

D7–4

D3 D2 D1 D0

D7–2

D1 D0

NameAddressRegister name Bit Function Setting Init. R/W Remarks

ADD7 ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0

ADD9 ADD8

–

MS TS1 TS0

CH2 CH1 CH0

–

CE2 CE1 CE0

CS2 CS1 CS0

–

ADF ADE ADST OWE

–

ST1 ST0

A/D converted data (low-order 8 bits) ADD0 = LSB

–

A/D converted data (high-order 2 bits) ADD9 = MSB

–

A/D conversion mode selection A/D conversion trigger selection

A/D conversion channel status

–

A/D converter end channel selection

A/D converter start channel selection

–

Conversion-complete flag A/D enable A/D conversion control/status Overwrite error flag

–

Input signal sampling time setup

0x0 to 0x3FF

(low-order 8 bits)

––

0x0 to 0x3FF

(high-order 2 bits)

1 0 1 0

1

0

1

0

1

0

1

0

1

0

1

0

–

Trigger

#ADTRG pin

8-bit timer 0

16-bit timer 0

Software

AD3 AD2 AD1 AD0

–

AD3 AD2 AD1 AD0

– –

Run/Standby

1 Continuous 0 Normal

TS[1:0] 1 1 0 0

CH[2:0] Channel 0 0 0 0

CE[2:0] End channel 0 0 0 0

CS[2:0] Start channel 0 0 0 0

1 Completed 0 1 Enabled 0 Disabled 1 Start/Run 0 Stop 1 Error 0 Normal

–

ST[1:0] Sampring time

1

1 1 0 0

9 clocks

0

7 clocks

1

5 clocks

0

3 clocks

0

R0040240 0 0 0 0 0 0 0

–

–R0 when being read.0040241

0 0

–

0 0 0

–

0 0 0

0 0 0 0

–

1

0 when being read. R/W R/W

Always set CH2 to 0

R

–

0 when being read. R/W

Always set CE2 to 0.

R/W

Always set CS2 to 0.

–

0 when being read. Reset when ADD is read.

R R/W R/W

Reset by writing 0.

R/W

–

0 when being read.

R/W

Use with 9 clocks.

1

A-26 EPSON S1C33210 PRODUCT PART

Port input 0/1 interrupt priority register

Port input 2/3 interrupt priority register

Key input interrupt priority register

High-speed DMA Ch.0/1 interrupt priority register

High-speed DMA Ch.2/3 interrupt priority register

IDMA interrupt priority register

16-bit timer 0/1 interrupt priority register

16-bit timer 2/3 interrupt priority register

16-bit timer 4/5 interrupt priority register

0040260

(B)

0040261

(B)

0040262

(B)

0040263

(B)

0040264

(B)

0040266

(B)

0040267

(B)

0040268

(B)

4 PERIPHERAL CIRCUITS

NameAddressRegister name Bit Function Setting Init. R/W Remarks

D7 D6 D5 D4 D3 D2 D1 D0

D7–3

D2 D1 D0

D7 D6 D5 D4 D3 D2 D1 D0

–

PP1L2 PP1L1 PP1L0

–

PP0L2 PP0L1 PP0L0

–

PP3L2 PP3L1 PP3L0

–

PP2L2 PP2L1 PP2L0

–

PK1L2 PK1L1 PK1L0

–

PK0L2 PK0L1 PK0L0

–

PHSD1L2 PHSD1L1 PHSD1L0

–

PHSD0L2 PHSD0L1 PHSD0L0

–

PHSD3L2 PHSD3L1 PHSD3L0

–

PHSD2L2 PHSD2L1 PHSD2L0

–

PDM2 PDM1 PDM0

–

P16T12 P16T11 P16T10

–

P16T02 P16T01 P16T00

–

P16T32 P16T31 P16T30

–

P16T22 P16T21 P16T20

–

P16T52 P16T51 P16T50

–

P16T42 P16T41 P16T40

reserved Port input 1 interrupt level

reserved Port input 0 interrupt level

reserved Port input 3 interrupt level

reserved Port input 2 interrupt level

reserved Key input 1 interrupt level

reserved Key input 0 interrupt level

reserved High-speed DMA Ch.1 interrupt level

reserved High-speed DMA Ch.0 interrupt level

reserved High-speed DMA Ch.3 interrupt level

reserved High-speed DMA Ch.2 interrupt level

reserved IDMA interrupt level

reserved 16-bit timer 1 interrupt level

reserved 16-bit timer 0 interrupt level

reserved 16-bit timer 3 interrupt level

reserved 16-bit timer 2 interrupt level

reserved 16-bit timer 5 interrupt level

reserved 16-bit timer 4 interrupt level

–

0 to 7

–

0 to 7

–

0 to 7

–

0 to 7

–

0 to 7

–

0 to 7

–

0 to 7

–

0 to 7

–

0 to 7

–

0 to 7

–

0 to 7

–

0 to 7

–

0 to 7

–

0 to 7

–

0 to 7

–

0 to 7

–

0 to 7

–

X X X

–

X X X

–

X X X

–

X X X

–

X X X

–

X X X

–

X X X

–

X X X

–

X X X

–

X X X

–

X X X

–

X X X

–

X X X

–

X X X

–

X X X

–

X X X

–

X X X

–

0 when being read.

R/W

–

0 when being read.

R/W

–

0 when being read.

R/W

–

0 when being read.

R/W

–

0 when being read.

R/W

–

0 when being read.

R/W

–

0 when being read.

R/W

–

0 when being read.

R/W

–

0 when being read.

R/W

–

0 when being read.

R/W

–

0 when being read.0040265

R/W

–

0 when being read.

R/W

–

0 when being read.

R/W

–

0 when being read.

R/W

–

0 when being read.

R/W

–

0 when being read.

R/W

–

0 when being read.

R/W

S1C33210 PRODUCT PART EPSON A-27

4 PERIPHERAL CIRCUITS

8-bit timer, serial I/F Ch.0 interrupt priority register

Serial I/F Ch.1, A/D interrupt priority register

Clock timer interrupt priority register

Port input 4/5 interrupt priority register

Port input 6/7 interrupt priority register

0040269

004026A

004026C

004026D

(B)

D7 D6 D5 D4 D3 D2 D1 D0

D7–3

D2 D1 D0

D7 D6 D5 D4 D3 D2 D1 D0

NameAddressRegister name Bit Function Setting Init. R/W Remarks

–

PSIO02 PSIO01 PSIO00

–

P8TM2 P8TM1 P8TM0

–

PAD2 PAD1 PAD0

–

PSIO12 PSIO11 PSIO10

–

PCTM2 PCTM1 PCTM0

–

PP5L2 PP5L1 PP5L0

–

PP4L2 PP4L1 PP4L0

–

PP7L2 PP7L1 PP7L0

–

PP6L2 PP6L1 PP6L0

reserved Serial interface Ch.0 interrupt level

reserved 8-bit timer 0–3 interrupt level

reserved A/D converter interrupt level

reserved Serial interface Ch.1 interrupt level

reserved Clock timer interrupt level

reserved Port input 5 interrupt level

reserved Port input 4 interrupt level

reserved Port input 7 interrupt level

reserved Port input 6 interrupt level

–

0 to 7

–

0 to 7

–

0 to 7

–

0 to 7

–

0 to 7

–

0 to 7

–

0 to 7

–

0 to 7

–

0 to 7

–

R/W

–

R/W

–

R/W

–

R/W

–

R/W

0 when being read.

–

0 when being read.

–

0 when being read.

–

0 when being read.

–

Writing 1 not allowed.004026B

X X X

–

R/W

–

R/W

–

R/W

–

R/W

0 when being read.

–

0 when being read.

–

0 when being read.

–

0 when being read.

X X X

A-28 EPSON S1C33210 PRODUCT PART

Key input, port input 0–3 interrupt enable register

DMA interrupt enable register

16-bit timer 0/1 interrupt enable register

16-bit timer 2/3 interrupt enable register

16-bit timer 4/5 interrupt enable register

8-bit timer interrupt enable register

Serial I/F interrupt enable register

Port input 4–7, clock timer, A/D interrupt enable register

0040272

0040273

0040274

(B)

4 PERIPHERAL CIRCUITS

NameAddressRegister name Bit Function Setting Init. R/W Remarks

–

D7–6

D5 D4 D3 D2 D1 D0

D7–5

D4 D3 D2 D1 D0

D7 D6

D5–4

D3 D2

D1–0

D7 D6

D5–4

D3 D2

D1–0

D7 D6

D5–4

D3 D2

D1–0

D7–4

D3 D2 D1 D0

D7–6

D5 D4 D3 D2 D1 D0

D7–6

D5 D4 D3 D2 D1 D0

EK1 EK0 EP3 EP2 EP1 EP0

–

EIDMA EHDM3 EHDM2 EHDM1 EHDM0

E16TC1 E16TU1

–

E16TC0 E16TU0

–

E16TC3 E16TU3

–

E16TC2 E16TU2

–

E16TC5 E16TU5

–

E16TC4 E16TU4

–

E8TU3 E8TU2 E8TU1 E8TU0

–

ESTX1 ESRX1 ESERR1 ESTX0 ESRX0 ESERR0

–

EP7 EP6 EP5 EP4 ECTM EADE

reserved Key input 1 Key input 0 Port input 3 Port input 2 Port input 1 Port input 0

reserved IDMA High-speed DMA Ch.3 High-speed DMA Ch.2 High-speed DMA Ch.1 High-speed DMA Ch.0

16-bit timer 1 comparison A 16-bit timer 1 comparison B reserved 16-bit timer 0 comparison A 16-bit timer 0 comparison B reserved

16-bit timer 3 comparison A 16-bit timer 3 comparison B reserved 16-bit timer 2 comparison A 16-bit timer 2 comparison B reserved

16-bit timer 5 comparison A 16-bit timer 5 comparison B reserved 16-bit timer 4 comparison A 16-bit timer 4 comparison B reserved

reserved 8-bit timer 3 underflow 8-bit timer 2 underflow 8-bit timer 1 underflow 8-bit timer 0 underflow

reserved SIF Ch.1 transmit buffer empty SIF Ch.1 receive buffer full SIF Ch.1 receive error SIF Ch.0 transmit buffer empty SIF Ch.0 receive buffer full SIF Ch.0 receive error

reserved Port input 7 Port input 6 Port input 5 Port input 4 Clock timer A/D converter

1 Enabled 0 Disabled

– –

1 Enabled 0 Disabled

–

1 Enabled 0 Disabled

–

1 Enabled 0 Disabled

–

1 Enabled 0 Disabled

–

1 Enabled 0 Disabled

–

1 Enabled 0 Disabled

–

– –

1 Enabled 0 Disabled

– –

1 Enabled 0 Disabled

– –

1 Enabled 0 Disabled

0 0 0 0 0 0

0 0 0 0 0

0 0

–

0 0

–

0 0

–

0 0

–

0 0

–

0 0

–

0 0 0 0

0 0 0 0 0 0

–

0 when being read.0040270 R/W R/W R/W R/W R/W R/W

–

0 when being read.0040271 R/W R/W R/W R/W R/W

R/W R/W

0 when being read.

–

R/W R/W

0 when being read.

–

R/W R/W

0 when being read.

–

R/W R/W

0 when being read.

–

R/W R/W

0 when being read.

–

R/W R/W

0 when being read.

–

0 when being read.0040275 R/W R/W R/W R/W

–

0 when being read.0040276 R/W R/W R/W R/W R/W R/W

–

0 when being read.0040277 R/W R/W R/W R/W R/W R/W

S1C33210 PRODUCT PART EPSON A-29

4 PERIPHERAL CIRCUITS

Key input, port input 0–3 interrupt factor flag register

DMA interrupt factor flag register

16-bit timer 0/1 interrupt factor flag register

16-bit timer 2/3 interrupt factor flag register

16-bit timer 4/5 interrupt factor flag register

8-bit timer interrupt factor flag register

Serial I/F interrupt factor flag register

Port input 4–7, clock timer, A/D interrupt factor flag register

0040282

0040283

0040284

(B)

D7–6

D5 D4 D3 D2 D1 D0

D7–5

D4 D3 D2 D1 D0

D7 D6

D5–4

D3 D2

D1–0

D7 D6

D5–4

D3 D2

D1–0

D7 D6

D5–4

D3 D2

D1–0

D7–4

D3 D2 D1 D0

D7–6

D5 D4 D3 D2 D1 D0

D7–6

D5 D4 D3 D2 D1 D0

NameAddressRegister name Bit Function Setting Init. R/W Remarks

–

FK1 FK0 FP3 FP2 FP1 FP0

–

FIDMA FHDM3 FHDM2 FHDM1 FHDM0

F16TC1 F16TU1

–

F16TC0 F16TU0

–

F16TC3 F16TU3

–

F16TC2 F16TU2

–

F16TC5 F16TU5

–

F16TC4 F16TU4

–

F8TU3 F8TU2 F8TU1 F8TU0

–

FSTX1 FSRX1 FSERR1 FSTX0 FSRX0 FSERR0

–

FP7 FP6 FP5 FP4 FCTM FADE