Epson RX-8801SA-JE User Manual

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ETM26E-03

Application Manual

Real Time Clock Module

RX-8801SA/JE

NOTICE

• The material is subject to change without notice.

• Any part of this material may not be reproduced or duplicated in any form or any means without the written permission of Epson Toyocom.

• The information, applied circuit, program, usage etc., written in this material is just for reference.

Epson Toyocom does not assume any liability for the occurrence of infringing any patent or copyright of a third party. This material does not authorize the licensing for any patent or intellectual copyrights.

• Any product described in this material may contain technology or the subject relating to strategic

products under the control of the Foreign Exchange and Foreign Trade Law of Japan and may require an export licence from the Ministry of International Trade and industry or other approval from another government agency.

• You are requested not to use the products (and any technical information furnished, if any) for the

development and/or manufacture of weapon of mass destruction or for other military purposes. You are also requested that you would not make the products available to any third party who may use the products for such prohibited purposes.

• These products are intended for general use in electronic equipment. When using them in specific

applications that require extremely high reliability such as applications stated below, it is required to obtain the permission from Epson Toyocom in advance. / Space equipment (artificial satellites, rockets, etc) / Transportation vehicles and related (automobiles, aircraft, trains, vessels, etc) / Medical instruments to sustain life / Submarine transmitters / Power stations and related / Fire work equipment and security equipment / traffic control equipment / and others requiring equivalent reliability.

• In this manual for Epson Tyocom, product code and marking will still remain as previously

identified prior to the merger.Due to the on going strategy of gradual unification of part numbers, please review product code and marking as they will change during the course of the coming months. We apologize for the inconvenience, but we will eventually have a unified part numbering system for Epson Toyocom which will be user friendly.

RX - 8801 SA / JE

Contents

1. Overview..........................................................................................................................1

2. Block Diagram .................................................................................................................1

3. Terminal description ........................................................................................................2

3.1. Terminal connections........................................................................................................................2

3.2. Pin Functions ....................................................................................................................................2

4. Absolute Maximum Ratings ............................................................................................. 3

5. Recommended Operating Conditions.............................................................................. 3

6. Frequency Characteristics...............................................................................................3

7. Electrical Characteristics .................................................................................................4

7.1. DC Characteristics............................................................................................................................4

7.2. AC Characteristics ............................................................................................................................5

8. Use Methods....................................................................................................................6

8.1. Overview of Functions ......................................................................................................................6

8.2. Description of Registers....................................................................................................................7

8.2.1. Register table .....................................................................................................................7

8.2.2. Control register (Reg F)......................................................................................................8

8.2.3. Flag register (Reg-E) ........................................................................................................10

8.2.4. Extension register (Reg-D) ...............................................................................................11

8.2.5. RAM register (Reg - 7) .....................................................................................................12

8.2.6. Clock counter (Reg - 0 ∼ 2)...............................................................................................12

8.2.7. Day counter (Reg - 3) .......................................................................................................12

8.2.8. Calendar counter (Reg 4 to 6) ..........................................................................................13

8.2.9. Alarm registers (Reg - 8 ∼ A)............................................................................................13

8.2.10. Fixed-cycle timer control registers (Reg - B to C) ...........................................................13

8.3. Fixed-cycle Timer Interrupt Function...............................................................................................14

8.3.1. Diagram of fixed-cycle timer interrupt function..................................................................14

8.3.2. Related registers for function of time update interrupts. ...................................................15

8.3.3. Fixed-cycle timer interrupt interval (example) ...................................................................16

8.3.4. Fixed-cycle timer start timing............................................................................................16

8.4. Time Update Interrupt Function ......................................................................................................17

8.4.1. Time update interrupt function diagram ............................................................................17

8.4.2. Related registers for time update interrupt functions. .......................................................18

8.5. Alarm Interrupt Function .................................................................................................................19

8.4.1. Diagram of alarm interrupt function ..................................................................................19

8.5.2. Related registers ..............................................................................................................20

8.5.2. Examples of alarm settings...............................................................................................21

8.6. Reading/Writing Data via the I2C Bus Interface..............................................................................22

8.6.1. Overview of I2C-BUS .......................................................................................................22

8.6.2. System configuration ........................................................................................................22

8.6.3. Starting and stopping I2C bus communications ................................................................23

8.6.4. Data transfers and acknowledge responses during I2C-BUS communications ................24

8.6.5. Slave address...................................................................................................................24

8.6.6. I2C bus protocol ................................................................................................................25

8.7. Backup and Recovery.....................................................................................................................26

8.8. Connection with Typical Microcontroller..........................................................................................27

8.9. When used as a clock source (32 kHz-TCXO) ...............................................................................27

9. External Dimensions / Marking Layout ..........................................................................28

10. Application notes .........................................................................................................30

RX − 8801 SA / JE

I2C-Bus Interface Real-time Clock Module

RX − 8801 SA / JE

• Features built-in 32.768 kHz DTCXO, High Stability.

• Supports I

• Alarm interrupt function for day, date, hour, and minute settings

• Fixed-cycle timer interrupt function

• Time update interrupt function

• 32.768 kHz output with OE function

• Auto correction of leap years

• Wide interface voltage range: 2.2 V to 5.5 V

• Wide time-keeping voltage range:1.6 V to 5.5 V

• Low current consumption: 0.8

1. Overview

2. Block Diagram

C-Bus's high speed mode (400 kHz)

(Seconds, minutes)

(FOE and FOUT pins)

(from 2000 to 2099)

μA / 3 V (Typ.)

This module is an I2C bus interface-compliant real-time clock which includes a 32.768 kHz DTCXO. In addition to providing a calendar (year, month, date, day, hour, minute, second) function and a clock counter function, this module provides an abundance of other functions including an alarm function, fixed-cycle timer function, time update interrupt function, and 32.768 kHz output function. The devices in this module are fabricated via a C-MOS process for low current consumption, which enables long-term battery back-up. All of these many functions are implemented in SOP-14 pin and VSOJ-20 pin package.

The I2C-BUS is a trademark of NXP Semiconductors.

FOUT

FOE

/ INT

SCL

SDA

32kHz

DTCXO

DIVIDER

FOUT CONTROLLER

INTERRUPT CONTROLLER

I2C-BUS

INTERFACE

CIRCUIT

32.768 kHz

CLOCK

and

CALENDAR

TIMER

ALARM

CONTROL

and

SYSTEM

CONTROLLER

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RX − 8801 SA / JE

3. Terminal description

3.1. Terminal connections

T1 (CE) 14. N.C.

SCL 13. SDA

FOUT 12. T2 (VPP)

N.C. 11. GND

TEST 10. / INT

VDD 9. N. C.

FOE

SOP − 14pin

RX − 8801 SA

3.2. Pin Functions

Signal

name

I/O Function

SCL Input This is the serial clock input pin for I2C Bus communications.

This pin's signal is used for input and output of address, data, and ACK bits, synchronized

SDA I/O

with the serial clock used for I2C communications. Since the SDA pin is an N-ch open drain pin during output, be sure to connect a suitable pull-up resistance relative to the signal line capacity.

This is the C-MOS output pin with output control provided via the FOE pin.

FOUT Output

When FOE = "H" (high level), this pin outputs a 32.768 kHz signal. When output is stopped, the FOUT pin = "Hi-Z"( high impedance ).

This is an input pin used to control the output mode of the FOUT pin.

FOE Input

When this pin's level is high, the FOUT pin is in output mode. When it is low, output via the FOUT pin is stopped.

/ INT Output

This pins is used to output alarm signals, timer signals, time update signals, and other signals. This pin is an open drain pin.

TEST Input * Use by the manufacture for testing. ( Do not connect externally.)

T1 (CE) Input * Use by the manufacture for testing. ( Do not connect externally.)

T2 (VPP)

VDD

GND

N.C.

−

* Use by the manufacture for testing. ( Do not connect externally.)

This pin is connected to a positive power supply.

This pin is connected to a ground.

This pin is not connected to the internal IC. Leave N.C. pins open or connect them to GND or V

Note: Be sure to connect a bypass capacitor rated at least 0.1 μF between VDD and GND.

8. N.C.

10. FOE

1. /INT 20. N.C.

2. GND 19. N.C.

3. T2

(VPP) 18. N. C.

4. SDA 17. N. C.

5. N.C. 16. N.C.

6. T 1 (CE) 15. N. C.

7. SCL 14. N.C.

8. FOUT 13. N.C.

9. N.C. 12. N.C.

VSOJ − 20pin

RX − 880 1 JE

# 1

# 10

DD.

# 20

# 11

11. V

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RX − 8801 SA / JE

4. Absolute Maximum Ratings

Item Symbol Condition Rating Unit

Supply voltage VDD Between VDD and GND Input voltage (1) VIN1 FOE pin Input voltage (2) VIN2 SCL and SDA pins

Output voltage (1) VOUT1 FOUT pin

Output voltage (2) VOUT2 SDA and /INT pins

Storage temperature TSTG

When stored separately,

without packaging

GND−0.3 GND−0.3 GND−0.3

GND−0.3

to +6.5 V

−0.3 to VDD+0.3 V to +6.5 V

to VDD+0.3 V

to +6.5 V

to +125

−55

5. Recommended Operating Conditions

Item Symbol Condition Min. Typ. Max. Unit

Operating supply voltage VDD Interface voltage 1.6 3.0 5.5 V

Temp. compensation

voltage

VTEM

Clock supply voltage VCLK

Operating temperature TOPR No condensation

6. Frequency Characteristics

Item Symbol Condition Rating Unit

Frequency stability

Δ f / f

Temperature compensation

voltage

−

U A

U B

Ta= 0 to +40 °C, VDD=3.0 V Ta=−40 to +85 °C, V

Ta= 0 to +50 °C, VDD=3.0 V Ta=−40 to +85 °C, V

2.2 3.0 5.5 V

1.6 3.0 5.5 V

−40

DD=3.0 V

+25 +85

(∗1)

± 1.9 ± 3.4

± 3.8 ± 5.0

(∗2)

(∗3)

(∗4)

GND = 0 V

°C

GND = 0 V

°C

GND = 0 V

× 10−6

Frequency/voltage

characteristics

f / V

Oscillation start time

tSTA

Aging fa

1 )

Equivalent to 5 seconds of month deviation. *

3 )

Equivalent to 10 seconds of month deviation. *

Ta= +25 °C, V

Ta= +25 °C, V Ta=−40 to +85 °C, V

Ta= +25 °C, V

2 )

Equivalent to 9 seconds of month deviation.

4 )

Equivalent to 13 seconds of month deviation.

DD=2.2 V to 5.5 V ± 1.0 Max. × 10

DD=1.6 V

DD=1.6 V to 5.5 V

DD=3.0 V, first year ± 3 Max. × 10

1.0 Max.

3.0 Max.

−６

/ V

−６

/ year

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RX − 8801 SA / JE

7. Electrical Characteristics

7.1. DC Characteristics

Item Symbol Condition Min. Typ. Max. Unit

Current consumption (1) Current consumption (2)

Current consumption (3)

Current consumption (4)

Current consumption (5)

Current consumption (6)

Current consumption (7)

Current consumption (8)

Current consumption (9)

Current consumption (10)

High-level input voltage

voltage

High-level output voltage

DD1

DD2

IDD3

IDD4

DD5

IDD6

IDD7

IDD8

IDD9

IDD10

VIH

VIL

VOH1 VOH2 VOH3 VOL1 VDD=5 V, IOL=1 mA GND GND+0.5 VOL2 VDD=3 V, IOL=1 mA GND GND+0.8

Low-level output voltage

VOL3 VOL4 VDD=5 V, IOL=1 mA GND GND+0.25 VOL5 V

OL6 SDA pin

Input leakage current Output leakage current

LK FOE, SCL, SDA pins , VIN = VDD or GND

OZ / INT, SDA, FOUT pins, VOUT = VDD or GND

• Temperature compensation and consumption current

SCL = 0 Hz, / INT = VDD

f FOE = GND FOUT : output OFF ( High Z ) Compensation interval 2.0 s

SCL = 0 Hz, / INT = VDD

f FOE = VDD FOUT :32.768 kHz, CL =0pF Compensation interval 2.0 s

SCL = 0 Hz, / INT = VDD

f FOE = VDD FOUT :32.768 kHz, CL =30pF Compensation interval 2.0 s

SCL = 0 Hz, / INT = VDD

FOE = GND FOUT : output OFF ( High Z ) Compensation OFF

SCL = 0 Hz, / INT = VDD

FOE = GND FOUT : output OFF ( High Z ) Compensation ON ( peak )

FOE pin SCL and SDA pins FOE pin SCL and SDA pins

FOUT pin

/ INT pin

*Unless otherwise specified, GND = 0 V, VDD = 1.6 V to 5.5 V, Ta = −40 °C to +85 °C

VDD=5 V, IOH=−1 mA VDD=3 V, IOH=−1 mA VDD=3 V, IOH=−100 μA

VDD=3 V, IOL=100 μA

VDD=3 V, IOL=1 mA GND GND+0.4 VDD ≥2 V, IOL=3 mA

VDD = 5 V

VDD = 3 V

DD = 5 V

DD = 3 V

DD = 5 V

DD = 3 V

DD = 5 V

DD = 3 V

DD = 5 V

DD = 3 V

0.8 × VDD

0.7 × VDD GND − 0.3 GND − 0.3

1.2 3.4 μA

0.8 2.1

3.0 7.5 μA

2.0 5.0

8.0 20.0 μA

5.0 12.0

1.15 2.95 μA

0.72 1.85

430 900

μA

180 350

VDD + 0.3

5.5

0.2 × VDDLow-level input

0.3 × VDD

4.5 5.0

2.2 3.0

2.9 3.0

GND GND+0.1

GND GND+0.4 V

−0.5

0.5

μA

Compensation ON

0.977 ms

IDD9,10

verage

IDD7,8

Compensation OFF

Compensation interval ( 2.0 s )

Page - 4 ETM26E-03

IDD1,2

RX − 8801 SA / JE

7.2. AC Characteristics

GND = 0 V , V

DD = 1.8 V to 5.5 V , Ta = −40 °C to +85 °C

Item Symbol Condition Min. Typ. Max. Unit

SCL clock frequency fSCL 400 kHz Start condition setup time tSU;STA 0.6 Start condition hold time tHD;STA 0.6 Data setup time tSU;DAT 100 ns Data hold time tHD;DAT 0 900 ns Stop condition setup time tSU;STO 0.6 Bus idle time between

start condition and stop condition Time when SCL = "L" Time when SCL = "H" Rise time for SCL and SDA tr 0.3 Fall time for SCL and SDA tf 0.3

Allowable spike time on bus tSP 50 ns FOUT duty tW /t 50% of VDD level 40 50 60 %

Timing chart

START

Protocol

CONDITION

(S)

SU ; STA

tLOW tHIGH 1 / fSCL

BUF 1.3

LOW 1.3

HIGH 0.6

BIT 7 MSB

(A7)

BIT 6

(A6)

BIT 0

LSB

(R/W)

ACK

(A)

* Unless otherwise specified,

μs μs

μs

μs μs μs μs

STOP

CONDITION

(P)

START

CONDITION

(S)

SU ; STA

SCL

(S)

(P)

BUF

(S)

(A)

HD ; STA

SU ; DAT

HD ; DAT

SU ; STO

HD ; STA

Caution: When accessing this device, all communication from transmitting the start condition to transmitting the stop

condition after access should be completed within 0.95 seconds. If such communication requires 0.95 seconds or longer, the I

C bus interface is reset by the internal bus

timeout function.

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RX − 8801 SA / JE

8. Use Methods

8.1. Overview of Functions

1) Clock functions

This function is used to set and read out month, day, hour, date, minute, second, and year (last two digits) data. Any (two-digit) year that is a multiple of 4 is treated as a leap year and calculated automatically as such until the year

2099.

2) Fixed-cycle interrupt generation function

The fixed-cycle timer interrupt generation function generates an interrupt event periodically at any fixed cycle set between 244.14 μs and 4095 minutes. When an interrupt event is generated, the /INT pin goes to low level ("L") and "1" is set to the TF bit to report that an event has occurred. (However, when a fixed-cycle timer interrupt event has been generated, low-level output from the /INT pin occurs only when the value of the control register's TIE bit is "1". Up to 7.8 ms after the interrupt occurs, the /INT status is automatically cleared (/INT status changes from low level to Hi-Z).

3) Time update interrupt function

The time update interrupt function generates interrupt events at one-second or one-minute intervals, according to the timing of the internal clock. When an interrupt event occurs, the UF bit value becomes "1" and the /INT pin goes to low level to indicate that an event has occurred. (However, when a fixed-cycle timer interrupt event has been generated, low-level output from the /INT pin occurs only when the value of the control register's UIE bit is "1". This /INT status is automatically cleared (/INT status changes from low level to Hi-Z) 7.8 ms (a fixed value) after the interrupt occurs.

4) Alarm interrupt function

The alarm interrupt generation function generates interrupt events for alarm settings such as date, day, hour, and minute settings. When an interrupt event occurs, the AF bit value is set to "1" and the /INT pin goes to low level to indicate that an event has occurred.

5) 32.768-kHz clock output

The 32.768-kHz clock (with precision equal to that of the built-in crystal oscillator) can be output via the FOUT pin. The FOUT pin is a CMOS output pin which can be set for clock output when the FOE pin is at high level and for low-level output when the FOE pin is at high impedance.

6) Interface with CPU

Data is read and written via the I2C bus interface using two signal lines: SCL (clock) and SDA (data). Since neither SCL nor SDA includes a protective diode on the V supply voltages can still be implemented by adding pull-up resistors to the circuit board. The SCL's maximum clock frequency is 400 kHz (when V

DD side, a data interface between hosts with differing

DD ≥ 1.8 V), which supports the I

C bus's high-speed mode.

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RX − 8801 SA / JE

8.2. Description of Registers

8.2.1. Register table

Address Function bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

0 SEC

1 MIN

2 HOUR

3 WEEK

4 DAY

5 MONTH

6 YEAR 80 40 20 10 8 4 2 1

7 RAM

8 MIN Alarm AE 40 20 10 8 4 2 1

9 HOUR Alarm AE

WEEK Alarm 6 5 4 3 2 1 0

DAY Alarm

B Timer Counter 0 128 64 32 16 8 4 2 1

C Timer Counter 1

D Extension Register TEST WADA USEL TE FSEL1 FSEL0 TSEL1 TSEL0

E Flag Register

F Control Register CSEL1 CSEL0 UIE TIE AIE

Note

When after the initial power-up or when the result of read out the VLF bit is "1" , initialize all registers, before using the module. Be sure to avoid entering incorrect date and time data, as clock operations are not guaranteed when the data or time data is incorrect.

∗1) During the initial power-up, the TEST bit is reset to "0" and the VLF bit is set to "1".

∗ At this point, all other register values are undefined, so be sure to perform a reset before using the module.

Only a "0" can be written to the UF, TF, AF, or VLF bit.

∗2)

Any bit marked with "{" should be used with a value of "0" after initialization.

∗3)

∗4) Any bit marked with "•" is a RAM bit that can be used to read or write any data.

The TEST bit is used by the manufacturer for testing. Be sure to set "0" for this bit when writing.

∗5)

{

40 20 10 8 4 2 1

{

40 20 10 8 4 2 1

{ {

{

{ {

{ { {

6 5 4 3 2 1 0

20 10 8 4 2 1

10 8 4 2 1

• • • • • • • •

20 10 8 4 2 1

•

20 10 8 4 2 1

•

• • • •

{ {

UF TF AF

2048 1024 512 256

{

VLF VDET

{ {

RESET

Remark

∗3

−

∗4

−

∗4

−

∗4

∗1, ∗3, ∗5

∗1, ∗2, ∗3

∗3

Page - 7 ETM26E-03

RX − 8801 SA / JE

8.2.2. Control register (Reg F) Address Function bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

∗1) The default value is the value that is read (or is set internally) after powering up from 0 V. ∗2) "o" indicates write-protected bits. A zero is always read from these bits. ∗3) "−" indicates no default value has been defined.

• This register is used to control interrupt event output from the /INT pin and the stop/start status of clock and

calendar operations.

1) CSEL0,1 ( Compensation interval Select 0, 1 ) bits The combination of these two bits is used to set the temperature compensation interval.

2) UIE ( Update Interrupt Enable ) bit When a time update interrupt event is generated (when the UF bit value changes from "0" to "1"), this bit's value specifies if an interrupt signal is generated (/INT status changes from Hi-Z to low) or is not generated (/INT status remains Hi-Z). When a "1" is written to this bit, an interrupt signal is generated (/INT status changes from Hi-Z to low) when an interrupt event is generated. When a "0" is written to this bit, no interrupt signal is generated when an interrupt event occurs.

Control Register CSEL1 CSEL0 UIE TIE AIE

CSEL0,1

Write/Read

UIE

(Default) (0) (1)

CSEL1

(bit 7)

CSEL0

(bit 6)

(−) (−) (−)

Compensation interval

{ {

(0) (0)

0 0 0.5 s

0 1 2.0 s

∗ Default

1 0 10 s

1 1 30 s

Data Function

RESET

(−)

When a time update interrupt event occurs, an interrupt signal is not generated or is canceled (/INT status changes from low to Hi-Z).

When a time update interrupt event occurs, an interrupt signal is generated (/INT status changes from Hi-Z to low).

When a time update interrupt event occurs, low-level output from the /INT pin occurs only when

∗

the value of the control register's UIE bit is "1". This /INT status is automatically cleared (/INT status changes from low to Hi-Z) 7.8 ms after the interrupt occurs.

Write/Read

2) TIE ( Timer Interrupt Enable ) bit When a fixed-cycle timer interrupt event occurs (when the TF bit value changes from "0" to "1"), this bit's value specifies if an interrupt signal is generated (/INT status changes from Hi-Z to low) or is not generated (/INT status remains Hi-Z). When a "1" is written to this bit, an interrupt signal is generated (/INT status changes from Hi-Z to low) when an interrupt event is generated. When a "0" is written to this bit, no interrupt signal is generated when an interrupt event occurs.

TIE

Write/Read

Data Function

When a fixed-cycle timer interrupt event occurs, an interrupt signal is not generated or is canceled (/INT status changes from low to Hi-Z).

When a fixed-cycle timer interrupt event occurs, an interrupt signal is generated (/INT status changes from Hi-Z to low).

* When a fixed-cycle timer interrupt event has been generated low-level output from the /INT pin

occurs only when the value of the control register's TIE bit is "1". Up to 7.8 ms after the interrupt occurs, the /INT status is automatically cleared (/INT status changes from low to Hi-Z)

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