EPSON RX8010SJ B Datasheet

RX

8010SJ

ETM37E-06

Application Manua

Real Time Clock Module

Preliminary

l

NOTICE

• This material is subject to change without notice.

• Any part of this material may not be reproduced or duplicated in any form or any means without the

written permission of Seiko Epson.

• The information about applied circuitry, software, usage, etc. written in this material is intended for reference only. Seiko Epson does not assume any liability for the occurrence of infringing on any patent or copyright of a third party. This material does not authorize the licensing for any patent or intellectual copyrights.

• When exporting the products or technology described in this material, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations.

• You are requested not to use the products (and any technical information furnished, if any) for the development and/or manufacture of weapon of mass destruction or for other military purposes. You are also requested that you would not make the products available to any third party who may use the products for such prohibited purposes.

• These products are intended for general use in electronic equipment. When using them in specific applications that require extremely high reliability, such as the applications stated below, you must obtain permission from Seiko Epson in advance.

• All brands or product names mentioned herein are trademarks and/or registered trademarks of their respective.

/ Space equipment (artificial satellites, rockets, etc.) / Transportation vehicles and related (automobiles, aircraft, trains, vessels, etc.) / Medical instruments to sustain life / Submarine transmitters / Power stations and related / Fire work equipment and security equipment / traffic control equipment / and others requiring equivalent reliability.

ETM37E Revision History

Rev No. Date Page Description ETM37E-01 14.Jul.2013 Release ETM37E-02 06.Sep.2013 28 Corrected a setting data of Flow chart Ex2 ETM37E-03 13.Sep.2013 1 Changed a 1. Overview.

5 Deleted contents of a 8.1 DC characteristics. 5 Corrected a fCLK to fSCL. 6 Changed a comment of 8.2.1. AC characteristics. 7 Deleted a comment of “Target spec” 7 Deleted a software command of TS sample. 20,21 Corrected a 13.3. Alarm interrupt Function. 28 Corrected a setting data of Flow chart Ex2

ETM37E-04 06.Nov.2013 4 Corrected a Item of 7. Frequency Characteristics

6 Corrected a caution of 8.2.1. AC characteristics(1)

ETM37E-05 13.Dec.2013 12 Changed a 12.2. Register table

34

ETM37E-06 25.Sep.2014 7,26

Corrected a 13.8.7. The example of the communication wave pattern Corrected a power-on reset procedure by the software command.

RX8010 SJ

This is a real-time clock module of the serial interface system that incorporates a 32.768 kHz crystal oscillator. The real-time clock function incorporates not only a calendar and clock counter for the year, month, day, day of the week, hour, minute, and second, but also a time alarm, interval timer, and time update interruption, among other

features. All of these many functions are implemented in a thin, compact SOP package, which makes it suitable for various kinds of small electronic devices.

2. Block Diagram

BUILT-IN XTAL ( 32.768 kHz )

/ IRQ1

/ IRQ2

SCL SDA

OSC

ALARM,TIMER,FOUT

TIMER, FOUT

DIVIDER

INTERRUPTS CONTROLLER

BUS INTERFACE CIRCUIT

USER RAM 128 bit

CLOCK

and

CALENDR

TIMER REGISTER

ALARM REGISTER

CONTROL

REGISTER and SYSTEM

CONTROLLER

Page − 1

ETM37E-06

RX8010 SJ

.

1.

8.

2.

7.

3./ IRQ2

6.

4.

5.

3. Terminal description

3.1. Terminal connections

N.C. N.C.

VDD / IRQ1 SCL

GND

SOP − 8pin

SDA

3.2. Pin Functions

Signal

name

SCL Input This is a shift clock input pin for serial data transmission.

SDA Input/Output This is the data input/output pin for serial data transfer.

/ IRQ1 Output

/ IRQ2 Output

VDD Supply

GND Supply

Note: Input pins are able to input up to 5.5V regardless of VDD applied voltage. Note: Open drain pins are able to Pull-up to 5.5V regardless of VDD applied voltage. Note: Connect a bypass capacitor rated at least 0.1µF between power supply pins and GND pin.

I/O Function

This pin outputs interrupt signals ("L" level) for alarm, timer, time update, and FOUT. This is an N-ch open-drain output.

This pin outputs interrupt signals ("L" level) for timer and FOUT. This is a C-MOS output.

This is a power-supply pin. This pin is connected to a ground.

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ETM37E-06

RX8010 SJ

Unit : mm

#8

4.

External Dimensions

4.1. External Dimensions

RX8010SJ

• External dimensions

( SOP − 8 pin )

#1

0.4

7.0 ± 0.2

1.27

0° - 8°

#5

3.9 ± 0.1

#4

6.0 ± 0.2

0.22

2.65 Max.

0.6

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ETM37E-06

RX8010 SJ

to

6.

Recommended Operating

5. Absolute Maximum Ratings

Item Symbol

GND = 0 V

Condition Rating Unit

Supply voltage V

Input voltage VIN SCL,SDA

Output voltage 1 V

Output voltage 2 V

Storage temperature T

Item Symbol

Operating supply voltage V

Clock supply voltage V

Low voltage detection V

Applied voltage when OFF V

Operating temperature

∗Minimum value of Clock supply voltage V supply voltage V

ACC

.

DD

OUT1

/IRQ2

OUT2

SDA, /IRQ1

STG

ACC

CLK

- 1.1 3.0 5.5 V

LOW

- 1.10 V

PUP

SDA, /IRQ1pin 5.5 V

T

OPR

No condensation

CLK

Between VDD and GND

When stored separately,

is the timekeeping continuation lower limit value that initialized RX8010 in operating

7. Frequency Characteristics

−0.3 ∼

without packaging

*Unless otherwise specified, GND = 0 V , Ta = −40 °C to +85 °C

Condition Min. Typ. Max. Unit

-

*Unless otherwise specified, GND = 0 V , Ta = −40 °C to +85 °C

−0.3 ∼

−55

1.6 3.0 5.5 V

−40

+6.5 V

VDD+0.3 V

+6.5 V

+125

+25 +85

°C

Item Symbol

Output frequency fo 32.768

Frequency stability Frequency/voltage

characteristics

Frequency/temperatur

e characteristics

Oscillation start time

Aging fa

∗1 )

The monthly error is equal to one minute. ( excluding offset )

∆ f / f

f / V

Top

t

STA

Ta = +25 °C VDD = 3.0 V Ta = +25 °C

VDD = 1.2 V Ta = −20 °C ∼ +70 °C VDD = 3.0 V ; +25 °C reference Ta = ±0 °C ∼ +50 °C

VDD = 1.6 V Ta = −40 °C ∼ +85 °C

VDD = 1.6 V Ta = +25 °C , VDD = 3.0 V ; first year −5

Condition Min. Typ. Max. Unit

∼

∼ ∼

5.5 V

−2

−120

1.0 s

3.0 s

5 ± 23

+2

+10

+5

( Typ. )

(∗1)

kHz

× 10−6

× 10−6 / V

× 10−6

/ year

Page − 4

ETM37E-06

RX8010 SJ

8. Electrical Characteristics

8.1. DC characteristics

*Unless otherwise specified, GND = 0 V , Ta = −40 °C to +85 °C

8.1.1.

DC characteristics ( 1 )

Item Symbol

*

Unless otherwise specified, GND = 0 V , VDD = 1.6 V ∼ 5.5 V , Ta = −40°C ∼ +85°C

Condition Min. Typ. Max. Unit

Current consumption (1)

Current consumption (2)

Current consumption (3)

Current consumption (4)

Current consumption (5)

Current consumption (6)

High-level input voltage

Low-level input voltage

High-level output voltage

Low-level output voltage

Input

leakage current

Onput

leakage current

I

DD1

Input pins are "L" f

SCL

= 0 Hz, /IRQ1,2 = OFF

TSEL2=”1”

I

DD2

V

I

DD3

f

SCL

= 0 Hz, /IRQ2 = OFF,

V

DD

= 5 V

= 3 V

= 5 V

350

160 320

0.60 1.10

/IRQ1 : 32.768 kHz ON

I

DD4

I

DD5

f

SCL

= 0 Hz, /IRQ1 = OFF,

V

DD

= 3 V

V

DD

= 5 V

0.52 0.90

0.45 1.10

/IRQ2 : 1024 Hz ON ,

I

V

CL = 15 pF

DD6

VIH SCL,SDA pin

VIL SCL, SDA pin

OH1

V

DD

= 3 V

VDD=5 V, IOH=−1 mA

0.40 0.90

0.8 × V

GND − 0.3

5.5 V

DD

4.5 5.0

/IRQ2 pin

V

OH2

V

OL1

VDD =3 V, IOH=−0.5 mA VDD =5 V, IOL=1 mA GND GND +0.5

2.7 3.0

/IRQ2 pin

V

OL2

VDD =3 V, IOL=0.5 mA GND GND +0.3

V

OL4

VDD =5 V, IOL=1 mA GND

/IRQ1 pin

V

OL5

VDD =3 V, IOL=1 mA GND GND +0.4

ILK

IOZ

Input pin, VIN = VDD or GND −0.1 Input pin, V

OUT

= VDD or GND −0.1

0.1

0.2 × V

GND +0.25

DD

nA

µA

V

µA µA

Page − 5

ETM37E-06

RX8010 SJ

t

SU ; STA

SDA

SCL

t

SU ; STA

8.2. AC characteristics

8.2.1. AC characteristics(1)

Item Symbol

SCL clock frequency Start condition setup time Start condition hold time Data setup time Data hold time Stop condition setup time Bus idle time between

start condition and stop condition Time when SCL = "L" Time when SCL = "H" Rise time for SCL and SDA Fall time for SCL and SDA

Allowable spike time on bus t

• Timing chart

Protocol

START

CONDITION

(S)

t

LOW

BIT 7 MSB

(A7)

t

HIGH

*

Unless otherwise specified, GND = 0 V , VDD= 1.6 V ∼ 5.5 V , Ta = −40°C ∼ +85°C

Standard-Mode

(f

SCL

=100kHz)

Fast-Mode

(f

SCL

=400kHz)

Min. Max. Min. Max.

f

SCL

100 400 kHz

t

SU;STA

t

HD;STA

t

SU;DAT

t

HD;DAT

t

SU;STO

t

BUF

t

LOW

t

HIGH

t

r

t

f

SP

1 / f

SCL

4.7 0.6

4.0 0.6

250 100 ns

0 0 ns

4.0 0.6

4.7 1.3

4.0 0.6

1.0 0.3

0.3 0.3 50 50 ns

BIT 6

(A6)

BIT 0

LSB

(R/W)

ACK

(A)

STOP

CONDITION

(P)

START

CONDITION

(S)

Unit

µs µs

µs µs µs

(S)

t

r

t

f

(A)

t

HD ; STA

t

SU ; DAT

t

HD ; DAT

t

SP

Caution: When communication of I2C-bus is started, consumption electric currents increase.

When accessing this device, all communication from transmitting the start condition to transmitting the stop condition after access should be completed within 0.95 seconds. If such communication requires 0.95 seconds or longer, the I2C bus interface is reset by the internal bus timeout function.

8.2.2. AC characteristics (2)

Item Symbol

FOUT symmetry (/IRQ2) SYM 50% V

*

Unless otherwise specified, GND = 0 V , VDD= 1.6 V ∼ 5.5 V , Ta = −40°C ∼ +85°C

Condition Min. Typ. Max. Unit

DD Level

40 50 60 %

t

SU ; STO

(P)

t

BUF

(S)

t

HD ; STA

Page − 6

ETM37E-06

RX8010 SJ

Power supply

VDD

tR1

Backup mode

tCL

IF

Access is

im

possible

Valid V

voltage range

tF

9. Matters that demand special attention on use

9.1. Instructions in the power on

9.1.1. Characteristic for the fluctuation of the power supply

∗tR1 is restrictions to validate power-on reset. When cannot keep this standard, power-on reset does not work normally. It is necessary to initial setting by the software command. Repeated ON/OFF of the power supply in short term, the power-on reset becomes unstable. After power-OFF, keep a state of VDD=GND more than 60 seconds to validate power-on reset.

When it is impossible, please perform initial setting by the software command.

VDD

V

CLK

GND

Access is possible

Item Symbol

Power supply rise time access wait time (Initial power on) access wait time ( Normal power on)

tR1 tCL tCU

Condition Min. Typ. Max. Unit

GND – VDD

-

40 - - ms

A power-on reset procedure by the software command

1) Power- on

2) Wait: At least 40ms.

3) Dummy read. ∗1

4) Check VLF bit = “1”

5) Write 00[h] Address:Reg-1F[h]

6) Write 80[h] Address:Reg-1F[h]

7) Write D3[h] Address:Reg-60[h]

8) Write 03[h] Address:Reg-66[h]

9) Write 02[h] Address:Reg-6B[h]

10) Write 01[h] Address:Reg-6B[h]

11) Wait: At least 2ms *2 END

A disappearance of the FOUT output when the voltage sharply went up and down.

For example, VDD voltage of the RX8010 is come and go between Main power and backup battery. The clock output from output pins disappears then during several milli-seconds when a sharp voltage change happens. Please check that there is not a problem by this characteristic on your system.

An reference example of a power up and down timing without affect to FOUT.

5.5V

1.6 V

DD

for using FOUT.

FOUT

∗1 Dummy read The location of the address is arbitrary. Do not check ACK/NACK from RX8010.

∗2 Wait: At least 2ms This wait time is necessary before transmitting

the command for clearing VLF bit after software command transmission.

tR

FOUT

tCU

1 - 100 µs / V

FOUT

Please make speed to descend of a power supply voltage loose than 4 ms/V.

tR

FOUT

Please make speed to rise of a power supply voltage loose than 4 ms/V.

Page − 7

ETM37E-06

RX8010 SJ

• Normal access is enabled

4

0 [ ms ]

Note: After

4

0 (ms) has elapsed, access is enabled.

9.2.

Restrictions on Access Operations during Power-on Initialization and Recovery from Backup

• RTC-register operations are linked to the internal quartz oscillator's clock signal, so normal operation is not possible if there is no internal oscillation (= oscillation is stopped).

Therefore, we recommend that the initial setting to be set during power-on initialization or backup and restore operations (i.e., when the power supply voltage is recovered after oscillation has stopped due to a voltage drop, etc.) should be "first start internal oscillation, then wait for the oscillation stabilization time (see tSTA standard) to elapse".

• Note the following caution points concerning access operations during power-on initialization or when restoring the power supply voltage from backup mode (here after referred to as "switching to the operating voltage").

1) Before switching to the operating voltage, read the VLF-bit (which indicates the RTC error status).

2) Initialization is required when the value read from the VLF-bit is "VLF = 1 (error status)". Before initializing in response to this VLF = "1" result, we recommend first waiting for the internal oscillation

stabilization time (see the tSTA standard) to elapse.

Initialization is required when the status after reading a VLF-bit value of "1" is either of the following. (Status 1) During power-on initialization

(Status 2) When the clock setting is invalid, such as due to a voltage drop during backup

∗ Access timing during power-on initialization and when recovering the power supply voltage after a drop in the voltage used to maintain the clock

V

DD

(illustration)

During power-on initialization or power supply voltage recovery after drop in clock maintenance voltage

Internal oscillation

Oscillation start voltage [v] Minimum voltage for clock maintenance V

t

STA [ s ]

Oscillation start time

(internal oscillation wait time)

However, access guarantee range is address 20h

∼2Fh.

( Min. )

CLK

[ V ]

• Normal operation is enabled

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ETM37E-06

RX8010 SJ

× 10

-6

10. Reference information

10.1.

Reference Data

(1) Example of frequency and temperature characteristics

0

T

f

∆

-50

-100

Frequency

-150

-50 0 50 100

θT = +25 °C Typ.

α = -0.035 × 10-6 Typ.

Temperature [°C]

[ Finding the frequency stability ]

1.

Frequency and temperature characteristics can be

approximated using the following equations.

∆fT = α ( θT − θX ) 2



∆fT : Frequency deviation in any temperature



α [ 1 / °

( −0.035 ± 0.005 ) × 10



θT [ °C ]



θX [ °C ]

2

C

: Coefficient of secondary temperature

]

6

−

/ °C2

: Ultimate temperature ( +25

: Any temperature

± 5 °C )

2. To determine overall clock accuracy, add the frequency precision and voltage characteristics.

f/f = ∆f/fo + ∆f

∆



∆f/f : Clock accuracy (stable frequency)



f/fo : Frequency precision

∆



fT : Frequency deviation in any temperature.

∆



fV : Frequency deviation in any voltage.

∆

T

fV

+ ∆

in any temperature and voltage.

3. How to find the date difference

Date Difference = ∆f/f × 86400(Sec)

For example: ∆f/f = 11.574

∗

approximately 1 second/day.

10-6 is an error of

×

Page − 9

ETM37E-06

RX8010 SJ

Ts min : +150

Ts max : +200

　-6 ℃/

s Max

ｔｓ

11. Application notes

1) Notes on handling

This module uses a C-MOS IC to realize low power consumption. Carefully note the following cautions when handling.

(1) Static electricity

(2) Noise

(3) Voltage levels of input pins

2) Notes on packaging

(1) Soldering heat resistance.

(2) Mounting equipment

(3) Ultrasonic cleaning

(4) Mounting orientation

(5) Leakage between pins

While this module has built-in circuitry designed to protect it against electrostatic discharge, the chip could still be damaged by a large discharge of static electricity. Containers used for packing and transport should be constructed of conductive materials. In addition, only soldering irons, measurement circuits, and other such devices which do not leak high voltage should be used with this module, which should also be grounded when such devices are being used.

If a signal with excessive external noise is applied to the power supply or input pins, the device may malfunction or "latch up." In order to ensure stable operation, connect a filter capacitor (preferably ceramic) of greater that 0.1 µF as close as possible to the power supply pins. Also, avoid placing any device that generates high level of electronic noise near this module.

When the input pins are at the mid-level, this will cause increased current consumption and a reduced noise margin, and can impair the functioning of the device. Therefore, try as much as possible to apply the voltage level close to VIO or GND.

If the temperature within the package exceeds +260 °C, the characteristics of the crystal oscillator will be degraded and it may be damaged. The reflow conditions within our reflow profile is recommended. Therefore, always check the mounting temperature and time before mounting this device. Also, check again if the mounting conditions are later changed. * See Fig. 1 profile for our evaluation of Soldering heat resistance for reference.

While this module can be used with general-purpose mounting equipment, the internal crystal oscillator may be damaged in some circumstances, depending on the equipment and conditions. Therefore, be sure to check this. In addition, if the mounting conditions are later changed, the same check should be performed again.

Depending on the usage conditions, there is a possibility that the crystal oscillator will be damaged by resonance during ultrasonic cleaning. Since the conditions under which ultrasonic cleaning is carried out (the type of cleaner, power level, time, state of the inside of the cleaning vessel, etc.) vary widely, this device is not warranted against damage during ultrasonic cleaning.

This device can be damaged if it is mounted in the wrong orientation. Always confirm the orientation of the device before mounting.

Leakage between pins may occur if the power is turned on while the device has condensation or dirt on it. Make sure the device is dry and clean before supplying power to it.

Fig. 1 : Reference profile for our evaluation of Soldering heat resistance.

Temperature[℃]

300

TP : +260 ℃ Over

250

℃

200

℃

150

100

50

0

255 ℃

TL : +217 ℃

Time +25 ℃ to Peak

60 120 1 80 240 300 360 420 480 54 0 600 660 720 780

Ramp-up rate +3 ℃/s Max.

60 sto120 s

(+150 ℃ t o +20 0 ℃)

60 sto 150 s

(+2 17 ℃

Page − 10

tp: at least 30s

ｔＬ

Ramp-down rate

Time[s]

ETM37E-06

RX8010 SJ

12. Overview of Functions and Description of Registers

Note:

The initialization of the register is necessary about the unused function and Reserved bit

12.1. Overview of Functions

1) Clock functions

This function is used to set and read out month, day, hour, date, minute, second, and year (last two digits) data. Any (two-digit) year that is a multiple of 4 is treated as a leap year and calculated automatically as such until the year 2099. At the time of a communication start, the Clock & Calendar data are fixed (hold the carry operation), and it is automatically revised at the time of the communication end.

2) Fixed-cycle Timer Interrupt function

The fixed-cycle timer interrupt function generates an interrupt event periodically at any fixed cycle set between

244.14 µs and 65535 hours. When an interrupt event is generated, the /IRQ2 pin goes to low level ("L") and "1" is set to the TF bit to report

3) Long-Timer function

It is able to use fixed cycle timer interrupt function as Long-Timer that deals with for approx. 15 years.

4) Alarm interrupt function

that an event has occurred.

The alarm interrupt function generates interrupt events for alarm settings such as date, day, hour, and minute settings. When an interrupt event occurs, the AF bit value is set to "1" and the /IRQ1 pin goes to low level to indicate that an event has occurred.

5) Time Update Interrupt Function

The time update interrupt function generates interrupt events at one-second or one-minute intervals, according to the timing of the internal clock. When an interrupt event is generated, the /IRQ1 pin goes to low level ("L") and "1" is set to the UF bit to report that an event has occurred.

6) Frequency stop detection function (VLF-bit)

This flag bit indicates the retained status of clock operations or internal data. Its value changes from "0" to "1"

7) Clock output function

when data loss occurs, such as due to a supply voltage drop.

A clock with the same frequency (32.768 kHz) as the built-in crystal resonator can be output from the /IRQ1, /IRQ2 pin.

8) User RAM

RAM register is read/write accessible for any data.

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ETM37E-06

RX8010 SJ

 

-

12.2. Register table

Address [h]

Function bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

10 SEC 11

12 13 14 15 16

MIN HOUR WEEK

DAY

MONTH

YEAR 80 40 20 10 8 4 2 1

Reserved

17

18 19

1A

1B 1C 1D 1E

1F

Setting data 1 1 0 1 1 0 0 0

MIN Alarm AE 40 20 10 8 4 2 1

HOUR Alarm AE

WEEK Alarm

DAY Alarm

Timer Counter 0 128 64 32 16 8 4 2 1 Timer Counter 1 32768 16384 8192 4096 2048 1024 512 256

Extension Register FSEL1 FSEL0 USEL TE WADA TSEL2 TSEL1 TSEL0

Flag Register

Control Register TEST STOP UIE TIE AIE TSTP

Setting data



40

20

10



40 20 10 8 4 2 1



-

AE



0



20 10 8 4 2 1

6 5 4 3 2 1 0



20 10 8 4 2 1



-

•

6 5 4 3 2 1 0

•



STOP UIE TIE AIE TSTP



10 8 4 2 1

-

20 10 8 4 2 1

UF TF AF

-

8

-

4

-



2

-

VLF

- -

1

-



0 0

Address [h]

20

|

2F

Address [h]

30

31

32

Note

∗1.

∗2.

∗3. The '  ' mark indicates a write-prohibited bit, which returns a "0" when read. ∗4. The ' • ' mark indicates a read/write-accessible RAM bit for any data. ∗5. ∗6.

During the initial power-on (from 0 V) and if the value of the VLF bit is "1" when the VLF bit is read, be sure to initialize all registers before using them. When doing this, be careful to avoid setting incorrect data as the date or time, as timed operations cannot be guaranteed if incorrect date or time data has been set.

During the initial power-on (from 0 V), the power-on reset function sets "1" to the VLF bit. ∗ Since the value of other registers is undefined at this time, be sure to reset all registers before using them.

The TEST, bit are Epson test bits.

∗ Be sure to write "0" by initializing before using the clock module. Afterward, be sure to set "0" when writing. ∗ The four TEST* bits are undefined when read. Those bits should be masked after being read.

The '-' mark is a Reserved bit. It is necessary to write in Setting data at the time of initialization. User Register is a free register.

Function bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

RAM

User Register

128 bit ( 16 word x 8 bit )

Function bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

Reserved

-

Setting data 0 0 0 0 0 0 0 0

Reserved



-

Setting data 0 0 0 0 1 0 0 0



IRQ Control

Setting data

-

0 0 0 0 0

-



-

TMPIN FOPIN1 FOPIN0 TMPIN FOPIN1 FOPIN0

-

Page − 12

ETM37E-06

RX8010 SJ

12.3. Description of registers

12.3.1. Clock and calender counter ( Reg - 10[h] ∼ 16[h] )

This is counter registers from a second to year.

12.3.2. RAM registers (Reg - 20[h] ∼ 2F[h] )

12.3.3. Alarm registers ( Reg - 18[h] ∼ 1A[h] )

12.3.4. Timer setting and Timer counter register ( Reg - 1B[h] ∼ 1C[h] )

12.3.5. Function-related register 1 ( Reg - 1D[h] ∼ 1F[h] )

∗ Please refer to [13.1 Clock calendar explanation ] for the details.

This RAM register is read/write accessible for any data in the range from 00 h to FF h.

The alarm interrupt function is used, along with the AE, AF, and WADA bits, to set alarms for specified date, day, hour, and minute values.

∗ Please refer to [13.3. Alarm Interrupt Function ] for the details.

This register is used to set the default (preset) value for the counter. To use the fixed-cycle timer interrupt function,TE, TF, TIE, TSEL2,TSEL1, TSEL0,TMPIN bits are set and used. When the fixed-cycle timer interrupt function is not being used, the fixed-cycle timer control register can be used as a RAM register. In such cases, stop the fixed-cycle timer function by writing "0" to the TE and TIE bits.

∗ Please refer to [13.2. Fixed-cycle Timer Interrupt Function ] for the details.

1) FSEL1, FSEL0 bit

A combination of the FSEL1 and FSEL0 bits is used to select the frequency to be output. The choice is possible by a combination of FSEL-bits select the frequency of clock output or inhibits the clock output.

∗ Please refer to [13.6. FOUT Function ] for the details.

2) USEL , UF, UIE bit

This bit is used to specify either "second update" or "minute update" as the update generation timing of the time update interrupt function.

∗ Please refer to [13.4. Update interrupt function] for the details.

3) TE, TF, TIE, TSEL2, TSEL1, TSEL0, TSTP bit

These bits are used to control operation of the fixed-cycle timer interrupt function.

4) WADA, AF, AIE bit

These bits are used to control operation of the alarm interrupt function.

5) TEST bit

Those bits are the manufacturer's test bit. Always leave this bit value as "0" except when testing.

6) VLF bit

This flag bit indicates the retained status of clock operations or internal data. Its value changes from "0" to "1" when data loss occurs, such as due to a supply voltage drop.

∗ Please refer to [13.5. Frequency stop detection function ] for the details.

7) STOP bit

This bit is to stop a timekeeping operation. In the case of “STOP bit = 1", working is as follows a function . ∗ 1) All the update of timekeeping and the calendar operation stops.

With it, an update interrupt event does not occur at an alarm interrupt and the time.

∗ 2) The part of the fixed-cycle timer interrupt function stops.

A count stops the source clock setting of the timer in case of "64Hz, 1Hz, 1min, 1h".

∗ 3) Note 3: The effect of STOP bit to FOUT functions.

When STOP = "1", 32768Hz output is possible.

But 1Hz and 1024Hz output is disabled.

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12.3.6. Function-related register 2 ( Reg - 30[h] ∼ 32[h] )

1)FOPIN1,FOPIN0 bit

2)TMPIN bit

This bit selects destination (/IRQ1 or /IRQ2) of FOUT.

This bit selects destination (/IRQ1 or /IRQ2) of fixed-cycle timer function.

12.3.7.

Reservedbit

The ' - ' mark has to write in specified fixed value in the case of initialization by all means. Writing data as follows.

Address [h]

17

1F

Function bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

-

Reserved

Setting data

Control Register TEST STOP UIE TIE AIE TSTP

Setting data

1 1 0 1 1 0 0 0

0

-

STOP UIE TIE AIE TSTP

-

Address [h]

30

31

32

The '  ' mark indicates a write-prohibited bit, which returns a "0" when read.

Function bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

-

Reserved

Setting data

Reserved

Setting data

IRQ Control

Setting data

0 0 0 0 0 0 0 0



0 0 0 0 1 0 0 0



0 0 0 0 0

-



-



-

- -

-

0 0

-



-

TMPIN FOPIN1 FOPIN0 TMPIN FOPIN1 FOPIN0

-

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13.

How to use

13.1. Clock calendar explanation

At the time of a communication start, the Clock & Calendar data are fixed (hold the carry operation), and it is automatically revised at the time of the communication end. Therefore it recommends that the access to a clock calendar has continuous access by the auto increment function.

Setting example: Sun, 29-Feb-88 17:39:45 (leap year)

Address [h]

10 SEC 11 MIN 12 HOUR 13 WEEK 14 DAY 15 MONTH 16 YEAR

∗ Note with caution that writing non-existent time data may interfere with normal operation of the clock counter.

13.1.1. Clock counter

Function bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

1) [ SEC ] [ MIN ] register

These registers are 60-base BCD counters. These registers are incremented at the timing when carry is generated from a lower register. At the timing when the lower register changes from 59 to 00, carry is generated to the higher register and thus incremented.

When writing is performed to [SEC] register, Internal-count-down-chain less than one second is cleared to 0.

2) [ HOUR ] register

This register is a 24-base BCD counter (24 hour format).These registers are incremented at the timing

13.1.2. Week counter

when carry is generated from a lower register.

The day (of the week) is indicated by 7 bits, bit 0 to bit 6. The day data values are counted as: Day 01h → Day 02h → Day 04h → Day 08h → Day 10h → Day 20h → Day

40h → Day 01h → Day 02h, etc. It is incremented when carry is generated from the HOUR register. This register does not generate carry to a higher register. Since this register is not connected with the YEAR, MONTH and DAY registers, it needs to be set again with the matching day of the week if any of the YEAR, MONTH or DAY registers have been changed.

The setting example of the week register value.

Day bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Data [h]

Sunday 0 0 0 0 0 0 0 Monday 0 0 0 0 0 0

Tuesday 0 0 0 0 0

Wednesday

0 0 0 0 1 0 0 0 08 h

Thursday 0 0 0

Friday 0 0

Saturday 0

13.1.3. Calendar counter

∗ Do not set "1" to more than one day at the same time.

1

0 0 0 0 0 0 40 h

1) [ DAY ], [ MONTH ] resister

The DAY register is a variable (between 28-base and 31-base) BCD counter that is influenced by the month and the leap year. The MONTH register is 12-base BCD counter. when carry is generated from a lower register.

Jan. Feb. Mar Apr. May June July Aug. Sep. Oct. Nov. Dec. Days Normal year

Leap year 29

31

28

31 30 31 30 31 31 30 31 30 31

2) [ YEAR ] register

This register is a BCD counter for years 00 to 99. The leap year is automatically determined, which reflects in the DAY register.

13.2. Fixed-cycle Timer Interrupt Function

The fixed-cycle timer interrupt function generates an interrupt event periodically at any fixed cycle set between

0 1 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 0 0 1 0 1 1 1 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 1 0 0 0 0 0 0 1 0 1 0 0 0 1 0 0 0

( 512Hz ∼ 1 Hz )

1

0 0 0 0 10 h

0 0 04 h

0 02 h

01 h

0 0 0 0 0 20 h

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244.14 µs and 65535 hours. This function can stop at one time and is available as a accumulative timer.

After the interrupt occurs, the /IRQ status is automatically cleared .

13.2.2. Related registers for function of fixed-cycle timer interrupt function

Address [h]

1B Timer Counter 0 1C Timer Counter 1 1D Extension Register FSEL1 FSEL0 USEL 1E Flag Register 1F Control Register

Address [h]

32 IRQ Control 

∗ Before entering operation settings, we recommend first clearing the TE bit to "0" .

Function bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

128 64 32 16 8 4 2 1

32768 16384 8192 4096 2048 1024

WADA

TE



TEST

Function bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0



UF

STOP UIE

- - -

TF

TIE

AIE

TSEL2 TSEL1 TSEL0



TSTP

TMPIN

TMPINTMPIN

AF



512 256

VLF

- -

FOPIN1 FOPIN0



∗ When the fixed-cycle timer function is not being used, the fixed-cycle Timer Counter0,1 register can be used as a

RAM register. In such cases, stop the fixed-cycle timer function by writing "0" to the TE and TIE bits.

1) Down counter for fixed-cycle timer ( Timer Counter 1, 0 )

This register is used to set the default (preset) value for the counter. Any count value from 1 (0001 h) to 65535 (FFFFh) can be set.

Be sure to write "0" to the TE bit before writing the preset value.

∗ When TE=0, read out data of timer counter is default(Preset) value. And when TE=1, read out data of timer counter is just counting value. But, when access to timer counter data, counting value is not held. Therefore, for example, perform twice read access to obtain right data, and a way to adopt the case that two data accorded is necessary.

2) TSEL2, TSEL1, TESL0 bit

The combination of these three bits is used to set the countdown period (source clock) for this function.

TSEL2

( bit 2 )

∗1) The /IRQ pin's auto reset time (tRTN) varies as shown above according to the source clock setting.

TSEL1

( bit 1 ) 0 0 0 0 0 1 0 1 0 0 1 1

TSEL0 ( bit 0 )

Source clock

4096 Hz /Once per 244.14 µs 122 µs

64 Hz

1/60 Hz

/Once per 15.625 ms /Once per second

1 Hz

/Once per minute

1 0 0 1/3600 Hz /Once per hour

Auto reset time

tRTN

7.813 ms

∗2) The first countdown shortens than a source clock.

When selected 4,096Hz / 64HZ / 1Hz as a source clock, one period of error occurs at the maximum. When selected1/60Hz / 1/3600Hz as a source clock, 1Hz of error occurs at the maximum.

The example of the error of the first countdown: A value to preset is 0004h

TE

Internal source clock

Cycle error

Down counter

TF

Designated cycle

3 2 1 4

4

TF Flag ”0” ⇒ “1”

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Inside counter block diagram

4096Hz

64Hz

1Hz 1/60Hz

1/3600Hz

1/60

1Hz

TSTP

1/60

source

clock

selector

TSTP

timer stop signal TSTP bit

Resister Timer Counter 0 Timer Counter 1

∗ Cannot read the count value that is lower than a selected source clock.

3) TE bit ( Timer Enable )

4) TF bit ( Timer Flag )

When TE bit is "0", the default (preset) can be checked by reading this register.

TE

Write

This is a flag bit that retains the result when a fixed-cycle timer interrupt event is detected.

TF

Data Description

0

Stops fixed-cycle timer interrupt function.

∗ Clearing this bit to zero does not enable the /IRQ low output status to be cleared (to Hi-z).

Starts fixed-cycle timer interrupt function.

1

∗

The countdown that starts when the TE bit value changes from "0" to "1" always begins from the preset value.

Data Description

Write

0

1 This bit is invalid after a "1" has been written to it. 0

Read

1

5) TIE bit ( Timer Interrupt Enable )

The TF bit is cleared to zero to prepare for the next status detection

∗ Clearing this bit to zero does not enable the /IRQ low output status to be cleared (to Hi-z).

−

Fixed-cycle timer interrupt events are detected. (Result is retained until this bit is cleared to zero.)

This bit is used to control output of interrupt signals from the /IRQ1 or /IRQ” pin when a fixed-cycle timer interrupt event has occurred.

TIE

Data Description

1) When a fixed-cycle timer interrupt event occurs, an interrupt signal is not

0

Write

1

generated.

2) When a fixed-cycle timer interrupt event occurs, the interrupt signal is canceled (/IRQ status changes from low to Hi-z).

When a fixed-cycle timer interrupt event occurs, an interrupt signal is generated (/IRQ status changes from Hi-z to low).

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7) TSTP bit ( Timer Stop )

This bit is used to stop fixed-cycle timer count down.

operation

Write

STOP TSTP

0

1 Count stops.

Writing a "0" to this bit cancels stop status (restarts timer count down). ∗The reopening value of the countdown is a stopping value

Description

8) TMPIN bit

Select the destination of the timer interrupt output signal.(/IRQ1 or /IRQ2)

TMPIN

Write

13.2.3. Fixed-cycle timer start timing

Counting down of the fixed-cycle timer value starts at the rising edge of the SCL (ACK output) signal that occurs when the TE value is changed from "0" to "1".

SC L

SD A(Master󲷈

SDA (Slave󲷈

Internal timer

1 X

The count stops at the time of the setting of 64Hz, 1Hz,1/60Hz,1/3600Hz.

Data Description

0 /IRQ2 pin 1 /IRQ1 pin

TE

WADA

TSEL2 TSEL1

TSEL0

ACK

/ IRQ1,2 pin

Count down

13.2.4. Fixed-cycle timer interrupt interval (example)

The combination of the source clock settings and fixed-cycle timer countdown setting sets interrupt interval, as shown in the following examples.

Source clock

Timer Counter

setting

1 ∼ 65535

0 1

•

4096 Hz

TSEL2 = 0

TSEL1, 0 = 0, 0

64 Hz

TSEL2 = 0

TSEL1, 0 = 0, 1

1 Hz

TSEL2 = 0

TSEL1, 0 = 1, 0

1 / 60 Hz

TSEL2 = 0

TSEL1, 0 = 1, 1

− − − − −

244.14 µs

•

15.625 ms 1 s 1 min 1 h

•

1 / 3600 Hz TSEL2 = 1

TSEL1, 0 = 0, 0

•

410 100.10 ms 6.406 s 410 s 410 min 410 h

•

3840 0.9375 s 60.000 s 3840 s 3840 min 3840 h

•

4096 1.0000 s 64.000 s 4096 s 4096 min 4096 h

•

65535 15.9998 s 1023.984 s 65535 s 65535 min 65535 h

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TF bit

TE bit

tRTN

tRTN tRTN

period period period

tRTN

period

" 0 "

Hi -

" 0 "

/IRQ1

4096 Hz

13.2.5. Diagram of fixed-cycle timer interrupt function

TMPIN[1:0]

TIE bit

1

Source clock

1/60 Hz

1/3600 Hz

TSEL[2:0]

TF ( “0” Clear )

Fixed-cycle timer starts

64 Hz

1 Hz

TE

0

/IRQ2

TF Flag

16 bit counter

Timer Control

Circuit

Operation of fixed-cycle timer

/tRTN

Fixed-cycle timer stops

" 1 "

TIE bit

/ IRQ1,2 output

Event occurs

RTC internal operation

Write operation

" 1 "

" L "

" 1 "

∗ After the interrupt event that occurs when the count value changes from 0001h to 0000h, the counter automatically

reloads the preset value and again starts to count down. (Repeated operation)

∗ The count down that starts when the TE bit value changes from "0" to "1" always begins from the preset value.

z

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13.3. Alarm Interrupt Function

13.3.1. Related registers for Alarm interrupt functions.

The alarm interrupt function generates interrupt events for alarm settings such as date, day, hour, and minute settings. When an interrupt event occurs, the AF bit value is set to "1" and the /IRQ1 pin goes to low level to indicate that an event has occurred. AF bit and IRQ output change after 1.46ms from alarm agreement at the maximum.

∗ /IRQ1=”L” output when occurs alarm interruption event is not cancelled automatically unless giving intentional cancellation and /IRQ1=”L” is maintained.

Address [h]

Function bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

18 MIN Alarm AE 40 20 10 8 4 2 1 19 HOUR Alarm

1A

WEEK Alarm

DAY Alarm

AE

•

6 5 4 3 2 1 0

• 1D Extension Register FSEL1 FSEL0 USEL TE 1E Flag Register



1F Control Register TEST STOP UIE TIE

20 10 8 4 2 1

TSEL2 TSEL1 TSEL0



AF

TSTP

WADA

UF TF

AIE

VLF

- -



∗ Before entering settings for operations, we recommend writing a "0" to the AIE bit to prevent hardware interrupts

from occurring inadvertently while entering settings.

∗ When the STOP bit value is "1" alarm interrupt events do not occur. ∗ When the alarm interrupt function is not being used, the Alarm registers can be used as a RAM register. In such

cases, be sure to write "0" to the AIE bit.

∗ Even if use alarm register as RAM register, inside of RTC is processed as alarm setting, therefore it is able to

prevent unintentional alarm occurrence (/IRQ1=”L” occurrence) due to unexpected agreement with writing data and timer condition by means of setting to AIE=”0”.

1) Alarm registers ( Reg − 18[h] to 1A[h] )

In the WEEK alarm /Day alarm register (Reg - 1A), the setting selected via the WADA bit determines whether WEEK alarm data or DAY alarm data will be set. If WEEK has been selected via the WADA bit, multiple days can be set (such as Monday, Wednesday, Friday, Saturday).

∗1) The register that "1" was set to "AE" bit, doesn't compare alarm.

(Example) Write 80h (AE = "1") to the WEEK Alarm /DAY Alarm register (Reg - 1A): Only the hour and minute settings are used as alarm comparison targets. The week and date settings are not used as alarm comparison targets. As a result, alarm occurs if only an hour and minute accords with alarm data.

∗2) If all three AE bit values are "1" the week/date settings are ignored and an alarm interrupt event will

occur once per minute.

∗3) Even if the current date/time is used as the setting, the alarm will not occur until the counter counts up

2) WADA bit ( Week Alarm / Day Alarm Select )

to the current date/time (i.e., an alarm will occur next time, not immediately).

The alarm interrupt function uses either "Day" or "Week" as its target. The WADA bit is used to specify either WEEK or DAY as the target for alarm interrupt events.

WADA

Write

3) AF bit ( Alarm Flag )

Data Description

0 Sets WEEK as target of alarm function 1 Sets DAY as target of alarm function

When this flag bit value is already set to "0", occurrence of an alarm interrupt event changes it to "1". When this flag bit value is "1", its value is retained until a "0" is written to it.

AF

Write

Data Description

0

Clearing this bit to zero enables /IRQ1 low output to be canceled (/IRQ1 remains Hi-z) when an alarm interrupt event has occurred.

1 This bit is invalid after a "1" has been written to it. 0

Read

1

−

Alarm interrupt events are detected. (Result is retained until this bit is cleared to zero.)

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Χ Χ Χ Χ Χ Χ Χ

4) AIE bit ( Alarm Interrupt Enable )

13.3.2. Examples of alarm settings

1) Example of alarm settings when "Week" has been specified (and WADA bit = "0")

2) Example of alarm settings when "Day" has been specified (and WADA bit = "1")

This bit is used to control output of interrupt signals from the /IRQ1 pin when an Alarm interrupt event has occurred.

AIE

Write

∗The AIE bit is only output control of the /IRQ1 terminal. It is necessary to clear an AF flag to cancel alarm.

Week is specified

WADA bit = "0"

Monday through Friday, at 7:00 AM ∗ Minute value is ignored Every Saturday and Sunday, for 30 minutes each hour ∗ Hour value is ignored

Every day, at 6:59 AM

Χ: Don't care

Day is specified

WADA bit = "1"

First of each month, at 7:00 AM ∗ Minute value is ignored 15th of each month, for 30 minutes each hour ∗ Hour value is ignored

Every day, at 6:59 PM 1

Χ: Don't care

Data Description

1) When an alarm interrupt event occurs, an interrupt signal is not

0

generated or is canceled (/IRQ1 status remains Hi-z).

2) When an alarm interrupt event occurs, the interrupt signal is canceled (/IRQ1 status changes from low to Hi-z).

1

When an alarm interrupt event occurs, an interrupt signal is generated (/IRQ1 status changes from Hi-z to low).

Week Alarm

bit

7

AE

6

5

4

S

F

3

T

W

T

bit

2

1

0

M

S

0 0 1 1 1 1 1 0 0 1 0 0 0 0 0 1 AE bit = 1 30 h

0 1 1 1 1 1 1 1 1

Day Alarm

bit

AE

bit

6

7

5

4

20

•

3

10

08

04

bit

2

1

0

02

01

0 0 0 0 0 0 0 1 0 0 0 1 0 1 0 1 AE bit = 1 30 h

HOUR

Alarm

07 h AE bit = 1

18 h 59 h

HOUR

Alarm

07 h AE bit = 1

18 h 59 h

MIN

Alarm

MIN

Alarm

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AIE bit

AF bit

" 0 "

" L "

" 1 "

13.3.3. Diagram of alarm interrupt function

MIN comparison result

MIN AE

HOUR comparison result

HOUR AE

WEEK comparison result

WEEK / DAY AE

DAY comparison result

Internal MIN Update

AF ( “0” Clear )

/IRQ1 output

WADA

AIE

0

AF Flag

1

/IRQ1

" 1 "

Hi - z

" 0 "

Event occurs

RTC internal operation Write operation

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13.4. Time Update Interrupt Function

The time update interrupt function generates interrupt events at one-second or one-minute intervals, according to the timing of the internal clock. This /IRQ1 status is automatically cleared

13.4.1. Related registers for time update interrupt functions.

Address [h]

1D Extension Register FSEL1 FSEL0 1E Flag Register 1F Control Register TEST STOP

Function bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

USEL



UF

UIE

TE WADA TSEL2 TSEL1 TSEL0



TF AF

TIE AIE TSTP

VLF

- -



∗ Before entering settings for operations, we recommend writing a "0" to the UIE bit to prevent hardware interrupts

from occurring inadvertently while entering settings.

∗ When the STOP bit value is "1" time update interrupt events do not occur. ∗ Although the time update interrupt function cannot be fully stopped, if "0" is written to the UIE bit, the time update

interrupt function can be prevented from changing the /IRQ1 pin status to low.

1) USEL bit ( Update Interrupt Select ) This bit is used to select "second" update or "minute" update as the timing for generation of time update interrupt events.

USEL Data Description

Selects "second update" (once per second) as the timing for generation of interrupt events

Selects "minute update" (once per minute) as the timing for generation of interrupt events

Write

2) UF bit ( Update Flag )

0

1

This flag bit value changes from "0" to "1" when a time update interrupt event occurs.

UF Data Description

Write

0 1 This bit is invalid after a "1" has been written to it.

0

Read

3) UIE bit ( Update Interrupt Enable )

1

Clearing this bit to zero enables /IRQ1 low output to be canceled (/IRQ1 remains Hi-z) when an time update interrupt event has occurred.

−

Time update interrupt events are detected. (The result is retained until this bit is cleared to zero.)

This bit selects whether to generate an interrupt signal or to not generate it.

UIE Data Description

1) Does not generate an interrupt signal. (/IRQ1 remains Hi-z)

Write / Read

0

1 When an Update interrupt event occurs, an interrupt signal is generated.

2) Cancels interrupt signal triggered by time update interrupt event (/IRQ1 changes from low to Hi-z).

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tRTN

period period period period

13.4.2. Time update interrupt function diagram

UIE bit

UF ( “0” Clear )

UF Flag

/IRQ1

Carry Sec. Carry Min.

USEL bit

F64Hz

UIE bit

/ IRQ1 output

UF bit

Carry

tRTN = 7.568 ms ~ 15.625 ms

Operation in RTC

Write operation

Update Control

Circuit

/tRTN

" 1 " " 0 "

Hi - z " L "

" 1 " " 0 "

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13.5.

Frequency stop detection function

This flag bit indicates the retained status of clock operations or internal data. Its value changes from "0" to "1" when data loss occurs, such as due to a supply voltage drop. Once this flag bit's value is "1", its value is retained until a "0" is written to it.This function can not detect voltage down of short time. During the initial power-on (from 0 V) and if the value of the VLF bit is "1" when the VLF bit is read, be sure to initialize all registers before using them.

VLF

Data Description

Write

0 The VLF is cleared to 0, and waiting for next low voltage detection. 1 It is impossible to write in 1 to VLF.

0 RTC register data are valid.

Read

1

RTC register data are invalid. Should be initialized of all register data. VLF is maintained till it is cleared by zero.

13.6. FOUT function [clock output function]

The clock signal can be output via the /IRQ1, /IRQ2 pin.

When stopped the /IRQ2 pin output, the pin becomes the Hi-z.

13.6.1. FOUT control register.

Address [h]

Function bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

1D Extension Register

Address [h]

Function bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

32 IRQ Control

By a combination of FSEL1,FSEL0, an FOUT outputs 32768Hz and 1024Hz and 1Hz and can stop the output.

13.6.2. FOUT function table.

FOUT output pin layout and select the frequency.

FOPIN1 FOPIN0

0 0

0 1

Output pin FSEL1 FSEL0 output

/IRQ2

(CMOS)

/IRQ1

(Open-Drain)

∗ At the time of the initial power-on, “0” is set to FSEL1, FSEL0.

Note: The effect of STOP bit to FOUT functions.

When STOP = "1", 32768Hz output is possible.

But 1Hz and 1024Hz output is disabled.

FSEL1 FSEL0



-

0 0 OFF 0 1 1 0 1 1 Don't set it 0 0 OFF 0 1 1 0 1 1

USEL TE WADA TSEL2 TSEL1 TSEL0



-

TMPIN

FOPIN1 FOPIN0

1 Hz Output 1024 Hz Output

1 Hz Output 1024 Hz Output 32768 Hz Output32768 Hz Output

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•

13.7. Flow-chart

The following flow-chart is one instance. Mention for easy understanding takes precedence over others; therefore there are some inefficient cases for the actual processing. If you wish to take more efficient process, perform some processes at the same time or try to confirm and adjust some part where is no hindered from transposing of operation procedure. (Unnecessary processing may be included in mentioned items according to conditions to use. To get movement according to your expectation, please surely adjust according to conditions to use (use environment).

1) Processing example of the power on.

Start

Power on

Wait

Dummy read

VLF=1 ?

VLF=”0” clear

Wait

VLF=0 ?

Software reset

Wait time of 40ms is necessary at least

When power-on reset cannot satisfy a power supply condition

valid, execute a dummy read.

NO

Whether it is a return from the state of the backup is confirmed.

YES

When an internal oscillation starts, 0 writing of VLF is approved.

Please set waiting time depending on load of a system optionally

NO

YES

When power-on reset cannot satisfy a power supply condition

valid, execute a software reset.

After software reset, VLF bit is set “1” again.

Initialize

Start-up complete

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•

stop the fixed

-

cycle timer function by writing "0" to the TE and TIE bits

.

∗

−

•

2) An example of the initialization

Ex.1 Initialize

START

Setting the reserved bits

Reg − 17[h], 30[h]∼ 32[h]

Reg

1D[h]

Reg − 1E[h]

Reg − 1F[h]

Setting the present time

( Reg − 10[h] ∼ 16[h] )

Setting the Alarm function

( Reg −18[h] ∼ 1A[h] )

Setting the Timer function

( Reg −1B[h] ∼ 1F[h],32[h] )

Setting the Update function

( Reg − 1D[h] ∼ 1F[h] )

Reserved bits have to write in specified fixed value in the case

of initialization by all means.

Set TE bit to “0”.

• Set FSEL1, 0 bit optionally.

Clear VLF bit to “0”.

Surely set TEST bit to " 0 ".

• Set AIE, TIE, UIE bit to “0 " to prevent unprepared interruption output.

Set the present time.

∗ Setting the present time concerned, please refer to item of [ Clock and

calendar writing ] .

Set the Alarm interrupt function. When the alarm interrupt function is not being used, the Alarm registers (Reg - 18h to 1Ah) can be used as a RAM register. In such cases, be sure to

write "0" to the AIE bit.

Set the fixed-cycle Timer function.

When the fixed-cycle timer function is not being used, the fixed-cycle timer

register (Reg – 1B to 1C) can be used as a RAM register. In such cases,

Set the Update interrupt function.

When initialization is finished, be sure to set STOP bit to “0”.

Next processing

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•

∗

•

[

•

∗

Ex.2 This example is use only for clock functions.

START

Setting the reserved bits

Reg − 17[h], 30[h]∼ 32[h]

Reserved bits have to write in specified fixed value in the case

of initialization by all means.

Reg − 1D[h]

Reg − 1E[h]

Reg − 1F[h]

Setting the present time

( Reg − 10[h] ∼ 16[h] )

Setting the Alarm function

( Reg −18[h] ∼ 1A[h] )

Setting the Timer function

( Reg − 1B[h] ∼ 1C[h] )

Stop cancellation

( Reg − 1F[h] )

Start clock

3) The setting of a clock and calendar

START

STOP ← " 1 "

• Write 04[h]

• Write 00[h]

Write 40[h]

Set STOP bit to “1” to prevent timer update in time setting.

•Set the present time.

The alarm function stops by initialization of Reg 1F[h].

Reg - 18h to 1Ah can be used as a RAM register.

The Timer function stops by initialization of Reg - 1E[h] and Reg – 1F[h]. Reg – 1Bh to 1Ch can be used as a RAM register.

Write 00[h]

Cancel STOP bit to “0” and start (restart) clock.

When initialization is finished, be sure to set STOP bit to “0”.

Set STOP bit to “1” to prevent timer update in time setting.

Write time

Write information of

minute: second ] which is necessary to set (or reset).

year / month /date [day of the week] hour:

In case of initialization, please initialize all data.

STOP ← " 0 "

Cancel STOP bit to “0” and start (restart) timer movement. Timer is started when set STOP bit to “0”.

Next process

It is able to set time even if not combined use of STOP bit. Please note that [ clock is started at the time of writing [second ] ] in case STOP bit is not used.

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•

∗

→ " 1 "

•

4) The reading of a clock and calendar

Reading of the clock

Read clock

Next process

• Please complete access within 0.95 seconds The STOP bit holds "0".

(It causes the clock delay to set STOP bit to “1”)

• At the time of a communication start, the Clock & Calendar data are fixed (hold the carry operation), and it is automatically revised at the time of the communication end.

• The access to a clock calendar recommends to have access to continuation by a auto increment function.

5) The setting example of the fixed-cycle timer interrupt function

START

Reg-1D[h]

Clear TE bit to “0” to stop timer-interrupt function.

• The countdown period is fixed by the combination of the TSEL2, TSEL1, TSEL0 bit.

Reg-1E[h]

Reg-1F[h]

Clear TF bit to “0” to cancel last timer interrupt output (/IRQ output).

Select and set /IRQ output

(if output “L” level interrupt output or not) when event occurs.

If output “L” level interrupt output, set TIE bit to “1”.

Select output pin. (/IRQ1 or /IRQ2)

Reg-32[h]

Reg − 1B[h], 1C[h]

Start count

• Set initial value of down counter.

Set TE bit to "1" to start timer interrupt function. When start timers interrupt function, please surely set/reset (*implement 2) initial value of down counter in advance.

Next process

1 Countdown is suspended with TSTP, " 0 "

performed again with TSTP, " 1 " → " 0 "

and countdown is

∗2 When you want to restart from a pre-set value, please set a TE bit to “1”

again after setting a TE bit to “0”.

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•

−

•

6) The setting example of the Alarm interrupt function

START

Reg-1F[h]

Clear AIE bit to “0” to stop Alarm-interrupt function.

Reg

18[h], 1A[h]

Reg-1D[h]

Reg-1E[h]

Reg − 1F[h]

Next process

Set alarm data.

Select week or day in WADA bit

Clear AF bit

• Select and set /IRQ1 output in AIE bit.

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13.8.

Reading/Writing Data via the I2C Bus Interface

13.8.1. Overview of I2C-BUS

13.8.2. Data transfers

13.8.3. Starting and stopping I2C bus communications

The I2C bus supports bi-directional communications via two signal lines: the SDA (data) line and SCL (clock) line. A combination of these two signals is used to transmit and receive communication start/stop signals, data transfer signals, acknowledge signals, and so on.

Both the SCL and SDA signals are held at high level whenever communications are not being performed.

The starting and stopping of communications is controlled at the rising edge or falling edge of SDA while SCL is at high level.

Data transfers are performed in 8-bit (1 byte) units once the START condition has occurred. There is no limit on the amount (bytes) of data that are transferred between the START condition and STOP condition. (However, the transfer time must be no longer than 0.95 seconds.)

SCL

START

condition

[ S ]

Repeated START(RESTART)

condition

[ Sr ]

STOP

condition

[ P ]

SDA

0.95

s ( Max. )

1) START condition, repeated START condition, and STOP condition (1) START condition

• The SDA level changes from high to low while SCL is at high level.

(2) STOP condition

• This condition regulates how communications on the I2C -BUS are terminated. The SDA level changes from low to high while SCL is at high level.

(3) Repeated START condition (RESTART condition)

• In some cases, the START condition occurs between a previous START condition and the next STOP condition, in which case the second START condition is distinguished as a RESTART condition. Since the required status is the same as for the START condition, the SDA level changes from high to low while SCL is at high level.

13.8.4. Slave address

The I2C-BUS devices do not have any chip select or chip enable pins. All I2C-BUS devices are memorized with a fixed unique number in it. The chip selection on the I2C-BUS is executed, when the interface starts, the master device send the required slave address to all devices on the I2C-BUS. The receiving device only reacts for interfacing, when the required slave address is agreed with its own slave address.

During in actual data transmission, the transmitted data contains the slave address and the data with R/W

(read/write) bit.

Slave address R/W

bit

bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

0 1 1 0 0 1 0 R/W

0 when write mode

1 when read mode

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Master

Slave

CPU, etc.

Master

Slave

13.8.5. System configuration

All ports connected to the I2C bus must be either open drain or open collector ports in order to enable AND connections to multiple devices.

SCL and SDA are both connected to the VIO line via a pull-up resistance. Consequently, SCL and SDA are both held at high level when the bus is released (when communication is not being performed).

V

DD

SDA SCL

Transmitter/

Receiver

Transmitter/

Receiver

RX8010

Transmitter/

Receiver

Other I2C bus device

Transmitter/

Receiver

Any device that controls the data transmission and data reception is defined as a "Master". and any device that is controlled by a master device is defined as a “Slave”. The device transmitting data is defined as a “Transmitter” and the device receiving data is defined as a receiver”

In the case of this RTC module, controllers such as a CPU are defined as master devices and the RTC module is defined as a slave device. When a device is used for both transmitting and receiving data, it is defined as either a transmitter or receiver depending on these conditions.

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(1)

(3)

(4)

(5)

(8)

(9)

(6)

(7) (2)

(1)

(3)

(4)

(6)

(5)

(8)

(9)

(10)

(11)

(13)

(12)

(7)

(2)

(1)

(3)

(4)

(5)

(7)

(6)

(8)

(2)

13.8.6. I2C bus protocol

In the following sequence descriptions, it is assumed that the CPU is the master and the RX8010 is the slave.

1) Address specification write sequence Since the RX8010 includes an address auto increment function, once the initial address has been specified, the

RX8010 increments (by one byte) the receive address each time data is transferred.

(1) CPU transfers start condition [S]. (2) CPU transmits the RX8010's slave address with the R/W bit set to write mode. (3) Check for ACK signal from RX8010. (4) CPU transmits write address to RX8010. (5) Check for ACK signal from RX8010. (6) CPU transfers write data to the address specified at (4) above. (7) Check for ACK signal from RX8010. (8) Repeat (6) and (7) if necessary. Addresses are automatically incremented. (9) CPU transfers stop condition [P].

S

2) Address specification read sequence

3) Read sequence when address is not specified

After using write mode to write the address to be read, set read mode to read the actual data.

(1) CPU transfers start condition [S]. (2) CPU transmits the RX8010's slave address with the R/W bit set to write mode. (3) Check for ACK signal from RX8010. (4) CPU transfers address for reading from RX8010. (5) Check for ACK signal from RX8010. (6) CPU transfers RESTART condition [Sr] (in which case, CPU does not transfer a STOP condition [P]). (7) CPU transfers RX8010's slave address with the R/W bit set to read mode. (8) Check for ACK signal from RX8010 (from this point on, the CPU is the receiver and the RX8010 is the transmitter). (9) Data from address specified at (4) above is output by the RX8010. (10) CPU transfers ACK signal to RX8010. (11) Repeat (9) and (10) if necessary. Read addresses are automatically incremented. (12) CPU transfers ACK signal for "1". (13) CPU transfers stop condition [P].

S

Slave address

Once read mode has been initially set, data can be read immediately. In such cases, the address for each read operation is the previously accessed address + 1.

(1) CPU transfers start condition [S]. (2) CPU transmits the RX8010's slave address with the R/W bit set to read mode. (3) Check for ACK signal from RX8010 (from this point on, the CPU is the receiver and the RX8010 is the transmitter). (4) Data is output from the RX8010 to the address following the end of the previously accessed address. (5) CPU transfers ACK signal to RX8010. (6) Repeat (4) and (5) if necessary. Read addresses are automatically incremented in the RX8010. (7) CPU transfers ACK signal for "1". (8) CPU transfers stop condition [P].

S

Slave address

0

R/W

Slave address

R/W

0

R/W ACK from RX8010

0

Address

0

ACK signal from RX8010

Address

1

0

ACK from RX8010

Data

Sr

0

Data

Slave address

ACK from CPU

0

1

0

Data

R/W

1

0

Data

P

Data

0

P

Data

ACK from CPU

P

1

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13.8.7. The example of the communication wave pattern

1) Address specification read sequence When write in A5h for address 20h:

SCL

SDA

START

Slave address + 0(Write)

Address (20h)

Write data Write in A5h

ACK signal from RX8010

∗CPU release the SDA line

STOP

2) Address specification read sequence When read A5h from address 20h:

SCL

SDA

STRAT

Slave address + 0(Write)

Address (20h)

RESTRAT

Slave address + 1(Read)

ACK signal from RX8010

∗CPU release the SDA line

Data of Address 20h A5h read

STOP

ACK from CPU

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Application Manual

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Electronic devices information on WWW server

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EPSON RX8010SJ B Datasheet

NOTICE

Contents

1. Overview

2. Block Diagram

3. Terminal description

3.1. Terminal connections

3.2. Pin Functions

External Dimensions

4.1. External Dimensions

Recommended Operating

5. Absolute Maximum Ratings

7. Frequency Characteristics

8. Electrical Characteristics

8.1. DC characteristics

8.2. AC characteristics

9. Matters that demand special attention on use

9.1. Instructions in the power on

Restrictions on Access Operations during Power-on Initialization and Recovery from Backup

10. Reference information

Reference Data

11. Application notes

12. Overview of Functions and Description of Registers

12.1. Overview of Functions

12.2. Register table

12.3. Description of registers

How to use

13.1. Clock calendar explanation

13.2. Fixed-cycle Timer Interrupt Function

13.3. Alarm Interrupt Function

13.4. Time Update Interrupt Function

Frequency stop detection function

13.6. FOUT function [clock output function]

13.7. Flow-chart

Reading/Writing Data via the I2C Bus Interface