EPSON RX6110SA B Datasheet

ETM40E-03

Application Manua

Real Time Clock Module

RX6110SA B

( Tolerance B : 5 ± 23 x 10-6 )

Preliminary

l

NOTICE

• This material is subject to change without notice.

• Any part of this material may not be reproduced or duplicated in any form or any means without the

written permission of Seiko Epson.

• The information about applied circuitry, software, usage, etc. written in this material is intended for reference only. Seiko Epson does not assume any liability for the occurrence of infringing on any patent or copyright of a third party. This material does not authorize the licensing for any patent or intellectual copyrights.

• When exporting the products or technology described in this material, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations.

• You are requested not to use the products (and any technical information furnished, if any) for the development and/or manufacture of weapon of mass destruction or for other military purposes. You are also requested that you would not make the products available to any third party who may use the products for such prohibited purposes.

• These products are intended for general use in electronic equipment. When using them in specific applications that require extremely high reliability, such as the applications stated below, you must obtain permission from Seiko Epson in advance.

• All brands or product names mentioned herein are trademarks and/or registered trademarks of their respective.

/ Space equipment (artificial satellites, rockets, etc.) / Transportation vehicles and related (automobiles, aircraft, trains, vessels, etc.) / Medical instruments to sustain life / Submarine transmitters / Power stations and related / Fire work equipment and security equipment / traffic control equipment / and others requiring equivalent reliability.

ETM40E Revision History

Rev No. Date Page Description ETM40E-01 02.Dec.2013 Release ETM40E-02 15.Oct.2014 10,33

30,31 Added a 14.9. Digital offset function 6 Added a Low-level output voltage VOL6 15,17,28

29,32

17 Added a comment to 13.3.7. Reserved bit

ETM40E-03 12.Apr.2016 5

6 10

13 14

16,18 29

Corrected a power-on reset procedure by the software command.

An exhibition of an IOCUTEN function and a flow chart review with it. (bit4 of address 31h(I2C),bit4 of address 1 of BANK3(SPI))

Added a rank of the frequency tolerance [tolerance B]. Corrected a condition of the frequency / voltage characteristic.

Corrected a condition of the current consumption. Corrected a [10.2.2. Characteristic for the fluctuation of

the power supply]. Added a [11.2. Reference characteristic data (Typical)] Added a [(6) Installation of charged battery.] in [12.

Application notes] Added a rank of the frequency tolerance [tolerance B] in Register table . Added a description in [14.8.2. Related register of Battery backup switchover function].

RX6110 SA B

This is a real-time clock module of the serial interface system that incorporates a 32.768 kHz crystal oscillator. The real-time clock function incorporates not only a calendar and clock counter for the year, month, day, day of the week, hour, minute, and second, but also a time alarm, interval timer, and time update interruption, among other features. By the battery backup switchover function and the interface power supply input pin, RX6110SA can support

various power supply circuitries. All of these many functions are implemented in a thin, compact SOP package, which makes it suitable for various kinds of small electronic devices.

2. Block Diagram

VDD VIO VBAT

/ IRQ1 / IRQ2

SPISEL

CLK/SCL DI / SDA DO/FOUT

CE/FOE

( 32.768 kHz )

OSC

ALARM,FOUT TIMER,FOUT

DIVIDER

POWER CONTROLLER

INTERRUPTS CONTROLLER

BUS INTERFACE CIRCUIT

USER RAM 128 bit

CLOCK

and

CALENDR

TIMER REGISTER

ALARM REGISTER

CONTROL

REGISTER and SYSTEM

CONTROLLER

Page − 1

ETM40E-03

RX6110 SA B

14.

13.

12.

11.

10.

9.

8.

3. Terminal description

3.1. Terminal connections

1. CLK/SCL

2. DI/SDA

3. DO/FOUT

4. CE/FOE

5. SPISEL

6. GND

7. /IRQ2

3.2. Pin Functions

Signal

name

I/O Function

SOP − 14pin

N.C.

N.C. /IRQ1 VIO VDD

VBAT

N.C.

SPISEL Input

CE/FOE Input

CLK/SCL Input This is a shift clock input pin for serial data transmission.

DI/SDA Input/Output

DO/FOUT Output

/ IRQ1 Output

/ IRQ2 Output

VDD Supply

VIO Supply

V

BAT

Supply

GND Supply

Interface selection pin. SPI is chosen at a "H" level (VIO voltage). I2C is chosen at a "L" level (GND voltage). Slave address [0110010]

SPI: Should be held high to allow access to the CPU.

Incorporates a pull-down resistor. I2C: It is an input pin for controlling the DO/FOUT output. When the frequency output from a DO/FOUT pin does not need, CE/FOE pin must be

connected to GND.

SPI: This is the data input pin for serial data transfer. I2C: This is the data input/output pin for serial data transfer.

SPI: This is the data output pin for serial data transfer. I2C: This is the C-MOS output pin with output control provided via the CE/FOE pin. (frequency selection: 32.768 kHz / 1024 Hz / 1Hz / Hi-z)

This pin outputs interrupt signals ("L" level) for alarm, timer, time update, and FOUT. This is an N-ch open-drain output. This pin can output even a backup mode.

This pin outputs interrupt signals ("L" level) for timer and FOUT. This is an C-MOS output. This pin becomes Hi-z in less than VDD=1.6V.

This is a power-supply pin. This is a interface power supply pin.

This is a pin to supply the voltage same as a host. This is a power supply pin for backup battery.

This is a pin to connect a large-capacity capacitor, a secondary battery. When the battery switchover function does not need, V

This pin is connected to a ground.

It can impress the voltage unlike VIO.

BAT

must be connected to VDD.

Note: Input pins are able to input up to 5.5V regardless of VIO applied voltage.

Note: Open drain pins are able to Pull-up to 5.5V regardless of VIO applied voltage.

Note:Connect a bypass capacitor rated at least 0.1µF between power supply pins and GND pin.

Page − 2

ETM40E-03

RX6110 SA B

SCL

SDA

VD3

FOE

32kHz

VDD

VD5

VBAT

OSC

DIV

I/O

EDLC

/IRQ2

: Timer,

FOUT

/IRQ1:Ararm,Timer,

FOUT

R

GND

VIO

CLK

DI

VD5

VD3

VIO

CE

SPISEL

DO

/IRQ1:Ararm,Timer,

FOUT

/I

RQ2

: Timer,

FOUT

VDD

VBAT

OSC

DIV

I/O

EDLC

internal

R

GND

VIO

VD3

C

battery

EDLC

or

R

C

4.

External connection example

4.1. Interface connection example

Ex.1. I2C-Bus

Ex.2 SPI-Bus

internal VDD

VDD Detector

LOGIC Area

Control

VIO

SPISEL

L S

4.2. Power supply connection example

EX1. The circuit which charges battery by high voltage

VIO

V

DD

VD5

Ex.2 A circuit to use with the same system power supply

VD3

VIO

VDD

Detector

Control

LOGIC

Area

LS

Ex.3 A circuit to connect a

primary cell

V

IO

BKSON =”0” BKSOFF =”1”

VDD

VD3

V

BAT

Ex.4 The circuit where backup is unnecessary

VIO

BKSON =”1” BKSOFF =”0”

VDD

V

BAT

R

or secondary

VD3

V

BAT

secondary

V

BAT

R primary

battery

Page − 3

ETM40E-03

RX6110 SA B

Unit : mm

#8

#1

R 6110

E

A123B

5.

External Dimensions / Marking Layout

5.1. External Dimensions

RX6110 SA B

• External dimensions • Recommended soldering pattern

#14

0.35

( SOP − 14 pin )

10.1

±

0.2

1.27 1.2

#7

5.0 7.4

0.05 Min.

3.2

0° - 10°

1.4

±

0.2

0.6

0.15

±

0.1

5.4

1.4

1.27

0.7

1.27 × 6 = 7.62

∗ The cylinder of the crystal oscillator can be seen in this area ( front ), but it has no affect on the performance of the device.

5.2. Marking Layout

RX6110 SA B

( SOP − 14 pin )

Type

Logo

Production lot

∗ Contents displayed indicate the general markings and display, but are not the standards for the fonts, sizes and positioning.

Page − 4

ETM40E-03

RX6110 SA B

to

7.

Recommended Operating Conditions

6. Absolute Maximum Ratings

Item Symbol

GND = 0 V

Condition Rating Unit

Supply voltage 1 V

DD

Between VDD and GND Supply voltage 2 VIO Between VIO and GND Supply voltage 3 V

BAT

Between V

BAT

Input voltage VIN SPISEL,CE/FOE,CLK/SCLK

Output voltage 1 V

OUT1

DO/FOUT, /IRQ2

DI/SDA, /IRQ1

Output voltage 2 V

Storage temperature T

OUT2

STG

A case of the Open drain

output pin setting

When stored separately,

without packaging

*Unless otherwise specified, GND = 0 V , Ta = −40 °C to +85 °C

Item Symbol

Operating supply voltage V

Clock supply voltage V

Main power supply

Low voltage detection

Backup power supply

Low voltage detection

ACC

CLK

VDD,V

V

DET+

V

DET-

V

LOW

V

Condition Min. Typ. Max. Unit

VDD, V

DD

pin, Rise 1.15 1.35 1.60 V

V

DD

pin, Fall 1.10 1.30 1.55 V

BAT

−0.3 ∼

and GND

−0.3 ∼

−55

IO

BAT

pin 1.1 3.0 5.5 V

1.6 3.0 5.5 V

+6.5 V +6.5 V +6.5 V

+6.5 V

VIO+0.3 V

+6.5 V

+125

pin 1.10 V

°C

Applied voltage when OFF V

Operating temperature

∗Minimum value of Clock supply voltage V supply voltage V

∗

The tolerance level of the power supply voltage that can connect with the pulling up in the state

ACC

.

PUP

DI/SDA, /IRQ1pin 5.5 * V

T

OPR

No condensation

CLK

is the timekeeping continuation lower limit value that initialized RX6110 in operating

−40

+25 +85

that VDD, VIO are power off.

8. Frequency Characteristics

Item Symbol

*Unless otherwise specified, GND = 0 V , Ta = −40 °C to +85 °C

Condition Min. Typ. Max. Unit

Output frequency fo 32.768

Frequency tolerance

Frequency/voltage

characteristics

Frequency/temperature

characteristics

Oscillation start time t

∆ f / f

f / V

Top

STA

Aging fa

∗1 )

The monthly error is equal to one minute. ( excluding offset )

Ta = +25 °C

VDD = 3.0 V

Ta = +25 °C VDD = 1.1 V

∼

5.5 V Ta = −20 °C ∼ +70 °C VDD = 3.0 V ; +25 °C reference Ta = ±0 °C ∼ +50 °C

VDD = 1.6 V Ta = −40 °C ∼ +85 °C

VDD = 1.6 V Ta = +25 °C , V

∼ ∼

5.5 V

BAT

first year

= 3.0 V ;

tolerance B: 5 ± 23

−2

−120

0.3 1.0 s

3.0 s

−5

( Typ. )

(∗1)

+2

+10

+5

°C

kHz

× 10−6

× 10−6 / V

× 10−6

/ year

Page − 5

ETM40E-03

RX6110 SA B

9. Electrical Characteristics

9.1. DC characteristics

9.1.1.

DC characteristics ( 1 )

Item Symbol

*

Unless otherwise specified, GND = 0 V , V

BAT=VDD

= 1.1 V ∼ 5.5 V , VIO= 1.6 V ∼ 5.5 V ,

Ta = −40°C ∼ +85°C

Condition Min. Typ. Max. Unit

Current consumption (1)

Current consumption (2)

Current consumption (4)

Input pins are "L" , V

I

DD1

DO/FOUT=OFF f

CLK

= 0 Hz, /IRQ1,2 = OFF

TSEL2=1, It include an OFF leak current

I

DD2

I

DD4

of SW between the power

V

supply (V

f

CLK

/IRQ1,2 = OFF, CE/FOE = VIO,

BAT-VDD

= 0 Hz,

DD

= 0 V

V

BAT

= 5 V

BAT

)

= 3 V

V

DD

= 5 V

V

IO

= 5 V

130 250

2.5 3.3

DO/FOUT : 32.768 kHz ON ,

Current consumption (5)

Current consumption (6)

I

DD5

I

DD6

CL = 0 pF Total current VDD and V

f

CLK

= 0 Hz,

/IRQ1,2 = OFF, CE/FOE = VIO,

IO

pin.

V

DD

= 3 V

V

IO

= 3 V

V

DD

= 5 V

V

IO

= 5 V

1.5 2.1

5.5 7.0

DO/FOUT : 32.768 kHz = ON ,

Current consumption (7)

High-level input voltage

Low-level input voltage

High-level output voltage

Low-level output voltage

Input leakage current

SW - ON * resistance

Input resistance(1) Input resistance(2)

I

CL = 15 pF

DD7

Total current VDD and V

IO

pin.

VIH SPISEL, CE/FOE pin

V

IHSPI

CLK/SCL, DI/SDA pin, SPISEL=VIO∗ 0.7 × V

V

IHI2C

CLK/SCL, DI/SDA pin, SPISEL=GND∗ 0.8 × V

VIL SPISEL, CE/FOE pin

V

ILSPI

CLK/SCL, DI/SDA pin, SPISEL=VIO

V

ILI2C

CLK/SCL, DI/SDA pin, SPISEL=GND

V

OH1

DO/FOUT pin

V

V V V

/IRQ2 pin

OH2

OL1

DO/FOUT pin /IRQ2 pin

OL2

VIO =3 V, IOL=0.5 mA GND GND +0.3

OL4

VIO=5 V, IOH=−1 mA VIO =3 V, IOH=−0.5 mA VIO =5 V, IOL=1 mA GND GND +0.5

V

BAT

=5 V, IOL=1 mA GND

/IRQ1 pin

V

OL5

V

OL6

DI/SDA pin

ILK

I

LKPD

IOZ

Input pins(excluding CE/FOE), VIN = VIO or GND

CE/FOE pin,VIN = GND −0.1 Output pins, V SW – ON resistance

R

SWON

between VDD and V

R

DWN1

Pull-down resistance

BAT

OUT

BAT

=3 V, IOL=1 mA GND GND +0.4

VIO ≥ 2 V, IOL=3.0 mA

= VIO or GND −0.1

VDD = 5V VDD = 3V

VDD = 5V

of CE/FOE pin.

R

DWN2

VIN = VIO

VDD = 3V

V

DD

V

IO

= 3 V

0.7 × V

3.0 4.0

IO IO IO

GND − 0.3 GND − 0.3 GND − 0.3

4.5 5.0

2.7 3.0

GND GND +0.4

−0.1

250 500

400 650

75 150 300

150 300 600

∗ When a DI/SDApin connects with a DO/FOUT pin, Maxmum value of High-level input voltage

IO

of the DI/SDA pin becomes the V

+0.3 V.

∗ The current consumption are target specifications. ∗ SW-ON resistance between VDD and V

BAT

of Backup switchover circuit

270

nA

µA

5.5 V

0.3 × V

IO

0.3 × V

IO

0.2 × V

IO

V V V

V

GND +0.25

V

0.1 µA

0.1

µA

Ω

kΩ

Page − 6

ETM40E-03

RX6110 SA B

t

SU ; STA

SDA

SCL

t

SU ; STA

9.2. AC characteristics

9.2.1. AC characteristics (1) I2C-Bus interface (SPISEL pin = “L”)

Item Symbol

SCL clock frequency Start condition setup time Start condition hold time Data setup time Data hold time Stop condition setup time Bus idle time between

start condition and stop condition Time when SCL = "L" Time when SCL = "H" Rise time for SCL and SDA Fall time for SCL and SDA

Allowable spike time on bus t

• Timing chart

Protocol

START

CONDITION

(S)

t

LOW

BIT 7

t

HIGH

MSB (A7)

*

Unless otherwise specified, GND = 0 V , VIO= 1.6 V ∼ 5.5 V , Ta = −40°C ∼ +85°C

Standard-Mode

(f

SCL

=100kHz)

Fast-Mode

(f

SCL

=400kHz)

Min. Max. Min. Max.

f

SCL

100 400 kHz

t

SU;STA

t

HD;STA

t

SU;DAT

t

HD;DAT

t

SU;STO

t

BUF

t

LOW

t

HIGH

t

r

t

f

SP

1 / f

SCL

4.7 0.6

4.0 0.6

250 100 ns

0 0 ns

4.0 0.6

4.7 1.3

4.0 0.6

1.0 0.3

0.3 0.3 50 50 ns

BIT 6

(A6)

BIT 0

LSB

(R/W)

ACK

(A)

STOP

CONDITION

(P)

START

CONDITION

(S)

Unit

µs µs

µs µs µs

(S)

t

HD ; STA

(P)

t

r

t

f

(A)

t

SU ; DAT

t

HD ; DAT

t

SP

t

SU ; STO

t

BUF

(S)

t

HD ; STA

Caution:When accessing this device, all communication from transmitting the start condition to transmitting the stop

condition after access should be completed within 0.95 seconds. If such communication requires 0.95 seconds or longer, the I2C bus interface is reset by the internal bus timeout function.

Page − 7

ETM40E-03

RX6110 SA B

•

CERF

9.2.1. AC characteristics (2) SPI-Bus interface (SPISEL pin = “H”)

Item Symbol Condition

CLK clock cycle CLK H pulse width CLK L pulse width CLK rise and fall time CLK setup time CE setup time CE hold time CE recovery time CE enable time Write data setup time Write data hold time Read data delay time DO output switching time

DO output disable time DI/DO conflict avoiding time

t

CLK t

WH

t

WL

t

RF

t

CLKS

t

CS

t

CH

t

CR

t

WCE

t

CERF

t

DS

t

DH

t

RD

t

RZ

t

ZZ

Caution: 1. Please refer to a standard of VIO = 1.8V ± 0.2V for VIO = 2.0 V ∼ 2.7 V.

2. Please refer to a standard of VIO = 3.0V ±10% for VIO = 3.3 V ∼ 4.5 V.

3. The access to this device must be finished within 0.95 seconds(CE enable time ). When access continues more than 0.95 seconds, second update fails.

Timing chart

*

Unless otherwise specified, GND = 0 V , V

DD

= 1.6 V ∼ 5.5 V , Ta = −40°C ∼ +85°C

VIO=1.8V ±0.2V VIO=3.0V ±10% VIO=5.0V ±10%

Min. Max. Min. Max. Min. Max.

1000 - 500 - 350 - ns

CL = 50 pF CL = 50 pF RL = 10 kΩ

450 - 250 - 175 - ns 450 - 250 - 175 - ns

- 100 - 100 - 50 ns 100 - 50 - 30 - ns 400 - 200 - 150 - ns 400 - 200 - 100 - ns 500 - 300 - 200 - ns

- 0.95 - 0.95 - 0.95

- 100 - 50 ns 200 - 100 - 50 - ns 200 - 100 - 50 - ns

0 400 - 200 - 150 ns 0 400 - 200 - 120 ns 0 - 0 - 0 - ns

t

WCE

Unit

s

C E

CLK

Read

D I

D O

CERF

t

CLKS

t

RF

t

RF

80 %

20 %

t

DS

t

DH

M 3

Hi-Z

M 2

A 0

t

ZZ

t

RD

D 7

CLK

t

WH

t

WL

D 6

t

CH

t

CR

t

RZ

D 0

CS

t

Wri te

D I

D O

M 3

Hi-Z

M 2

A 0

D 7

D 6

D 0

∗ If DI and DO pins are wired-OR connected to make it to 3 lines form, secure tzz to avoid bus conflict.

Page − 8

ETM40E-03

RX6110 SA B

V

9.2.2. AC characteristics (3)

Item Symbol

FOUT symmetry SYM 50% V

*

Unless otherwise specified, GND = 0 V , VIO= 1.6 V ∼ 5.5 V , Ta = −40°C ∼ +85°C

Condition Min. Typ. Max. Unit

IO Level

40 50 60 %

10. Matters that demand special attention on use

10.2. Instructions in the power on

10.2.1. Procedure of the power-on

VDD and VIO separate and can give different power supplies. In specifications range, the voltage relations(V

In the status that the voltage more than V an interface becomes unstable with the middle electric potential between GND-VDD, a through current will flow. VIO becomes unsettled, and an electric current of about 10uA flows when a through current flows by voltage relations of VDD and VIO. When the VIO voltage comes to stabilize, the through current of 10uA does not flow. If can permit this 10uA, VDD and VIO and V problem. By this through current, RTC does not destroy it and the malfunction does not occur.

If can not permit this 10uA, the following power-up is recommended. When the power-source supply of VDD is carried out earlier than VIO, please start VIO from a GND level not to become unstable.

DD

and VIO) are free.

DET

+ was supplied to main power-source VDD, if power-source VIO for

BAT

completely impress it by an independent timing and do not have any

DD

IO

≥ 0 ms

GND

≥ 0 ms

BAT

Backup mode

≥ 0 ms

Page − 9

ETM40E-03

RX6110 SA B

Power supply

VDD,V

tR1

Backup mode

tCL

V

-

V

DET

+

IF

Access is

tF

for using FOUT.

5.5V

10.2.2. Characteristic for the fluctuation of the power supply

∗tR1 is restrictions to validate power-on reset. When cannot keep this standard, power-on reset does not work normally. It is necessary to initial setting by the software command.

Repeated ON/OFF of the power supply in short term, the power-on reset becomes unstable. After power-OFF, keep a state of V

BAT

=GND more than 60 seconds to validate power-on reset.

When it is impossible, please perform initial setting by the software command.

VDD, V

BAT

DET

Access is impossible

DET+

CLK

V

BAT

VDD

tCU

1 - 100

40 - - ms

V

CLK

GND

Item Symbol

Power supply rise time access wait time

(Initial power on) access wait time ( Normal power on)

V

DET

+

Access is possible

Condition Min. Typ. Max. Unit

V

DD

tR1 tCL

tCU

rise time :GND – V

V

BAT

rise time: GND – V

V

DD

> V

DET+, VBAT

V

DD

> V

DET+, VBAT

> V

A power-on reset procedure by the software command

I2C-Bus interface (SPISEL pin = “L”)

1)

Power- on

2)

Wait: At least 40ms.

3)

Dummy read.

4)

Check VLF bit = “1”

5)

6)

7)

8)

9)

10)

11)

12)

Write 00[h] Write 00[h] Write 80[h] Write D3[h] Write 03[h] Write 02[h] Write 01[h] Wait:

Address:Reg-31[h] Address:Reg-1F[h] Address:Reg-1F[h] Address:Reg-60[h] Address:Reg-66[h] Address:Reg-6B[h] Address:Reg-6B[h] At least 2ms

∗1

∗2

∗3

END

∗1 Dummy read(I2C-Bus Only)

The location of the address is arbitrary.Do not check ACK/NACK from RX6110.

∗2 This command must be sent when executing the soft reset, even if the VLF=”0”.

(There is not influence even if it transmit at the time of VLF=”1”)

∗3 This wait time is necessary before transmitting the command for clearing VLF bit after software reset

command transmission.

∗4 SPI-Bus setting code (

Please refer to [14.12. Reading/Writing Data via the SPI Bus Interface ] for the details.)

Mode Bank1 Bank6

Read 9h Eh Write 1h 6h

A disappearance of the FOUT output when the voltage sharply went up and down.

For example, V

BAT

voltage is come and go between Main power and backup battery. The clock output from output pins and internal clock disappears then during several milli-seconds when a sharp voltage change happens. Please check that there is not a problem by this characteristic on your system.

An reference example of a power up and down timing without affect to FOUT.

Valid VDD voltage range

1.6 V tF

FOUT

SPI-Bus interface (SPISEL pin = “H”)

1)

Power- on

2)

Wait: At least 40ms.

3)

Check VLF bit = “1”

4)

Write 00[h]

5)

Write 00[h]

6)

Write 80[h]

7)

Write D3[h]

8)

Write 03[h]

9)

Write 02[h]

10)

Write 01[h]

11)

Wait: END

tR

FOUT

Address SPI:BANK3 Reg-1[h] Address SPI:BANK1 Reg-F[h] Address SPI:BANK1 Reg-F[h] Address SPI:BANK6 Reg-0[h] Address SPI:BANK6 Reg-6[h] Address SPI:BANK6 Reg-B[h] Address SPI:BANK6 Reg-B[h] At least 2ms

possible

µs / V

∗2

∗3

FOUT

Please make speed to descend of a power supply voltage loose than 4 ms/V.

tR

FOUT

Please make speed to rise of a power supply voltage loose than 4 ms/V.

Page − 10

ETM40E-03

RX6110 SA B

(

During power

-

on initialization or power

A source clock transmits in the circuit

,

Recovery from Backup

Because interface

d

isable

before

40 [ms], reading data

10.3.

Restrictions on Access Operations During Power-on Initialization and Recovery from Backup

• RTC-register operations are linked to the internal quartz oscillator's clock signal, so normal operation is not possible if there is no internal oscillation (= oscillation is stopped).

Therefore, we recommend that the initial setting to be set during power-on initialization or backup and restore operations (i.e., when the power supply voltage is recovered after oscillation has stopped due to a voltage drop, etc.) should be "first start internal oscillation, then wait for the oscillation stabilization time (see tSTA standard)

to elapse".

• Note the following caution points concerning access operations during power-on initialization or when restoring the

power supply voltage from backup mode (hereafter referred to as "switching to the operating voltage").

1) Before switching to the operating voltage, read the VLF-bit (which indicates the RTC error status).

2) Initialization is required when the value read from the VLF-bit is "VLF = 1 (error status)". Before initializing in response to this VLF = "1" result, we recommend first waiting for the internal oscillation

stabilization time (see the tSTA standard) to elapse.

Initialization is required when the status after reading a VLF-bit value of "1" is either of the following. (Status 1) During power-on initialization

(Status 2) When the clock setting is invalid, such as due to a voltage drop during backup

∗ Access timing during power-on initialization and when recovering the power supply voltage after a drop in the voltage used to maintain the clock

V

BAT

V

DD

supply voltage recovery after drop in clock maintenance voltage

Internal oscillation (illustration)

• Recovery from Backup

V

BAT

V

DD

Oscillation start voltage [v] V

DD

detection voltage V

Minimum voltage for clock maintenance V

tSTA [ s ]

Oscillation start time

(internal oscillation wait time)

40 [ ms ]

DET+

and timekeeping starts and becomes the normal operation.

Note: After 40 (ms) has elapsed, access is enabled.

V

DD

detect voltage V

DET

+

Minimum voltage for clock maintenance V

40 [ ms ]

After 40 [ms] progress, access is enabled.

are indefinite.

CLK

Min.

)

[ V ]

( Min. )

[ V ]

Page − 11

ETM40E-03

RX6110 SA B

× 10

-6

11. Reference information

11.1.

Reference Data

(1) Example of frequency and temperature characteristics

0

T

f

∆

-50

-100

Frequency

-150

-50 0 50 100

θT = +25 °C Typ.

α = -0.035 × 10-6 Typ.

Temperature [°C]

[ Finding the frequency stability ]

1.

Frequency and temperature characteristics can be

approximated using the following equations.

∆fT = α ( θT − θX ) 2



∆fT : Frequency deviation in any temperature



α [ 1 / °

( −0.035 ± 0.005 ) × 10



θT [ °C ]



θX [ °C ]

2

C

: Coefficient of secondary temperature

]

6

−

/ °C2

: Ultimate temperature ( +25

: Any temperature

± 5 °C )

2. To determine overall clock accuracy, add the frequency precision and voltage characteristics.

f/f = ∆f/fo + ∆f

∆



∆f/f : Clock accuracy (stable frequency)



f/fo : Frequency precision

∆



fT : Frequency deviation in any temperature.

∆



fV : Frequency deviation in any voltage.

∆

T

fV

+ ∆

in any temperature and voltage.

3. How to find the date difference

Date Difference = ∆f/f × 86400(Sec)

For example: ∆f/f = 11.574

∗

approximately 1 second/day.

10-6 is an error of

×

Page − 12

ETM40E-03

RX6110 SA B

11.2. Reference characteristic data (Typical)

Page − 13

ETM40E-03

RX6110 SA B

GND, beforehand.

Ts min : +150

Ts max : +200

　-6 ℃/

s Max

ｔｓ

12. Application notes

1) Notes on handling

This module uses a C-MOS IC to realize low power consumption. Carefully note the following cautions when handling.

(1) Static electricity

While this module has built-in circuitry designed to protect it against electrostatic discharge, the chip could still be damaged by a large discharge of static electricity. Containers used for packing and transport should be constructed of conductive materials. In addition, only soldering irons, measurement circuits, and other such devices which do not leak high voltage should be used with this module, which should also be grounded when such devices are being used.

(2) Noise

If a signal with excessive external noise is applied to the power supply or input pins, the device may malfunction or "latch up." In order to ensure stable operation, connect a filter capacitor (preferably ceramic) of greater that 0.1 µF as close as possible to the power supply pins. Also, avoid placing any device that generates high level of electronic noise near this module. * Do not connect signal lines to the shaded area in the figure shown in Fig. 1 and, if possible, embed this area in a GND land.

(3) Voltage levels of input pins

When the input pins are at the mid-level, this will cause increased current consumption and a reduced noise margin, and can impair the functioning of the device. Therefore, try as much as possible to apply the voltage level close to VIO or GND.

(4) Handling of unused pins

Since the input impedance of the input pins is extremely high, operating the device with these pins in the open circuit state can lead to unstable voltage level and malfunctions due to noise. Therefore, try as much as possible to apply the voltage level close to VIO or GND.

2) Notes on packaging

(1) Soldering heat resistance.

If the temperature within the package exceeds +260 °C, the characteristics of the crystal oscillator will be degraded and it may be damaged. The reflow conditions within our reflow profile is recommended. Therefore, always check the mounting temperature and time before mounting this device. Also, check again if the mounting conditions are later changed. * See Fig. 2 profile for our evaluation of Soldering heat resistance for reference.

(2) Mounting equipment

While this module can be used with general-purpose mounting equipment, the internal crystal oscillator may be damaged in some circumstances, depending on the equipment and conditions. Therefore, be sure to check this. In addition, if the mounting conditions are later changed, the same check should be performed again.

(3) Ultrasonic cleaning

Depending on the usage conditions, there is a possibility that the crystal oscillator will be damaged by resonance during ultrasonic cleaning. Since the conditions under which ultrasonic cleaning is carried out (the type of cleaner, power level, time, state of the inside of the cleaning vessel, etc.) vary widely, this device is not warranted against damage during ultrasonic cleaning.

(4) Mounting orientation

This device can be damaged if it is mounted in the wrong orientation. Always confirm the orientation of the device before mounting.

(5) Leakage between pins

Leakage between pins may occur if the power is turned on while the device has condensation or dirt on it. Make sure the device is dry and clean before supplying power to it.

(6) Installation of charged battery.

When a charged backup battery is installed by soldering, battery connection terminal of this device should connect to

Fig. 1 : Example GND Pattern

RX6110 SA

( SOP − 14pin )

∗ The shaded part (

pattern should be set without getting too close to a signal line

) indicates where a GND

Fig. 2 : Reference profile for our evaluation of Soldering heat resistance.

Temperature[℃]

300

TP : +260 ℃ Over

250

℃

200

℃

150

100

50

0

255 ℃

TL : +217 ℃

Time +25 ℃ to Peak

60 120 180 240 300 360 42 0 4 80 540 600 660 720 780

Ramp-up rate +3 ℃/s Max.

60 sto120 s

(+150 ℃ t o +20 0 ℃)

60 sto 150 s

tp: at least 30s

ｔＬ

(+2 17 ℃

Ramp-down rate

Time[s]

Page − 14

ETM40E-03

RX6110 SA B

13. Overview of Functions and Description of Registers

Note:

The initialization of the register is necessary about the unused function and Reserved bit

13.1. Overview of Functions

1) Clock functions

This function is used to set and read out month, day, hour, date, minute, second, and year (last two digits) data. Any (two-digit) year that is a multiple of 4 is treated as a leap year and calculated automatically as such until the year 2099. At the time of a communication start, the Clock & Calendar data are fixed (hold the carry operation), and it is automatically revised at the time of the communication end.

2) Fixed-cycle Timer Interrupt function

The fixed-cycle timer interrupt function generates an interrupt event periodically at any fixed cycle set between

244.14 µs and 65535 hours. When an interrupt event is generated, the /IRQ2 pin goes to low level ("L") and "1" is set to the TF bit to report

3) Long-Timer function

4) Alarm interrupt function

that an event has occurred.

It is able to use fixed cycle timer interrupt function as Long-Timer. This function selects the operation time with the main power supply or the operation time with the backup power supply and can automatically multiply it.

The alarm interrupt function generates interrupt events for alarm settings such as date, day, hour, and minute settings. When an interrupt event occurs, the AF bit value is set to "1" and the /IRQ1 pin goes to low level to indicate that an event has occurred.

5) Time Update Interrupt Function

The time update interrupt function generates interrupt events at one-second or one-minute intervals, according to the timing of the internal clock. When an interrupt event is generated, the /IRQ1 pin goes to low level ("L") and "1" is set to the UF bit to report that an event has occurred.

6) Voltage low detection function (VLF-bit)

This flag bit indicates the retained status of clock operations or internal data. Its value changes from "0" to "1"

7) Clock output function

when data loss occurs, such as due to a supply voltage drop.

A clock with the same frequency (32.768 kHz) as the built-in crystal resonator can be output from the DO/FOUT, /IRQ1, /IRQ2 pin.

8) User RAM

RAM register is read/write accessible for any data.

9) 1Hz Output function

/IRQ1 pin outputs the Fixed-cycle pulse of one period of =1s(Hi-z = 31.25ms)

Page − 15

ETM40E-03

RX6110 SA B



13.2. Register table

Address [h]

SPI

BANK 1

I2C

0 10 SEC 1 11 MIN 2 12 HOUR 3 13 WEEK 4 14 DAY 5 15 MONTH 6 16 YEAR 80 40 20 10 8 4 2 1

7 17

8 18 MIN Alarm AE 40 20 10 8 4 2 1 9 19 HOUR Alarm AE

A 1A

B 1B Timer Counter 0 128 64 32 16 8 4 2 1 C 1C Timer Counter 1 32768 16384 8192 4096 2048 1024 512 256 D 1D Extension Register FSEL1 FSEL0 USEL TE WADA TSEL2 TSEL1 TSEL0 E 1E Flag Register F 1F Control Register TEST STOP UIE TIE AIE TSTP TBKON TBKE

Address [h]

SPI

BANK 2

1

|

F

Address [h]

SPI

BANK 3

I2C

20

|

2F

I2C

Function bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

Reserved

(For tolerance B

setting data)

WEEK Alarm

DAY Alarm



-

1 0 1 0 1 0 0 0

AE



40 20 10 8 4 2 1 40 20 10 8 4 2 1



20 10 8 4 2 1

6 5 4 3 2 1 0

20 10 8 4 2 1



10 8 4 2 1

-

•

-

20 10 8 4 2 1

6 5 4 3 2 1 0

•



20 10 8 4 2 1

UF TF AF



VLF

Function bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

RAM

User Register

128 bit ( 16 word x 8 bit )

Function bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

-



0 30 Digital Tuning

1 31

2 32

Note

During the initial power-on (from 0 V) and if the value of the VLF bit is "1" when the VLF bit is read, be sure to

Reserved

(Setting data)

IRQ Control

(Setting data)

DTE



0



0

L7 L6 L5 L4 L3 L2 L1



0

-

0 0

IOCUT



EN

IOCUT

0

EN

TMREC

-

TMREC

BK

SON

BK

SON



0

BK

SOFF

BK

SOFF

TMPIN FOPIN1 FOPIN0 TMPIN FOPIN1 FOPIN0

BK

SMP1

BK

SMP1

BK

SMP0

BK

SMP0

initialize all registers before using them. When doing this, be careful to avoid setting incorrect data as the date or time, as timed operations cannot be guaranteed if incorrect date or time data has been set.

∗1.

∗2.

During the initial power-on (from 0 V), the power-on reset function sets "1" to the VLF bit. ∗ Since the value of other registers is undefined at this time, be sure to reset all registers before using them.

The TEST, bit are Epson test bits.

∗ Be sure to write "0" by initializing before using the clock module. Afterward, be sure to set "0" when writing. ∗3. The '  ' mark indicates a write-prohibited bit, which returns a "0" when read. ∗4. The ' • ' mark indicates a read/write-accessible RAM bit for any data. ∗5. The ' - ' mark has to write in specified fixed value in the case of initialization by all means. ∗6.

User Register is a free register.

Page − 16

ETM40E-03

RX6110 SA B

13.3. Description of registers

13.3.1. Clock and calender counter ( SPI:BANK1 Reg - 0[h] ∼ 6[h] / I2C Reg - 10[h] ∼ 16[h] )

This is counter registers from a second to year.

13.3.2. RAM

13.3.3. Alarm registers ( SPI:BANK1 Reg - 8[h] ∼ A[h] / I2C Reg - 18[h] ∼ 1A[h] )

13.3.4. Timer setting and Timer counter register ( SPI:BANK1 Reg - B[h] ∼ C[h] / I2C Reg - 1B[h] ∼ 1C[h] )

13.3.5. Function-related register 1 ( SPI:BANK1 Reg - D[h] ∼ F[h] / I2C Reg - 1D[h] ∼ 1F[h] )

∗ Please refer to [14.1 Clock calendar explanation ] for the details.

registers

This RAM register is read/write accessible for any data in the range from 00 h to FF h.

( SPI:BANK2 Reg - 0[h] ∼ F[h] / I2C Reg - 20[h] ∼ 2F[h] )

The alarm interrupt function is used, along with the AE, AF, and WADA bits, to set alarms for specified date, day, hour, and minute values.

∗ Please refer to [14.3. Alarm Interrupt Function ] for the details.

This register is used to set the default (preset) value for the counter. To use the fixed-cycle timer interrupt function,TE, TF, TIE, TSEL2,TSEL1, TSEL0,TBKON,TBKE,TMPIN bits are set and used. When the fixed-cycle timer interrupt function is not being used, the fixed-cycle timer control register can be used as a RAM register. In such cases, stop the fixed-cycle timer function by writing "0" to the TE and TIE bits.

∗ Please refer to [14.2. Fixed-cycle Timer Interrupt Function ] for the details.

1) FSEL1, FSEL0 bit

A combination of the FSEL1 and FSEL0 bits is used to select the frequency to be output. The choice is possible by a combination of FSEL-bits and CE/FOE-pin, select the frequency of clock output or inhibit the clock output.

∗ Please refer to [14.6. FOUT Function ] for the details.

2) USEL , UF, UIE bit

This bit is used to specify either "second update" or "minute update" as the update generation timing of the time update interrupt function.

∗ Please refer to [14.4. Update interrupt function] for the details.

3) TE, TF, TIE, TSEL2, TSEL1, TSEL0, TSTP,TBKON,TBKE bit

These bits are used to control operation of the fixed-cycle timer interrupt function.

4) WADA, AF, AIE bit

These bits are used to control operation of the alarm interrupt function.

5) TEST bit

Those bits are the manufacturer's test bit. Always leave this bit value as "0" except when testing.

6) VLF bit

This flag bit indicates the retained status of clock operations or internal data. Its value changes from "0" to "1" when data loss occurs, such as due to a supply voltage drop.

∗ Please refer to [14.5. Frequency stop detection function] for the details.

7) STOP bit

This bit is to stop a timekeeping operation. In the case of “STOP bit = 1", working is as follows a function . ∗ 1) All the update of timekeeping and the calendar operation stops.

With it, an update interrupt event does not occur at an alarm interrupt and the time.

∗ 2) The part of the fixed-cycle timer interrupt function stops.

A count stops the source clock setting of the timer in case of "64Hz, 1Hz, 1min, 1h".

∗ 3) Note 3: The effect of STOP bit to FOUT functions.

When STOP = "1", 32768Hz and 1024Hz output is possible.

But 1Hz output is disabled.

∗ 4) Switchover function cannot work in order that the VDD voltage drop detection stops even if a main

power supply falls.

Page − 17

ETM40E-03

RX6110 SA B

13.3.6. Function-related register 2 ( SPI:BANK2 Reg - 0[h] ∼ 2[h] / I2C Reg - 30[h] ∼ 32[h] )

1)BKSON,BKSOFF,BKSMP1,BKSMP0 bit

13.3.7.

SPI

BANK 1

These are the setting of the MOS switch between VDD - V low voltage detect circuit of VDD.

∗ Please refer to [14.8. Battery Backup switchover function] for the details.

2)FOPIN1,FOPIN0 bit

This bit selects destination (/IRQ1 or /IRQ2) of FOUT.

3)TMPIN bit

This bit selects destination (/IRQ1 or /IRQ2) of fixed-cycle timer function.

4)TMREC bit

The /IRQ1 pin outputs the Fixed-cycle pulse of one period of =1s(Hi-z = 31.25ms) by this bit.

5)IOCUTEN bit

This bit selects whether to stop interface and FOUT /IRQ2 in backup mode.

Reservedbit

The ' - ' mark has to write in specified fixed value in the case of initialization by all means. Writing data as follows.

Address [h]

I2C

*

Setting for this frequency tolerance B products.

Function bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

BAT

and setting of the operation mode of the

7

Address [h]

SPI

BANK 3

1 31

2 32

-

17

Reserved

(For tolerance B

setting data)

1 0 1 0 1 0 0 0

-

I2C

Function bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

Reserved

(Setting data)

IRQ Control

(Setting data)



0



0



0

-

0 0

IOCUT



EN

IOCUT

0

EN

TMREC

-

TMREC

BK

SON

BK

SON



0

SOFF

TMPIN FOPIN1

BK

SMP1

BK

SMP1

BK

SMP0

BK

SMP0

FOPIN0 FOPIN0

Page − 18

ETM40E-03

RX6110 SA B

14.

How to use

14.1. Clock calendar explanation

At the time of a communication start, the Clock & Calendar data are fixed (hold the carry operation), and it is automatically revised at the time of the communication end. Therefore it recommends that the access to a clock calendar has continuous access by the auto increment function.

Setting example: Sun, 29-Feb-88 17:39:45 (leap year)

Address [h]

SPI

BANK 1

0 10 SEC 1 11 MIN 2 12 HOUR 3 13 WEEK 4 14 DAY 5 15 MONTH 6 16 YEAR

∗ Note with caution that writing non-existent time data may interfere with normal operation of the clock counter.

14.1.1. Clock counter

I2C

1) [ SEC ] [ MIN ] register

These registers are 60-base BCD counters. These registers are incremented at the timing when carry is generated from a lower register. At the timing when the lower register changes from 59 to 00, carry is generated to the higher register and thus incremented. When writing is performed to [SEC] register, Internal-count-down-chain less than one second is cleared to 0.

2) [ HOUR ] register

This register is a 24-base BCD counter (24 hour format).These registers are incremented at the timing

14.1.2. Week counter

when carry is generated from a lower register.

The day (of the week) is indicated by 7 bits, bit 0 to bit 6. The day data values are counted as: Day 01h → Day 02h → Day 04h → Day 08h → Day 10h → Day 20h → Day

40h → Day 01h → Day 02h, etc. It is incremented when carry is generated from the HOUR register. This register does not generate carry to a higher register. Since this register is not connected with the YEAR, MONTH and DAY registers, it needs to be set again with the matching day of the week if any of the YEAR, MONTH or DAY registers have been changed.

The setting example of the week register value.

Day bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Data [h]

Sunday 0 0 0 0 0 0 0

Monday 0 0 0 0 0 0

Tuesday 0 0 0 0 0

Wednesday

Thursday 0 0 0

Friday 0 0

Saturday 0

14.1.3. Calendar counter

∗ Do not set "1" to more than one day at the same time.

1) [ DAY ], [ MONTH ] resister

The DAY register is a variable (between 28-base and 31-base) BCD counter that is influenced by the month and the leap year. The MONTH register is 12-base BCD counter. when carry is generated from a lower register.

Jan. Feb. Mar Apr. May June July Aug. Sep. Oct. Nov. Dec.

Days Normal year

Leap year 29

2) [ YEAR ] register

This register is a BCD counter for years 00 to 99. The leap year is automatically determined, which reflects in the DAY register.

Function bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

0 0 0 0 1 0 0 0 08 h

31

0 1 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 0 0 1 0 1 1 1 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 1 0 0 0 0 0 0 1 0 1 0 0 0 1 0 0 0

( 512Hz ∼ 1 Hz )

1

0 0 0 0 0 0 40 h

28

0 0 0 0 0 20 h

31 30 31 30 31 31 30 31 30 31

0 0 0 0 10 h

0 0 04 h

0 02 h

01 h

Page − 19

ETM40E-03

RX6110 SA B

14.2. Fixed-cycle Timer Interrupt Function

The fixed-cycle timer interrupt function generates an interrupt event periodically at any fixed cycle set between

244.14 µs and 65535 hours. This function can stop at one time and is available as an accumulative timer.

After the interrupt occurs, the /IRQ status is automatically cleared.

14.2.2. Related registers for function of fixed-cycle timer interrupt function

Address [h]

SPI

BANK 1

B 1B Timer Counter 0 C 1C Timer Counter 1 D 1D Extension Register FSEL1 FSEL0 USEL E 1E Flag Register

F 1F Control Register

Address [h]

SPI

BANK 3

2 32 IRQ Control 

I2C

Function bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

128 64 32 16 8 4 2 1

32768 16384 8192 4096 2048 1024



TEST

Function bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0



UF

STOP UIE

- -

∗ Before entering operation settings, we recommend first clearing the TE bit to "0" . ∗ When the fixed-cycle timer function is not being used, the fixed-cycle Timer Counter0,1 register can be used as a

RAM register. In such cases, stop the fixed-cycle timer function by writing "0" to the TE and TIE bits.

1) Down counter for fixed-cycle timer ( Timer Counter 1, 0 )

This register is used to set the default (preset) value for the counter. Any count value from 1 (0001 h) to 65535 (FFFFh) can be set.

Be sure to write "0" to the TE bit before writing the preset value.

∗ When TE=0, read out data of timer counter is default(Preset) value. And when TE=1, read out data of timer counter is just counting value. But, when access to timer counter data, counting value is not held. Therefore, for example, perform twice read access to obtain right data, and a way to adopt the case that two data accorded is necessary.

2) TSEL2, TSEL1, TESL0 bit

The combination of these three bits is used to set the countdown period (source clock) for this function.

TSEL2

( bit 2 )

TSEL1 ( bit 1 )

TSEL0

( bit 0 ) 0 0 0 0 0 1 0 1 0 0 1 1

Source clock

4096 Hz /Once per 244.14 µs 122 µs

64 Hz

1/60 Hz

/Once per 15.625 ms /Once per second

1 Hz

/Once per minute

1 0 0 1/3600 Hz /Once per hour

∗1) The /IRQ pin's auto reset time (tRTN) varies as shown above according to the source clock setting. ∗2) The first countdown shortens than a source clock.

When selected 4,096Hz / 64HZ / 1Hz as a source clock, one period of error occurs at the maximum. When selected1/60Hz / 1/3600Hz as a source clock, 1Hz of error occurs at the maximum.

The example of the error of the first countdown: A value to preset is 0004h

TE

TE TF

TIE

TMREC 

Auto reset time

WADA

AF

AIE

tRTN

7.813 ms

512 256

TSEL2 TSEL1 TSEL0



VLF

TSTP TBKON TBKE

TMPIN

TMPINTMPIN

FOPIN1 FOPIN0



Internal source clock

Cycle error

Down counter

TF

Designated cycle

3 2 1 4

4

TF Flag ”0”  “1”

Page − 20

ETM40E-03

RX6110 SA B

Inside counter block diagram

4096Hz

64Hz

1Hz 1/60Hz

1/3600Hz

1/60

1Hz

TSTP

1/60

source

clock

selector

TSTP

timer stop signal TSTP,TBKE,TBKON bit

Timer Counter 0 Timer Counter 1

Resister

∗ Cannot read the count value that is lower than a selected source clock.

3) TE bit ( Timer Enable )

4) TF bit ( Timer Flag )

When TE bit is "0", the default (preset) can be checked by reading this register.

TE

Write

This is a flag bit that retains the result when a fixed-cycle timer interrupt event is detected.

TF

Data Description

0

Stops fixed-cycle timer interrupt function.

∗ Clearing this bit to zero does not enable the /IRQ low output status to be cleared (to Hi-z).

Starts fixed-cycle timer interrupt function.

1

∗

The countdown that starts when the TE bit value changes from "0" to "1" always begins from the

preset value.

Data Description

Write

0

1 This bit is invalid after a "1" has been written to it. 0

Read

1

5) TIE bit ( Timer Interrupt Enable )

The TF bit is cleared to zero to prepare for the next status detection

∗ Clearing this bit to zero does not enable the /IRQ low output status to be cleared (to Hi-z).

−

Fixed-cycle timer interrupt events are detected. (Result is retained until this bit is cleared to zero.)

This bit is used to control output of interrupt signals from the /IRQ1 or /IRQ2 pin when a fixed-cycle timer interrupt event has occurred.

TIE

Data Description

1) When a fixed-cycle timer interrupt event occurs, an interrupt signal is not

0

Write

1

generated.

2) When a fixed-cycle timer interrupt event occurs, the interrupt signal is canceled (/IRQ status changes from low to Hi-z).

When a fixed-cycle timer interrupt event occurs, an interrupt signal is generated (/IRQ status changes from Hi-z to low).

6) TBKON, TBKE bit

This function selects the operation time with the main power supply or the operation time with the backup power supply. The count value is added.

operation

TBKE TBKON

Description

0 X This setting counts normal mode and backup mode.

Write

1

0

This setting counts it at time of normal mode(VDD ≥ V

1 This setting counts it at time of backup mode (V

DET-

BAT

operation)

)

Page − 21

ETM40E-03

RX6110 SA B

7) TSTP bit ( Timer Stop )

This bit is used to stop fixed-cycle timer count down.

operation

Write

STOP TBKE TSTP

0

1 Count stops.

1 X

Description

Writing a "0" to this bit cancels stop status (restarts timer count down). ∗The reopening value of the countdown is a stopping value

Setting of TSTP value becomes invalid, and the count does not stop even if set it in TSTP="1".

8) TMPIN bit

Select the destination of the timer interrupt output signal.(/IRQ1 or /IRQ2)

TMPIN

Write

14.2.3. Fixed-cycle timer start timing

SPI setting

Counting down of the fixed-cycle timer value starts at the rising edge of the CLK signal that occurs when the TE value is changed from "0" to "1".

CLK

DI

Internal timer

/ IRQ1,2 pin

I2C setting

Counting down of the fixed-cycle timer value starts at the rising edge of the SCL (ACK output) signal that occurs when the TE value is changed from "0" to "1".

1 X X

The count stops at the time of the setting of 64Hz, 1Hz,1/60Hz,1/3600Hz.

Data Description

0 /IRQ2 pin 1 /IRQ1 pin

TE

WADA

TSEL2

TSEL0

Count down

SC L

TE

SD A(Master󲷈

SDA (Slave󲷈

Internal timer

/ IRQ1,2 pin

WADA

TSEL2 TSEL1

TSEL0

ACK

Count down

Page − 22

ETM40E-03

RX6110 SA B

tRTN

tRTN tRTN

period period period

tRTN

period

14.2.4. Fixed-cycle timer interrupt interval (example)

The combination of the source clock settings and fixed-cycle timer countdown setting sets interrupt interval, as shown in the following examples.

Timer Counter

setting

1 ∼ 65535

0 1

•

410 100.10 ms 6.406 s 410 s 410 min 410 h

•

3840 0.9375 s 60.000 s 3840 s 3840 min 3840 h

•

4096 1.0000 s 64.000 s 4096 s 4096 min 4096 h

•

65535 15.9998 s 1023.984 s 65535 s 65535 min 65535 h

14.2.5. Diagram of fixed-cycle timer interrupt function

Fixed-cycle timer starts

Source clock

4096 Hz

TSEL2 = 0

TSEL1, 0 = 0, 0

64 Hz

TSEL2 = 0

TSEL1, 0 = 0, 1

1 Hz

TSEL2 = 0

TSEL1, 0 = 1, 0

1 / 60 Hz

TSEL2 = 0

TSEL1, 0 = 1, 1

− − − − −

244.14 µs

•

15.625 ms 1 s 1 min 1 h

•

Fixed-cycle timer stops

1 / 3600 Hz TSEL2 = 1

TSEL1, 0 = 0, 0

•

TE bit

TIE bit

Operation of fixed-cycle timer

" 1 " " 0 "

Hi - z

/ IRQ1,2 output

TF bit

Event occurs

internal operation

" L "

" 1 " " 0 "

Write operation

∗ After the interrupt event that occurs when the count value changes from 0001h to 0000h, the counter automatically

reloads the preset value and again starts to count down. (Repeated operation)

∗ The count down that starts when the TE bit value changes from "0" to "1" always begins from the preset value.

Page − 23

ETM40E-03

RX6110 SA B

14.3. Alarm Interrupt Function

14.3.1. Related registers for Alarm interrupt functions.

The alarm interrupt function generates interrupt events for alarm settings such as date, day, hour, and minute settings. When an interrupt event occurs, the AF bit value is set to "1" and the /IRQ1 pin goes to low level to indicate that an event has occurred. AF bit and IRQ output change after 1.46ms from alarm agreement at the maximum.

∗ /IRQ1=”L” output when occurs alarm interruption event is not cancelled automatically unless giving intentional cancellation and /IRQ1=”L” is maintained.

Address [h]

SPI

BANK 1

I2C

8 18 MIN Alarm 9 19 HOUR Alarm

A 1A

Function bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

40 20 10 8 4 2 1

•

6 5 4 3 2 1 0

•

WEEK Alarm

DAY Alarm

AE AE

AE

D 1D Extension Register FSEL1 FSEL0 USEL TE E 1E Flag Register



F 1F Control Register TEST STOP UIE TIE

∗ Before entering settings for operations, we recommend writing a "0" to the AIE bit to prevent hardware interrupts

from occurring inadvertently while entering settings.

∗ When the STOP bit value is "1" alarm interrupt events do not occur. ∗ When the alarm interrupt function is not being used, the Alarm registers can be used as a RAM register. In such

cases, be sure to write "0" to the AIE bit.

∗ Even if use alarm register as RAM register, inside of RTC is processed as alarm setting, therefore it is able to

prevent unintentional alarm occurrence (/IRQ1=”L” occurrence) due to unexpected agreement with writing data and timer condition by means of setting to AIE=”0”.

1) Alarm registers

In the WEEK alarm /Day alarm register (Reg - 0A), the setting selected via the WADA bit determines whether WEEK alarm data or DAY alarm data will be set. If WEEK has been selected via the WADA bit, multiple days can be set (such as Monday, Wednesday, Friday, Saturday).

∗1) The register that "1" was set to "AE" bit, doesn't compare alarm.

(Example) Write 80h (AE = "1") to the WEEK Alarm /DAY Alarm register (Reg - 0A): Only the hour and minute settings are used as alarm comparison targets. The week and date settings are not used as alarm comparison targets. As a result, alarm occurs if only an hour and minute accords with alarm data.

∗2) If all three AE bit values are "1" the week/date settings are ignored and an alarm interrupt event will

occur once per minute.

∗3) Even if the current date/time is used as the setting, the alarm will not occur until the counter counts up

2) WADA bit ( Week Alarm / Day Alarm Select )

to the current date/time (i.e., an alarm will occur next time, not immediately).

The alarm interrupt function uses either "Day" or "Week" as its target. The WADA bit is used to specify either WEEK or DAY as the target for alarm interrupt events.

WADA

Data Description

0 Sets WEEK as target of alarm function

Write

3) AF bit ( Alarm Flag )

1 Sets DAY as target of alarm function

When this flag bit value is already set to "0", occurrence of an alarm interrupt event changes it to "1". When this flag bit value is "1", its value is retained until a "0" is written to it.

AF

Write

Data Description

0

Clearing this bit to zero enables /IRQ1 low output to be canceled (/IRQ1 remains Hi-z) when an alarm interrupt event has occurred.

1 This bit is invalid after a "1" has been written to it.

20 10 8 4 2 1

WADA

UF TF

AIE

TSEL2 TSEL1 TSEL0



AF

TSTP TBKON TBKE

VLF



0

Read

1

−

Alarm interrupt events are detected. (Result is retained until this bit is cleared to zero.)

Page − 24

ETM40E-03

RX6110 SA B

Χ Χ Χ Χ Χ Χ Χ

" L "

4) AIE bit ( Alarm Interrupt Enable )

14.3.2. Examples of alarm settings

1) Example of alarm settings when "WEEK" has been specified (and WADA bit = "0")

2) Example of alarm settings when "Day" has been specified (and WADA bit = "1")

This bit is used to control output of interrupt signals from the /IRQ1 pin when an Alarm interrupt event has occurred.

AIE

Write

∗The AIE bit is only output control of the /IRQ terminal. It is necessary to clear an AF flag to cancel alarm.

Day is specified

WADA bit = "0"

Monday through Friday, at 7:00 AM ∗ Minute value is ignored Every Saturday and Sunday, for 30 minutes each hour ∗ Hour value is ignored

Every day, at 6:59 AM

Χ: Don't care

Day is specified

WADA bit = "1"

First of each month, at 7:00 AM ∗ Minute value is ignored 15th of each month, for 30 minutes each hour ∗ Hour value is ignored

Every day, at 6:59 PM 1

Χ: Don't care

Data Description

1) When an alarm interrupt event occurs, an interrupt signal is not

0

generated or is canceled (/IRQ1 status remains Hi-z).

2) When an alarm interrupt event occurs, the interrupt signal is canceled (/IRQ1 status changes from low to Hi-z).

1

When an alarm interrupt event occurs, an interrupt signal is generated (/IRQ1 status changes from Hi-z to low).

WEEK Alarm

bit

7

AE

6

5

4

3

S

F

T

2

W

T

bit

1

0

M

S

0 0 1 1 1 1 1 0 0 1 0 0 0 0 0 1 AE bit = 1 30 h

0 1 1 1 1 1 1 1 1

Day Alarm

bit

AE

bit

6

7

5

4

3

20

10

•

2

08

04

bit

1

0

02

01

0 0 0 0 0 0 0 1 0 0 0 1 0 1 0 1 AE bit = 1 30 h

HOUR

Alarm

07 h AE bit = 1

18 h 59 h

HOUR

Alarm

07 h AE bit = 1

18 h 59 h

MIN

Alarm

MIN

Alarm

14.3.3. Diagram of alarm interrupt function

AIE bit

/IRQ1 output

AF bit

Event occurs

I

nternal operation

Write operation

Page − 25

ETM40E-03

" 1 " " 0 "

Hi - z

" 1 " " 0 "

RX6110 SA B

tRTN

period period period period

" L "

14.4. Time Update Interrupt Function

The time update interrupt function generates interrupt events at one-second or one-minute intervals, according to the timing of the internal clock. This /IRQ1 status is automatically cleared (/IRQ1 status changes from low level to Hi-z 7.813ms after the interrupt occurs).

14.4.1. Related registers for time update interrupt functions.

Address [h]

SPI

BANK 1

I2C

Function bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

D 1D Extension Register FSEL1 FSEL0



E 1E Flag Register F 1F Control Register TEST STOP

∗ Before entering settings for operations, we recommend writing a "0" to the UIE bit to prevent hardware interrupts

from occurring inadvertently while entering settings.

∗ When the STOP bit value is "1" time update interrupt events do not occur. ∗ Although the time update interrupt function cannot be fully stopped, if "0" is written to the UIE bit, the time update

interrupt function can be prevented from changing the /IRQ1 pin status to low.

1) USEL bit ( Update Interrupt Select )

This bit is used to select "second" update or "minute" update as the timing for generation of time update interrupt events.

USEL Data Description

Selects "second update" (once per second) as the timing for generation of interrupt events

Selects "minute update" (once per minute) as the timing for generation of interrupt events

Write

2) UF bit ( Update Flag )

0

1

This flag bit value changes from "0" to "1" when a time update interrupt event occurs.

UF Data Description

Clearing this bit to zero enables /IRQ1 low output to be canceled (/IRQ1 remains Hi-z) when an time update interrupt event has occurred.

Write

0 1 This bit is invalid after a "1" has been written to it.

0

Read

3) UIE bit ( Update Interrupt Enable )

1

−

Time update interrupt events are detected. (The result is retained until this bit is cleared to zero.)

This bit selects whether to generate an interrupt signal or to not generate it.

UIE Data Description

1) Does not generate an interrupt signal. (/IRQ1 remains Hi-z)

Write / Read

0

2) Cancels interrupt signal triggered by time update interrupt event (/IRQ1 changes from low to Hi-z).

1 When an Update interrupt event occurs, an interrupt signal is generate.

14.4.2. Time update interrupt function diagram

UIE bit

USEL



UF

UIE

TE WADA TSEL2 TSEL1 TSEL0



TF AF

VLF

TIE AIE TSTP TBKON TBKE



" 1 " " 0 "

/ IRQ1 output

UF bit

Carry

I

nternal operation

Write operation

Hi - z

" 1 " " 0 "

Page − 26

ETM40E-03

RX6110 SA B

14.5.

Frequency stop detection function

This flag bit indicates the retained status of clock operations or internal data. Its value changes from "0" to "1" when data loss occurs, such as due to a supply voltage drop. Once this flag bit's value is "1", its value is retained until a "0" is written to it. This function cannot detect a instantaneous voltage drop . During the initial power-on (from 0 V) and if the value of the VLF bit is "1" when the VLF bit is read, be sure to initialize all registers before using them.

14.5.1. Related registers for Frequency stop detection function and Voltage low detection function.

Address [h]

SPI

BANK 1

I2C

Function bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

E 1E Flag Register

1) VLF bit

VLF

Data Description



UF TF AF



VLF



Write

0 The VLF is cleared to 0, and waiting for next low voltage detection. 1 It is impossible to write in 1 to VLF.

0 RTC register data are valid.

Read

1

RTC register data are invalid. Should be initialized of all register data. VLF is maintained till it is cleared by zero.

Page − 27

ETM40E-03

RX6110 SA B

14.6. 1Hz output function

It is a function to output a fixed cycle pulse of 1 second. The destination is a /IRQ1 pin. It is 31.25 ms for the Hi-z period.

14.6.1. Related registers for 1Hz output function.

Address [h]

SPI

BANK 3

2 32 IRQ Control 

I2C

Function bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

1) TMREC bit

TMREC

Data Description

- - TMREC



TMPIN

FOPIN1 FOPIN0

Write

0 Disable a 1Hz output function. 1 Enable a 1Hz output function.

14.7. FOUT function [clock output function]

The clock signal can be output via the DO/FOUT, /IRQ1, /IRQ2 pin.

When stopped the DO/FOUT, /IRQ2 pin output, the pin becomes the Hi-z.

14.7.1. FOUT control register.

Address [h]

SPI

BANK 1

I2C

Function bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

D 1D Extension Register

Address [h]

SPI

BANK 3

I2C

Function bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

2 32 IRQ Control

By a combination of FSEL1,FSEL0 and CE/FOE pin, an FOUT outputs 32768Hz and 1024Hz and 1Hz and can stop the output.

14.7.2. FOUT function table.

FOUT output pin layout

SPISELpin FOPIN1 FOPIN0

0 0 /IRQ2 OFF(Hi-z)

L

0 1 /IRQ1 Enable 1 X DO/FOUT OFF(Hi-z) 0 0 /IRQ2

H

0 1 /IRQ1 1 X Do not output

2) FSEL1,FSEL0 bit CE/FOE pin

I2C setting

FSEL1 FSEL0 output

0 0 OFF 0 1

" L "

1 0 1 1

" H "

Χ: don’t care

0 0

∗ At the time of the initial power-on, “0” is set to FSEL1, FSEL0. ∗ At initial power-on, in case of CE/FOE input is high, 32768Hz is selected automatically and output from

DO/FOUT pin by power-on-reset-function.(I

Note: The effect of STOP bit to FOUT functions.

When STOP = "1", 32768Hz output is possible.

But 1Hz and 1024Hz output is disabled.

FSEL1 FSEL0



-

Output pin Output on the backup

1 Hz Output 1024 Hz Output

32768 Hz Output Do not set it in /IRQ2

32768 Hz Output (DO/FOUT)

2

C setting)

USEL TE WADA TSEL2 TSEL1 TSEL0



TMREC

-

TMPIN

OFF(Hi-z)

Enable

FOPIN1 FOPIN0

−

Page − 28

ETM40E-03

RX6110 SA B

14.8.

Battery ba

14.8.1. Description of Battery backup switchover function

It consists of the power-source detector "V and built-in MOS switches located between the main power-source pin "VDD" and the backup power supply pin "V In turning off a MOS switch according to the supply-voltage detection result of V changes to VDD OFF ->V prevent a reverse-current (V At the time of a backup operation, "DO/FOUT and /IRQ2" pin becomes Hi-z, and signal of serial-data input pin does not transmit inside, so floating of a pin is permitted. To not use this function, it's necessary to fix VDD pin to V

14.8.2. R

elated register of

Address [h]

SPI

BANK 3

1 31

1) BKSON, BKSOFF bit

MOS-Switch is controlled by these bits.

By power-on reset at the time of initial power-on, the initial state is set to MOS switch ON,BKSON = BKSOFF = 0.

When implementing a backup battery first while the voltage VDD is not applied, the VDD voltage monitoring is operating and automatically MOS switch is turned OFF when the voltage of VDD is detected below V

2) BKSMP1, BKSMP0 bit

ckup switchover function

DET

BAT

".

BAT

(it shifts to a backup operation from a normal operation), it becomes possible to

BAT

->VDD) of an electric current.

Battery backup switchover function

I2C

operation

Write

The time of the VDD voltage monitoring and the turning off time of MOS-Switch for the VDD voltage

monitoring are set by these bits. When RTC monitor the voltage, MOS-Switch becomes OFF, and discharge of VDD is cut off from V

BKSMP1 BKSMP0 Monitor time Comment

0 0 2 ms Default 0 1 16 ms 1 0 128 ms 1 1 256 ms

Operation once in 1000ms.

Status of MOS-Switch (BKSON=1,BKSOFF=1)

Function bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

Reserved

BKSON BKSOFF

0 0 In the case of using a backup circuitry. Default 0 1 In the case of using a primary cell for a backup power.

1 0

1 1

BAT

, and

1s

discharges electricity.

VDD



In the case of using a primary cell for a backup power supply. It is necessary to fix VDD to V This set does not perform a power-down detection of VDD. Even if VDD becomes less than 1.6V, neither an interface and FOUT output is turned off automatically. In the case of using a backup circuitry. The consumption electric current at the time of a normal operation can be lessened more by set of BKSON=0 and BKSOFF=0.

" which detect the power down of the main power source "VDD",

DET

, when an drive power source

BAT

.



IOCUT



EN

Description

BAT

1s

BK

SON

BK

SOFF

BK

SMP1

BK

SMP0

.

DET-

.

Moniter time

VDD

V

BAT

Switch ON Switch OFF Switch ON

2ms ~ 256ms

VDD

V

BAT

VDD

V

BAT

VDD

BAT

Switch OFF

Page − 29

ETM40E-03

RX6110 SA B

MOS Switch

VDD

2ms timing pulse

256ms timing pulse

Detector

Flag

Control OFF / ON

Control ON / OFF

3) Operation list by register setting

BKSON BKSOFF BKSMP1 BKSMP0

0 0

1 1

0 1

1 0 1 1 Always OFF Always OFF Always ON

1) MOS-Switch when backup is always OFF.

2) Intermittent period: Normal mode Once /1s Backup mode Once / 31.25ms

4) Block diagram

Normal mode Backup mode

0 0 Always ON 0 1 Always ON 1 0 Always ON 1 1 Always ON 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1

Detector

1Hz Freq.

32Hz Freq.

16ms timing pulse

128ms timing pulse

Intermittent ON Intermittent ON Intermittent ON Intermittent ON Intermittent ON Intermittent ON Intermittent ON Intermittent ON

Latch

VDD monitor time

2ms

16ms 128ms 256ms

2ms

16ms 128ms 256ms

Switch & Detector

Controller

Intermittent ON

2ms

Intermittent ON

2ms

Intermittent ON

2ms

VDD

MOS-Switch

ON/OFF

Intermittent OFF

2ms

Intermittent OFF

16ms

Intermittent OFF

128ms

Intermittent OFF

256ms

Intermittent OFF

2ms

Intermittent OFF

16ms

Intermittent OFF

128ms

Intermittent OFF

256ms

Always OFF Always OFF Always OFF Always OFF

BKSMP1, BKSMP0

BKSON, BKSOFF

V

BAT

Internal VDD

5) IOCUTEN This bit selects whether to stop I/O (Interface, DO/FOUT, /IRQ2) in backup mode.

I/O automatically stop when it become to the backup mode by detecting(V

IOCUTEN

Write

Data Description

0 Do not control I/O. 1 Stop I/O at the time of backup mode.

DET-

) a VDD voltage drop.

When inside crystal oscillation stops, it is “0” cleared automatically. Therefore cannot set “1” to

IOCUTEN bit in a state of a non-oscillation just after initial power-on.

Page − 30

ETM40E-03

RX6110 SA B

14.9. Digital offset function

The clock precision can be set ahead or behind. The minimum resolution is 3.05×10

-6

and it can adjust it in the range of +192.3×10-6 from -195.3×10-6. When calculate compensation value from frequency accuracy or clock accuracy, please refer to accuracy after initialized a register by all means.

14.9.1.Digital offset register

Address [h]

SPI

BANK 3

0 30 Digital offset DTE L7

I2C

• When DTE=”1”, the digital offset function is enabled. When digital offset is enabled, the digital offset register digitally offsets the timekeeper according to the values set for the digital offset register by changing one second of the clock count every 10 seconds. The FOUT of 32.768kHz output does not change because the oscillation frequency of a built-in crystal does not change.

• When disabled digital offset, set to DTE = ”0”. A value of setting of L7 L1 is arbitrary.

• The relationship of the L7∼L1 bit and the digital offset value

When the L7 bit = “0”, it is a positive offset, when the L7 bit = “1”, it is a negative offset.

0 1 1 1 1 1 1 +192.26 0 1 1 1 1 1 0 +189.21

0 0 0 0 0 1 0 +6.10 0 0 0 0 0 0 1 +3.05 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 0

1 0 0 0 0 0 1 1 0 0 0 0 0 0

The offset value is shift value for internal real crystal frequency.

• How to calculate the offset value 1 ) When the offset value is positive:

L [7 ∼ 1] =[Offset Value]/ 3.05 However, decimals are discarded. Example calculation: When the offset value is +192 × 10-6

L[7 ∼ 1] = 192.26 / 3.05 = 63 (dec) = 0111111(bin) is set.

L[7 ∼ 1] = 128 – [Offset Value] / 3.05 However, decimals are discarded.

2 ) When the offset value is negative:

Example calculation: When the offset value is −158 × 10-6 L[7 ∼ 1] = 128 - ( 158 / 3.05 ) = 76(dec) = 1001100(bin) is set.

3 ) When calculate from accuracy of a clock When adjust 30 seconds in 30 days:

Example calculation: 30min. / 2592000s (30days) = 11.57 × 10-6

L[7 ∼ 1] = 11.57 / 3.05 = 4 (dec) However, decimals are discarded. = 0000100(bin) is set.

Negative offset L[7 ∼ 1] = 128 – ( 11.57 / 3.05 ) = 124 (dec) However, decimals are discarded. = 1111100(bin) is set.

Function bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

Positive offset

Digital offset bits

•

L6 L5 L4 L3 L2 L1

Offset value

( × 10

-6

) L7 L6 L5 L4 L3 L2 L1

•

±0.00

−3.05

−6.10

•

−192.26

−195.31

Page − 31

ETM40E-03

RX6110 SA B

14.9.2. About effect to the other function when used a digital offset function

Because this function adjusts an internal clock, this function affects a Fixed-cycle timer interrupt function

and a FOUT function.

1) FOUT funtion

• 1Hz setting: Once in 10 seconds, a 1Hz period fluctuates.

2) Fixed-cycle timer interrupt function

• 64Hz or 1Hz source clock setting: Once in 10 seconds, a period fluctuates. When the setting of the down counter is large, the influence looks

•

1024Hz setting: Once in 10 seconds, a 1024Hz period fluctuates.

∗There is a case that does not change depending on a set content.

•

32.768kHz is not affected.

small relative.

•

4kHz source clock is not affected.

Page − 32

ETM40E-03

RX6110 SA B

•

∗

−

SPI:Bank

1 / Reg − D[h]

•

14.10. Flow-chart

The following flow-chart is one instance. Mention for easy understanding takes precedence over others; therefore there are some inefficient cases for the actual processing. If you wish to take more efficient process, perform some processes at the same time or try to confirm and adjust some part where is no hindered from transposing of operation procedure. (Unnecessary processing may be included in mentioned items according to conditions to use. To get movement according to your expectation, please surely adjust according to conditions to use (use environment).

1) An example of the initialization

Ex.1 Initialize

Initialization

Setting the reserved bits I2C:Reg − 17[h], 30[h]∼ 32[h] SPI :Bank1/Reg − 7[h],

Bank3/Reg − 0[h]∼ 2[h]

I2C:Reg

I2C:Reg − 1E[h] SPI:Bank1 / Reg − E[h]

I2C:Reg − 1F[h] SPI:Bank1 / Reg − F[h]

I2C:

SPI:Bank1 / Reg − 0[h] ∼ 6[h]

Setting the Alarm function

Setting the Timer function

Setting the Update function

1D[h]

Setting the present time

Reg − 10[h] ∼ 16[h]

Reserved bits have to write in specified fixed value in the case

of initialization by all means.

Set TE bit to “0”.

• Set FSEL1, 0 bit optionally.

Clear VLF bit to “0”.

State of VLF=1 is held even if it 0 clear until oscillation start. When initialize it without waiting for an oscillation start, Clear VLF bit after an oscillation start. And initialize IOCUTEN bit after an oscillation start.

Surely set TEST bit to " 0 ".

• Set AIE, TIE, UIE bit to “0 " to prevent unprepared interruption output.

Set the present time.

∗ Setting the present time concerned, please refer to item of [ Clock and

calendar writing ] .

Set the Alarm interrupt function.

When the alarm interrupt function is not being used, the Alarm registers

can be used as a RAM register. In such cases, be sure to write "0" to the

AIE bit. Set the fixed-cycle Timer function.

When the fixed-cycle timer function is not being used, the Timer Counter

register can be used as a RAM register. In such cases,

stop the fixed-cycle timer function by writing "0" to the TE and TIE bits.

Set the Update interrupt function.

When initialization is finished, be sure to set STOP bit to “0”.

Next processing

Page − 33

ETM40E-03

RX6110 SA B

•

2) Method of initialization after starting of internal oscillation

The Initialize is possible in 40ms since Internal VDD becomes higher than VDET+.

Even in this case, after an internal oscillation begins, it is necessary to clear VLF= “0”.

Start

Power on

Wait

Dummy read

VLF=1 ?

VLF=”0” clear

Wait

VLF=0 ?

Software reset

Initialize

Wait time of 40ms is necessary at least

When power-on reset cannot satisfy a power supply condition

valid, execute a dummy read. (Only I2C use)

NO

Whether it is a return from the state of the backup is confirmed.

YES

When an internal oscillation starts, 0 writing of VLF is approved.

Please set waiting time depending on load of a system optionally

NO

YES

When power-on reset cannot satisfy a power supply condition valid, execute

a software reset. On the left [software reset], below a " Check VLF bit = “1”" of [P.10 A power-on reset procedure by the software command] procedure corresponds. After software reset, VLF bit is set “1” again.

Start-up complete

Page − 34

ETM40E-03

RX6110 SA B

•

[

•

∗

3) The setting of a clock and calendar

Set time

STOP ← " 1 "

Set STOP bit to “1” to prevent timer update in time setting.

Write time

STOP ← " 0 "

Next process

minute: second ] which is necessary to set (or reset).

4) The reading of a clock and calendar

Reading of the clock

Read clock

Next process

Write information of

In case of initialization, please initialize all data.

Cancel STOP bit to “0” and start (restart) timer movement.

Timer is started when set STOP bit to “0”.

It is able to set time even if not combined use of STOP bit. Please note that [ clock is started at the time of writing [second ] ] in case STOP bit is not used.

• Please complete access within 0.95 seconds The STOP bit holds "0".

(It causes the clock delay to set STOP bit to “1”)

• At the time of a communication start, the Clock & Calendar data are fixed (hold the carry operation), and it is automatically revised at the time of the communication end.

• The access to a clock calendar recommends to have access to continuation by a auto increment function.

year / month /date [day of the week] hour:

Page − 35

ETM40E-03

RX6110 SA B

−

•

∗

→ " 1 "

SPI:Bank

3/:

Reg-2

[h]

•

−

•

−

∼

5) The setting example of the fixed-cycle timer interrupt function

I2C:Reg-1D[h] SPI:Bank1/ Reg-D[h]

Timer setting

Clear TE bit to “0” to stop timer-interrupt function.

• The countdown period is fixed by the combination of the TSEL2, TSEL1, TSEL0 bit.

I2C:Reg-1E[h] SPI:Bank1/:Reg-E[h]

I2C:Reg-1F[h] SPI:Bank1/:Reg-F[h]

I2C:Reg-32[h]

I2C:Reg SPI:Bank1/:Reg-B[h], C[h]

1B[h, 1C[h]

Start count

Next process

Clear TF bit to “0” to cancel last timer interrupt output (/IRQ output).

Select and set /IRQ output

• Select a power supply condition of a count

Select output pin. (/IRQ1 or /IRQ2)

• Set initial value of down counter.

Set TE bit to "1" to start timer interrupt function.

When start timers interrupt function, please surely set/reset (*implement 2) initial value of down counter in advance.

1 Countdown is suspended with TSTP, " 0 "

performed again with TSTP, " 1 " → " 0 "

∗2 When you want to restart from a pre-set value, please set a TE bit to “1”

again after setting a TE bit to “0”.

6) The setting example of the Alarm interrupt function

I2C:Reg-1F[h] SPI:Bank1/ Reg-F[h]

Alarm setting

Set AIE bit to “0” to stop Alarm-interrupt function.

and countdown is

I2C:Reg SPI:Bank1/ Reg - 8[h] ∼ A[h]

18[h]

1A[h]

I2C:Reg-1D[h] SPI:Bakn1/ Reg-D[h]

I2C:Reg-1E[h] SPI:Bank1/ Reg-E[h]

I2C:Reg SPI:Bank1/ Reg-F[h]

1F[h]

Next process

Set alarm data.

Select week or day in WADA bit

Clear AF bit

• Select and set /IRQ1 output in AIE bit.

Page − 36

ETM40E-03

RX6110 SA B

14.11.

14.11.1. Overview of I2C-BUS

14.11.2. Data transfers

14.11.3. Starting and stopping I2C bus communications

Reading/Writing Data via the I2C Bus Interface

The I2C bus supports bi-directional communications via two signal lines: the SDA (data) line and SCL (clock) line. A combination of these two signals is used to transmit and receive communication start/stop signals, data transfer signals, acknowledge signals, and so on.

Both the SCL and SDA signals are held at high level whenever communications are not being performed.

The starting and stopping of communications is controlled at the rising edge or falling edge of SDA while SCL is at high level.

Data transfers are performed in 8-bit (1 byte) units once the START condition has occurred. There is no limit on the amount (bytes) of data that are transferred between the START condition and STOP condition. (However, the transfer time must be no longer than 0.95 seconds.)

SCL

START

condition

[ S ]

Repeated START(RESTART)

condition

[ Sr ]

STOP

condition

[ P ]

SDA

0.95

s ( Max. )

1) START condition, repeated START condition, and STOP condition (1) START condition

• The SDA level changes from high to low while SCL is at high level.

(2) STOP condition

• This condition regulates how communications on the I2C -BUS are terminated. The SDA level changes from low to high while SCL is at high level.

(3) Repeated START condition (RESTART condition)

• In some cases, the START condition occurs between a previous START condition and the next STOP condition, in which case the second START condition is distinguished as a RESTART condition. Since the required status is the same as for the START condition, the SDA level changes from high to low while SCL is at high level.

14.11.4. Slave address

The I2C-BUS devices do not have any chip select or chip enable pins. All I2C-BUS devices are memorized with a fixed unique number in it. The chip selection on the I2C-BUS is executed, when the interface starts, the master device send the required slave address to all devices on the I2C-BUS. The receiving device only reacts for interfacing, when the required slave address is agreed with its own slave address.

During in actual data transmission, the transmitted data contains the slave address and the data with R/W

(read/write) bit.

Slave address R/W

bit

bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

0 1 1 0 0 1 0 R/W

0 when write mode

1 when read mode

Page − 37

ETM40E-03

RX6110 SA B

Master

Slave

CPU, etc.

Master

Slave

14.11.5. System configuration

All ports connected to the I2C bus must be either open drain or open collector ports in order to enable AND connections to multiple devices.

SCL and SDA are both connected to the VIO line via a pull-up resistance. Consequently, SCL and SDA are both held at high level when the bus is released (when communication is not being performed).

V

IO

SDA

SCL

Transmitter/

Receiver

Transmitter/

Receiver

RX6110

Transmitter/

Receiver

Other I2C bus device

Transmitter/

Receiver

Any device that controls the data transmission and data reception is defined as a "Master". and any device that is controlled by a master device is defined as a “Slave”. The device transmitting data is defined as a “Transmitter” and the device receiving data is defined as a receiver”

In the case of this RTC module, controllers such as a CPU are defined as master devices and the RTC module is defined as a slave device. When a device is used for both transmitting and receiving data, it is defined as either a transmitter or receiver depending on these conditions.

Page − 38

ETM40E-03

RX6110 SA B

(1)

(3)

(4)

(5)

(8)

(9)

(6)

(7) (2)

(1)

(3)

(4)

(6)

(5)

(8)

(9)

(10)

(11)

(13)

(12)

(7)

(2)

(1)

(3)

(4)

(5)

(7)

(6)

(8)

(2)

14.11.6. I2C bus protocol

In the following sequence descriptions, it is assumed that the CPU is the master and the RX6110 is the slave.

1) Address specification write sequence Since the RX6110 includes an address auto increment function, once the initial address has been specified, the

RX6110 increments (by one byte) the receive address each time data is transferred.

(1) CPU transfers start condition [S]. (2) CPU transmits the RX6110's slave address with the R/W bit set to write mode. (3) Check for ACK signal from RX6110. (4) CPU transmits write address to RX6110. (5) Check for ACK signal from RX6110. (6) CPU transfers write data to the address specified at (4) above. (7) Check for ACK signal from RX6110. (8) Repeat (6) and (7) if necessary. Addresses are automatically incremented. (9) CPU transfers stop condition [P].

S

Slave address

2) Address specification read sequence

3) Read sequence when address is not specified

After using write mode to write the address to be read, set read mode to read the actual data.

(1) CPU transfers start condition [S]. (2) CPU transmits the RX6110's slave address with the R/W bit set to write mode. (3) Check for ACK signal from RX6110. (4) CPU transfers address for reading from RX6110. (5) Check for ACK signal from RX6110. (6) CPU transfers RESTART condition [Sr] (in which case, CPU does not transfer a STOP condition [P]). (7) CPU transfers RX6110's slave address with the R/W bit set to read mode. (8) Check for ACK signal from RX6110 (from this point on, the CPU is the receiver and the RX6110 is the transmitter). (9) Data from address specified at (4) above is output by the RX6110. (10) CPU transfers ACK signal to RX6110. (11) Repeat (9) and (10) if necessary. Read addresses are automatically incremented. (12) CPU transfers ACK signal for "1". (13) CPU transfers stop condition [P].

S

Slave address

Once read mode has been initially set, data can be read immediately. In such cases, the address for each read operation is the previously accessed address + 1.

(1) CPU transfers start condition [S]. (2) CPU transmits the RX6110's slave address with the R/W bit set to read mode. (3) Check for ACK signal from RX6110 (from this point on, the CPU is the receiver and the RX6110 is the transmitter). (4) Data is output from the RX6110 to the address following the end of the previously accessed address. (5) CPU transfers ACK signal to RX6110. (6) Repeat (4) and (5) if necessary. Read addresses are automatically incremented in the RX6110. (7) CPU transfers ACK signal for "1". (8) CPU transfers stop condition [P].

S

Slave address

Address

Sr

0

ACK from RX6110

Data

0

ACK signal from RX6110

0

R/W

0

R/W

Address

1

0

R/W ACK from RX6110

Data

Slave address

ACK from CPU

0

1

0

Data

R/W

1

0

Data

P

Data

0

P

Data

ACK from CPU

P

1

Page − 39

ETM40E-03

RX6110 SA B

0 1 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0

1 A3 A2 A1 A0 D7 D6 D5 D1 D0 D7 D6

D1 D0 0

1 A3 A2 A1 A0

D1 D0 D7 D6

D1 D0

14.12.

Reading/Writing Data via the SPI Bus Interface

For both read and write, first set up chip condition (internally CE="H") to CE="H" , then specify the 4-bits address, and finally read or write in 8-bits units. Both read and write use MSB-first. In continuous operation, objected address is auto incremented. Auto incrementing of the address is cyclic, so address "F" is followed by address "0".

14.12.1 Write / Read and Bank Select

R/W and Register bank are specified by the four bits mode setting code.

Mode Bank1 Bank2

Read 9 h A h B h Eh Write 1 h 2 h 3 h 6h

∗Bank5 and Bank6 are for software reset

14.12.2 Write of data

1) One-shot writing

C E

Bank3

Bank6

CLK

D I

D O

2 ) Continuous writing

C E

CLK

D I

D O

*When writing data, the data needs to be entered in 8-bits units. If the input of data in 8-bits unit is not completed before CE input falls, the 8-bits data will not be written properly at the time CE input falls.

14.12.3 Read of data

1) One-shot reading

C E

1 2 3 4 5 6 7 8 9 1 0 11 12 13 14 15 16

0

Address N

Hi-Z

1 2 3 4 5 6 7 8 9 10 11

0

Address N

Hi-Z

Data N

Data N+1

D1 D0 D7 D6

Data N+m

CLK

D I

D O

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

1 0 0 1 A3 A2 A1 A0

Mode

Hi-Z

Address N

D7 D6 D5 D4 D3 D2 D1 D0

Data N

2 ) Continuous reading

C E

CLK

D I

D O

1 2 3 4 5 6 7 8 9 10 11

1 0

0

Mode

Hi-Z

Address N

D7 D6 D5

Data N

D1 D0 D7 D6

Data N+1

Data N+m

Page − 40

ETM40E-03

Application Manual

AMERICA

Epson Electronics America, Inc.

Headquarter

Chicago Office 1827 Walden Office Square. Suite 520 Schaumburg, IL 60173, U.S.A. Phone: (1)847-925-8350 Fax: (1)847 925-8965

El Segundo Office 1960 E. Grand Ave., 2nd Floor, El Segundo, CA 90245, U.S.A.

214 Devcon Drive, San Jose, CA 95112, U.S.A.

Phone: (1)800-228-3964 FAX :(1)408-922-0238

http://www.eea.epson.com

Phone: (1)800-249-7730 (Toll free) : (1)310-955-5300 (Main) Fax: (1)310-955-5400

EUROPE

Epson Europe Electronics GmbH

Headquarter Riesstrasse 15, 80992 Munich, Germany Phone: (49)-(0)89-14005-0 Fax: (49)-(0)89-14005-110 http://www.epson-electronics.de

ASIA

Epson (China) Co., Ltd.

Headquarter 4F, Tower 1 of China Central Place, 81 Jianguo Street, Chaoyang District, Beijing, 100025 China Phone: (86) 10-8522-1199 Fax: (86) 10-8522-1125 http://www.epson.com.cn/ed/ Shanghai Branch High-Tech Building,900 Yishan Road Shanghai 200233,China Phone: (86) 21-5423-5577 Fax: (86) 21-5423-4677 Shenzhen Branch 12/F, Dawning Mansion,#12 Keji South Road, Hi-Tech Park,Shenzhen, China Phone: (86) 755-2699-3828 Fax: (86) 755-2699-3838

Epson Hong Kong Ltd.

Unit 715-723 7/F Trade Square, 681 Cheung Sha Wan Road, Kowloon, Hong Kong Phone: (86) 755-2699-3828 (Shenzhen Branch) Fax: (86) 755-2699-3838 (Shenzhen Branch) http://www.epson.com.hk

Epson Taiwan Technology & Trading Ltd.

14F, No.7, Song Ren Road, Taipei 110 Phone: (886) 2-8786-6688 Fax: (886)2-8786-6660 http://www.epson.com.tw/ElectronicComponent

Epson Singapore Pte. Ltd.

No 1 HarbourFront Place, #03-02 HarbourFront Tower One, Singapore 098633. Phone: (65)- 6586-5500 Fax: (65) 6271-3182 http://www.epson.com.sg/epson_singapore/electronic_devices/electronic_devices.page

Seiko Epson Corporation Korea Office

19F (63Bldg.,Yoido-dong) 50, 63-ro, Yeongdeungpo-gu, Seoul, 150-763, Korea Phone: (82) 2-784-6027 Fax: (82) 2-767-3677 http://www.epson-device.co.kr

Electronic devices information on WWW server

http://www5.epsondevice.com/en/