Emerson ATCA-9305 User Manual

User’s Manual
from Emerson Network Power
Embedded Computing

™

ATCA-9305: ATCA® Blade with Dual Cavium Processors

April 2009

The information in this manual has been checked and is believed to be accurate and reliable.
HOWEVER, NO RESPONSIBILITY IS ASSUMED BY EMERSON NETWORK POWER, EMBEDDED
COMPUTING FOR ITS USE OR FOR ANY INACCURACIES. Specifications are subject to change
without notice. EMERSON DOES NOT ASSUME ANY LIABILITY ARISING OUT OF USE OR
OTHER APPLICATION OF ANY PRODUCT, CIRCUIT, OR PROGRAM DESCRIBED HEREIN. This
document does not convey any license under Emerson patents or the rights of others.

Emerson. Consider It Solved is a trademark, and Business-Critical Continuity, Emerson Net­work Power, and the Emerson Network Power logo are trademarks and service marks of
Emerson Network Power, Embedded Computing, Inc.
© 2009 Emerson Network Power, Embedded Computing, Inc.

Revision Level: Principal Changes: Date:

10009109-00 Original release January 2009
10009109-01 Added “GR-1089-CORE Standard” on page -i

Updated “Product Certification” on page 1-4

Copyright © 2009 Emerson Network Power, Embedded Computing, Inc. All rights reserved.

April 2009

Regulatory Agency Warnings & Notices

!

!

!

The Emerson ATCA-9305 meets the requirements set forth by the Federal Communications
Commission (FCC) in Title 47 of the Code of Federal Regulations. The following information
is provided as required by this agency.

This device complies with part 15 of the FCC Rules. Operation is subject to the following two
conditions: (1) This device may not cause harmful interference, and (2) this device must
accept any interference received, including interference that may cause undesired opera­tion.

FCC RULES AND REGULATIONS — PART 15

This equipment has been tested and found to comply with the limits for a Class A digital
device, pursuant to part 15 of the FCC Rules. These limits are designed to provide reason­able protection against harmful interference when the equipment is operated in a commer­cial environment. This equipment generates, uses and can radiate radio frequency energy
and, if not installed and used in accordance with the instructions, may cause harmful inter­ference to radio communications. Operation of this equipment in a residential area is likely
to cause harmful interference, in which case the user will be required to correct the interfer­ence at his own expense.

Caution: Making changes or modifications to the ATCA-9305 hardware without the explicit consent

of Emerson Network Power could invalidate the user’s authority to operate this equipment.

EMC COMPLIANCE

The electromagnetic compatibility (EMC) tests used an ATCA-9305 model that includes a
front panel assembly from Emerson Network Power.

Caution: For applications where the ATCA-9305 is provided without a front panel, or where the front

panel has been removed, your system chassis/enclosure must provide the required
electromagnetic interference (EMI) shielding to maintain EMC compliance.

GR-1089-CORE STANDARD

Caution: WARNING: The intra-building port(s) of the equipment or subassembly is suitable for

connection to intrabuilding or unexposed wiring or cabling only. The intra-building port(s)
of the equipment or subassembly MUST NOT be metallically connected to interfaces that
connect to the OSP or its wiring. These interfaces are designed for use as intra-building
interfaces only (Type 2 or Type 4 ports as described in GR-1089-CORE, Issue 4) and require
isolation from the exposed OSP cabling. The addition of Primary Protectors is not sufficient
protection in order to connect these interfaces metallically to OSP wiring.

10009109-01 ATCA- 9305 User’s Manual

i

Regulatory Agency Warnings & Notices (continued)

EC Declaration of Conformity

According to EN 45014:1998

Manufacturer’s Name: Emerson Network Power

Embedded Computing

Manufacturer’s Address: 8310 Excelsior Drive

Madison, Wisconsin 53717

Declares that the following product, in accordance with the requirements of 2004/108/EEC, EMC
Directive and 1999/5/EC, RTTE Directive and their amending directives,

Product: ATCA Blade

Model Name/Number: ATCA-9305/10009986-xx

has been designed and manufactured to the following specifications:

EN55022:1998 Information Technology Equipment, Radio disturbance characteristics, Limits and
methods of measurement

EN55024:1998 Information Technology Equipment, Immunity characteristics, Limits and methods
of measurement

EN300386 V.1.3.2:2003-5 Electromagnetic compatibility and radio spectrum matters (ERM);
Telecommunication network equipment; EMC requirements

As manufacturer we hereby declare that the product named above has been designed to comply
with the relevant sections of the above referenced specifications. This product complies with the
essential health and safety requirements of the EMC Directive and RTTE Directive. We have an inter­nal production control system that ensures compliance between the manufactured products and
the technical documentation.

Issue date: April 7, 2009

Bill Fleury
Compliance Engineer

ii

ATCA-9305 User’s Manual 10009109-01

Regulatory Agency Warnings & Notices (continued)

10009109-01 ATCA- 9305 User’s Manual

iii

Regulatory Agency Warnings & Notices (continued)

iv

ATCA-9305 User’s Manual 10009109-01

Contents

1Overview

Components and Features . . . . . . . . . . . 1-1

Functional Overview . . . . . . . . . . . . . . . . 1-3

Additional Information . . . . . . . . . . . . . . 1-4

Product Certification . . . . . . . . . . . . . 1-4

RoHS Compliance. . . . . . . . . . . . . . . . 1-5

Terminology and Notation. . . . . . . .1-6

Technical References. . . . . . . . . . . . .1-6

2Setup

Electrostatic Discharge . . . . . . . . . . . . . . 2-1

ATCA-9305 Circuit Board . . . . . . . . . . . . 2-1

Connectors . . . . . . . . . . . . . . . . . . . . .2-7

Configuration Header . . . . . . . . . . . .2-8

ATCA-9305 Setup. . . . . . . . . . . . . . . . . . . 2-8

Power Requirements. . . . . . . . . . . . .2-9

Environmental Considerations . . . . 2-9

Hot Swap . . . . . . . . . . . . . . . . . . . . . .2-10

Insert a board: . . . . . . . . . 2-11

Remove a board: . . . . . . . 2-11

Troubleshooting. . . . . . . . . . . . . . . . . . . 2-11

Technical Support . . . . . . . . . . . . . .2-11

Product Repair . . . . . . . . . . . . . . . . .2-12

Comments and Suggestions . . . . .2-13

3 Cavium Processor Complex

Cavium CN5860 Processor . . . . . . . . . . . 3-1

Cavium Memory Map . . . . . . . . . . . . 3-2

PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2

CN5860 Boot Over PCI . . . . . . . . . . . 3-3

Cavium Reset . . . . . . . . . . . . . . . . . . . 3-4

Cavium Ethernet. . . . . . . . . . . . . . . . . . . . 3-5

Cavium Monitor . . . . . . . . . . . . . . . . . . . . 3-6

Start-up Display . . . . . . . . . . . . . . . . .3-6

Power-up/Reset Sequence . . . . . . . . 3-6

Diagnostic Tests During Power-up and

Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7

POST Diagnostic Results . . . . . . 3-7

Cavium Environment Variables . . . . 3-8

Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9

DDR2 SDRAM . . . . . . . . . . . . . . . . . . . 3-9

RLDRAM . . . . . . . . . . . . . . . . . . . . . . . .3-9

I2C EEPROM. . . . . . . . . . . . . . . . . . . . . 3-9

Flash, 512 KB x 8. . . . . . . . . . . . . . . .3-10

Flash, 4 MB x 16 . . . . . . . . . . . . . . . . 3-10

StratixGX Interconnect . . . . . . . . . . . . . 3-10

PLD Registers . . . . . . . . . . . . . . . . . . 3-10

Data Registers . . . . . . . . . . . . . 3-10

Address Registers . . . . . . . . . . 3-12

Control Register. . . . . . . . . . . . 3-12

Version Register. . . . . . . . . . . . 3-13

Scratch Register. . . . . . . . . . . . 3-13

Headers and Connectors. . . . . . . . . . . . 3-14

COP/JTAG Headers . . . . . . . . . . . . . 3-14

Console Serial Ports (optional) . . . 3-15

4 Management Complex

MPC8548 Processor. . . . . . . . . . . . . . . . . .4-2

MPC8548 Memory Map . . . . . . . . . . 4-2

Chip Selects . . . . . . . . . . . . . . . . . . . . 4-5

Reset Diagram . . . . . . . . . . . . . . . . . . 4-6

Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-7

SDRAM. . . . . . . . . . . . . . . . . . . . . . . . . 4-7

Flash. . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7

512 KB x 8 (optional). . . . . . . . . 4-7

4M x 16 . . . . . . . . . . . . . . . . . . . . 4-7

1 GB x 16 . . . . . . . . . . . . . . . . . . . 4-8

64 MB x 16. . . . . . . . . . . . . . . . . . 4-8

PCI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-8

PCI Express . . . . . . . . . . . . . . . . . . . . . 4-8

I2C Interface . . . . . . . . . . . . . . . . . . . . . . . .4-9

Management Processor Header and Serial

Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-9

JTAG/COP Interface (optional) . . . . 4-9

Serial Debug Port. . . . . . . . . . . . . . . 4-10

5 Management Processor

CPLD

MPC8548 PLD Register Summary . . . . . .5-1

Product ID. . . . . . . . . . . . . . . . . . . . . . 5-2

Hardware Version . . . . . . . . . . . . . . . 5-2

PLD Version. . . . . . . . . . . . . . . . . . . . . 5-3

PLL Reset Configuration . . . . . . . . . . 5-3

Hardware Configuration 0 . . . . . . . . 5-3

Jumper Settings . . . . . . . . . . . . . . . . . 5-4

LED . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4

Reset Event . . . . . . . . . . . . . . . . . . . . . 5-5

Reset Command 1. . . . . . . . . . . . . . . 5-5

Reset Command 2. . . . . . . . . . . . . . . 5-6

Reset Command 3. . . . . . . . . . . . . . . 5-6

10009109-01 ATCA- 9305 User’s Manual

v

Contents (continued)

Reset Command 4 . . . . . . . . . . . . . . . 5-7

Reset Command 5 . . . . . . . . . . . . . . . 5-7

Reset Command Sticky #1 . . . . . . . .5-7

Reset Command Sticky #2 . . . . . . . .5-8

Boot Device Redirection . . . . . . . . . . 5-8

Miscellaneous Control. . . . . . . . . . . . 5-9

Low Frequency Timer 1 and 2 . . . . . 5-9

RTM GPIO State . . . . . . . . . . . . . . . .5-10

RTM GPIO Control . . . . . . . . . . . . . .5-10

RTM Status . . . . . . . . . . . . . . . . . . . . 5-10

Cavium 1 C_MUL Clock Divisor Control

5-11

Cavium 2 C_MUL Clock Divisor Control

5-11

JTAG . . . . . . . . . . . . . . . . . . . . . . . . . .5-12

Cavium GPIO Control . . . . . . . . . . .5-12

Cavium GPIO Data Out . . . . . . . . . .5-13

Cavium GPIO Data In . . . . . . . . . . . .5-13

IPMP/IPMC GPIO Control . . . . . . . .5-14

LPC Bus Control . . . . . . . . . . . . . . . . 5-14

LPC Data. . . . . . . . . . . . . . . . . . . . . . .5-14

Serial IRQ Interrupt 1 . . . . . . . . . . .5-15

Serial IRQ Interrupt 2 . . . . . . . . . . .5-15

6 Ethernet Interface

Broadcom BCM56802 Switch . . . . . . . . .6-1

Ethernet Switching. . . . . . . . . . . . . . . . . . .6-1

Ethernet Transceivers . . . . . . . . . . . . 6-2

Ethernet Switch Ports . . . . . . . . . . . .6-2

VLAN Setup . . . . . . . . . . . . . . . . . . . . . 6-3

MPC8548 Management Processor Ethernet

Address. . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-3

Front Panel Ethernet Ports . . . . . . . . 6-4

7 System Management

IPMC Overview . . . . . . . . . . . . . . . . . . . . . .7-1

IPMI Messaging. . . . . . . . . . . . . . . . . . . . . .7-2

IPMI Completion Codes . . . . . . . . . . 7-4

IPMB Protocol . . . . . . . . . . . . . . . . . . . . . . .7-5

SIPL Protocol . . . . . . . . . . . . . . . . . . . . . . . .7-6

Message Bridging. . . . . . . . . . . . . . . . . . . .7-7

Standard Commands. . . . . . . . . . . . . . . . .7-9

OEM Boot Options . . . . . . . . . . . . . . . . . 7-11

IPMC Watchdog Timer Commands. . . 7-12

Watchdog Timer Actions . . . . . . . .7-12

Watchdog Timer Use Field and

Expiration Flags . . . . . . . . . . . . . . . . 7-12

Using the Timer Use Field and

Expiration Flags . . . . . . . . . . . . 7-13

Watchdog Timer Event Logging . . 7-13

Monitor Support for Watchdog

Timer . . . . . . . . . . . . . . . . . . . . . 7-13

Reset Watchdog Timer Command7-14
Set Watchdog Timer Command. . 7-14
Get Watchdog Timer Command . 7-16

FRU LEDs . . . . . . . . . . . . . . . . . . . . . . . . . 7-18

Get FRU LED Properties Command7-19
Get LED Color Capabilities Command .

7-19

Set FRU LED State Command . . . . 7-21

Get FRU LED State Command . . . . 7-22

Vendor Commands . . . . . . . . . . . . . . . . 7-24

Get Status . . . . . . . . . . . . . . . . . . . . . 7-25

Get Serial Interface Properties . . . 7-27

Set Serial Interface Properties . . . . 7-28

Get Debug Level . . . . . . . . . . . . . . . 7-29

Set Debug Level. . . . . . . . . . . . . . . . 7-29

Get Hardware Address . . . . . . . . . . 7-30

Set Hardware Address . . . . . . . . . . 7-30

Get Handle Switch. . . . . . . . . . . . . . 7-31

Set Handle Switch . . . . . . . . . . . . . . 7-31

Get Payload Communication Time-Out
7-32

Set Payload Communication Time-Out
7-32

Enable Payload Control . . . . . . . . . 7-32

Disable Payload Control . . . . . . . . . 7-33

Reset IPMC . . . . . . . . . . . . . . . . . . . . 7-33

Hang IPMC . . . . . . . . . . . . . . . . . . . . 7-33

Bused Resource . . . . . . . . . . . . . . . . 7-34

Bused Resource Status . . . . . . . . . . 7-34

Graceful Reset . . . . . . . . . . . . . . . . . 7-35

Diagnostic Interrupt Results . . . . . 7-36

Get Payload Shutdown Time-Out. 7-36
Set Payload Shutdown Time-Out . 7-37

Set Local FRU LED State . . . . . . . . . 7-38

Get Local FRU LED State . . . . . . . . . 7-39

Update Discrete Sensor . . . . . . . . . 7-40

Update Threshold Sensor. . . . . . . . 7-40

Boot Device Redirection (BDR) . . . . . . 7-41

Message Listeners . . . . . . . . . . . . . . . . . 7-43

Add Message Listener. . . . . . . . . . . 7-44

Remove Message Listener . . . . . . . 7-44

vi

ATCA-9305 User’s Manual 10009109-01

Contents (continued)

Get Message Listener List . . . . . . . .7-45

System Firmware Progress Sensor . . . 7-45

Entities and Entity Associations . . . . . . 7-46

Sensors and Sensor Data Records . . . . 7-48

FRU Inventory . . . . . . . . . . . . . . . . . . . . . 7-50

E-Keying . . . . . . . . . . . . . . . . . . . . . . . . . . 7-51

Base Point-to-Point Connectivity .7-52

HPM.1 Firmware Upgrade. . . . . . . . . . . 7-52

HPM.1 Reliable Field Upgrade

Procedure . . . . . . . . . . . . . . . . . . . . .7-53

IPMC Headers . . . . . . . . . . . . . . . . . . . . . 7-53

8 Back Panel Connectors

Zone 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-1

Zone 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-2

Zone 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-3

9 Management Processor

Monitor

Command-Line Features. . . . . . . . . . . . . .9-1

Basic Operation. . . . . . . . . . . . . . . . . . . . . .9-3

Power-up/Reset Sequence. . . . . . . . 9-3

POST Diagnostic Results. . . . . . . . . . 9-4

Monitor SDRAM Usage . . . . . . . . . . . 9-5

Monitor Recovery and Updates . . . . . . . .9-5

Recovering the Monitor . . . . . . . . . . 9-6

Resetting Environment Variables . .9-6

Updating the Monitor via TFTP . . . . 9-6

Monitor Command Reference . . . . . . . . .9-7

Command Syntax. . . . . . . . . . . . . . . . 9-7

Command Help . . . . . . . . . . . . . . . . . 9-8

Typographic Conventions . . . . . . . . 9-8

Boot Commands. . . . . . . . . . . . . . . . . . . . .9-8

bootd . . . . . . . . . . . . . . . . . . . . . . . . . . 9-8

bootelf . . . . . . . . . . . . . . . . . . . . . . . . . 9-8

bootm . . . . . . . . . . . . . . . . . . . . . . . . . 9-8

bootp . . . . . . . . . . . . . . . . . . . . . . . . . . 9-8

bootv . . . . . . . . . . . . . . . . . . . . . . . . . .9-9

bootvx . . . . . . . . . . . . . . . . . . . . . . . . . 9-9

dhcp . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-9

rarpboot. . . . . . . . . . . . . . . . . . . . . . . 9-10

tftpboot . . . . . . . . . . . . . . . . . . . . . . .9-10

File Load Commands . . . . . . . . . . . . . . . 9-11

loadb . . . . . . . . . . . . . . . . . . . . . . . . . 9-11

loads . . . . . . . . . . . . . . . . . . . . . . . . . .9-11

Memory Commands . . . . . . . . . . . . . . . 9-11

cmp . . . . . . . . . . . . . . . . . . . . . . . . . . 9-12

cp . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-12

find . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-12

md . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-12

mm. . . . . . . . . . . . . . . . . . . . . . . . . . . 9-13

nm . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-13

mw . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-13

Flash Commands . . . . . . . . . . . . . . . . . . 9-14

cp . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-14

erase . . . . . . . . . . . . . . . . . . . . . . . . . 9-14

flinfo. . . . . . . . . . . . . . . . . . . . . . . . . . 9-14

protect. . . . . . . . . . . . . . . . . . . . . . . . 9-15

EEPROM/I2C Commands . . . . . . . . . . . 9-15

eeprom . . . . . . . . . . . . . . . . . . . . . . . 9-15

icrc32. . . . . . . . . . . . . . . . . . . . . . . . . 9-16

iloop. . . . . . . . . . . . . . . . . . . . . . . . . . 9-16

imd . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-16

imm . . . . . . . . . . . . . . . . . . . . . . . . . . 9-16

imw . . . . . . . . . . . . . . . . . . . . . . . . . . 9-16

inm . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-16

iprobe . . . . . . . . . . . . . . . . . . . . . . . . 9-17

IPMC Commands . . . . . . . . . . . . . . . . . . 9-17

bootdev. . . . . . . . . . . . . . . . . . . . . . . 9-17

fru. . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-17

fruinit . . . . . . . . . . . . . . . . . . . . . . . . . 9-18

fruled . . . . . . . . . . . . . . . . . . . . . . . . . 9-18

ipmchpmfw . . . . . . . . . . . . . . . . . . . 9-18

sensor . . . . . . . . . . . . . . . . . . . . . . . . 9-18

Environment Parameter Commands . 9-19

printenv. . . . . . . . . . . . . . . . . . . . . . . 9-19

saveenv . . . . . . . . . . . . . . . . . . . . . . . 9-19

setenv . . . . . . . . . . . . . . . . . . . . . . . . 9-19

Test Commands . . . . . . . . . . . . . . . . . . . 9-20

diags. . . . . . . . . . . . . . . . . . . . . . . . . . 9-20

mtest . . . . . . . . . . . . . . . . . . . . . . . . . 9-20

um . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-20

Other Commands. . . . . . . . . . . . . . . . . . 9-20

autoscr. . . . . . . . . . . . . . . . . . . . . . . . 9-20

base . . . . . . . . . . . . . . . . . . . . . . . . . . 9-20

bdinfo . . . . . . . . . . . . . . . . . . . . . . . . 9-21

coninfo . . . . . . . . . . . . . . . . . . . . . . . 9-21

crc32 . . . . . . . . . . . . . . . . . . . . . . . . . 9-21

date . . . . . . . . . . . . . . . . . . . . . . . . . . 9-21

echo . . . . . . . . . . . . . . . . . . . . . . . . . . 9-21

enumpci . . . . . . . . . . . . . . . . . . . . . . 9-21

go . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-21

help . . . . . . . . . . . . . . . . . . . . . . . . . . 9-22

10009109-01 ATCA- 9305 User’s Manual

vii

Contents (continued)

iminfo. . . . . . . . . . . . . . . . . . . . . . . . .9-22

isdram . . . . . . . . . . . . . . . . . . . . . . . .9-22

loop. . . . . . . . . . . . . . . . . . . . . . . . . . .9-22

memmap. . . . . . . . . . . . . . . . . . . . . .9-22

moninit . . . . . . . . . . . . . . . . . . . . . . . 9-22

pci . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-23

phy . . . . . . . . . . . . . . . . . . . . . . . . . . .9-23

ping. . . . . . . . . . . . . . . . . . . . . . . . . . .9-24

reset . . . . . . . . . . . . . . . . . . . . . . . . . . 9-24

run. . . . . . . . . . . . . . . . . . . . . . . . . . . .9-24

script. . . . . . . . . . . . . . . . . . . . . . . . . .9-24

showmac . . . . . . . . . . . . . . . . . . . . . .9-24

showpci . . . . . . . . . . . . . . . . . . . . . . .9-24

sleep. . . . . . . . . . . . . . . . . . . . . . . . . . 9-25

switch_reg . . . . . . . . . . . . . . . . . . . . 9-25

version. . . . . . . . . . . . . . . . . . . . . . . . 9-25

vlan. . . . . . . . . . . . . . . . . . . . . . . . . . . 9-25

MPC8548 Environment Variables . . . . 9-26

Troubleshooting. . . . . . . . . . . . . . . . . . . 9-28

Download Formats. . . . . . . . . . . . . . . . . 9-28

Binary. . . . . . . . . . . . . . . . . . . . . . . . . 9-29

Motorola S-Record . . . . . . . . . . . . . 9-29

10Acronyms

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Figure 1-1: General System Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3

Figure 2-1: ATCA-9305 Front Panel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2

Figure 2-2: Component Map, Top (Rev. 01) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3

Figure 2-3: Component Map, Bottom (Rev. 01). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4

Figure 2-4: LED, Fuse and Switch Locations, Top. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5

Figure 2-5: LED and Switch Locations, Bottom. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6

Figure 2-6: Configuration Header, J9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8

Figure 2-7: Air Flow Graph . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10

Figure 2-8: Serial Number and Product ID on Top Side. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12

Figure 3-1: Cavium Processor Complex Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1

Figure 3-2: CN5860 Reset Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4

Figure 3-3: Example Cavium CN5860 Monitor Start-up Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6

Figure 3-4: Power-up/Reset CN5860 Boot Sequence Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7

Figure 4-1: MPC8548 Management Processor Complex Block Diagram. . . . . . . . . . . . . . . . . . . . . 4-1

Figure 4-2: MPC8548 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3

Figure 4-3: MPC8548 Reset Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6

Figure 6-1: Ethernet Switching Interface Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2

Figure 7-1: IPMC Connections Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2

Figure 7-2: Extension Command Request Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7

Figure 7-3: Extension Command Response Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7

Figure 7-4: Boot Device Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-42

Figure 7-5: Boot Redirection Control Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-42

Figure 7-6: IPMB Entity Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-47

Figure 8-1: Zone 1 Connector, P10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1

Figure 8-2: Zone 2 and 3 Connectors; J23, J30-J31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2

Figure 8-3: Zone 3 Connector, J33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4

Figure 9-1: Example MPC8548 Monitor Start-up Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2

Figure 9-2: Power-up/Reset Sequence Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4

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Table 1-1: Regulatory Agency Compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4

Table 1-2: Technical References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6

Table 2-1: Circuit Board Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1

Table 2-2: Typical Power Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9

Table 2-3: Environmental Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9

Table 3-1: CN5860 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1

Table 3-2: Cavium Address Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2

Table 3-3: Ethernet Port Address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5

Table 3-4: POST Diagnostic Results–Bit Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8

Table 3-5: Standard Cavium Environment Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8

Table 3-6: Cavium NVRAM Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10

Table 3-7: CN5860 Processor COP/JTAG Headers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14

Table 3-8: CN5860 Processor Debug Headers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15

Table 4-1: MPC8548 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2

Table 4-2: MPC8548 Address Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3

Table 4-3: Device Chip Selects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5

Table 4-4: PCI Device Interrupts and ID Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8

Table 4-5: I2C Device Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9

Table 4-6: MPC8548 NVRAM Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9

Table 4-7: Serial Debug Connector, P2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9

Table 4-8: Serial Debug Connector, P7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10

Table 5-1: PLD Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1

Table 5-2: Low Frequency Timer Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10

Table 6-1: Ethernet Switch Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2

Table 6-2: VLAN Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3

Table 6-3: Ethernet Port Address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4

Table 6-4: Front Panel Ethernet Ports. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4

Table 7-1: Network Function Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3

Table 7-2: Completion Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4

Table 7-3: Format for IPMI Request Message . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5

Table 7-4: Format for IPMI Response Message . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6

Table 7-5: IPMC IPMI Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9

Table 7-6: Emerson Boot Option Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-11

Table 7-7: IPMC Watchdog Timer Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-12

Table 7-8: Reset Watchdog Timer Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-14

Table 7-9: Set Watchdog Timer Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-15

Table 7-10: Get Watchdog Timer Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-16

Table 7-11: FRU LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-18

Table 7-12: Get FRU LED Properties Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-19

Table 7-13: Get LED Color Capabilities Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-19

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Table 7-14: Set FRU LED State Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-21

Table 7-15: Get FRU LED State Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-22

Table 7-16: Vendor Command Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-24

Table 7-17: Get Status Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-25

Table 7-18: Get Serial Interface Properties Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-27

Table 7-19: Set Serial Interface Properties Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-28

Table 7-20: Get Debug Level Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-29

Table 7-21: Set Debug Level Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-29

Table 7-22: Get Hardware Address Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-30

Table 7-23: Set Hardware Address Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-30

Table 7-24: Get Handle Switch Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-31

Table 7-25: Set Handle Switch Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-31

Table 7-26: Get Payload Communication Time-Out Command . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-32

Table 7-27: Set Payload Communication Time-Out Command . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-32

Table 7-28: Enable Payload Control Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-32

Table 7-29: Disable Payload Control Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-33

Table 7-30: Reset IPMC Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-33

Table 7-31: Hang IPMC Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-33

Table 7-32: Bused Resource Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-34

Table 7-33: Bused Resource Status Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-35

Table 7-34: Graceful Reset Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-36

Table 7-35: Diagnostic Interrupt Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-36

Table 7-36: Get Payload Shutdown Time-Out Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-37

Table 7-37: Set Payload Shutdown Time-Out Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-37

Table 7-38: Set Local FRU LED State Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-38

Table 7-39: Get Local FRU LED State Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-39

Table 7-40: Update Discrete Sensor Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-40

Table 7-41: Update Threshold Sensor Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-40

Table 7-42: Add Message Listener Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-44

Table 7-43: Remove Message Listener Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-44

Table 7-44: Get Message Listener List Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-45

Table 7-45: Update System Firmware Progress Sensor Command. . . . . . . . . . . . . . . . . . . . . . . . . 7-46

Table 7-46: IPMI Threshold Sensors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-48

Table 7-47: IPMI Discrete Sensors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-48

Table 7-48: Event Message Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-49

Table 7-49: FRU Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-50

Table 7-50: Link Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-52

Table 7-51: IPMP CPLD JP1 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-53

Table 7-52: IPMP EIA-232 P4 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-53

Table 8-1: Zone 1 Connector, P10 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1

Table 8-2: Zone 2 Connector, J23 Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3

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Table 8-3: Zone 3 Connector, J30 Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3

Table 8-4: Zone 3 Connector, J31 Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4

Table 8-5: Zone 3 Connector, J33 Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4

Table 9-1: Debug LED Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2

Table 9-2: POST Diagnostic Results–Bit Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5

Table 9-3: Monitor Address per Flash Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-6

Table 9-4: Static IP Ethernet Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-9

Table 9-5: DHCP Ethernet Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-10

Table 9-6: Standard Environment Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-26

Table 9-7: Optional Environment Variables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-28

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Register 3-1: Data 31:24 (0x0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10

Register 3-2: Data 23:16 (0x1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11

Register 3-3: Data 15:8 (0x2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11

Register 3-4: Data 7:0 (0x3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11

Register 3-5: Address 9:8 (0x4). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12

Register 3-6: Address 7:0 (0x5). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12

Register 3-7: Control (0x6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12

Register 3-8: Version (0x7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13

Register 3-9: Scratch (0x8-0x3F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13

Register 5-1: Product ID (0x00) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2

Register 5-2: Hardware Version (0x04). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2

Register 5-3: PLD Version (0x08) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3

Register 5-4: PLL Reset Configuration (0x0C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3

Register 5-5: Hardware Configuration 0 (0x10). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4

Register 5-6: Jumper Settings (0x18). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4

Register 5-7: LED (0x1C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5

Register 5-8: Reset Event (0x20) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5

Register 5-9: Reset Command 1 (0x24) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6

Register 5-10: Reset Command 2 (0x28) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6

Register 5-11: Reset Command 3 (0x2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6

Register 5-12: Reset Command 4 (0x30) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7

Register 5-13: Reset Command 5 (0x34) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7

Register 5-14: Reset Command Sticky #1 (0x38) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8

Register 5-15: Reset Command Sticky #2 (0x3C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8

Register 5-16: Boot Device Redirection (0x50) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9

Register 5-17: Miscellaneous Control (0x54) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9

Register 5-18: RTM GPIO State (0x60). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10

Register 5-19: RTM GPIO Control (0x64). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10

Register 5-20: RTM Control (0x68). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11

Register 5-21: Cavium 1 C_MULL Clock Divisor Control (0x70) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11

Register 5-22: Cavium 2 C_MULL Clock Divisor Control (0x74) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12

Register 5-23: JTAG (0x78). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12

Register 5-24: Cavium GPIO Control (0x80) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12

Register 5-25: Cavium GPIO Data Out (0x84) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13

Register 5-26: Cavium GPIO Data In (0x88) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13

Register 5-27: IPMP/IPMC GPIO Control (0x8C). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-14

Register 5-28: LPC Bus (0xD0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-14

Register 5-29: LPC Data (0xD4). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15

Register 5-30: Serial IRQ Interrupts 1 (0xD8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15

Register 5-31: Serial IRQ Interrupts 2 (0xDC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15

10009109-01 ATCA- 9305 User’s Manual

i

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ii

ATCA-9305 User’s Manual 10009109-01

Overview

The ATCA-9305 is an Advanced Telecom Computing Architecture (AdvancedTCA®, ATCA®)
blade based on dual Cavium OCTEON™ CN5860 processors and the Freescale™ Semicon­ductor MPC8548 management processor. This blade is targeted at security and packet-pro­cessing applications in the wireless and transport market segments. These markets include
data-plane packet-processor, security co-processor, video compression, and pattern match­ing.

The ATCA-9305 complies with the SCOPE recommended profile for central office ATCA sys­tems, PICMG® 3.0 ATCA mechanical specifications, E-keying, and Hot Swap.

COMPONENTS AND FEATURES

The following is a brief summary of the ATCA-9305 hardware components and features:

Cavium Processor : The Cavium CN5860 processor is a highly programmable, high-performance 16-core archi-

tecture operating up to 800 MHz.

Section 1

Management Processor:

The Freescale PowerQUICC™ III MPC8548 processor is a 32-bit enhanced e500 core operat­ing at 1 GHz.

Ethernet Switch: The Broadcom® BCM56802 is a sixteen-port, 10 GbE switch which interconnects the pro-

cessors using SPI to XAUI™ bridges. The functionality includes both 10-Gbps XAUI and 1­Gbps SGMII PHY interfaces.

Stratix™ GX Bridge: There are two packet routing Altera® SPI-4.2 high-speed interconnect to XAUI bridges per

CN5860 processor.

Ethernet: 10/100/1000BASE-T Ethernet ports are accessible via the front panel RJ45 connectors and

through the base channel on the back panel. The 10 GbE ports route to the back panel
through the fabric and RTM connectors.

Serial Port: The front panel serial port (MGT CSL) connects to the MPC8548 management processor.

System Management: This product supports an Intelligent Platform Management Controller (IPMC) based on a

proprietary BMR-H8S-AMCc® reference design from Pigeon Point Systems. The IPMC has
an inter-integrated circuit (I2C) controller to support an Intelligent Management Platform
Bus (IPMB) that routes to the AdvancedTCA connector. The IPMB allows for features such as
remote shutdown, remote reset, payload voltage monitoring, temperature monitoring,
and access to Field Replaceable Unit (FRU) data.

PCI/PCIe: The PCI bus allows for read/write memory access between the MPC8548 processor, Ether-

net switch, and Cavium processors. The four lane PCI Express® (PCIe) routes between the
MPC8548 and the optional RTM.

10009109-01 ATCA- 9305 User’s Manual

1-1

Overview: Components and Features

Real-time Clock: The STMicroelectronics M41T00S RTC provides counters for seconds, minutes, hours, day,

date, month, years, and century. The M41T00S serial interface supports I
super-cap backup capable of maintaining the clock for a minimum of two hours.

Software: The Cavium CN5860 processor provides a GNU compiler that implements the MIPS64 Rel 2

instruction set in addition to the specialized instructions and a Linux® Board Specific Pack­age (BSP) including the IP-stack optimization. The CN5860 also provides libraries that take
advantage of the chip’s hardware acceleration for certain security protocols.

RTM (optional): This blade supports a custom Rear Transition Module (RTM) with the following I/O:

• Either two or six 10GbE connections

• One x4 PCI Express port from the MPC8548

• Connections for an MMC to control Hot Swap

• MPC8548 console port

For more detailed information, see the ATCA-9305 Rear Transition Module User’s Manual.

2

C bus and has a

1-2

ATCA-9305 User’s Manual 10009109-01

Overview: Functional Overview

Console

(ENG use only)

PCI Bus

10G - 4 PORTS

RJ45 RJ45

BCM5482

1 2

Base

3 2 1 0 3 2 1 0

FC2 FC1

10G Fabric

J23

I2C

EEPROM

COP/
JTAG

NAND

Flash
1GB

x 16

BCM56802
XAUI 10 Gb

Switch

5 XAUI

SGMII2SGMII1XAUI

8 7

XAUI 13

XAUI 14

3

SGMII

4

SGMII

PCI Bus

IDSEL13

6 XAUI

Mag

KSL

CPLD

Latched Adrs

A/D

IPMB

P10

Console

(ENG use only)

Cavium
Octeon
CN5860

Processor 1

SPI-1

PCI
Bus

IDSEL11

Serial 0D1_DDR2

I2C

Serial 1

SPI-0

Adrs/Data

Console

BCM5461S

Stratix II GX

#2

I2C

EEPROM

RTC

MPC8548

Management

Processor

RLDRAM

64MB

Local Bus

Addr/Data

J31

10G - 2 PORTS

J30

Socketed

ROM

512KB

x 8

COP/
JTAG

To R TM

XAUI

11-12 15 -18

J33

RTM RST

12V Hot Swap

RTM Console

PQ I2C

Serial CFG

EEPROM

RLDRAM

64MB

PQ DDR2

SDRAM

NOR

Flash

4M

x 16

P1 DDR
SDRAM

P2 DDR2

SDRAM

RLDRAM

64MB

RLDRAM

64MB

I2C

EEPROM

RLDRAM

64MB

RLDRAM

64MB

RLDRAM

64MB

RLDRAM

64MB

Stratix II GX

#1

Stratix II GX

#4

BCM5461S BCM5461S

Mag

Mag Mag

I2C

EEPROM

COP/JTAG

PCIe x4

I2CI2C

Stratix II GX

#3

Cavium
Octeon
CN5860

Processor 2

Serial 0

Serial 1

D1_DDR2

I2C

SPI-1

SPI-0

Local Bus

Addr/Data

PCI
Bus
IDSEL12

NOR

Flash
512Mb or
64MB x 16

Socketed

ROM
512K

x 8

NOR
Flash

4M
x 8

Socketed

ROM
512K

x 8

NOR
Flash

4M
x 8

FUNCTIONAL OVERVIEW

The following block diagram provides a functional overview for the ATCA-9305:

Figure 1-1: General System Block Diagram

10009109-01 ATCA- 9305 User’s Manual

1-3

Overview: Additional Information

ADDITIONAL INFORMATION

This section lists the ATCA-9305 hardware’s regulatory certifications and briefly discusses
the terminology and notation conventions used in this manual. It also lists general technical
references.

Mean time between failures (MTBF) has been calculated at 439,924 hours using the Telcor­dia SR-332, Issue 1 (Reliability Prediction for Electronic Equipment), method 2 at 30

Product Certification

The ATCA-9305 hardware has been tested to comply with various safety, immunity, and
emissions requirements as specified by the Federal Communications Commission (FCC),
Underwriters Laboratories (UL), and others. The following table summarizes this compli­ance:

Table 1-1: Regulatory Agency Compliance

Type: Specification:

Safety IEC60950/EN60950 – Safety of Information Technology Equipment

(Western Europe)

UL60950, CSA C22.2 No. 60950 – Safety of Information Technology
Equipment, including Electrical Business Equipment (BI-National)

GR1089-CORE

Global IEC – CB Scheme Report IEC 60950, all country deviations

Environmental NEBS: Telecordia GR-63 –

Section 4.1.1 Transportation and Storage Environmental Criteria;
Section 4.1.2 Operating Temperature and Humidit y;
Section 4.1.3 Altitude;
Section 4.1 4 Temperature Margins;
Section 4.4.1 Earthquake Environment;
Section 4.4.4 Office Vibration:
Section 4.4.5 Transportation Vibration

° C.

1-4

ATCA-9305 User’s Manual 10009109-01

Overview: Additional Information

Type: Specification: (continued)

EMC FCC Part 15, Class A– Title 47, Code of Federal Regulations, Radio

Emerson maintains test reports that provide specific information regarding the methods
and equipment used in compliance testing. Unshielded external I/O cables, loose screws, or
a poorly grounded chassis may adversely affect the ATCA-9305 hardware’s ability to comply
with any of the stated specifications.

Frequency Devices

ICES 003, Class A – Radiated and Conducted Emissions, Canada

NEBS: Telecordia GR-1089 level 3 – Emissions and Immunity (circuit pack
level testing only)

EN55022 – Information Technology Equipment, Radio Disturbance
Characteristics, Limits and Methods of Measurement

EN55024 – Information Technology Equipment, Immunity
Characteristics, Limits and Methods of Measurement

ETSI EN300386 – Electromagnetic Compatibility and Radio Spectrum
Matters (ERM), Telecommunication Network Equipment,
Electromagnetic Compatibility (EMC) Requirements

AS/NZS 3548 003, Class A – Standard for radiated and conducted
emissions for Australia and New Zealand

The UL web site at ul.com has a list of Emerson’s UL certifications. To find the list, search in
the online certifications directory using Emerson’s UL file number, E190079. There is a list
for products distributed in the United States, as well as a list for products shipped to Can­ada. To find the ATCA-9305, search in the list for 10009986-xx, where xx changes with each
revision of the printed circuit board.

The Ethernet connection of the equipment or subassembly must be connected with
shielded cables that are grounded at both ends.

RoHS Compliance

The ATCA-9305 is compliant with the European Union’s RoHS (Restriction of use of Hazard­ous Substances) directive created to limit harm to the environment and human health by
restricting the use of harmful substances in electrical and electronic equipment. Effective
July 1, 2006, RoHS restricts the use of six substances: cadmium (Cd), mercury (Hg), hexava­lent chromium (Cr (VI)), polybrominated biphenyls (PBBs), polybrominated diphenyl ethers
(PBDEs) and lead (Pb). Configurations that are RoHS compliant are built with lead-free sol­der.

To obtain a certificate of conformity (CoC) for the ATCA-9305, send an e-mail to
[e-mail] or call 1-800-356-9602. Have the part number(s)
(e.g., C000####-##) for your configuration(s) available when contacting Emerson.

10009109-01 ATCA- 9305 User’s Manual

1-5

Overview: Additional Information

Terminology and Notation

Active low signals: An active low signal is indicated with an asterisk * after the signal name.

Byte, word: Throughout this manual byte refers to 8 bits, word refers to 16 bits, and long word refers to

32 bits, double long word refers to 64 bits.

PLD: This manual uses the acronym, PLD, as a generic term for programmable logic device (also

known as FPGA, CPLD, EPLD, etc.).

Radix 2 and 16: Hexadecimal numbers end with a subscript 16. Binary numbers are shown with a

subscript 2.

Technical References

Further information on basic operation and programming of the ATCA-9305 components
can be found in documents listed in

Table 1-2: Technical References

Device /
Interface: Document: 1

ATC A AdvancedTCA® Base Specification

(PICMG

Engineering Change Notice 3.0-1.0-001

(PICMG

Ethernet/Fibre Channel for AdvancedTCA™ Systems

(PICMG

http://www.picmg.org

CPU
CN5860
MPC8548

DRAM 576Mb: x9, x18, x36 2.5V V

EEPROM Atmel® 2-Wire Serial EEPROM 64K (8192 x 8) Preliminary Data Sheet

Ethernet
BCM5461S
BCM5482

Cavium Networks OCTEON™ Plus CN58XX Hardware Reference Manual
(Cavium Networks, CN58XX-HM-1.2 Sept. 2008)

http:/www.caviumnetworks.com

MPC8548E PowerQUICC™ III Integrated Processor Family Reference Manual

(Freescale™ Semiconductor, Inc. MPC8548ERM Rev.2, 02/2007

http://www.freescale.com

(Micron Technology, Inc. 576Mb_RLDRAM_II_CIO_D1.fm - Rev C 9/07 EN)
http://www.micron.com

(Atmel Corporation, 5174C-SEEPR-6/07)

http://www.atmel.com

10/100/1000BASE-T Gigabit Ethernet Transceiver Data Sheet

(Broadcom® Corporation, Document 5461S-DS17-R 5/12/08)

10/100/1000BASE-T Gigabit Ethernet Transceiver Data Sheet

(Broadcom® Corporation, Document 5482-DS04-R 10/18/07)

http://www.broadcom. com

®

3.0 Revision 2.0 March 18, 2005)

®

3.0 R2.0: ECN 3.0-2.0-001 June 15, 2005)

®

3.1 Revision 1.0 January 22, 2003)

Ta bl e 1- 2 .

, 1.8C VDD, HSTL, CIO,RLDRAM II Data Sheet

EXT

1-6

ATCA-9305 User’s Manual 10009109-01

Overview: Additional Information

Device /
Interface: Document: 1 (continued)

Flash 32 Mbit (x8/x16) Concurrent SuperFlash Data Sheet

(Silicon Storage Technology, Inc., S71270-01-000 9/05)

http://www.sst.com

mDOC H3 Embedded Flash Drive (EFD) featuring Embedded TrueFFS® Flash Management
Software Preliminary Data Sheet

(msystems 92-DS-1205-10 Rev. 0.2 June 2006)

http://www.m-systems.com/mobile

StrataFlash® Embedded Memory (P33) Data Sheet

(Intel®, Order Number: 314749-004 November 2007)

http://www.intel.com

4. Serial Configuration Devices (EPCS1, EPCA4, EPCS16, & EPCS64)

(Altera® Corporation CS1014-2.0 April 2007)

http://www.altera.com

IPMI IPMI — Intelligent Platform Management Interface Specification v2.0

(Intel Hewlett-Packard NEC Dell, Rev. 1.0, Feb. 12, 2004)

IPMI — Intelligent Platform Management Bus Communications Protocol Specification v1.0

(Intel Hewlett-Packard NEC Dell, Rev. 1.0, November 15, 1999)

IPMI — Platform Management FRU Storage Definition v1.0

(Intel Hewlett-Packard NEC Dell, Rev. 1.1, September 27, 1999)

http://www.intel.com/design/servers/ipmi/

Hardware Platform Management IPM Controller Firmware Upgrade Specification v1.0

(PICMG HPM.1 R1.0 May 4, 2007)

http://www.picmg.org

RTC
M41T00S

Switch
BCM56802

1. Frequently, the most current information regarding addenda/errata for specific documents may be
found on the corresponding web site.

Serial Access Real-Time Clock Data Sheet

(STMicroelectronics December 2004)

BCM56800 Series 20-Port 10-Gigabit Ethernet Multilayer Switch Preliminary Data Sheet

(Broadcom® Corporation, Document 56800-DS03-R 12/28/07)

http://www.broadcom. com

10009109-01 ATCA- 9305 User’s Manual

1-7

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1-8

ATCA-9305 User’s Manual 10009109-01

Setup

!

Section 2

This chapter describes the physical layout of the boards, the setup process, and how to
check for proper operation once the boards have been installed. This chapter also includes
troubleshooting, service, and warranty information.

ELECTROSTATIC DISCHARGE

Before you begin the setup process, please remember that electrostatic discharge (ESD) can
easily damage the components on the ATCA-9305 hardware. Electronic devices, especially
those with programmable parts, are susceptible to ESD, which can result in operational fail­ure. Unless you ground yourself properly, static charges can accumulate in your body and
cause ESD damage when you touch the board.

Caution: Use proper static protection and handle ATCA-9305 boards only when absolutely

necessary. Always wear a wriststrap to ground your body before touching a board. Keep
your body grounded while handling the board. Hold the board by its edges–do not touch
any components or circuits. When the board is not in an enclosure, store it in a static­shielding bag.

To ground yourself, wear a grounding wriststrap. Simply placing the board on top of a static­shielding bag does not provide any protection–place it on a grounded dissipative mat. Do
not place the board on metal or other conductive surfaces.

ATCA-9305 CIRCUIT BOARD

The ATCA-9305 circuit board is an ATCA blade assembly and complies with the PICMG 3.0
ATCA mechanical specification. It uses a 16-layer printed circuit board with the following
dimensions:

Table 2-1: Circuit Board Dimensions

Width: Depth: Height: Weight (typical):

12.687 in.
(322.25 mm)

1. This is the typical weight for the ATCA-9305. Board weight varies slightly per configuration; contact
Technical Support if you require a specific configuration weight.

The following figures show the front panel, component maps, and LED locations for the
ATCA-9305 circuit board.

11.024 in.
(280.01 mm)

< .84 in.
(<21.33 mm)

4.2 lb.
(1.91 kg)

1

10009109-01 ATCA- 9305 User’s Manual

2-1

Setup: ATCA-9305 Circuit Board

ATCA-9035

O
O
S

Blue Hot Swap

2

3

MGT ETH

SWITCH

ETH

SPD

LINK
ACT

SPD

LINK
ACT

MGT CSL

RST

H/S

Reset

Red/Amber = Out of Service (OOS)

Green = In Service (2)

Amber = User Defined (3)

Off = 10 Mbps
Yellow = 100 Mbps
Green = 1000Mbps

Off = No Link
On= Link, No Activity
Blink = Link/Activity

Ethernet Speed (top LED)

Ethernet Link/Activity (bottom LED)

Port 1

Port 2

Management Console

!

Figure 2-1: ATCA-9305 Front Panel

2-2

Note: The electromagnetic compatibility (EMC) tests used an ATCA-9305 model that includes a front panel assem-

bly from Emerson Network Power, Embedded Computing.

Caution: For applications where the ATCA-9305 is provided without a front panel, or where the front

ATCA-9305 User’s Manual 10009109-01

panel has been removed, your system chassis/enclosure must provide the required
electromagnetic interference (EMI) shielding to maintain CE compliance.

Setup: ATCA-9305 Circuit Board

+

+

+

+

C523

R153

C420

C518

C311

C717

C149

L30

C9

F5

U61

C314

C140

U22

C751

R172

C684

L41

C197

C549

C254

C220

R169

R91

U53

CR7

C54

R187

R146

C740

C508

C491

C544

C644

C592

R199

C2108

U38

C240

C538

C612

R45

C2145

R19

C406

C731

R40

R228

R58

C330

R279

F10

U15

CN58x0

Processor 2

C527

C336

C533

CR11

R57

R223

C1

C607

R102

C5

C176

C264

R136

C710

C466

C526

C200

R21

C561

C259

U7

C69

C67

CR6

L53

C552

C26

C506

CR34

C312

R178

R47

C675

C535

C766

R1034

C764

U19
MPC8548
Processor

C755

R183

C415

R75

Y1

C19

C32

C227

C692

R280

L20

R247

C516

R1

C775

C542

R166

C235

C78

C591

C512

C447

C2147

R6

C315

C96

CR40

R69

R197

C486

R1010

C20

R213

C748

R1039

C680

C713

CR38

RN2

R66

R210

R4

C173

C216

C454

C2106

C520

C693

C307

L67

C712

C395

R181

R161

C763

C58

C345

C485

R292

C519

C419

C588

C767

C219

R103

R118

C777

C732

R757

C727

C632

R236

R132

U43

L32

C459

C458

C726

L14

C218

C111

C550

C298

RN12

C403

C181

R202

U34

BCM5680x

Switch

C500

C536

Y9

C129

R216

U36

C162

R73

C114

C678

C596

C636

C504

C733

C103

C437

R24

CR42

C272

CR53

C559

C555

R111

C445

C595

U39

U33

C52

R49

C152

C75

R157

C325

C556

CR29

C147

C190

C530

R214

C366

C271

RN1

C281

C761

R56

C440

R237

L52

R272

C463

C709

L69

R100

R139

C66

C61

C10

U54

R201

R291

C451

C402

C279

C575

C482

C696

U46

R759

C273

P2

F4

R36

C85

C64

C164

R34

R18

R170

C203

R204

C192

C229

C628

C599

Y6

C753

R460

C139

C746

R16

C741

C799

C60

R254

C301

R83

C377

C45

C677

C418

F1

U32

C155

C416

C424

C72

U5

C722

C238

C2103

R192

C479

C131

C261

C148

J13

L28

C141

C353

F2

CR8

C226

CR52

C56

L43

C788

R44

C79

C332

C385

C540

CR25

C786

C53

R261

C743

R293

C467

C117

L66

C151

C207

C399

C364

C258

U58

C704

C503

C461

C214

U65

U3S

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C303

L55

C706

R171

R287

C309

C376

R189

RN10

R8

C365

C110

R35

R165

C615

R89

CR19

C464

C510

C581

CR9

C697

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C172

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C391

L44

C369

RN3

C351

C509

R258

R285

C380

R137

C265

C600

C25

C389

C448

L35

C444

C630

SW1

C275

C179

R25

C779

C191

R243

L48

C409

CR12

R276

C30

CR18

C758

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R1056

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C502

M2

C41

C300 C306

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C422

R177

R206

C333

C398

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R195

R217

C201

R274

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R3

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C159

C361

C436

C665

C154

L23

C557

R149

C319

C250

CR21

C183

C560

R286

C168

C410

C230

R92

U2

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C2105

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C196

R144

C29

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L40

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C642

CR24

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C435

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R295

C100

CR3

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C723

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R126

C493

C2148

C525

C368

R1060

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C80

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C474

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C295

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C65

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R81

C76

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C322

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C90

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C36

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CR36

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CR4

CR20

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CR45

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C178

R138

R72

R164

C46

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C237

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C694

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C529

R97

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C452

C101

C397

R39

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C133

C417

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C569

C421

C77

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C432

C660

CR33

C12

R218

C2120

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C603

C8

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C428

C528

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C252

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L1

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R22

C212

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L2

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C616

CR23

CR32

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R88

C633

CR49

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C531

C62

C33

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C11

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C735

C771

R220

C619

C574

C388

C182

C38

C695

R123

CR31

C223

C718

C543

R260

R1032

R275

CR44

C667

C651

C2117

R27

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C623

R128

C499

C654

R193

C177

C93

CR15

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C687

C625

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R205

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C277

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C352

C287

L46

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P5

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R222

R176

C267

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CR14

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R194

C714

C57

C622

C174

R134

C160

C13

C699

U20

C22

R207

R85

C4

C725

C443

C666

C617

C262

C657

C765

C89

RN6

C784

C329

U48

Micro-

controller

F8

C613

C524

C302

U9

C690

C394

C769

C2112

R462

R78

C343

R154

C107

C283

C153

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C367

C292

CR37

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C2116

C414

C202

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C2104

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R242

C571

R251

C686

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C59

C28

C34

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C73

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U11

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R265

C2109

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R32

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C304

C331

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R249

C513

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C355

C120

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PHY

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R70

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C645

C356

C31

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P6

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R174

C92

R173

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C392

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L7

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C492

C384

C225

C204

C2107

R284

C169

C205

C165

CR2

C744

C494

C700

C648

R11

C124

C39

R106

C2118

L47

C122

C610

C263

C363

U52

U55

12V

Power Supply

C349

U44

C167

C703

C401

U57

C566

C246

C800

C393

C2149

R246

C521

C691

F7

C233

R17

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C545

C602

C118

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C2111

C17

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C426

C759

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C251

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R168

L36

CR35

C199

C573

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R270

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C593

C408

C242

C664

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C16

C15

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C647

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M1

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U17

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RN7

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R145

C483

C715

C99

C564

C14

C413

L50

C760

C270

C750

C570

J11

C514

C450

R65

R219

C334

C534

C736

C658

C719

C430

C541

C652

R262

C434

R158

C537

R79

C43

C477

R179

R10

C188

C774

R124

U24
KSL

CPLD

C253

C144

C501

C789

C274

C194

C563

C51

C371

C484

C583

C209

C112

C472

C257

C278

C323

C346

R211

C770

C539

R76

C439

R266

C649

C594

R765

C341

C299

R77

R212

R229

R30

C468

R1049

C320

R257

C752

R198

R20

C653

C119

C507

C222

R116

C627

C2

C609

C208

C142

R231

L45

R90

C184

C383

C590

C620

C109

R2

R155

C115

R1050

C373

C465

R71

C768

R15

R263

R125

C370

C49

RN9

C128

R87

C601

CR39

J3

C186

C3

R9

J15

R151

C453

L34

R14

C662

R133

C797

C412

L33

CR30

R200

C81

C94

R269

C778

C362

Y7

R108

L8

C327

R224

C745

U25

C40

C47

C626

C562

J14

C582

C547

C27

C456

R115

C116

CR27

C749

C280

L31

R248

C558

C294

CR22

C171

C671

C698

R332

C249

R131

C580

C132

L58

L51

C236

L38

R84

C318

RN5

C669

C441

C629

C145

C245

R109

C2119

C71

R67

CR10

C50

C193

C305

L9

C135

CR1

C310

C224

C433

C88

C793

C476

C460

R12

L27

R68

C374

F6

J9

C386

U41

SPI-XAUI

Bridge

R98

C429

R110

CR28

L68

L22

C791

C2110

U1

C606

J5

C55

C720 C721

C35

C248

C685

C326

C63

C673

R60

C344

C339

U26

C572

U4

R1041

R46

C163

R244

C217

R99

C243

L16

C42

C496

U27

C390

C734

C121

C792

C213

R119

C656

C102

C634

C211

C635

C256

C605

CR5

R208

C126

L57

R191

C382

R234

C239

C337

C97

C701

C2113

R33

C586

C286

C801

C130

C795

R761

C711

C597

C375

C260

U18

SO-CDIMM

U63

C756

C358

C568

C618

R188

U8

C37

C82

R184

C134

C316

C215

C335

CR13

C672

U6

C489

C469

C554

U60

C688

C663

Y2

C324

C776

R96

C198

R64

C480

C407

C757

C643

C359

R186

R148

C614

C166

CR17

C146

C221

C108

C21

C754

R38

C170

C83

C641

C372

C621

C313

C44

R182

R250

C24

C724

C291

CR26

P3

RJ45

P1

RJ45

P7

Mini-B

USB

U42

SPI-XAUI

Bridge

U13

SPI-XAUI

Bridge

U10

SPI-XAUI

Bridge

J33

24-pin ATCA

Connector

Polar Key

ATCA Guide

Polar Key

ATCA Guide

J31

80-pin

Zone 3

ATCA

Connector

J30

80-pin

Zone 3

ATCA

Connector

J23

80-pin

Zone 2

ATCA

Connector

P10

30-pin

Zone 13

ATCA

Connector

U56

CN58x0

Processor 1

Figure 2-2: Component Map, Top (Rev. 01)

10009109-01 ATCA- 9305 User’s Manual

2-3

Setup: ATCA-9305 Circuit Board

C1882

C1004

C1877

C1442

C1506

C1330

R999

C1499

C1578

C1703

C1914

R831

C1818

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C1923

C1829

C941

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C1718

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C1878

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C1207

C1556

C968

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C1935

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C1066

C1902

C1849

C1857

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C1934

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C1364

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C1660

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C1592

C1977

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C1015

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C1726

R604

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R1003

C1011

R1031

C1137

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C2027

C1762

R328

R343

R437

C958

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C2177

R736

C1738

R693

C1221

C1327

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C1505

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C1002

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C2068

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C1897

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C1720

C985

RN13

C1705

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C1910

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C1256

C1111

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C1018

C1764

C1341

C2050

R915

C1146

R749

C1044

C1649

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C811

R380

C1317

R550

C1138

C1761

RN38

R441

R924

C998

R510

R752

C1671

C1305

C1982

R925

C1292

C1990

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C1286

C1260

RN14

C1681

C2013

R1008

R340

C1293

R574

L108

R412

C1299

R910

C935

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C1704

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C1098

C1000

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R746

R416

C1475

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C1664

C1773

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C2001

C1816

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C1907

R1045

R1053

C2136

C1975

C2039

C1159

C1525

C1272

R979

C1452

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C1091

C1129

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C2081

C1614

C1225

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C2121

C1967

C2041

R758

R344

C814

C1890

C1549

R587

C869

C832

C1998

R367

C1760

RN34

C1562

C1079

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C1864

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C1267

C1722

C1244

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C1670

C1226

C1099

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C1842

C1880

C2158

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C2032

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C971

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R942

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C2161

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C1171

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C987

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C1782

C1687

C984

C979 C980

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C1887

C1770

C906

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R324

RN26

R928

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C1852

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C1264

C2172

C1950

C1428

C1152

C1249

C1961

C947

C1544

R945

R624

C1196

C1844

C1326

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R528

C1903

R425

C2031

C1392

R838

C2176

R865

C2191

C916

R767

C864

R714

R395

C1250

R710

C1060

R539

C1607

C1796

C2059

R827

R897

R405

R962

C1609

R981

C1552

C1733

R541

R921

C1097

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R730

C842

C1624

C1689

C1046

C1173

C908

C2189

R947

C1020

R554

R493

C1338

R886

C1841

R719

C1407

C876

C1806

R816

C1241

C1163

C1834

C1734

C2071

R506

L89

C1875

C1631

C1613

C1373

C831

C1768

C1645

C1136

R690

R662

R327

C1801

C1458

C1333

C966

C858

R1002

R360

R336

C2192

C1838

R365

C1156

L95

R653

C1711

C1074

C1183

C957

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C1672

C1906

C1441

C1583

C1120

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C1512

C1478

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C2157

C1105

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C846

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C2102

C1873

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C1725

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C1618

C1635

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C1483

C1597

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C1194

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C2040

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C1242

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C1677

C2020

C2028

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C1698

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C1182

C1537

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U81

R807

R871

C866

C855

R858

R898

C824

C1572

C1238

C1543

C1680

C919

C1712

C1398

C1033

C1166

R776

C1468

C1281

C1587

C1140

R467

C1003

C2183

R386

C1685

R830

R516

C815

R856

C2131

C1301

C1714

R930

R929

C1586

U72

C1616

C1320

C1064

R1014

C883

C2003

C1100

C872

R454

C965

C1113

R982

C891

L79

C1420

C928

C1521

C2078

C1691

C2184

RN22

C1948

R751

C2035

C813

C1634

C1924

C1056

R651

C1814

L88

C1659

C2008

R1052

C1832

R938

C1926

L92

R932

R665

R611

C1516

C802

C819

Q2

R842

C820

R832

C1431

R422

C1255

C1445

R320

C1047

C1376

R638

C1257

C1117

R1019

R849

C1859

R1026

RN25

C1318

C1289

C1846

C1062

C1331

C1602

C867

C2088

C1825

C2052

C2011

C1350

R800

C1371

C1937

C1803

R483

R1055

C1312

R404

C1055

C1077

C1905

C2086

C2067

C1195

R562

C1310

R647

R492

R576

C1296

R621

R1004

R724

C1637

C1223

R583

R383

C1188

C901

C1308

R366

R772

C1454

C1992

C1576

C1507

C2181

C2015

R893

C1736

Q1

C1051

C1831

C1034

R789

R469

C1172

R591

C1271

C1384

C1640

C2133

R704

C893

U78

R794

R419

C1658

C810

C936

C1557

C1943

C1848

R1006

C1519

R696

C1275

C1606

C2047

R676

C1346

R371

C1547

C1541

C1304

C1515

C1679

C2005

C1788

C1917

C1174

R547

C1081

C2180

C1130

R847

C1654

C1566

L85

C1430

C943

L106

C946

C2014

C2082

C1052

R524

C2156

R805

C1214

C1657

Q4

R809

C1466

R703

R477

R697

C1464

C1110

R310

C807

C898

C1835

C1895

C1363

C1854

C1735

R685

R674

C1827

R694

C1716

R936

R863

R600

R628

C887

C1147

C1236

R976

C1190

R829

C1463

C1582

C1187

C830

C1287

R602

C1239

C822

C1528

C905

C868

C2044

C2080

C2056

R840

C2017

C1335

R590

R926

C1745

C1024

R804

SW2

C1237

C1962

R888

C1279

R931

R712

R447

C1176

C2021C1956

C969

C852

C1774

C1568

C1414

C1951

C1960

C1192

R303

C1707

C1413

C1881

C952

R427

R824

R899

C1322

R854

R363

R485

C1353

C1409

C2074

C1860

C1254

R705

C1396

C1121

R1058

R381

R1001

C1185

C1994

C1472

C1558

C1112

C1899

C1102

R641

C2174

C1252

C2151

C2155

C851

C1694

C2168

R548

C2018

C1347

C2193

R708

R490

C1314

C1601

C1485

R561

C1328

C2127

C1776

R348

R474

R960

C1933

R810

C1337

CR54

R438

C1648

R392

R1007

C924

R625

R879

C1122

C1203

C1573

C955

C1813

R578

C1840

C1503

C1486

C1551

C1104

R480

C1045

C975

RN29

C1719

R907

C841

C2054

R835

C1766

R667

C1339

C1199

C1290

C2134

R806

R826

C1405

C1554

C1619

R869

C1469

C2160

C1276

C1850

R549

C1010

C839

C1879

C2122

R984

R584

R895

C884

R596

C925

C1282

C970

R546

R796

R884

C1006

C1270

C1565

R678

R877

C1177

C1661

R922

R434

R391

R672

C850

C1588

C1268

C1197

RN28

R717

C954

C1520

C1394

R764

R961

C1972

C2091

C1569

R975

C2128

C1481

R645

R535

C1035

R820

C2079

C1263

C1563

C1824

C1978

C899

R709

R971

C1747

C2089

C950

C1217

R588

R481

C1866

C1767

R299

C1819

R777

RN24

C1453

C1612

C2085

C1432

R457

R466

R991

R346

C918

L80

C816

C911

C1273

C856

L84

R544

C1471

R874

R949

C1737

R798

C1125

C1342

C1298

R846

R556

C917

R684

R305

C2098

C1090

C1870

C1061

C2023

R657

C1311

C2190

R321

C1284

C1080

C967

R711

C1868

C1193

R825

C2073

C1861

C1916

R311

C1219

C1451

C1555

C2154

C2171

C1131

C2125

R593

C2075

R326

R523

R1043

R459

C1261

C1158

R540

L70

C1123

C1334

C1888

R755

C2093

C1674

C2022

C1180

C1561

C1070

C1786

C1448

C1433

R509

C1799

C961

C1032

R384

R880

C1354

R478

L107

R426

C1608

R595

C1345

C1867

C1678

R738

C1446

R335

C1042

C2077

R679

C1759

C1579

C1291

R908

C1913

C1911

C1699

RN17

C1303

L81

R1042

R615

R394

C1157

R864

C1830

R501

R452

R916

C1727

C1511

R572

R318

R495

C2063

R1030

C2042

R1011

C1845

C929

C1030

R620

R841

C1487

C1016

R522

R472

R309

C2055

R525

R940

R502

R851

R867

R890

C1932

Q5

R723

R622

C1765

C2024

R555

C1374

R689

R670

RN27

R649

C894

C2159

R333

C1666

R814

C1036

R786

C835

R388

R918

C1772

C1222

C1779

R471

R464

C978

C1753

C1625

C1181

C1538

C1361

C1966

RN18

C1898

C1927

R323

C1610

C1741

R505

R319

C1621

R387

R537

R769

R636

C1771

C1360

C2057

RN35

C1141

R413

R873

R787

C2097

C1940

R914

C2179

C951

R682

C1900

C2076

R680

R433

C1724

C1088

C1508

R792

C1748

C2169

C923

C1790

R663

C1349

C1093

C1126

C1527

R661

C1372

C1439

C838

C2010

R315

C1580

R660

R753

R409

C1548

C1492

C1143

R487

R756

C1622

C944

C915

C1560

C1939

R731

C1412

C1119

C907

R812

R985

C2166

R436

C1729

R511

R378

R445

C989

C1686

C1945

R570

R967

R567

R389

C1509

R424

C1300

L71

R423

R735

R565

C1863

R688

R770

C1103

C1936

C1069

C1262

C1209

C1368

C1826

RN20

R451

C1584

R923

C1386

R379

R486

C1701

C1791

C1883

C1743

C2163

C1575

C1351

R955

C1323

C1352

C1504

R322

R444

C1662

C1871

C1477

R418

C812

C1986

C1721

C1564

C1605

C2009

C2062

C1401

C1211

C1952

R791

C1891

C1949

R1029

C2092

C903

C1522

R594

C1784

C976

C1800

R860

R996

C1438

R797

C1632

C1078

R993

C1118

R845

C1644

C1307

C1072

R633

R545

R301

C1474

R514

C845

C1491

R739

C1489

C1377

C878

C1533

C992

R737

R400

C1938

R304

C1154

L101

C1603

C1114

C1416

C1355

R821

C1971

C1201

C1400

C1455

C1348

R793

R773

C1449

C1266

C1964

C1684

R1040

R421

C1577

C1479

C1643

C1053

C1380

C1728

C993

C1399

C1175

R721

R815

R950

R519

C2087

R458

R308

C1083

C1259

R488

C1408

C1789

C1435

C2084

R390

C806

C1058

C948

C972

R592

C1812

CR57

C1315

C949

C1014

C1946

R823

C1889

C1751

C1655

R564

C2002

C1912

C1820

C885

C1777

R640

C1094

C1370

R790

C983

R626

C1636

R885

R440

C1482

C1265

R905

C862

R668

C1571

C1007

R669

C1647

C1856

R952

U70

C914

C836

C1031

R644

C1595

R586

R937

C1029

C1095

R1046

C2066

R1016

R399

C1501

C1955

R1048

C2129

C1628

C1688

R589

C1332

R935

C2048

C1922

C1591

C1792

R1044

C1682

R683

R500

R866

Q3

R742

C1313

R435

R875

C2162

R527

R720

R358

C1996

C2072

C1805

C1574

C995

C818

C1216

C1369

R965

R316

R397

R904

R780

C1620

R476

L104

C847

R992

C1633

C1008

C940

C1947

R978

C1665

C1316

C1968

R370

C1757

C2033

C1411

R449

R357

C1109

R375

C897

C2025

R782

C1706

C2069

R374

C1170

C1976

C1918

R853

C1985

R939

R781

R442

C1617

C1023

C1434

R811

R314

R997

R577

C825

L87

C1422

C1941

C1387

R834

C2100

C1019

R948

C1953

R361

R432

C1134

R642

R900

C1744

C1001

C2186

R581

C1150

R969

C1837

C1437

C1754

C1041

R1017

R1022

R306

R695

C1797

C1876

C1224

R580

C1623

R779

C904

C1240

R998

R342

R585

C1793

C1865

R557

R870

L91

C1082

C1295

R1005

C1186

C1885

R722

R338

C1651

C1497

C1599

C1164

R428

R330

L93

R740

C1959

R521

R353

C1071

C1529

R325

C1210

C1510

R635

L102

C1178

R1012

C932

R956

C1165

C930

C1858

C1390

C1280

C912

C1277

R648

R675

R783

C960

R337

C1215

U71
PHY

R808

R1028

C809

R414

R503

C1732

L103

R489

C2043

R482

C1700

C1843

C1590

C1874

C1532

R627

C1410

C1027

C913

C2019

C1153

C1638

R843

R878

C1594

L82

R609

R420

C1343

C1756

C1904

C2173

R571

C1050

R623

R941

R300

C1993

C910

R497

R297

R560

C1798

U75

NAND

Flash

C1500

C1853

C1283

R302

C1067

C1297

C1783

C1306

C1205

C1139

C2058

R410

C1709

C1253

C1054

C1366

C808

C1021

C1989

R659

R687

C988

C805

C1440

R446

C857

C1022

R531

C1530

C895

C1362

C1278

R813

C1769

C1496

C1184

C1073

C1822

C1488

C1092

C973

C1869

C2030

R983

C1494

C1456

C1646

C1038

C1708

C1656

C1037

C2090

C1476

C2036

C1421

C1160

R747

C1229

C1559

R768

R345

R889

C1404

C1085

C1981

C945

RN30

R559

R951

C1447

C1808

C1124

C920

U73

C1930

R943

C1663

C1162

R372

R568

C1059

R844

C2061

C1925

C880

L78

R468

C1785

C1459

C1484

C1329

R903

R836

C1531

C1443

C1775

C2185

R686

R802

L74

C896

R632

C1495

R122

R298

L90

C2170

R861

C1213

R692

R616

R964

C2095

C1523

C2083

R760

C1043

C1535

C1269

R617

C1344

C1715

C1406

C1626

C1669

C1692

R607

C2012

C1817

R354

C1593

R598

C854

C1749

C1892

C1954

C2101

R407

C1427

R317

C1145

C1089

C1202

C1542

C1168

C1365

C1778

R718

C1025

C1750

C1393

R701

R788

C900

C1075

C1227

RN33

R655

C977

C1127

C1467

C1894

C1740

RN23

R331

R643

C1600

C1668

C931

R601

C1063

R536

C890

C1389

C2053

R439

C1921

C2178

R341

R356

R538

C1872

L98

C1086

R818

R980

C873

R376

C1005

C1169

C1232

C1191

R771

C1581

C865

C959

C843

C2130

C1915

R484

C827

R610

C1161

C1781

C1436

C1462

U76

StrataFlash

C1132

C1423

U69

R944

C1920

R518

C1795

R573

C1596

R989

R403

C1942

C1461

R868

C1206

R566

R599

C1553

C1695

U68

PHY

R741

C1862

C1598

C2070

R732

R606

C1919

C1804

R953

C1149

C1415

R901

R729

C1144

C1049

C2135

C1076

C1929

C1246

C1087

U79

C1325

R654

C1893

C1403

C997

C1274

R1018

C1040

C879

C1752

C1148

RN19

C1821

C834

C996

RN15

R455

C938

R852

R894

C1108

C1285

C1604

R977

C1815

C1807

C1245

C804

C1493

C874

C1983

R778

C803

R504

R461

C1702

C886

C1984

R745

R634

R906

C999

R859

C909

R393

C1096

C829

C1385

C1151

C1550

C1526

C860

C1358

R629

C1324

C1787

C1208

U80

R699

C1653

C1758

C875

R382

C1836

C1886

R475

C1723

C1969

R529

C1809

C1847

R785

R959

C2049

C1057

C1627

R1033

R673

R934

C1068

R408

C1425

C1302

C991

R313

C2187

R990

C1258

C1251

R987

C2026

C1517

R973

C848

C1457

R855

C1629

C1697

R359

R543

C1615

R512

C922

R614

C870

C1974

R373

R448

C1763

C1426

C1382

C823

C1696

C1673

C1545

R850

R715

C1388

C889

C986

C1963

C1944

R933

R1013

C1336

C1585

C934

C2167

C964

C1630

C1540

C1589

L86

C942

C1084

C1828

R496

C2046

R744

C1908

C1200

R532

R766

C828

C1116

RN32

C2060

R605

C1502

R1038

C1460

R307

C1247

C1780

C1730

C1524

C1009

Figure 2-3: Component Map, Bottom (Rev. 01)

2-4

ATCA-9305 User’s Manual 10009109-01

Setup: ATCA-9305 Circuit Board

CR1 - P2_LED_GPIO12-R
CR2 - P2_LED_GPIO13-R
CR3 - P2_LED_GPIO14-R
CR4 - P2_LED_GPIO15-R

CR23 - MIP1_LED1_R
CR24 - MIP1_LED2_R
CR25 - MIP1_LED3_R
CR26 - MIP1_LED4_R

CR50 - P1_LED_GPIO12_R1
CR51 - P1_LED_GPIO13_R1
CR52 - P1_LED_GPIO14_R1
CR53 - P1_LED_GPIO15_R1

IPMP State

CR35 - STATE_LED8
CR36 - STATE_LED7
CR37 - STATE_LED6
CR38 - STATE_LED5
CR39 - STATE_LED4
CR40 - STATE_LED3
CR41 - STATE_LED2
CR42 - STATE_LED1
CR43 - STATE_LED0

SW1 - IPMC Reset

F3 - .75 Amp Fuse
(self resetting)

F10 - .75 Amp Fuse
(self resetting)

F2 - .75 Amp Fuse
(self resetting)

F1 - .75 Amp Fuse
(self resetting)

F4 - 1 Amp Fuse
F5 - 1 Amp Fuse
F6 - 10 Amp Fuse
F7 - 8 Amp Fuse
F8 - 10 Amp Fuse
F9 - 8 Amp Fuse

Ethernet

CR15 - TSEC2_ACTIVITY

Ethernet

CR44 - BC1_LINKSPD1/2
CR45 - BC1_LINKSPD1/2
CR46 - BC1_ACT*
CR47 - BC2_LINKSPD1/2
CR48 - BC2_LINKSPD1/2
CR49 - BC2_ACT*

MPC8548

CR13 - PQ_GREENLED_R*
CR14 - PQ_CKSTP_OUT_R*
CR16 - PQ_REDLED_R*

Debug

CR18 - DEBUG_LED1_R*
CR19 - DEBUG_LED2_R*
CR21 - DEBUG_LED3_R*
CR22 - DEBUG_LED43_R*

Boot Device

CR31 - FL0_LED_R*
CR32 - FL1_LED_R*
CR33 - SKT_LED_R*

+

+

+

+

CR49

CR26

JP1

CR19

CR3

CR25

CR50

F4

CR51

F9

CR1

CR18

CR4

CR46

F6

F8

CR15

CR21

CR2

SW1

CR14

CR32

CR45

CR31

CR33

CR23

CR16

F5

CR22

CR52

CR48

CR24

CR47

J9

CR13

CR35

CR38

CR40

CR36

CR39

CR43

CR37

CR42

CR41

CR53

CR44

F7

J1

P2

J15

F10

F1

F2

F3

Figure 2-4: LED, Fuse and Switch Locations, Top

10009109-01 ATCA- 9305 User’s Manual

2-5

Setup: ATCA-9305 Circuit Board

J16

Front Panel

CR54 - Red = LED1R_CONN
Amber = LED1A_CONN
CR55 - LED2_CONN
CR56 - LED3_CONN

SW2 - Front Panel Reset

Hot Swap

CR57 - BLUE_LED_CONN_K

CR56 CR57

CR54

SW2

CR55

Figure 2-5: LED and Switch Locations, Bottom

2-6

ATCA-9305 User’s Manual 10009109-01

Setup: ATCA-9305 Circuit Board

Connectors

The ATCA-9305 circuit board has various connectors and headers (see the figures beginning
on page 2-3), summarized as follows:

J1: This 14-pin JTAG header is used for debugging CN5860 processor 2. See

Ta bl e 3- 7 .

J3-J6: These 240-pin sockets are installed for the CN5860 processor 1 DDR2 SDRAM memory.

J9: This 14-pin configuration header allows selection of boot device, and MPC8548 configura-

tion for the configuration SROM. See

Fig. 2-6.

J11-J14: These 240-pin sockets are installed for the CN5860 processor 2 DDR2 SDRAM memory.

J15: This 14-pin JTAG header is used for debugging CN5860 processor 1. See

Ta bl e 3- 7 .

J23: The 80-pin Zone 2 connector provides 1 GB and 10 GB Ethernet access to the backplane, see

Ta bl e 8- 2 .

J30-J31: The 80-pin Zone 3 connectors route PCIe and XAUI (10G) to the optional RTM. See

and

Ta bl e 8- 4 for pin assignments.

Ta bl e 8- 3

J33: The 24-pin Zone 3 connector routes the reset, Hot Swap, MPC8548 console, power, and

2

IPMC I

C to the optional RTM, see Ta bl e 8 -5 .

JP1: This is the 10-pin programming header for the IPMP, CPLD, and SPI 10G (1-4) devices, see

Ta bl e 7- 5 1 .

P1: This 14-pin RJ45 connector with LEDs routes the Three-speed Ethernet Controller (TSEC1)

between the MPC8548 and the front panel. See

P2: This 16-pin JTAG debug header accesses the MPC8548 processor, see

Ta bl e 6- 4 for pin assignments.

Ta bl e 4- 7 .

P3: This 14-pin RJ45 connector with LEDs routes Ethernet (FP1) between the switch and the

front panel, see

Ta bl e 6- 4 for pin assignments.

P4: The 5-pin vertical mini-B USB provides the IPMP EIA-232 console debug, see

Ta bl e 7- 5 2 .

P5, P6: These 5-pin vertical mini-B USBs are the CN5860 console and for factory debug use only.

P7: This 5-pin mini-B USB is the console serial port for the MPC8548 management processor,

see

Ta bl e 4- 8 .

P10: The 30-pin Zone 1 connector routes IPMB to the backplane, see

10009109-01 ATCA- 9305 User’s Manual

Ta bl e 8- 1 .

2-7

Setup: ATCA-9305 Setup

Configuration Header

There are a total of seven jumper pairs on J9 (pins 11-14 are spare posts). See figure Fig. 2-2
for the jumper location on the ATCA-9305. Also reference the “Jumper Settings (0x18)” reg­ister.

Figure 2-6: Configuration Header, J9

13 11 9 7 5 3 1

14 12 10 8 6 4 2

PROG

BOOT

STAND

IG ROM

BT FLASH

BT SKT: A shunt on pins 1-2 selects the 512 KB socketed ROM as the boot device for the MPC8548.

IG SROM: If the serial ROM configuration jumper is installed (pins 3-4), the ATCA-9305 will not try to

configure (IGNORE_SROM*) from the MPC8548 serial ROM.

REDIR EN: A shunt installed on pins 5-6 disables the boot redirection, see page 7-41 for more informa-

tion.

REDIR EN

BT SKT

BOOT: A shunt on pins 7-8 causes both Cavium CN5860s to boot from their local bus and not boot

over PCI.

STAND: A shunt on pins 9-10, IPMC stand alone mode, allows the board to boot without manage-

ment control.

PROG: Installing a shunt on pins 11-12 puts the IPMC controller into programming mode. This is

only used in the factory to configure the IPMC.

BT FLASH: If BOOT shunt is installed (booting from local bus), this shunt determines whether the boot

is from local flash or socket. When this BT FLASH shunt is installed, the ATCA-9305 boots
from flash. Otherwise, it boots from the socket.

ATCA-9305 SETUP

You need the following items to set up and check the operation of the Emerson ATCA-9305:

ATCA chassis and power supply

MPC8548 Console cable for EIA-232 port, Emerson part # C0007662-00

Computer terminal

Save the antistatic bag and box for future shipping or storage.

2-8

ATCA-9305 User’s Manual 10009109-01

Setup: ATCA-9305 Setup

Power Requirements

The ATCA-9305 circuit board uses —48 volts from the backplane to derive 3.3 volts for the
IPMC and 12 volts for payload power.

Table 2-2: Typical Power Requirements

Configuration: Power:

1.0 GHz MPC8548 and 800 MHz Cavium processors,
board running at room temperature with all
processors at U-Boot prompt

The exact power requirements for the ATCA-9305 circuit board depend upon the specific
configuration of the board, including the CPU frequency and amount of memory installed
on the board. Please contact Emerson Technical Support at 1-800-327-1251 if you have
specific questions regarding the board’s power requirements.

Environmental Considerations

As with any printed circuit board, be sure that air flow to the board is adequate. Chassis con­straints and other factors greatly affect the air flow rate. The environmental requirements
are as follows:

Table 2-3: Environmental Requirements

135 watts

Environment: Range: Relative Humidity:

Operating Temperature 0° to +55° Centigrade, ambient

(at board)

Storage Temperature —40° to 85° Centigrade Not to exceed 95%

Altitude 0 to 4,000 meters above sea

level

Air Flow Requires 30 CFM at 55° Centigrade at sea level. Meets thermal

performance requirements of CP-TA ATCA ICD Book 1.1Class B-2

10009109-01 ATCA- 9305 User’s Manual

Not to exceed 85% (non­condensing)

(non-condensing)
—

2-9

Setup: ATCA-9305 Setup

Figure 2-7: Air Flow Graph

2-10

Hot Swap

The ATCA-9305 can be Hot Swapped, as defined in the AdvancedTCA specification (see ref­erence in
in a typical AdvancedTCA system. (These procedures assume the system is using a shelf
manager.)

Note: The ATCA-9305 Rear Transistion Module (RTM) has its own Hot Swap LED and switch, and it can be Hot

Swapped in/out independently of the front board. If the front board is not present, then the RTM will not be
powered. If the front board is Hot Swapped out, the RTM’s blue LED will illuminate. In either case, the RTM can
be safely removed.

ATCA-9305 User’s Manual 10009109-01

Ta bl e 1 - 2 ). This section describes how to insert and extract an ATCA-9305 module

Setup: Troubleshooting

!

Insert a board:

1 Insert the ATCA-9305 into an available slot.

2 Push in the front panel handle (tab).

The blue Hot Swap LED on the front panel (see
board insertion is in progress and system management software is activating the slot. Then
the blue LED turns off, indicating the insertion process is complete, and payload power is
present.

Remove a board:

1 Pull out the handle (tab) on the ATCA-9305 front panel one click.

A short blink indicates the board is requesting permission for extraction.

2 Remove the board when the blue LED on the front panel is on (no payload power).

Caution: Do not remove the ATCA-9305 while the blue LED is blinking.

Fig. 2-1) flashes a long blink to indicate that

TRO UB LESHOO TI NG

In case of difficulty, use the following checklist:

Be sure the ATCA-9305 circuit board is seated firmly in the carrier.

Be sure the system is not overheating.

Check the cables and connectors to be certain they are secure.

Check that your terminal is connected to a console port.

Technical Support

If you need help resolving a problem with your ATCA-9305, visit
http://www.emersonembeddedcomputing.com/ on the internet or send E-mail to sup­[e-mail]. Please have the following information handy:

• ATCA-9305 serial number and product identification (see

• MPC8548 monitor version number (see

• Cavium monitor version number (see

• version and part number of the operating system (if applicable)

10009109-01 ATCA- 9305 User’s Manual

Fig. 9-1)

Fig. 3-3)

Fig. 2-8)

2-11

Setup: Troubleshooting

Product ID

Serial Number

• whether your board has been customized for options such as a higher processor speed or
additional memory

• license agreements (if applicable)

If you do not have internet access, please call Emerson for further assistance:

Figure 2-8: Serial Number and Product ID on Top Side

[phone] or [phone] (US)

44-131-475-7070 (UK)

2-12

Product Repair

If you plan to return the board to Emerson Network Power for service, visit
http://www.emersonembeddedcomputing.com/ on the internet or send E-mail to servi­[e-mail] to obtain a Return Merchandise Authorization (RMA) number. We
will ask you to list which items you are returning and the board serial number, plus your pur­chase order number and billing information if your ATCA-9305 hardware is out of warranty.
Contact our Test and Repair Services Department for any warranty questions. If you return
the board, be sure to enclose it in an antistatic bag, such as the one in which it was originally
shipped. Send it prepaid to:

Emerson Network Power, Embedded Computing
Test and Repair Services Department
8310 Excelsior Drive
Madison, WI 53717

ATCA-9305 User’s Manual 10009109-01

RMA #____________

Setup: Troubleshooting

Please put the RMA number on the outside of the package so we can handle your problem
efficiently. Our service department cannot accept material received without an RMA num­ber.

Comments and Suggestions

We welcome and appreciate your comments on our documentation. We want to know
what you think about our manuals and how we can make them better.

Mail comments to us by filling out the following online form:
http://www.emersonnetworkpowerembeddedcomputing.com/ Contact Us > Online Form

In “Area of Interest” select “Technical Documentation”. Be sure to include the title, part
number, and revision of the manual and tell us how you used it.

10009109-01 ATCA- 9305 User’s Manual

2-13

(blank page)

2-14

ATCA-9305 User’s Manual 10009109-01

Cavium Processor Complex

Console

(ENG use only)

PCI Bus

I2C

EEPROM

COP/
JTAG

BCM56802

XAUI 10 Gb

Switch

5 XAUI

XAUI 13

XAUI 14

PCI Bus

IDSEL13

6 XAUI

Console

(ENG use only)

Cavium

Octeon
CN5860

Processor 1

SPI-1

PCI
Bus

IDSEL11

Serial 0D1_DDR2

I2C

Serial 1

SPI-0

Stratix II GX

#2

RLDRAM

64MB

Local Bus

Addr/Data

COP/

JTAG

Serial CFG

EEPROM

RLDRAM

64MB

P1 DDR
SDRAM

P2 DDR2

SDRAM

RLDRAM

64MB

RLDRAM

64MB

I2C

EEPROM

RLDRAM

64MB

RLDRAM

64MB

RLDRAM

64MB

RLDRAM

64MB

Stratix II GX

#1

Stratix II GX

#4

I2CI2C

Stratix II GX

#3

Cavium

Octeon

CN5860

Processor 2

Serial 0

Serial 1

D1_DDR2

I2C

SPI-1

SPI-0

Local Bus

Addr/Data

PCI
Bus
IDSEL12

Cavium Processor Complex 1 Cavium Processor Complex 2

NOR
Flash

4M x8

Socketed

ROM

512K x8

NOR

Flash

4M x8

Socketed

ROM

512K x8

The ATCA-9305 provides two Cavium processor complexes. The major devices on each
complex consist of the Cavium CN5860 processor, two StratixGX bridges, SDRAM,
RLDRAM®, an I

Figure 3-1: Cavium Processor Complex Block Diagram

2

C EEPROM, socketed ROM, Flash, and the PCI bus interface.

Section 3

CAVIUM CN5860 PROCESSOR

The main features of the CN5860 include:

Table 3-1: CN5860 Features

Feature: Description:

Processor Core Up to 16 cnMIPS™ cores
Core Speed

Network Services Processor (NSP)
System Packet Interface Two SPI-4.2 ports
L2 Cache 2 MB, eight-way set associative
DRAM 144-bit DDR2 DRAM interface
RLDRAM 18-bit RLDRAM, low-latency memory direct access
PCI 64-bit, PCI 2.3 compatible

up to 800 MHz, processing up to 30 million packets per second

10009109-01 ATCA- 9305 User’s Manual

3-1

Cavium Processor Complex: PCI

The CN5860 and switch route packets using SPI-4.2 and control information flow using PCI.
The CN5860 has two SPI-4.2 interfaces with each one supporting up to 16 ports. Two high­speed SPI-4.2 Altera (Stratix™ GX) FPGAs function as the SPI-to-XAUI bridge for each pro­cessor to switch complex. The PCI interface supports up to four ports, consequently a total
of 36 ports can be supported internally by each CN5860.

Cavium Memory Map

Although the Cavium processors are 64-bit, the ATCA-9305 uses a 49-bit implementation.
Refer to the Cavium Networks OCTEON Plus CN58xx Hardware Reference Manual for more
detailed information on the memory map.

Table 3-2: Cavium Address Summary

Hex Physical
Address: Register Description:

1,2000,0000,0000 reserved
1,1F00,0000,0000 Cavium Hardware registers
1,1E00,0000,0000 PCI Memory Space (6)
1,1D00,0000,0000 PCI Memory Space (5)
1,1C00,0000,0000 PCI Memory Space (4)
1,1B00,0000,0000 PCI Memory Space (3)
1,1A00,0000,0000 PCI I/O Space
1,1910,0000,0000 reserved
1,1900,0000,0000 PCI Special Space
1,0700,0000,0000 CN58xx Registers
1,0001,0000,0000 reserved
1,0000,0000,0000 Local Boot Bus
0,0004,1000,0000 DDR2 SDRAM, middle block (256-512 MB)
0,0004,0000,0000 reserved
0,0000,2000,0000 DDR2 SDRAM, upper block (512 MB-2 GB)
0,0000,1000,0000 reserved
0,0000,0000,0000 DDR2 SDRAM, bottom block (256 MB)

1. This depends on how much memory is installed.

1

PCI

The Cavium is a slave device on the PCI bus. The Cavium U-boot monitor image is provided
by the MPC8548 management processor via PCI. The MPC8548 monitors the Cavium boot
status and has the ability to try alternate boot images if the current one fails.

3-2

ATCA-9305 User’s Manual 10009109-01

Cavium Processor Complex: PCI

The CN5860 processor is designed such that another PCI device can initialize its memory
interface, copy code over PCI into its local memory space, and then write a boot release reg­ister.

CN5860 Boot Over PCI

The PCI bus is configured to run at 66 MHz in 64-bit conventional PCI mode. On power-up,
the CN5860 processor’s 16 internal cores are held in reset. The MPC8548 management pro­cessor performs the following steps:

1 Initialize the CN5860 RAM.

2 Copy the CN5860 U-boot to the CN5860 RAM.

3 Copy boot code to the reset vector to jump to the U-boot code in RAM.

4 Release the CN5860 processor cores from reset.

5 Receive return codes from the CN5860 that indicate any boot or POST errors and take the

appropriate action.

The management processor (MPC8548) monitor implements a utility to load non-volatile
memory redundant U-boot images for the CN5860 processors. The utility tags each copy as
primary or secondary.

10009109-01 ATCA- 9305 User’s Manual

3-3

Cavium Processor Complex: PCI

Voltage
Monitor

Delay

IPMC

Stratix II GX

XAUI #2

P1 DDR
SDRAM

Stratix II GX

XAUI #1

Stratix II GX

XAUI #4

Stratix II GX

XAUI #3

KSL

CPLD

P1_RESET*

CN5860
Cavium

Processor 1

P1_PCI_RST*

P1_PWRGD

P1_DDR_RST*

MIP1_RST*

MIP2_RST*

MIP3_RST*

MIP4_RST*

CN5860
Cavium

Processor 2

P2_RESET*

P2_PCI_RST*

P2_PWRGD

P2 DDR
SDRAM

P2_DDR_RST*

IPMP

CPLD

PWRGD_OK

L_PAYLD_EN
3_3V_PWRGD
2_5V_PWRGD
1_8V_PWRGD
1_2V_PWRGD
1_0V_PWRGD

PQ_CORE_PWRGD

P1_CORE_PWRGD
P2_CORE_PWRGD

POR_RST*

48A_OK

48B_OK

E_HANDLE

I2C IO

Port

L_PAYLOAD_RST*

PRIV_I2C_SCL

PRIV_I2C_SDA

IPMC_PO_RST*

3_3V_MP

3_3V_MP

Hot Swap

Switch

3_3V_MP

3_3V_MP

Front

Panel

Reset

3_3V

Voltage
Monitor

Delay

33MHz

IPMC_PO_RST*

Cavium Reset

Each CN5860 can be reset independently of the other processor without affecting its opera­tion. This task is performed by the MPC8548 management processor.

Figure 3-2: CN5860 Reset Diagram

3-4

ATCA-9305 User’s Manual 10009109-01

Cavium Processor Complex: Cavium Ethernet

CAVIUM ETHERNET

The Ethernet address for your board is a unique identifier on a network. The address con­sists of 48 bits (MAC [47:0]) divided into two equal parts. The upper 24 bits define a unique
identifier that has been assigned to Emerson Network Power, Embedded Computing by
IEEE. The lower 24 bits are defined by Emerson for identification of each of our products.

The Ethernet address for the ATCA-9305 is a binary number referenced as 12 hexadecimal
digits separated into pairs, with each pair representing eight bits. The address assigned to
the ATCA-9305 has the following form:

00 80 F9 xx yy zz

00 80 F9 is Emerson’s identifier. The last three bytes of the Ethernet address consist of the
port (one byte); 0x99(SPI 1), 0x9A (SPI 2), 0x9B (SPI 3), or 0x9C (SPI 4), followed by the serial
number (two byte hexadecimal). The ATCA-9305 Cavium has been assigned the Ethernet
address range 00:80:F9:99:00:00 to 00:80:F9:9C:FF:FF. The format is shown in

Table 3-3: Ethernet Port Address

Offset: MAC: Description: Ethernet Identifier (hex):

Byte 5 15:0 LSB of (serial number in hex) —
Byte 4 MSB of (serial number in hex) —
Byte 3 23:16 SPI 1

SPI 2
SPI 3

SPI 4
Byte 2 47:24 Assigned to Emerson by IEEE 0xF9
Byte 1 0x80
Byte 0 0x00

0x99
0x9A
0x9B
0x9C

Ta bl e 3- 3 .

The last two bytes, MAC[15:0], are calculated from the serial number stored in the Cavium
EEPROM. This corresponds to the following formula: n —1000, where n is the unique serial
number assigned to each board. So if an ATCA-9305 serial number is 1032, the calculated
value is 32 (20

), and the default Ethernet port addresses are:

16

• Cavium 1 SPI 1 MAC address is: 0x00 0x80 0xF9 0x99 0x00 0x20

• Cavium 1 SPI 2 MAC address is: 0x00 0x80 0xF9 0x9A 0x00 0x20

• Cavium 2 SPI 1 MAC address is: 0x00 0x80 0xF9 0x9B 0x00 0x20

• Cavium 2 SPI 2 MAC address is: 0x00 0x80 0xF9 0x9C 0x00 0x20

10009109-01 ATCA- 9305 User’s Manual

3-5

Cavium Processor Complex: Cavium Monitor

Hardware initialization

Monitor command prompt

U-Boot 1.1.1 (Jan 16 2009 - 14:26:14)0.9

OCTEON CN58XX-NSP revision: 1
Core clock: 750 MHz
DDR clock: 266 MHz (533 Mhz data rate)
DRAM: 4096 MB
Flash: 4 MB

Clearing DRAM........ done

PCI console init succeeded, 1 consoles, 1024 bytes each
Net: octspi0, octspi1
RLDRAM not present
Octeon BIST Passed
POST i2c PASSED
POST memory PASSED
2 ATCA-9305 (Mon 0.9)=>

CAVIUM MONITOR

The primary function of the monitor software is to transfer control of the hardware to the
user’s application. Secondary responsibilities include:

• low-level initialization of the hardware

•diagnostic tests

• low-level monitor commands/functions to aid in debug

Start-up Display

At power-up or after a reset, the Cavium monitor runs diagnostics and reports the results in
the start-up display, see an example in
configures the board according to the environment variables (see “MPC8548 Environment
Variables” on page 9-26). If the configuration indicates that autoboot is enabled, the moni­tor attempts to load the application from the specified device. If the monitor is not config­ured for autoboot or a failure occurs during power-up, the monitor enters normal
command-line mode. The monitor command prompt in
hardware boot of the ATCA-9305.

Figure 3-3: Example Cavium CN5860 Monitor Start-up Display

Fig. 3-3. During the power-up sequence, the monitor

Fig. 3-3 is the result of a successful

3-6

ATCA-9305 User’s Manual 10009109-01

Note: There will be either a 1 or 2 in front of the monitor prompt indicating which Cavium processor is prompting.

Power-up/Reset Sequence

The Cavium CN5860 processor follows the boot sequence in Fig. 3-4 before auto-booting
the operating system or application software. At power-up or board reset, the monitor per­forms hardware initialization, diagnostic routines, autoboot procedures, and if necessary,
invokes the command line. See

Ta bl e 3- 5 for default Cavium environment variables settings.

Cavium Processor Complex: Cavium Monitor

Power-up or Reset

Cavium Hardware

Wait for PCI load of U-boot

U-Boot Monitor

Default Board Initialization

U-Boot Monitor

Execute POST

U-Boot Monitor

Start Autoboot Sequence

(Boot Operating System)

Operating System Boot

Boot OS image

according to

configuration parameters

Figure 3-4: Power-up/Reset CN5860 Boot Sequence Flowchart

Diagnostic Tests During Power-up and Reset

The Cavium monitor diagnostic tests can be executed during power-up or invoked from the
monitor’s command prompt. This is accomplished by changing the state of the monitor
configuration parameters that define power-up and reset diagnostics mode. If the poweron-
diags parameter is set to “on”, the monitor invokes the diagnostic tests after a reset of the
hardware. Results are displayed to the console including whether the test passed or failed.

POST Diagnostic Results

The ATCA-9305 Power-On Self-Test (POST) diagnostic results are stored as a 32-bit value in
memor y acces sible by the management console at locatio n 0x80 080A6C. E ach bit indicates
the result of a specific test, so this field can store the results of up to 32 diagnostic tests.

Ta bl e 3- 4 assigns the bits to specific tests.

10009109-01 ATCA- 9305 User’s Manual

3-7

Cavium Processor Complex: Cavium Monitor

Table 3-4: POST Diagnostic Results–Bit Assignments

Diagnostic

Bit:

0-1 Reser ved
2 DRAM Verify address and data lines are intact
3Cavium BIST­4I

5-31 Reser ved

Cavium Environment Variables

The following table lists the standard Cavium environment variables:

Table 3-5: Standard Cavium Environment Variables

Var iabl e:

baudrate 115200 Console port baud rate

bootcmd " " Command to execute when auto-booting or executing

bootdelay 0 Choose the number of seconds the Monitor counts down

bootfile " " Path to boot file on server (used with TFTP)—set this to

ethaddr undefined SPI 1 MAC address
eth1addr undefined SPI 2 MAC address
ethact octspi0 Specifies Ethernet port to use
gatewayip 0.0.0.0 Select the network gateway machine IP address
hostname none Target hostname
ipaddr 0.0.0.0 Board IP address
loadaddr 0x20000000 Define the address to download user application code

netmask 0.0.0.0 Board sub-network mask
powerondiags off Turns POST diagnostics on or off after power-on/reset

rootpath eng/ Path name of the NFS’ server root file system
serial# xxxxx Board serial number
serverip 0.0.0.0 Boot server IP address
stderr serial Sets the standard destination for console error reporting

Tes t: De sc ri pt io n: Va lu e:

2

C Verify all local I2C devices are connected

to the I

2

C bus

Default
Value: Description:

Valid rates: 9600, 14400, 19200, 38400, 57600, 115200

the ‘bootd’ command

before booting user application code
Valid options: time in seconds, -1 to disable autoboot

“path/file.bin” to specify filename and location of the file
to load.

(used with TFTP)

Valid options: on, off

Valid options: serial, pci

0 Passed the test

1 Failure detected

3-8

ATCA-9305 User’s Manual 10009109-01

Cavium Processor Complex: Memory

Default

Var iabl e:

stdin serial Sets the standard source for console input

stdout serial Sets the standard destination for console output

MEMORY

The processor complex supports DDR2 Synchronous DRAM (SDRAM) and Reduced Latency
DRAM (RLDRAM) memory devices.

DDR2 SDRAM

The ATCA-9305 supports up to 16 gigabytes of 144-bit wide DDR2 SDRAM per processor
complex. The SDRAM interface clock speed frequency is 400 MHz. The four low-profile,
dual-inline memory modules (buffered DIMM) are installed in 240-pin very low profile (VLP)
sockets to reduce board density and routing constraints. A 2 KB EEPROM on the DIMM pro­vides the serial presence detection (SPD). On-card SDRAM occupies physical addresses
from 0,0000,0000,0000

Each processor memory bus is operating in 144-bit mode. Error-correcting Code (ECC) is
performed on the memory bus so that the CN5860 detects all double-bit errors, multi-bit
errors within a nibble, and corrects all single-bit errors.

Value: Description: (continued)

Valid options: serial, pci

Valid options: serial, pci

to 0,0003,FFFF,FFFF16.

16

RLDRAM

Each CN5860 supports 256 MB Common I/O (CIO) RLDRAM operating up to 400 MHz
(depends on the processor speed). The Micron RLDRAM II is organized as 32Mx18x8 internal
banks. The DDR I/O interface transfers two data words per clock cycle. Output data is refer­enced to the free-running output data clock. Read and write accesses to the RLDRAM are
burst-oriented. RLDRAM is accessed by using Cavium-specific instructions which operate on
MIPS Coprocessor 2.

I2C EEPROM

Each Cavium processor complex has one user EEPROM device for parameter storage located

2

on the I
from the other CN5860 processor and MPC8548 processor I
serial EEPROM on each CN5860 processor I
input and the Serial Data (SDA) bidirectional lines.

C bus, address 0xA8. The I2C bus for each processor is completely independent

2

2

C interface consists of the Serial Clock (SCL)

10009109-01 ATCA- 9305 User’s Manual

C buses. The Atmel two-wire

3-9

Cavium Processor Complex: StratixGX Interconnect

Table 3-6: Cavium NVRAM Memory Map

Address Offset
(hex): Description:

0x1E00-0x1FFF Monitor parameters 256
0x0000-0x1D36 User defined 79F

Window
Size (bytes)

Flash, 512 KB x 8

The 512 KB of 32-pin PLCC socketed flash starts at physical address1D46,0000
for Engineering code.

The StrataFlash features high-performance fast asynchronous access

times, low power, and flexible security options.

and is used

16

Flash, 4 MB x 16

The 4 MB soldered NOR flash starts at physical address 1D05,0000
provides CN5860 code storage and non-volatile memory.

The 32-Mbit device

16.

STRATIXGX INTERCONNECT

The Altera StratixGX FPGA provides the high-speed SPI-4.2 interconnect. Each complex has
dual SPI-to-XAUI bridges connected to the XAUI Ethernet switch ports.

PLD Registers

The FPGA bridge is located at address 0x1D030000. Use the following registers to access
the XAUI to SPI bridge configuration registers. See the “Read Example” and “Write Exam­ple.”

3-10

Data Registers

Register 3-1: Data 31:24 (0x0)

Bits: R/W: Function:

7R/WData 31
6R/WData 30
5R/WData 29
4R/WData 28
3R/WData 27
2R/WData 26
1R/WData 25
0R/WData 24

ATCA-9305 User’s Manual 10009109-01

Cavium Processor Complex: StratixGX Interconnect

Register 3-2: Data 23:16 (0x1)

Bits: R/W: Function:

7R/WData 23
6R/WData 22
5R/WData 21
4R/WData 20
3R/WData 19
2R/WData 18
1R/WData 17
0R/WData 16

Register 3-3: Data 15:8 (0x2)

Bits: R/W: Function:

7R/WData 15
6R/WData 14
5R/WData 13
4R/WData 12
3R/WData 11
2R/WData 10
1R/WData 9
0R/WData 8

Register 3-4: Data 7:0 (0x3)

Bits: R/W: Function:

7R/WData 7
6R/WData 6
5R/WData 5
4R/WData 4
3R/WData 3
2R/WData 2
1R/WData 1
0R/WData 0

10009109-01 ATCA- 9305 User’s Manual

3-11

Cavium Processor Complex: StratixGX Interconnect

Address Registers

Register 3-5: Address 9:8 (0x4)

Bits: R/W: Function:

7 — Reserved
6 —
5 —
4 —
3 —
2 —
1R/WAddress 9
0R/WAddress 8

Register 3-6: Address 7:0 (0x5)

Bits: R/W: Function:

7R/WAddress 7
6R/WAddress 6
5R/WAddress 5
4R/WAddress 4
3R/WAddress 3
2R/WAddress 2
1R/WAddress 1
0R/WAddress 0

3-12

Control Register

The write only Control register performs two functions:

• Writing a value of 0x01 causes the contents of the Data registers to be written to the

FPGA bridge at the location specified by the Address registers.

• Writing a value of 0x02 causes the contents of the Data registers to be overwritten by the

contents of the FPGA bridge at the location specified by the Address registers.

Note: Writing any other value to the Control register will be ignored.

Register 3-7: Control (0x6)

Bits: R/W: Function:

7 — Reserved
6 —
5 —
4 —
3 —
2 —

ATCA-9305 User’s Manual 10009109-01

Cavium Processor Complex: StratixGX Interconnect

Bits: R/W: Function:

1W Read
0W Write

Version Register

This read-only register tracks the PLD versions. The version is hard coded in the PLD and
changes with every released code change. Version starts at 01

Register 3-8: Vers ion (0x7)

Bits: R/W: Function:

7R 0x01
6R
5R
4R
3R
2R
1R
0R

.

16

Scratch Register

All registers in this range act as the same register.

Register 3-9: Scratch (0x8-0x3F)

Bits: R/W: Function:

7R/W
6R/W
5R/W
4R/W
3R/W
2R/W
1R/W
0R/W

Read Example: To read the FPGA bridge SPI_COMMAND register at 0x204, use the following commands.

Set address bits 9:8.

=>write64b 1d030004 02

Set address bits 7:0.

=>write64b 1d030005 04

10009109-01 ATCA- 9305 User’s Manual

3-13

Cavium Processor Complex: Headers and Connectors

Perform a read.

=>write64b 1d030006 02

Display the results.

=>read64l 1d030000

Write Example: To write to the FPGA bridge MAC_CMD_CFG register at 0x00C, use the following com-

mands.

Set data bits 31:24.

=>write64b 1d030000 a9

Set data bits 23:16.

=>write64b 1d030001 b8

Set data bits 15:8.

=>write64b 1d030002 c7

Set data bits 7:0.

=>write64b 1d030003 d6

Set address bits 9:8.

=>write64b 1d030004 00

Set address bits 7:0.

=>write64b 1d030005 0c

Perform a write.

=>write64b 1d030006 01

HEADERS AND CONNECTORS

COP/JTAG Headers

The CN5860 processor complex uses headers J1 and J15 for debug.

Table 3-7: CN5860 Processor COP/JTAG Headers

Pin: J1 (processor 2): J15 (processor 1):

1 P2_ETRST* P1_ETRST*
2 ground ground
3P2_TDI P1_TDI
4 ground ground

3-14

ATCA-9305 User’s Manual 10009109-01

Cavium Processor Complex: Headers and Connectors

Pin: J1 (processor 2): J15 (processor 1): (continued)

5P2_ETDO P1_ETDO
6 ground ground
7P2_TMS P1_TMS
8 ground ground
9 P2_ TCK P 1_TC K
10 ground ground
11 P2_EJTAG_RST P1_EJTAG_RST
12 key (pin not installed) key (pin not installed)
13 P2_EJTAG_DINT P1_EJTAG_DINT
14 P2_COP_PWR (3.3V) P1_COP_PWR (3.3V)

Console Serial Ports (optional)

Connectors P6 (processor P1) and P5 (processor P2) access the CN5860 processors for Engi­neering debug use only. The supported baud rates for these ports operate at 9600, 14400,
19200, 38400, 57600, and 115200 bps. (The default rate is 115200 bps.)

Table 3-8: CN5860 Processor Debug Headers

Pin: P6: P5:

1 no connect no connect
2 P1_SER1_RXD P2_SER1_RXD
3 P1_SER1_TXD P2_SER1_TXD
4 no connect no connect
5 signal ground signal ground
6-7 shield signal ground

10009109-01 ATCA- 9305 User’s Manual

3-15

(blank page)

3-16

ATCA-9305 User’s Manual 10009109-01

Management Complex

PCI Bus

RJ45 RJ45

NAND

Flash

1GB
x 16

BCM56802
XAUI 10 Gb

Switch

3

SGMII4SGMII

PCI Bus

IDSEL13

KSL

CPLD

Latched Adrs

A/D

Adrs/Data

Console

I2C

EEPROM

RTC

MPC8548

Management

Processor

J30

Socketed

ROM

512KB

x 8

PQ DDR2

SDRAM

NOR
Flash

4M

x 16

I2C

EEPROM

COP/JTAG

PCIe x4

NOR

Flash
512Mb or
64MB x 16

To Cavium

Processor 2

& Ethernet Switch

To Cavium

Processor 1

Management Processor Complex

PHY

PHY

PHY

Section 4

The ATCA-9305 management complex is comprised of the Freescale MPC8548 processor,
CPLD, SDRAM, flash, I

2

C EEPROM, Real-time Clock, and PCI bus interface. Board power-up,
booting and monitoring the Cavium processors, PCI bus arbitration, interrupt servicing,
memory persistence functionality, and other board level management tasks are imple­mented using the MPC8548 processor. The MPC8548 stores the Cavium operating system
and monitor code in its local memory and then uses the boot over PCI functionality to bring
up the Cavium processor complexes. The CPLD registers are described in Chapter 5. See
Chapter 9 for the Management Processor Monitor.

The management complex connects to the Broadcom Ethernet switch via a 1000BASE-T
Ethernet port. This connection uses the TSEC2 interface operating in SGMII mode. See
Chapter 6, “Ethernet Interface.”

Figure 4-1: MPC8548 Management Processor Complex Block Diagram

10009109-01 ATCA- 9305 User’s Manual

4-1

Management Complex: MPC8548 Processor

MPC8548 PROCESSOR

The MPC8548 processor has the following features:

Table 4-1: MPC8548 Features

Feature: Description:

L1 Cache 32-kilobyte data and instruction caches with parity protection, 32-

byte line, eight-way set associative
L2 Cache 512 kilobytes, eight-way set associative
CPU Core Speed 1 GHz with a 400 MHz DDR2 bus
DDR2 Memory Controller 64-bit data interface, four banks of memory supported (each up to 4

GB), full ECC support
Dual I2C Controllers Two-wire interface, master or slave I
Boot Sequencer Loads configuration data from serial ROM at reset via the I
Ethernet Four 10/100/1000 enhanced three-speed controllers (eTSECs), full-

/half-duplex support, MAC address recognition
Local Bus Controller (LBC) DDR2 SDRAM memory controller, General Purpose Chip Select

Machine (GPCM), three User-Programmable Machines (UPM), eight

chip selects support eight external slaves
PCI 64-bit, PCI 2.2 compatible
PCI Express Single x4 PCIe high-speed interconnect, complies with PCI Express™

Base Specification Revision 1.0a

JTAG Complies with IEEE Std. 1149.1

2

C support

2

C interface

For more detailed information, reference the Freescale MPC8548E PowerQUICC™ III Inte-

grated Processor Family Reference Manual.

MPC8548 Memory Map

The monitor can boot from either the soldered flash (Bank 1, default) or the socketed PLCC
device. Based on the configuration header (see page 2-8) either the socketed device or sol­dered flash is mapped to the boot bank at FFF8,0000
lar portions of the memory map can be found in later sections of this manual, see

4-2

ATCA-9305 User’s Manual 10009109-01

, see Fig. 4-2. Information on particu-

16

Ta bl e 4- 2 .

Management Complex: MPC8548 Processor

E000,0000

EFFF,FFFF

F000,0000

SDRAM DDR2 (2 GB)

Soldered Flash Bank 4 (32 MB)

Soldered Flash Bank 3 (32 MB)

PCI (1.5 GB)

Soldered Flash Bank 2 (4 MB)

Reserved (64 MB)

NAND Flash (32 KB)

LPC Interface (64 KB)

Reserved (992 KB)

Reserved (2.9 MB)

CPLD Registers (512 KB)

Reserved (3.5 MB)

Socketed Flash, optional (512 KB)

Reserved (46 MB)

MPC8548 CCSRBAR (1 MB)

Reserved (7.5 MB)

Boot Window (512 KB)

F3C0,0000

F400,0000

F600,0000

F800,0000

FC00,0000

FC00,8000

FC10,0000

FC11,0000

FC40,0000

FC48,0000

FC80,0000

FC88,0000

FF70,0000

FF80,0000

FFF0,0000

F3BF,FFFF

F3FF,FFFF

F5FF,FFFF

F7FF,FFFF

FBFF,FFFF

FC00,7FFF

FC0F,FFFF

FC10,FFFF

FC3F,FFFF

FC47,FFFF

FC7F,FFFF

FC87,FFFF

FF6F,FFFF

FF7F,FFFF

FFEF,FFFF

FFFF,FFFF

Address Range

Reserved (56 MB)

F080,0000

F3FF,FFFF

PCI Express (256 MB)

Soldered Flash Bank 1 (4 MB)

8000,0000

DFFF,FFFF

0000,0000

7FFF,FFFF

Product ID

Hardware Version

PLD Version

PLL Configuration

Hardware Configuration 0

reserved

Jumper Setting

LED

Reset Event

Reset Command #1

Reset Command #2

Reset Command #3

Reset Command #4

Reset Command #5

Reset Command Sticky #1

Reset Command Sticky #2

Scratch #1

Boot Device Redirection

Miscellaneous Control

RTM GPIO State

RTM GPIO Control

RTM Control

Cavium 1 Clock Divisor Control

Cavium 2 Clock Divisor Control

Altera JTAG Software Control

Cavium GPIO Control

LPC Data

IPMP/IPMC GPIO Control

LPC Bus Control

FC40,0000

FC40,0004

FC40,0008

FC40,000C

FC40,0010

FC40,0014

FC40,0018

FC40,001C

FC40,0020

FC40,0024

FC40,0028

FC40,002C

FC40,0030

FC40,0034

FC40,0038

FC40,003C

FC40,0040

FC40,0050

FC40,0054

FC40,0060

FC40,0064

FC40,0068

FC40,0070

FC40,0074

FC40,0078

FC40,0080

FC40,0084

FC40,0088

FC40,008C

FC40,00D0

Hex Address

FC40,00D4

FC40,00D8

Serial IRQ Interrupt 1

Serial IRQ Interrupt 2

Cavium GPIO Data Output

Cavium GPIO Data Input

FC40,00DC

F0FF,FFFF

F380,0000

PCI Express I/O (16 MB)

Figure 4-2: MPC8548 Memory Map

Table 4-2: MPC8548 Address Summary

Hex Physical
Address:

FFF8,0000 R/W Boot window (512 KB) —
FF80.0000 — reserved (7.5 MB)
FF70,0000 R/W MPC8548 CCSRBAR (1MB) —
FC88,0000 — reserved (46 MB)

Access
Mode: Register Description:

10009109-01 ATCA- 9305 User’s Manual

See
Page:

4-3

Management Complex: MPC8548 Processor

Hex Physical
Address:

FC80,0000 R/W Socketed flash, optional (512 KB) 4-7
FC48,0000 — reserved (3.5 MB)
FC40,00DC0 R/W Serial IRQ Interrupt 2 5-15
FC40,00D8 R/W Serial IRQ Interrupt 1 5-15
FC40,00D4 R/W LPC Data 5-15
FC40,00D0 R/W Low Pin Count (LPC) Bus Control 5-14
FC40,008C R/W IPMP/IPMC GPIO Control 5-14
FC40,0088 R/W Cavium GPIO Data Input 5-13
FC40,0084 R/W Cavium GPIO Data Output 5-13
FC40,0080 R/W Cavium GPIO Control 5-12
FC40,0078 R/W Altera JTAG Chain Software Control 5-12
FC40,0074 R/W Cavium 2 C_MUL Clock Divisor Control 5-11
FC40,0070 R/W Cavium 1 C_MUL Clock Divisor Control 5-11
FC40,0068 R/W RTM Control 5-10
FC40,0064 R/W RTM GPIO Control 5-10
FC40,0060 R/W RTM GPIO State 5-10
FC40,0054 R/W Miscellaneous Control (SIO, I2C, Test Clock) 5-9
FC40,0050 R/W Boot Device Redirection 5-8
FC40,0040 R/W Scratch #1 —
FC40,003C R/W Reset Command Sticky #2 5-8
FC40,0038 R/W Reset Command Sticky #1 5-7
FC40,0034 W Reset Command #5 5-7
FC40,0030 W Reset Command #4 5-7
FC40,002C W Reset Command #3 5-6
FC40,0028 W Reset Command #2 5-6
FC40,0024 W Reset Command #1 5-5
FC40,0020 R/W Reset Event 5-5
FC40,001C R/W LED 5-4
FC40,0018 R/W Jumper Setting 5-4
FC40,0014 — reserved —
FC40,0010 R/W Hardware Configuration 0 5-3
FC40,000C R/W PLL Configuration 5-3
FC40,0008 R/W PLD Version 5-3
FC40,0004 R/W Hardware Version 5-2
FC40,0000 R/W Product ID (CPLD 512 KB) 5-2
FC11,0000 reserved (2.9 MB)
FC10,0000 R/W LPC Interface (64 KB) 4-5
FC00,8000 — reserved (992 KB)
FC00,0000 R/W NAND flash (32 KB) 4-8

Access
Mode: Register Description: (continued)

See
Page:

4-4

ATCA-9305 User’s Manual 10009109-01

Management Complex: MPC8548 Processor

Hex Physical
Address:

F800,0000 — reserved (64 MB)
F600,0000 R/W Soldered flash bank 4 (32 MB) 4-7
F400,0000 R/W Soldered flash bank 3 (32 MB) 4-7
F080,0000 — reserved (56 MB)
F3C0,0000 R/W Soldered flash bank 2 (4 MB) 4-7
F380,0000 R/W Soldered flash bank 1 (4 MB) 4-7
F000,0000 R/W PCI Express I/O space (16 MB) 4-8
E000,0000 R/W PCI Express (256 MB) 4-8
8000,0000 R/W PCI (1.5 GB) 4-8
0000,0000 R/W SDRAM DDR2 (2 GB) 4-7

Chip Selects

The MPC8548 memory controller functions as a chip select (CS) generator to access on­board memory devices. In order to select one device over another, the following chip
selects have been established.

Table 4-3: Device Chip Selects

Pin: Signal:

0Boot bank
1 Soldered flash boot bank 1 (default)
2 Soldered flash boot bank 2
3Socketed flash (optional)
4KSL CPLD registers
5NAND flash
6 Soldered NOR flash boot banks 3 and 4
7LPC interface

1. Boot bank can be either socketed flash, flash 1, or flash 2;

depending on the jumper setting (see Fig. 2-6).

Access
Mode: Register Description: (continued)

1

See
Page:

10009109-01 ATCA- 9305 User’s Manual

4-5

Management Complex: MPC8548 Processor

NAND

Flash

1GB
x 16

PQ_HRESET*

MPC8548MPC8548

ManagementManagement

ProcessorProcessor

PQ DDR2PQ DDR2
SODIMMSODIMM

Module Module

NOR
Flash

4M

x 16

Ethernet Port

BCM5461S

PQ_SRESET*

PQ_TRST*

RESET_INDICATION*

I2C1

I2C2

Reset to IPMC

FLASH_RST*

NAND_RST*

NAND_WARM_RST*

PQ_DDR_RST*

TSEC1_RST*

Ethernet Port

BCM5461S

Ethernet Port

BCM5461S

Ethernet Port

BCM5482

TSEC2_RST*

FP1_RST*

BC_RST*

Voltage
Monitor

Delay

IPMC

KSL

CPLD

IPMP

CPLD

PWRGD_OK

L_PAYLD_EN
3_3V_PWRGD
2_5V_PWRGD
1_8V_PWRGD
1_2V_PWRGD
1_0V_PWRGD

PQ_CORE_PWRGD*
P1_CORE_PWRGD*
P2_CORE_PWRGD*

POR_RST*

48A_OK

48B_OK

E_HANDLE

I2C IO

Port

BOOT_REDIR
BOOT_SEL0
BOOT_SEL1

L_PAYLOAD_RST*

PRIV_I2C_SCL

PRIV_I2C_SDA

IPMC_PO_RST*

3_3V_MP

IPMC Reset

3_3V_MP

Hot Swap

Switch

3_3V_MP

3_3V_MP

Front
Panel
Reset

3_3V

Voltage

Monitor

Delay

33MHz

IPMC_PO_RST*

Reset Diagram

Figure 4-3: MPC8548 Reset Diagram

4-6

ATCA-9305 User’s Manual 10009109-01

Management Complex: Memory

MEMORY

The memory devices in the management complex consist of:

• 1 GB DDR2 SDRAM

• 512 KB socketed flash

• 8 MB soldered NOR flash (two redundant banks of 4 MB each)

• 1 GB soldered NAND flash

• 512 Mb or 64 MB soldered NOR flash

SDRAM

This is a specialized, socketed, 200-pin, small outline, clocked, dual in- line, memory mod­ule (SO-CDIMM). It provides Error-correcting Code (ECC) on the SDRAM memory bus oper­ating at 200 MHz. The MPC8548 detects all double-bit errors, multi-bit errors within a
nibble and corrects all single-bit errors.

The 128M X 72 DDR2 SDRAM is a high-density, un-buffered SO-CDIMM. This module con­sists of nine 128x8-bit with eight banks DDR2 SDRAMs, a zero delay phase-lock loop (PLL)
clock, and a 2 KB serial presence detect (SPD) EEPROM. The SDRAM starts at physical
address 0000,0000

16

.

Flash

There are several flash devices on the local bus interfacing the CPLD and MPC8548 proces­sor. The four soldered flash banks are labeled 1 through 4:

• Banks 1 and 2 are the MPC8548 U-boot banks (see “4M x 16”). These boot banks are
used in the boot redirection scheme, see “Boot Device Redirection (BDR).”

• Banks 3 and 4 are physically one device, but appear in the software as two banks of 32
MB (see “64 MB x 16”). These are for general purpose storage.

512 KB x 8 (optional)

The 512 KB of 32-pin PLCC socketed flash starts at physical address FC80,0000
for Engineering code.
access times, low power, and flexible security options.

4M x 16

The two 4 MB soldered flash devices are used for MPC8548 boot code. This redundant bank
configuration allows booting from either bank in case of corruption in one bank. See “Boot
Device Redirection (BDR)” on page 7-41. The SST NOR flash devices are organized as 4Mx8

The StrataFlash (P33) features high-performance fast asynchronous

10009109-01 ATCA- 9305 User’s Manual

and is used

16

4-7

Management Complex: PCI

in a dual-bank architecture for concurrent read/write operation with hardware and soft ware
data protection schemes. These devices start at physical addresses F000,0000

1) and F040,0000

1 GB x 16

The ATCA-9305 uses 1 GB of M-Systems DiskOnChip (mDOC H3) NAND flash starting at
physical address FC00,0000
(TFFS). This memory incorporates an embedded flash controller and memory, and includes
hardware protection and security-enabling features, an enhanced programmable boot
block enabling eXecution In Place (XIP) functionality using 16-bit access, user-controlled
One Time Programmable (OTP) partitions, and 6-bit Error Detection Code/Error Correction
Code (EDC/ECC).

64 MB x 16

The 64 MB soldered NOR flash starts at physical address F400,0000
P33 device provides CN5860 code storage and non-volatile memory.

(boot bank 2).

16

16

(boot bank

16

for non-volatile RAM storage and True Flash File System

(bank 3). The 64-Mbit

16

PCI

The MPC8548 performs all the functions of a PCI host and monarch, and handles all arbitra­tion and enumeration functions. PCI starts at physical address 8000,0000

The PCI bus connects to both Cavium processors, the MPC8548 processor and the Broad­com Ethernet switch, see

Ta bl e 4- 4 . All of the devices on the PCI bus can operate at 66 MHz

and perform 64-bit transactions in conventional PCI mode except for the Broadcom switch.
The switch has a 32-bit PCI bus.

The MPC8548 stores the Cavium CN5860 operating system and monitor code in local
memory and then uses the boot over PCI functionality to bring up the CN5860 processor
complexes.

Table 4-4: PCI Device Interrupts and ID Assignments

PCI Device: Interrupt: IDSEL:

Cavium processor 1 IRQ6 PCI_AD11
Cavium processor 2 IRQ5 PCI_AD12
Ethernet switch IRQ4 PCI_AD13
MPC8548 — PCI_AD14

PCI Express

The four lane PCIe routes between the MPC8548 and the optional rear transition module
(zone 3 connector). PCIe starts at physical address E000,000016.

16

.

4-8

ATCA-9305 User’s Manual 10009109-01

Management Complex: I2C Interface

I2C INTERFACE

The I2C interface consists of the MPC8548 initialization EEPROM, user (storage) NVRAM,
SO-CDIMM, and the Real-time Clock (RTC). The two Atmel two-wire serial EEPROMs on the

2

I

C interface consist of the Serial Clock (SCL) input and the Serial Data (SDA) bidirectional

lines.

Table 4-5: I2C Device Addresses

I2C Device: Address:

MPC8548 Initialization (EEPROM-2) 0xA0
User NVRAM (EEPROM-1) 0xA2
DDR2 SDRAM (SO-CDIMM) 0xA4
M41T00 RTC 0xD0

The two EEPROMs store non-volatile information such as board, monitor, and operating sys­tem configurations as well as customer specific items.

Table 4-6: MPC8548 NVRAM Memory Map

Address Offset

EEPROM:

EEPROM-1
0xA2
(write
protected)

EEPROM-2
0xA0
(write
protected)

Note: Both EEPROMs are write-protected.

(hex): Description:

0x1FF0-0x1FFF Boot verify secondary area (monitor) 16
0x1FE0-0x1FEF Boot verify primary area (monitor) 16
0x1EE0-0x1FDF Operating system parameters (monitor) 256
0x0000-x1EDF User defined 7903
0x0900-0x1FFF Emerson reserved area 5887
0x0800-0x08FF Miscellaneous 256
0x07F0-0x07FF Power-on Self-test (POST) 16
0x0000-0x07EF User defined 2032

MANAGEMENT PROCESSOR HEADER AND SERIAL PORT

JTAG/COP Interface (optional)

The management complex uses header P2 for debug purposes.

Table 4-7: Serial Debug Connector, P2

Pin: Signal: Description:

1 PQ_TDO Test Data Output is the serial data output as well as test and

2 no connect —

Window
Size (bytes)

programming data.

10009109-01 ATCA- 9305 User’s Manual

4-9

Management Complex: Management Processor Header and Serial

Pin: Signal: Description: (continued)

3 PQ_TDI Test Data Input is the serial input pin for instructions as well as test and

4 DEBUG_TRST* Test Reset input signal resets the test access port.
5 no connect —
6 PQ_JTAG_PWR 3.3 volt power
7 PQ_TCK_R Test Clock Input is the clock input to the boundary scan test (BST)

8 no connect —
9 PQ_TMS Test Mode Select input pin provides the control signal to determine

10 no connect —
11 DEBUG_SRESET* Soft Reset input signal indicates that the MPC8548 must initiate a

12 ground —
13 DEBUG_HRESET* Hard Reset input signal indicates that a complete Power-on Reset must

14 no connect —
15 PQ_CKSTP_OUT* Checkstop Out indicates the MPC8548 has detected a checkstop

16 ground —

programming data.

circuitr y.

the transitions of the TAP controller state machine.

System Reset interrupt.

be initiated by the MPC8548.

condition and has ceased operation.

4-10

Serial Debug Port

The console port for the management processor is accessible via the front panel mini-B USB
connector P7. The supported baud rates for these ports operate at 9600, 14400, 19200,
38400, 57600, and 115200 bps.

Table 4-8: Serial Debug Connector, P7

Pin: Signal:

1 no connect
2 PQ_CONSOLE_RX_C
3 PQ_CONSOLE_TX_C
4 no connect
5 signal ground
6 chassis ground
7 chassis ground

ATCA-9305 User’s Manual 10009109-01

Management Processor CPLD

The ATCA-9305 uses a Programmable Logic Device (PLD) to provide control logic for the
local bus. The PLD implements various registers for reset, hardware, and LPC bus communi­cation between the processors.

MPC8548 PLD REGISTER SUMMARY

The PLD registers start at address FC40,000016. As a rule, registers retain their values
through all resets except for power-on and front panel reset.
isters followed by the register bit descriptions.

Table 5-1: PLD Register Summary

Address
Offset (hex): Mnemonic: Register Name: See Page:

0x00 PIDR Product ID 5-2
0x04 HVR Hardware Version 5-2
0x08 PVR PLD Version 5-3
0x0C PLLCR PLL Configuration 5-3
0x10 HCR00 Hardware Configuration 0 5-4
0x18 JSR Jumper Setting 5-4
0x1C LEDR LED 5-5
0x20 RER Reset Event 5-5
0x24 RCR1 Reset Command #1 5-6
0x28 RCR2 Reset Command #2 5-6
0x2C RCR3 Reset Command #3 5-6
0x30 RCR4 Reset Command #4 5-7
0x34 RCR5 Reset Command #5 5-7
0x38 RCRS1 Reset Command Sticky #1 5-8
0x3C RCRS2 Reset Command Sticky #2 5-8
0x40 SCR1 Scratch #1
0x50 BDRR Boot Device Redirection 5-9
0x54 MISC Miscellaneous Control (SIO, I2C, Test Clock) 5-9
0x58 LFTR1 Low Frequency Timer 1 5-9
0x5C LFTR2 Low Frequency Timer 2 5-9
0x60 RGSR RTM GPIO State 5-10
0x64 RGCR RTM GPIO Control 5-10
0x68 RTMCR RTM Control 5-11
0x70 CMUL1 Cavium 1 C_MUL Clock Divisor Control 5-11
0x74 CMUL2 Cavium 2 C_MUL Clock Divisor Control 5-12
0x78 JTAG Altera JTAG Chain Software Control 5-12
0x80 CGCR Cavium GPIO Control 5-12

Section 5

Ta bl e 5- 1 lists the 8-bit PLD reg-

1

—

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5-1

Management Processor CPLD: MPC8548 PLD Register

Address
Offset (hex): Mnemonic: Register Name: (continued) See Page:

0x84 CGDO Cavium GPIO Data Out 5-13
0x88 CGDI Cavium GPIO Data In 5-13
0x8C IGCR IPMP/IPMC GPIO Control 5-14
0xD0 LPC1 Low Pin Count (LPC) Bus Control 5-14
0xD4 LPCD LPC Data 5-15
0xD8 SIRQI1 Serial IRQ Interrupt 1 [15:8] 5-15
0xDC SIRQI2 Serial IRQ Interrupt 2 [7:0] 5-15

1. Scratch 1 (0x40) is a read/write register for storage only.

Product ID

This read-only register identifies the board as ATCA-9305, and is used for PLD coding.

Register 5-1: Product ID (0x00)

Bits: Function: Description:

7 CAVF1 Cavium Frequency 1
6 CAVF0 Cavium Frequency 0
50 Product ID
40
30
20
1 HC1 Hardware Configuration 1
0 HC0 Hardware Configuration 0

Hardware Version

This read-only register tracks hardware revisions.

Register 5-2: Hardware Version (0x04)

Bits: Function: Description:

70
60
50
40
3 HVN (3) Hardware Version Number is hard coded in the PLD and changes
2HVN (2)
1HVN (1)
0HVN (0)

5-2

ATCA-9305 User’s Manual 10009109-01

with every major PCB artwork version.
Version star ts at 00

.

16

Management Processor CPLD: MPC8548 PLD Register

PLD Version

This read-only register tracks PLD revisions.

Register 5-3: PLD Version (0x08)

Bits: Function: Description:

7 0 This is hard coded in the PLD and changes with every released code
60
50
40
30
20
10
00

PLL Reset Configuration

Write to this register to reconfigure the SYSCLK to CCB clock ratio and the CCB to CORE
clock ratio using valid values from the MPC8548E PowerQUICC™ III Integrated Processor Family
Reference Manual. The changes take affect when the processor is reset (for example, the
software hard reset command or watchdog timer expires). Default values are restored
when the board is power-cycled, front panel reset is pressed, or receives a PCI reset that was
not the result of the MPC8548 software initiating a PCI RSTOUT command.

Register 5-4: PLL Reset Configuration (0x0C)

change. Version starts at 00

.

16

Bits: Function: Description:

7 reserved
6 CCCB2 CCB2 to CORE clock ratio
5 CCCB1 CCB1 to CORE clock ratio
4 CCCB0 CCB0 to CORE clock ratio
3 CCBSYS3 SYSCLOCK3 to CCB clock ratio
2 CCBSYS2 SYSCLOCK2 to CCB clock ratio
1 CCBSYS1 SYSCLOCK1 to CCB clock ratio
0 CCBSYS0 SYSCLOCK0 to CCB clock ratio

Hardware Configuration 0

The read-only HCR0 allows the MPC8548 monitor software to easily determine specific
hardware configurations, such as the processor clock and MPC8548 DDR memory.

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Management Processor CPLD: MPC8548 PLD Register

Register 5-5: Hardware Configuration 0 (0x10)

Bits: Function: Description:

70
6 P33P P33 (StrataFlash) is Present
5 RST_IND_CLR Clear the Reset Indication to the IPMC controller
4 CAVF1 Cavium Frequency 1
3 CAVF0 Cavium Frequency 0
2 PQCF1 MPC8548 Core Frequency 1
1 PQCF0 MPC8548 Core Frequency 0
0 PQDDRF MPC8548 DDR SDRAM Fast

Jumper Settings

These read-only bits may be read by software to determine the current jumper settings. See
the jumper descriptions on page 2-8.

Register 5-6: Jumper Settings (0x18)

Bits: Function: Description:

70
60
50
4 SJ Cavium Boot Flash Jumper

0 Installed, Cavium processors boot from soldered flash
1 Not installed, Cavium processors boot from socket

3BOOT Boot PCI Jumper

0 Installed, boot from flash (socket or soldered per bit 4)
1 Not installed, boot over PCI from the MPC8548

2 REDIR Boot Redirect Jumper

1IG ROM Ignore SROM

0 BT SKT Boot from Socket

0 Installed, disables boot redirection
1 Not installed, enables boot redirection

0 Not installed, SROM is used for initialization (default)
1 Installed, disables SROM, uses default values in monitor
code

0 Not installed, enables MPC8548 to boot from soldered
flash (default)
1 Installed, enables MPC8548 to boot from socketed flash

LED

Writing a one to an LED bit lights that LED. During monitor power-up, the debug LEDs are
used to display the software progress.

5-4

ATCA-9305 User’s Manual 10009109-01

Management Processor CPLD: MPC8548 PLD Register

Register 5-7: LED (0x1C)

Bits: Function: Description:

7 PQRED MPC8548 red LED

Lit on power-up and turned off when the monitor finishes boot

up and Power-on Self Testing (POST)
6 PQGREEN MPC8548 green LED
5 SWLEDCLK Ethernet Switch LED Clock
4 SWLEDDAT Ethernet Switch LED Data
3 DEBUGLED3 LED CR22
2 DEBUGLED2 LED CR21
1 DEBUGLED1 LED CR19
0 DEBUGLED0 LED CR18

Reset Event

This read-only register contains the bit corresponding to the most recent event which
caused a reset. When power is first applied, the FP_PSH_BUTTN reset event is not latched
into the Reset Event register, this is the Power-on Reset (POR) event. Front panel reset
events which occur after power-up will be latched.

Note: At power-up, the FRST_PWR_UP defaults to 1.

Register 5-8: Reset Event (0x20)

Bits: Function: Description:

7 RTMPB RTM push button
6 SHR Software Hard Reset Set to 1 when the last reset was caused

by a write to the Reset Command register
5 CPUHRR CPU Hard Reset Request
4 COPSR Set to 1 when a COP header or software-issued Soft Reset

(SRESET) has occurred
3 COPHR Set to 1 when a COP header Hard Reset (HRESET) has occurred
2 PAYR Set to 1 when a Payload Reset from the IPMC has occurred
1SBR Software Board Reset

Set to 1 when the IPMC software issued the board (payload)

reset
0 FPPB Front Panel Push Button (FP_PSH_BUTTN, POR_RST)

Reset Command 1

The write-only Reset Command 1 register forces one of several types of resets, as shown
below. A reset sequence is first initiated by writing a one to a single valid bit, then the PLD
performs that particular reset, and the bit is automatically cleared.

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5-5

Management Processor CPLD: MPC8548 PLD Register

Register 5-9: Reset Command 1 (0x24)

Bits: Function: Description:

7 WBR Reset the Whole Board
6 PQCR Reset the MPC8548 Complex
5 CAV1CR Reset the Cavium CN5860 1 Complex
4 CAV2CR Reset the Cavium CN5860 2 Complex
3 SWICR Reset the switch BCM5680x Complex
2 I2C R Reset the I2C on the MPC8548
1 RTMR Reset the (optional) RTM
0 reserved

Reset Command 2

The write-only Reset Command 2 register forces one of several types of MPC8548 resets, as
shown below. A reset sequence is first initiated by writing a one to a single valid bit, then the
PLD performs that particular reset, and the bit is automatically cleared.

Register 5-10: Reset Command 2 (0x28)

Bits: Function: Description:

7 PQHR MPC8548 Hardware Reset
6 PQSR MPC8548 Software Reset
5 PQDR MPC8548 DDR SDRAM Reset
4 PQF MPC8548 Flash reset
3 NANDR MPC8548 NAND flash Reset
2 NANDWR MPC8548 NAND flash Warm Reset
1 reserved
0 reserved

Reset Command 3

The write-only Reset Command 3 register forces one of several types of Cavium 1 resets, as
shown below. A reset sequence is first initiated by writing a one to a single valid bit, then the
PLD performs that particular reset, and the bit is automatically cleared.

Register 5-11: Reset Command 3 (0x2C)

Bits: Function: Description:

7 CAV1R Cavium 1 Reset
6 CAV1PR Cavium 1 PCI Reset
5 CAV1DR Cavium 1 DDR SDRAM Reset
4 CAV1F Cavium 1 4 MB Flash (Cavium local bus) reset
3 CAV1M1 Cavium 1 MIP1 reset
2 CAV1M2 Cavium 1 MIP2 reset

5-6

ATCA-9305 User’s Manual 10009109-01

Management Processor CPLD: MPC8548 PLD Register

Bits: Function: Description: (continued)

1 reserved
0 reserved

Reset Command 4

The write-only Reset Command 4 register forces one of several types of Cavium 2 resets, as
shown below. A reset sequence is first initiated by writing a one to a single valid bit, then the
PLD performs that particular reset, and the bit is automatically cleared.

Register 5-12: Reset Command 4 (0x30)

Bits: Function: Description:

7 CAV2R Cavium 2 Reset
6 CAV2PR Cavium 2 PCI Reset
5 CAV2DR Cavium 2 DDR SDRAM Reset
4 CAV2F Cavium 2 4 MB Flash (Cavium local bus) reset
3 CAV2M3 Cavium 2 MIP3 reset
2 CAV2M4 Cavium 2 MIP4 reset
1 reserved
0 reserved

Reset Command 5

The write-only Reset Command 5 register forces one of several types of BCM5680x Ethernet
switch resets, as shown below. A reset sequence is first initiated by writing a one to a single
valid bit, then the PLD performs that particular reset, and the bit is automatically cleared.

Register 5-13: Reset Command 5 (0x34)

Bits: Function: Description:

7 SWIR Switch Reset
6 TSEC1R TSEC1 Ethernet to front panel PHY Reset
5 TSEC2R TSEC2 Ethernet to switch PHY Reset
4 FPIR FPI Ethernet to front panel PHY Reset
3 BCR Ethernet dual PHY to backplane Base Channel reset
2 reserved
1 reserved
0 reserved

Reset Command Sticky #1

The read/write Reset Command Sticky #1 register forces one of several types of the group­complex resets, as shown below. A reset sequence is first initiated by writing a one to one or
more bits, then the PLD performs that particular reset. The bit will persist until cleared.

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5-7

Management Processor CPLD: MPC8548 PLD Register

Note: The board powers down and powers back up when the Cavium processors power is back up (bits 0 or 1 are

cleared).

Register 5-14: Reset Command Sticky #1 (0x38)

Bits: Function: Description:
7
6
5
4
3
2
1
0

Reset Command Sticky #2

The read/write Reset Command Sticky #2 register forces one of several types of the PHY
reset command, as shown below. A reset sequence is first initiated by writing a one to one
or more bits, then the PLD performs that particular reset. The bit will persist until cleared.

Register 5-15: Reset Command Sticky #2 (0x3C)

CAV1C Cavium 1 Complex reset

CAV2C Cavium 2 Complex reset

SWIC Switch Complex reset

CAV1CF Cavium 1 Complex 4MB Flash reset

CAV2CF Cavium 2 Complex 4MB Flash reset

NANDF NAND Flash reset

CAV2RPD Reset and power down the Cavium 2 core

CAV1RPD Reset and power down the Cavium 1 core

Bits: Function: Description:

7 TSEC1R TSEC1 Ethernet to front panel PHY Reset
6 TSEC2R TSEC2 Ethernet to switch PHY Reset
5 FPIR FPI Ethernet from switch to front panel PHY Reset
4 BCR Ethernet dual PHY to backplane Base Channel Reset
3 MIP1 SPI to XAUI bridge #1 on Cavium 1
2 MIP2 SPI to XAUI bridge #2 on Cavium 1
1 MIP3 SPI to XAUI bridge #3 on Cavium 2
0 MIP4 SPI to XAUI bridge #4 on Cavium 2

Boot Device Redirection

The read/write Boot Device Redirection register (BDRR) allows the user to determine which
of three boot devices the MPC8548 CPU is using as the boot device. Several bits also indi­cate which device was set as the initial boot device. The Boot Redirected bit is set to a 1
when the current boot device does not match the initial default boot device. This indicates
to the user that the image in the default device was bad, the MPC8548 watch dog timer
expired, and the next device was tried. The boot device redirection order is determined by
IPMC. Reference the “Boot Device Diagram”.

5-8

ATCA-9305 User’s Manual 10009109-01

Management Processor CPLD: MPC8548 PLD Register

Register 5-16: Boot Device Redirection (0x50)

Bits: Function: Description:

7 SELFRS Self Refresh Started
6 BOOTSEL1 IPMC successful boot indication (BOARD_BOOTED)
5 reserved
4 BSJ Boot from Socket Jumper A shunt on J9 [1:2] selects the

512KB socketed ROM as the boot device, see Fig. 2-6.
3 NFBS Nand Flash Busy Signal
2BDS Active boot device is socket
1 BDF1 Active boot device is flash 2
0 BDF0 Active boot device is flash 1

Miscellaneous Control

This register includes two bits for manually toggling the MPC8548 I2C bus.

Register 5-17: Miscellaneous Control (0x54)

Bits: Function: Description:

7 P33WP 0 Write Protect disabled (default until the monitor boots)

6 SROM1WP 0 Write Protect disabled

5 SROM0WP 0 Write Protect disabled

4 FLASH1WP 0 Write Protect disabled (default until the monitor boots)

3 FLASH0WP 0 Write Protect disabled (default until the monitor boots)

2 NANDWP 0 Write Protect disabled

1I2CSDA I

0I2CSCL

1Write Protect enabled

1 Write Protect enabled (default)

1 Write Protect enabled (default)

1Write Protect enabled

1Write Protect enabled

1 Write Protect enabled (default)

2

C Data line
0 Drive a 0 onto the I2C SDA line
1 Drive a 1 onto the I2C SDA line

2

I

C Clock line
0Drive a 0 onto the I2C SCL line
1Drive a 1 onto the I2C SCL line

Low Frequency Timer 1 and 2

Registers LFTR1 (0x58) and LFTR2 (0x5C) are timers. They determine how many 50 μs inter­vals you want before the next interrupt on Cavium GPIO5.

Note: Unless the frequency is set to 0, there is always one 50 μs interval. This is the reason for the register setting

being 1 less than an even hundred, for example 199 rather than 200.

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5-9

Management Processor CPLD: MPC8548 PLD Register

Table 5-2: Low Frequency Timer Settings

Frequency: Set Register: Comments:

0 Off Never interrupts
1 Hz 19999 (0x4E1F) These frequencies require the use of both registers
10 Hz 1999 (0x7CF)
100 Hz 199 (0xC7)
1 KHz 19 (0x13)
10 KHz 1 This equals two 50 μs time units (default)

RTM GPIO State

This read-only register reads the current state of the GPIO pins.

Register 5-18: RTM GPIO State (0x60)

Bits: Function: Description:

7RTM_GPIO 7
6RTM_GPIO 6
5RTM_GPIO 5
4RTM_GPIO 4
3RTM_GPIO 3
2RTM_GPIO 2
1RTM_GPIO 1
0RTM_GPIO 0

5-10

RTM GPIO Control

This register sets the state of the GPIO pins. These signals are implemented as open collec­tor signals.

Register 5-19: RTM GPIO Control (0x64)

Bits: Function: Description:

7 RTM_GPIO 7 0 Causes the corresponding bit to be driven to 0
6RTM_GPIO 6
5RTM_GPIO 5
4RTM_GPIO 4
3RTM_GPIO 3
2RTM_GPIO 2
1RTM_GPIO 1
0RTM_GPIO 0

1 Tristates t he signal; t his wil l either b e read by the RTM as a 1
or can be driven by the RTM to any value

RTM Status

The RTM identification (ID) is determined by factory installed configuration resistors.

ATCA-9305 User’s Manual 10009109-01

Management Processor CPLD: MPC8548 PLD Register

!

!

Register 5-20: RTM Control (0x68)

Bits: Function: Description:

70
60
50
4 RTMP RTM is Present
3 RTMID3 RTM Identification bits 3:0
2RTMID2
1RTMID1
0RTMID0

Cavium 1 C_MUL Clock Divisor Control

Use the C_MUL1 register to reduce the speed of the Cavium CN5860 processor 1 core.

Caution: Do not over-clock the Cavium frequency (bits 6:7 hard strapped).

0000 = Test RTM (factor y only)
1000 = 20GbE I/O RTM
1100 = 18GbE and 2x10GbE I/O RTM
1010 = Storage RTM

Register 5-21: Cavium 1 C_MULL Clock Divisor Control (0x70)

Bits: Function: Description:

7 CAVF Cavium Frequency resistor set bit (read-only)
6

5CMULOE C_MUL Output Enable
4 P1CMUL4 These bits drive directly to the Cavium 1. The core clock speed
3P1CMUL3
2P1CMUL2
1P1CMUL1
0P1CMUL0

00 600
01 750
10 800
11 reserved

is the number multiplied by 50 MHz. For example, the 800 MHz
core is set to 16(0x10).

Cavium 2 C_MUL Clock Divisor Control

Use the C_MUL2 register to reduce the speed of the Cavium CN5860 processor 2 core.

Caution: Do not over-clock the Cavium frequency (bits 6:7 hard strapped).

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5-11

Management Processor CPLD: MPC8548 PLD Register

Register 5-22: Cavium 2 C_MULL Clock Divisor Control (0x74)

Bits: Function: Description:

7 CAVF1 Cavium 1 Frequency resistor set bit (read-only, see Register

Map 5-21)

6 CAVF0 Cavium 0 Frequency resistor set bit (read-only)
5CMULOE C_MUL Output Enable
4 P1CMUL4 These bits drive directly to the Cavium 2. The core clock speed
3P1CMUL3
2P1CMUL2
1P1CMUL1
0P1CMUL0

JTAG

This register allows for manual reprogramming of the PLDs on the board. Changes to this
register do not take effect until after a full board reset.

Register 5-23: JTAG (0x78)

Bits: Function: Description:

7 reserved
6 reserved
5 JTAGOEN JTAG Output Enable
4 JTAGTCKSEL JTAG Test Clock Select changes from header to PLD as the TCK

3JTAGTCK JTAG Test Clock
2 JTAGTMS JTAG Test Mode Select
1JTAGTDO JTAG Test Data Output
0 JTAGTDI JTAG Test Data Input (read only)

is the number multiplied by 50 MHz. For example, the 800 MHz
core is set to 16(0x10).

source

5-12

Cavium GPIO Control

Each Cavium processor has three GPIO control bits connected to the PLD. This register
determines whether the PLD is driving or receiving on these lines. Setting a bit to 1 causes
the PLD to drive the corresponding line.

Register 5-24: Cavium GPIO Control (0x80)

Bits: Function: Description:

7 reserved
6 reserved
5 P2GPIO5OE Processor 2 GPIO5 Output Enable (enabled is the default)

Output enable is set for the TIC timer output to the Cavium

4 P2GPIO4OE Processor 2 GPIO4 Output Enable

This is an input from the Cavium to reset the MIP4

ATCA-9305 User’s Manual 10009109-01

Management Processor CPLD: MPC8548 PLD Register

Bits: Function: Description: (continued)

3 P2GPIO3OE Processor 2 GPIO3 Output Enable

2 P1GPIO5OE Processor 1 GPIO5 Output Enable (enabled is the default)

1 P1GPIO4OE Processor 1 GPIO4 Output Enable

0 P1GPIO3OE Processor 1 GPIO3 Output Enable

Cavium GPIO Data Out

This register is the data that will be driven on the GPIO line when the Output enable is set.

Register 5-25: Cavium GPIO Data Out (0x84)

Bits: Function: Description:

7 reserved
6 reserved
5 reserved
4 P2GPIO4 Set the value of the Cavium 2 GPIO bit 4
3 P2GPIO3 Set the value of the Cavium 2 GPIO bit 3
2 reserved
1 P1GPIO4 Set the value of the Cavium 1 GPIO bit 4
0 P1GPIO3 Set the value of the Cavium 1 GPIO bit 3

This is an input from the Cavium to reset the MIP3

Output enable is set for the TIC timer output to the Cavium

This is an input from the Cavium to reset the MIP2

This is an input from the Cavium to reset the MIP1

Cavium GPIO Data In

This register reads the value on the GPIO lines connected to each Cavium.

Register 5-26: Cavium GPIO Data In (0x88)

Bits: Function: Description:

7 reserved
6 reserved
5 reserved
4 P2GPIO4 Read the value of the Cavium 2 GPIO bit 4
3 P2GPIO3 Read the value of the Cavium 2 GPIO bit 3
2 reserved
1 P1GPIO4 Read the value of the Cavium 1 GPIO bit 4
0 P1GPIO3 Read the value of the Cavium 1 GPIO bit 3

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5-13

Management Processor CPLD: MPC8548 PLD Register

IPMP/IPMC GPIO Control

This register provides access (if required) to signals between the KSL CPLD and the IPMP, as
well as to signals between the KSL CPLD and the IPMC. The lower two bits can request
request the power down of a Cavium core from the sticky reset register.

Register 5-27: IPMP/IPMC GPIO Control (0x8C)

Bits: Function: Description:

7IPMC2KSL4 Input only
6IPMC2KSL3
5IPMC2KSL2
4IPMC2KSL1
3 IPMP2KSL4 Output only
2 IPMP2KSL3 Output only
1 IPMP2KSL2 Power-down signal for Cavium 2 (output)

Ass ert hig h to shut dow n the cor e. The stick y Cavi um reset also
causes this to be asserted.

0 IPMP2KSL1 Power-down signal for Cavium 1 (output)

Ass ert hig h to shut dow n the cor e. The stick y Cavi um reset also
causes this to be asserted.

5-14

LPC Bus Control

This is the control register for the 4-bit LPC bus. It allows for communication with the IPMC
controller from the management CPU.

Register 5-28: LPC Bus (0xD0)

Bits: Function: Description:

7 LPCIE LPC Interrupt Enable
6 LPCS LPC State (internal use only)
5
4
3
2 LPCIOE LPC I/O Error
1 SYNCE SYNC Error
0SYNCT SYNC Time-out

LPC Data

This is the data register for the 4-bit LPC bus. It allows for communication with the IPMC
controller from the management CPU. This register provides the data to be sent or received,
depending upon the commands given in the control register.

ATCA-9305 User’s Manual 10009109-01

Management Processor CPLD: MPC8548 PLD Register

Register 5-29: LPC Data (0xD4)

Bits: Function: Description:

7:0 - LPC Data

Serial IRQ Interrupt 1

This is interrupt register1 for the LPC bus.

Register 5-30: Serial IRQ Interrupts 1 (0xD8)

Bits: Function: Description:

7:0 - Interrupts

Serial IRQ Interrupt 2

This is interrupt register2 for the LPC bus.

Register 5-31: Serial IRQ Interrupts 2 (0xDC)

Bits: Function: Description:

7:0 - Interrupts

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5-15

(blank page)

5-16

ATCA-9305 User’s Manual 10009109-01

Ethernet Interface

The ATCA-9305 supports multiple Ethernet interfaces. This chapter describes the Broadcom
BCM56802 switch, PHYS BCM5482 and BCM5461S, Ethernet address, LEDs and connec­tors.

BROADCOM BCM56802 SWITCH

The BCM56802 is a 16-port, 10-GbE multi-layer switch based on the StrataXGS® architec­ture. The switch operates at 66 MHz with a 32-bit PCI bus for processor communication.
SERDES functionality includes 10-Gbps XAUI and 1-Gbps SGMII PHY interfaces.

One 10/100/1000BASE-T Ethernet (SGMII) port is routed to a front panel RJ45 connector
(see

Fig. 6-1), one is routed to the MPC8548 management processor TSEC2 port, and two

are routed to the base channel backplane (see
the back panel via the fabric channel (see

Two XAUI ports process packets to and from each CN5860 processor. Six 10 GbE XAUI ports
route to the optional rear transition module (RTM). See
ments.

Note: Proprietary information on the Broadcom switch is not available in this user’s manual. Refer to their web site

for available documentation.

Section 6

Fig. 8-2). Two 10 GbE XAUI ports connect to

Fig. 8-2).

Ta bl e 8- 3 and Ta bl e 8 -4 for pin assign-

ETHERNET SWITCHING

The base interface Ethernet ports are provided by the Broadcom BCM56802 16-port, 10
gigabit (GbE) switch. The SerDes functionality includes 10-Gbps XAUI and 1-Gbps SGMII
PHY interfaces. The integrated SerDes complies with the CX-4 standard and PICMG 3.1
standard. The Fabric interface is compliant with PICMG 3.1 Revision 1.0, specifically link
option 9 (one 10GBASE-BX4). Switch connectivity consists of the following devices:

• Two 10GbE ports to CN5860 processor complex 1

• Two 10GbE ports to CN5860 processor complex 2

• One GbE port to the front panel (RJ45 connector)

• One GbE port to the MPC8548 management processor complex, then out the front
panel (RJ45 connector)

• Two 10 GbE ports to the fabric interface

• Two 1 GbE ports to the base interface

• Two or six 10 GbE ports to the Zone 3 connector (optional RTM)

10009109-01 ATCA- 9305 User’s Manual

6-1

Ethernet Interface: Ethernet Switching

10G - 4 PORTS

RJ45 RJ45

BCM5482

Base 10G Fabric

J23

P1 DDR2

SDRAM

BCM56802
XAUI 10 Gb

Switch Ports

5 XAUI

SGMII2SGMII1XAUI

8 7

XAUI 13

XAUI 14

3

SGMII

4

SGMII

6 XAUI

Cavium
Octeon
CN5860

Processor 2

SPI-1

SPI-0

Cavium
Octeon
CN5860

Processor 1

SPI-1

SPI-0

BCM5461S

Stratix II GX

#2

MPC8548

Management

Processor

J31

10G - 2 PORTS

J30

XAUI

11-12 15 -18

Stratix II GX

#1

Stratix II GX

#3

Stratix II GX

#4

BCM5461S BCM5461S

To Optional RTM

Figure 6-1: Ethernet Switching Interface Diagram

star ts at 0. Ther efore, t o issue a command to a por t, you mus t subtra ct 1 fro m the port n umbers shown in the
figure.

Ethernet Transceivers

The BCM5461S is a 10/100/1000BASE-T GbE Ethernet transceiver using the SGMII interface.
The BCM5482 consists of two complete 10/100/1000BASE-T GbE transceivers supporting
both voice and data simultaneously.

Ethernet Switch Ports

Port: Interface: Connection:

Note: The phyiscal port numbering starts at 1, as indicated in the figure. However, the software port numbering

Table 6-1: Ethernet Switch Ports

1 SGMII 1 GB PHY to backplane BASE
2 SGMII 1 GB PHY to backplane BASE

6-2

ATCA-9305 User’s Manual 10009109-01

Ethernet Interface: MPC8548 Management Processor Ethernet

Port: Interface: Connection: (continued)

3 SGMII 1 GB Switch PHY to front panel RJ45 connector
4 SGMII 1 GB Management processor PHYs to front panel RJ45 connector
5 XAUI 10 GB Stratix II GX bridge 2
6 XAUI 10 GB Stratix II GX bridge 1
7 XAUI 10 GB Back plane Fabric
8 XAUI 10 GB Back plane Fabric
9— not used
10 — not used
11 XAUI 10 GB BCM56802 to J30 to optional RTM
12
13 XAUI 10 GB Stratix II GX bridge 3
14 XAUI 10 GB Stratix II GX bridge 4
15 XAUI 10 GB BCM56802 to J31 to optional RTM
16
17
18

VLAN Setup

The default VLAN configuration is defined in Tab l e 6 - 2 . See page 9-25 for the monitor vlan
command.

Table 6-2: VLAN Configuration

VLAN: Ports:

11, 3, 4
26, 7
38, 13
45, 11
512, 14

MPC8548 MANAGEMENT PROCESSOR ETHERNET ADDRESS

The Ethernet address for your board is a unique identifier on a network. The address con­sists of 48 bits (MAC [47:0]) divided into two equal parts. The upper 24 bits define a unique
identifier that has been assigned to Emerson Network Power, Embedded Computing by
IEEE. The lower 24 bits are defined by Emerson for identification of each of our products.

The Ethernet address for the ATCA-9305 is a binary number referenced as 12 hexadecimal
digits separated into pairs, with each pair representing eight bits. The address assigned to
the ATCA-9305 has the following form:

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Ethernet Interface: MPC8548 Management Processor Ethernet

00 80 F9 xx yy zz

00 80 F9 is Emerson’s identifier. The last three bytes of the Ethernet address consist of the
port (one byte), 0x97(port 1) or 0x98 (port 2), followed by the serial number (two byte
hexadecimal). The ATCA-9305 has been assigned the Ethernet address range
00:80:F9:97:00:00 to 00:80:F9:98:FF:FF. The format is shown in

Table 6-3: Ethernet Port Address

Offset: MAC: Description: Ethernet Identifier (hex):

Byte 5 15:0 LSB of (serial number in hex) —
Byte 4 MSB of (serial number in hex) —
Byte 3 23:16 Port 1 (TSEC_1)

Byte 2 47:24 Assigned to Emerson by IEEE 0xF9
Byte 1 0x80
Byte 0 0x00

The last two bytes, MAC[15:0], correspond to the following formula: n —1000, where n is
the unique serial number assigned to each board. So if an ATCA-9305 serial number is 1032,
the calculated value is 32 (20

• TSEC_1 MAC address is: 0x00 0x80 0xF9 0x97 0x00 0x20

Port 2 (TSEC_2)

), and the default Ethernet port addresses are:

16

Tab l e 6- 3 .

0x97
0x98

• TSEC_2 MAC address is: 0x00 0x80 0xF9 0x98 0x00 0x20

Front Panel Ethernet Ports

One MPC8548 PHY (TSEC1) routes to front panel RJ45 connector, P1. The BCM56802 switch
PHY (port 3) routes to front panel RJ45 connector, P3. The Ethernet port LEDs (green or yel­low) indicate link and activity status, see front panel

Table 6-4: Front Panel Ethernet Ports

Pin: P1 Signal: P3 Signal:

1TSEC1_TRD0_P FP1_TRD0_P
2TSEC1_TRD0_N FP1_TRD0_N
3TSEC1_TRD1_P FP1_TRD1_P
4TSEC1_TRD2_P FP1_TRD2_P
5TSEC1_TRD2_N FP1_TRD2_N
6 TSE1C_TRD1_N FP1_TRD1_N
7TSEC1_TRD3_P FP1_TRD3_P
8TSEC1_TRD3_N FP1_TRD3_N
9 TSEC1_ACTIVITY (green LED 1) FP1_ACTIVITY (green LED1)
10 2_5V (yellow LED 1) 2_5V (yellow LED 1)
11 TSEC1_LINKSPD1 (green LED 2) FP1_LINKSPD1 (green LED 2)

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ATCA-9305 User’s Manual 10009109-01

Fig. 2-1.

Ethernet Interface: MPC8548 Management Processor Ethernet

Pin: P1 Signal: P3 Signal: (continued)

12 TSEC1_LINKSPD2 (yellow LED 2) FP1_LINKSPD2 (yellow LED 2)
13 TSEC1_CHSGND FP1_CHSGND
14 TSEC1_CHSGND FP1_CHSGND

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ATCA-9305 User’s Manual 10009109-01

System Management

The ATCA-9305 provides an intelligent hardware management system, as defined in the
AdvancedTCA Base Specification (PICMG® 3.0). This system implements an Intelligent Plat­form Management Controller (IPMC) based on the BMR-H8S-AMCc® reference design from
Pigeon Point Systems. It also has an inter-integrated circuit (I
Intelligent Platform Management Bus (IPMB) that routes to the ATCA backplane.

The IPMC implements all the standard Intelligent Platform Management Interface (IPMI)
commands and provides hardware interfaces for other system management features such
as Hot Swap control, LED control, power negotiation, and temperature and voltage moni­toring. The IPMC also supports an EIA-232 interface for serial communications via the Serial
Interface Protocol Lite (SIPL) IPMI commands.

IPMC OVERVIEW

The basic features for the IPMC implementation include:

• Conformance with AdvancedTCA Base Specification (PICMG® 3.0)

2

C) controller to support an

Section 7

• Geographical addressing according to PICMG® 3.0

• Ability to read and write Field Replaceable Unit (FRU) data

• Ability to reset IPMC from IPMB

• Ability to read inlet and outlet airflow temperature sensors

• Ability to read payload voltage/current levels

• Ability to send event messages to a specified receiver

• All sensors generate assertion and/or de-assertion event messages

• Support for fault tolerant HPM.1 firmware upgrades

• Support for field updates of firmware via IPMB-0 or the payload interface

• Redundant boot bank capability

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System Management: IPMI Messaging

UART
& LPC

Figure 7-1: IPMC Connections Block Diagram

IPMI MESSAGING

All IPMI messages contain a Network Function Code field, which defines the category for a
particular command. Each category has two codes assigned to it–one for requests and one
for responses. The code for a request has the least significant bit of the field set to zero,
while the code for a response has the least significant bit of the field set to one.
the network function codes (as defined in the IPMI specification) used by the IPMC.

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Ta bl e 7- 1 lists

System Management: IPMI Messaging

Table 7-1: Network Function Codes

Hex Code
Value(s): Name: Type: Name:

00, 01 Chassis chassis device

requests/responses

02, 03 Bridge bridge

requests/responses

04, 05 Sensor/

Event

06, 07 App application

08, 09 Firmware firmware transfer

0A, 0B Storage non-volatile

0C-2F reserved – reserved: 30 network functions (15 pairs)
30-3F OEM – 30 = command/request, 3F = response:

sensor and event
requests/responses

requests/responses

requests/responses

storage
requests/responses

00 = command/request, 01 = response:
common chassis control and status functions

02 = request, 03 = response:
message contains data for bridging to the next
bus. Typically, the data is another message,
which also may be a bridging message. This
function is only present on bridge nodes.

04 = command/request, 05 = response:
for configuration and transmission of Event
Messages and system Sensors. This function
may be present on any node.

06 = command/request, 07 = response:
message is implementation-specific for a
particular device, as defined by the IPMI
specification

08 = command/request, 09 = response:
firmware transfer messages match the format
of application messages, as determined by the
particular device

0A = command/request, 0B = response:
may be present on any node that provides
nonvolatile storage and retrieval services

vendor specific: 16 network functions (8 pairs).
The vendor defines functional semantics for
cmd and data fields. The cmd field must hold the
same value in requests and responses for a
given operation to support IPMI message
handling and transport mechanisms. The
controller’s Manufacturer ID value identifies the
vendor or group.

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System Management: IPMI Messaging

IPMI Completion Codes

All IPMI response messages contain a hexadecimal Completion Code field that indicates the
status of the operation.

Table 7-2: Completion Codes

Code: Description:

Generic Completion Codes 00, C0-FF
00 Command completed normally
C0 Node busy–command could not be processed because command-processing resources

are temporarily unavailable
C1 Invalid command–indicates an unrecognized or unsupported command
C2 Command invalid for given LUN
C3 Time-out while processing command, response unavailable
C4 Out of space–command could not be completed because of a lack of storage space

required to execute the given command operation
C5 Reservation canceled or invalid Reservation ID
C6 Request data truncated
C7 Request data length invalid
C8 Request data field length limit exceeded
C9 Parameter out of range–one or more parameters in the data field of the Request are out

CA Cannot return number of requested data bytes
CB Requested sensor, data, or record not present
CC Invalid data field in Request
CD Command illegal for specified sensor or record type
CE Command response could not be provided
CF Cannot execute duplicated request–for devices that cannot return the response returned

D0 Command response could not be provided, SDR Repository in update mode
D1 Command response could not be provided, device in firmware update mode
D2 Command response could not be provided, Baseboard Management Controller (BMC)

D3 Destination unavailable–cannot deliver request to selected destination. (This code can be

D4 Cannot execute command, insufficient privilege level
D5 Cannot execute command, parameter(s) not supported in present state
FF Unspecified error

of range. This is different from Invalid data field code (CC) because it indicates that the

erroneous field(s) has a contiguous range of possible values.

for the original instance of the request. These devices should provide separate commands

that allow the completion status of the original request to be determined. An Event

Receiver does not use this completion code, but returns the 00 completion code in the

response to (valid) duplicated requests.

initialization or initialization agent in progress

returned if a request message is targeted to SMS, but receive message queue reception is

disabled for the particular channel.)

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ATCA-9305 User’s Manual 10009109-01

System Management: IPMB Protocol

Code: Description: (continued)

Device-Specific (OEM) Codes 01-7E
01-7E Device specific (OEM) completion codes–command-specific codes (also specific for a

particular device and version). Interpretation of these codes requires prior knowledge of

the device command set.
Command-Specific Codes 80-BE
80-BE Standard command-specific codes–reserved for command-specific completion codes

(described in this chapter)

IPMB PROTOCOL

The IPMB message protocol is designed to be robust and support many different physical
interfaces. The IPMC supports messages over the IPMB interface. Messages are defined as
either a request or a response, as indicated by the least significant bit in the Network Func­tion Code of the message.

Table 7-3: Format for IPMI Request Message

Byte: Bits:

76543210

1 rsSA
2 Network Function (netFn)
3Checksum
4
5rqSeq
6Command
7:N Data
N+1 Checksum

rsLUN

rqSA

rqLUN

• The first byte contains the responder’s Slave Address, rsSA.

• The second byte contains the Network Function Code, netFn, and the responder’s

Logical Unit Number, rsLUN.

• The third byte contains the two’s-complement checksum for the first two bytes.

• The fourth byte contains the requester’s Slave Address, rqSA.

• The fifth byte contains the requester’s Sequence Number, rqSeq, and requester’s Logical

Unit Number, rqLUN. The Sequence number may be used to associate a specific response
to a specific request.

• The sixth byte contains the Command Number.

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System Management: SIPL Protocol

• The seventh byte and beyond contain parameters for specific commands (if required).

• The final byte is the two’s-complement checksum of all of the message data after the

first checksum.

An IPMI response message (see
difference is that the seventh byte contains the Completion Code, and the eighth byte and
beyond hold data received from the controller (rather than data to send to the controller).
Also, the Slave Address and Logical Unit Number for the requester and responder are
swapped.

Table 7-4: Format for IPMI Response Message

Byte: Bits:

76543210

1 rqSA
2 Network Function (netFn)
3Checksum
4
5rsSeq
6Command
7Completion Code
8:N Data
N+1 Checksum

SIPL PROTOCOL

The IPMC supports the Serial Interface Protocol Lite (SIPL) protocol. It supports raw IPMI
messages in SIPL and handles these messages the same way as it handles IPMI messages
from the IPMB-0 bus, except that the replies route to either the payload or serial debug
interface. Messages are entered as case-insensitive hex-ASCII pairs, separated optionally by
a space, as shown in the following examples:

[18 00 22]<newline>

[180022]<newline>

The IPMC does not, however, support SIPL ASCII text commands, as defined by the IPMI
specification.

Tab l e 7- 4 ) is similar to an IPMI request message. The main

rqLUN

rsSA

rsLUN

The IPMC does support Pigeon Point Systems extension commands, implemented as OEM
IPMI commands. These commands use Network Function Codes 2E/2F (hex), and the mes­sage body is transferred similarly to raw IPMI messages, as described previously.

The following figures show an example of an extension command request and response,
respectively.

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ATCA-9305 User’s Manual 10009109-01

System Management: Message Bridging

[B8 00 01 0A 40 00 12]

Command Code

rqSeq (00

16

) / Bridge (002)

NetFn Code (2E

16

) / LUN (002)

Pigeon Point IANA

Data

[B8 00 01 0A 40 00 12]

Command Code

rqSeq (00

16

) / Bridge (002)

NetFn Code (2E

16

) / LUN (002)

Pigeon Point IANA

Data

[BC 00 01 00 0A 40 00 34]

Command Code

rqSeq (00

16

) / Bridge (002)

NetFn Code (2F

16

) / LUN (002)

Pigeon Point IANA

Dat

a

Completion Code

Figure 7-2: Extension Command Request Example

Figure 7-3: Extension Command Response Example

MESSAGE BRIDGING

The Message Bridging facility is responsible for bridging messages between various inter­faces of the ATCA-9305 IPMI. The message bridging is implemented via the standard Send
Message command.

The ATCA-9305 IPMC also supports message bridging between the Payload Interface and
IPMB-0, which allows the payload to send custom messages to and receive them from other
shelf entities, such as the shelf manager. Message bridging is implemented using the
Send/Get Message commands and also via LUN 10 of the ATCA-9305 IPMC.

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System Management: Message Bridging

The following example illustrates how the Send/Get Message and Get Address Info com­mands can be used by the payload software to get the physical location of the board in the
shelf:

1 The payload software sends the Get Address Info command to the BMR-H8S-AMCc,

requesting address information for FRU device 0. Using the SIPL protocol:

[B0 xx 01 00]

2 The BMR-H8S-AMCc returns its IPMB address in the Get Address Info reply. In this example,

72

is the IPMB-0 address of the IPMC.

16

{B4 00 01 00 00 FF 72 FF 00 01 07]

3 The payload software composes a Get Address Info command requesting the responder to

provide its addressing information for FRU device 0. The request is composed in the IPMB
format. The responder address is set to 20
is set to the value obtained in the previous step.

{20 B0 30 72 00 01 00 8D]

4 The payload software forwards the command composed in the previous step to the shelf

manager using the Send Message command. The Send/Get Message in SIPL format is:

[18 xx 34 40 20 B0 30 72 00 01 00 8D]

5 The BMR-H8S-AMCc firmware sends the Get Address Info request to the shelf manager,

waits for a reply to this request, and sends this reply to the payload soft ware in the Send/Get
Message response.

[1C 00 34 00 72 B4 DA 20 00 01 00 00 41 82 FF 00 FF 00 1E]

6 The payload software extracts the Get Address info reply from the Send/Get Message

response and retrieves the physical address of the board from it.

(for the shelf manager). The requester address

16

The second message bridging implementation, bridging via LUN 10, allows the payload to
receive responses to requests sent to IPMB-0 via the Send Message command with request
tracking disabled, as well as receive requests from IPMB-0. To provide this functionality, the
ATCA-9305 IPMC places all messages coming to LUN 10 from IPMB-0 in a dedicated Receive
Message Queue, and those messages are processed by the payload instead of the IPMC
firmware. To read messages from the Receive Message Queue, the payload software uses
the standard Get Message command. The payload software is notified about messages
coming to LUN 10 via the Get Status command of the SIPL protocol and the payload notifi­cation mechanism, or, if the LPC/KCS-based Payload Interface is used, using the KCS inter­rupt. The Receive Message Queue of the ATCA-9305 IPMC is limited to 128 bytes, which is
sufficient for storing at least three IPMB messages, but may be not enough for a larger num­ber of messages. Taking this into account, the payload software must read messages from
the queue as fast as possible, caching them on the on-carrier payload side for further han-

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ATCA-9305 User’s Manual 10009109-01

System Management: Standard Commands

dling, if it is necessary. If the Receive Message Queue is full, the ATCA-9305 IPMC rejects all
requests coming to LUN 10 with the C0h (Node Busy) completion code and discards all
responses coming to this LUN.

STANDARD COMMANDS

The Intelligent Peripheral Management Controller (IPMC) supports standard IPMI com­mands to query board information and to control the behavior of the board. These com­mands provide a means to:

• identify the controller

• reset the controller

• return the controller’s self-test results

• read and write the controller’s SROMs

• read the temperature, voltage, and watchdog sensors

• get specific information, such as thresholds, for each sensor

• read and write the Field Replaceable Unit (FRU) data

• reserve and read the Sensor Data Record (SDR) repository

• configure event broadcasts

• bridge an IPMI request to the public IPMB and return the response

Ta bl e 7- 5 lists the IPMI commands supported by the IPMC along with the hexadecimal values

for each command’s Network Function Code (netFn), Logical Unit Number (LUN), and Com­mand Code (Cmd):

Table 7-5: IPMC IPMI Commands

Command: netFn: LUN: Cmd:

Set System Boot Options Chassis 01, 01 07
Get System Boot Options Chassis 01, 01 08
Set Event Receiver Sensor/Event 04, 05 00
Get Event Receiver Sensor/Event 04, 05 01
Platform Event (Event Message) Sensor/Event 04, 05 02
Get Device SDR Information Sensor/Event 04, 05 20
Get Device SDR Sensor/Event 04, 05 21
Reserve Device SDR Repository Sensor/Event 04, 05 22
Get Sensor Reading Factors Sensor/Event 04, 05 23
Set Sensor Hysteresis Sensor/Event 04, 05 24
Get Sensor Hysteresis Sensor/Event 04, 05 25

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System Management: Standard Commands

Command: (continued) netFn: LUN: Cmd:

Set Sensor Thresholds Sensor/Event 04, 05 26
Get Sensor Thresholds Sensor/Event 04, 05 27
Set Sensor Event Enable Sensor/Event 04, 05 28
Get Sensor Event Enable Sensor/Event 04, 05 29
Rearm Sensor Events Sensor/Event 04, 05 2A
Get Sensor Event Status Sensor/Event 04, 05 2B
Get Sensor Reading Sensor/Event 04, 05 2D
Set Sensor Type Sensor/Event 04, 05 2E
Get Sensor Type Sensor/Event 04, 05 2F
Get Device ID Application 06, 07 01
Broadcast 'Get Device ID' Application 06, 07 01
Cold Reset Application 06, 07 02
Warm Reset Application 06, 07 03
Get Self Test Results Application 06, 07 04
Get Device GUID Application 06, 07 08
Reset Watchdog Timer Application 06, 07 22
Set Watchdog Timer Application 06, 07 24
Get Watchdog Timer Application 06, 07 25
Send Message Application 06, 07 34
Get FRU Inventory Area Info Storage 0A, 0B 10
Read FRU Data Storage 0A, 0B 11
Write FRU Data Storage 0A, 0B 12
Get PICMG Properties PICMG 2C, 2D 00
Get Address Info PICMG 2C, 2D 01
FRU Control PICMG 2C, 2D 04
Get FRU LED Properties PICMG 2C, 2D 05
Get LED Color Capabilities PICMG 2C, 2D 06
Set FRU LED State PICMG 2C, 2D 07
Get FRU LED State PICMG 2C, 2D 08
Set IPMB State PICMG 2C, 2D 09
Set FRU Activation Policy PICMG 2C, 2D 0A
Get FRU Activation Policy PICMG 2C, 2D 0B
Set FRU Activation PICMG 2C, 2D 0C
Get Device Locator Record ID PICMG 2C, 2D 0D
Set Port State PICMG 2C, 2D 0E
Get Port State PICMG 2C, 2D 0F
Compute Power Properties PICMG 2C, 2D 10
Set Power Level PICMG 2C, 2D 11

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ATCA-9305 User’s Manual 10009109-01

System Management: OEM Boot Options

Command: (continued) netFn: LUN: Cmd:

Get Power Level PICMG 2C, 2D 12
Bused Resource

(Release, Quer y, Force, Bus Free)

The IPMC implements many standard IPMI commands. For example, software can use the
watchdog timer commands to monitor the system’s health. Normally, the software resets
the watchdog timer periodically to prevent it from expiring. The IPMI specification allows
for different actions such as reset, power off, and power cycle, to occur if the timer expires.
The watchdog’s ‘timer use’ fields can keep track of which software (Operating System, Sys­tem Management, etc.) started the timer. Also, the time-out action and ‘timer use’ infor­mation can be logged automatically to the System Event Log (SEL) when the time-out
occurs. Refer to the IPMI specification (listed in
request and response data. The IPMC also implements ATCA commands, see the ATCA Base
Specification (PICMG 3.0).

OEM BOOT OPTIONS

PICMG 2C, 2D 17

Ta bl e 1- 2 ) for details about each command’s

The Set System Boot Options and Get System Boot Options commands provide a means to
set/retrieve the boot options. The IPMI specification defines a set of standard boot option
parameters. In addition, the specification includes a range of numbers (96-127) for OEM
extensions. Emerson utilizes this area for OEM function extensions, such as boot bank selec­tion and POST configuration. The following table describes these extensions:

Table 7-6: Emerson Boot Option Parameters

Parameter: # Parameter Data:

Boot Bank
(non-volatile)

POST Type
(non-volatile)

96 data 1 — Set Selector. This is the processor ID for which the

boot option is to be set.

data 2 — Boot Bank Selector. This parameter is used to
indicate the boot bank from which the payload will boot.

00h = Primary (i.e., default) Boot Bank is selected.
01h = Secondary Boot Bank is selected.
02h-FFh = unused

97 data 1 — Set Selector. This is the processor ID for which the

boot option is to be set.

data 2 — PSOT Type Selector. This parameter is used to
specify the POST type that the payload boot firmware will
execute.

00h = Short POST
01h = Long POST
02h-FFh = unused

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System Management: IPMC Watchdog Timer Commands

IPMC WATCHDOG TIMER COMMANDS

The IPMC implements a standardized ‘Watchdog Timer’ that can be used for a number of
system time-out functions by System Management Software (SMS) or by the monitor. Set­ting a time-out value of zero allows the selected time-out action to occur immediately. This
provides a standardized means for devices on the IPMB to perform emergency recovery
actions.

Table 7-7: IPMC Watchdog Timer Commands

Command: See Page: Optional/Mandatory:

Reset Watchd og Timer 7-14 M
Set Watchdog Timer 7-14 M
Get Watchdog Timer 7-16 M

Watchdog Timer Actions

The following actions are available on expiration of the Watchdog Timer:

•System Reset

Monitor FRB-2 Time-out:

•System Power Off

The System Reset and System Power Off on time-out selections are mutually exclusive. The
watchdog timer is stopped whenever the system is powered down. A command must be
sent to start the timer after the system powers up.

Watchdog Timer Use Field and Expiration Flags

The watchdog timer provides a ‘timer use’ field that indicates the current use assigned to
the watchdog timer. The watchdog timer provides a corresponding set of ‘timer use expira­tion’ flags that are used to track the type of time-out(s) that had occurred.

The time-out use expiration flags retain their state across system resets and power cycles, as
long as the IPMC remains powered. The flags are normally cleared solely by the Set Watch­dog Timer command; with the exception of the “don’t log” flag, which is cleared after every
system hard reset or timer time-out.

The Timer Use fields indicate:

A Fault-resilient Booting, level 2 (FRB-2) time-out has occurred. This indicates that the last
system reset or power cycle was due to the system time-out during POST, presumed to be
caused by a failure or hang related to the bootstrap processor.

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ATCA-9305 User’s Manual 10009109-01