DYNEX MP02TT800-16, MP02TT800-12, MP02TT800-13, MP02TT800-14, MP02TT800-15 Datasheet
MP02TT800
1/8
www.dynexsemi.com
FEATURES
■ Dual Device Module
■ Electrically Isolated Package
■ Pressure Contact Construction
■ International Standard Footprint
■ Alumina (Non Toxic) Isolation Medium
■ Integral Water Cooled Heatsink
APPLICATIONS
■ Welding
VOLTAGE RATINGS
ORDERING INFORMATION
Order As:
MP02TT800-XX W12 1/4 - 18NPT
MP02TT800-XX W13 1/4 BSP connection
XX shown in the part number about represents V
DRM
/100
selection required, e.g. MP02TT800-14-W12
Note: When ordering, please use the whole part number.
Auxiliary gate and cathode leads can be ordered separately.
KEY PARAMETERS
V
DRM
1600V
I
LINE(cont.)
510A
I
LINE(20cy./50%)
805A
I
TSM(per arm)
6800A
V
isol
3000V
MP02TT800
Dual Thyristor Water Cooled Welding Module
Preliminary Information
DS5435-1.1 June 2001
Fig. 1 Circuit diagram
Fig. 2 Electrical connections - (not to scale)
Outline type code: MP02 W12/W13
(See package details for further information)
1600
1500
1400
1300
MP02TT800-16
MP02TT800-15
MP02TT800-14
MP02TT800-13
Conditions
T
vj
= 0˚ to 125˚C,
I
DRM
= I
RRM
= 30mA
V
DSM
= V
RSM
=
V
DRM
= V
RRM
+ 100V
respectively
Lower voltage grades available
Type Number Repetitive Peak
Voltages
V
DRM VRRM
V
G1K1K2G
2
1
23
K1 G1
K2
G2
1
23
MP02TT800
2/8
www.dynexsemi.com
Parameter
Max. controllable RMS line
current - single phase
Surge (non-repetitive) on-current
I
2
t for fusing
Surge (non-repetitive) on-current
I
2
t for fusing
Isolation voltage
Test Conditions
Continuous 50/60Hz T
water (in)
= 25˚C
4.5 Ltr/min T
water (in)
= 40˚C
20 cycles, 50% duty cycle T
water (in)
= 25˚C
4.5 Ltr/min T
water (in)
= 40˚C
10ms half sine, T
j
= 125˚C
V
R
= 0
10ms half sine, T
j
= 125˚C
V
R
= 50% V
DRM
Commoned terminals to base plate.
AC RMS, 1 min, 50Hz
Symbol
I
LINE
I
TSM
I2t
I
TSM
I2t
V
isol
Units
A
A
A
A
kA
A
2
s
kA
A
2
s
V
Max.
510
450
920
805
6.8
0.231 x 10
6
5.5
0.15 x 10
6
3000
Test Conditions
dc, 4.5 Ltr/min
Half wave, 4.5 Ltr/min
3 Phase, 4.5 Ltr/min
Reverse (blocking)
-
Mounting - M6
Electrical connections - M6
-
Parameter
Thermal resistance - junction to water
(per thyristor)
Virtual junction temperature
Storage temperature range
Screw torque
Weight (nominal)
THERMAL AND MECHANICAL RATINGS
ABSOLUTE MAXIMUM CURRENT RATINGS
Stresses above those listed under 'Absolute Maximum Ratings' may cause permanent damage to the device. In extreme
conditions, as with all semiconductors, this may include potentially hazardous rupture of the package. Appropriate safety
precautions should always be followed. Exposure to Absolute Maximum Ratings may affect device reliability.
Symbol
R
th(j-c)
T
vj
T
stg
-
-
Units
˚C/kW
˚C/kW
˚C/kW
˚C
˚C
Nm (lb.ins)
Nm (lb.ins)
g
Max.
0.3
0.32
0.33
125
125
-
5 (44)
1200
Min.
-
-
-
-
–40
5 (44)
-
-
MP02TT800
3/8
www.dynexsemi.com
Units
mA
V/µs
A/µs
V
mΩ
Test Conditions
At V
RRM/VDRM
, Tj = 125˚C
To 67% V
DRM
, Tj = 125˚C
From 67% V
DRM
to 200A, gate source 10V, 5Ω
t
r
= 0.5µs, Tj = 125˚C
At T
vj
= 125˚C
At T
vj
= 125˚C
Parameter
Peak reverse and off-state current
Linear rate of rise of off-state voltage
Rate of rise of on-state current
Threshold voltage
On-state slope resistance
DYNAMIC CHARACTERISTICS
Symbol
I
RRM/IDRM
dV/dt
dI/dt
V
T(TO)
r
T
Max.
30
1000
500
0.98
0.75
Min.
-
-
-
-
-
Parameter
Gate trigger voltage
Gate trigger current
Gate non-trigger voltage
Peak forward gate voltage
Peak forward gate voltage
Peak reverse gate voltage
Peak forward gate current
Peak gate power
Mean gate power
Test Conditions
V
DRM
= 5V, T
case
= 25oC
V
DRM
= 5V, T
case
= 25oC
At V
DRM Tcase
= 125oC
Anode positive with respect to cathode
Anode negative with respect to cathode
-
Anode positive with respect to cathode
See table fig. 5
-
Symbol
V
GT
I
GT
V
GD
V
FGM
V
FGN
V
RGM
I
FGM
P
GM
P
G(AV)
GATE TRIGGER CHARACTERISTICS AND RATINGS
Max.
3
150
0.25
30
0.25
5
10
100
5
Units
V
mA
V
V
V
V
A
W
W
Note 1: The data given in this datasheet with regard to forward voltage drop is for calculation of the power dissipation in the
semiconductor elements only. Forward voltage drops measured at the power terminals of the module will be in excess of these
figures due to the impedance of the busbar from the terminal to the semiconductor.
Loading...