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MA5114
MA5114
Radiation hard 1024x4 Bit Static RAM
Replaces June 1999 version, DS3591-4.0 DS3591-5.0 January 2000
The MA5114 4k Static RAM is configured as 1024 x 4 bits and
manufactured using CMOS-SOS high performance, radiation hard,
3µm technology.
The design uses a 6 transistor cell and has full static operation with
no clock or timing strobe required. Address input buffers are deselected
when Chip Select is in the HIGH state.
Operation Mode CS WE I/O Power
Read L H D OUT ISB1
Write L L D IN
Standby H X High Z ISB2
Figure 1: Truth Table
FEATURES
■ 3µm CMOS-SOS Technology
■ Latch-up Free
■ Fast Access Time 90ns Typical
■ Total Dose 10
■ Transient Upset >10
■ SEU <10
■ Single 5V Supply
■ Three State Output
■ Low Standby Current 50µA Typical
■ -55°C to +125°C Operation
■ All Inputs and Outputs Fully TTL or CMOS
Compatible
■ Fully Static Operation
■ Data Retention at 2V Supply
6
Rad(Si)
-10
Errors/bitday
10
Rad(Si)/sec
Figure 2: Block Diagram
1/12
MA5114
CHARACTERISTICS AND RATINGS
Symbol Parameter Min. Max. Units
V
CC
V
T
A
T
S
Supply Voltage -0.5 7 V
Input Voltage -0.3 VDD+0.3 V
I
Operating Temperature -55 125 °C
Storage Temperature -65 150 °C
Stresses above those listed may cause permanent
damage to the device. This is a stress rating only and
functlonal operation of the device at these condltions,
or at any other condition above those indicated in the
operations section of this specification, is not Implied
Exposure to absolute maxlmum rating conditions for
extended perlods may affect device reliability.
Figure 3: Absolute Maximum Ratings
Notes for Tables 4 and 5:
1. Characteristics apply to pre radiation at T
= -55°C to +125°C with VDD = 5V ±10% and to post 100k Rad(Si) total dose
A
radiation at TA = 25°C with VDD = 5V ±10% (characteristics at higher radiation levels available on request).
2. Worst case at TA = +125°C, guaranteed but not tested at TA = -55°C.
GROUP A SUBGROUPS 1, 2, 3.
Symbol Parameter Conditions Min. Typ. Max. Units
V
V
V
V
V
I
I
LO
I
PUI
I
PDI
I
DD
I
SB1
I
SB2
Supply voltage - 4.5 5.0 5.5 V
DD
Input High Voltage - VDD/2 - V
lH
Input Low Voltage - V
lL
Output High Voltage I
OH
Output Low Voltage IOL = 2mA - - 0.4 V
OL
Input Leakage Current (note 2) All inputs except CS --±10 µA
LI
Output Leakage Current (note 2) Output disabled, V
= -1mA 2.4 - - V
OH1
= VSS or V
OUT
DD
SS
--±20 µA
- 0.8 V
Input Pull-Up Current VIN = VSS on CS input only - - -100 µA
Input Leakage Current VIN = VSS on CS input only - - 5 µA
Power Supply Current fRC = 1MHz, CS = 50% mark:space- 12 16 mA
Selected Supply Current CS = V
SS
-2535mA
Standby Supply Current Chip disabled - 50 3000 µA
DD
V
Figure 4: Electrical Characteristics
Symbol Parameter Conditions Min. Typ. Max. Units
V
I
DR
DDR
VCC for Data Retention CS = V
DR
2.0 - - V
Data Retention Current CS = VDR, VDR = 2.0V - 30 2000 µA
Figure 5: Data Retention Characteristics
2/12
AC CHARACTERISTICS
Conditions of Test for Tables 5 and 6:
1. Input pulse = VSS to 3.0V.
2. Times measurement reference level = 1.5V.
3. Transition is measured at ±500mV from steady state.
4. This parameter is sampled and not 100% tested.
Notes for Tables 6 and 7:
Characteristics apply to pre-radiation at TA = -55°C to +125°C with V
at TA = 25°C with VDD = 5V ±10%. GROUP A SUBGROUPS 9, 10, 11.
Symbol Parameter Min Max Units
MA5114
= 5V±10% and to post 100k Rad(Si) total dose radiation
DD
T
AVAVR
T
AVQV
T
ELQV
T
(3,4) Chip Select to Output Active 10 - ns
ELQX
T
(3,4) Chip Select to Output Tri State 10 50 ns
ELQZ
T
AXQX
Read Cycle Time 135 - ns
Address Access Time - 135 ns
Chip Select to Output Valid - 135 ns
Output Hold from Address Change 10 - ns
Figure 6: Read Cycle AC Electrical Characteristics
Symbol Parameter Min Max Units
T
AVAVW
T
AVWL
T
WLWH
T
WHAV
T
DVWH
T
NHDX
T
(3,4) Write Enable to Output Tri State 10 50 ns
WLQZ
T
ELWL
T
ELWH
T
AVWH
T
(3,4) Output Active from End to Write 5 - ns
WHQX
Write Cycle Tlme 135 - ns
Address Set Up Time 10 - ns
Write Pulse Width 50 - ns
Write Recovery Time 5 - ns
Data Set Up Time 35 - ns
Data Hold Time 5 - ns
Chip Selection to Write Low 25 - ns
Chip Selection to End of Write 85 - ns
Address Valid to End of Write 80 - ns
Figure 7: Write Cycle AC Electrical Characteristics
Symbol Parameter Conditions Min. Typ. Max. Units
C
Note: T
C
IN
OUT
= 25°C and f = 1MHz. Data obtained by characterisation or analysis; not routinely measured.
A
Input Capacitance Vl = 0V - 6 10 pF
Output Capacitance VO = 0V - 8 12 pF
Figure 8: Capacitance
3/12
MA5114
Symbol Parameter Conditions
F
T
Basic Functionality VDD = 4.5V - 5.5V, FREQ = 1MHz
V
= VSS, VIH = VDD, VOL ≤ 1.5V, VOH ≥ 1.5V
IL
TEMP = -55°C to +125°C, GPS PATTERN SET
GROUP A SUBGROUPS 7, 8A, 8B
Figure 9: Functionality
Subgroup Definition
1 Static characteristics specified in Tables 4 and 5 at +25°C
2 Static characteristics specified in Tables 4 and 5 at +125°C
3 Static characteristics specified in Tables 4 and 5 at -55°C
7 Functional characteristics specified in Table 9 at +25°C
8A Functional characteristics specified in Table 9 at +125°C
8B Functional characteristics specified in Table 9 at -55°C
9 Switching characteristics specified in Tables 6 and 7 at +25°C
10 Switching characteristics specified in Tables 6 and 7 at +125°C
11 Switching characteristics specified in Tables 6 and 7 at -55°C
Figure 10: Definition of Subgroups
4/12
TIMING DIAGRAMS
ADDRESS
CS
T
T
ELQX
T
AVAVR
AVQV
T
ELQV
T
AXQX
T
MA5114
EHQZ
DATA OUT
1. WE is high for Read Cycle.
2. Address Vaild prior to or coincident with CS transition low.
HIGH
IMPEDANCE
Figure 11a: Read Cycle 1
T
AVAVR
ADDRESS
T
AVQV
DATA OUT
1. WE is high for Read Cycle.
2. Device is continually selected. CS low.
DATA VALID
T
AXQX
DATA VALID
Figure 11b: Read Cycle 2
5/12
MA5114
ADDRESS
T
AVWL
T
AVWH
T
AVAVW
T
WLWH (2)
T
WHAV (3)
ELWL
(7)
(4)
T
WLQZ
T
DVWH
T
WLQH
T
T
AXQX
WE
DATA OUT
T
HIGH
IMPEDANCE
DATA VALIDDATA IN
T
ELWH
CS
1. WE must be high during all address transitions.
2. A write occurs during the overlap (T
3. T
is measured from either CS or WE going high, whichever is the earlier, to the end of the write cycle.
WHAV
) of a low CS and a low WE.
WLWH
4. If the CS low transition occurs simultaneously with, or after, the WE low transition, the output remains in
the high impedance state.
5. DATA OUT is in the active state, so DATA IN must not be in opposing state.
6. DATA OUT is the write data of the current cycle, if selected.
7. DATA OUT is the read data of the next address, if selected.
8. T
must be met to prevent memory corruption.
ELWL
(5) (6)
WHDX
6/12
Figure 12: Write Cycle
OUTLINES AND PIN ASSIGNMENTS
D
MA5114
19
1810
W
Seating Plane
A
1
A
e b Z
Ref
A - - 5.715 - - 0.225
A1 0.38 - 1.53 0.015 - 0.060
b 0.35 - 0.59 0.014 - 0.023
c 0.20 - 0.36 0.008 - 0.014
D - - 23.11 - - 0.910
e - 2.54 Typ. - - 0.100 Typ. -
e1 - 8.13 Typ. - - 0.300 Typ. -
H 4.44 - 5.38 0.175 - 0.212
Me - - 8.28 - - 0.326
Z - - 1.27 - - 0.050
W - - 1.53 - - 0.060
Min. Nom. Max. Min. Nom. Max.
Millimetres Inches
XG406
M
E
A6
A5
A4
A3
A0
A1
A2
CS
Vss
C
e
1
1
2
3
4
5
6
7
8
9
Top
View
18 Vdd
17 A7
A8
16
15 A9
14 D1
D2
13
12 D3
11 D4
10
WE
H
15°
Figure 13: 18-Lead Ceramic DIL (Solder Seal) - Package Style C
7/12
MA5114
D
M
b
Z
e
L
A
c
M
E
A1
Pin 1
Ref
A - - 3.07 - - 0.121
A1 0.66 - - 0.026 - -
b 0.38 - 0.48 0.015 - 0.019
c 0.08 - 0.152 0.003 - 0.006
D 14.99 - 15.50 0.590 - 0.610
e - 2.54 - - 0.050 L 6.73 - 7.75 0.265 - 0.305
M 9.96 - 10.36 0.392 - 0.408
Me 7.6 - - 0.30 - -
Z 0.13 - 1.14 0.005 - 0.045
Millimetres Inches
Min. Nom. Max. Min. Nom. Max.
XG544
24Vdd
23A7
22A8
21A9
20NC
19NC
18D1
Bottom
View
17D2
16D3
15D4
14NC
13
WE
1NC
2A6
3A5
4A4
5A3
6NC
7A0
8A1
9A2
10 NC
11
CS
12 Vss
8/12
Figure 14: 24-Lead Ceramic Flatpack (Solder Seal) - Package Style F
D A
3
C
C
C
MA5114
Pad 1
Radius r
3 corners
Ref
e b
Bottom
View
Millimetres Inches
Min. Nom. Max. Min. Nom. Max.
1
A5
A6
E
N
Vdd
A7
A8
A - - 2.16 - - 0.096
b1 - 0.51 - - 0.020 -
D 8.76 - 9.14 0.345 - 0.360
E 8.76 - 9.14 0.345 - 0.360
e - 1.02 - - 0.040 -
r - 0.19 - - 0.0075 -
XG470
A4
A3
NCA0A1
2
1
24
23
22
A9
Bottom
View
NC
NC
D1
D2
A2
987654
10
N
11
CS
Vss
12
13
WE
14
N
15
161718192021
D4
D3
Figure 15: 24-Pad Leadless Chip Carrier - Package Style L
9/12
MA5114
Package Option Burnin
Function F C L Via Static 1 Static 2 Dynamic Radiation
A6 2 1 2 R 0V 5V F6 5V
A5 3 2 3 R 0V 5V F5 5V
A4 4 3 4 R 0V 5V F4 5V
A3 5 4 5 R 0V 5V F3 5V
A0 7 5 7 R 0V 5V F0 5V
A1 8 6 8 R 0V 5V F1 5V
A2 9 7 9 R 0V 5V F2 5V
NC S 11 8 11 R 0V 5V 0V 5V
VSS 12 9 12 Direct 0V 0V 0V 0V
NW E 13 10 13 R 0V 5V 5V 5V
D4 15 11 15 R 0V 5V LOAD 5V
D3 16 12 16 R 0V 5V LOAD 5V
D2 17 13 17 R 0V 5V LOAD 5V
D1 18 14 18 R 0V 5V LOAD 5V
A9 21 15 21 R 0V 5V F9 5V
A8 22 16 22 R 0V 5V F8 5V
A7 23 17 23 R 0V 5V F7 5V
VDD 24 18 24 Direct 5V 5V 5V 5V
1. F0=150KHz, F1=F0/2, F2=F0/4, F3=F0/8 etc.
2. Burnin R=1k
3. Radiation R=10k
Figure 16: Burnin and Radiation Configuration
10/12
MA5114
RADIATION TOLERANCE
Total Dose Radiation Testing
For product procured to guaranteed total dose radiation
levels, each wafer lot will be approved when all sample
devices from each lot pass the total dose radiation test.
The sample devices will be subjected to the total dose
radiation level (Cobalt-60 Source), defined by the ordering
code, and must continue to meet the electrical parameters
specified in the data sheet. Electrical tests, pre and post
irradiation, will be read and recorded.
GEC Plessey Semiconductors can provide radiation
testing compliant with MIL-STD-883 test method 1019,
Ionizing Radiation (Total Dose).
SINGLE EVENT UPSET CHARACTERISTICS
Total Dose (Function to specification)* 1x105 Rad(Si)
Transient Upset (Stored data loss) 5x10
10
Rad(Si)/sec
Transient Upset (Survivability) >1x1012 Rad(Si)/sec
Neutron Hardness (Function to specification) >1x1015 n/cm
2
Single Event Upset** 3.4x10-9 Errors/bit day
Latch Up Not possible
* Other total dose radiation levels available on request
** Worst case galactic cosmic ray upset - interplanetary/high altitude orbit
Figure 17: Radiation Hardness Parameters
UPSET BIT
CROSS-SECTION
(cm2/bit)
Ion LET (MeV.cm2/mg)
Figure 18: Typical Per-Bit Upset Cross-Section vs Ion LET
11/12
MA5114
ORDERING INFORMATION
Unique Circuit Designator
Radiation Tolerance
Radiation Hard Processing
S
30 kRads (Si) Guaranteed
L
50 kRads (Si) Guaranteed
C
100 kRads (Si) Guaranteed
R
MAx5114xxxxx
Package Type
C
Ceramic DIL (Solder Seal)
F
Flatpack (Solder Seal)
L
Leadless Chip Carrier
For details of reliability, QA/QC, test and assembly
options, see ‘Manufacturing Capability and Quality
Assurance Standards’ Section 9.
QA/QCI Process
(See Section 9 Part 4)
Test Process
(See Section 9 Part 3)
Assembly Process
(See Section 9 Part 2)
Reliability Level
Rel 0
L
Rel 1
C
Rel 2
D
Rel 3/4/5/STACK
E
Class B
B
Class S
S
http://www.dynexsemi.com
e-mail: power_solutions@dynexsemi.com
HEADQUARTERS OPERATIONS
DYNEX SEMICONDUCTOR LTD
Doddington Road, Lincoln.
Lincolnshire. LN6 3LF. United Kingdom.
Tel: 00-44-(0)1522-500500
Fax: 00-44-(0)1522-500550
DYNEX POWER INC.
Unit 7 - 58 Antares Drive,
Nepean, Ontario, Canada K2E 7W6.
Tel: 613.723.7035
Fax: 613.723.1518
Toll Free: 1.888.33.DYNEX (39639)
Datasheet Annotations:
Dynex Semiconductor annotate datasheets in the top right hard corner of the front page, to indicate product status. The annotations are as follows:-
Target Information: This is the most tentative form of information and represents a very preliminary specification. No actual design work on the product has been started.
Preliminary Information: The product is in design and development. The datasheet represents the product as it is understood but details may change.
Advance Information: The product design is complete and final characterisation for volume production is well in hand.
No Annotation: The product parameters are fixed and the product is available to datasheet specification.
This publication is issued to provide information only which (unless agreed by the Company in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded
as a representation relating to the products or services concerned. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. The Company
reserves the right to alter without prior notice the specification, design or price of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute any
guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user's responsibility to fully determine the performance and suitability of any equipment using such information and
to ensure that any publication or data used is up to date and has not been superseded. These products are not suitable for use in any medical products whose failure to perform may result in significant injury
or death to the user. All products and materials are sold and services provided subject to the Company's conditions of sale, which are available on request.
All brand names and product names used in this publication are trademarks, registered trademarks or trade names of their respective owners.
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SALES OFFICES
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These offices are supported by Representatives and Distributors in many countries world-wide.
© Dynex Semiconductor 2000 Publication No. DS3581-5 Issue No. 5.0 January 2000
TECHNICAL DOCUMENTATION – NOT FOR RESALE. PRINTED IN UNITED KINGDOM
12/12
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