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PAM2319
DUAL HIGH-EFFICIENCY PWM STEP-DOWN DC-DC CONVERTER
Description
The PAM2319 is a dual step-down current-mode, DC-DC converter.
At heavy load, the constantf requency PWM control performs
excellent stability and transient response. To ensure the longest
battery life in portable applications, the PAM2319 provides a power-
saving Pulse-Skipping Modulation (PSM) mode to reduce quiescent
current under light load operation.
The PAM2319 supports a range of input voltages from 2.7V to 5.5V,
allowing the use of a single Li+/Li-polymer cell, multiple Alkaline/NiMH
cell, USB, and other standard power sources. The dual output
voltages are adjustable from 1.0V to 3.3V. Both channels employ
internal power switch and synchronous rectifier to minimize external
part count and realize high efficiency. During shutdown, the input is
disconnected from the output and the shutdown current is less than
0.1µA. Other key features include under-voltage lockout, soft-start,
short circuit protection and thermal shutdown.
Features
Pin Assignments
Applications
Supply Voltage: 2.7V to 5.5V
Output Voltage:
Vo1 ADJ/1000mA
Vo2 ADJ/2000mA
Low Quiescent Current: Channel 1: 40µA; Channel 2: 55µA
High Efficiency:
Switching Frequency: 3MHz(Channel 1)
2.5MHz(Channel 2)
Internal Synchronous Rectifier
Soft Start
Under-Voltage Lockout
Short Circuit Protection
Thermal Shutdown
Small W-DFN3X3-12L Pb-Free/Halogen Free Package
RoHS/REACH Compliant
PAM2319
Document number: DSxxxxx Rev. 1 - 1
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Portable Electronics
Personal Information Appliances
Wireless and DSL Modems
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Typical Applications Circuit
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PAM2319
Figure 1. Adjustable Voltage Regulator
Pin Descriptions
Pin
Number
1 FB2 Channel 2 feedback pin internally set to 0.6V.
2 VIN2 Input voltage pin of channel 2.
3 AGND2 Signal ground of channel 2 for small signal components.
4 VIN1 Input voltage pin of channel 1.
5 PGND1 Main power ground pin of channel 1
6 SW1 Channel 1 switching pin. The drains of the internal main and synchronous power MOSFET.
7 FB1 Channel 1 feedback pin internally set to 0.6V.
8 AGND1 Signal ground of channel 1 for small signal components.
9 EN1 Enable control input. Pull logic high to enable Vo1. Pull logic low to disable.
10 EN2 Enable control input. Pull logic high to enable Vo2. Pull logic low to disable.
11 PGND2 Main power ground pin of channel 2.
12 SW2 Channel 2 switching pin. The drains of the internal main and synchronous power MOSFET.
— Exposed Pad Connect to GND
PAM2319
Document number: DSxxxxx Rev. 1 - 1
W-DFN3x3-12L
Pin Name
Function
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Functional Block Diagram
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PAM2319
Note: 1. The diagram above just shows one channel.
Absolute Maximum Ratings (@T
These are stress ratings only and functional operation is not implied. Exposure to absolute maximum ratings for prolonged time periods may
affect device reliability. All voltages are with respect to ground.
Parameter Rating Unit
Input Voltage -0.3 to 6.5 V
EN1, FB1, SW1, EN2, FB2 and SW2 Pin Voltage
Maximum Junction Temperature 150 °C
Storage Temperature Range -65 to +150 °C
Soldering Temperature 260, 10sec °C
Recommended Operating Conditions (@T
Parameter Rating Unit
Supply Voltage 2.7 to 5.5 V
Ambient Temperature Range -40 to +85
Junction Temperature Range -40 to +1255
= +25°C, unless otherwise specified.)
A
-0.3 to (V
+0.3)
IN
= +25°C, unless otherwise specified.)
A
V
°C
Thermal Information
Parameter Symbol Package Max Unit
Thermal Resistance (Junction to Ambient)
Thermal Resistance (Junction to Case)
θ
JA
θ
JC
PAM2319
Document number: DSxxxxx Rev. 1 - 1
W-DFN3x3-12L 60
W-DFN3x3-12L 8.5
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°C/W
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PAM2319
Electrical Characteristics (@T
Channel 1
Parameter Symbol Test Conditions Min Typ Max Units
Input Voltage Range
UVLO Threshold
Regulated Feedback Voltage
Reference Voltage Line Regulation
Regulated Output Voltage Accuracy
Peak Inductor Current
Output Voltage Line Regulation LNR
Output Voltage Load Regulation LDR
Quiescent Current
Shutdown Current
Oscillator Frequency
Drain-Source On-State Resisitance
SW Leakage Current ILSW ±0.01 1 µA
Efficiency η
PSM Threshold
EN Threshold High
EN Threshold Low
EN Leakage Current
Soft-Start
Over Temperature Protection OTP 150 °C
OTP Hysteresis OTH 30 °C
PAM2319
Document number: DSxxxxx Rev. 1 - 1
= +25°C, VIN = 3.3V, VO = 1.8V, CIN = 10µF, CO = 10µF, L = 1µH, unless otherwise specified.)
A
V
IN
V
UVLO
V
FB
∆V
FB
V
IO = 100mA
O
I
VO = 90%
PK
I
Q
I
VEN = 0V
SD
f
OSC
R
DS(ON)
I
VIN = 3.3V
TH
V
EH
V
EL
I
EN
T
ON
Rising
V
IN
Hysteresis 240 mV
VIN Falling
0.588 0.600 0.612 V
0.3 %/V
V
= 2.7V to 5V, IO = 10mA
IN
I
= 1mA to 1000mA
O
No Load 40 80 µA
= 100%
V
O
VFB = 0V or VO =0V
P MOSFET 0.35 0.45 Ω
N MOSFET 0.35 0.45 Ω
Output1, I
= 500mA, VIN = 3.3V
O
1.5 V
0.3 V
±0.01 µA
From EN1 to Output 2 ms
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2.7 5.5 V
2.4 2.5 V
1.8 V
-3 +3 %
1.5 A
0.2 0.5 %/V
-2 +2 %
0.1 1 µA
3 MHz
1 MHz
84 %
100 mA
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PAM2319
Electrical Characteristics (@T
Channel 2
Parameter Symbol Test Conditions Min Typ Max Units
Input Voltage Range
UVLO Threshold
Regulated Feedback Voltage
Reference Voltage Line Regulation
Regulated Output Voltage Accuracy
Peak Inductor Current
Output Voltage Line Regulation LNR
Output Voltage Load Regulation LDR
Quiescent Current
Shutdown Current
Oscillator Frequency
Drain-Source On-State Resisitance
SW Leakage Current ILSW ±0.01 1 µA
Efficiency η
PSM Threshold
EN Threshold High
EN Threshold Low
EN Leakage Current
Soft-Start
Over Temperature Protection OTP 150 °C
OTP Hysteresis OTH 30 °C
PAM2319
Document number: DSxxxxx Rev. 1 - 1
= +25°C, VIN = 3.3V, VO = 1.2V, CIN = 10µF, CO = 10µF, L = 1µH, unless otherwise specified.)
A
V
IN
V
UVLO
V
FB
∆V
FB
V
IO = 100mA
O
I
VO = 90%
PK
I
Q
I
VEN = 0V
SD
f
VO = 100%
OSC
R
DS(ON)
I
VIN = 3.3V
TH
V
EH
V
EL
I
EN
T
ON
Rising
V
IN
Hysteresis 250 mV
VIN Falling
0.588 0.600 0.612 V
0.3 %/V
V
= 2.7V to 5V, IO = 10mA
IN
I
= 1mA to 1000mA
O
No Load 55 100 µA
P MOSFET 0.11 Ω
N MOSFET 0.85 Ω
Output1, I
= 500mA, VIN = 3.3V
O
1.5 V
0.3 V
±0.01 µA
From EN1 to Output 250 ms
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2.7 5.5 V
2.6 2.7 V
12 V
-3 +3 %
3 A
0.2 0.5 %/V
-2 +2 %
0.1 1.0 µA
2.5 MHz
87 %
250 450 mA
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Typical Performance Characteristics
(@TA = +25°C, VO = 1.8V CIN = 10µF, CO = 10µF, L = 1µH, unless otherwise specified.)
Channel 1
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PAM2319
PAM2319
Document number: DSxxxxx Rev. 1 - 1
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Typical Performance Characteristics (cont.)
(@TA = +25°C, VO = 1.2V CIN = 10µF, CO = 10µF, L = 1µH, unless otherwise specified.)
Channel 2
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PAM2319
PAM2319
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PAM2319
Application Information
The basic PAM2319 application circuit is shown in Page 2. External component selection is determined by the load requirement, selecting L first
and then C
Inductor Selection
For most applications, the value of the inductor will fall in the range of 0.47μH to 2μH. Its value is chosen based on the desired ripple current and
efficiency. Large value inductors lower ripple current and small value inductors result in higher ripple currents. Higher V
the ripple current as shown in equation. For channel 1, 1A reasonable starting point for setting ripple current is ∆I
channel 2, 2A setting ripple current is 800mA.
The DC current rating of the inductor should be at least equal to the maximum load current plus half the ripple current to prevent core saturation.
Thus, a 4.2A rated inductor should be enough for most applications (3A + 1.2A). For better efficiency, choose a low DC-resistance inductor.
V
CIN and C
In continuous mode, the source current of the top MOSFET is a square wave of duty cycle V
ESR input capacitor sized for the maximum RMS current must be used. The maximum RMS capacitor current is given by:
This formula has a maximum at V
significant deviations do not offer much relief. Note that the capacitor manufacturer's ripple current ratings are often based on 2000 hours of life.
This makes it advisable to further derate the capacitor, or choose a capacitor rated at a higher temperature than required. Consult the
manufacturer if there is any question.
The selection of C
Typically, once the ESR requirement for C
output ripple ∆V
Where f = operating frequency, C
highest at maximum input voltage since ∆I
Using Ceramic Input and Output Capacitors
Higher values, lower cost ceramic capacitors are now becoming available in smaller case sizes. Their high ripple current, high voltage rating and
low ESR make them ideal for switching regulator applications. Using ceramic capacitors can achieve very low output ripple and small circuit size.
When choosing the input and output ceramic capacitors, choose the X5R or X7R dielectric formul ations. These dielectrics have the best
temperature and voltage characteristics of all the ceramics for a given value and size.
Thermal Consideration
Thermal protection limits power dissipation in the PAM2319. When the junction temperature exceeds +150°C, the OTP (Over Temperature
Protection) starts the thermal shutdown and turns the pass transistor off. The pass transistor resumes operation after the junction temperature
drops below +120°C.
For continuous operation, the junction temperature should be maintained below +125°C. The power dissipation is defined as:
I
is the step-down converter quiescent current. The term tsw is used to estimate the full load step-down converter switching losses.
Q
PAM2319
Document number: DSxxxxx Rev. 1 - 1
and C
IN
I
1.2V 1.5V 1.8V 2.5V 3.3V
O
L 1.2µH 1.5µH 2.2µH 2.2µH 2.2µH
OUT
required
C
IN
.
OUT
1
Lf
1
V
OUTL
V
OUT
Equation (1)
V
IN
Selection
II
OMAXRMS
= 2V
IN
OUT
is driven by the required effective series resistance (ESR).
OUT
OUT
is determined by:
OUT
2
IP
OD
f8/1ESR
IV
LOUT
C
OUT
= output capacitance and ∆IL = ripple current in the inductor. For a fixed output voltage, the output ripple is
OUT
increases with input voltage.
L
V
IN
VVV
V
IN
, where I
RMS
has been met, the RMS current rating generally far exceeds the I
RVVRV
2/1
OUTINOUT
=I
/2. This simple worst-case condition is commonly used for design because even
OUT
L)ON(DSOINH)ON(DSO
t
SW
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or V
IN
= 400mA (40% of 1A) and for
L
. To prevent large voltage transients, a low
OUT/VIN
RIPPLE
VIIF
INQOS
also increases
OUT
(P-P) requirement. The
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Application Information (cont.)
For the condition where the step-down converter is in dropout at 100% duty cycle, the total device dissipation reduces to:
2
OD
VIRIP
INQH)ON(DS
PAM2319
Since R
voltage range. The maximum power dissipation depends on the thermal resistance of IC package, PCB layout, the rate of surrounding airflow
and temperature difference between junction and ambient. The maximum power dissipation can be calculated by the following formula:
Where T
junction to the ambient. Based on the standard JEDEC for a two layers thermal test board, the thermal resistance θ
The maximum power dissipation at T
P
, quiescent current, and switching losses all vary with input voltage, the total losses should be investigated over the complete input
DS(ON)
TT
A)MAX(J
P
D
J(max)
= (125°C - 25°C) /60°C/W = 1.67W
D
is the maximum allowable junction temperature +125°C. TA is the ambient temperature and θJA is the thermal resistance from the
JA
= +25°C can be calculated by following formula:
A
of WDFN3x3 is 60°C/W.
JA
Setting the Output Voltage
The internal reference is 0.6V (Typical). The output voltage is calculated as below:
The output voltage is given by Table 1.
1R
Table 1: Resistor selection for output voltage setting.
V
O
V
O
1.2V 150k 150k
1.5V 150k 100k
1.8V 300k 150k
2.5V 380k 120k
3.3V 680k 150k
1x6.0
2R
R1 R2
Pulse Skipping Mode (PSM) Description
When load current decreases, the peak switch current in Power-PMOS will be lower than skip current threshold and the device will enter into
Pulse Skipping Mode.
In this mode, the device has two states, working state and idle state. First, the device enters into working state controlled by internal error
amplifier.When the feedback voltage gets higher than internal reference voltage, the device will enter into low I
blocks disabled. The output voltage will be reduced by loading or leakage current. When the feedback voltage gets lower than the internal
reference voltage, the convertor will start a working state again.
idle state with most of internal
Q
100% Duty Cycle Operation
As the input voltage approaches the output voltage, the converter turns the P-Channel transistor continuously on. In this mode the output voltage
is equal to the input voltage minus the voltage drop across the P-Channel transistor:
where R
= P-Channel switch ON resistance, I
DS(ON)
RRIVV
LDSONLOADINOUT
= Output Current, RL = Inductor DC Resistance
LOAD
UVLO and Soft-Start
The reference and the circuit remain reset until the VIN crosses its UVLO threshold.
The PAM2319 has an internal soft-start circuit that limits the in-rush current during start-up. This prevents possible voltage drops of the input
voltage and eliminates the output voltage overshoot.
Thermal Shutdown
When the die temperature exceeds +150°C, a reset occurs and the reset remains until the temperature decrease to +120°C, at which time the
circuit can be restarted.
PAM2319
Document number: DSxxxxx Rev. 1 - 1
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PAM2319
Application Information (cont.)
Short Circuit Protection
Channel 1:
The swich peak current is limited cycle-by-cycle to a typical vaule in the event of an output voltage short circuit. The device operates with a
frequency of 1MHz and minimum duty clycle. Therefore the average input current is typical 350mA (V
Channel 2:
When the converter output is shorted or the device is overloaded, each high-side MOSFET current-limit event (3A typ) turns off the high-side
MOSFET and turns on the low-side MOSFET. An internal counter is used to count the each current-limit event. The counter is reset after
consecutive high-side MOSFETs turn on without reaching current limit. If the current-limit condition persists, the counter fills up. The control logic
then stops both high-side and lowside MOSFETs and waits for a hiccup period, before attemping a new soft-start sequence. The counter bits is
decided by V
1.7%. The hiccup mode is disable during soft-start time.
voltage. If VFB 0 2, the counter is 3-bit counter; if VFB > 0.2 the counter is 6-bit counter. The typical hicuup made duty cycle is
FB
= 3.3V).
IN
PCB Layout Check List
When laying out the printed circuit board, the following checklist should be used to ensure proper operation of the PAM2319. Check the following
in your layout:
1. The input capacitor should be close to IC as close as possible.
2. Minimize the switching loop area to avoid excessive switching noise.
3. Two parts GND should be separately layout to avoid disturbing by each other.
4. Must put a small decoupling capacitor between Vin2 Pin and AGND2 Pin.
5. Vo2 output capacitor should be close to output connector to minimize PCB t race resistance affect on ripple voltage. Recommend use two
output capacitor, one close to inductor and IC, another close to output connector.
6. PGND1 Pin should not directly connect to the thermal pad (PGND), it should connect to input capacitor GND then to other GND.
7. AGND should connect to PGND at input capacitor GND.
8. For the good thermal dissipation, PAM2316 has a heat dissipate pad in the bottom side, it should be soldered to PCB surface. For the copper
area can't be large in the component side, so we can use multiple vias connect to other side of the PCB.
9. Avoid using vias in the high-current paths. If vias are unavoidable, use multiple vias in parallel to reduce resistance and inductance.
Ordering Information
Part Number Part Marking Package Type Standard Package
PAM2319AYAA
PAM2319
Document number: DSxxxxx Rev. 1 - 1
BNAA
XXXYW
W-DFN3x3-12L 3000 Units/Tape & Reel
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Marking Information
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PAM2319
Package Outline Dimensions (All dimensions in mm.)
W-DFN3x3-12
PAM2319
Document number: DSxxxxx Rev. 1 - 1
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PAM2319
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INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
(AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION).
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without further notice to this document and any product described herein. Diodes Incorporated does not assume any liability arising out of the
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indirectly, any claim of personal injury or death associated with such unintended or unauthorized application.
Products described herein may be covered by one or more United States, international or foreign patents pending. Product names and markings
noted herein may also be covered by one or more United States, international or foreign trademarks.
Diodes Incorporated products are specifically not authorized for use as critical components in life support devices or systems without the express
written approval of the Chief Executive Officer of Diodes Incorporated. As used herein:
A. Life support devices or systems are devices or systems which:
1. are intended to implant into the body, or
2. support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the
labeling can be reasonably expected to result in significant injury to the user.
B. A critical component is any component in a life support device or system whose failure to perform can be reasonably expected to cause the
failure of the life support device or to affect its safety or effectiveness.
Customers represent that they have all necessary expertise in the safety and regulatory ramifications of their life support devices or systems, and
acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products and any
use of Diodes Incorporated products in such safety-critical, life support devices or systems, notwithstanding any devices- or systems-related
information or support that may be provided by Diodes Incorporated. Further, Customers must fully indemnify Diodes Incorporated and its
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Copyright © 2012, Diodes Incorporated
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IMPORTANT NOTICE
LIFE SUPPORT
PAM2319
Document number: DSxxxxx Rev. 1 - 1
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