2XSRFINI/AAnalog RF signal input after passing through the equalizer
3XSIPINI/AInverting input pin of data slicer
5XSDSSLVO/ASlice level output pin
6XSRSLINTI/AReference current setting pin for analog data slicer
8XSAWRCO/AOutput for enlarge VCO range. Analog output from DAC buffer
9XSRFGCO/ARF gain control output
10XSEFGCO/AE,F gain control output
11XSFOCUSO/AOutput voltage level for focusing buffer IC
12XSTRACKO/AOutput voltage level for tracking buffer IC
13XSSLEGO/AOutput voltage level for sledge buffer IC
15XSMOTORO/AOutput voltage level for spindle motor buffer IC
17XSRFRPLPI/AHigh bandwidth low pass filter input for RFRP
18XSTELPI/AHigh bandwidth low pass filter input for TE
19XSVREF2I/A2.1V reference voltage input
20XSRFRPI/ARF ripple/envelope signal input
21XSTEXII/ATracking zero crossing input signal
23XSTEII/ATracking error input signal
24XSFEII/AFocus error input signal
25XSCEII/A
1. Center error input signal
2. Photo Interrupt input
DescriptionPin No.
PC
MPEG
DEC.
13
Page 14
ADV-M71
14
Pin Name
27XSSBADI/ASub-beam addition signal input
166XSPDIREFI/A
167XSFDIREFI/A
169XSPLLFTR2I/AData PLL loop filter pin#2
171XSFDOO/AOutput node of frequency detector charge pump circuit
172XSFTROPII/AInput node of loop filter OP circuit
173XSVR_PLLI/APLL reference voltage input
174XSPDOFTR2I/APhase detector filter pin#1
175XSVREFOO/AReference voltage output
176XSAWRCVCOI/AAuto Wide Range Control of VCO input pin. For enlarge VCO range in CAV mode
29XSDFCTIDetect detection signal input
30XSCSJOChip select signal for accessing control registers
31XSCLKOClock output for accessing control registers
32XSDATAI/ORegisters data input/output pin
33XSLDCOLaser diode on/off control output for both CD/DVD
34XSFGINIMotor Hall sensor input
35XSSPDONOSpindle motor on output
36, 37, 38, 39 XSFLAG[3:0]OThese pins are used to monitor some status of servo control block
48, 51, 52XGPIO[2:0]I/O
40XMP1_7I/OInternal microcontroller programmable I/O port 1.7.
41XMP1_6I/OInternal microcontroller programmable I/O port 1.6.
43XMP1_5I/OThis pin is now changed to be NC.
44XMP1_4I/OInternal microcontroller programmable I/O port 1.4.
45XMP1_3I/OInternal microcontroller programmable I/O port 1.3.
47XMP1_2I/OInternal microcontroller programmable I/O port 1.2.
49XMP1_1I/OInternal microcontroller programmable I/O port 1.1.
57XMP1_0I/O
46XMFSCSJI/OOutput chip select connected to external flash ROM chip enable pin
54XMPSENJI/OOutput program store enable connected to external ROM PSENJ pin.
56XMALEI/OThis signal is used as address latch signal in address/data mux mode
70XMCSJI/O
71XMRDJI/O
72XMWRJI/OThis signal is used as the Wire Strobe signal
73XMINT1JI/O
74, 75, 77, 78,
79, 80, 81, 82,
83, 84, 85, 86,
87, 89, 90, 91
62, 63, 64, 65,
66, 67, 68, 69bus for the 8-bit processor mode.
163XTPLCKI/OPLCK test pin
164XTSLRFI/OSLRF test pin
59XOSC1ICrystal input/System clock. The input frequency from outside crystal or oscillator is 33.8688MHz
60XOSC2OCrystal output
53XCRSTJI
94XHCS1JIThis pin is used to select the command block task file registers
93XHCS3JIThis pin is used to select the control block task file registers
103XHIORJIAsserted by the host during a host I/O read operation
104XHIOWJIAsser ted by the host during a host I/O write operation
105XHDRQO
101XHDACKJI
99XHCS16JO
50XHRSTJIHost Reset. The reset of ATA bus
100XHINTO
XMA[15:0]I/OThese pins are used as address bus
XMD[7:0]I/O
Type
Phase detector reference current generator. Connect a resistor between this pin and
ground to set reference current
Frequency detector reference current generator. Connect a resistor between this pin and
ground to set reference current
1. These pins are used as general purpose I/O bus
2. When use internal microcontroller, XGPIO[2] can be used as programmable I/O port 3.6.
Internal microcontroller programmable I/O port 1.0.
This pin is default used as the A16 (microcontroller address line 16)
1. This signal must be asserted for all microcontroller accesses to the register of this chip
2. When use internal microcontroller, this signal can be used as programmable I/O port 3.1
1. This signal is used as the Read Strobe signal
2. When use internal microcontroller, this signal can be used as programmable I/O port 3.0
1. This signal is an interrupt line to the microcontroller
2. When use internal microcontroller, this signal can be used as programmable I/O port 3.7
These pins are used as data bus for the 16-bit processor mode, or the address/data mux
Chip Reset. As asserted low input generates a component reset that stops all operations within
the chip and deasserts all output signals. All input/output signals are set to input.
1.
DMA request. This pin is configured as the DMA request signal, and is used during DMA transfer
between the host and the controller. This pin is tri-stated when DMA transfers are not enabled.
2.
MPEG acknowledge. This pin is used as the ACKJ signal when MPEG interface mode is selected.
1. DMA acknowledge. This pin is configured as DACKJ, and is used as the DMA acknowledge
signal during DMA data transfers.
2. MPEG request. This pin is used as the REQ signal when MPEG interface mode is selected
1. 16-bit data select. This signal indicates that a 16-bit data transfer is active on the host data
bus. This pin is open-drain tri-state output.
2. MPEG clock. This pin is used as the CLOCK signal when MPEG interface mode is selected.
1. Host interface request. This tri-state pin is the host interrupt request, and is asserted to
indicate to the host that the controller needs attention.
2. MPEG begin. This pin is used as the BEGIN signal when MPEG interface mode is selected
DescriptionPin No.
14
Page 15
ADV-M71
15
Pin Name
97XHPDIAGJI/OThis pin is used as the Passed Diagnostics signal, and may be an input or an open-drain output
92XHDASPJI/O
102XHIORDYI/O
95, 96, 98XHA[2:0]I
106, 107, 108,2.
109, 111, 112,3. VCD I/F. Bit3-0 are used as VCD I/F signal when VCD function is enabled. The relationship of
113, 114, 116,bit3-0 and VCD I/F is as follow
117, 118, 119,HD0—CD-DATA
120, 121, 122,HD1—CD-LRCK
123HD2—CD-BCK
143XRSDCLKOThis signal is the clock output for SDRAM
147XROEJO
142XRWEJOThis signal is asserted low when a buffer memory write operation is active
124, 125, 126,
127, 128, 129,
131, 132, 134,
135, 136, 137,
138, 139, 140,
141
4AVDD5_DSAnalog Power +5V for Data Slicer part
14AVDD5_DAAnalog Power +5V for DAC part
26AVDD5_ADAnalog Power +5V for ADC part
168AVDD5_PLAnalog Power +5V for Data PLL part
7, 55, 58, 76,
115, 146,
150, 162
1AVSS_DSAnalog Ground for Data Slicer part
16AVSS_DAAnalog Ground for DAC part
22AVSS_ADAnalog Ground for ADC part
170AVSS_PLAnalog Ground for Data PLL part
28, 42, 61,
88, 110, 130,
138, 154, 165
XHD[15.0]I/O
XRA[11:0]O1: Normal operation
XRD[15:0]I/OThese signals are the 8-bit parallel data lines to/from the buffer memory.
VDDPower +3.3V for digital core logic and pad
GNDDigital Ground core logic and pad.
Type
This pin is used as the Drive Active/Slave Present signal, and is an input or an open-drain
output. This pin is used for Master/Slave drive communication and/or for driving an LED
1. I/O channel ready. This signal is driven low to extend host transfer cycles when the controller
is not ready to respond. This pin will be tri-stated when a read or write is not in progress.
2. MPEG error. This pin is used as the ERROR signal when MPEG interface mode is selected
Host address lines. The host address lines A[2:0] are used to access the various host control,
status, and data registers
1. Host data bus. This bus is used to transfer data and status between the host and the controller.
MPEG data bus 7-8. The HD[7:0] are used as the DATA [7:0] when MPEG interface mode is selected.
HD3—CD-C2PO
This signal is used as the memory output enable for external DRAM buffers. After RSTJ is
asserted, this signal will be low
This signal is used as Row address output to external DRAM buffer. After RSTJ is asserted, this
signal will be high
This signal is used as column address output to external DRAM. After RSTJ is asserted, this
signal will be high
1. RAM address lines. These are bits11-0 for addressing the buffer memory.
2. Hardware setting. The bits6-0 are used as hardware setting for some functions.
RA[9] : FLASH size is 64K/128K
1: FLASH size is 64K
0: FLASH size is 128K
RA[8] : External CPU is 8032/H8
1: 8032
0: H8
RA[7] : Microcontroller programmable I/O port 1 pin control
1: By internal microcontroller
0: By registers to decide input/output
RA[6] : System test pin output
0: System test pin output
RA[5] : For testing purpose, don’t need to set
RA[4] : IDE master/slave
1: Slave
0: Master
RA[3] : For testing purpose, don’t need to set
RA[2] : For testing purpose, don’t need to set
RA[1-0] : MCU Mode selection
11: Normal Mode (internal uP, internal address latch)
10: Outside uP Mode (ICE Mode)
01: Test mode for internal uP testing
00: Internal uP mode with external address latch
DescriptionPin No.
15
Page 16
M30626FHPGP (MA: IC302)
ADV-M71
16
M30626FHPGP PORT
Pin No. port function Port settingPort nameExplanation
1P94
2P93
3P92
4P91
5P90
6BYTE-Gnd
7CNVSS-don't use
8P87
9P86
10RESETRESETReset input
11XOUTXOUTXtal output
12VSSVSSGnd
13XINXINXtal input
14VCCVCCVcc
15NMI-don't use
16INT2
17INT1
18INT0INTDE RXDSerial data input from DENON BUS
19TA4IN
20P80
21P77
22P76
23P75
24P74
25P73
OE2P CS
O3811 DATA
SOE2P DI
SIE2P DO
SOE2P CK
O3811 CLK
OVMUTE
INTPROTECT
INTESS CS
I50/60
OPROG/INTE
IVR JOG-B
IVR JOG-A
IFN JOG-B
IFN JOG-A
OFLCS
Chip select output to EEPROM
Serial data output to elec.VR
Serial data output to EEPROM
Serial data input from EEPROM
Serial clock output to EEPROM
Serial clock output to elec.VR
Mute output to video driver
Protect signal input L:Protect detect
Chip select input from ESS
Line pulse input(50/60Hz)
Progressive/Interlace switching signal output
VR encoder pulse-B input
VR encoder pulse-A input
Function encoder pulse-B input
Function encoder pulse-A input
Chip select output to FLD driver
16
Page 17
Pin No. port function Port settingPort nameExplanation
26CLK2
27RXD2
28TXD2
29TXD1
30P66ODSPCOREPOWDSP(Mel100) core power ON/OFF switching H:P-ON
31CLK1
32P64
33TXD0
34RXD0
35CLK0
36P60
37P57
38P56
39P55O-don't use
40P54
41P53
42P52ORGB HConposite/S/RGB switching
43P51
44P50O-don't use
45P47
46P46
47P45
48P44
49P43
50P42
51P41
52P40
53P37
54P36
55P35
56P34
57P33OEXP OEfor port expand
58P32OEXP STBfor port expand
59P31OEXP DAfor port expand
60VCCVCCVcc
61P30OEXP CLKfor port expand
62VSSVSSGnd
63P27
64P26
65P25
66P24
67P23
68P22
69P21
70P20
71INT5
72INT4
73INT3
74P14
75P13
76P12
77P11
78P10
79P07
80P06
81P05
82P04
83P03
84P02
85P01
SODE CK
SIDE RXD
SODE TXD
SOFLDA
SOFLCK
OFLRST
SOESS DO
SIESS DI
SIESS CK
IESS ON
ODVD RST
IHP SW
O
REQ1
ODVD ON/OFF
OVCONT1
OVCONT2
OCODEC RST
OSEL CLK
OBSE
OERR MUTE
ODIR CE
ODIR RST
OCLATCH
OP.ON/OFF
OSCART MUTE
OSUB ON
OFR-RELAY
ITEMP FAN
ISTEREO
ITUNED
OTMUTE
OTU CE
OTU DI
OTU CK
ITU DO
DFRESExt reset signal from ESS
I
IDIR INT1
IREMOTE
OSYR
ODSP1-RST
OROM RST1
ODSPOSCON
ODSPIOPOWER
IOIO8
IOIO7
IOIO6
IOIO5
IOIO4
IOIO3
IOIO2
Serial clock output to DENON BUS
Serial data input from DENON BUS
Serial data output to DENON BUS
Serial data output to FLD driver
Serial clock output to FLD driver
RESET output to FLD driver
Serial data output to ESS
Serial data input from ESS
Serial clock input from ESS
ESS"Active" signal input H:Active
Forced reset output to DVD drive
H/P insert detect signal input H:insert
Control signal input from DSP(Mel100)
DVD drive power supply ON/OFF switching H:P-ON
Aspect ratio switching-1
Aspect ratio switching-2
Reset output to CODEC(AD1837)
DSP clock switching
DSP mute output
Mute output at DSP error
Chip select output to DIR(LC89057)
Reset output to DIR(LC89057)
Latch output to DIR(LC89057)
Main power ON/OFF switching H:ON
Mute output to SCART audio output H:mute-on
Standby power ON/OFF switching H:OFF
Front SP relay ON/OFF switching H:ON
Temp detect input for fan L: fan-on
"STEREO"indicator input from tuner
Tuned detect input from tuner
Mute output to tuner audio signal L:mute-on
Chip enable output to tuner
Serial data output to tuner
Serial clock output to tuner
Serial data input from tuner
Interrupt request from DIR
Remote controler signal input
Reset output to RDS IC
Reset output to DSP
Reset output to DSP ROM
OSC(for DSP) ON/OFF switching
DSP(Mel100) I/O power ON/OFF switching H:P-ON
I/O interface port to DSP
I/O interface port to DSP
I/O interface port to DSP
I/O interface port to DSP
I/O interface port to DSP
I/O interface port to DSP
I/O interface port to DSP
ADV-M71
17
17
Page 18
Pin No. port function Port settingPort nameExplanation
Analog inputs for RF Single Buffer. Differential analog inputs to the RF single-ended output buffer
and full wave rectifier
Low Impedance Enable. A TTL compatible input pin that activates the FDCHG switches. A low
32FDCHG#I
level activates the switches and the falling edge of the internal FDCHG triggers the fast decay for
the MIRR bottom hold circuit. (open high)
49HOLD1I
Hold Control. A TLL compatible control pin which, when pulled high, disables the RF AGC charge
pump and holds the RF AGC amplifier gain at its present value. (open high)
11~14D, C, B, AIPhoto Detector Interface Inputs. Inputs from the main beam Photo detector matrix outputs
5~8A2, B2, C2, D2I
Photo Detector Interface Inputs. AC coupled inputs for the DPD from the main beam Photo
detector matrix outputs
15~16F, EICD tracking Error Inputs. Inputs from the CD photo detector error outputs.
3~4PD1, PD2ICD Photo detector Interface Inputs. Inputs from the CD photo detector error outputs
40MEIIMirror Envelope Inputs. The SIGO envelope input pin
35MINI
RF signal Input for Mirror. AC coupled inputs for the mirror detection circuit from the pull-in signal
output. (PI)
21DVDPDIAPC Input. DVD APC input pin from the monitor photo diode
23CDPDIAPC Input. CD APC input pin from the monitor photo diode
25LDON#IAPC Output On/Off. APC output control pin. A low level activates the LD output. (open high)
22DVDLDOAPC output. DVD APC output pin to control the laser power
24CDLDOAPC output. CD APC output pin to control the laser power
56BYPI/OThe RF AGC integration capacitor CBYP, is connected between BYP and VPA
9CPI/O
10CNI/O
45LCP—Center Error LPF pin. An external capacitance is connected between this pin and the LCN pin
44LCN—Center Error LPF pin. An external capacitance is connected between this pin and the LCP pin
30MP—MIRR signal Peak hold pin. An external capacitance is connected to between this pin and VPB
31MB—MIRR signal Bottom hold pin. An external capacitance is connected to between this pin and VPB
39MEV—Sigo Bottom Envelope pin. An external capacitance is connected to between this pin and VPB
17CDTE—CD Tracking. E-F Opamp output for feedback
38TPH—PI Top Hold pin. An external capacitance is connected to between this pin and VPB
26VC—
27VCI—Reference Voltage input. DC bias voltage input for the servo input reference
18VCI2—Reference Voltage input. DC bias voltage input for the servo input reference
55RX—
33MLPF—MIRR signal LPF pin. An external capacitance is connected between this pin and VPB
19NC—No Connect
48SDENI
47SDATAI/O
46SCLKI
58VPAPower. Power supply pin for the RF block and serial port
28VPBPower. Power supply pin for the servo block
50VNAGround. Ground pin for the RF block and serial port
20VNBGround. Ground pin for the servo bolck
Type
Defect Output. Pseudo CMOS output. When a defect is detected, the DFT output goes high. Also
the servo AGC output can be monitored at this pin, when CAR bits 7-4 are ‘0011’
Pull-in Signal Output. The summing signal output of A, B, C, D or PD1, PD2 for mirror detection.
Reference to VCI
Differential Phase tracking LPF pin. An external capacitance is connected between this pin and
the CN pin
Differential Phase tracking LPF pin. An external capacitance is connected between this pin and
the CP pin
Reference Voltage output. This pin provides the internal DC bias reference voltage (+2.5V lix).
Output Impedance is less than 50ohms
Reference Resistor Input. An external 8.2kohm, 1% resistor is connected from this pin to ground
to establish a precise PTAT (proportional to absolute temperature) reference current for the filter
Serial Data Enable. Serial Enable CMOS input. A high level input enable the serial port (Not to be
left open)
Serial Data. Serial data bi-directional CMOS pin. NRZ programming data for the internal registers
is applied to this input ( Not to be left open)
Serial Clock. Serial Clock CMOS input. The clock applied to this pin is synchronized with the data
applied to SDATA (Not to be left open)
1,39DVDDDigital Power Supply. Connect to digital 5V supply.
2CLATCHILatch Input for Control Data
33CINISerial Control Input
4PD/RSTIPower-Down/Reset
5,10,16,24,30,35AGNDAnalog Ground
6,12,25,31NCNot connected
7,13,26,32OUTLxODACx Left Channel Output
8,14,27,33NCNot connected
9,15,28,34OUTRxODACx Right Channel Output
11,19,29AVDDAnalog Power Supply. Connect to analog 5V supply.
17FILTDFilter Capacitor Connection. Recommend 10µF/100nF.
18FILTRReference Filter Capacitor Connection. Recommended 10µF/100nF.
20ADCLNIADC Left Channel Negative Input
21ADCLPIADC Left Channel Positive Input
22ADCRNIADC Right Channel Negative Input
23ADCRPIADC Right Channel Positive Input
36M/SIADC Master/Slave Select
37DLRCLKI/ODAC LR Clock
38DBCLKI/ODAC Bit Clock
40,52DGNDDigital Ground
41-44DSDATAxIDACx Input Data (Left and Right Supply)
45ABCLKI/OADC Bit Clock
46ALRCLKI/OADC LR Clock
47MCLKIMaster Clock Input
48ADVDDDigital Output Driver Power Supply
49ASDATAOADC Serial Data Output
50COUTOOutput for Control Data
51CCLKIControl Clock Input for Control Data
Active on the positive going edge to sample all input.
Disables or enables device operation by masking or enabling all input
except CLK,CKE and L(U)DQM
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
Row/column aaddresses are multiplexed on the same pins.
Row address : RA0 ~ RA10,column address : CA0 ~ CA7
Selects bank to activated during row address latch time.
Select bank for read/write during column address latch time.
Latches row addresses on the positive going edge of the CLK
with RAS low.
Enables row access & precharge.
Latches column addresses on the positive going edge of the CLK
with CAS low.
Enables column access.
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
Makes data output Hi-Z, t
Blocks data input when L(U)DQM active.
Data inputs/outputs are multiplexed on the same pins.
Powe and ground for the input buffers and the core logic.
Isolated power supply and ground for the output buffers to provide
improved noise immunity.
This pin is recommended to be left No Connection on the device.
9H1+IHall signal (H1+)
10H1-IHall signal (H1-)
11H2+IHall signal (H2+)
12H2-IHall signal (H2-)
13H3+IHall signal (H3+)
14H3-IHall signal (H3-)
15VHIHall bias
16NC-No connection
17PC1-Phase compensation capacitor
18SBIShort brake
19FG3XOFG waveform (3X)
20DIRORotational direction output
21ECRIOutput current control reference
22ECIOutput current control voltage
23S/SIPower save (Start/Stop switch)
24FG1XOFG waveform (1X)
25VCC-Supply voltage (Signal)
26NC-No connection
27VM-Supply voltage (Motor)
28CS1-Output current detection
First stage of the shift register goes low.
Other stages store the data of previous stage, respectively.
First stage of the shift register goes high.
Other stages store the data of previous stage, respectively.
X↓HXXShift-register state is not changed.
XXX↑XShift-register data is stored in the storage register.
XXX↓XStorage-register state is not changed.
ADV-M71
FRONT
VIEW
C
IN
V
VO
V
GND
32
logic diagram (positive logic)
13
OE
12
RCLK
10
SRCLR
11
SRCLK
14
SER
Q
1D
C1
R
Q
2D
C2
R
2D
Q
C2
R
2D
Q
C2
R
2D
Q
C2
R
2D
Q
C2
R
2D
Q
C2
R
3D
Q
C3
3D
Q
C3
3D
Q
C3
3D
Q
C3
3D
Q
C3
3D
Q
C3
3D
Q
C3
15
Q
A
1
Q
B
2
Q
C
3
Q
D
4
Q
E
5
Q
F
6
Q
G
2D
Q
C2
R
3D
Q
C3
7
Q
H
9
Q
H
32
Page 33
STK402-050 (AP: IC401)
Block Diagram
ADV-M71
33
8
FRONT VIEW
1
SN74HCU04PWR (ME: U8)
1
1Y
2Y
GND
1A
2
3
2A
4
5
3A
6
3Y
7
14
13
12
11
10
9
8
4
R1
C1
1
TR1TR2
2
R3
R4
15
TR3
D1
R2
SUB
13
5
TR4
TR7
R6
TR5
TR8
TR6
R5
R7
7610
12
TR9
TR11
R8
C2
TR14
TR12
TR13
R9
R11
R12
R10
TR10
11
R13
TR15
TR16
R14
9
14 15
AT24C02N-10SC (ME: U13)
Vcc
6A
6Y
1
5A
5Y
4A
A0
A1
A2
GND
2
3
4
4Y
VCC
8
WP
7
SCL
6
SDA
5
BD4828G (MA: IC303)
VDD
2
1V
OUT
V
DD
GND
2
3
N.C.
5
4 N.C.
Vref
GND
1
VOUT
3
SE-B2 (AP: IC908) SI-8050JF (AP: IC910,911)
SI-8120JF (AP: IC909)
FRONT
VIEW
REF
GROUND
2
1 REF
3
GND
FRONT
VIEW
IN
V
OUT
GND
SW
OS
V
ON/OFF
C
COLLECTOR
33
Page 34
STR-F6238S (AP: IC902)
O.C.P.
GND
D
V
IN
F.B
FRONT
VIEW
PC123 (AP: IC914)
UVLO
REG
Drive
OVP
TSD
TSD
Icont
GND
OCP/FB
S
D
1
3
4
2 , 5
7 , 8
Comp.
OCP
OSC
PWM Latch
Internal Bias
Vin
Latch
Delay
R
S Q
TOP VIEW
ANODE
CATHODE
COLLECTOR
EMITTER
Start
Reg.
T.S.D.
O.L.P
ADV-M71
4
VIN
34
3
D
DRV.REG
O.V.P
Latch
O. S. C
DRV
Rg3
O.C.P
INH1
Rg2
Rg1
2
GND
1
O.C.P
STR-A6359 (AP: IC801)
1
S
GND
2
3
IN
V
OCP/FB
4
Cu rre nt
Mi rro r
5
F.B
D
8
D
7
6
N.C.
GND
5
INH2
F.B
RC1117S285T (ME: Q4) VA6309M (ME; Q5)
3
IN
2
1
OUT
ADJ/GND
34
V
OUT
Page 35
TRANSISTORS
ADV-M71
35
2SC4132T100(PQR)
B
TOP
CC
VIEW
E
DIODES (LED included)
SPR-54MVW
TOP VIEW
SIDE VIEW
RedGreen
2SK2731
G
TOP
VIEW
S
D
MMBD4148SE
35
Page 36
●FLTUBEHNV-15SS04T(MA:FL101)
(45)
(46)(90)
ADV-M71
(1)
36
PIN CONNECTION
GRID ASSIGNMENT
36
Page 37
ANODE CONNECTION
ADV-M71
37
37
Page 38
PRINTED WIRING BOADE
1U-3527 MAIN UNIT ASS’Y COMPONENT SIDE
ADV-M71
38
38
Page 39
1U-3527 MAIN UNIT ASS’Y FOIL SIDE
ADV-M71
39
39
Page 40
1U-3528 AMP/POWER UNIT ASS’Y COMPONENT SIDE
ADV-M71
40
40
Page 41
1U-3528 AMP/POWER UNIT ASS’Y FOIL SIDE
ADV-M71
41
41
Page 42
1U-3474A DSP UNIT ASS'Y
ADV-M71
42
COMPONENT SIDE
42
FOIL SIDE
Page 43
RL-S871 MECHANISM UNIT ASS’Y COMPONENT SIDERL-S871 MECHANISM UNIT ASS’Y FOIL SIDE
ADV-M71
43
43
Page 44
NOTE FOR PARTS LIST
l Part indicated with the mark "" are not always in stock and possibly to
take a long period of time for supplying, or in some case supplying of
part may be refused.
l When ordering of part, clearly indicate "1" and "I" (i) to avoid mis-
supplying.
l Ordering part without stating its part number can not be supplied.
l Part indicated with the mark "
l Not including Carbon Film Resister ±5%, 1/4W Type in the P.W.Board
parts list. (Refer to the Schematic Diagram for those parts.)
l Not including Carbon Chip Resister 1/16W Type in the P.W.Board parts
list. (Refer to the Schematic Diagram for those parts.)
WARNING:
Parts marked with this symbol
Use ONLY replacement parts recommended by the manufacturer.
ll
Resistors
l
ll
Ex.: RN14K2E182GFR
Type Shape Power Resist- Allowable Others
and per-anceerror
formance
" is not illustrated in the exploded view.
have critical characteristics.
ADV-M71
5% 1/4W
1/16W
RN14K2E182GFR
44
RD : Carbon2B : 1/8W F : ±1%P : Pulse-resistant type
RC : Composition2E : 1/4W G : ±2%NL : Low noise type
RS : Metal oxide film2H : 1/2W J : ±5%NB : Non-burning type
RW : Winding3A : 1WK : ±10% FR : Fuse-resistor
RN : Metal film3D : 2WM : ±20% F : Lead wire forming
RK : Metal mixture3F : 3W
] Resistance
1 8 2⇒1800 ohm = 1.8 kohm
s
s
• Units: ohm
1 R 2⇒1.2 ohm
s
s
• Units: ohm
ll
l
Capacitors
ll
Ex.: CE04W1H2R2MBP
Type ShapeDielectric Capacity Allowable Others
and per- strengtherror
3H : 5W
Indicates number of zeros after effective number.
2-digit effective number.
1-digit effective number.
2-digit effective number, decimal point indicated by R.
formance
CE : Aluminum foil0J : 6.3VF : ±1%HS : High stability type
electrolytic
CA : Aluminum solid1A : 10VG : ±2%BP : Non-polar type
electrolytic
CS : Tantalum electrolytic1C : 16VJ : ±5%HR : Ripple-resistant type
CQ : Film1E : 25VK : ±10%DL : For change and discharge
CK : Ceramic1V : 35VM : ±20%HF : For assuring high
CC : Ceramic1H : 50VZ : +80%U : UL part
CP : Oil2A : 100V–20%C : CSA part
CM : Mica2B : 125VP : +100%W : UL-CSA type
CF : Metallized2C : 160V–0%F : Lead wire forming
CH : Metallized2D : 200VC : ±0.25pF
2E : 250V D : ±0.5pF
2H : 500V= : Others
2J : 630V
Parts marked with this symbol have critical characteristics.
Use ONLY replacement parts recommended by the manufacturer.
2. CAUTION:
Before returning the unit to the customer, make sure you
make either (1) a leakage current check or (2) a line to
chassis resistance check. If the leakage current exceeds
0.5 milliamps, or if the resistance from chassis to either
side of the power cord is less than 460 kohms, the unit is
defective.
3. WARNING:
DO NOT return the unit to the customer until the problem
is located and corrected.
4. NOTICE
ALL RESISTANCE VALUES IN OHM. k=1,000 OHM
M=1,000,000 OHM
ALL CAPACITANCE VALUES IN MICRO FARAD.
p=MICRO-MICRO FARAD
EACH VOLTAGE AND CURRENT ARE MEASURED AT
NO SIGNAL INPUT CONDITION.
CIRCUIT AND PARTS ARE SUBJECT TO CHANGE
WITHOUT PRIOR NOTICE.
配線図について
印の部品は安全を維持するために重要な部品です。
従って交換時は必ず指定の部品を使用してください。
注)
1. 指定なき抵抗値は Ω、k は kΩ、M は MΩ を示
す。
2. 指定なきコンデンサーの値は
す。
3. 各部の電圧は無信号の値を示す。
4. この配線図は基本配線図です。改良等のため変更
することがありますのでご了承ください。
SIGNAL LINE
F、pはpFを示
µ
SIGNAL LINE
67
Page 68
SCHEMATIC DIAGRAMS (1/14)
ADV-M71
1234567891011
68
A
B
C
D
E
F
SCHEMATIC DIAGRAMS (1/14)
1U-3527-3 DISPLAY UNIT
(For All model)
G
H
68
Page 69
SCHEMATIC DIAGRAMS (2/14)
ADV-M71
1234567891011
69
A
B
C
D
E
F
SCHEMATIC DIAGRAMS (2/14)
1U-3527-1 AUDIO UNIT (1/3)
DIR/DAC Secstion
(For All model)
G
H
69
Page 70
SCHEMATIC DIAGRAMS (3/14)
ADV-M71
1234567891011
70
A
B
C
D
E
F
SCHEMATIC DIAGRAMS (3/14)
1U-3527-1 AUDIO UNIT (2/3)
VOLUME Secstion
(For All model)
G
H
70
Page 71
SCHEMATIC DIAGRAMS (4/14)
ADV-M71
1234567891011
71
A
B
C
D
E
F
SCHEMATIC DIAGRAMS (4/14)
1U-3527-1 AUDIO UNIT (3/3)
µCOM Secstion
(For Japan model)
G
H
71
Page 72
SCHEMATIC DIAGRAMS (5/14)
ADV-M71
1234567891011
72
A
B
C
D
E
F
SCHEMATIC DIAGRAMS (5/14)
1U-3527-2 PIN JACK UNIT
(For All model)
G
H
72
Page 73
SCHEMATIC DIAGRAMS (6/14)
ADV-M71
1234567891011
73
A
B
C
D
E
F
SCHEMATIC DIAGRAMS (6/14)
1U-3528-2 POWER UNIT
(For Japan model)
G
H
73
Page 74
SCHEMATIC DIAGRAMS (7/14)
ADV-M71
1234567891011
74
A
B
C
D
E
F
SCHEMATIC DIAGRAMS (7/14)
1U-3528-1 AMP/VIDEO UNIT
1U-3528-3 POSISTOR UNIT
1U-3528-4 SP TERMINAL UNIT
1U-3528-5 D-TERMINAL UNIT
(For Japan model)
G
H
74
Page 75
SCHEMATIC DIAGRAMS (8/14)
ADV-M71
1234567891011
75
A
B
C
D
E
F
SCHEMATIC DIAGRAMS (8/14)
1U-3474 DSP UNIT
(For All model)
G
H
75
Page 76
SCHEMATIC DIAGRAMS (9/14)
ADV-M71
1234567891011
76
A
B
C
D
E
F
SCHEMATIC DIAGRAMS (9/14)
MECHANISM BORDE (1/6)
RL-S871(HD60) MPEG
(For All model)
G
H
76
Page 77
SCHEMATIC DIAGRAMS (10/14)
ADV-M71
1234567891011
77
ADV-M71 : OPEN
A
B
C
(2CH)
ADV-M71 : OPEN
D
E
F
SCHEMATIC DIAGRAMS (10/14)
MECHANISM BOARD (2/6)
RL-S871(HD60) AUDIO_DAC
(For All model)
G
H
77
Page 78
SCHEMATIC DIAGRAMS (11/14)
ADV-M71
1234567891011
78
A
B
C
D
E
F
SCHEMATIC DIAGRAMS (11/14)
MECHANISM BOARD (3/6)
RL-S871(HD60) DRIVE_IC
(For All model)
G
H
78
Page 79
SCHEMATIC DIAGRAMS (12/14)
ADV-M71
1234567891011
79
A
B
C
ADV-M71 : OPEN
D
E
F
SCHEMATIC DIAGRAMS (12/14)
MECHANISM BOARD (4/6)
RL-S871(HD60) DRAM_FE
(For All model)
G
H
79
Page 80
SCHEMATIC DIAGRAMS (13/14)
ADV-M71
1234567891011
80
A
B
C
D
E
F
SCHEMATIC DIAGRAMS (13/14)
MECHANISM BOARD (5/6)
RL-S871(HD60) RF_AMP
(For All model)
G
H
80
Page 81
SCHEMATIC DIAGRAMS (14/14)
ADV-M71
1234567891011
81
A
B
C
D
E
F
SCHEMATIC DIAGRAMS (14/14)
MECHANISM BOARD (6/6)
RL-S871(HD60) DVD_DSP
(For All model)
G
H
81
Page 82
SCHEMATIC DIAGRAMS (1/14)
ADV-M71
1234567891011
82
A
B
C
D
E
F
SCHEMATIC DIAGRAMS (1/14)
1U-3527-3 DISPLAY UNIT
(For All model)
G
H
82
Page 83
SCHEMATIC DIAGRAMS (2/14)
ADV-M71
1234567891011
83
A
B
C
D
E
F
SCHEMATIC DIAGRAMS (2/14)
1U-3527-1 AUDIO UNIT (1/3)
DIR/DAC Secstion
(For All model)
G
H
83
Page 84
SCHEMATIC DIAGRAMS (3/14)
ADV-M71
1234567891011
84
A
B
C
D
E
F
SCHEMATIC DIAGRAMS (3/14)
1U-3527-1 AUDIO UNIT (2/3)
VOLUME Secstion
(For All model)
G
H
84
Page 85
SCHEMATIC DIAGRAMS (4/14)
ADV-M71
1234567891011
85
A
B
C
D
E
F
SCHEMATIC DIAGRAMS (4/14)
1U-3527-1 AUDIO UNIT (3/3)
µCOM Secstion
(For U.S.A. & Canada model)
G
H
85
Page 86
SCHEMATIC DIAGRAMS (5/14)
ADV-M71
1234567891011
86
A
B
C
D
E
F
SCHEMATIC DIAGRAMS (5/14)
1U-3527-2 PIN JACK UNIT
(For All model)
G
H
86
Page 87
SCHEMATIC DIAGRAMS (6/14)
ADV-M71
1234567891011
87
A
B
C
D
E
F
SCHEMATIC DIAGRAMS (6/14)
1U-3528-2 POWER UNIT
(For U.S.A. & Canada model)
G
H
87
Page 88
SCHEMATIC DIAGRAMS (7/14)
ADV-M71
1234567891011
88
A
B
C
D
E
F
SCHEMATIC DIAGRAMS (7/14)
1U-3528-1 AMP/VIDEO UNIT
1U-3528-3 POSISTOR UNIT
1U-3528-4 SP TERMINAL UNIT
1U-3528-5 D-TERMINAL UNIT
(For U.S.A. & Canada model)
G
H
88
Page 89
SCHEMATIC DIAGRAMS (8/14)
ADV-M71
1234567891011
89
A
B
C
D
E
F
SCHEMATIC DIAGRAMS (8/14)
1U-3474 DSP UNIT
(For All model)
G
H
89
Page 90
SCHEMATIC DIAGRAMS (9/14)
ADV-M71
1234567891011
90
A
B
C
D
E
F
SCHEMATIC DIAGRAMS (9/14)
MECHANISM BORDE (1/6)
RL-S871(HD60) MPEG
(For All model)
G
H
90
Page 91
SCHEMATIC DIAGRAMS (10/14)
ADV-M71
1234567891011
91
ADV-M71 : OPEN
A
B
C
(2CH)
ADV-M71 : OPEN
D
E
F
SCHEMATIC DIAGRAMS (10/14)
MECHANISM BOARD (2/6)
RL-S871(HD60) AUDIO_DAC
(For All model)
G
H
91
Page 92
SCHEMATIC DIAGRAMS (11/14)
ADV-M71
1234567891011
92
A
B
C
D
E
F
SCHEMATIC DIAGRAMS (11/14)
MECHANISM BOARD (3/6)
RL-S871(HD60) DRIVE_IC
(For All model)
G
H
92
Page 93
SCHEMATIC DIAGRAMS (12/14)
ADV-M71
1234567891011
93
A
B
C
ADV-M71 : OPEN
D
E
F
SCHEMATIC DIAGRAMS (12/14)
MECHANISM BOARD (4/6)
RL-S871(HD60) DRAM_FE
(For All model)
G
H
93
Page 94
SCHEMATIC DIAGRAMS (13/14)
ADV-M71
1234567891011
94
A
B
C
D
E
F
SCHEMATIC DIAGRAMS (13/14)
MECHANISM BOARD (5/6)
RL-S871(HD60) RF_AMP
(For All model)
G
H
94
Page 95
SCHEMATIC DIAGRAMS (14/14)
ADV-M71
1234567891011
95
A
B
C
D
E
F
SCHEMATIC DIAGRAMS (14/14)
MECHANISM BOARD (6/6)
RL-S871(HD60) DVD_DSP
(For All model)
G
H
95
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