How it Works
Delta Tau
Loading...
UMAC-CPCI

Delta Tau UMAC-CPCI Hardware Reference Manual

Download
^1 HARDWARE REFERENCE MANUAL
^2 UMAC-CPCI
Turbo CPU Board
^3 Turbo CPU Board
^4 4Ax-603625-xUxx
Single Source Machine Control Power // Flexibility // Ease of Use
21314 Lassen Street Chatsworth, CA 91311 // Tel. (818) 998-2095 Fax. (818) 998-7807 // www.deltatau.com
Copyright Information
© 2003 Delta Tau Data Systems, Inc. All rights reserved. This document is furnished for the customers of Delta Tau Data Systems, Inc. Other uses are
unauthorized without written permission of Delta Tau Data Systems, Inc. Information contained in this manual may be updated from time-to-time due to product improvements, etc., and may not conform in every respect to former issues.
To report errors or inconsistencies, call or email:
Delta Tau Data Systems, Inc. Technical Support
Phone: (818) 717-5656 Fax: (818) 998-7807 Email: support@deltatau.com Website: http://www.deltatau.com
Operating Conditions
All Delta Tau Data Systems, Inc. motion controller products, accessories, and amplifiers contain static sensitive components that can be damaged by incorrect handling. When installing or handling Delta Tau Data Systems, Inc. products, avoid contact with highly insulated materials. Only qualified personnel should be allowed to handle this equipment.
In the case of industrial applications, we expect our products to be protected from hazardous or conductive materials and/or environments that could cause harm to the controller by damaging components or causing electrical shorts. When our products are used in an industrial environment, install them into an industrial electrical cabinet or industrial PC to protect them from excessive or corrosive moisture, abnormal ambient temperatures, and conductive materials. If Delta Tau Data Systems, Inc. products are exposed to hazardous or conductive materials and/or environments, we cannot guarantee their operation.
UMAC-CPCI Turbo CPU Board Hardware Reference Manual
Table of Contents
INTRODUCTION.......................................................................................................................................................1
Associated Manuals...................................................................................................................................................2
BOARD CONFIGURATION.....................................................................................................................................3
Option 1: Communications Interfaces.......................................................................................................................3
Option 2: Dual-Ported RAM.....................................................................................................................................3
Option 5: CPU and Memory Configurations.............................................................................................................3
Option 8: High-Accuracy Clock Crystal...................................................................................................................4
Option 9: Serial Port Configuration ..........................................................................................................................4
Option 10: Firmware Revision Specification............................................................................................................4
Option 16: Battery-Backed Parameter Memory........................................................................................................4
HARDWARE SETUP.................................................................................................................................................5
Clock-Source Jumpers...............................................................................................................................................5
Watchdog Timer Jumper...........................................................................................................................................5
Operation Mode Jumpers..........................................................................................................................................5
Firmware Reload Jumper..........................................................................................................................................5
Re-Initialization Jumper............................................................................................................................................5
Serial-Port Level Select Jumpers...............................................................................................................................6
DPRAM IC Select Jumper........................................................................................................................................6
Flash IC Firmware Bank Select Jumpers..................................................................................................................6
Flash IC Power Supply Select Jumper......................................................................................................................6
Power-Supply Check Select Jumper .........................................................................................................................6
Reset-Lock Jumper....................................................................................................................................................6
CONNECTIONS.........................................................................................................................................................7
Compact UBUS Connector.......................................................................................................................................7
Rear Field Wiring Connector....................................................................................................................................7
Front-Panel RS-232 Connector.................................................................................................................................7
Stack Connectors to Bridge Board............................................................................................................................7
Factory-Use Connectors............................................................................................................................................8
BOARD LAYOUT.......................................................................................................................................................9
JUMPER DESCRIPTIONS......................................................................................................................................11
E0: Reset-Lock Enable (Factory Use Only)............................................................................................................11
E1A: Servo and Phase Clock Direction Control......................................................................................................11
E1B: Servo/Phase Clock Source Control................................................................................................................11
E2: (Reserved for Future Use).................................................................................................................................11
E3: Re-Initialization on Reset Control....................................................................................................................12
E4: (Reserved for Future Use).................................................................................................................................12
E5: USB/Ethernet Communication Jumper.............................................................................................................12
E11: Power Supply Check Control..........................................................................................................................12
E17 – E18: Serial Port Select..................................................................................................................................12
E18A, B, C, D: Ethernet Communication Control..................................................................................................13
E19: Watchdog Disable Jumper..............................................................................................................................13
E20 – E22: Power-Up/Reset Load Source ..............................................................................................................13
E23: Firmware Reload Enable.................................................................................................................................13
E25A, B, C: Flash Memory Firmware Bank Select................................................................................................13
W1: Flash IC Power Supply Select Jumper.............................................................................................................14
CONNECTOR SUMMARY.....................................................................................................................................15
CONNECTOR PINOUTS.........................................................................................................................................17
Compact UBUS Connector (J1) Pin-Out.................................................................................................................17
UMAC-CPCI Turbo CPU Board Hardware Reference Manual
UMAC-CPCI Turbo CPU Board J2 Connector ......................................................................................................18
J4: RS-232 Serial Port Connector...........................................................................................................................19
ACCESSORIES.........................................................................................................................................................21
ACC-Cx Compact UBUS Backplane Boards..........................................................................................................21
ACC-8CR Test Breakout Board..............................................................................................................................21
ACC-11C Sinking I/O Board..................................................................................................................................21
ACC-24C2 PWM Axis Board.................................................................................................................................22
ACC-24C2A Analog Axis Board............................................................................................................................ 22
ACC-51C Analog Encoder Interpolator Board.......................................................................................................22
SCHEMATICS..........................................................................................................................................................23
Table of Contents
ii
UMAC-CPCI Turbo CPU Board Hardware Reference Manual
INTRODUCTION
Delta Tau’s UMAC-CPCI systems provide a compact and clean integration of motion and I/O control for sophisticated automation equipment. The system consists of a modular set of 3U-size (100mm x 160mm) boards in the “Compact PCI” format, implementing Turbo PMAC software and hardware functions, communicating with each other over a common backplane (the “Compact UBUS”). All field wiring is available on rear connectors, suitable for a user-designed distribution system to the machine. UMAC (Universal Motion and Automation Controller) -CPCI systems provide integrated connectivity as well as ease of assembly, diagnostics, and repair. UMAC-CPCI systems differ from “standard” UMAC systems in that all field wiring comes to the back of the rack, behind the backplane, instead of direct top and bottom access.
The UMAC-CPCI Turbo CPU board (Part number 3A0-603625-10x) implements a Turbo PMAC2 CPU in the 3U CPCI form factor. Its software operation is completely identical to other Turbo PMAC2 controllers.
Note that a Compact PCI interface does not automatically come with a UMAC-CPCI system, nor is one necessary to communicate to the system, given the other possible communications ports: RS-232, RS­422, USB, and Ethernet.
This picture shows the UMAC-CPCI Turbo CPU board. The connectors on the right side plug into the “Compact UBUS” backplane board, with the bottom right connector being the bus connector, and the top right connector containing the external “field wiring” signals, which typically pass through the backplane board. The connector at lower left is an RS-232 port intended for setup and diagnostics; the stack connectors top and bottom provide the link to a CPCI “bridge board”.
This picture shows a sample configuration of a UMAC-CPCI system, not installed in its rack. It consists of the following components:
1. Rack power supply (not a Delta Tau product)
2. UMAC-CPCI CPU board
3. ACC-11C Sinking I/O board
4. ACC-24C2A analog axis interface board
5. ACC-C8 8-slot Compact UBUS backplane. Note the “pass-through” connector on the back for field-wiring distribution. In this picture, alternate slots in the backplane have been left open to make each board more visible. This does not have to be done in actual use.
Introduction 1
UMAC-CPCI Turbo CPU Board Hardware Reference Manual
Associated Manuals
This document is the Hardware Reference Manual for the UMAC-CPCI Turbo CPU board for an UMAC­CPCI system. It describes the hardware features and provides setup instructions.
You will need other manuals as well to use your UMAC-CPCI system. Each accessory to the UMAC­CPCI Turbo CPU board has its own manual, describing its operation and any required software setup of the Turbo CPU.
You will also need the Software Reference Manual for the Turbo PMAC family, and the User Guide for the PMAC or Turbo PMAC families.
2 Introduction
UMAC-CPCI Turbo CPU Board Hardware Reference Manual
BOARD CONFIGURATION
The base version of the UMAC-CPCI Turbo CPU board provides a 1-slot 3U-format Eurocard board with:
• 80 MHz DSP56303 CPU (120 MHz PMAC equivalent)
• 128k x 24 SRAM compiled/assembled program memory (Opt. 5C0)
• 128k x 24 SRAM user data memory (Opt. 5C0)
• 1M x 8 flash memory for user backup & firmware (Opt. 5C0)
• Latest released firmware version
• RS-232/422 serial interface, available both on front-panel DB-9 connector and on backside field-
wiring connector
• Backplane Compact UBUS expansion connector for communication to servo and I/O accessory
boards
• Backside field-wiring connector
Option 1: Communications Interfaces
The UMAC-CPCI Turbo CPU board comes standard only with an RS-232/422 serial interface. The Option 1 family provides faster interfaces for high-speed communications – Universal Serial Bus (USB), Ethernet, or the link to the CPCI bus through a “bridge” daughter board.
• Option 1: On-board 10-Base-T TCP/IP Ethernet interface. The key added components are U67 and
U32.
• Option 1A: On-board 12 Mbit/sec USB interface. The key added component is U67.
• Option 1B: Solder-side stack connectors to CPCI-bridge daughter board. This option should only be
ordered when the bridge board is to be installed on the left side of the CPU board, so the CPU board is in the leftmost slot of the Compact UBUS backplane, and the bridge board is in the rightmost slot of the Compact PCI bus backplane.
Option 2: Dual-Ported RAM
With either the Option 1 Ethernet interface, or the Option 1A USB interface, communications throughput can be increased through the use of dual-ported RAM, which provides a bank of memory that can be directly accessed by both the UMAC-CPCI Turbo CPU and the communications microcontroller.
• Option 2: 32k x 16 bank of on-board dual-ported RAM (requires Option 1 or 1A) in component U56.
Option 5: CPU and Memory Configurations
The various versions of Option 5 provide different CPU speeds and main memory sizes on the piggyback CPU board. Only one Option 5xx may be selected for the board.
The CPU is a DSP563xx IC as component U1. It is currently available only as an 80 MHz or 100 MHz device (with computational power equivalent to a 120 MHz or 150 MHz non-Turbo PMAC, respectively), but higher speed versions may become available.
The compiled/assembled-program (“P”) memory SRAM ICs are located in U14, U15, and U16. These ICs form the active memory for the firmware, compiled PLCs, and user-written phase/servo algorithms. These can be 128k x 8 ICs (for a 128k x 24 bank), fitting in the smaller footprint, or they can be the larger 512k x 8 ICs (for a 512k x 24 bank), fitting in the full footprint.
The user-data memory (“X/Y”) SRAM ICs are located in U11, U12, and U13. These ICs form the active memory for user motion programs, uncompiled PLC programs, and user tables and buffers. These can be 128k x 8 ICs (for a 128k x 24 bank), fitting in the smaller footprint, or they can be the larger 512k x 8 ICs (for a 512k x 24 bank), fitting in the full footprint.
Board Configuration 3
UMAC-CPCI Turbo CPU Board Hardware Reference Manual
The flash memory IC is located in U10. This IC forms the non-volatile memory for the board’s firmware, the user setup variables, and for user programs, tables, and buffers. It can be 1M x 8, 2M x 8, or 4M x 8 in capacity.
• Option 5C0 is the standard CPU and memory configuration. It is provided automatically if no Option
5xx is specified. It provides an 80 MHz DSP56303 CPU (120 MHz PMAC equivalent) with 8k x 24 of internal memory, an external 128k x 24 of compiled/assembled program memory, an external 128k x 24 of user data memory; and a 1M x 8 flash memory. Setup variable I52 should be set and saved at 7 for 80 MHz operation.
• Option 5C3 provides an 80 MHz DSP56303 CPU (120 MHz PMAC equivalent) with 8k x 24 of
internal memory, an expanded external 512k x 24 of compiled/assembled program memory, an expanded external 512k x 24 of user data memory, and a 4M x 8 flash memory. Setup variable I52 should be set and saved at 7 for 80 MHz operation.
• Option 5D0 provides a 100 MHz DSP56309 CPU (150 MHz PMAC equivalent) with 34k x 24 of
internal memory, an external 128k x24 of compiled/assembled program memory, an external 128k x 24 of user data memory; and a 1M x 8 flash memory. Setup variable I52 should be set and saved at 9 for 100 MHz operation.
• Option 5D3 provides a 100 MHz DSP56309 CPU (150 MHz PMAC equivalent) with 34k x 24 of
internal memory, an expanded external 512k x 24 of compiled/assembled program memory, an expanded external 512k x 24 of user data memory, and a 4M x 8 flash memory. Setup variable I52 should be set and saved at 9 for 100 MHz operation.
Option 8: High-Accuracy Clock Crystal
The UMAC-CPCI Turbo CPU board has a clock crystal (component Y1) of nominal frequency 19.6608 MHz (~20 MHz). The standard crystal’s accuracy specification is +/-100 ppm.
• Option 8A provides a nominal 19.6608 MHz crystal with a +/-15 ppm accuracy specification.
Option 9: Serial Port Configuration
The UMAC-CPCI Turbo CPU board comes standard with a single RS-232/422 serial port, a second serial port can be added.
• Option 9T adds an auxiliary RS-232 port on the CPU board. The key components added are ICs U28
and U43.
Option 10: Firmware Revision Specification
Normally the UMAC-CPCI Turbo CPU board is provided with the newest released firmware revision. Some users may wish to “freeze” their designs on an older revision. A label on the U10 flash memory IC shows the firmware revision loaded at the factory. The VERSION command can be used to report what firmware revision is currently installed.
• Option 10 provides for a user-specified firmware version.
Option 16: Battery-Backed Parameter Memory
The contents of the standard memory are not retained through a power-down or reset unless they have been saved to flash memory first. Option 16 provides supplemental battery-backed RAM for real-time parameter storage that is ideal for holding machine state parameters in case of an unexpected power­down.
• Option 16A provides a 32k x 24 bank of battery-backed parameter RAM in components U17, U18,
and U19 and a “can-stack” lithium battery in component BT1. While the average expected battery life is over five years, a yearly replacement schedule is recommended. Replacement batteries can be ordered from Delta Tau as Acc-1LS (Part # 100-0QTC85-000).
4 Board Configuration
UMAC-CPCI Turbo CPU Board Hardware Reference Manual
HARDWARE SETUP
Clock-Source Jumpers
In order to operate properly, the Turbo CPU board must receive servo and phase clock signals from a source external to the board. These clock signals can be brought into the board from one of three possible ports: the stack connector, the UBUS backplane connector, or the front-side main serial-port connector. Jumpers E1A and E1B must be configured properly for the clock source used.
(Note: If the UMAC-CPCI Turbo CPU board cannot find the clock signal from the source specified by these jumpers, it will generate its own 2.26kHz servo clock and its own 9.04kHz phase clock so it will stay in operation.)
To receive the clock signals over the Compact-UBUS backplane, usually from an ACC-24C2x axis­interface board, E1A must connect pins 1 and 2, and E1B must connect pins 2 and 3. This configuration is typical for an UMAC-CPCI system. The clock signals are output on the main serial port.
To receive the clock signals through the stack connectors, usually from the MACRO IC on the CPCI “bridge” board, E1A must connect pins 1 and 2, and the E1B jumper must be removed. The clock signals are output on the main serial port.
To receive the clock signals through the main serial port, usually from another UMAC system or a reference signal generator, E1A must connect pins 2 and 3, and E1B must connect pins 1 and 2. This configuration is rarely used, but permits complete synchronization to the system that is generating the clock signals.
Watchdog Timer Jumper
Jumper E19 should be OFF for normal operation, leaving the watchdog timer circuit active and prepared to shut down the card in case of a severe problem. Putting jumper E19 ON disables the watchdog timer circuit. This should only be used for test purposes, in trying to track down the source of watchdog timer trips. Normal operation of a system with this jumper ON should never be attempted, as an important safety feature is disabled.
Operation Mode Jumpers
Jumpers E20, E21, and E22 control the operational mode of the UMAC-CPCI Turbo CPU. For normal operation, E20 must be OFF, E21 must be ON, and E22 must be ON. Other settings of these jumpers are for factory use only.
Firmware Reload Jumper
Jumper E23 should be OFF for normal operation. If you want to load new firmware into the flash­memory IC on the CPU, E23 should be ON when the card is powered up. This puts the card in “bootstrap mode”, ready to accept new firmware. If you then try to establish communications to the card with the Executive program, either over the main serial port or the optional USB or Ethernet ports, the Executive program will automatically recognize that the card is in bootstrap mode, and prompt you for the firmware file to download.
Re-Initialization Jumper
Jumper E3 should be OFF for normal operation, where the last saved I-variable values are loaded from flash memory into active memory at power-up/reset. If E3 is ON during power-up/reset, the factory default I-variable values are instead loaded into active memory at power-up/reset. The last saved values are not lost when this happens. This jumper is typically only used when the system’s set up has a problem severe enough that communications does not work – otherwise, a $$$*** command can be used for re-initialization.
Board Configuration 5
UMAC-CPCI Turbo CPU Board Hardware Reference Manual
Serial-Port Level Select Jumpers
The standard serial port can be used for either RS-232 or RS-422 serial communications. To use RS-232, jumpers E17 and E18 should connect pins 1 and 2; to use RS-422, jumpers E17 and E18 should connect pins 2 and 3. The front-panel DB-9 serial connector provides only the RS-232 signals, so in order to use this connector, E17 and E18 must both connect pins 1 and 2.
DPRAM IC Select Jumper
The UMAC-CPCI Turbo CPU board can provide dual-ported RAM (DPRAM) communications using either the on-board Option 2B DPRAM IC through the USB or Ethernet port, or using the DPRAM IC on the CPCI bridge daughter board through that board’s CPCI port. Jumper E24 must connect pins 1 and 2 to use the on-board Option 2B DPRAM; it must connect pins 2 and 3 to use the CPCI bridge board DPRAM.
Flash IC Firmware Bank Select Jumpers
Some makes of the U10 flash memory IC on the UMAC-CPCI Turbo CPU board can store multiple versions of the operating firmware inside. Jumpers E25A, E25B, and E25C select which bank is loaded into active memory on a normal power-up/reset, and which bank will be written to if the board is powered up or reset with the E23 jumper on.
The eight possible settings of these three jumpers provide eight banks for the firmware. A standard production version of the UMAC-CPCI Turbo CPU board is shipped with firmware loaded only in the bank selected by having all three of these jumpers OFF.
Flash IC Power Supply Select Jumper
Jumper W1 is set at the factory for the voltage level of the flash IC installed in U10. It connects pins 1 and 2 for a 3.3V flash IC; it connects pins 2 and 3 for a 5V flash IC. Even if this is a removable, not soldered, jumper, it should not be changed by the user.
Power-Supply Check Select Jumper
The UMAC-CPCI Turbo CPU board has a circuit to evaluate the voltage levels received through the J1 Compact UBUS backplane connector. This circuit can then notify other boards in the system (without software intervention) of a bad supply, so the outputs of those boards are automatically shut down. Jumper E11 should be OFF if only the 5V supply is checked for this purpose; it should be ON if the +12V and –12V backplane supplies are to be checked for this purpose. Note that many users will provide a separate isolated +/-12V supply into the analog axis boards, and each analog axis board has its own power-supply check circuit.
Reset-Lock Jumper
Putting jumper E0 ON locks the UMAC-CPCI Turbo CPU board in the reset state. This setting permits the loading of logic into the programmable ICs on the board and is for factory use only. This jumper should be OFF for all normal operation.
6 Hardware Setup
UMAC-CPCI Turbo CPU Board Hardware Reference Manual
CONNECTIONS
In a typical installation, the UMAC-CPCI Turbo CPU board is simply slid into a slot of a 3U-Eurocard rack until it inserts into the mating connectors on the backplane board already installed in the rack. In actual operation, all signals to the board come into the CPU board through the backplane. (The front­panel RS-232 connector is intended for test and debugging purposes.)
Compact UBUS Connector
The J1 “Compact UBUS” connector at the bottom of the back edge of the board provides the means for the UMAC-CPCI Turbo CPU board to communicate with axis and I/O boards through a common backplane board, such as a Delta Tau ACC-Cx board, or a user-designed backplane board. It also provides the 3.3V and 5V power supply lines to the CPU board.
Because of the design of the Compact UBUS, the CPU board can operate in any slot of the bus. However, if the CPU board has the CPCI bridge board installed on it, the CPU board must be installed in the end slot of the Compact UBUS backplane immediately adjacent to the Compact PCI bus backplane board, so the bridge board can be installed in the adjacent CPCI end slot.
Rear Field Wiring Connector
The J2 field-wiring connector at the top of the back edge of the board provides the path for all of the signals between the CPU board and the outside system. In a typical configuration, this connector is mated with a “pass-through” connector on the Compact UBUS backplane board, and a system-specific distribution system is installed behind the backplane.
The J2 connector contains the signals for the main serial port (either RS-232 or RS-422 levels), the optional auxiliary RS-232 serial port, the optional USB port, and the optional Ethernet port. It also provides the outputs of the relay for the CPU board’s watchdog timer.
Front-Panel RS-232 Connector
The J4 DB-9S connector on the front panel is a standard RS-232 connector for the main serial port into the CPU, permitting a straight-across cable to a matching cable on a host computer. Jumpers E17 and E18 must each connect pins 1 and 2 to permit use of this connector. These same signals are available on the rear J2 connector; this front connector is intended for setup and diagnostic use more than use in the actual application.
Stack Connectors to Bridge Board
Stacking socket connectors J11 and J12 on the top and bottom edges, respectively, of the component side of the CPU board provide connection to the optional CPCI bridge board that can form a two-board “stack” with the CPU board. (Mating prong connectors on the solder side of the bridge board must be ordered.) In this configuration, the UMAC-CPCI Turbo CPU board can be installed in the rightmost slot of a Compact UBUS backplane, and the bridge board can be installed in the leftmost slot of a CPCI backplane.
If Option 2C is ordered, stacking “prong” connectors J11A and J12A are provided at the same locations on the solder side of the board. These provide connection to mating socket connectors on the component side of the bridge board. In this configuration, the UMAC-CPCI Turbo CPU board can be installed in the leftmost slot of a Compact UBUS backplane, and the bridge board can be installed in the rightmost slot of a CPCI backplane.
Connections 7
UMAC-CPCI Turbo CPU Board Hardware Reference Manual
Factory-Use Connectors
There are several connectors on the interior of the board for factory setup and diagnostic use. These are not for customer use.
8
Connections
UMAC-CPCI Turbo CPU Board Hardware Reference Manual
BOARD LAYOUT
This diagram of the UMAC-CPCI Turbo CPU board shows the locations of the jumpers and connectors. Detailed information about each of the jumpers and connectors follows.
UMAC-CPCI Turbo CPU Board Layout
Board Layout 9
UMAC-CPCI Turbo CPU Board Hardware Reference Manual
10 Board Layout
UMAC-CPCI Turbo CPU Board Hardware Reference Manual
JUMPER DESCRIPTIONS
Note:
Pin 1 of an E-point is masked by an X and a bold square in white ink on the composite side, and by a square solder pad on the solder side.
E0: Reset-Lock Enable (Factory Use Only)
E Point &
Location Description Default
Physical Layout
Jump pins 1 and 2 to lock the UMAC-CPCI Turbo CPU board in the “reset” state to permit installation of on-board logic. This setting for factory use only.
Remove jumper to permit normal operation of board.
E1A: Servo and Phase Clock Direction Control
E Point &
Physical Layout
Location Description Default
Jump pins 1 and 2 or remove jumper for the UMAC-CPCI system to use its internally generated servo and phase clock signals and to output these signals on the field wiring connector on the CPU board. E1B should connect pins 2 and 3 or be removed.
Jump pins 2 and 3 for the UMAC-CPCI system to expect to receive its servo and phase clock signals on J2 field-wiring connector on the Turbo CPU board. E1B should also connect pins 1 and 2.
E1B: Servo/Phase Clock Source Control
E Point &
Physical Layout
Location Description Default
Jump pin 1 to 2 to get phase and servo clocks from J7 RS422 connector (from an external source such as another UMAC).
Jump pin 2 to 3 to get phase and servo clocks from J1 backplane connector (from an ACC-24C2x, or equivalent board).
Remove jumper to get phase and servo clocks from J2 Stack connector (from an ACC-2E or equivalent board)
No jumper installed
Pins 1-2 jumpered
Pins 2 – 3 jumpered
E2: (Reserved for Future Use)
E Point &
Physical Layout
Jumper Descriptions 11
Location Description Default
No jumper
installed
UMAC-CPCI Turbo CPU Board Hardware Reference Manual
E3: Re-Initialization on Reset Control
E Point &
Location Description Default
Physical Layout
Remove jumper for normal reset mode (default). Jump pins 1 to 2 for re-initialization on reset.
E4: (Reserved for Future Use)
E Point &
Physical Layout
Location Description Default
No jumper
E5: USB/Ethernet Communication Jumper
E Point &
Physical Layout
Location Description Default
Jump 1-2 for Ethernet or USB communications from J7 (Ethernet connector) or J3 (USB connector).
Jump 2-3 for Ethernet or USB communications through the back J2 connector
No jumper installed
installed
Factory installed
E11: Power Supply Check Control
E Point &
Physical Layout
E11:
Location Description Default
Jump E11 pin 1 to 2 to include the +12V and –12V analog supplies from the J1 backplane connector in the power-supply check circuit, inhibiting outputs if these supplies fail.
Remove E11 jumper so only 5V digital supply is used in power­supply check circuit.
E17 – E18: Serial Port Select
E Point &
Physical Layout
E17:
E18:
Location Description Default
Jump E17 pin 1 to 2 to select RS-232 serial data input for main serial port (J4 front-panel or J2 backside connector).
Jump E17 pin 2 to 3 to select RS-422 serial data input for main serial port (J4 front-panel or J2 backside connector). Jump E18 pin 1 to 2 to select RS-232 serial handshake input for main serial port (J2 backside connector only).
Jump E18 pin 2 to 3 to select RS-422 serial handshake input f for main serial port (J2 backside connector only).
No jumper installed
Pins 1-2 jumpered
Pins 1-2 jumpered
12 Jumper Descriptions
UMAC-CPCI Turbo CPU Board Hardware Reference Manual
E18A, B, C, D: Ethernet Communication Control
E Point & Physical
Location Description Default
Layout
E18D1 E18C1 E18B1
Jump 1 to 2 to Ethernet Connection to J7 front connector Jump 2-3 for Ethernet connection through back J2 connector
E19: Watchdog Disable Jumper
E Point & Physical
Layout
Location Description Default
Jump pin 1 to 2 to disable Watchdog timer (for test purposes only.).
Remove jumper to enable Watchdog timer.
E20 – E22: Power-Up/Reset Load Source
E Point &
Physical Layout
E20:
Location Description Default
To load active memory from flash IC on power-up/reset, Remove jumper E20;
Jump E21 pin 1 to 2; Jump E22 pin 1 to 2.
Other combinations are for factory use only; the board will not operate in any other configuration.
Pins 1-2 jumpered
No jumper installed
No E20 jumper installed
E21 and E22 jump pin 1 to 2
E23: Firmware Reload Enable
E Point &
Physical Layout
Location Description Default
Jump pin 1 to 2 to reload firmware through serial or host bus port. Remove jumper for normal operations.
E25A, B, C: Flash Memory Firmware Bank Select
E Point &
Physical Layout
Location Description Default
Remove all jumpers to select standard factory-installed bank of operational firmware.
Install one or more jumper(s) to select alternate bank of operation firmware to install (E23 ON) or use (E23 OFF).
No jumper installed
No jumpers installed
Jumper Descriptions 13
UMAC-CPCI Turbo CPU Board Hardware Reference Manual
W1: Flash IC Power Supply Select Jumper
E Point &
Physical Layout
Location Description Default
B-1
(Note: This jumper is set at the factory and possibly hard soldered. Users should not change this jumper.)
Jump pin 1 to 2 to select 3.3V supply for flash memory IC in U10. Jump pin 2 to 3 to select 5V supply for flash memory IC in U10.
Setting dependent on flash IC used.
14 Jumper Descriptions
UMAC-CPCI Turbo CPU Board Hardware Reference Manual
CONNECTOR SUMMARY
J1: * J2: * J4: * J5: J6: J10: J11: J11A: J12: J12A: * Pinouts shown in next section. Connectors not flagged with an asterisk are for internal use or factory setup.
Compact UBUS Backplane Connector “Thru-Backplane” Field Wiring Connector RS-232 Front-Panel Serial-Port Connector JTAG/OnCE (for factory use only): 10-pin IDC connector JISP (for factory use only): 8-pin SIP connector JISP_B (for factory use only) 8-pin SIP connector First component-side stack connector to CPCI bridge board First solder-side stack connector to CPCI bridge board First component-side stack connector to CPCI bridge board First solder-side stack connector to CPCI bridge board
Connector Summary 15
UMAC-CPCI Turbo CPU Board Hardware Reference Manual
16 Connector Summary
UMAC-CPCI Turbo CPU Board Hardware Reference Manual
CONNECTOR PINOUTS
Compact UBUS Connector (J1) Pin-Out
Row Z A B C D E F
25 GND 5V 3.3V 5V GND 24 GND BD02 5V V(I/O) BD01 BD00 GND 23 GND 3.3V BD05 BD04 5V BD03 GND 22 GND BD09 BD08 3.3V BD07 BD06 GND 21 GND 3.3V BD13 BD12 BD11 BD10 GND 20 GND BD17 GND BD16 BD15 BD14 GND 19 GND 3.3V BD20 BD19 GND BD18 GND 18 GND BD23 GND 3.3V BD22 BD21 GND 17 GND 3.3V {BD26} {BD25} GND {BD24} GND 16 GND {BD30} GND {BD29} {BD28} {BD27} GND 15 GND 3.3V BWR- BRD- GND {BD31} GND 14 (KEY) (KEY) (KEY) (KEY) (KEY) (KEY) (KEY) 13 (KEY) (KEY) (KEY) (KEY) (KEY) (KEY) (KEY) 12 (KEY) (KEY) (KEY) (KEY) (KEY) (KEY) (KEY) 11 GND CS10- CS4- CS3- GND CS2- GND 10 GND CS16- GND 3.3V CS14- CS12- GND
9 GND IREQ2- IREQ1- MEMCS1- GND MEMCS0- GND 8 GND PHASE+ GND SERVO+ WAIT- IREQ3- GND 7 GND PHASE- WDO SERVO- GND GND 6 GND BA02 GND 3.3V BA01 BA00 GND 5 GND BA04 BA03 RESET- GND BX/Y GND 4 GND BA07 GND V(I/O) BA06 BA05 GND 3 GND BA11 BA10 BA09 5V BA08 GND 2 GND {BA15} 5V {BA14} BA13 BA12 GND 1 GND 5V -12V PWRGUD +12V 5V GND
Notes:
1. Row 25 is physically at the top of the connector in its “normal” orientation; Row 1 is at the bottom. Looking from the front of the rack, Column Z is on the left; Column F is on the right.
2. Supply (Vxx & xxV) and ground pins are in the same locations as the Compact PCI bus.
3. Spaces marked (KEY) are for the mechanical key; these are not pins.
4. Pins marked with {} brackets are reserved for future use; the signals inside the brackets are proposed for future expansion to a 32-bit data bus and 16-bit address bus.
Connector Pinouts 17
UMAC-CPCI Turbo CPU Board Hardware Reference Manual
UMAC-CPCI Turbo CPU Board J2 Connector
Row Z A B C D E F
22 GND +5V GND 21 GND RxD/ CTS +5V TxD/ RTS GND 20 GND RD- RD+ GND SD- SD+ GND 19 GND CS+ CS- GND RS+/ RS- GND 18 GND DSR DTR INIT/ GND 17 GND SERVO- SERVO+ PHASE- PHASE+ GND 16 GND GND 15 GND AuxRxD/ AuxCTS AuxTxD/ AuxRTS GND 14 GND AuxDSR AuxDTR GND 13 GND USBDP (D+) GND USBDM (D-) GND 12 GND GND 11 GND EthTxF+ EthTxF- EthRxF+ EthRxF- GND 10 GND GND
9 GND GND 8 GND GND 7 GND GND 6 GND GND 5 GND GND 4 GND GND 3 GND GND 2 GND WD_NO WD_CO
M
1 GND GND
Notes:
1. Row 25 is physically at the top of the connector in its “normal” orientation; Row 1 is at the bottom. Looking from the front of the rack, Column Z is on the left; Column F is on the right.
2. The RxD/, CTS, TxD/, and RTS lines are standard RS-232 signals. The inputs are only used if jumpers E17 and E18 each connect their pins 1 and 2. The DSR and DTR lines are simply shorted together.
3. The RD-, RD+, SD-, SD+, CS+, CS-, RS+, and RS- lines are standard RS-422 signals. The inputs are only used if jumpers E17 and E18 each connect their pins 2 and 3.
4. The SERVO-, SERVO+, PHASE- and PHASE+ clock lines are at RS-422 levels. These signals are outputs if jumper E1A connects its pins 1 and 2; they are inputs if jumper E1A connects pins 2 and 3.
5. The AuxRxD/, AuxCTS, AuxTxD/, and AuxRTS lines are standard RS-232 signals. These signals are provided only if the Option 9T auxiliary serial port is ordered. The AuxDSR and AuxDTR lines are simply shorted together.
6. The USBDP(D+) and USBDM(D-) signals are standard USB signals. They are only provided if the Option 1A USB interface is ordered.
7. The EthTxF+, EthTxF-, EthRxF+, and EthRxF- signals are standard Ethernet signals. They are only provided if the Option 1 Ethernet interface is ordered.
8. The WD_NO (normally open), WD_COM (common) and WD_NC (normally closed) lines are the outputs of the watchdog-timer hard-contact relay. The normally open contact is only conducting to common if the card is powered and operating correctly. The normally closed contact is only conducting to common if the card is not powered or the watchdog timer has tripped.
WD_NC GND
18 Connector Pinouts
UMAC-CPCI Turbo CPU Board Hardware Reference Manual
J4: RS-232 Serial Port Connector
(DB-9S Connector)
Pin # Symbol Function Description Notes
1 N.C. No connect 2 TXD- Output Send Data Low TRUE 3 RXD- Input Receive Data Low TRUE 4 DSR Bidirect Data Set Ready Shorted to DTR 5 GND Common UMAC CPCI Reference 6 DTR Bidirect Data Terminal Ready Shorted to DSR 7 CTS Input Clear to Send High TRUE 8 RTS Output Request to Send High TRUE
9 N.C. No connect Jumpers E17 and E18 should connect pins 1 and 2 to use this port for RS-232 communications; they should connect pins 2 and 3 to use this port for RS-422 communications.
Connector Pinouts 19
UMAC-CPCI Turbo CPU Board Hardware Reference Manual
20 Connector Pinouts
UMAC-CPCI Turbo CPU Board Hardware Reference Manual
ACCESSORIES
The UMAC-CPCI Turbo CPU board is always used with accessory boards. Delta Tau provides several accessory boards in the UMAC-CPCI family that can be used with the CPU board; other parties may produce accessory boards as well. Each accessory board has its own hardware reference manual.
ACC-Cx Compact UBUS Backplane Boards
The ACC-Cx family of Compact UBUS backplane boards provides the means for the CPU board to communicate with other accessory boards. The x in the name of the backplane board refers to the number of backplane data slots provided.
This picture shows an ACC-C8 8-slot backplane board. It has a P47-style power connector suitable for a standard 1-slot CPCI-format power supply.
ACC-8CR Test Breakout Board
The ACC-8CR board provides a behind-the-backplane breakout scheme for the J2 field wiring connector on any of the 3U-format UMAC-CPCI board. It is designed to plug into the rear of an ACC-Cx Compact UBUS backplane board, and it meets the Compact PCI physical specification (100mm x 80mm) for rear distribution boards. It has 110 screw-down terminal points, one for each signal on the J2 field wiring connector.
ACC-11C Sinking I/O Board
The ACC-11C board provides 32 isolated 12V-24V sinking inputs and 16 isolated sinking outputs up to 24V and 100mA per output. With its Option 1 mezzanine board, an additional 32 inputs and 16 outputs are provided, for a total of 96 I/O points in a single slot.
Schematics
UMAC-CPCI Turbo CPU Board Hardware Reference Manual
ACC-24C2 PWM Axis Board
The ACC-24C2 PWM axis board provides the interface circuitry for 4 axes of purely digital control in a single slot, with direct PWM outputs, serial ADC inputs, quadrature encoder inputs, and input/output flags. Because of pin limitations on the J2 field wiring connector, signals that are differential on other ACC-24x2 boards are single-ended here. To take these signals any significant distance, differential line drivers and receivers are required on a distribution board.
ACC-24C2A Analog Axis Board
The ACC-24C2A analog axis board provides the interface circuitry for 4 axes of control in a single slot, with analog interface to the servo drives. It also has one pulse-and-direction output per axis for stepper drives, or stepper-replacement servo drives. One 18-bit D/A converter comes standard for each axis; Option 1 provides a second D/A converter per axis, which can be used as part of a “sine-wave” control scheme, or for non-servo use. Option 2 provides eight 12-bit A/D converters.
ACC-51C Analog Encoder Interpolator Board
The ACC-51C provides the circuitry for the high-resolution interpolation of 2 or 4 analog sine/cosine encoders, yielding 4096 states per line of the encoder. The board comes standard with two channels of interface; Option 1 provides two additional channels.
22 Accessories
UMAC-CPCI Turbo CPU Board Hardware Reference Manual
Schematics 23
SCHEMATICS
BA09_A
BA03
BA11
MainCTS
TP7
SIRQ-
RP12A
1KSIP6I
1 2
+
$000000-$00FFFF Firmware (64K)
GUARD BAND
GND
GND
BA08
J4
DB9F
594837261
10
+3P3V
GND
GND
A14
BA05_A
CTS-
TXD
RP11D
3.3KSIP8I
7 8
C104
.1UF
D6
MMBD301LT1
1 3
MainTXD-
MainRXD-
R_SERVO-
IRQB-
PHASE-
422_RD+
OF DELTA TAU DATA SYSTEMS INC. ALL RIGHTS TO DESIGNS AND
PWR
SHEET2
625-0SH2
+3P3V
F1ER
PHA
SIRQ-
BSA01
IPOS
X/Y:$078000-$0780FF
+5V
422_CS+
MainCTS
AuxCTS
EXTAL
MainRxD-
MEMCS0-
CS4-
C94
22pf
C111
.1UF
E18
HREQ-
IRQB-
422_RS+
MainRxD-
A5
BA10
R_SERVO-
MODE
BWR-
GND
BA02
DPRCS0-
BA09
C93
22pf
CS14-
C95
.1UF
U4F
74ACT14
(SO14)
13 12
DATA SYSTEMS INC. AND IS LOANED SUBJECT TO RETURN UPON
ispEN-
603625-322A
-
UMAC-CPCI-CPU, DSP56309 CPU SECTI
O
Delta Tau Data Systems, Inc.
D
13Monday, January 14, 2002
Title
Size Document Number Rev
Date: Sheet
of
+3P3V
BA07_A
MODE
BSA00
U33D
74ACT14
(SO14)
9 8
C1
.1UF
GND
BA12
BRXD
BFUL
CS1-
BSA02
RP12B
1KSIP6I
3 4
R6
1K
C23
.1UF
MainDTR
BA07
BA12_A
MODD/IRQD-
WDO
E1A
2
3
1
C2
.1UF
DEMAND. TITLE TO THIS DOCUMENT IS NEVER SOLD OR
+5V
GND
RXD
422_RD-
+3P3V
A2
BA09_A
WR-
IOCS_A-
R_SERVO+
$050000-$0BFFFF Plcc Extended Memory Option (448K)
RTS-
RESET
U7
74LCX16245
(TSSOP48)
23568911
12
46444341403837
36
147
10
47
48
1314151617181920212223
2425
26272829303132333435394245
B0B1B2B3B4B5B6
B7
A1A2A3A4A5A6A7
A8
T/R1
GND
VCC
GND
A0
OE1
B8
B9
GND
B10
B11
VCC
B12
B13
GND
B14
B15
T/R2
OE2
A15
A14
GND
A13
A12
VCC
A11
A10
GNDA9GND
VCC
GND
JUMP 1 TO 2 TO DIS PHASE,SERVO,INIT ON `J2'
BA00
AuxRTS
U38C
74ACT08
(SO14)
9
10
8
+
C39
10UF
16V
(TANT)
DE-
CARD0
TXD
WAIT1-
CS14-
C88
.1UF
U3
DS1231S
(SOL16)
1234567
8
16151413121110
9
N.C.INN.C.
MODE
N.C.
TOL
N.C.
GND
N.C.
VCC
N.C.
NMI
N.C.
RST
N.C.
RST
C103
.1UF
X/Y:$078800-$0789FF
E1B 2 TO 1 ON = ENABLE `PHASE & SERVO' FROM `P2'
BA00
RESET-
WDO
BSA01
SRD0
IOCS-
PWRG
C35
.01UF
RP10C
3.3KSIP8I
5 6
U33C
74ACT14
(SO14)
5 6
U33F
74ACT14
(SO14)
13 12
J5
HEADER14_NO8
1234567
9
1011121314
C102
.1UF
C150
.1UF
ABOVE AGREEMENT.
GND
BA01
BA13_A
DE-
BPHA
BSC11
RP13
3.3KSIP10C
12
3 4 5 6 7 8 9 10
OF DELTA TAU DATA SYSTEMS INC. ALL RIGHTS TO DESIGNS AND
+3P3V
GND
422_CS-
C40
.1UF
U4D
74ACT14
(SO14)
9 8
TSO
+3P3V
CS16-
EROR
E1B
2
3
1
E17
2
3
1
E1A 2 TO 1 = ENABLE `CARD0'
BWR-
SERVO+
CS2-
RP3A
3.3K 2 1
C22
.1UF
X/Y:$068000-$06FFFF EXTENDED MEMORY OFF_BOARD (32K)
BA08
CS2-
CS4-
BA15
FLASHCS-
C32
.1UF
CARD0
TRST-
RP2C
RX
5 6
TO LOAD
A10
BA14_A
MainTxD-
C105
.1UF
D4
MMBD301LT1
1 3
TSI
R_SERVO+
+5V
BA11
AuxRxD-
BA06_A
CS10-
C100
.1UF
C25
.1UF
SCLK
+3P3V
BA11_A
WAIT1-
422_CS-
A11
C21
.01UF
RP20
3.3KSIP10C
12
3
4
5
6
7
8
9 10
THIS DOCUMENT IS THE CONFIDENTIAL PROPERTY OF DELTA TAU
JUMP 2 TO 3 TO ENA PHASE,SERVO,INIT ON `J2'
MEMCS1-
422_SD-
BA01
CS3-
BCTS-
R5
1K
C101
.1UF
X/Y:$074000-$077FFF
+5V
+5V
Vout
A6
RESET
J6
HSIP8NO5
1234678
E18
2
3
1
GND
+5V
IOCS_A-
BA11_A
ENA_P1-
WR-
+
C14
10UF
16V
(TANT)
RP2A
RX
12
U33B
74ACT14
(SO14)
3 4
SDO
X/Y:$078D00-$078DFF
+5V
EROR
CS02-
BRD-
A17 CS12-
Vbat
U4B
74ACT14
(SO14)
3 4
INVENTIONS ARE RESERVED BY DELTA TAU DATA SYSTEMS INC.
+5V
BA12_A
CS16-
VMECS0-
Vout
C87
.1UF
BA09
PRAMCS-
BPHA
GND
MainTxD-
BA05
BA05
422_SD-
ENA422
U28
MAX3232ECWE
(SOL16)
213
111210
9
16
645141378
15
+V
C1+
C1-
TXD
RXD
RTS
CTS
VCC
V-
C2+
C2-
TXD
RXD
RTS
CTS
VSS
GND
TA-
CTS-
MainRTS
+3P3V
+3P3V
CS3-
AuxCTS
19.6608Mhz
MainTxD-
RP10B
3.3KSIP8I
3 4
BRD-
CTS-
C106
.1UF
R15
15K
J5
X/Y:$078E00-$078EFF
BA04
422_SD+
BA13_A
RTS-
RXD
POSSESSION OF THIS DOCUMENT INDICATES ACCEPTANCE OF THE
E1B 2 TO 3 ON = ENABLE `PHASE & SERVO' FROM `P1'
NOTE:
RP11C
3.3KSIP8I
5 6
SOT23
Q5
2N7002
(SOT23)
3
12
TRST-
BA14_A
BA11
BA05_A
ENA_P1-
CS12-
A15
R14
15K
U8
74LCX16245
(TSSOP48)
23568911
12
46444341403837
36
147
10
47
48
1314151617181920212223
2425
26272829303132333435394245
B0B1B2B3B4B5B6
B7
A1A2A3A4A5A6A7
A8
T/R1
GND
VCC
GND
A0
OE1
B8
B9
GND
B10
B11
VCC
B12
B13
GND
B14
B15
T/R2
OE2
A15
A14
GND
A13
A12
VCC
A11
A10
GNDA9GND
VCC
GND
RP25
1KSIP10C
1 2 3 4 5 6 7 8 910
SOCKET REQ'D
BHA1
U4C
74ACT14
(SO14)
5 6
RP3D
3.3K 5 1
TRANSFERRED FOR ANY REASON. THIS DOCUMENT IS TO BE USED
RESET-
BX/Y
TDI
R7
100
E1B EMPTY = ENABLE `PHASE & SERVO' FROM `J12/J12A'
|625-0SH2.sch
A13
CTS-
NMI-
CPURST-
SERVO+
422_CS+
TCK
RP1A
3.3K 2 1
C96
.1UF
DEMAND. TITLE TO THIS DOCUMENT IS NEVER SOLD OR
E1A 2 TO 3 = DISABLE `CARD0'
RXD
422_RS+
RESET
C92
.1UF
(jisp)
X/Y:$078F00-$078FFF
+3P3V
RP15
33SIP8I
1 2
3 4
5 6
7 8
C151
.1UF
CS06-
AuxRxD-
MEMCS1-
HREQ-
RP12C
1KSIP6I
56
D1
LED
RED
N.C.
CS1-
ENA422
U34
PI74FCT245TL
(TSSOP20)
234567891
19
181716151413121120
10
A0A1A2A3A4A5A6A7T/R
OE
B0B1B2B3B4B5B6
B7
VCC
GND
MODE
BSCK1
R1
10
A15
BSER
RESET-
U2
MAX795SCSE
(SO8)
2 713
4 5
6
8
VCC RST
VOUTONGND CEI
CEO
BATT
BA06_A
A3
BSER
U30
MC3486D
(SO16)
1234567
8 9
10111213141516
IN-A
IN-A
OUT-A
EN-A,C
OUT-C
IN-C
IB-C
GND IN-D
IN-D
OUT-D
EN-B,D
OUT-B
IN-B
IN-B
VCC
INVENTIONS ARE RESERVED BY DELTA TAU DATA SYSTEMS INC.
GND
X/Y:$060000-$067FFF EXTENDED MEMORY ON_BOARD (32K)
GND
BA15
PRDY
SER
BBRAMCS-
RP3E
3.3K 6 1
GND
SERVO+
PHASE+
TDO
X/Y:$078A00-$078AFF
RP11A
3.3KSIP8I
1 2
U51
PI74FCT16245ATA
(TSSOP48)
23568911
12
46444341403837
36
147
10
47
48
1314151617181920212223
2425
26272829303132333435394245
B0B1B2B3B4B5B6
B7
A1A2A3A4A5A6A7
A8
T/R1
GND
VCC
GND
A0
OE1
B8
B9
GND
B10
B11
VCC
B12
B13
GND
B14
B15
T/R2
OE2
A15
A14
GND
A13
A12
VCC
A11
A10
GNDA9GND
VCC
GND
U27
74LCX245
(TSSOP20)
234567891
19
181716151413121120
10
A0A1A2A3A4A5A6A7T/R
OE
B0B1B2B3B4B5B6
B7
VCC
GND
JUMP 2 TO 3 TO ENABLE "RS422" TRANSCEIVER
+3P3V
C27
.1UF
C86
.1UF
C153
.1UF
`isp' PART
SERVO+
CS04-
+3P3V
BA05
BA07
BA08_A
422_RD+
RP4
3.3KSIP10C
12
3
4
5
6
7
8
9 10
X/Y:$078400-$0787FF
BA12
SERVO-
POSSESSION OF THIS DOCUMENT INDICATES ACCEPTANCE OF THE
GND
+3.3V
BA12
CS00-
BHREQ-
C26
.1UF
X/Y:$078100-$0781FF
BA10
PWRG
R_PHASE-
U43
MAX3100CEE
(QSOP)
1234567
8 9
10111213141516
DIN
DOUT
SCLK
CS
N.C.
IRQ
SHDN
GND X2
X1
CTS
N.C.
RTS
RX
TX
VCC
SDI
+3P3V GND
A8
BA09
ENA_P2-
PHA
GND
GND
BA02
BA15
SERVO-
SOT23
Q4
2N7002
(SOT23)
3
12
(JTAG/OnCE)
MainCTS
+5V
GND
SER
STD0
OSC_OUT
CS06-
PHA_A
PHASE
BT1
3.6V BAT
U9
NC7SZ00
(SOT23-5)
1
2
4
53
SHEET3
625-0SH3
+5V
BA14
RXD
D3
MMBD301LT1
1 3
E19
21
CS10-
PHASE-
SERVO-
INIT-
C17
.01FARAD
FM0H103Z
NEC
RESET
BA14
E0
21
C98
.1UF
X/Y:$078300-$0783FF
SCK0
BA06
BA10
MainRTS
ISPEN-
D2
LED
GRN
U33A
74ACT14
(SO14)
1 2
SERVO
RST-
PHASE-
PHASE+
BSC12
BFUL
RP11B
3.3KSIP8I
3 4
R10
1K
RP1D
3.3K 5 1
GND
GND
GND
BA03
IPOS
422_RS-
RESET-
WAIT2-
U31
MC75174BDW
(SOL20)
1234567
8 13
14151617181920
9
10
12
11
IN-A
OUT-A
N.C.
OUT-A
EN-A,C
OUT-C
N.C.
OUT-C N.C.
OUT-D
EN-B,D
OUT-B
N.C.
OUT-B
IN-B
VCC
IN-C
GND
OUT-D
IN-D
Q3
MMBT3906LT1
(SOT23)
1
23
GND
GND
GND
+5V
BA13
CS00-
A0
A4
RTS-
CS0-
TCK
D5
MMBD301LT1
1 3
U50
NC7SZ08M5
(SOT23-5)
1
2
4
53
ONLY PURSUANT TO WRITTEN LICENSE OR WRITTEN INSTRUCTIONS
N.C.
+3P3V
INIT-
BA04
A19X/YP
BA10_A
DRAMCS-
A16
WAIT1-
RESET_A
RP14
3.3KSIP10C
1 2
3
4
5
6
7
8
910
X/Y:$078C00-$078CFF
CS0-
MEMCS0-
$050000-$05FFFF Plcc Standard Memory Option (64K)
|625-0SH3.sch
RESET_A
422_RD-
SC02
WR-
BA07_A
422_RS-
BA15
R3
10K
J4
DRAMCS-
IOCS_B-
BA14
U4E
74ACT14
(SO14)
11 10
+3.3V
J6
BA06
BA10
BSRD1
U6B
TURBO-DECODE5
ispLSI2032E-135LT48
(TQFP48)
202122232622728333435
37
131415
16
25
44
47
18642
30
4541403846
7
29131
9
101119
8
4173
482412
36
39325
43
CS0
CS1
CS2
CS3
CS02
IOCS
CS04
CS06
CS10
CS12
CS14
CS16
A8A9A10
A11
CS00
CS4
IOCS_B
GND
VCC
GND
VCC
CPURST-
VMECS1
VMECS0
DPRCS0
IOCS_A
BSCAN
TCK
A14
RESET
FLASHCS
DRAMCS
PRAMCS
TDO/A17
TDI/A16RDA15WRVCCIO
VCCIO
GND
GND
DPRCS1
TMS
N.C.
N.C.
U4A
74ACT14
(SO14)
1 2
+
C34
1UF
35V
tant
+3P3V
422_SD+
R_PHASE-
A9
BA08
MainDSR
ISPEN-
MainRTS
CPURST-
C16
.1UF
$040000-$0403FF User Written Phase (1K)
+3P3V
BA06
BA14
JUMP `E0'
GND
A1
IOCS_B-
R_PHASE+
RP10D
3.3KSIP8I
7 8
Q1
MMBT3906LT1
(SOT23)
1
23
GUARD BAND
(JRS232)
MainRTS
BA09
BBRCS-
GND
BSTD1
U38A
74ACT08
(SO14)
1
2
3
E1B 2 TO 1 OFF = DISABLE `PHASE & SERVO' FROM `P2'
ENA_P2-
BA07
E17
PHASE
RD-
X/Y:$070000-$073FFF
Front Panel
PWRGUD
RXEN-
C24
.1UF
ONLY PURSUANT TO WRITTEN LICENSE OR WRITTEN INSTRUCTIONS
$040400-$040BFF User Written Servo (2K)
+3P3V
AuxTxD-
A7
BRD-
WDTC
R2
1K
C152
.1UF
X/Y:$078200-$0782FF
"Vbat" s/b 30mil trace
VMECS0-
BA11
A17
BA13
RESET
JUMP 1 TO 2 TO ENABLE "RS232" TRANSCEIVER
BA08
HACK-
C113
.1UF
PRAM MEMORY P:
+5V
CS04-
PRAMCS-
ENA422
PHASE+
BHA2
T/R-
DPRCS0-
TXD
RP1E
3.3K 6 1
+5V
BBRCS-
R_PHASE+
IRQB-
C15
.1UF
BWR-
PHASE+
SOT23
Q2
2N7002
(SOT23)
3
12
RT. angle through
WAIT2-
BSA00
CS02-
MainRxD-
PHASE-
BTXD
Y2
ECS-36-20-5P
3.6864Mhz
+5V
MainCTS
RESET-
C97
.1UF
C36
.1UF
A12
WAIT2-
SER_A
HACK-
DATA SYSTEMS INC. AND IS LOANED SUBJECT TO RETURN UPON
GND
PRDY
NMI-
BHACK-
SERVO-
U29
LTC1384CS
(SOL18)
324
121311
10
17
756151489
16
1 18
+V
C1+
C1-
TXD
RXD
RTS
CTS
VCC
V-
C2+
C2-
TXD
RXD
RTS
CTS
VSS
RXEN TXEN
TMS
N.C.
|Link
GND
+5V
AuxTxD-
BA13
ISPEN-
U33E
74ACT14
(SO14)
11 10
WD
GND
TMS
PWRGUD
F1ER
U38B
74ACT08
(SO14)
4
5
6
BA08_A
OSC_OUT
TRANSFERRED FOR ANY REASON. THIS DOCUMENT IS TO BE USED
N.C.
X/Y:$078B00-$078BFF
+3P3V
BHA0
BRTS-
RP10A
3.3KSIP8I
1 2
E1B 2 TO 3 OFF = DISABLE `PHASE & SERVO' FROM `P1'
BA10_A
BSA02
AuxRTS
R4
100K
CHGND
BX/Y
19.6608Mhz
FLASHCS-
SERVO
TRST-
C99
.1UF
THIS DOCUMENT IS THE CONFIDENTIAL PROPERTY OF DELTA TAU
ABOVE AGREEMENT.
UMAC-CPCI Turbo CPU Board Hardware Reference Manual
24 Schematics
IOCS_B-
D5
IREQ3-
DIRECTLY UNDER J12
n.c.
BA07
HPBD7
BA11_A
BA02_B
HPBD5
BD08_B
D8
BD19_A
U52
PI74FCT245TL
(TSSOP20)
234567891
19
181716151413121120
10
A0A1A2A3A4A5A6A7T/R
OE
B0B1B2B3B4B5B6
B7
VCC
GND
J1-2
CONN175-CPCI
B1B2B3B4B5B6B7B8B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B1B2B3B4B5B6B7B8B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
SERVO+
+5V
BD05_A
BD09_A
BD20_A
IREQ1-
BD00_B
D9
(KEY)
{BD24}
D6
BA05
BD11
BD16
CS06-
D14
BX/Y
BA02_A
BSA02
WAIT2-
BD05_A
BD15_A
BD11_A
CS04-
TRANSFERRED FOR ANY REASON. THIS DOCUMENT IS TO BE USED
GND
V(I/O
BA06_A
HPBD0
CS1-
BA04
IREQ3-
+5V
BD04_A
BA12_B
PWRGUD
{BA28}
+3P3V
CS10-
HPBD4
BD09_B
SCL
BD01_A
BD06_A
BD08_A
D3
DEMAND. TITLE TO THIS DOCUMENT IS NEVER SOLD OR
+3.3V
BD07_A
CS00-
BD20_B
D21
D22
CS12-
HPBD0
INIT-
BD16_A
HR/W
BA00_B
WAIT2-
CS16-
BA03_B
BD15_A
BD07
GND
BD08_A
BD12_A
BD08_A
BD22_A
BA06_A
SERVO_B+
BRD-
BD10_B
BD17_A
BD22_A
BA01_A
BA13_B
C49
.1UF
SOLDER SIDE
n.c.
PHASE_B-
BD12_B
C51
.1UF
{BD26}
GND
BX/Y_A
D11
D13
BD18_A
BA02
+3.3V
BD03
GND
HR/W
BD14_B
U25
ADM1485JR
(SO8)
123
4 5
678
RO
RE
DE
DI GND
A
B
VCC
RESET-
BD12
(KEY)
+5V
-12V
IOCS_A-
GND
BD04
BWR-
+5V
+5V
WDO
J1-4
CONN175-CPCI
D1D2D3D4D5D6D7D8D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D1D2D3D4D5D6D7D8D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
BD10
+3.3V
(KEY)
GND
BA12_A
BRD-
BD19_B
BA09
BSA02
R18 3.3K
OF DELTA TAU DATA SYSTEMS INC. ALL RIGHTS TO DESIGNS AND
+3P3V
SER
HDS-
BD04_B
BA01
BA03_B
BA06_B
C82
.1UF
R19 100
GND
GND
(KEY)
{BA15}
BA07_A
BA07_B
BD00_A
MEMCS0-
C48
.1UF
+12V
GND
-5V
CS3-
BD03_B
BD11_A
BA05_B
BD17
+5V
BD01_A
BA10_A
BRD_A-
D1
BD15_B
D16
{BD30}
GND
+5V
+3P3V
RESET_A
EQU_2-
WAIT2-
C74
.1UF
J1-3
CONN175-CPCI
C1C2C3C4C5C6C7C8C9
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
C25
C1C2C3C4C5C6C7C8C9
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
C25
U23
IDT74FCT164245TPA
(TSSOP48)
23568911
12
46444341403837
36
147
10
47
48
1314151617181920212223
2425
26272829303132333435394245
B0B1B2B3B4B5B6
B7
A1A2A3A4A5A6A7
A8
T/R1
GND
VCCB
GND
A0
OE1
B8
B9
GND
B10
B11
VCCB
B12
B13
GND
B14
B15
T/R2
OE2
A15
A14
GND
A13
A12
VCCA
A11
A10
GNDA9GND
VCCA
GND
+5V
+5V
CS1-
CS06-
BD07_A
MEMCS1-
HPBD2
BD12_A
MEMCS1-
BD04_B
BA11
C47
.1UF
GND
GND
VMECS0-
CS00-
SERVO_B-
(JEXP_B)
(KEY)
+3P3V
+12V
VMECS0-
BD08_B
BD21_B
BD03_B
n.c.
(KEY)
GND
ENA_P1-
HPBD2
BD05_A
D6
BX/Y_A
J1
GND
BD03_A
BD13_B
BA09_B
J1-5
CONN175-CPCI
E1E2E3E4E5E6E7E8E9
E10
E11
E12
E13
E14
E15
E16
E17
E18
E19
E20
E21
E22
E23
E24
E25
E1E2E3E4E5E6E7E8E9
E10
E11
E12
E13
E14
E15
E16
E17
E18
E19
E20
E21
E22
E23
E24
E25
BD09
N.C.
BD02
+5V
BSA00
IREQ2-
PHASE
D16
BA04
R9 100
BD18_A
CPCIDPR-
BD02_B
ABOVE AGREEMENT.
+5V
GND
BD04_A
BD00_A
SDA
J11
HEADER 20X2(FEM)
CLS120LDDV
12345678910
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
+5V
+5V
GND
+3P3V
BD10_A
BD18_A
CS02-
BA02_A
HPBD0
BWR_A-
D21
DIRECTLY UNDER J11
BA13
BRD-
JEXP
Modified
BD09_B
BD13_B
n.c.
+3P3V
BD10_A
D13
BD18_B
n.c.
CS12-
BA00_A
BA11_B
BA00_A
BA10_A
BA07
C83
.1UF
n.c.
N.C.
BD15_A
BA00_A
BA13_A
BD10_A
BD15_B
WAIT-
GND
HPBD5
BA07_A
IOCS_A-
INIT-
BD03_A
D7
BD23_A
SOLDER SIDE
CS04-
BA01_A
BA05_A
HPBD1
BD21_A
BD19_A
V_I/O
WDO
BSA01
SSM-120-L-DV-LC
GND
GND
GND
GND
BA09_A
EQU_1-
BD06_B
D23
J11A
HEADER 20X2(MALE)
HW2015GD450SM
12345678910
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
n.c.
SERVO
BA00_B
GND
GND
BD01
19.6608Mhz
BA03_A
BRD-
BA09_B
C50
.1UF
BA06
+3P3V
CS10-
D20
(KEY)
+5V
BA09_A
WDO
BD00
(KEY)
{BD27}
GND
D1
PHASE_B-
BD14
GND
+5V
+5V
SERVO
BD12_A
BA13_A
PHA
BD11_B
{BD31}
(KEY)
+3.3V
MEMCS0-
GND
BD04_A
BD14_A
HPBD6
BD12_B
D0
D7
THIS DOCUMENT IS THE CONFIDENTIAL PROPERTY OF DELTA TAU
GND
HPBD1
BWR_A-
BA03_A
U20
IDT74FCT164245TPA
(TSSOP48)
23568911
12
46444341403837
36
147
10
47
48
1314151617181920212223
2425
26272829303132333435394245
B0B1B2B3B4B5B6
B7
A1A2A3A4A5A6A7
A8
T/R1
GND
VCCB
GND
A0
OE1
B8
B9
GND
B10
B11
VCCB
B12
B13
GND
B14
B15
T/R2
OE2
A15
A14
GND
A13
A12
VCCA
A11
A10
GNDA9GND
VCCA
GND
BD21
EQU_1-
BA13_A
BD01_A
BD02_A
BD05_B
BD16_B
BX/Y_B
BA00
+3P3V
BD17_B
BD00_A
BD05_B
CS3-
BA08
PHASE-
BA05
+3P3V
BD02_A
BD16_A
SDA
+12V
+5V
WAIT2-
CS0-
BD15_A
HPBD2
BD01_B
GND
BD06_A
BD23_A
+3.3V
(KEY)
+3.3V
BD17_A
IRQB-
BD10_B
CPCIDPR-
DATA SYSTEMS INC. AND IS LOANED SUBJECT TO RETURN UPON
BA04
GND
GND
BA03_A
BRD_A-
BD13_A
D18
D19
+3.3V
BD14_A
BA01
BA02_A
IREQ1-
BD04_A
D3
BD07_B
BD09_A
RESET_A
CS10-
+3P3V
+5V
PHASE
BD02_A
BD14_A
BD03_A
BD11_A
BA11_A
BD20_A
HPBD7
ENA_P1-
D12
(JEXP_A)
{BD20}
BA11
+12V
+3P3V
CS00-
D22
BA05_B
BD18
(KEY)
GND
-12V
CS14-
SDA
CPCIDPR-
BD23_B
PWRG
BWR_B-
BD09_A
PWRG
D11
BA01_B
SSM-125-L-DV-LC
DB22
BA03_A
BA04_A
BD22_B
{BA29}
CS4-
BD05
GND
GND
HPBD6
RESET_A
19.6608Mhz
D4
GND
PHA
BA08_A
D2
BD08_A
RESET_B
GND
GND
HPBD3
D15
C46
.1UF
GND
BA05_A
BA08_A
BD22_B
BD14_B
BRD-
D19
CS2-
INIT-
BD02_B
HPBD5
CS12-
n.c.
+5V
GND
BA07_A
PHASE
BD06_B
BSA00
J12
HEADER 25X2(FEM)
CLS125LDDV
12345678910
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
41 42
43 44
45 46
47 48
49 50
n.c.
+3.3V
BD15
+3P3V
BRD-
BD01_B
BD23_B
BA12
BA10_B
GND
BD06_A
PHASE_B+
CS14-
ONLY PURSUANT TO WRITTEN LICENSE OR WRITTEN INSTRUCTIONS
IREQ2-
VMECS0-
BA06_A
BA04_A
BA09
WDO
BRD_A-
BA03
SERVO-
BA11_A
CS0-
C75
.1UF
U21
IDT74FCT164245TPA
(TSSOP48)
23568911
12
46444341403837
36
147
10
47
48
1314151617181920212223
2425
26272829303132333435394245
B0B1B2B3B4B5B6
B7
A1A2A3A4A5A6A7
A8
T/R1
GND
VCCB
GND
A0
OE1
B8
B9
GND
B10
B11
VCCB
B12
B13
GND
B14
B15
T/R2
OE2
A15
A14
GND
A13
A12
VCCA
A11
A10
GNDA9GND
VCCA
GND
J1-1
CONN175-CPCI
A1A2A3A4A5A6A7A8A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A1A2A3A4A5A6A7A8A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
PHASE+
GND
GND
PWRG
BA10_A
BD19_A
CS04-
CS4-
BD16_B
BD21_A
GND
-12V
+3P3V
BA04_A
BD17_A
SERVO
BD20_B
GND
+5V
BA02
D15
BA03
n.c.
BD19
19.6608Mhz
BWR_A-
BD23_A
PWRGUD
BX/Y_B
BA10
SERVO_B+
BSA00
MEMCS1-
+5V
BA12_A
(KEY)
GND
BA01_A
BA08_A
BD22_A
BD19_B
BA02_B
C52
.1UF
BD06
+5V
SERVO_B-
D4
BD07_B
BD18_B
BA13
BD01_A
BD13_A
BA12_A
HR/W
WDO_B
HPBD3
BA11_B
U22
IDT74FCT164245TPA
(TSSOP48)
23568911
12
46444341403837
36
147
10
47
48
1314151617181920212223
2425
26272829303132333435394245
B0B1B2B3B4B5B6
B7
A1A2A3A4A5A6A7
A8
T/R1
GND
VCCB
GND
A0
OE1
B8
B9
GND
B10
B11
VCCB
B12
B13
GND
B14
B15
T/R2
OE2
A15
A14
GND
A13
A12
VCCA
A11
A10
GNDA9GND
VCCA
GND
CS16-
BD08
+3.3V
BD00_A
BA10_B
D8
BD16_A
GND
+3P3V
CS4-
BSA01
BD10_A
BA06_B
WAIT2-
BD17_B
+5V
BA02_A
{BA14}
CS2-
PWRGUD
SCL
BX/Y_A
BD21_B
(JEXP_A)
n.c.
+3.3V
(KEY)
CS02-
D2
BA01_B
D17
{BA25}
GND
+5V
CS02-
SERVO
BD11_B
BA09_A
HPBD3
WDO
BD07_A
V(I/O)
BA08
GND
BD03_A
BD13_A
D9
D14
D23
BA00
BA08_B
(KEY)
CS16-
HPBD7
BA13_B
BD06_A
D10
+5V
603625-322A
-
UMAC-CPCI-CPU, MEMORY & I/O SECTI
O
Delta Tau Data Systems, Inc.
D
23Tuesday, January 15, 2002
Title
Size Document Number Rev
Date: Sheet
of
BD13_A
BA00
BA04_B
BD00_B
POSSESSION OF THIS DOCUMENT INDICATES ACCEPTANCE OF THE
BA12
+5V
+5V
BD07_A
BA07_B
WDO_B
HW20-09-GD-450-SM
GND
GND
GND
HPBD1
CS06-
PHASE_B+
D17
C127
.1UF
+3P3V
BD02_A
BD14_A
C76
.1UF
-12V
BD21_A
V_I/O
RESET_A
PHASE
GND
n.c.
HDS-
BD20_A
BA00_A
BA03
(JEXP_B)
+5V
CS0-
IOCS_B-
BD09_A
HPBD6
SER
D12
BRD-
BA08_B
D20
BSA02
C45
.1UF
J12A
HEADER 25X2(MALE)
HW2515GD450SM
12345678910
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
41 42
43 44
45 46
47 48
49 50
+5V
+3P3V
BA04_B
CS1-
BA06
J1-6
CONN175-CPCI
F1F2F3F4F5F6F7F8F9
F10
F11
F12
F13
F14
F15
F16
F17
F18
F19
F20
F21
F22
F23
F24
F25
F1F2F3F4F5F6F7F8F9
F10
F11
F12
F13
F14
F15
F16
F17
F18
F19
F20
F21
F22
F23
F24
F25
INVENTIONS ARE RESERVED BY DELTA TAU DATA SYSTEMS INC.
CS14-
n.c.
GND
BA10
+5V
IRQB-
EQU_2-
BX/Y
HW25-09-GD-450-SM
+5V
+3P3V
+3P3V
-5V
BA01_A
BA05_A
D5
BA12_B
BSA01
WAIT2-
C77
.1UF
BD05_A
BRD_B-
HPBD4
D10
BD12_A
BD23
GND
+5V
GND
BX/Y_A
RESET_B
HDS-
D0
GND
D18
BX/Y
HPBD4
BD11_A
BA04_A
U26
ADM1485JR
(SO8)
123
4 5
678
RO
RE
DE
DI GND
A
B
VCC
GND
N.C.
+5V
MEMCS0-
SCL
(KEY)
BD13
+5V
CS2-
BA02
CS3-
BA01
UMAC-CPCI Turbo CPU Board Hardware Reference Manual
Schematics 25
XIN_5
USBD3
C20
0.1uF
J10
HSIP8NO5
1234678
n.c.
GND
EQU_1
EthExtRxF+
USBDM
WD_NC
422_CS+
INIT-
HPBD4
SDI
SERVO-
GND
HPBD7
EthRxF-
IPOS
SOT23
Q6
2N7002
3
12
+5V
EthExtTxF+
XIN_2
R28
1M
IPOS
R_PHASE+
GND
E3
+12V
J7
RJ45
123456789
10
WD_NC
EthExtRxF-
C196
.1UF
E2
HPBD2
WD_NO
J2-1
CONN154-CPCI
A1A2A3A4A5A6A7A8A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A1A2A3A4A5A6A7A8A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
(1-3)(16-14)1:1
(6-8)(11-9)1:2.5
U32
ST7011
1234567
8
16151413121110
9
n.c.
+3P3V
422_RS+
VR1
LT1175CST-5
(SOT223)
(TAB IS INPUT)
2
1
3
VI
GND
VO
U65
NC7SZ02M5
(SOT32-5)
1
2
4
53
GND
CHGND
422_SD-
USBDP
J2-4
CONN154-CPCI
D1D2D3D4D5D6D7D8D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D1D2D3D4D5D6D7D8D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
AuxDSR
EthExtTxF-
RAMOE-
MainCTS
TP2
+3P3
SOT23
Q7
2N7002
3
12
422_CS-
XIN_1
422_RS+
-12V
AuxRXD-
n.c.
+5V
GND
XIN_3
AuxRTS
USBRST-
R29 24.3
MainRXD-
AuxTxD-
GND
BSC_USB-
USBD4
EthTxF+
EthExtTxF+
GND
NMI-
USBD6
+
C192
10UF
16V
(TANT)
D9
1SMC5.0AT3
USBRD-
L5
BEAD
OPTION 1
XIN_6
MainCTS
422_SD-
MainTxD-
MainRTS
422_RD+
HPBD1
HPBD3
n.c.
GND
AuxTxD-
ENA_P2-
GND
WDO
USBD7
-5V
SCLK
+12V
422_RD-
CARD0
C190
.1UF
U64
NC7SZ02M5
(SOT32-5)
1
2
4
53
+5V
+3P3V
PSEN-
GND
+5V
+
C176
2.2UF
AuxCTS
AuxRTS
R_PHASE-
n.c.
HPBD0
(jisp_b)
-12V
EthExtTxF+
D12
1SMC18AT3
422_SD+
GND
HREQ-
D13
MMBD301LT1
(SOT23)
1 3
PHASE+
+5V
TBD_0
REMOVE `E11' FOR
WD_NO
+3P3V
NMI-
n.c.
R_SERVO-
E18D
2
3
1
AuxRTS
GND
INIT-
GND
TP3
+5V
USBD0 HPBD0
E4
EthExtRxF-
D10
1SMC5.0AT3
RP22
3.3KSIP10C
12
3 4 5 6 7 8 9 10
ispEN-
+3P3
MainRTS
INIT-
GND
MainRxD-
R_SERVO+
HPBD2
422_RD+
422_RD+
422_SD+
U62
SN75240PW
123
4 5
678
GNDCGND
D GND
B
GND
A
SERVO+
GND
HPBD4
422_SD+
Avcc
MainDSR
GND
PWRG
AuxRxD-
E18C
2
3
1
J3
USB-B
12345
6
VCC
D-
D+
GND
shell
shell
+5V
HOSTENA-
WD_NO
+
C195
10UF
25V
(TANT)
J2
MainRTS
-5V
TDI_USB
GND
HPBD7
M2
HOLE
GND AuxRxD-
WD_COM
+5V
GND
+12V
GND
J2-2
CONN154-CPCI
B1B2B3B4B5B6B7B8B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B1B2B3B4B5B6B7B8B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
U61
NC7SZ00M5
1
2
4
53
E4
n.c.
MainRxD-
C175
0.1uF
+5V
EthExtTxF-
1:1.41
E11
422_RS-
USBD1
Ethernet Option
USBDP
R_PHASE-
GND
422_RD-
HPBD5
U66
MAX8215CSD
(SO14)
1234567 8
910111213
14
VREF
GND
+5V
-5V
+12V
-12V
DIN PGND
DOUT
OUT4
OUT3
OUT2
OUT1
VDD
USBD5
GND
U58
NC7SZ08M5
1
2
4
53
J2-5
CONN154-CPCI
E1E2E3E4E5E6E7E8E9
E10
E11
E12
E13
E14
E15
E16
E17
E18
E19
E20
E21
E22
E1E2E3E4E5E6E7E8E9
E10
E11
E12
E13
E14
E15
E16
E17
E18
E19
E20
E21
E22
R_PHASE+
GND
GND
ENA_P1-
EthRxF+
CHGND
RAMENA-
EthTxF-
CE1
0.1uF
D11
1SMC18AT3
TP1
GND
422_CS-
40/60
422_RS-
E18A
2
3
1
-12V
INIT-
XIN_4
U6
PI74FCT245TL
(TSSOP20)
234567891
19
181716151413121120
10
A0A1A2A3A4A5A6A7T/R
OE
B0B1B2B3B4B5B6
B7
VCC
GND
SDO
GND
AuxCTS
+
C193
10UF
16V
(TANT)
M4
HOLE
PHASE-
GND
GND
R_SERVO-
C160
.1UF
MainTxD-
J2-6
CONN154-CPCI
F1F2F3F4F5F6F7F8F9
F10
F11
F12
F13
F14
F15
F16
F17
F18
F19
F20
F21
F22
F1F2F3F4F5F6F7F8F9
F10
F11
F12
F13
F14
F15
F16
F17
F18
F19
F20
F21
F22
422_CS+
n.c.
GND
E_51
J2-3
CONN154-CPCI
C1C2C3C4C5C6C7C8C9
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C1C2C3C4C5C6C7C8C9
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
HPBD5
C191
.01UF
AuxTXD-
MainCTS
XIN_7
HPBD6
WD_NC
U54
NC7SZ00M5
1
2
4
53
CE4
0.1uF
K1
FBR12ND05
4
3
5910
8
1
12
EthExtRxF+
DIGITAL ONLY USE
ETHENA-
TP5
-12V
+5V
AuxDTR
+
C194
10UF
25V
(TANT)
MainDTR
603625-322A
-
UMAC-CPCI-CPU, USB/2.0/Ethernet Secti
o
Delta Tau Data Dystems, Inc.
2.0/Ethernet UMAC-CPCI Communicatio
n
D
33Tuesday, January 15, 2002
Title
Size Document Number Rev
Date: Sheet
of
+5V
AuxCTS
USBD2
n.c.
EQU_1
ENA_P1-
TDO_USB
E18B
2
3
1
M3
HOLE
n.c.
PWRG
EthExtRxF+
E3
MainTXD-
EthExtTxF-
+3P3V
422_CS+
U73
NC7SZ00
1
2
4
53
C28
.1UF
MODE
GND
EQU_1-
n.c.
GND
HPBD1
WD_COM
422_RD-
TMS_USB
TCK_USB
USBDM
CE3
0.1uF
+3P3V
GND
R_SERVO+
E11
21
GND
422_RS-
CARD0
422_CS-
TP4
+12V
R30 24.3
+5V
ENA_P2-
R31 1.5K
CE2
0.1uF
TP6
-5V
422_SD-
+3P3V
HPBD6
M1
HOLE
J10
+5V
422_RS+
+5V
GND
E2
GND
WDO
GND
HPBD3
U57
NC7SZ08M5
1
2
4
53
+3P3V
RAMCS-
GND
EthExtRxF-
WD_COM
Loading...
Buy Points How it Works FAQ Contact Us Questions and Suggestions Privacy Policy Cookie Policy Terms of Use