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In the case of industrial applications, we expect our products to be protected from hazardous or
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If Delta Tau Data Systems, Inc. products are exposed to hazardous or conductive materials and/or
environments, we cannot guarantee their operation.
Base Version............................................................................................................................................................1
Option 1: Additional Four Channels Axis Interface Circuitry...............................................................................1
Option 9: Serial Port Configuration ......................................................................................................................2
Option 10: Firmware Version Specification ..........................................................................................................3
E2-E3: Expansion Port Configure..............................................................................................................................5
E1: Servo and Phase Clock Direction Control ...........................................................................................................7
E2: (Reserved for Future Use)....................................................................................................................................7
E4 – E6: (Reserved for Future Use) ...........................................................................................................................7
E7A-H, E8A-H, E9A-H, E10A-H: P2 Connector B-Row Use Select........................................................................7
E11 – E12: Compare Output Supply Voltage Configure...........................................................................................8
E13 - E14: Encoder Sample Clock Direction Control................................................................................................8
E17 - E18: Serial Connector Select............................................................................................................................8
E20A-I: DPRAM Byte Order Control........................................................................................................................9
JP1-1 to JP1-32: P2A Connector B-Row Use Select ...............................................................................................11
E14: SCLK Direction Control..................................................................................................................................11
CPU Board Connectors .............................................................................................................................................13
Base Board Connectors .............................................................................................................................................13
J4 (JMACRO)/Macro Digital Data.......................................................................................................................13
J5 (JRS232)/RS-232 Serial Communications........................................................................................................13
J5A (JRS422)/RS-422 Serial Communications......................................................................................................13
J9 (JMACH1)/Machine Port 1 ..............................................................................................................................14
J10 (JMACH2)/Machine Port 2 ............................................................................................................................14
P1 (PVME)/Main VME Bus Connector.................................................................................................................14
J11 (JMACH3)/ Machine Port 3 ...........................................................................................................................14
J12 (JMACH4)/ Machine Port 4 ...........................................................................................................................14
P2A (PMACHA)/Alternate Machine Port .............................................................................................................14
BASE BOARD CONNECTOR PINOUTS............................................................................................................15
J1 (JANA) Analog Input Port Connector..................................................................................................................15
J2 (JTHW) Multiplexer Port Connector....................................................................................................................16
J3 (JI/O) General Input/Output Connector................................................................................................................17
J4 (JMACRO) MACRO Network Ring Interface Connector....................................................................................18
J5 (JRS232) Serial Port Connector............................................................................................................................18
J5A: RS422 Serial Port Connector............................................................................................... .............................19
P1 (JVME) VME Bus Connector..............................................................................................................................27
The Turbo PMAC2 VME is a member of the Turbo PMAC family of boards optimized for interface to
sinewave or direct PWM servo drives and to pulse-and-direction stepper drives. Its software is capable of
32 axes of control. It can have up to eight channels of on-board axis interface circuitry. It can also
support up to 32 channels of off-board axis interface circuitry through its expansion port, connected to
Acc-24P or Acc-24P2 boards.
The Turbo PMAC2 VME is a full-sized ISA-bus expansion card, with a small piggyback board
containing the CPU board. This piggyback board occupies part of the next slot, but ½-sized boards are
permitted in this next slot. While the Turbo PMAC2 VME is capable of ISA bus communications, with
or without the optional on-board dual-ported RAM, it does not need to be inserted into an ISA expansion
slot. Communications can be done through an RS-232 or optional RS-422 serial port; standalone
operation is possible.
Board Configuration
Base Version
The base version of the Turbo PMAC2 VME provides a 2-slot board with:
• 80 MHz DSP56303 CPU (120 MHz PMAC equivalent)
• 128k x 24 SRAM compiled/assembled program memory (5C0)
• 128k x 24 SRAM user data memory (5C0)
• 1M x 8 flash memory for user backup & firmware (5C0)
• Latest released firmware version
• RS-232 serial interface, VME bus interface
• 1 16-node MACRO interface IC
• Four channels axis interface circuitry, each including:
• Three output command signal sets, configurable as either:
Two serial data streams to external DACs, 1 pulse-and-direction
Three PWM top-and-bottom pairs
• One output command signal set, configurable as pulse-and-direction or
PWM top-and-bottom pair
• Display, MACRO, muxed I/O, direct I/O interface ports
• PID/notch/feedforward servo algorithms
• Extended "pole-placement" servo algorithms
• 1-year warranty from date of shipment
• One manual per set of one to four PMACs in shipment
(Cables, mounting plates, mating connectors not included)
Option 1: Additional Four Channels Axis Interface Circuitry
• Option 1V provides an additional four channels of axis interface circuitry on a small piggyback
board, identical to the standard first four channels on the base board.
Introduction 1
Turbo PMAC2 VME Hardware Reference
Option 2: Dual-Ported RAM
Dual-ported RAM provides a high speed communications path for bus communications with the host
computer through a bank of shared memory. DPRAM is advised if more than about 100 data items per
second are to be passed between the controller and the host computer in either direction.
Option 2V provides an 8k x 16 bank of dual-ported RAM. The key component on the board is U87.
Option 5: CPU and Memory Configurations
The various versions of Option 5 provide different CPU speeds and main memory sizes on the piggyback
CPU board. Only one Option 5xx may be selected for the board.
The CPU is a DSP5630x IC as component U1. Currently, it is available only as an 80 MHz device (with
computational power equivalent to a 120 MHz non-Turbo PMAC), but higher speed versions will be
available shortly.
The compiled/assembled-program memory SRAM ICs are located in U14, U15, and U16. These ICs
form the active memory for the firmware, compiled PLCs, and user-written phase/servo algorithms.
These can be 128k x 8 ICs (for a 128k x 24 bank), fitting in the smaller footprint, or they can be the larger
512k x 8 ICs (for a 512k x 24 bank), fitting in the full footprint.
The user-data memory SRAM ICs are located in U11, U12, and U13. These ICs form the active memory
for user motion programs, uncompiled PLC programs, and user tables and buffers. These can be 128k x 8
ICs (for a 128k x 24 bank), fitting in the smaller footprint, or they can be the larger 512k x 8 ICs (for a
512k x 24 bank), fitting in the full footprint.
The flash memory IC is located in U10. This IC forms the non-volatile memory for the board’s firmware,
the user setup variables, and for user programs, tables, and buffers. It can be 1M x 8, 2M x 8, or 4M x 8
in capacity.
• Option 5C0 is the standard CPU and memory configuration. It is provided automatically if no Option
5xx is specified. It provides an 80 MHz CPU (120 MHz PMAC equivalent), 128k x24 of
compiled/assembled program memory, 128k x 24 of user data memory; and a 1M x 8 flash memory.
• Option 5C1 provides an 80 MHz CPU (120 MHz PMAC equivalent), 128k x 24 of
compiled/assembled program memory, an expanded 512k x 24 of user data memory, and a 2M x 8
flash memor y.
• Option 5C2 provides an 80 MHz CPU (120 MHz PMAC equivalent), an expanded 512k x 24 of
compiled/assembled program memory, 128k x 24 of user data memory, and a 2M x 8 flash memory.
• Option 5C3 provides an 80 MHz CPU (120 MHz PMAC equivalent), an expanded 512k x 24 of
compiled/assembled program memory, an expanded 512k x 24 of user data memory, and a 4M x 8
flash memor y.
Option 7: Plate Mounting
• Option 7 provides a mounting plate connected to the PMAC with standoffs. It is used to install the
PMAC in standalone applications.
Option 8: High-Accuracy Clock Crystal
The Turbo PMAC2 VME has a clock crystal (component Y1) of nominal frequency 19.6608 MHz (~20
MHz). The standard crystal’s accuracy specification is +/-100 ppm.
• Option 8A provides a nominal 19.6608 MHz crystal with a +/-15 ppm accuracy specification.
Option 9: Serial Port Configuration
The Turbo PMAC2 VME comes standard with a single serial port, which can be used in either RS-232 or
RS-422 format. Optionally, a second independent serial port may be added.
2 Introduction
Turbo PMAC2 VME Hardware Reference
• Option 9T adds an auxiliary RS-232 port on the CPU piggyback board. The key components added
are IC U22 and connector J8 on the CPU board.
Option 10: Firmware Version Specification
Normally, the Turbo PMAC2 VME is provided with the newest released firmware version. A label on
the U10 flash memory IC shows the firmware version loaded at the factory.
• Option 10 provides for a user-specified firmware version.
Option 12: Analog-to-Digital Converters
Option 12 permits the installation of 8 or 16 channels of on-board multiplexed analog-to-digital
converters. One or two of these converters are read every phase interrupt. The analog inputs are not
optically isolated, and each can have a 0 – 5V input range, or a +/-2.5V input range, individually
selectable.
• Option 12 provides an 8-channel 12-bit A/D converter. The key components on the board are U28
and connector J1.
• Option 12A provides an additional 8-channel 12-bit A/D converter. The key component on the board
is U29.
Option 16: Battery-Backed Parameter Memory
The contents of the standard memory are not retained through a power-down or reset unless they have
been saved to flash memory first. Option 16 provides supplemental battery-backed RAM for real-time
parameter storage that is ideal for holding machine state parameters in case of an unexpected powerdown. The battery is located at component BT1.
• Option 16A provides a 32k x 24 bank of battery-backed parameter RAM in components U17, U18,
and U19 on the CPU board, fitting in the smaller footprint for those locations.
• Option 16B provides a 128k x 24 bank of battery-backed parameter RAM in components U17, U18,
and U19 on the CPU board, filling the full footprint for those locations.
Option 18: Identification Number and Real Time Clock/Calendar Module
Option 18 provides a module at location U5 on the CPU board that contains an electronic identification
number and possibly a real-time clock/calendar.
• Option 18A provides an electronic identification number module.
• Option 18B provides an electronic identification number module with a real-time clock and calendar.
The year representation in the calendar is a 4-digit value, so there are no Year 2000 problems.
Introduction 3
Turbo PMAC2 VME Hardware Reference
4 Introduction
Turbo PMAC2 VME Hardware Reference
CPU BOARD E-POINT DESCRIPTIONS
E1: Watchdog Disable Jumper
E Point and
Description Default
Physical Layout
E1
Jump pin 1 to 2 to disable Watchdog timer (for test purposes
only).
Remove jumper to enable Watchdog timer.
No jumper installed
E2-E3: Expansion Port Configure
(Prototype boards {-104 and earlier} only)
E Point and
Description Default
Physical Layout
E2
E3
Note: Production versions of the Turbo CPU board are built with circuit traces providing the equivalent of E2
and E3 ON. To use with an Option 2 DPRAM board, pins 41 and 42 on the 50-pin connector of the Option 2
board must be clipped in order to be able to operate properly. All Option 2 boards built since Turbo PMAC
production began have been built with these pins clipped.
Jump pin 1 to 2 to permit use of Acc-24 expansion boards.
Remove jumper to permit use of unmodified (pin 41 intact)
Option 2 DPRAM board
Jump pin 1 to 2 to permit use of Acc-24 expansion boards.
Remove jumper to permit use of unmodified (pin 42 intact)
Option 2 DPRAM board
Jumper installed
Jumper installed
E4 – E6: Power-Up/Reset Load Source
E Point and
Physical Layout
E4
E6
Remove jumper E4;
jump E5 pin 1 to 2;
jump E6 pin 2 to 3;
to read flash IC on power-up/reset.
Other combinations are for factory use only; the board will not
operate in any other configuration
E7: Firmware Reload Enable
E Point and
Physical Layout
E7
Jump pin 1 to 2 to reload firmware through serial or bus port
Remove jumper for normal operation.
Description Default
No E4 jumper
installed;
E5 and E6 jump pin
1 to 2
Description Default
No jumper installed
CPU Board E-Point Descriptions 5
Turbo PMAC2 VME Hardware Reference
6 CPU Board E-Point Descriptions
Turbo PMAC2 VME Hardware Reference
BOTTOM BOARD E-POINT JUMPER DESCRIPTIONS
E1: Servo and Phase Clock Direction Control
E Point and
Description Default
Physical Layout
E1
Note: If the E1 jumper is ON and the servo and phase clocks are not brought in on the J4 serial port, the
watchdog timer will trip immediately.
Remove jumper for Turbo PMAC2 VME to use its internally
generated servo and phase clock signals and to output these
signals on the J5x serial port connector
Jump pins 1 and 2 for Turbo PMAC2 VME to expect to receive its
servo and phase clock signals on the J5x serial port connector.
No jumper
E2: (Reserved for Future Use)
E3: Normal/Re-Initializing Power-Up/Reset
E Point and
Physical Layout
E51
Location Description Default
A2 Jump pin 1 to 2 to re-initialize ON power-up/reset.
Remove jumper for Normal power-up/reset.
No jumper installed
E4 – E6: (Reserved for Future Use)
E7A-H, E8A-H, E9A-H, E10A-H: P2 Connector B-Row Use Select
E Point and
Location Description Default
Physical Layout
E7A-H
E8A-H
E9A-H
E10A-H
Note: All jumpers in the E7 to E10 families must be in the same setting.
Jump pins 1 to 2 to use B-row of P2 connector for
JMACH pins (not compatible with 32-bit VME).
Jump pins 2 to 3 to use B-row of P2 connector for 32-
bit VME bus interface
Jump pins 1 to 2 to use B-row of P2 connector for
JMACH pins (not compatible with 32-bit VME).
Jump pins 2 to 3 to use B-row of P2 connector for 32-
bit VME bus interface.
Jump pins 1 to 2 to use B-row of P2 connector for
JMACH pins (not compatible with 32-bit VME).
Jump pins 2 to 3 to use B-row of P2 connector for 32-
bit VME bus interface.
Jump pins 1 to 2 to use B-row of P2 connector for
JMACH pins (not compatible with 32-bit VME).
Jump pins 2 to 3 to use B-row of P2 connector for 32-
bit VME bus interface.
1-2 Jumpers installed
1-2 Jumpers installed
1-2 Jumpers installed
1-2 Jumpers installed
(32-bit VME)
Bottom Board E-Point Jumper Descriptions 7
Turbo PMAC2 VME Hardware Reference
E11 – E12: Compare Output Supply Voltage Configure
E Point and
Location Description Default
Physical Layout
E11
D3 Jump pin 1 to 2 to apply +V (+5V to 24V) to pin 11
of U74 (should be ULN2803A for sink output
configuration) JEQU Compare outputs EQU1-EQU8.
Jump pin 2 to 3 to apply GND to pin 11 of U74
(should be UDN2981A for source output
configuration).
WARNING:
The jumper setting must match the type of driver
IC, or damage to the IC will result.
E12
C3 Jump pin 1 to 2 to apply GND to pin 10 of U74
(should be ULN2803A for sink output configuration).
Jump pin 2 to 3 to apply +V (+5V to 24V) to pin 10
of U74 (should be UDN2981A for source output
configuration).
WARNING:
The jumper setting must match the type of driver
IC, or damage to the IC will result.
E13 - E14: Encoder Sample Clock Direction Control
1-2 Jumper installed
1-2 Jumper installed
E Point and
Location Description Default
Physical Layout
E13
Remove jumper to output SCLK generated in first
ASIC on SCLK_12 and SCLK_34, or to control
direction by software.
Jump pins 1 to 2 to input SCLK signal for first ASIC
on SCLK_34 and output this signal on SCLK_12.
Jump pins 2 to 3 to input SCLK signal for first ASIC
on SCLK_12 and output this signal on SCLK_34.
E17 - E18: Serial Connector Select
E17 and E18 control whether the RS-232 or RS-422 serial port is used.
All E20A-I jumpers must be in the same setting for DPRAM communications to work.
Jump pins 1 to 2 and pins 3 to 4, to tie DPRAM data
lines 8-15 to VMEbus data lines 8-15, and DPRAM
data lines 0-7 to VMEbus data lines 0-7 (Motorola
big-endian format).
Jump pins 2 to 3 and pins 4 to 5 to tie DPRAM data
lines 8-15 to VMEbus data lines 0-7, and DPRAM
data lines 0-7 to VMEbus data lines 8-15 (Intel littleendian format).
E39: Reset-from-Bus Enable
E Point and
Physical Layout
E39
Location Description Default
B5 Jump pin 1 to 2 to permit VMEbus reset line to reset
PMAC2.
Remove jumper so VMEbus reset line does not reset
PMAC2.
1-2, 3-4 Jumpers
installed (Motorola
format)
1-2 Jumper installed
Bottom Board E-Point Jumper Descriptions 9
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