Delta Tau PMAC MINI PCI, PMAC PCI, PMAC PCI LITE, PMAC VME, PMAC2 PCI Reference Manual

...
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^1 HARDWARE REFERENCE MANUAL
^2 Flex CPU Piggyback Board
21314 Lassen Street Chatsworth, CA 91311 // Tel. (818) 998-2095 Fax. (818) 998-7807 // www.deltatau.com
^3 CPU
^4 3xx-603605-xHxx
^5 December 8 2003
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Copyright Information
© 2003 Delta Tau Data Systems, Inc. All rights reserved. This document is furnished for the customers of Delta Tau Data Systems, Inc. Other uses are
unauthorized without written permission of Delta Tau Data Systems, Inc. Information contained in this manual may be updated from time-to-time due to product improvements, etc., and may not conform in every respect to former issues.
To report errors or inconsistencies, call or email:
Delta Tau Data Systems, Inc. Technical Support
Phone: (818) 717-5656 Fax: (818) 998-7807 Email: support@deltatau.com Website: http://www.deltatau.com
Operating Conditions
All Delta Tau Data Systems, Inc. motion controller products, accessories, and amplifiers contain static sensitive components that can be damaged by incorrect handling. When installing or handling Delta Tau Data Systems, Inc. products, avoid contact with highly insulated materials. Only qualified personnel should be allowed to handle this equipment.
In the case of industrial applications, we expect our products to be protected from hazardous or conductive materials and/or environments that could cause harm to the controller by damaging components or causing electrical shorts. When our products are used in an industrial environment, install them into an industrial electrical cabinet or industrial PC to protect them from excessive or corrosive moisture, abnormal ambient temperatures, and conductive materials. If Delta Tau Data Systems, Inc. products are directly exposed to hazardous or conductive materials and/or environments, we cannot guarantee their operation.
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Flex CPU Piggyback Board Hardware Reference
Table of Contents
INTRODUCTION.......................................................................................................................................................1
BOARD CONFIGURATION.....................................................................................................................................3
Non-Turbo CPU Base Configuration...................................................................................................................3
Non-Turbo CPU Further Options.........................................................................................................................3
Turbo CPU Base Configuration...........................................................................................................................3
Turbo CPU Further Options.................................................................................................................................3
HARDWARE SETUP.................................................................................................................................................5
Flex CPU Board Jumper Configuration............................................................................................................... 5
Watchdog Timer Jumper.......................................................................................................................................5
Dual-Ported RAM Source Jumper........................................................................................................................5
Power-Up State Jumpers......................................................................................................................................5
Firmware Load Jumper........................................................................................................................................5
Flash Memory Bank Select Jumpers.....................................................................................................................5
Installation............................................................................................................................................................5
OPERATION OF THE FLEX CPU..........................................................................................................................7
Operation as Non-Turbo CPU..............................................................................................................................7
Operation as a Turbo CPU...................................................................................................................................9
FLEX CPU BOARD JUMPER DESCRIPTIONS..................................................................................................11
E1: Watchdog Disable Jumper...........................................................................................................................11
E2: Dual-Ported RAM Port Select......................................................................................................................11
E4 – E6: Power-Up/Reset Load Source..............................................................................................................11
E7: Firmware Reload Enable.............................................................................................................................11
E10A, B, C: Flash Memory Bank Select.............................................................................................................12
CONNECTOR SUMMARY.....................................................................................................................................13
CONNECTOR PINOUTS.........................................................................................................................................15
J8 JRS232 (10-Pin Connector)...........................................................................................................................15
SCHEMATICS
Table of Contents i
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Flex CPU Piggyback Board Hardware Reference
ii Table of Contents
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Flex CPU Piggyback Board Hardware Reference
INTRODUCTION
The Flex CPU piggyback board (Part # 300-603605-10x) for the PMAC/PMAC2 and Turbo PMAC/PMAC2 families of boards provides new high-end capabilities for these controllers and uses newer components with longer product lifetimes. It can be manufactured in a wide variety of configurations, and can be used in the following products:
PMAC(1)-PC
PMAC(1)-PCI
PMAC(1)-VME
PMAC2-PC
PMAC2-PCI
PMAC2-VME
Turbo PMAC(1)-PC
Turbo PMAC(1)-PCI
Turbo PMAC(1)-VME
Turbo PMAC2-PC
Turbo PMAC2-PCI
Turbo PMAC2-VME
On the regular (non-Turbo) PMAC(1) and PMAC2 boards, the Flex CPU is provided automatically when any of the following CPU options are ordered:
Option 5AF: 40 MHz CPU with 128k x 24 internal SRAM
Option 5CF: 80 MHz CPU with 128k x 24 internal SRAM
Option 5EF: 160 MHz CPU with 128k x 24 internal SRAM
The Flex CPU board is not provided if Option 4x or 5x is not ordered, or if Option 4A, 5A, 5B, or 5C is ordered.
On Turbo PMAC(1) and Turbo PMAC2 boards, the Flex CPU may be provided when any of the following CPU options is ordered:
Option 5C0: 80 MHz DSP56303 CPU with 8k x 24 internal SRAM, 256k x 24 external SRAM
Option 5C3: 80 MHz DSP56303 CPU with 8k x 24 internal SRAM, 1M x 24 external SRAM
Option 5D0: 100 MHz DSP56309 CPU with 34k x 24 internal SRAM, 256k x 24 external SRAM
Option 5D3: 100 MHz DSP56309 CPU with 34k x 24 internal SRAM, 1M x 24 external SRAM
In these cases, however, the older Turbo only CPU piggyback board may also be provided. On Turbo PMAC(1) and Turbo PMAC2 boards, the Flex CPU will be provided automatically when either
of the following CPU options is ordered:
Option 5E0: 160 MHz DSP56309 CPU with 128k x 24 internal SRAM, 256k x 24 external SRAM
Option 5E3: 160 MHz DSP56309 CPU with 128k x 24 internal SRAM, 1M x 24 external SRAM
Introduction 1
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Flex CPU Piggyback Board Hardware Reference
2 Introduction
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Flex CPU Piggyback Board Hardware Reference
BOARD CONFIGURATION

Non-Turbo CPU Base Configuration

When assembled for a non-Turbo CPU, the DSP IC in U1 of the Flex CPU board contains all of the memory required for operation. Therefore, there are no ICs installed in the locations for external RAM: U11, U12, U13, U14, U15, and U16.
The CPU is available in several speed options: 40 MHz (Option 5AF), 80 MHz (Option 5CF), and 160 MHz (Option 5EF). The maximum frequency of operation is indicated with a sticker on the CPU in U1.
When the Flex CPU is built for ISA-bus or VME-bus baseboards, the P3 connector consists of a 36-pin header on the solder side for direct connection to the baseboard, and a 10-pin header on the component side for cable connection of the extra signals required for dual-ported RAM interface. When the Flex CPU is built for PCI-bus baseboards the P3 connector consists only of a 56-pin header on the solder side for direct connection of all signals to the baseboard.

Non-Turbo CPU Further Options

The Option 16 battery-backed parameter RAM provides a bank of non-volatile memory for the controller. Its key components are RAM ICs in U17, U18, and U19, and a battery in BT1

Turbo CPU Base Configuration

When assembled for a Turbo CPU section, the Flex CPU board contains external RAM ICs in locations U11, U12, U13, U14, U15, U16. With the standard memory configuration (Option 5x0), these ICs fill the smaller footprint in these locations, leaving an open pin on the board on each end of each side.
When the Flex CPU is built for ISA-bus or VME-bus baseboards, the P3 connector consists of a 36-pin header on the solder side for direct connection to the baseboard, and a 10-pin header on the component side for cable connection of the extra signals required for dual-ported RAM interface. When the Flex CPU is built for PCI-bus baseboards the P3 connector consists only of a 56-pin header on the solder side for direct connection of all signals to the baseboard.

Turbo CPU Further Options

If an expanded memory configuration (Option 5x3) is ordered, larger RAM ICs are installed in locations U11, U12, U13, U14, U15, U16, occupying the full footprints in these locations
If the Option 9T auxiliary serial port is ordered for the Turbo PMAC controller, an RS-232 serial port is provided on the CPU board to supplement the serial port on the baseboard. The key components are ICs in U28 and U29, and the connector J8.
The Option 16A battery-backed parameter RAM provides a bank of non-volatile memory for the controller. Its key components are RAM ICs in U17, U18, and U19, and a battery in BT1
Board Configuration 3
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Flex CPU Piggyback Board Hardware Reference
4 Board Configuration
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Flex CPU Piggyback Board Hardware Reference
HARDWARE SETUP

Flex CPU Board Jumper Configuration

Watchdog Timer Jumper

Jumper E1 on the Turbo CPU board must be OFF for the watchdog timer to operate. This is a very important safety feature, so it is vital that this jumper be OFF in normal operation. E1 should be put ON only to debug problems with the watchdog timer circuit.

Dual-Ported RAM Source Jumper

Jumper E2 must connect pins 1 and 2 to access dual-ported RAM (non-Turbo addresses $Dxxx, Turbo addresses $06xxxx) from the baseboard. If it is desired to use the Option 2 DPRAM on the baseboard, jumper E2 must be in this setting. All Delta Tau base boards except the PMAC(1)-PC board have the option for installing DPRAM on the base board.
Jumper E2 must connect pins 2 and 3 to access dual-ported RAM (non-Turbo addresses $Dxxx, Turbo addresses $06xxxx) through the JEXP expansion port. If it is desired to use DPRAM on an external accessory board, jumper E2 must be in this setting. The PMAC(1)-PC base board (part # 602191-10x) does not have the option for installing on-board DPRAM; it requires the external Option 2 DPRAM board (part #602240-10x) for this functionality. Use of this DPRAM board, interfacing through the JEXP port, requires E2 to connect pins 2 and 3.

Power-Up State Jumpers

Jumper E4 on the Turbo CPU board must be OFF, jumper E5 must be ON, and jumper E6 must be ON, in order for the CPU to copy the firmware from flash memory into active RAM on power-up/reset. This is necessary for normal operation of the card. (Other settings are for factory use only.)

Firmware Load Jumper

If jumper E7 on the CPU board is ON during power-up/reset, the board comes up in “bootstrap mode,” which permits loading new firmware into the flash-memory IC on the board. When the PMAC Executive program tries to establish communications with a board in this mode, it will automatically detect that the board is in bootstrap mode and ask you what file you want to download as the new firmware.
Jumper E7 must be OFF during power-up/reset for the board to come up in normal “operational mode.”

Flash Memory Bank Select Jumpers

The flash-memory IC in location U10 on the Flex CPU board has the capacity for eight separate banks of firmware, only one of which can be used at any given time. The eight combinations of settings for jumpers E10A, E10B, and E10C select which bank of the flash memory is used. In the factory production process, firmware is loaded only into Bank 0, which is selected by having all of these jumpers OFF.

Installation

The Flex CPU board installs on the base controller board using the P1 and P3 stack connectors on the solder side of the CPU board. The CPU board can be further secured to the base board with a standoff and screw through the central hole. When a complete PMAC or Turbo PMAC controller is purchased, this assembly is done at the factory. In the case of retrofits or updates to existing controllers, this assembly is easy to do in the field.
ESD Warning: The Flex CPU board and PMAC controller boards contain static-sensitive components. Make sure proper ESD protection is employed.
Hardware Setup 5
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Flex CPU Piggyback Board Hardware Reference
6 Hardware Setup
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Flex CPU Piggyback Board Hardware Reference
OPERATION OF THE FLEX CPU

Operation as Non-Turbo CPU

When used as a non-Turbo CPU, the Flex CPU board operates in a manner that is fundamentally compatible with older CPU designs. However, there are a few issues to note:
The Flex CPU requires the use of V1.17 or newer firmware. There are few differences between the
previous V1.16H firmware and the V1.17 firmware other than the addition of internal support for the Flex CPU design.
Due to more advanced processor logic and the internal integration of all memory, the Flex CPU will
operate significantly faster than older non-Turbo CPU designs, even for equivalent CPU frequencies. The Flex CPU in a non-Turbo configuration will generally operate more than twice as fast as older non-Turbo CPUs running at the same frequency.
This will result in significantly faster cycle times for background tasks such as PLC programs (the frequency of interrupt-driven foreground tasks is not affected, although the increased computational speeds permit higher frequencies for these tasks). Generally, this will not be a problem, but if existing programs controlled timing by computational delay (e.g. number of loops waiting), operational differences may occur.
The operational frequency of the CPU can now be set in software by new variable I46. If this
variable is set to 0, PMAC firmware looks at the jumpers (E48 on a PMAC(1), E2 and E4 on a PMAC2) to set the operational frequency, retaining backward compatibility for 40, 60, and 80 MHz operation.. If I46 is set to a value greater than 0, the operational frequency is set to 10MHz * (I46 +
1), regardless of the jumper setting. If the desired operational frequency is higher than the maximum rated frequency for that CPU, the operational frequency will be reduced to the rated maximum. It is always possible to operate the Flex CPU board at a frequency below its rated maximum.
On a Flex CPU board configured for Option 5AF with 40 MHz maximum frequency, I46 should be set to 3 to operate the CPU at its maximum rated frequency.
On a Flex CPU board configured for Option 5CF with 80 MHz maximum frequency, I46 should be set to 7 to operate the CPU at its maximum rated frequency.
On a Flex CPU board configured for Option 5EF with 160 MHz maximum frequency, I46 should be set to 15 to operate the CPU at its maximum rated frequency.
I46 is only used at power-up/reset, so to change the operational frequency, set a new value of I46, issue a SAVE command to store this value in non-volatile flash memory, then issue a $$$ command to reset the controller.
To determine the frequency at which the CPU is actually operating, issue the TYPE command to the PMAC. The PMAC will respond with five data items, the last of which is CLK Xn, where n is the multiplication factor from the 20 MHz crystal frequency (not 10 MHz). n should be equivalent to (I46+1)/2 if I46 is not requesting a frequency greater than the maximum rated for that CPU board. n will be “2” for 40 MHz operation, 4 for 80 MHz operation, and 8 for 160 MHz operation.
If the CPU’s operational frequency has been determined by (a non-zero setting of) I46, the serial
communications baud rate is determined at power-up/reset by variable I54 alone according to the following table:
Operation of the Flex CPU 7
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Flex CPU Piggyback Board Hardware Reference
I54 Baud Rate I54 Baud Rate
0 600 8 9600 1 900 9 14,400 2 1200 10 19,200 3 1800 11 28,800 4 2400 12 38,400 5 3600 13 57,600 6 4800 14 76,800 7 7200 15 115,200
Note that these values can be different from those used on PMAC2 boards with jumper-set CPU frequencies (see below).
If the saved value of I46 is 0, so the CPU’s operational frequency is determined by jumper settings,
then the serial baud rate is determined by a combination of the setting of jumpers E44-E47 and the CPU frequency on a PMAC(1) board, as shown in the following table. These settings maintain backward compatibility.
E44 E45 E46 E47 Baud Rate
for
20MHz
N ON ON ON Disabled Disabled Disabled OFF ON ON ON 300 600 900 ON OFF ON ON 400* 800* 1200 OFF OFF ON ON 600 1200 1800 ON ON OFF ON 800* 1600* 2400 OFF ON OFF ON 1200 2400 3600 ON OFF OFF ON 1600* 3200* 4800 OFF OFF OFF ON 2400 4800 7200 ON ON ON OFF 3200* 6400* 9600 OFF ON ON OFF 4800 9600 14400 ON OFF ON OFF 6400* 12800* 19200 OFF OFF ON OFF 9600 19200 28800 ON ON OFF OFF 12800* 25600* 38400 OFF ON OFF OFF 19200 38400 57600 ON OFF OFF OFF 25600* 51200* 76800 OFF OFF OFF OFF 38400 76800 115200 * Not an exact baud rate
Baud Rate
for
40MHz
Baud Rate
for
60MHz
8 Operation of the Flex CPU
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Flex CPU Piggyback Board Hardware Reference
For a PMAC2 board with a saved value of 0 for I46, the serial baud rate is determined by the combination of I54 and the CPU frequency on a PMAC2 board as shown in the following table. These settings maintain backward compatibility.
I54 Baud Rate for
40 MHz CPU
0 600 Disabled 1200 1 900* (-0.05%) 900 1800* (-0.1%) 2 1200 1200 2400 3 1800* (-0.1%) 1800 3600* (-0.19%) 4 2400 2400 4800 5 3600* (-0.19%) 3600 7200* (-0.38%) 6 4800 4800 9600 7 7200* (-0.38%) 7200 14,400*(-0.75%) 8 9600 9600 19,200
9 14,400*(-0.75%) 14,400 28,800*(-1.5%) 10 19,200 19,200 38,400 11 28,800*(-1.5%) 28,800 57,600*(-3.0%) 12 38,400 38,400 76,800 13 57,600*(-3.0%) 57,600 115,200*(-6.0%) 14 76,800 76,800 153,600 15 Disabled 115,200 DISABLED
* Not an exact baud rate
With the Flex CPU, the card number (0 – 15) for serial addressing of multiple cards on a daisy-chain
Baud Rate for
60 MHz CPU
Baud Rate for
80 MHz CPU
serial cable is determined by variable I0, even on PMAC(1) boards. This has always been the case for PMAC2 boards, but with other CPU boards, the card number on PMAC(1) boards has been determined by the settings of jumpers E40 – E43. Jumpers E40 – E43 on a PMAC(1) board with the Flex CPU still determine the “direction” of the phase and servo clocks: all of these jumpers must be ON for the card to use its internally generated clock signals and to output these on the serial port connector; if any of these jumpers is OFF, the card will expect to input these clock signals from the serial port connector, and its watchdog timer will trip immediately if it does not receive these signals.

Operation as a Turbo CPU

When used as a Turbo CPU, the Flex CPU is fully compatible with older CPU designs. It does permit higher-speed configurations (Option 5Ex at 160 MHz), which offer significantly higher performance both due to increased operation frequency and added internal memory.
Variable I52 determines the actual operating frequency of the Turbo CPU. The operational frequency is set to 10MHz * (I52 + 1). I52 should be set to 7 to operate an Option 5Cx board at its maximum rated frequency of 80 MHz; it should be set to 9 to operate an Option 5Dx board at its maximum rated frequency of 100 MHz; it should be set to 15 to operate an Option 5Ex board at is maximum rated frequency of 160 MHz.
I52 is used only at power-up/reset, so to change the operational frequency, set a new value of I52, issue a SAVE command to store this value in non-volatile flash memory, then issue a $$$ command to reset the controller.
Operation of the Flex CPU 9
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Flex CPU Piggyback Board Hardware Reference
10 Operation of the Flex CPU
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Flex CPU Piggyback Board Hardware Reference
FLEX CPU BOARD JUMPER DESCRIPTIONS

E1: Watchdog Disable Jumper

E Point and
Description Default
Physical Layout
E1
Jump pin 1 to 2 to disable Watchdog timer (for test purposes only).
Remove jumper to enable Watchdog timer.

E2: Dual-Ported RAM Port Select

E Point and
Physical Layout
E2
Jump pin 1 to 2 to access DPRAM from baseboard. Jump pin 2 to 3 to access DPRAM through JEXP
expansion port (PMAC(1)-PC with Option 2 DPRAM board).
Description Default

E4 – E6: Power-Up/Reset Load Source

E Point and
Physical Layout
E6
Remove jumper E4; jump E5 pin 1 to 2; jump E6 pin 2 to 3; to read flash IC on power-up/reset Other combinations are for factory use only ; the boa r d
will not operate in any other configuration.
Description Default
No jumper installed
Pins 2 and 3 jumpered (with PMAC(1)-PC base board only)
Pins 1 and 2 jumpered (when used on all other base boards)
No E4 jumper installed; E5 and E6 jump pin 1 to 2
E4

E7: Firmware Reload Enable

E Point and
Physical Layout
E7
Jump pin 1 to 2 to reload firmware through serial or bus port.
Remove jumper for normal operation.
Flex CPU Board Jumper Descriptions 11
Description Default
No jumper installed
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Flex CPU Piggyback Board Hardware Reference

E10A, B, C: Flash Memory Bank Select

E Point and
Physical Layout
E10A
E10C
Description Default
Remove all 3 jumpers to select flash memory bank with factory-installed firmware.
Use other configuration to select one of the 7 other flash memory banks
No jumpers installed
12 Flex CPU Board Jumper Descriptions
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Flex CPU Piggyback Board Hardware Reference
CONNECTOR SUMMARY
J2: JEXP Expansion Port (50-pin IDC header for Delta Tau accessory boards) J5: JTAG/OnCE Port (for factory use only) J6: JSIO Port (for factory use only) J7: JISP Port (for factory use only) J8: Auxiliary Serial Port (10-pin IDC header)* P1: Stack Connector (Internal connections to main PMAC board) P3: Stack Connector (Internal connections to main PMAC board)
*Pinout shown in next section
Connector Summary 13
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Flex CPU Piggyback Board Hardware Reference
14 Connector Summary
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Flex CPU Piggyback Board Hardware Reference
CONNECTOR PINOUTS

J8 JRS232 (10-Pin Connector)

Front View
Pin # Symbol Function Description Notes
1 N.C. No Connect 2 DTR Bidirect Data Terminal Ready Tied to DSR 3 TXD/ Input Receive Data Host transmit data 4 CTS Input Clear to Send Host ready bit 5 RXD/ Output Send Data Host receive data 6 RTS Output Request to Send PMAC ready bit 7 DSR Bidirect Data Set Ready Tied to DTR 8 N.C. No Connect 9 GND Common PMAC Common
10 +5V Output +5VDC Supply Power supply out The JRS232 connector provided with Option 9T on a Turbo PMAC is an auxiliary serial port that can be used independently of the standard main serial port and other communications ports. It can be connected with a straight-across flat cable to a DB-9 connector with the standard RS-232 pinout.
Connector Pinouts 15
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POSSESSION OF THIS DOCUMENT INDICATES ACCEPTANCE OF THE ABOVE AGREEMENT.
ABOVE AGREEMENT.
D D
J5
(JTAG/OnCE)
J5
TSI
1
GND
2
TSO
3
GND
4
TCK
5
GND
6
N.C.
7
RST-
9
TMS
10
+3.3V
11
N.C.
12
DE-
13
TRST-
14
HEADER14_NO8
CTS­RTS-
INIT-
N.C.
(.100 MOLEX) JUMP `J6' PIN 6 TO 7 TO LOAD `isp' PART
C C
+3.3V
BSCAN-
B B
GUARD BAND
GND
A A
GND
J6
(jsio)
J6
+5V
1
TXD
2
RXD
3 4 5 6
GND
7 8
HEA_SIP 8
J7
(jisp)
J7
1
TDO
2
TDI
3 4
TMS
6
GND
7
TCK
8
HSIP8NO5
GND
PRAMCS-
DRAMCS-
FLASHCS-
+3P3V
1
3
C85
C83
C84
.1UF
.1UF
.1UF
E2 1-to-2 is for DPR on base board E2 2-to-3 is for DPR on expansion board
8
10UF
(TANT)
+3P3V
12
RP1
3.3KSIP10C
3456789 10
RP1_9 D1 SC02
PRDY D3 SIRQ-
PRDY
TDI
TDO
TCK
RESET-
TMS A2 BA02 SRD0 BHA0 D8 D16
DE- A4 BA04 BB- MODD/IRQD- D11 D19
TRST-
+5V
TXD A13 BA13 BSCK1 D23 RXD BRCLK A0 CTS- A14 BA14 PHA_A A1 RTS- A15 BA15 SER_A A2
INIT- BCTS- A3
+3P3V
RD- BA06 BA06_A RD­FLASHCS- BA07 BA07_A WR­BSCAN-
PRAMCS-
WR- BA11 BA11_A
C21
.01UF
H0 BH0 SC01 H1 BH1 SIRQ­H2 BH2 BTXD H3 BH3 BSC11 H4 BH4 H5 BH5 Vbat H6 BH6 H7 BH7 HR/W BHR/W HDS- BHDS­A3 LA12 A4 LA13 Vout A5 PA16 A6 PA17 A7 PA18 A8 PA19 A9 PA20 A10 PA21 A11 A12 BBRCS­A13 BBRAMCS­A14 IOCS_A- BBRAMCS­A15 IOCS_B­A16 TRST­A17 RD- 19.6608Mhz WR­PRAMCS- CS0­DRAMCS- CS1­FLASHCS­CPUCLK CS2­SEL CS3­RESET- BSTD1 STD1 BSCAN- CS4- BSRD1 SRD1
2
E2
C86
.1UF
U6
86
H0
17
H1
29
H2
33
H3
55
H4
46
H5
57
H6
70
H7
59
HRW
31
HDS-
80
A3
56
A4
3
A5
71
A6
73
A7
8
A8
4
A9
79
A10
90
A11
6
A12
84
A13
9
A14
82
A15
78
A16
54
A17
39
RD-/TDO
60
WR-/TCK
37
PRAMCS-/TMS
20
DRAMCS-
16
PROMCS-/TDI
11
CPUCLK/Y0
7
SEL
15
RESET-
14
BSCAN-
66
GOE0
87
GOE1
65
Y1
62
Y2
10
N.C.
26
N.C.
1
VCCIO
24
VCCIO
52
VCCIO
75
VCCIO
27
N.C.
49
N.C.
2
GND
13
GND
25
GND
38 51
GND GND
ISPLSI2064E_DECODE (TSOP100)
GND
BHRW BHDS-
VMECS­DPRCS-
BBRCS-
IOCS0­IOCS1-
CS00­CS04­CS06­CS10­CS12­CS14­CS16-
BRCLK
WDTC
LA12 LA13 PA16 PA17 PA18 PA19 PA20 PA21
+3P3V
C22
.1UF
+3P3V
C23
.1UF
+3P3V
C24
.1UF
+3P3V
C25
.1UF
+5V
85
BH0
68
BH1
36
BH2
23
BH3
18
BH4
53
BH5
44
BH6
21
BH7
81 83 5 92 91 98 94 95 96 97 69 34 72 35 30 64
VCC
12
VCC
100
N.C.
99
N.C.
43
CS0-
40
CS1-
28
CS2-
19
CS3-
22
CS4-
89
N.C.
C105
77
N.C.
76
N.C.
.1UF
61
N.C.
32 58 47 45 48 42 41 93 67 50
N.C.
88
GND
74
GND
63
GND
GND
10UF
16V
(TANT)
48
A0 BA00 BHREQ- BH5 D5 D13
47
A1 BA01 DE- BH6 D6 D14
46 45 44
A3 BA03 STD0 BHA1 D9 D17
43 42 41
A5 BA05 BHDS- D12 D20
40 39
A6 BA06 BHACK- D14 D22
38
A7 BA07 BRTS- BHREQ- D15 D23
37
A8 BA08 TMS BRXD D16
36
A9 BA09 BG- BTXD D17
35 34
A10 BA10 BSTD1 STD0 D19
33
A11 BA11 BSRD1 BOOTEN- D20
32 31
A12 BA12 BSC12 SCK0 D22
30 29 28 27 26
48
CPUCLK EXTAL A9
47
HACK- BHACK- A10
46 45
A19X/YP BX/Y A12
44
WR- BWR- A13
43 42
RD- BRD- A15
41
BA05 BA05_A A16 WDTC
40 39 38 37
BA08 BA08_A
36
BA09 BA09_A BB-
35 34
BA10 BA10_A
33 32 31
BA12 BA12_A
30
BA13 BA13_A
29 28
BA14 BA14_A
27
BA15 BA15_A
26
LA12 LA13 PA16 PA17 PA18 PA19 PA20
IOCS_A­IOCS_B-
BRCLK
PRAM MEMORY P:
$000000-$00FFFF Firmware (64K)
$040000-$0403FF User Written Phase (1K)
$040400-$040BFF User Written Servo (2K)
$050000-$05FFFF Plcc Standard Memory Option (64K)
$050000-$0BFFFF Plcc Extended Memory Option (448K)
8
7
OR
OR
T/R1
B0 B1
GND
B2 B3
VCC
B4 B5
GND
B6 B7 B8 B9
GND
B10 B11
VCC
B12 B13
GND
B14 B15
T/R2
T/R1
B0 B1
GND
B2 B3
VCC
B4 B5
GND
B6 B7 B8 B9
GND
B10 B11
VCC
B12 B13
GND
B14 B15
T/R2
VR2 LM1117MPX-1.8 MC33269ST-1.8 3
IN
NOTE2:
VR1
LM1117MPX-3.3 MC33269ST-3.3
3
IN
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 2425
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 2425
C100
.1UF
RP1_9
7
OUT
GND
(SOT-223) 1
OUT
GND
(SOT-223) 1
2
2
GUARD BANDGUARD BAND
C101
.1UF
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26
PI74FCT16245ATA
+5V VCCQL
C89
+
16V
GND
+5V +3P3V
C37
+
GND
U7
OE1 A0 A1 GND A2 A3 VCC A4 A5 GND A6 A7 A8 A9 GND A10 A11 VCC A12 A13 GND A14 A15 OE2
74LCX16245 (TSSOP48) U8
OE1 A0 A1 GND A2 A3 VCC A4 A5 GND A6 A7 A8 A9 GND A10 A11 VCC A12 A13 GND A14 A15 OE2
74LCX16245 (TSSOP48)
*NETLIST CHANGE* *NETLIST CHANGE*
NOTE1:
C90
+
*
16V
NOTE2:
GND
C38
+
10UF 16V
(TANT)
(Request 6pf load capacitance)
(See layout instructions)
+3P3V
+3P3V
C29
.1UF
+3P3V
C28
.1UF
+3P3V
+3P3V
+3P3V
C27
.1UF
+3P3V
C26
.1UF
+3P3V
GND
Memory Range
P:$D00000-$D3FFFF (MAXIMUM OF 16 BANKS) X/Y:$050000-$053FFF STANDARD MEMORY OPTION (16K) X/Y:$050000-$05FFFF EXTENDED MEMORY OPTION (64K)
C102
.1UF
C103
.1UF
1 2
B0
3
B1
4 5
B2
6
B3
7 8
B4
9
B5
10 11
B6
12
B7
13
B8
14
B9
15 16
B10
17
B11
18 19
B12
20
B13
21 22
B14
23
B15
2425
GNDGND
BA00 BA01
BA02 BA03
BA04 BA05
BA06 BA07 BA08 BA09
BA10 BA11
BA12 BA13
BA14 BA15
BX/Y BWR-
BRD­BA05_A
BA06_A BA07_A BA08_A BA09_A
BA10_A BA11_A
BA12_A BA13_A
BA14_A BA15_A
GND
+5V
T/R1
GND
VCC
GND
GND
VCC
GND
T/R2
(TANT)
U25
OE1 A0 A1 GND A2 A3 VCC A4 A5 GND A6 A7 A8 A9 GND A10 A11 VCC A12 A13 GND A14 A15 OE2
(TSSOP48)
10UF
6
INSTALL `F2' ONLY FOR `DSP56303PW80'
DO NOT INSTALL
`VR1,C89,C90,R11,R12'
FOR `DSP56303PW80'
INSTALL
`VR1,C89,C90,R11,R12'
FOR `DSP56309PW80' AND `DSP56311GC150' DO NOT INSTALL `F2'
Y3
C-002RX
32.768Khz
Vbat D0 SCK0
RP3
1 2
10KSIP10C
RP6
1 2
10KSIP10C
*NETLIST CHANGE* ********
GUARD BAND
U5
6
GND
X2
5
DATA
X1
VDDVBAT
DS2415P (TSOC)
SC02 BH4 D4 D12 3 4
*NETLIST CHANGE*
5
********
6 7
SCK0 BHA2 D10 D18
8 910
3 4
T/R- SRD0 D18
5 6 7
BSCK1 BRTS- D21
8 910
GUARD BAND
55FZ103N
VCCQL
F1
C41
.1UF
GND
**POLY CAP**
MODA/IRQA­MODB/IRQB­MODC/IRQC­BOOTEN-
X/Y:$078000-$0780FF
CS0-
X/Y:$078100-$0781FF
CS1-
X/Y:$078200-$0782FF
CS2-
X/Y:$078300-$0783FF
CS3-
X/Y:$078400-$0787FF
CS4-
CS00- BSCK1 SCK1
CS04- BSC11 SC11 CS06- WAIT1- BTXD TXD CS10- TA- BRTS- RTS­CS12- WAIT2- BHREQ- HREQ-
CS14­CS16-
VMECS­DPRCS-
WDTC
X/Y:$078800-$0789FF
CS00-
X/Y:$078A00-$078AFF
CS04-
X/Y:$078B00-$078BFF
CS06-
X/Y:$078C00-$078CFF
CS10-
X/Y:$078D00-$078DFF
CS12-
X/Y:$078E00-$078EFF
CS14-
X/Y:$078F00-$078FFF
CS16-
X/Y:$078F00-$078FFF X/Y:$060000-$060FFF STANDARD MEMORY OPTION (4K)
VMECS-
X/Y:$060000-$063FFF EXTENDED MEMORY OPTION (16K)
DPRCS-
X/Y:$060000-$06FFFF EXTENDED MEMORY OPTION (64K) X/Y:$070000-$077FFF
6
RESET- A5
*NETLIST CHANGE*
PINIT TRST- A7 MODD/IRQD- A8 MODC/IRQC- A9 MODB/IRQB- A10 MODA/IRQA- A11 DE- A12 TA- A13 TMS A14 TCK A15 TDO A16 TDI A17 BSC12 A19X/YP BSC11 WR­BSTD1 RD­BSRD1 SC02 STD0
1
SC01 SRD0
2 34
C104
.1UF
BH0 D0 D8
GND
BH1 D1 D9 BH2 D2 D10 BH3 D3 D11
BH7 D7 D15
BHR/W D13 D21
BG- A4 A19X/YP A5 FLASHCS- A6 DRAMCS- A7 INIT­PRAMCS- A8
EXTAL A11
C43
C42
.001
POLY
(0805)
.47UF
TP1 GND
E4
E4
2 1
E5
E5
2 1
E6
E6
2 1
E7
E7
2 1
GND
RP2
12 3 4 5 6 7 8 9 10
3.3KSIP10C
+3P3V
D2C1B1C2A2B2B3A4C3
SC01
SC02
H0 H1 H2 H3 H4 H5 H6 H7 HA0 HA1 HA2 HCS­HDS­HRW HACK­HREQ­RXD TXD SRD0 STD0 SC00 SC10 SCK0 SCK1 SCLK TIO0 TIO1 TIO2 BG­AA0 AA1 AA2 AA3 CAS­XTAL EXTAL CLKOUT BCLK BCLK­VCCP PCAP GNDP GNDP1 GND GND GND GND GND GND GND GND
GND
GND
GND
E4
E5E6E7E8E9
GND
10
12
13
SRD1
GND
1
2
4
5
9
M5
P4
N4
P3
N3
P2 N1 N2 M3 M1 M2
L1
J3
J2
J1
K2
F1 G3
E3
E1
F3
F2 H3 G1 G2
L3
L2
K3
P13 N13 P12
P7 N7 N8
P8 M8 M9
N10 M10
M6
P5 N6
P6 D4 D5 D6 D7 D8 D9
D10 D11
X/Y:$000000 -$0107FF ST ANDARD MEMORY OPTION (64K) X/Y:$000000 -$03FFFF EX TENDED MEMORY OPTION (256K)
IOCS_A- H6 SC12
BWR- H4
BRD-
IOCS_B- BHA1 HA1
BWR- MODD/IRQD- IRQB-
BRD-
5
P10A3D3C4A5C5B5
TA
DE
TDI
TCK
TMS
TDO
SC11
SC12
STD1
GND
GND
GND
GND
GND
GND
GND
GND
GND
E10
E11F4F5F6F7F8F9
C33
Y1A
.1UF
1
N.C.
VCC
2 3
GND CLK
MHR13FAJ19.6608
(4 PIN SMT)
Y1B
1
N.C.
VCC
4
GND
CLK
7 8
GND CLK
19.6608MHz
(DIP14WIDE)
C20
+5V
.1UF
U24A
3
74ACT32 (SO14)
U24B
6
74ACT32 (SO14)
U24C
8
74ACT32 (SO14)
U24D
11
74ACT32 (SO14)
5
4
+3P3V
C10
C8
C7
C9
.1UF
.1UF
.1UF
N9H2G13C7P14P9N12
L12
K12
H12
D14
N5D1B4
PINT
IRQA
IRQB
IRQC
IRQD
TRST
RESET
GND
GND
GND
GND
GND
GND
GND
GND
GND
F10
F11G4G5G6G7G8G9
P:$000000-$0FFFFF
+5V
*DUAL FOOTPRINT*
4
CPUCLK
14
11
WAIT2-
BWR_A- H5 SC11
BRD_A-
BWR_B- BHA0 HA0
BRD_B-
DSP56311GC150
GND
GND
GND
G10
G11H4H5H6H7H8H9
13 12
BWR_A-
BRD_A-
BWR_B-
BRD_B-
GND
GND
GND
U4F
74ACT14
M4
N.C.
N.C.
VCCH
U1
GND
GND
GND
GUARD BAND
(SO14)
NC7SZ00
(SOT23-5)
VCCS
GND
H10
1
2
C11C9A7
B14M7H1
F12
A14K1E2P1A1
N.C.
N.C.
VCCS
VCCD
VCCQH
VCCQH
VCCQH
GND
GND
GND
GND
GND
GND
GND
H11J4J5J6J7J8J9
J10
GUARD BAND
R1
10
+3P3V
C40
53
U9
.1UF
GND
BRXD RXD BPHA BCTS- CTS­SER_A BSER PHA_A BPHA BHA2 HA2
T/R­RESET
VCCA
VCCA
VCCD
VCCD
VCCD
GND
GND
GND
GND
GND
J11K4K5K6K7K8K9
4
12
RP4
3456789 10
VCCA
GND
VCCC
GND
VCCC
GND
N.C.
GND
K10
VCCQL
VCCQL
GND
GND
K11L4L5
3.3KSIP10C
VCCQL
VCCQL
GND
GND
L6
19.6608Mhz
U27
2
A0
3
A1
4
A2
5
A3
6
A4
7
A5
8
A6
9
A7
1
T/R
19
OE
74LCX245
(TSSOP20)
4
WR-
GND GND GND GND GND
C12
C11
.1UF
.1UF
C3
.1UF
.1UF
E14
D0
D12
D1
D13
D2
C13
D3
C14
D4
B13
D5
C12
D6
A13
D7
B12
D8
A12
D9
B11
D10
A11
D11
C10
D12
B10
D13
A10
D14
B9
D15
A9
D16
B8
D17
C8
D18
A8
D19
B7
D20
B6
D21
C6
D22
A6
D23
N14
A0
M13
A1
M14
A2
L13
A3
L14
A4
K13
A5
K14
A6
J13
A7
J12
A8
J14
A9
H13
A10
H14
A11
G14
A12
G12
A13
F13
A14
F14
A15
E13
A16
E12
A17
M12
RD-
M11 N11
BR-
P11
BB-
L11 L10 L9 L8 L7
GNDGND
B0 B1 B2 B3 B4 B5 B6 B7
VCC GND
C14
C13
.1UF
.1UF
.1UF
C5
C4
.1UF
.1UF
+3P3V
18 17 16 15 14 13 12 11
20 10
C87
.1UF
GND
F2
C6
GND
A14
A17
NOTE1:
55FZ103N
VCCQL
+3P3V
BT1
R7
100
RESET- RESET_A WDO
+
3.6V BAT
D6
1 3
MMBD301LT1
.01FARAD FM0H103Z
U26C
5 6
74ACT14 (SO14)
12
3
A0 A1 A2 A3 A4
A6
D2
D4 D5 D6 D7
56
RP5C
1KSIP6I
E1
Vout
1 3
MMBD301LT1
NEC
INIT- 19.6608Mhz
HA2 HA1 HA0 TXD HR/W HDS- STD1 HREQ- SRD1 H7 SCK1
H3 H2 H1 H0
WAIT2-
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17
A19X/YP
WR­RD-
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23
R2
10K
E1
D5
C17
U4A
1 2
C1
74ACT14
.1UF
(SO14)
GND
C35
1 2
1KSIP6I
.01UF
1
23
Q1
MMBT3906LT1
(SOT23)
21
3
C16
.1UF
R4 100K
MMBT3906LT1
(SOT23)
12
RP7
3.3KSIP10C
3456789 10
GND
C34
+
1UF 35V tant
Q3
1
23
VSP01VT18A01
TP2
SIRQ-
C36
.1UF
RP5A
U2
1
VOUT
2 7
VCC RST
3
ON
4 5
GND CEI
MAX795SCSA
(SO8)
P1
P1
12 34 56 78 910 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
D7
1SMC5.0AT3
R3
1K
+5VGND
U4B
3 4
74ACT14
3 4
1KSIP6I
U3
1
N.C.
2
IN
3
N.C.
4
MODE
5
N.C.
6
TOL
7
N.C.
8
GND
DS1231S (SOL16)
1 3
MMBD301LT1
*NETLIST CHANGE*
GND
(SO14)
RP5B
D3
1 3
MMBD301LT1
D4
BATT
CEO
********
+5V
12
1 2 3 4 5 6 7 8 9
SOT23
2N7002
(SOT23)
16
N.C.
15
VCC
14
N.C.
13
NMI
12
N.C.
11
RST
10
N.C.
9
RST
.1UF
8
6
C15
.1UF
3456789 10
U26A
1 2
74ACT14 (SO14)
U26F
13 12
74ACT14 (SO14)
C32
U28
DIN DOUT SCLK CS N.C. IRQ SHDN GND X2
MAX3100CEE (QSOP)
ECS-36-20-5P
3.6864Mhz
Q4
3
+5V
C2
RP8
3.3KSIP10C
9 8
12
.1UF
VCC
SOT23
U26D
74ACT14 (SO14)
TX
RX RTS N.C. CTS
X1
3
GND
HACK­RXD
CTS-
IRQB-
CS4­WAIT1-
11 10
16 15 14 13 12 11 10
12
3 4
2
Y2
C70
22pf
GUARD BANDING REQ'D
U4C
5 6
12
74ACT14
Q5
3
2N7002
SOT23
(SOT23)
U4D
9 8
74ACT14
U4E
11 10
74ACT14
Q2 2N7002
(SOT23)
GUARD BANDING REQ'D
U26B
74ACT14 (SO14)
U26E
74ACT14 (SO14)
2
NOTE:
THIS PART MUST BE `MAX3232ECWE'
TO PROVIDE `ESD' PROTECTION
OF THE `RS232' INPUT SECTION.
C76
C72
.1UF
2
C73
1
.1UF
3
11
12
10
9
MAX3232ECWE
(SOL16)
D2 LED GRN
R5 1K
BSC12 SC12
BPHA
C82
GND
.1UF
BSER
RESET_B
|Link |605-1sh2.sch
.1UF
U29
+V
C1+
C1-
TXD
RXD
RTS
CTS
D2A LED GRN
PWR WD
R5A 1K
U30
2
A0
3
A1
4
A2
5
A3
6
A4
7
A5
8
A6
9
A7
1
T/R
19
OE
PI74FCT245TL
(TSSOP20)
16
VCC
TXD
RXD
RTS
CTS
VSS
15
1K
+5V
GND
C74
.1UF
6
V-
C75
4
C2+
.1UF
5
C2-
14
13
7
8
RESET
WDO
D1A
D1
LED
LED
RED
RED
WDPWR
R6A
R6
1K
RESET-
RP9A
330SIP8I
18
1 2
B0
3 4
17
B1
5 6
16
B2
15
7 8
B3
14
B4
13
B5
12
B6
11
B7
20
VCC
10
GND
Title
Size Document Number Rev
D
Date: Sheet
C88
.1UF
Delta Tau Data Systems, Inc.
DSP563XX CPU Piggyback Board
603605-322P
(SO14)
(SO14)
(SO14)
+5V
BSER
RESET_B
+3P3V
C71
22pf
R8
330
1
RESET-PA21
BBRCS-
1
+5V
J8
J8
1 2 3 4 5 6 7 8 9 10
HEADER 10
(BOX)
12Thursday, September 19, 2002
(JRS232)
N.C. DTR TXD­CTS RXD­RTS DSR N.C. GND +5V
of
-
Page 21
8
THIS DOCUMENT IS THE CONFIDENTIAL PROPERTY OF DELTA TAU
THIS DOCUMENT IS THE CONFIDENTIAL PROPERTY OF DELTA TAU DATA SYSTEMS INC. AND IS LOANED SUBJECT TO RETURN UPON
DATA SYSTEMS INC. AND IS LOANED SUBJECT TO RETURN UPON DEMAND. TITLE TO THIS DOCUMENT IS NEVER SOLD OR
DEMAND. TITLE TO THIS DOCUMENT IS NEVER SOLD OR TRANSFERRED FOR ANY REASON. THIS DOCUMENT IS TO BE USED
TRANSFERRED FOR ANY REASON. THIS DOCUMENT IS TO BE USED ONLY PURSUANT TO WRITTEN LICENSE OR WRITTEN INSTRUCTIONS
ONLY PURSUANT TO WRITTEN LICENSE OR WRITTEN INSTRUCTIONS OF DELTA TAU DATA SYSTEMS INC. ALL RIGHTS TO DESIGNS AND
OF DELTA TAU DATA SYSTEMS INC. ALL RIGHTS TO DESIGNS AND INVENTIONS ARE RESERVED BY DELTA TAU DATA SYSTEMS INC.
INVENTIONS ARE RESERVED BY DELTA TAU DATA SYSTEMS INC. POSSESSION OF THIS DOCUMENT INDICATES ACCEPTANCE OF THE
POSSESSION OF THIS DOCUMENT INDICATES ACCEPTANCE OF THE ABOVE AGREEMENT.
ABOVE AGREEMENT.
D D
"E10" FLASH BANK SELECT
+3p3V
E10A
E10B
E10C
*NETLIST CHANGE*
FLASHCS-
PA21 PA20 PA19
C C
+5V
B B
A A
PA18 PA17 PA16
RESET-
W1
SOLDER JUMPER
1
2
W1
3
IOCS_A- IOCS_B-
+3P3V
C45
.1UF
+3P3V
C46
.1UF
+3P3V
C47
.1UF
+3P3V
C48
.1UF
LA12 LA13
*NETLIST CHANGE*
FLASHCS- BWR- D21 A19X/YP D8 A0 D8 BX/Y D8
PA21 BRD- D22 PA20 PRDY D23 PA19 PA18 D7 PA17 PA16 D6 BA00 RD- RD-
+3P3V/+5V BA01 WR- WR-
BA15 BA02 A17 A19X/YP BA14 D5 BA03 A16 A17 BA13 BA04 A15 A16 BA15 BA12 D4 BA05 A14 A15 BA14 BBRCS-
RESET- BA08 A11 A12 BA11 BA11 D3 BA09 A10 A11 BA10 BA10 BA10 A9 A10 BA09 BA09 D2 BA11 A8 A9 BA08 BA08 +3P3V/+5V BA12 A7 A8 BA07
BA07 D1 BA14 A5 D6 A6 D6 BA05 D6 BA06 BA15 A4 D5 A5 D5 BA04 D5 BA05 D0 BX/Y A3 D4 A4 D4 BA03 D4 BA04 BA00 A2 D3 A3 D3 BA02 D3 BA03 A1 D2 A2 D2 BA01 D2 BA02 A0 D1 A1 D1 BA00 D1 BA01 A19X/YP D0 A0 D0 BX/Y D0
C77
.1UF
IOCS_A- BRD- IOCS_B- BRD-
8
C78
.1UF
`W1'= 1 TO 2 FOR 28F320J3A `W1'= 2 TO 3 FOR 28F320J5A
U20
48 D0 BD00_A D0 BD00_B D1 BD01_A D1 BD01_B
D2 BD02_A D2 BD02_B D3 BD03_A D3 BD03_B
D4 BD04_A D4 BD04_B D5 BD05_A D5 BD05_B
D6 BD06_A D6 BD06_B BD00_A BD01_A D7 BD07_A D7 BD07_B BD02_A BD03_A D8 BD08_A D8 BD08_B BD04_A BD05_A D9 BD09_A D9 BD09_B BD06_A BD07_A
D10 BD10_A D10 BD10_B BD10_A BD11_A D11 BD11_A D11 BD11_B BD12_A BD13_A
D12 BD12_A D12 BD12_B BD16_A BD17_A D13 BD13_A D13 BD13_B BD18_A BD19_A
D14 BD14_A D14 BD14_B BD22_A BD23_A D15 BD15_A D15 BD15_B
D16 BD16_A D16 BD16_B BD12_B BD13_B BA14_A BA15_A D17 BD17_A D17 BD17_B BD14_B BD15_B BA04_A BA05_A
D18 BD18_A D18 BD18_B BD18_B BD19_B BA08_A BA09_A D19 BD19_A D19 BD19_B BD20_B BD21_B BA10_A BA11_A
D20 BD20_A D20 BD20_B D21 BD21_A D21 BD21_B BA00_B BA01_B
D22 BD22_A D22 BD22_B BA04_B BX/Y_B D23 BD23_A D23 BD23_B CS2- CS3­BA00 BA00_A BA00 BA00_B CS04- CS06­BA01 BA01_A BA01 BA01_B CS10- CS12-
BA02 BA02_A BA02 BA02_B BA12_B BA13_B BA03 BA03_A BA03 BA03_B BWR_B- BRD_B-
BA04 BA04_A BA04 BA04_B RESET_B WAIT2­BX/Y BX/Y_A BX/Y BX/Y_B SER_B PHA_B
LA12 BA12_B BPHA PHA_B LA13 BA13_B BSER SER_B
OE1
47
A0
46
A1
45
GND
44
A2
43
A3
42
VCCA
41
A4
40
A5
39
GND
38
A6
37
A7
36
A8
35
A9
34
GND
33
A10
32
A11
31
VCCA
30
A12
29
A13
28
GND
27
A14
26
A15 OE2
IDT74FCT164245TPA
(TSSOP48) U21
48
OE1
47
A0
46
A1
45
GND
44
A2
43
A3
42
VCCA
41
A4
40
A5
39
GND
38
A6
37
A7
36
A8
35
A9
34
GND
33
A10
32
A11
31
VCCA
30
A12
29
A13
28
GND
27
A14
26
A15 OE2
IDT74FCT164245TPA
(TSSOP48)
U10
1
A22
2
CE1-
3
A21
4
A20
5
A19
6
A18
7
A17
8
A16
9
VCC
10
A15
11
A14
12
A13
13
A12
14
CE0
15
VPEN
16
RP-
17
A11
18
A10
19
A09
20
A08
21
GND
22
A07
23
A06
24
A05
25
A04
26
A03
27
A02
28 29
A01 CE2
GND GND
T/R1
B0 B1
GND
B2 B3
VCCB
B4 B5
GND
B6 B7 B8 B9
GND
B10 B11
VCCB
B12 B13
GND
B14 B15
T/R2
T/R1
B0 B1
GND
B2 B3
VCCB
B4 B5
GND
B6 B7 B8 B9
GND
B10 B11
VCCB
B12 B13
GND
B14 B15
T/R2
7
R15
R16
3.3K
A24_WP
WE-
OE-
STS
DQ15
DQ7
DQ14
DQ6
GND
DQ13
DQ5
DQ12
DQ4
VCCQ
GND
DQ11
DQ3
DQ10
DQ2 VCC DQ9 DQ1 DQ8 DQ0
A00
BYTE-
A23
7
3.3K
56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30
R17
+5V
+5V
+5V
+5V
+5V
.1UF
.1UF
.1UF
.1UF
C52
C51
C50
C49
BWR­BRD­PRDY
C79
.1UF
GNDGND
3.3K
21
21
21
E28F320J3A
(TSOP56)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
BRD- BRD- BD00_B BD01_B BA00_A BA01_A
2425
BRD- BRD- BD10_B BD11_B BA13_A
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 2425
BPHA BSER
6
RD-
WR-
A0 A14 A15 BA14 BBRCS-
A0
A1 A13 A14 BA13 BRD-
A1
A2 A12 A13 BA12 BWR-
A2
A3 A11 A12 BA11
A3
A4 A10 A11 BA10
A4
A5 A9 A10 BA09
A5
A6 A8 A9 BA08
A6
A7 A7 A8 BA07
A7
A8 A6 D23 A7 D23 BA06 D23
A8
A9 A5 D22 A6 D22 BA05 D22
A9
A10 A4 D21 A5 D21 BA04 D21
A10
A11 A3 D20 A4 D20 BA03 D20
A11
A12 A2 D19 A3 D19 BA02 D19
A12
A13 A1 D18 A2 D18 BA01 D18
A13
A14 A0 D17 A1 D17 BA00 D17
A14
A15 A19X/YP D16 A0 D16 BX/Y D16
A15
A16
A16
A17
A17
6
A19X/YP
D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23
BA00 BA01 BA02 BA03 BA04 BA05 BA06 BA07 BA08 BA09 BA10 BA11 BA12 BA13 BA14 BA15 BX/Y
A19X/YP
D0
D0
D1 RD- RD-
D1
D2 WR- WR-
D2
D3 A17 A19X/YP
D3
D4 A16 A17
D4
D5 A15 A16 BA15
D5
D6 A14 A15 BA14 BBRCS-
D6
D7 A13 A14 BA13 BRD-
D7
D8 A12 A13 BA12 BWR-
D8
D9 A11 A12 BA11
D9
D10 A10 A11 BA10 D11 A9 A10 BA09 D12 A8 A9 BA08 D13 A7 A8 BA07 D14 A6 D15 A7 D15 BA06 D15 D15 A5 D14 A6 D14 BA05 D14 D16 A4 D13 A5 D13 BA04 D13 D17 A3 D12 A4 D12 BA03 D12 D18 A2 D11 A3 D11 BA02 D11 D19 A1 D10 A2 D10 BA01 D10 D20 A0 D9 A1 D9 BA00 D9
BA06 A13 A14 BA13 BRD­BA07 A12 A13 BA12 BWR-
BA13 A6 D7 A7 D7 BA06 D7
+3P3V +5V
U22
OE2
26
A15
27
A14
28
GND
29
A13
30
A12
31
VCCA
32
A11
33
A10
34
GND
35
A9
36
A8
37
A7
38
A6
39
GND
40
A5
41
A4
42
VCCA
43
A3
44
A2
45
GND
46
A1
47
A0
48
OE1
IDT74FCT164245TPA
(TSSOP48) U23
OE2
26
A15
27
A14
28
GND
29
A13
30
A12
31
VCCA
32
A11
33
A10
34
GND
35
A9
36
A8
37
A7
38
A6
39
GND
40
A5
41
A4
42
VCCA
43
A3
44
A2
45
GND
46
A1
47
A0
48
OE1
IDT74FCT164245TPA
(TSSOP48)
T/R2
B15 B14
GND
B13 B12
VCCB
B11 B10
GND
GND
VCCB
GND
T/R1
T/R2
B15 B14
GND
B13 B12
VCCB
B11 B10
GND
GND
VCCB
GND
T/R1
B9 B8 B7 B6
B5 B4
B3 B2
B1 B0
B9 B8 B7 B6
B5 B4
B3 B2
B1 B0
5
U11
(400MIL)
6 RD- RD­WR- WR­A17 A19X/YP A16 A17 A15 A16 BA15
2425 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
2425 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
GNDGND
CE
31
OE
13
WE
18
A18
1
A17
35
A16
34
A15
33
A14
32
A13
24
A12
23
A11
22
A10
21
A9
20
A8
17
A7
16
A6
15
A5
14
A4
5
A3
4
A2
3
A1
2
A0
KM68V4002 (SOJ36) U12
6
CE
31
OE
13
WE
18
A18
1
A17
35
A16
34
A15
33
A14
32
A13
24
A12
23
A11
22
A10
21
A9
20
A8
17
A7
16
A6
15
A5
14
A4
5
A3
4
A2
3
A1
2
A0
KM68V4002 (SOJ36) U13
6
CE
31
OE
13
WE
18
A18
1
A17
35
A16
34
A15
33
A14
32
A13
24
A12
23
A11
22
A10
21
A9
20
A8
17
A7
16
A6
15
A5
14
A4
5
A3
4
A2
3
A1
2
A0
KM68V4002 (SOJ36)
5
(400MIL)
(400MIL)
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
9
GND
+3P3V
10
27
GND
+3P3V
28
30
D7
29
D6
26
D5
25
D4
12
D3
11
D2
8
D1
7
D0
9
GND
+3P3V
10
27
GND
+3P3V
28
30
D7
29
D6
26
D5
25
D4
12
D3
11
D2
8
D1
7
D0
9
GND
+3P3V
10
27
GND
+3P3V
28
30
D7
29
D6
26
D5
25
D4
12
D3
11
D2
8
D1
7
D0
CS2­CS04­CS10­CS14-
BWR_B-
RESET_B
C58
.1UF
C59
.1UF
C60
.1UF
C61
.1UF
C62
.1UF
C63
.1UF
4
U16
(400MIL)
6
CE
31
OE
13
WE
18
A18
1
A17
35
A16
34
A15
33
A14
32
A13
24
A12
23
A11
22
A10
21
A9
20
A8
17
A7
16
A6
15
A5
14
A4
5
A3
4
A2
3
A1
2
A0
KM68V4002 (SOJ36) U15
(400MIL)
6
CE
31
OE
13
WE
18
A18
1
A17
35
A16
34
A15
33
A14
32
A13
24
A12
23
A11
22
A10
21
A9
20
A8
17
A7
16
A6
15
A5
14
A4
5
A3
4
A2
3
A1
2
A0
KM68V4002 (SOJ36) U14
(400MIL)
6
CE
31
OE
13
WE
18
A18
1
A17
35
A16
34
A15
33
A14
32
A13
24
A12
23
A11
22
A10
21
A9
20
A8
17
A7
16
A6
15
A5
14
A4
5
A3
4
A2
3
A1
2
A0
KM68V4002 (SOJ36)
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
3
9
GND
C68
.1UF
+3P3V
10
27
GND
C69
.1UF
+3P3V
28
30
D7
29
D6
26
D5
25
D4
12
D3
11
D2
8
D1
7
D0
9
GND
C66
.1UF
+3P3V
10
27
GND
C67
.1UF
+3P3V
28
30
D7
29
D6
26
D5
25
D4
12
D3
11
D2
8
D1
7
D0
9
GND
C64
.1UF
+3P3V
10
27
GND
C65
.1UF
+3P3V
28
30
D7
29
D6
26
D5
25
D4
12
D3
11
D2
8
D1
7
D0
W2 JUMPER SELECTION
JUMPER 2-3 for Standard PMAC1 and PMAC2
JUMPER 1-2 for TURBO
SOLDER JUMPER
BA12_A
BA12_A
GND
J2
(JEXP)
J2
BD02_B BD03_B BA02_A BA03_A BD04_B BD05_B CS00- BX/Y_A BD06_B BD07_B CS0- CS1­BD08_B BD09_B BWR_A- BRD_A-
BD16_B BD17_B BA06_A BA07_A
BD22_B BD23_B DPRCS- VMECS-
BA02_B BA03_B
CS14- CS16-
4
12 34 56 78 910 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
HEADER 25X2
GND GND
3
1
3
CS3­CS06­CS12­CS16-
BRD_B-
WAIT2-
W2
2
CS00-
CS0-
BWR_A-
BA14_A
BA06_A BA08_A BA10_A
DPRCS-
|605-1sh2.sch
2
U17
1 16
N.C. VSS
2
A16
31
A15
3
A14
28
A13
4
A12
25
A11
23
A10
26
A9
27
A8
5
A7
6
A6
7
A5
8
A4
9
A3
10
A2
11
A1
12
A0
KM68V1000BL-70
(SOJ/SOP32)
U18
1 16
N.C. VSS
2
A16
31
A15
3
A14
28
A13
4
A12
25
A11
23
A10
26
A9
27
A8
5
A7
6
A6
7
A5
8
A4
9
A3
10
A2
11
A1
12
A0
KM68V1000BL-70
(SOJ/SOP32)
U19
1 16
N.C. VSS
2
A16
31
A15
3
A14
28
A13
4
A12
25
A11
23
A10
26
A9
27
A8
5
A7
6
A6
7
A5
8
A4
9
A3
10
A2
11
A1
12
A0
KM68V1000BL-70
(SOJ/SOP32)
VDD
DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0
VDD
DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0
VDD
DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0
30
CE
22
CE
24
OE
29
WE
32
21 20 19 18 17 15 14 13
30
CE
22
CE
24
OE
29
WE
32
21 20 19 18 17 15 14 13
30
CE
22
CE
24
OE
29
WE
32
21 20 19 18 17 15 14 13
ON SOLDER SIDE
P3
1 2
SPARE SPARE
3 4
SPARE SPARE
5 6
SPARE SPARE
7 8
P3-01 P3-02
9 10
P3-03 P3-04
11 12
P3-05 P3-06
13 14
BD08_A BD09_A
BD14_A BD15_A
BD20_A BD21_A
Title
Size Document Number Rev
Date: Sheet
2
P3-07 P3-08
15 16
P3-09 P3-10
17 18
P3-11 P3-12
19 20
P3-13 P3-14
21 22
P3-15 P3-16
23 24
P3-17 P3-18
25 26
P3-19 P3-20
27 28
P3-21 P3-22
29 30
P3-23 P3-24
31 32
P3-25 P3-26
33 34
P3-27 P3-28
35 36
P3-29 P3-30
37 38
P3-31 P3-32
39 40
P3-33 P3-34
41 42
P3-35 P3-36
43 44
BA12A BA13A
45 46
BA14A BA15A
47 48
J4-01 J4-02
49 50
J4-03 J4-04
51 52
J4-05 J4-06
53 54
J4-07 J4-08
55
J4-09
VSP01VT28A01
GND GND
DSP563XX CPU, MEMORY,I/O SECTION
C
603605-322P
C53
.1UF
GND
C54
.1UF
GND
C55
.1UF
GND
P3
J4-10
Delta Tau Data Systems, Inc.
Vout
Vout
Vout
1
BBRCS-
Vout
CS1­BRD_A­BA13_A BA15_A BA05_A BA07_A BA09_A
56
BA11_A VMECS-
-
of
22Thursday, September 19, 2002
1
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