Delta Tau PMAC MINI PCI, PMAC PCI, PMAC PCI LITE, PMAC VME, PMAC2 PCI Reference Manual

^1 HARDWARE REFERENCE MANUAL

^2 Flex CPU Piggyback Board

Single Source Machine Control Power // Flexibility // Ease of Use

21314 Lassen Street Chatsworth, CA 91311 // Tel. (818) 998-2095 Fax. (818) 998-7807 // www.deltatau.com

^3 CPU

^4 3xx-603605-xHxx

^5 December 8 2003

Copyright Information

unauthorized without written permission of Delta Tau Data Systems, Inc. Information contained in this manual may be updated from time-to-time due to product improvements, etc., and may not conform in every respect to former issues.

To report errors or inconsistencies, call or email:

Delta Tau Data Systems, Inc. Technical Support

Phone: (818) 717-5656 Fax: (818) 998-7807 Email: support@deltatau.com Website: http://www.deltatau.com

Operating Conditions

All Delta Tau Data Systems, Inc. motion controller products, accessories, and amplifiers contain static sensitive components that can be damaged by incorrect handling. When installing or handling Delta Tau Data Systems, Inc. products, avoid contact with highly insulated materials. Only qualified personnel should be allowed to handle this equipment.

In the case of industrial applications, we expect our products to be protected from hazardous or conductive materials and/or environments that could cause harm to the controller by damaging components or causing electrical shorts. When our products are used in an industrial environment, install them into an industrial electrical cabinet or industrial PC to protect them from excessive or corrosive moisture, abnormal ambient temperatures, and conductive materials. If Delta Tau Data Systems, Inc. products are directly exposed to hazardous or conductive materials and/or environments, we cannot guarantee their operation.

Flex CPU Piggyback Board Hardware Reference

Table of Contents

INTRODUCTION.......................................................................................................................................................1

BOARD CONFIGURATION.....................................................................................................................................3

Non-Turbo CPU Base Configuration...................................................................................................................3

Non-Turbo CPU Further Options.........................................................................................................................3

Turbo CPU Base Configuration...........................................................................................................................3

Turbo CPU Further Options.................................................................................................................................3

HARDWARE SETUP.................................................................................................................................................5

Flex CPU Board Jumper Configuration............................................................................................................... 5

Watchdog Timer Jumper.......................................................................................................................................5

Dual-Ported RAM Source Jumper........................................................................................................................5

Power-Up State Jumpers......................................................................................................................................5

Firmware Load Jumper........................................................................................................................................5

Flash Memory Bank Select Jumpers.....................................................................................................................5

Installation............................................................................................................................................................5

OPERATION OF THE FLEX CPU..........................................................................................................................7

Operation as Non-Turbo CPU..............................................................................................................................7

Operation as a Turbo CPU...................................................................................................................................9

FLEX CPU BOARD JUMPER DESCRIPTIONS..................................................................................................11

E1: Watchdog Disable Jumper...........................................................................................................................11

E2: Dual-Ported RAM Port Select......................................................................................................................11

E4 – E6: Power-Up/Reset Load Source..............................................................................................................11

E7: Firmware Reload Enable.............................................................................................................................11

E10A, B, C: Flash Memory Bank Select.............................................................................................................12

CONNECTOR SUMMARY.....................................................................................................................................13

CONNECTOR PINOUTS.........................................................................................................................................15

J8 JRS232 (10-Pin Connector)...........................................................................................................................15

SCHEMATICS

Table of Contents i

Flex CPU Piggyback Board Hardware Reference

ii Table of Contents

Flex CPU Piggyback Board Hardware Reference

INTRODUCTION

The Flex CPU piggyback board (Part # 300-603605-10x) for the PMAC/PMAC2 and Turbo PMAC/PMAC2 families of boards provides new high-end capabilities for these controllers and uses newer components with longer product lifetimes. It can be manufactured in a wide variety of configurations, and can be used in the following products:

• PMAC(1)-PC

• PMAC(1)-PCI

• PMAC(1)-VME

• PMAC2-PC

• PMAC2-PCI

• PMAC2-VME

• Turbo PMAC(1)-PC

• Turbo PMAC(1)-PCI

• Turbo PMAC(1)-VME

• Turbo PMAC2-PC

• Turbo PMAC2-PCI

• Turbo PMAC2-VME

On the regular (non-Turbo) PMAC(1) and PMAC2 boards, the Flex CPU is provided automatically when any of the following CPU options are ordered:

• Option 5AF: 40 MHz CPU with 128k x 24 internal SRAM

• Option 5CF: 80 MHz CPU with 128k x 24 internal SRAM

• Option 5EF: 160 MHz CPU with 128k x 24 internal SRAM

The Flex CPU board is not provided if Option 4x or 5x is not ordered, or if Option 4A, 5A, 5B, or 5C is ordered.

On Turbo PMAC(1) and Turbo PMAC2 boards, the Flex CPU may be provided when any of the following CPU options is ordered:

• Option 5C0: 80 MHz DSP56303 CPU with 8k x 24 internal SRAM, 256k x 24 external SRAM

• Option 5C3: 80 MHz DSP56303 CPU with 8k x 24 internal SRAM, 1M x 24 external SRAM

• Option 5D0: 100 MHz DSP56309 CPU with 34k x 24 internal SRAM, 256k x 24 external SRAM

• Option 5D3: 100 MHz DSP56309 CPU with 34k x 24 internal SRAM, 1M x 24 external SRAM

In these cases, however, the older Turbo only CPU piggyback board may also be provided. On Turbo PMAC(1) and Turbo PMAC2 boards, the Flex CPU will be provided automatically when either

of the following CPU options is ordered:

• Option 5E0: 160 MHz DSP56309 CPU with 128k x 24 internal SRAM, 256k x 24 external SRAM

• Option 5E3: 160 MHz DSP56309 CPU with 128k x 24 internal SRAM, 1M x 24 external SRAM

Introduction 1

Flex CPU Piggyback Board Hardware Reference

2 Introduction

Flex CPU Piggyback Board Hardware Reference

BOARD CONFIGURATION

Non-Turbo CPU Base Configuration

When assembled for a non-Turbo CPU, the DSP IC in U1 of the Flex CPU board contains all of the memory required for operation. Therefore, there are no ICs installed in the locations for external RAM: U11, U12, U13, U14, U15, and U16.

The CPU is available in several speed options: 40 MHz (Option 5AF), 80 MHz (Option 5CF), and 160 MHz (Option 5EF). The maximum frequency of operation is indicated with a sticker on the CPU in U1.

When the Flex CPU is built for ISA-bus or VME-bus baseboards, the P3 connector consists of a 36-pin header on the solder side for direct connection to the baseboard, and a 10-pin header on the component side for cable connection of the extra signals required for dual-ported RAM interface. When the Flex CPU is built for PCI-bus baseboards the P3 connector consists only of a 56-pin header on the solder side for direct connection of all signals to the baseboard.

Non-Turbo CPU Further Options

The Option 16 battery-backed parameter RAM provides a bank of non-volatile memory for the controller. Its key components are RAM ICs in U17, U18, and U19, and a battery in BT1

Turbo CPU Base Configuration

When assembled for a Turbo CPU section, the Flex CPU board contains external RAM ICs in locations U11, U12, U13, U14, U15, U16. With the standard memory configuration (Option 5x0), these ICs fill the smaller footprint in these locations, leaving an open pin on the board on each end of each side.

When the Flex CPU is built for ISA-bus or VME-bus baseboards, the P3 connector consists of a 36-pin header on the solder side for direct connection to the baseboard, and a 10-pin header on the component side for cable connection of the extra signals required for dual-ported RAM interface. When the Flex CPU is built for PCI-bus baseboards the P3 connector consists only of a 56-pin header on the solder side for direct connection of all signals to the baseboard.

Turbo CPU Further Options

If an expanded memory configuration (Option 5x3) is ordered, larger RAM ICs are installed in locations U11, U12, U13, U14, U15, U16, occupying the full footprints in these locations

If the Option 9T auxiliary serial port is ordered for the Turbo PMAC controller, an RS-232 serial port is provided on the CPU board to supplement the serial port on the baseboard. The key components are ICs in U28 and U29, and the connector J8.

The Option 16A battery-backed parameter RAM provides a bank of non-volatile memory for the controller. Its key components are RAM ICs in U17, U18, and U19, and a battery in BT1

Board Configuration 3

Flex CPU Piggyback Board Hardware Reference

4 Board Configuration

Flex CPU Piggyback Board Hardware Reference

HARDWARE SETUP

Flex CPU Board Jumper Configuration

Watchdog Timer Jumper

Jumper E1 on the Turbo CPU board must be OFF for the watchdog timer to operate. This is a very important safety feature, so it is vital that this jumper be OFF in normal operation. E1 should be put ON only to debug problems with the watchdog timer circuit.

Dual-Ported RAM Source Jumper

Jumper E2 must connect pins 1 and 2 to access dual-ported RAM (non-Turbo addresses $Dxxx, Turbo addresses $06xxxx) from the baseboard. If it is desired to use the Option 2 DPRAM on the baseboard, jumper E2 must be in this setting. All Delta Tau base boards except the PMAC(1)-PC board have the option for installing DPRAM on the base board.

Jumper E2 must connect pins 2 and 3 to access dual-ported RAM (non-Turbo addresses $Dxxx, Turbo addresses $06xxxx) through the JEXP expansion port. If it is desired to use DPRAM on an external accessory board, jumper E2 must be in this setting. The PMAC(1)-PC base board (part # 602191-10x) does not have the option for installing on-board DPRAM; it requires the external Option 2 DPRAM board (part #602240-10x) for this functionality. Use of this DPRAM board, interfacing through the JEXP port, requires E2 to connect pins 2 and 3.

Power-Up State Jumpers

Jumper E4 on the Turbo CPU board must be OFF, jumper E5 must be ON, and jumper E6 must be ON, in order for the CPU to copy the firmware from flash memory into active RAM on power-up/reset. This is necessary for normal operation of the card. (Other settings are for factory use only.)

Firmware Load Jumper

If jumper E7 on the CPU board is ON during power-up/reset, the board comes up in “bootstrap mode,” which permits loading new firmware into the flash-memory IC on the board. When the PMAC Executive program tries to establish communications with a board in this mode, it will automatically detect that the board is in bootstrap mode and ask you what file you want to download as the new firmware.

Jumper E7 must be OFF during power-up/reset for the board to come up in normal “operational mode.”

Flash Memory Bank Select Jumpers

The flash-memory IC in location U10 on the Flex CPU board has the capacity for eight separate banks of firmware, only one of which can be used at any given time. The eight combinations of settings for jumpers E10A, E10B, and E10C select which bank of the flash memory is used. In the factory production process, firmware is loaded only into Bank 0, which is selected by having all of these jumpers OFF.

Installation

The Flex CPU board installs on the base controller board using the P1 and P3 stack connectors on the solder side of the CPU board. The CPU board can be further secured to the base board with a standoff and screw through the central hole. When a complete PMAC or Turbo PMAC controller is purchased, this assembly is done at the factory. In the case of retrofits or updates to existing controllers, this assembly is easy to do in the field.

ESD Warning: The Flex CPU board and PMAC controller boards contain static-sensitive components. Make sure proper ESD protection is employed.

Hardware Setup 5

Flex CPU Piggyback Board Hardware Reference

6 Hardware Setup

Flex CPU Piggyback Board Hardware Reference

OPERATION OF THE FLEX CPU

Operation as Non-Turbo CPU

When used as a non-Turbo CPU, the Flex CPU board operates in a manner that is fundamentally compatible with older CPU designs. However, there are a few issues to note:

• The Flex CPU requires the use of V1.17 or newer firmware. There are few differences between the

previous V1.16H firmware and the V1.17 firmware other than the addition of internal support for the Flex CPU design.

• Due to more advanced processor logic and the internal integration of all memory, the Flex CPU will

operate significantly faster than older non-Turbo CPU designs, even for equivalent CPU frequencies. The Flex CPU in a non-Turbo configuration will generally operate more than twice as fast as older non-Turbo CPUs running at the same frequency.

This will result in significantly faster cycle times for background tasks such as PLC programs (the frequency of interrupt-driven foreground tasks is not affected, although the increased computational speeds permit higher frequencies for these tasks). Generally, this will not be a problem, but if existing programs controlled timing by computational delay (e.g. number of loops waiting), operational differences may occur.

• The operational frequency of the CPU can now be set in software by new variable I46. If this

variable is set to 0, PMAC firmware looks at the jumpers (E48 on a PMAC(1), E2 and E4 on a PMAC2) to set the operational frequency, retaining backward compatibility for 40, 60, and 80 MHz operation.. If I46 is set to a value greater than 0, the operational frequency is set to 10MHz * (I46 +

1), regardless of the jumper setting. If the desired operational frequency is higher than the maximum rated frequency for that CPU, the operational frequency will be reduced to the rated maximum. It is always possible to operate the Flex CPU board at a frequency below its rated maximum.

On a Flex CPU board configured for Option 5AF with 40 MHz maximum frequency, I46 should be set to 3 to operate the CPU at its maximum rated frequency.

On a Flex CPU board configured for Option 5CF with 80 MHz maximum frequency, I46 should be set to 7 to operate the CPU at its maximum rated frequency.

On a Flex CPU board configured for Option 5EF with 160 MHz maximum frequency, I46 should be set to 15 to operate the CPU at its maximum rated frequency.

I46 is only used at power-up/reset, so to change the operational frequency, set a new value of I46, issue a SAVE command to store this value in non-volatile flash memory, then issue a $$$ command to reset the controller.

To determine the frequency at which the CPU is actually operating, issue the TYPE command to the PMAC. The PMAC will respond with five data items, the last of which is CLK Xn, where n is the multiplication factor from the 20 MHz crystal frequency (not 10 MHz). n should be equivalent to (I46+1)/2 if I46 is not requesting a frequency greater than the maximum rated for that CPU board. n will be “2” for 40 MHz operation, 4 for 80 MHz operation, and 8 for 160 MHz operation.

• If the CPU’s operational frequency has been determined by (a non-zero setting of) I46, the serial

communications baud rate is determined at power-up/reset by variable I54 alone according to the following table:

Operation of the Flex CPU 7

Flex CPU Piggyback Board Hardware Reference

I54 Baud Rate I54 Baud Rate

0 600 8 9600 1 900 9 14,400 2 1200 10 19,200 3 1800 11 28,800 4 2400 12 38,400 5 3600 13 57,600 6 4800 14 76,800 7 7200 15 115,200

Note that these values can be different from those used on PMAC2 boards with jumper-set CPU frequencies (see below).

• If the saved value of I46 is 0, so the CPU’s operational frequency is determined by jumper settings,

then the serial baud rate is determined by a combination of the setting of jumpers E44-E47 and the CPU frequency on a PMAC(1) board, as shown in the following table. These settings maintain backward compatibility.

E44 E45 E46 E47 Baud Rate

for

20MHz

N ON ON ON Disabled Disabled Disabled OFF ON ON ON 300 600 900 ON OFF ON ON 400* 800* 1200 OFF OFF ON ON 600 1200 1800 ON ON OFF ON 800* 1600* 2400 OFF ON OFF ON 1200 2400 3600 ON OFF OFF ON 1600* 3200* 4800 OFF OFF OFF ON 2400 4800 7200 ON ON ON OFF 3200* 6400* 9600 OFF ON ON OFF 4800 9600 14400 ON OFF ON OFF 6400* 12800* 19200 OFF OFF ON OFF 9600 19200 28800 ON ON OFF OFF 12800* 25600* 38400 OFF ON OFF OFF 19200 38400 57600 ON OFF OFF OFF 25600* 51200* 76800 OFF OFF OFF OFF 38400 76800 115200 * Not an exact baud rate

Baud Rate

for

40MHz

Baud Rate

for

60MHz

8 Operation of the Flex CPU

Flex CPU Piggyback Board Hardware Reference

For a PMAC2 board with a saved value of 0 for I46, the serial baud rate is determined by the combination of I54 and the CPU frequency on a PMAC2 board as shown in the following table. These settings maintain backward compatibility.

I54 Baud Rate for

40 MHz CPU

0 600 Disabled 1200 1 900* (-0.05%) 900 1800* (-0.1%) 2 1200 1200 2400 3 1800* (-0.1%) 1800 3600* (-0.19%) 4 2400 2400 4800 5 3600* (-0.19%) 3600 7200* (-0.38%) 6 4800 4800 9600 7 7200* (-0.38%) 7200 14,400*(-0.75%) 8 9600 9600 19,200

9 14,400*(-0.75%) 14,400 28,800*(-1.5%) 10 19,200 19,200 38,400 11 28,800*(-1.5%) 28,800 57,600*(-3.0%) 12 38,400 38,400 76,800 13 57,600*(-3.0%) 57,600 115,200*(-6.0%) 14 76,800 76,800 153,600 15 Disabled 115,200 DISABLED

* Not an exact baud rate

• With the Flex CPU, the card number (0 – 15) for serial addressing of multiple cards on a daisy-chain

Baud Rate for

60 MHz CPU

Baud Rate for

80 MHz CPU

serial cable is determined by variable I0, even on PMAC(1) boards. This has always been the case for PMAC2 boards, but with other CPU boards, the card number on PMAC(1) boards has been determined by the settings of jumpers E40 – E43. Jumpers E40 – E43 on a PMAC(1) board with the Flex CPU still determine the “direction” of the phase and servo clocks: all of these jumpers must be ON for the card to use its internally generated clock signals and to output these on the serial port connector; if any of these jumpers is OFF, the card will expect to input these clock signals from the serial port connector, and its watchdog timer will trip immediately if it does not receive these signals.

Operation as a Turbo CPU

When used as a Turbo CPU, the Flex CPU is fully compatible with older CPU designs. It does permit higher-speed configurations (Option 5Ex at 160 MHz), which offer significantly higher performance both due to increased operation frequency and added internal memory.

Variable I52 determines the actual operating frequency of the Turbo CPU. The operational frequency is set to 10MHz * (I52 + 1). I52 should be set to 7 to operate an Option 5Cx board at its maximum rated frequency of 80 MHz; it should be set to 9 to operate an Option 5Dx board at its maximum rated frequency of 100 MHz; it should be set to 15 to operate an Option 5Ex board at is maximum rated frequency of 160 MHz.

I52 is used only at power-up/reset, so to change the operational frequency, set a new value of I52, issue a SAVE command to store this value in non-volatile flash memory, then issue a $$$ command to reset the controller.

Operation of the Flex CPU 9

Flex CPU Piggyback Board Hardware Reference

10 Operation of the Flex CPU

Flex CPU Piggyback Board Hardware Reference

FLEX CPU BOARD JUMPER DESCRIPTIONS

E1: Watchdog Disable Jumper

E Point and

Description Default

Physical Layout

E1

Jump pin 1 to 2 to disable Watchdog timer (for test purposes only).

Remove jumper to enable Watchdog timer.

E2: Dual-Ported RAM Port Select

E Point and

Physical Layout

E2

Jump pin 1 to 2 to access DPRAM from baseboard. Jump pin 2 to 3 to access DPRAM through JEXP

expansion port (PMAC(1)-PC with Option 2 DPRAM board).

Description Default

E4 – E6: Power-Up/Reset Load Source

E Point and

Physical Layout

E6

Remove jumper E4; jump E5 pin 1 to 2; jump E6 pin 2 to 3; to read flash IC on power-up/reset Other combinations are for factory use only ; the boa r d

will not operate in any other configuration.

Description Default

No jumper installed

Pins 2 and 3 jumpered (with PMAC(1)-PC base board only)

Pins 1 and 2 jumpered (when used on all other base boards)

No E4 jumper installed; E5 and E6 jump pin 1 to 2

E4

E7: Firmware Reload Enable

E Point and

Physical Layout

E7

Jump pin 1 to 2 to reload firmware through serial or bus port.

Remove jumper for normal operation.

Flex CPU Board Jumper Descriptions 11

Description Default

No jumper installed

Flex CPU Piggyback Board Hardware Reference

E10A, B, C: Flash Memory Bank Select

E Point and

Physical Layout

E10A

E10C

Description Default

Remove all 3 jumpers to select flash memory bank with factory-installed firmware.

Use other configuration to select one of the 7 other flash memory banks

No jumpers installed

12 Flex CPU Board Jumper Descriptions

Flex CPU Piggyback Board Hardware Reference

CONNECTOR SUMMARY

J2: JEXP Expansion Port (50-pin IDC header for Delta Tau accessory boards) J5: JTAG/OnCE Port (for factory use only) J6: JSIO Port (for factory use only) J7: JISP Port (for factory use only) J8: Auxiliary Serial Port (10-pin IDC header)* P1: Stack Connector (Internal connections to main PMAC board) P3: Stack Connector (Internal connections to main PMAC board)

*Pinout shown in next section

Connector Summary 13

Flex CPU Piggyback Board Hardware Reference

14 Connector Summary

Flex CPU Piggyback Board Hardware Reference

CONNECTOR PINOUTS

J8 JRS232 (10-Pin Connector)

Front View

Pin # Symbol Function Description Notes

1 N.C. No Connect 2 DTR Bidirect Data Terminal Ready Tied to DSR 3 TXD/ Input Receive Data Host transmit data 4 CTS Input Clear to Send Host ready bit 5 RXD/ Output Send Data Host receive data 6 RTS Output Request to Send PMAC ready bit 7 DSR Bidirect Data Set Ready Tied to DTR 8 N.C. No Connect 9 GND Common PMAC Common

10 +5V Output +5VDC Supply Power supply out The JRS232 connector provided with Option 9T on a Turbo PMAC is an auxiliary serial port that can be used independently of the standard main serial port and other communications ports. It can be connected with a straight-across flat cable to a DB-9 connector with the standard RS-232 pinout.

Connector Pinouts 15

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ABOVE AGREEMENT.

D D

J5

(JTAG/OnCE)

J5

TSI

1

GND

2

TSO

3

GND

4

TCK

5

GND

6

N.C.

7

RST-

9

TMS

10

+3.3V

11

N.C.

12

DE-

13

TRST-

14

HEADER14_NO8

CTSRTS-

INIT-

N.C.

(.100 MOLEX) JUMP `J6' PIN 6 TO 7 TO LOAD `isp' PART

C C

+3.3V

BSCAN-

B B

GUARD BAND

GND

A A

GND

J6

(jsio)

J6

+5V

1

TXD

2

RXD

3 4 5 6

GND

7 8

HEA_SIP 8

J7

(jisp)

J7

1

TDO

2

TDI

3 4

TMS

6

GND

7

TCK

8

HSIP8NO5

GND

PRAMCS-

DRAMCS-

FLASHCS-

+3P3V

1

3

C85

C83

C84

.1UF

E2 1-to-2 is for DPR on base board E2 2-to-3 is for DPR on expansion board

8

10UF

(TANT)

+3P3V

12

RP1

3.3KSIP10C

3456789 10

RP1_9 D1 SC02

PRDY D3 SIRQ-

PRDY

TDI

TDO

TCK

RESET-

TMS A2 BA02 SRD0 BHA0 D8 D16

DE- A4 BA04 BB- MODD/IRQD- D11 D19

TRST-

+5V

TXD A13 BA13 BSCK1 D23 RXD BRCLK A0 CTS- A14 BA14 PHA_A A1 RTS- A15 BA15 SER_A A2

INIT- BCTS- A3

+3P3V

RD- BA06 BA06_A RDFLASHCS- BA07 BA07_A WRBSCAN-

PRAMCS-

WR- BA11 BA11_A

C21

.01UF

H0 BH0 SC01 H1 BH1 SIRQH2 BH2 BTXD H3 BH3 BSC11 H4 BH4 H5 BH5 Vbat H6 BH6 H7 BH7 HR/W BHR/W HDS- BHDSA3 LA12 A4 LA13 Vout A5 PA16 A6 PA17 A7 PA18 A8 PA19 A9 PA20 A10 PA21 A11 A12 BBRCSA13 BBRAMCSA14 IOCS_A- BBRAMCSA15 IOCS_BA16 TRSTA17 RD- 19.6608Mhz WRPRAMCS- CS0DRAMCS- CS1FLASHCSCPUCLK CS2SEL CS3RESET- BSTD1 STD1 BSCAN- CS4- BSRD1 SRD1

2

E2

C86

.1UF

U6

86

H0

17

H1

29

H2

33

H3

55

H4

46

H5

57

H6

70

H7

59

HRW

31

HDS-

80

A3

56

A4

3

A5

71

A6

73

A7

8

A8

4

A9

79

A10

90

A11

6

A12

84

A13

9

A14

82

A15

78

A16

54

A17

39

RD-/TDO

60

WR-/TCK

37

PRAMCS-/TMS

20

DRAMCS-

16

PROMCS-/TDI

11

CPUCLK/Y0

7

SEL

15

RESET-

14

BSCAN-

66

GOE0

87

GOE1

65

Y1

62

Y2

10

N.C.

26

N.C.

1

VCCIO

24

VCCIO

52

VCCIO

75

VCCIO

27

N.C.

49

N.C.

2

GND

13

GND

25

GND

38 51

GND GND

ISPLSI2064E_DECODE (TSOP100)

GND

BHRW BHDS-

VMECSDPRCS-

BBRCS-

IOCS0IOCS1-

CS00CS04CS06CS10CS12CS14CS16-

BRCLK

WDTC

LA12 LA13 PA16 PA17 PA18 PA19 PA20 PA21

+3P3V

C22

.1UF

+3P3V

C23

.1UF

+3P3V

C24

.1UF

+3P3V

C25

.1UF

+5V

85

BH0

68

BH1

36

BH2

23

BH3

18

BH4

53

BH5

44

BH6

21

BH7

81 83 5 92 91 98 94 95 96 97 69 34 72 35 30 64

VCC

12

VCC

100

N.C.

99

N.C.

43

CS0-

40

CS1-

28

CS2-

19

CS3-

22

CS4-

89

N.C.

C105

77

N.C.

76

N.C.

.1UF

61

N.C.

32 58 47 45 48 42 41 93 67 50

N.C.

88

GND

74

GND

63

GND

10UF

16V

(TANT)

48

A0 BA00 BHREQ- BH5 D5 D13

47

A1 BA01 DE- BH6 D6 D14

46 45 44

A3 BA03 STD0 BHA1 D9 D17

43 42 41

A5 BA05 BHDS- D12 D20

40 39

A6 BA06 BHACK- D14 D22

38

A7 BA07 BRTS- BHREQ- D15 D23

37

A8 BA08 TMS BRXD D16

36

A9 BA09 BG- BTXD D17

35 34

A10 BA10 BSTD1 STD0 D19

33

A11 BA11 BSRD1 BOOTEN- D20

32 31

A12 BA12 BSC12 SCK0 D22

30 29 28 27 26

48

CPUCLK EXTAL A9

47

HACK- BHACK- A10

46 45

A19X/YP BX/Y A12

44

WR- BWR- A13

43 42

RD- BRD- A15

41

BA05 BA05_A A16 WDTC

40 39 38 37

BA08 BA08_A

36

BA09 BA09_A BB-

35 34

BA10 BA10_A

33 32 31

BA12 BA12_A

30

BA13 BA13_A

29 28

BA14 BA14_A

27

BA15 BA15_A

26

LA12 LA13 PA16 PA17 PA18 PA19 PA20

IOCS_AIOCS_B-

BRCLK

PRAM MEMORY P:

$000000-$00FFFF Firmware (64K)

$040000-$0403FF User Written Phase (1K)

$040400-$040BFF User Written Servo (2K)

$050000-$05FFFF Plcc Standard Memory Option (64K)

$050000-$0BFFFF Plcc Extended Memory Option (448K)

8

7

OR

T/R1

B0 B1

GND

B2 B3

VCC

B4 B5

GND

B6 B7 B8 B9

GND

B10 B11

VCC

B12 B13

GND

B14 B15

T/R2

T/R1

B0 B1

GND

B2 B3

VCC

B4 B5

GND

B6 B7 B8 B9

GND

B10 B11

VCC

B12 B13

GND

B14 B15

T/R2

VR2 LM1117MPX-1.8 MC33269ST-1.8 3

IN

NOTE2:

VR1

LM1117MPX-3.3 MC33269ST-3.3

3

IN

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 2425

C100

.1UF

RP1_9

7

OUT

GND

(SOT-223) 1

OUT

GND

(SOT-223) 1

2

GUARD BANDGUARD BAND

C101

.1UF

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26

PI74FCT16245ATA

+5V VCCQL

C89

+

16V

GND

+5V +3P3V

C37

+

GND

U7

OE1 A0 A1 GND A2 A3 VCC A4 A5 GND A6 A7 A8 A9 GND A10 A11 VCC A12 A13 GND A14 A15 OE2

74LCX16245 (TSSOP48) U8

OE1 A0 A1 GND A2 A3 VCC A4 A5 GND A6 A7 A8 A9 GND A10 A11 VCC A12 A13 GND A14 A15 OE2

74LCX16245 (TSSOP48)

*NETLIST CHANGE* *NETLIST CHANGE*

NOTE1:

C90

+

*

16V

NOTE2:

GND

C38

+

10UF 16V

(TANT)

(Request 6pf load capacitance)

(See layout instructions)

+3P3V

C29

.1UF

+3P3V

C28

.1UF

+3P3V

C27

.1UF

+3P3V

C26

.1UF

+3P3V

GND

Memory Range

P:$D00000-$D3FFFF (MAXIMUM OF 16 BANKS) X/Y:$050000-$053FFF STANDARD MEMORY OPTION (16K) X/Y:$050000-$05FFFF EXTENDED MEMORY OPTION (64K)

C102

.1UF

C103

.1UF

1 2

B0

3

B1

4 5

B2

6

B3

7 8

B4

9

B5

10 11

B6

12

B7

13

B8

14

B9

15 16

B10

17

B11

18 19

B12

20

B13

21 22

B14

23

B15

2425

GNDGND

BA00 BA01

BA02 BA03

BA04 BA05

BA06 BA07 BA08 BA09

BA10 BA11

BA12 BA13

BA14 BA15

BX/Y BWR-

BRDBA05_A

BA06_A BA07_A BA08_A BA09_A

BA10_A BA11_A

BA12_A BA13_A

BA14_A BA15_A

GND

+5V

T/R1

GND

VCC

GND

VCC

GND

T/R2

(TANT)

U25

OE1 A0 A1 GND A2 A3 VCC A4 A5 GND A6 A7 A8 A9 GND A10 A11 VCC A12 A13 GND A14 A15 OE2

(TSSOP48)

10UF

6

INSTALL `F2' ONLY FOR `DSP56303PW80'

DO NOT INSTALL

`VR1,C89,C90,R11,R12'

FOR `DSP56303PW80'

INSTALL

`VR1,C89,C90,R11,R12'

FOR `DSP56309PW80' AND `DSP56311GC150' DO NOT INSTALL `F2'

Y3

C-002RX

32.768Khz

Vbat D0 SCK0

RP3

1 2

10KSIP10C

RP6

1 2

10KSIP10C

*NETLIST CHANGE* ********

GUARD BAND

U5

6

GND

X2

5

DATA

X1

VDDVBAT

DS2415P (TSOC)

SC02 BH4 D4 D12 3 4

*NETLIST CHANGE*

5

********

6 7

SCK0 BHA2 D10 D18

8 910

3 4

T/R- SRD0 D18

5 6 7

BSCK1 BRTS- D21

8 910

GUARD BAND

55FZ103N

VCCQL

F1

C41

.1UF

GND

**POLY CAP**

MODA/IRQAMODB/IRQBMODC/IRQCBOOTEN-

X/Y:$078000-$0780FF

CS0-

X/Y:$078100-$0781FF

CS1-

X/Y:$078200-$0782FF

CS2-

X/Y:$078300-$0783FF

CS3-

X/Y:$078400-$0787FF

CS4-

CS00- BSCK1 SCK1

CS04- BSC11 SC11 CS06- WAIT1- BTXD TXD CS10- TA- BRTS- RTSCS12- WAIT2- BHREQ- HREQ-

CS14CS16-

VMECSDPRCS-

WDTC

X/Y:$078800-$0789FF

CS00-

X/Y:$078A00-$078AFF

CS04-

X/Y:$078B00-$078BFF

CS06-

X/Y:$078C00-$078CFF

CS10-

X/Y:$078D00-$078DFF

CS12-

X/Y:$078E00-$078EFF

CS14-

X/Y:$078F00-$078FFF

CS16-

X/Y:$078F00-$078FFF X/Y:$060000-$060FFF STANDARD MEMORY OPTION (4K)

VMECS-

X/Y:$060000-$063FFF EXTENDED MEMORY OPTION (16K)

DPRCS-

X/Y:$060000-$06FFFF EXTENDED MEMORY OPTION (64K) X/Y:$070000-$077FFF

6

RESET- A5

*NETLIST CHANGE*

PINIT TRST- A7 MODD/IRQD- A8 MODC/IRQC- A9 MODB/IRQB- A10 MODA/IRQA- A11 DE- A12 TA- A13 TMS A14 TCK A15 TDO A16 TDI A17 BSC12 A19X/YP BSC11 WRBSTD1 RDBSRD1 SC02 STD0

1

SC01 SRD0

2 34

C104

.1UF

BH0 D0 D8

GND

BH1 D1 D9 BH2 D2 D10 BH3 D3 D11

BH7 D7 D15

BHR/W D13 D21

BG- A4 A19X/YP A5 FLASHCS- A6 DRAMCS- A7 INITPRAMCS- A8

EXTAL A11

C43

C42

.001

POLY

(0805)

.47UF

TP1 GND

E4

2 1

E5

2 1

E6

2 1

E7

2 1

GND

RP2

12 3 4 5 6 7 8 9 10

3.3KSIP10C

+3P3V

D2C1B1C2A2B2B3A4C3

SC01

SC02

H0 H1 H2 H3 H4 H5 H6 H7 HA0 HA1 HA2 HCSHDSHRW HACKHREQRXD TXD SRD0 STD0 SC00 SC10 SCK0 SCK1 SCLK TIO0 TIO1 TIO2 BGAA0 AA1 AA2 AA3 CASXTAL EXTAL CLKOUT BCLK BCLKVCCP PCAP GNDP GNDP1 GND GND GND GND GND GND GND GND

GND

E4

E5E6E7E8E9

GND

10

12

13

SRD1

GND

1

2

4

5

9

M5

P4

N4

P3

N3

P2 N1 N2 M3 M1 M2

L1

J3

J2

J1

K2

F1 G3

E3

E1

F3

F2 H3 G1 G2

L3

L2

K3

P13 N13 P12

P7 N7 N8

P8 M8 M9

N10 M10

M6

P5 N6

P6 D4 D5 D6 D7 D8 D9

D10 D11

X/Y:$000000 -$0107FF ST ANDARD MEMORY OPTION (64K) X/Y:$000000 -$03FFFF EX TENDED MEMORY OPTION (256K)

IOCS_A- H6 SC12

BWR- H4

BRD-

IOCS_B- BHA1 HA1

BWR- MODD/IRQD- IRQB-

BRD-

5

P10A3D3C4A5C5B5

TA

DE

TDI

TCK

TMS

TDO

SC11

SC12

STD1

GND

E10

E11F4F5F6F7F8F9

C33

Y1A

.1UF

1

N.C.

VCC

2 3

GND CLK

MHR13FAJ19.6608

(4 PIN SMT)

Y1B

1

N.C.

VCC

4

GND

CLK

7 8

GND CLK

19.6608MHz

(DIP14WIDE)

C20

+5V

.1UF

U24A

3

74ACT32 (SO14)

U24B

6

74ACT32 (SO14)

U24C

8

74ACT32 (SO14)

U24D

11

74ACT32 (SO14)

5

4

+3P3V

C10

C8

C7

C9

.1UF

N9H2G13C7P14P9N12

L12

K12

H12

D14

N5D1B4

PINT

IRQA

IRQB

IRQC

IRQD

TRST

RESET

GND

F10

F11G4G5G6G7G8G9

P:$000000-$0FFFFF

+5V

*DUAL FOOTPRINT*

4

CPUCLK

14

11

WAIT2-

BWR_A- H5 SC11

BRD_A-

BWR_B- BHA0 HA0

BRD_B-

DSP56311GC150

GND

G10

G11H4H5H6H7H8H9

13 12

BWR_A-

BRD_A-

BWR_B-

BRD_B-

GND

U4F

74ACT14

M4

N.C.

VCCH

U1

GND

GUARD BAND

(SO14)

NC7SZ00

(SOT23-5)

VCCS

GND

H10

1

2

C11C9A7

B14M7H1

F12

A14K1E2P1A1

N.C.

VCCS

VCCD

VCCQH

GND

H11J4J5J6J7J8J9

J10

GUARD BAND

R1

10

+3P3V

C40

53

U9

.1UF

GND

BRXD RXD BPHA BCTS- CTSSER_A BSER PHA_A BPHA BHA2 HA2

T/RRESET

VCCA

VCCD

GND

J11K4K5K6K7K8K9

4

12

RP4

3456789 10

VCCA

GND

VCCC

GND

VCCC

GND

N.C.

GND

K10

VCCQL

GND

K11L4L5

3.3KSIP10C

VCCQL

GND

L6

19.6608Mhz

U27

2

A0

3

A1

4

A2

5

A3

6

A4

7

A5

8

A6

9

A7

1

T/R

19

OE

74LCX245

(TSSOP20)

4

WR-

GND GND GND GND GND

C12

C11

.1UF

C3

.1UF

E14

D0

D12

D1

D13

D2

C13

D3

C14

D4

B13

D5

C12

D6

A13

D7

B12

D8

A12

D9

B11

D10

A11

D11

C10

D12

B10

D13

A10

D14

B9

D15

A9

D16

B8

D17

C8

D18

A8

D19

B7

D20

B6

D21

C6

D22

A6

D23

N14

A0

M13

A1

M14

A2

L13

A3

L14

A4

K13

A5

K14

A6

J13

A7

J12

A8

J14

A9

H13

A10

H14

A11

G14

A12

G12

A13

F13

A14

F14

A15

E13

A16

E12

A17

M12

RD-

M11 N11

BR-

P11

BB-

L11 L10 L9 L8 L7

GNDGND

B0 B1 B2 B3 B4 B5 B6 B7

VCC GND

C14

C13

.1UF

C5

C4

.1UF

+3P3V

18 17 16 15 14 13 12 11

20 10

C87

.1UF

GND

F2

C6

GND

A14

A17

NOTE1:

55FZ103N

VCCQL

+3P3V

BT1

R7

100

RESET- RESET_A WDO

+

3.6V BAT

D6

1 3

MMBD301LT1

.01FARAD FM0H103Z

U26C

5 6

74ACT14 (SO14)

12

3

A0 A1 A2 A3 A4

A6

D2

D4 D5 D6 D7

56

RP5C

1KSIP6I

E1

Vout

1 3

MMBD301LT1

NEC

INIT- 19.6608Mhz

HA2 HA1 HA0 TXD HR/W HDS- STD1 HREQ- SRD1 H7 SCK1

H3 H2 H1 H0

WAIT2-

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17

A19X/YP

WRRD-

D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23

R2

10K

E1

D5

C17

U4A

1 2

C1

74ACT14

.1UF

(SO14)

GND

C35

1 2

1KSIP6I

.01UF

1

23

Q1

MMBT3906LT1

(SOT23)

21

3

C16

.1UF

R4 100K

MMBT3906LT1

(SOT23)

12

RP7

3.3KSIP10C

3456789 10

GND

C34

+

1UF 35V tant

Q3

1

23

VSP01VT18A01

TP2

SIRQ-

C36

.1UF

RP5A

U2

1

VOUT

2 7

VCC RST

3

ON

4 5

GND CEI

MAX795SCSA

(SO8)

P1

12 34 56 78 910 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36

D7

1SMC5.0AT3

R3

1K

+5VGND

U4B

3 4

74ACT14

3 4

1KSIP6I

U3

1

N.C.

2

IN

3

N.C.

4

MODE

5

N.C.

6

TOL

7

N.C.

8

GND

DS1231S (SOL16)

1 3

MMBD301LT1

*NETLIST CHANGE*

GND

(SO14)

RP5B

D3

1 3

MMBD301LT1

D4

BATT

CEO

********

+5V

12

1 2 3 4 5 6 7 8 9

SOT23

2N7002

(SOT23)

16

N.C.

15

VCC

14

N.C.

13

NMI

12

N.C.

11

RST

10

N.C.

9

RST

.1UF

8

6

C15

.1UF

3456789 10

U26A

1 2

74ACT14 (SO14)

U26F

13 12

74ACT14 (SO14)

C32

U28

DIN DOUT SCLK CS N.C. IRQ SHDN GND X2

MAX3100CEE (QSOP)

ECS-36-20-5P

3.6864Mhz

Q4

3

+5V

C2

RP8

3.3KSIP10C

9 8

12

.1UF

VCC

SOT23

U26D

74ACT14 (SO14)

TX

RX RTS N.C. CTS

X1

3

GND

HACKRXD

CTS-

IRQB-

CS4WAIT1-

11 10

16 15 14 13 12 11 10

12

3 4

2

Y2

C70

22pf

GUARD BANDING REQ'D

U4C

5 6

12

74ACT14

Q5

3

2N7002

SOT23

(SOT23)

U4D

9 8

74ACT14

U4E

11 10

74ACT14

Q2 2N7002

(SOT23)

GUARD BANDING REQ'D

U26B

74ACT14 (SO14)

U26E

74ACT14 (SO14)

2

NOTE:

THIS PART MUST BE `MAX3232ECWE'

TO PROVIDE `ESD' PROTECTION

OF THE `RS232' INPUT SECTION.

C76

C72

.1UF

2

C73

1

.1UF

3

11

12

10

9

MAX3232ECWE

(SOL16)

D2 LED GRN

R5 1K

BSC12 SC12

BPHA

C82

GND

.1UF

BSER

RESET_B

|Link |605-1sh2.sch

.1UF

U29

+V

C1+

C1-

TXD

RXD

RTS

CTS

D2A LED GRN

PWR WD

R5A 1K

U30

2

A0

3

A1

4

A2

5

A3

6

A4

7

A5

8

A6

9

A7

1

T/R

19

OE

PI74FCT245TL

(TSSOP20)

16

VCC

TXD

RXD

RTS

CTS

VSS

15

1K

+5V

GND

C74

.1UF

6

V-

C75

4

C2+

.1UF

5

C2-

14

13

7

8

RESET

WDO

D1A

D1

LED

RED

WDPWR

R6A

R6

1K

RESET-

RP9A

330SIP8I

18

1 2

B0

3 4

17

B1

5 6

16

B2

15

7 8

B3

14

B4

13

B5

12

B6

11

B7

20

VCC

10

GND

Title

Size Document Number Rev

D

Date: Sheet

C88

.1UF

Delta Tau Data Systems, Inc.

DSP563XX CPU Piggyback Board

603605-322P

(SO14)

+5V

BSER

RESET_B

+3P3V

C71

22pf

R8

330

1

RESET-PA21

BBRCS-

1

+5V

J8

1 2 3 4 5 6 7 8 9 10

HEADER 10

(BOX)

12Thursday, September 19, 2002

(JRS232)

N.C. DTR TXDCTS RXDRTS DSR N.C. GND +5V

of

-