Delta Tau PMAC2 VME User Manual

^1 HARDWARE REFERENCE MANUAL

^2 PMAC2-VME

^3 Programmable Multi-Axis Controller

^4 3Ax-602413-xHxx

^5 May 27, 2004

Single Source Machine Control Power // Flexibility // Ease of Use

21314 Lassen Street Chatsworth, CA 91311 // Tel. (818) 998-2095 Fax. (818) 998-7807 // www.deltatau.com

unauthorized without written permission of Delta Tau Data Systems, Inc. Information contained in this manual may be updated from time-to-time due to product improvements, etc., and may not conform in every respect to former issues.

To report errors or inconsistencies, call or email:

Delta Tau Data Systems, Inc. Technical Support

Phone: (818) 717-5656 Fax: (818) 998-7807 Email: support@deltatau.com Website: http://www.deltatau.com

Operating Conditions

All Delta Tau Data Systems, Inc. motion controller products, accessories, and amplifiers contain static sensitive components that can be damaged by incorrect handling. When installing or handling Delta Tau Data Systems, Inc. products, avoid contact with highly insulated materials. Only qualified personnel should be allowed to handle this equipment.

In the case of industrial applications, we expect our products to be protected from hazardous or conductive materials and/or environments that could cause harm to the controller by damaging components or causing electrical shorts. When our products are used in an industrial environment, install them into an industrial electrical cabinet or industrial PC to protect them from excessive or corrosive moisture, abnormal ambient temperatures, and conductive materials. If Delta Tau Data Systems, Inc. products are exposed to hazardous or conductive materials and/or environments, we cannot guarantee their operation.

PMAC2 VME Hardware Reference Manual

Table of Contents

INTRODUCTION.......................................................................................................................................................1

Features.....................................................................................................................................................................1

PMAC2 VME Configuration ....................................................................................................................................1

PMAC2 VME ASICs.............................................................................................................................................1

DSPGATE1 Servo ASIC........................................................................................................................................1

DSPGATE2 I/O ASIC...........................................................................................................................................2

PMAC2 VME Board Configuration..........................................................................................................................2

PMAC2 VME Setup ..............................................................................................................................................3

PMAC2 CPUs...........................................................................................................................................................3

Configurations......................................................................................................................................................4

Firmware..............................................................................................................................................................4

Option 16 Supplemental Memory.........................................................................................................................4

Related Technical Documentation ............................................................................................................................5

CONNECTORS...........................................................................................................................................................7

PMAC2 VME Connector Summary..........................................................................................................................7

J1/JANA (20-Pin Header).........................................................................................................................................8

J2/JTHW (26-Pin Header).........................................................................................................................................9

J3/JIO (40-Pin Header)............................................................................................................................................10

J4 (JMACRO) 26-Pin Header .................................................................................................................................11

J5/JRS232 (10-Pin Header).....................................................................................................................................11

J5A/JRS422 (26-Pin Header)..................................................................................................................................12

J6/JDISP (14-Pin Header).......................................................................................................................................13

J7/JHW (20-Pin Header).........................................................................................................................................13

J8/JEQU (10-Pin Header)........................................................................................................................................14

J9/JMACH1 (100-Pin Header)................................................................................................................................14

J10/JMACH2 (100-Pin Header)..............................................................................................................................17

P1 JMACH (96-Pin Header)...................................................................................................................................20

P2/JMACHA (96-Pin Header) ...............................................................................................................................21

TB1 (2/4-Pin Terminal Block)................................................................................................................................22

TB2 (3-Pin Terminal Block) ...................................................................................................................................22

JUMPER SUMMARY..............................................................................................................................................23

E1: Card 0 Select....................................................................................................................................................23

E2: 40 MHz/60 MHz CPU Operation................................................................................................................23

E3: Re-Initialization on Reset Control ..............................................................................................................23

E4 - E6: (Reserved for future use).....................................................................................................................23

E7A-H through E10A-H: P2 Connector B-Row Use Selec t...............................................................................24

E11-E12: JEQU Port Sink/Source Select..........................................................................................................24

E13: SCLK Direction Control...........................................................................................................................24

E17 - E18: Serial Connector Select....................................................................................................................25

E20A-I: DPRAM Byte Order Control................................................................................................................25

E39: Reset-From-Bus Enable............................................................................................................................25

Option 1V Piggyback Connector Description.........................................................................................................26

J11/JMACH3 (100-Pin Header)..............................................................................................................................26

J12/JMACH4 (100-Pin Header)..............................................................................................................................29

P2A/JMACHB (96-Pin Header)..............................................................................................................................32

OPTION 1V PIGGYBACK JUMPER SUMMARY..............................................................................................33

E14: SCLK Direction Control...........................................................................................................................33

PMAC2 VME CPU....................................................................................................................................................35

Connector Summary................................................................................................................................................35

J1 ........................................................................................................................................................................35

J2 (JEXP)............................................................................................................................................................35

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PMAC VME Hardware Reference Manual

J3 ........................................................................................................................................................................35

J4 (JEXP)............................................................................................................................................................35

J5 (JTAG/OnCE) ................................................................................................................................................35

J6 ........................................................................................................................................................................35

J7 ........................................................................................................................................................................35

PMAC2 VME CPU Board......................................................................................................................................36

PMAC2 VME CPU Piggyback Board Jumpers ......................................................................................................37

ii Table of Contents

PMAC2 VME Hardware Reference Manual

INTRODUCTION

The PMAC2 VME provides state-of-the-art motion control for a wide variety of applications, including machine tools, robotics, semiconductor manufacturing, packaging equipment, and general-purpose automation. It utilizes the latest developments in electronics, software, and modern control theory to bring motion control capabilities to a whole new level.

The PMAC2 VME is designed as a bus expansion card, but is capable of standalone operation. It is VMEbus-compatible, with two slots and four or eight machine interface channels.

Features

PMAC2 VME supports a wide variety of servo and stepper interfaces:

• Analog +/-10V velocity command (requires Acc-8E or equivalent)

• Analog +/-10V torque command (requires Acc-8E or equivalent)

• Sinusoidal analog +/-10V phase current commands (requires Acc-8E or equivalent)

• Direct digital pulse-width modulated (PWM) phase voltage commands (requires Acc-8F, -8K or

equivalent)

• Pulse-and-direction commands (requires Acc-8S or equivalent)

• MACRO

PMAC2 VME also provides unparalleled speeds and resolutions:

• 40 MHz encoder count rate

• 18-bit analog outputs

• 18 microsecond per axis servo update time (60 MHz)

• 120 MHz PWM clock frequency (10-bit resolution at 120 kHz, 12-bit and 30 kHz, 14-bit at 7.5 kHz)

• 120 MHz MLDT (e.g. Temposonics

• 10 MHz maximum pulse-and-direction output frequency

• 10 MHz maximum position-compare output update rate

• 125 Mbit/sec optical ring network data rate

ring network commands (requires Acc-42)

) timer frequency (0.024mm, 0.9mil resolution)

PMAC2 VME Configuration

A PMAC2 VME board can have one or two DSPGATE1 ASICs; the first one is standard, and the second one comes if Option 1V is ordered. It also has a DSPGATE2 ASIC supporting the non-servo I/O.

PMAC2 VME ASICs

Delta Tau has designed its own custom application-specific integrated circuits (ASICs) for the PMAC2 VME using the latest sub-micron gate-array technology. Each ASIC contains 45,000 active logic gates. These ASICs contain all of the digital interface circuitry to tie the DSP to the machine; the rest of the circuitry on the board is buffer circuitry.

DSPGATE1 Servo ASIC

The DSPGATE1 ASIC contains the digital servo interface circuitry for four channels, usually sufficient for four axes of control. Each channel contains:

• Three command output sets:

• Top-and-bottom PWM or serial DAC data with clock

• Top-and-bottom PWM or serial DAC data with strobe

• Top-and-bottom PWM or PFM pulse-and-direction

• Encoder quadrature or pulse-and-direction decode and count

• Index channel input internally gated to 1 quadrature state wide

• Four flags with capability to perform hardware latching of encoder position

• HOME, PLIM, MLIM, USER

• Double-sided position-compare output with auto-increment capability

• Amplifier enable output

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PMAC VME Hardware Reference Manual

• Amplifier fault input

• Four supplementary flag inputs (T, U, V, W)

• Two inputs from serial analog-to-digital converters (ADCs)

• ADC clock and strobe signal outputs

The DSPGATE1 ASIC also generates several clock frequencies necessary for hardware and software operation, under the user’s software control:

• PWM output frequency

• DAC clock frequency

• ADC clock frequency

• Encoder sample clock frequency

• Pulse-frequency modulation (PFM) clock frequency

• Phase interrupt clock frequency

• Servo interrupt clock frequency

Note:

Phase interrupt clock frequency and Servo interrupt clock frequency are generated from the first DSPGATE1 only.

DSPGATE2 I/O ASIC

There is also a DSPGATE2 ASIC on PMAC2 VME, which is used for interface to other I/O. The DSPGATE2 ASIC has three parts:

• General-purpose digital I/O: 56 I/O points for JIO, JTHW, and JDISP ports

• Servo interface circuitry for 2 supplemental channels with clock generation

• MACRO ring interface circuitry

Generally, the general-purpose I/O and the servo interface circuitry on the DSPGATE2 share pins, except for two 2-channel encoder inputs and two PWM/PFM output sub-channels. On a PMAC2 VME board, usually the shared pins are used for general-purpose I/O instead of extra servo interface circuitry, but this is up to the individual user.

PMAC2 VME Board Configuration

Jumpers on the PMAC2 VME determine the frequency at which the DSP on the PV CPU board will operate. The 56002 DSP has a phased-locked loop (PLL) that allows it to multiply the crystal frequency by a programmable integer value, permitting very high CPU frequencies with a moderate crystal frequency. The crystal frequency on the PV CPU board is always 19.6608 MHz, commonly called 20 MHz.

The component rating of the DSP IC specifies the highest frequency at which it safely can run, but it is the multiplication factor typically set by jumpers that specifies the frequency at which it actually runs. Usually this is a frequency at or near the maximum for the component.

It is safe to run a DSP at a frequency below the maximum. It may be possible to run a DSP at a frequency higher than its maximum frequency, particularly at low ambient temperatures, but safe operation cannot be guaranteed. Unpredictable and possibly dangerous operation may result.

On power-up/reset, the DSP, operating at the crystal frequency of 20 MHz, reads the frequency jumpers (E2 and E4) and writes into its own PLL multiplier register at X:$FFFD. Bits 0-3 of this word contain a value one less than the multiplier value (if the frequency is being multiplied by 3, these bits contain a value of 2).

If you wish to check the value of your multiplier, you can use the on-line command RHX:$FFFD and look at the last hexadecimal digit. The actual multiplier is one greater than the value in this last digit.

2 Introduction

PMAC2 VME Hardware Reference Manual

Alternately, you can define an M-variable such as M99->X:$FFFD,0,4 and then read from or write to these bits with the M-variable.

PMAC2 VME Setup

On PMAC2 VME, jumpers E2 and E4 control the frequency of operation of the DSP according to the following table:

E2 E4 X:$FFFD; 0-3 True Multiplier DSP Frequency

OFF OFF 1 x2 40 MHz

ON OFF 2 x3 60 MHz

OFF ON 3 x4 80 MHz

On the PMAC2 VME, I54 is read at power-up to set the baud rate clock. Because this clock is derived from the CPU clock frequency, the proper setting of I54 is dependent on the CPU clock frequency as set by E2 and E4. Table 1-3 shows the settings of I54 for 40, 60, and 80 MHz CPU operation.

I54 Baud Rate for 40 MHz CPU Baud Rate for 60 MHz CPU Baud Rate for 80 MHz CPU

0 600 Disabled 1200 1 900* (-0.05%) 900 1800* (-0.1%) 2 1200 1200 2400 3 1800* (-0.1%) 1800 3600* (-0.19%) 4 2400 2400 4800 5 3600* (-0.19%) 3600 7200* (-0.38%) 6 4800 4800 9600 7 7200* (-0.38%) 7200 14,400*(-0.75%) 8 9600 9600 19,200

9 14,400*(-0.75%) 14,400 28,800*(-1.5%) 10 19,200 19,200 38,400 11 28,800*(-1.5%) 28,800 57,600*(-3.0%) 12 38,400 38,400 76,800 13 57,600*(-3.0%) 57,600 115,200*(-6.0%) 14 76,800 76,800 153,600 15 Disabled 115,200 Disabled

* not an exact baud rate

PMAC2 CPUs

The PMAC2 VME CPU communicates with the axes through specially designed custom gate array ICs, referred to as DSPGATES. Each of these ICs can handle four analog output channels, four encoders as input, and four analog-derived inputs from accessory boards. One PMAC2 VME can utilize from one to four of these gate array ICs, so specifying the hardware configuration amounts to counting the numbers and types of inputs and outputs. Up to 16 PMAC2 VMEs may be ganged together with complete synchronization, for a total of 128 axes. A PMAC2 VME may have one of three available CPU configurations. These configurations are described in the following paragraphs.

• P/N 602398 — This is the original standard CPU board for the PMAC2 VME. It has a 20MHz clock

and a battery backup RAM.

• P/N 602405 — This is a flash memory CPU board with no battery backup. This board provides

either a 40MHz or 60MHz clock.

• P/N 602705 — The PV CPU piggyback board provides 80 MHz CPU operation and supplemental

battery-backed RAM for the PMAC2 VME.

The PV CPU board gets its name from the PV package style of the Motorola 56002 DSP IC on the board. The board is also called the Universal CPU because it can support all speeds and configurations of the CPU section.

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PMAC VME Hardware Reference Manual

The PV CPU has operational differences from earlier CPU configurations to support the new features. The following paragraphs explain these differences and are only relevant if using the 602705 CPU piggyback board on the controller.

Configurations

The PV CPU board is configured at the factory to the customer’s specifications. The JEXP expansion port is buffered, providing the capability to connect many boards on the expansion port.

The following table shows the configuration of the key components on the PV CPU board for the PMAC2 VME.

Version Main Memory

Backup

Standard Flash Empty 32-pin RAM Flash ROM Empty Opt 5B Flash Empty 32-pin RAM Flash ROM Empty Opt 5C Flash Empty 32-pin RAM Flash ROM Empty +Opt 16 Flash 28-pin RAM 32-pin RAM Flash ROM Battery

U6, U9, U15 Components

U7, U10, U16 Components

U5 Components BT1 Components

Firmware

The PV CPU board does not support firmware versions previous to V1.16 of August 1996 without changes in programming of the on-board logic (GALs). If the firmware must be changed between a version previous to V1.16 and a version V1.16 or newer, the on-board logic must be re-programmed.

When loading new firmware into the flash configurations of the PV CPU, E4 on the CPU board must be ON in addition to having the PMAC2 VME re-initialization jumper E3 ON.

Option 16 Supplemental Memory

If the Option 16 supplemental battery-backed parameter memory is ordered, an extra bank of memory with battery backup circuitry is provided. This option can be ordered only if the main memory is flash backed (Option 4A, 5A, 5B, or 5C). This memory is for user parameter storage only. From PMAC programs it can be accessed with M-variables only (L-variables also in compiled PLCs). The on-line direct-memory read and write commands can be used from the host computer as well.

With M-variable access, arrays can be created with indirect addressing techniques by pointing a second M-variable to the definition of a first M-variable that points into this memory area. For example, with the M-variable definitions:

M0->L:$A000; 1st long word of Opt. 16 RAM; floating point M10->Y:$BC000,0,16; Low 16 bits of M0 def., with pointer address

Note:

This technique is not possible with L-variables in compiled PLCs.

The following code segment could load a sine table into the first 360 words of the Option 16 RAM:

P1=0 WHILE (P1<360) M10=$A000+P1 ; Sets address that M0 points to M0=SIN(P1) ; Puts value in register that M0 points to P1=P1+1

ENDWHILE

Physically, the Option 16 memory is a 16k x 24 bank of battery-backed static RAM. It maps into the PMAC2 VME at addresses $A000 to $BFFF, on both the X and Y data buses, an 8k x 48 block of address space. Addresses Y:$BC00 to Y:$BFFF are double-mapped with the main flash-backed RAM for the Mvariable definitions, and should not be used for user parameter storage.

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PMAC2 VME Hardware Reference Manual

Any value written into the Option 16 memory will automatically be retained through a power-down or reset; no SAVE operation is required. The power draw on the battery is low enough that battery life will typically be limited only by the quoted 10-year life of the battery.

Delta Tau PMAC2 VME User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

PMAC2 VME ASICs

DSPGATE1 Servo ASIC

DSPGATE2 I/O ASIC

PMAC2 VME Setup

Configurations

Firmware

Option 16 Supplemental Memory