Delta Tau PMAC2A-PC/104 CPU Reference Manual

^1 HARDWARE REFERENCE MANUAL

PMAC2A-PC/104 CPU

^3 PMAC2A-PC/104 CPU Hardware Reference

^4 4xx-603670-xAxx

^5 July 29, 2008

Single Source Machine Control Power // Flexibility // Ease of Use

21314 Lassen Street Chatsworth, CA 91311 // Tel. [phone] Fax. [phone] // www.deltatau.com

Copyright Information

© 2008 Delta Tau Data Systems, Inc. All rights reserved.

This document is furnished for the customers of Delta Tau Data Systems, Inc. Other uses are
unauthorized without written permission of Delta Tau Data Systems, Inc. Information contained
in this manual may be updated from time-to-time due to product improvements, etc., and may not
conform in every respect to former issues.

To report errors or inconsistencies, call or email:

Delta Tau Data Systems, Inc. Technical Support

Phone: [phone]
Fax: [phone]
Email: [e-mail]
Website: http://www.deltatau.com

Operating Conditions

All Delta Tau Data Systems, Inc. motion controller products, accessories, and amplifiers contain
static sensitive components that can be damaged by incorrect handling. When installing or
handling Delta Tau Data Systems, Inc. products, avoid contact with highly insulated materials.
Only qualified personnel should be allowed to handle this equipment.

In the case of industrial applications, we expect our products to be protected from hazardous or
conductive materials and/or environments that could cause harm to the controller by damaging
components or causing electrical shorts. When our products are used in an industrial
environment, install them into an industrial electrical cabinet or industrial PC to protect them
from excessive or corrosive moisture, abnormal ambient temperatures, and conductive materials.
If Delta Tau Data Systems, Inc. products are exposed to hazardous or conductive materials and/or
environments, we cannot guarantee their operation.

REV. DESCRIPTION DATE CHG APPVD

1 UPDATED JUMPER DESCRIPTIONS PGS. 6 & 30 05/17/06 CP S. MILICI

2 REVS: J4, E20-23, CONNECTOR PINOUTS,

& BOARD DIAGRAMS

3 CORRECTED TYPO IN I-VARIABLE SETTINGS, P. 17 01/22/08 CP S.MILICI

4 CORRECTED USER FLAGS FOR PINS 25 & 26, P.36 07/29/08 CP C.COKER

REVISION HISTORY

10/04/06 CP P. SHANTZ

PMAC2A PC104 Hardware Reference Manual

Table of Contents

INTRODUCTION .......................................................................................................................................................1

Board Configuration..................................................................................................................................................1

Base Version .........................................................................................................................................................1

Board Options ...........................................................................................................................................................1

Option 2A: PC/104 Bus Stack Interface ..............................................................................................................1

Option 5xF: CPU Speed Options.........................................................................................................................1

Option 6: Extended Firmware Algorithm............................................................................................................1

Option 6L: Multi-block Lookahead Firmware.....................................................................................................1

Option 10: Firmware Version Specification.........................................................................................................2

Option 12: Analog-to-Digital Converters.............................................................................................................2

Additional Accessories..............................................................................................................................................2

Acc-1P: Axis Expansion Piggyback Board...........................................................................................................2

Acc-2P: Communications Board .........................................................................................................................2

Acc-8TS Connections Board.................................................................................................................................3

Acc-8ES Four-Channel Dual-DAC Analog Stack Board......................................................................................3

Acc-8FS Four-Channel Direct PWM Stack Breakout Board................................................................................3

HARDWARE SETUP .................................................................................................................................................5

Clock Configuration Jumpers....................................................................................................................................5

Reset Jumpers............................................................................................................................................................5

CPU Configuration Jumpers .....................................................................................................................................6

Communication Jumpers...........................................................................................................................................6

ADC Configuration Jumpers.....................................................................................................................................6

Encoder Configuration Jumpers................................................................................................................................6

Single-Ended Encoders.........................................................................................................................................6

Differential Encoders............................................................................................................................................6

MACHINE CONNECTIONS.....................................................................................................................................9

Mounting ...................................................................................................................................................................9

Power Supplies..........................................................................................................................................................9

Digital Power Supply............................................................................................................................................9

DAC Outputs Power Supply .................................................................................................................................9

Flags Power Supply............................................................................................................................................10

Overtravel Limits and Home Switches....................................................................................................................10

Types of Overtravel Limits..................................................................................................................................10

Home Switches....................................................................................................................................................10

Motor Signals Connections .....................................................................................................................................10

Incremental Encoder Connection .......................................................................................................................10

DAC Output Signals ...........................................................................................................................................11

Pulse and Direction (Stepper) Drivers ...............................................................................................................11

Amplifier Enable Signal (AENAx/DIRn).............................................................................................................11

Amplifier Fault Signal (FAULT-) .......................................................................................................................12

Optional Analog Inputs ...........................................................................................................................................12

Compare Equal Outputs ..........................................................................................................................................12

Serial Port (JRS232 Port) ........................................................................................................................................12

Machine Connections Example: Using Analog ±10V Amplifier............................................................................13

Machine Connections Example: Using Pulse and Direction Drivers......................................................................14

SOFTWARE SETUP ................................................................................................................................................15

PMAC I-Variables...................................................................................................................................................15

Communications......................................................................................................................................................15

Operational Frequency and Baud Rate Setup ....................................................................................................15

Filtered DAC Output Configuration........................................................................................................................16

Parameters to Set up Global Hardware Signals.................................................................................................17

Parameters to Set Up Per-Channel Hardware Signals ......................................................................................18

Table of Contents i

PMAC2A PC104 Hardware Reference Manual

Effects of Changing I900 on the System .............................................................................................................18

How does changing I900 effect other settings in PMAC ....................................................................................20

Effects of Output Resolution and Servo Interrupt Frequency on Servo Gains....................................................21

Using Flag I/O as General-Purpose I/O...................................................................................................................22

Analog Inputs Setup................................................................................................................................................22

CPU Analog Inputs.............................................................................................................................................22

HARDWARE REFERENCE SUMMARY .............................................................................................................23

Board Dimensions...................................................................................................................................................23

From v106 to 107................................................................................................................................................23

From v107 to 108................................................................................................................................................24

From v108 to 109................................................................................................................................................25

Board Layout...........................................................................................................................................................26

Connectors and Indicators.......................................................................................................................................27

J3 - Machine Connector (JMACH1 Port)...........................................................................................................27

J4 - Machine Connector (JMACH2 Port)...........................................................................................................27

J8 - Serial Port (JRS232 Port)............................................................................................................................27

TB1 – Power Supply Terminal Block (JPWR Connector) ..................................................................................27

LED Indicators ...................................................................................................................................................27

E-POINT JUMPER DESCRIPTIONS ....................................................................................................................29

E0: Forced Reset Control .......................................................................................................................................29

E1: Servo and Phase Clock Direction Control .......................................................................................................29

E2: CPU Frequency Select.....................................................................................................................................29

E3: Normal/Re-Initializing Power-Up/Reset..........................................................................................................29

E4: CPU Frequency Select.....................................................................................................................................30

E8: Phase Clock Lines Output Enable....................................................................................................................30

E9: Servo Clock Lines Output Enable....................................................................................................................30

E10 – E12: Power-Up State Jumpers .....................................................................................................................30

E13: Power-Up/Reset Load Source........................................................................................................................31

E14: Watchdog Disable Jumper.............................................................................................................................31

E15A, B, C: Flash Memory Bank Select................................................................................................................31

E16: ADC Inputs Enable.........................................................................................................................................31

E18 – E19: PC/104 Bus Address............................................................................................................................32

E20-E23: ENCODER SINGLE ENDED/DIFFERENTIAL SELECT (Note: v107 and above only) ..............32

CONNECTOR PINOUTS.........................................................................................................................................33

TB1 (JPWR): Power Supply ..................................................................................................................................33

J4 (JRS232) Serial Port Connector..........................................................................................................................33

J3 (JMACH1): Machine Port Connector.................................................................................................................34

J3 JMACH1 (50-Pin Header)..................................................................................................................................35

J4 (JMACH2): Machine Port CPU Connector ........................................................................................................36

SCHEMATICS ..........................................................................................................................................................38

ii Table of Contents

PMAC2A PC104 Hardware Reference Manual

INTRODUCTION

The PMAC2A PC/104 motion controller is a compact, cost-effective version of Delta Tau’s PMAC2
family of controllers. The PMAC2A PC/104 can be composed of three boards in a stack configuration.

The CPU provides four channels of either DAC ±10V or pulse and direction command outputs. The
optional axis expansion board provides a set of four additional servo channels and I/O ports. The optional
communications board provides extra I/O ports and either the USB or Ethernet interface for faster
communications.

Board Configuration

Base Version

The base version of the PMAC2A PC/104 ordered with no options provides a 90mm x 95mm board with:

• 40 MHz DSP563xx CPU (80 MHz 560xx equivalent)

• 128k x 24 internal zero-wait-state SRAM

• 512k x 8 flash memory for user backup and firmware

• Latest released firmware version

• RS-232 serial interface

• Four channels axis interface circuitry, each including:

• 12-bit ±10V analog output

• Pulse-and-direction digital outputs

• 3-channel differential/single-ended encoder input

• Four input flags, two output flags

• Three PWM top-and-bottom pairs (unbuffered)

• 50-pin IDC header for amplifier/encoder interface

• 34-pin IDC header for flag interface

• PID/notch/feed forward servo algorithms

• 1-year warranty from date of shipment

• One CD-ROM per set of one to four PMACs in shipment (Cables, mounting plates, mating

connectors not included)

PMAC2A-PC/104 Base Board shown

Board Options

Option 2A: PC/104 Bus Stack Interface

Option 2A provides the PC/104 bus interface allowing bus communications between a PC/104 type
computer and the PMAC2A PC/104 motion controller.

Option 5xF: CPU Speed Options

• Option 5CF: 80 MHz DSP563xx CPU (160 MHz 56002 equivalent)

• Option 5EF: 160 MHz DSP563xx CPU (320 MHz 56002 equivalent)

Option 6: Extended Firmware Algorithm

Option 6 provides an Extended (Pole-Placement) Servo Algorithm firmware instead of the regular servo
algorithm firmware. This is required only in difficult-to-control systems (resonances, backlash, friction,
disturbances, changing dynamics).

Option 6L: Multi-block Lookahead Firmware

Option 6L provides a special lookahead firmware for sophisticated acceleration and cornering profiles
execution. With the lookahead firmware PMAC controls the speed along the path automatically (but
without changing the path) to ensure that axis limits are not violated.

Introduction 1

PMAC2A PC104 Hardware Reference Manual

Option 10: Firmware Version Specification

Normally the PMAC2A PC/104 is provided with the newest released firmware version. A label on the
memory IC shows the firmware version loaded at the factory. Option 10 provides for a user-specified
firmware version.

Option 12: Analog-to-Digital Converters

Option 12 permits the installation of two channels of on-board analog-to-digital converters with ±10V
input range and 12-bits resolution. The key component installed with this option is U20.

Additional Accessories

Acc-1P: Axis Expansion Piggyback Board

Acc-1P provides four additional channels axis interface circuitry for a total of eight servo channels, each
including:

• 12-bit ±10V analog output

• Pulse-and-direction digital outputs

• 3-channel differential/single-ended encoder input

• Four input flags, two output flags

• Three PWM top-and-bottom pairs (unbuffered)

Acc-1P Option 1: I/O Ports

Option 1 provides the following ports on the Acc-1P axes expansion board for digital I/O connections.

• Multiplexer Port: This connector provides eight input lines and eight output lines at TTL levels.

When using the PMAC Acc-34x type boards these lines allow multiplexing large numbers of
inputs and outputs on the port. Up to 32 of the multiplexed I/O boards may be daisy-chained on
the port, in any combination.

• I/O Port: This port provides eight general-purpose digital inputs and eight general-purpose digital

outputs at 5 to 24Vdc levels. This 34-pin connector was designed for easy interface to OPTO-22
or equivalent optically isolated I/O modules when different voltage levels or opto-isolation to the
PMAC2A PC/104 is necessary.

• Handwheel port: this port provides two extra channels, each jumper selectable between encoder

input or pulse output.

Acc-1P Option 2: Analog-to-Digital Converters

Option 2 permits the installation on the Acc-1P of two channels of analog-to-digital converters with ±10V
input range and 12-bits resolution. The key component installed with this option is U20.

Acc-2P: Communications Board

Without any options, the PMAC2A PC/104 communicates through the RS-232 serial interface (using the
optional Acc-3L flat cable) or PC/104 bus. This board provides added communication and I/O features.

Acc-2P Option 1A: USB Interface

Option 1A it provides a 480 Mbit/sec USB 2.0 interface.

Acc-2P Option 1B: Ethernet Interface

Option 1B provides a 100 Mbit/sec Ethernet.

Acc-2P Option 2: DPRAM Circuitry

Option 2 provides an 8K x 16 dual-ported RAM used with USB, Ethernet or PC/104 bus applications. If
using for USB or Ethernet communications, Acc-2P-Opt-1A or Acc-2P-Opt-1B must be ordered. If used

2 Introduction

PMAC2A PC104 Hardware Reference Manual

for PC/104-bus communications, PMAC2A PC/104 Option-2A must be ordered. The key component
installed with this option is U17. USB/Ethernet and PC/104 bus communications cannot be made
simultaneously it is jumper selectable.

Acc-2P Option 3: I/O Ports

Option 3 provides the following ports on the Acc-2P communications board for digital I/O connections.

• Multiplexer Port: this connector provides eight input lines and eight output lines at TTL levels.

When using the PMAC Acc-34x type boards these lines allow multiplexing large numbers of
inputs and outputs on the port. Up to 32 of the multiplexed I/O boards may be daisy-chained on
the port, in any combination.

• I/O Port: this port provides 16 general-purpose digital I/O lines at TTL levels and these can be

configured as all inputs, all outputs or eight inputs and eight outputs.

• Handwheel port: this port provides two extra channels, each jumper selectable between encoder

input or pulse output.

Acc-8TS Connections Board

Acc-8TS is a stack interface board to for the connection of either one or two Acc-28B A/D converter
boards. When a digital amplifier with current feedback is used, the analog inputs provided by the Acc­28B cannot be used.

Acc-8ES Four-Channel Dual-DAC Analog Stack Board

Acc-8ES provides four channels of 18-bit dual-DAC with four DB-9 connectors. This accessory is
stacked to the PMAC2A PC/104 board and it is mostly used with amplifiers that require two ±10 V
command signals for sinusoidal commutation.

Acc-8FS Four-Channel Direct PWM Stack Breakout Board

Acc-8FS it is a 4-channel direct PWM stack breakout board for PMAC2A PC/104. This is used for
controlling digital amplifiers that require direct PWM control signals. When a digital amplifier with
current feedback is used, the analog inputs provided by the Option 12 of the PMAC2A PC/104 (the
Option 2 of the Acc-1P or the Acc-28B) could not be used.

Introduction 3

PMAC2A PC104 Hardware Reference Manual

4 Introduction

PMAC2A PC104 Hardware Reference Manual

HARDWARE SETUP

On the PMAC2 PC/104 CPU, there are a number of jumpers called E-points or W-points. That customize
the hardware features of the CPU for a given application and must be setup appropriately. The following
is an overview grouped in appropriate categories. For an itemized description of the jumper setup
configuration, refer to the E-Point Descriptions section.

Clock Configuration Jumpers

E1: Servo and Phase Clock Direction Control – Jumper E1 should be OFF if the board is to use its
own internally generated phase and servo clock signals. In this case, these signals are output on spare
pins on the J8 RS-232 serial-port connector, where they can be used by other PMAC controllers set up to
take external phase and servo clock signals.

Jumper E1 should be ON if the board is to use externally generated phase and servo clock signals brought
in on the J8 RS-232 serial port connector. In this case, typically the clock signals are generated by
another PMAC controller and output on its serial port connector.

If E1 is ON for external phase and clock signals, and these clock signals are not brought in on the serial
port connector, the watchdog timer will trip almost immediately and shut down the board.

E2 and E4: CPU Frequency Control Jumpers – When the PMAC I46 I- variable is set to zero jumpers
E2 and E4 on the base PMAC2A PC/104 board control the frequency at which the CPU will operate (or
attempt to operate). Generally, this will be the highest frequency at which the CPU is rated to operate.
Note that it is always possible to operate a CPU at a frequency lower than its maximum rating. While it
may be possible to operate an individual processor at a frequency higher than its maximum rating,
particularly at low ambient temperatures, performance cannot be guaranteed at such a setting, and this
operation is done completely at the user’s own risk.

• If jumpers E2 and E4 are both OFF, the CPU will operate at a 40 MHz frequency.

• If E2 is ON and E4 is OFF, the CPU will operate at a 60 MHz frequency.

• If E2 is OFF and E4 is ON, the CPU will operate at an 80 MHz frequency.

If I46 is set to a value greater than 0, the operational frequency is set to 10MHz * (I46 + 1), regardless of
the jumper setting. See the Software Setup section for details on this.

E8: Phase Clock Lines Output Enable – Jump pin 1 to 2 to enable the Phase clock line on the J8
connector. Remove jumper to disconnect the Phase clock line on the J8 connector.

E9: Servo Clock Lines Output Enable – Jump pin 1 to 2 to enable the Servo clock line on the J8
connector. Remove jumper to disconnect the Servo clock line on the J8 connector.

Reset Jumpers

E0: Forced Reset Control – Remove E0 for normal operation. Installing E0 forces PMAC to a reset
state, this configuration is for factory use only; the board will not operate with E0 installed.

E3: Re-Initialization on Reset Control – If E3 is OFF (default), PMAC executes a normal reset,
loading active memory from the last saved configuration in non-volatile flash memory. If E3 is ON,
PMAC re-initializes on reset, loading active memory with the factory default values.

E13: Firmware Load Jumper – If jumper E13 is ON during power-up/reset, the board comes up in
bootstrap mode which permits loading of firmware into the flash-memory IC. When the PMAC
Executive program tries to establish communications with a board in this mode, it will detect
automatically that the board is in bootstrap mode and ask what file to download as the new firmware.

Jumper E13 must be OFF during power-up/reset for the board to come up in normal operational mode.

Hardware Setup 5

PMAC2A PC104 Hardware Reference Manual

6

CPU Configuration Jumpers

E15A-E15C: Flash Memory Bank Select Jumpers – The flash-memory IC in location U10 on the
PMAC2A PC/104 base board has the capacity for eight separate banks of firmware, only one of which
can be used at any given time. The eight combinations of settings for jumpers E15A, E15B, and E15C
select which bank of the flash memory is used. In the factory production process, firmware is loaded only
into Bank 0, which is selected by having all of these jumpers OFF.

E10-E12: Power-Up State Jumpers – Jumper E10 must be OFF, jumper E11 must be ON, and jumper
E12 must be ON, in order for the CPU to copy the firmware from flash memory into active RAM on power­up/reset. This is necessary for normal operation of the card. (Other settings are for factory use only.)

E14: Watchdog Timer Jumper – Jumper E14 must be OFF for the watchdog timer to operate. This is a
very important safety feature, so it is vital that this jumper be OFF for normal operation. E14 should only
be put ON to debug problems with the watchdog timer circuit.

W1: Flash chip select – Jumper W1 in position 1-2 selects a 28F320J3A part for the U10 flash chip.
Jumper W1 in position 2-3 selects a 28F320J5A part for the U10 flash chip. This jumper is installed in
the factory and must not be changed from its default state.

Communication Jumpers

E18-E19: PC/104 Bus Base Address Control – Jumpers E18 and E19 on the PMAC2A PC/104 CPU
determine the base address of the card in the I/O space of the host PC. Together, they specify four
consecutive addresses on the bus where the card can be found. The jumpers form the base address in the
following fashion:

E18 E19 Address (hex) Address (dec.)

OFF OFF $200 512
OFF ON $210 528

ON OFF $220 544
ON ON $230 560

The default base address is 528 ($210) formed with jumper E18 removed and E19 installed. This setting
is necessary when using the USB or Ethernet ports of the Acc-2P communications board.

ADC Configuration Jumpers

E16: ADC Enable Jumper – Install E16 to enable the analog-to-digital converter circuitry ordered
through Option-12. Remove this jumper to disable this option, which might be necessary to control
motor 1 through a digital amplifier with current feedback.

Encoder Configuration Jumpers

E20-E23: Encoder Single Ended/Differential Select – PMAC has differential line receivers for each
encoder channel, but can accept either single-ended (one signal line per channel) or differential (two
signal lines, main and complementary, per channel). A jumper for each encoder permits customized
configurations, as described below.

Single-Ended Encoders

With the jumper for an encoder set for single-ended, the differential input lines for that encoder are tied to

2.5V; the single signal line for each channel is then compared to this reference as it changes between 0
and 5V.

When using single-ended TTL-level digital encoders, the differential line input should be left open, not
grounded or tied high; this is required for The PMAC differential line receivers to work properly.

Differential Encoders

Differential encoder signals can enhance noise immunity by providing common-mode noise rejection.
Modern design standards virtually mandate their use for industrial systems, especially in the presence of
PWM power amplifiers, which generate a great deal of electromagnetic interference.

Hardware Setup

PMAC2A PC104 Hardware Reference Manual

Connect pin 1 to 2 to tie differential line to +2.5V

• Tie to +2.5V when no connection

• Tie to +2.5V for single-ended encoders

Connect pin 2 to 3 to tie differential line to +5V

• Don’t care for differential line driver encoders

• Tie to +5V for complementary open-collector encoders (obsolete)

Hardware Setup 7

PMAC2A PC104 Hardware Reference Manual

Hardware Setup

8

PMAC2A PC104 Hardware Reference Manual

MACHINE CONNECTIONS

Typically, the user connections are made to terminal blocks that attach to the JMACH connectors by a
flat cable. The following are the terminal blocks recommended for connections:

• 34-Pin IDC header to terminal block breakouts (Phoenix part number 2281063) Delta Tau

part number 100-FLKM34-000

• 50-Pin IDC header to terminal block breakouts (Phoenix part number 2281089) Delta Tau

part number 100-FLKM50-000

Mounting

The PMAC2A PC/104 is typically installed using standoffs when stacked
to a PC/104 computer or as a stand-alone controller. At each of the four
corners of the PMAC2A PC/104 board, there are mounting holes that can
be used for this.

The PMAC2A PC/104 CPU is placed always at the bottom of the stack.
The order of the Acc-1P or Acc-2P with respect to the CPU does not
matter.

Power Supplies

Baseboard mounted at
the bottom of the stack

Digital Power Supply

3A @ +5V (±5%) (15 W) with a minimum 5 msec rise time
(Eight-channel configuration, with a typical load of encoders)
The PMAC2A PC/104, the Acc-1P and the Acc-2P each require a 1A @ 5VDC power supply for

operation. Therefore, a 3A @ 5VDC power supply is recommended for a PMAC2A PC/104 board
stack with Acc-1P and Acc-2P boards.

• The host computer provides the 5 Volts power when installed in the PC/104 bus and cannot

be disconnected. In this case, there must be no external +5V supply, or the two supplies will
"fight" each other, possibly causing damage. This voltage could be measured on the TB1
terminal block or the JMACH1 connector.

• In a stand-alone configuration, when PMAC is not plugged in a computer bus, it will need an

external 5V supply to power its digital circuits. The 5V power supply can be brought in
either from the TB1 terminal block or from the JMACH1 connector.

• When an ACC-2P is used, a minimum rise time of 5 msec is a requirement of the power

supply. In addition, the power supply ramp-down time should not exceed 20 msec. While
solutions to this issue can involve complex circuitry that minimizes power loss during normal
operation, the simplest method of quickly bringing down the power rail is to add a bleed­down resistor between VCC and GND. The resistor should be large enough that it does not
cause unnecessary power consumption, while still discharging the bulk capacitance as
quickly as possible. Specific resistor values will depend on the overall design of the system,
but in general the voltage drop-off time should not exceed 20 msec. A value that has been
found to work for some systems is 18k.

DAC Outputs Power Supply

0.3A @ +12 to +15V (4.5W)

0.25A @ -12 to -15V (3.8W)
(Eight-channel configuration)

• The host computer provides the ±12 Volts power supply in the case PMAC is installed in the

PC/104 bus. With the board stack into the bus, it will pull ±12V power from the bus
automatically and it cannot be disconnected. In this case, there must be no external ±12V

Machine Connections 9

PMAC2A PC104 Hardware Reference Manual

0

supply, or the two supplies will fight each other, possibly causing damage. This voltage
could be measured on the TB1 terminal block.

• In a stand-alone configuration, when PMAC is not plugged in a computer bus, it will need an

external ±12V supply only when the digital-to-analog converter (DAC) outputs are used. The
±12V lines from the supply, including the ground reference, can be brought in either from the
TB1 terminal block or from the JMACH1 connector.

Flags Power Supply

Each channel of PMAC has five dedicated digital inputs on the machine connector: PLIMn, MLIMn
(overtravel limits), HOMEn (home flag), FAULTn (amplifier fault), and USERn. A power supply
from 5 to 24V must be used to power the circuits related to these inputs. This power supply can be
the same used to power PMAC and can be connected from the TB1 terminal block or the JMACH1
connector.

Overtravel Limits and Home Switches

When assigned for the dedicated uses, these signals provide important safety and accuracy functions.
PLIMn and MLIMn are direction-sensitive over-travel limits that must conduct current to permit
motion in that direction. If no over-travel switches will be connected to a particular motor, this
feature must be disabled in the software setup through the PMAC Ix25 variable.

Types of Overtravel Limits

PMAC expects a closed-to-ground connection for the limits to not be considered on fault. This
arrangement provides a failsafe condition. Usually, a passive normally close switch is used. If a
proximity switch is needed instead, use a 5 to 24V normally closed to ground NPN sinking type
sensor.

Home Switches

While normally closed-to-ground switches are required for the overtravel limits inputs, the home
switches could be either normally close or normally open types. The polarity is determined by
the home sequence setup, through the I-variables I9n2.

Motor Signals Connections

Incremental Encoder Connection

Each JMACH1 connector provides two +5V outputs and two logic grounds for powering encoders
and other devices. The +5V outputs are on pins 1 and 2; the grounds are on pins 3 and 4. The
encoder signal pins are grouped by number: all those numbered 1 (CHA1+, CHA1-, CHB1+, CHC1+,
etc.) belong to encoder #1. The encoder number does not have to match the motor number, but
usually does. Connect the A and B (quadrature) encoder channels to the appropriate terminal block
pins. For encoder 1, the CHA1+ is pin 5 and CHB1+ is pin 9. If there is a single-ended signal, leave
the complementary signal pins floating – do not ground them. However, if single-ended encoders are
used, check the setting of the resistor packs (see the Hardware Setup section for details). For a
differential encoder, connect the complementary signal lines – CHA1- is pin 7, and CHB1- is pin 11.
The third channel (index pulse) is optional; for encoder 1, CHC1+ is pin 13, and CHC1- is pin 15.

Machine Connections

1

PMAC2A PC104 Hardware Reference Manual

Example: differential quadrature encoder connected to channel #1:

DAC Output Signals

If PMAC is not performing the commutation for the motor, only one analog output channel is
required to command the motor. This output channel can be either single-ended or differential,
depending on what the amplifier is expecting. For a single-ended command using PMAC channel 1,
connect DAC1+ (pin 29) to the command input on the amplifier. Connect the amplifier’s command
signal return line to PMAC’s GND line (pin 48). In this setup, leave the DAC1- pin floating; do not
ground it.

For a differential command using PMAC channel 1, connect DAC1 (pin 29) to the plus-command
input on the amplifier. Connect DAC1- (pin 31) to the minus-command input on the amplifier.
PMAC’s GND should still be connected to the amplifier common.

Any analog output not used for dedicated servo purposes may be utilized as a general-purpose analog
output by defining an M-variable to the command register, then writing values to the M-variable. The
analog outputs are intended to drive high-impedance inputs with no significant current draw. The
220Ω output resistors will keep the current draw lower than 50 mA in all cases and prevent damage to
the output circuitry, but any current draw above 10 mA can result in noticeable signal distortion.

Example:

Pulse and Direction (Stepper) Drivers

The channels provided by the PMAC2A PC/104 board or the Acc-1P board can output pulse and
direction signals for controlling stepper drivers or hybrid amplifiers. These signals are at TTL levels.

Amplifier Enable Signal (AENAx/DIRn)

Most amplifiers have an enable/disable input that permits complete shutdown of the amplifier
regardless of the voltage of the command signal. PMAC’s AENA line is meant for this purpose.
AENA1- is pin 33. This signal is an open-collector output and an external 3.3 kΩ pull-up resistor can
be used if necessary.

Machine Connections 11

PMAC2A PC104 Hardware Reference Manual

Amplifier Fault Signal (FAULT-)

This input can take a signal from the amplifier so PMAC knows when the amplifier is having
problems, and can shut down action. The polarity is programmable with I-variable Ix25 (I125 for
motor 1) and the return signal is ground (GND). FAULT1- is pin 35. With the default setup, this
signal must actively be pulled low for a fault condition. In this setup, if nothing is wired into this
input, PMAC will consider the motor not to be in a fault condition.

Optional Analog Inputs

The optional analog-to-digital converter inputs are ordered either through Option-12 on the CPU or
Option-2 on the axes expansion board. Each option provides two 12-bit analog inputs analog inputs
with a ±10Vdc range.

Compare Equal Outputs

The compare-equals (EQU) outputs have a dedicated use of providing a signal edge when an encoder
position reaches a pre-loaded value. This is very useful for scanning and measurement applications.
Instructions for use of these outputs are covered in detail in the PMAC2 User Manual.

Serial Port (JRS232 Port)

For serial communications, use a serial cable to connect your PC's COM port to the J8 serial port
connector present on the PMAC2A PC/104 CPU. Delta Tau provides the Acc-3L cable for this
purpose that connects the PMAC to a DB-9 connector. Standard DB-9-to-DB-25 or DB-25-to-DB-9
adapters may be needed for your particular setup.

Machine Connections

12

PMAC2A PC104 Hardware Reference Manual

If a cable needs to be made, the easiest approach is to use a flat cable prepared with flat-cable type
connectors as indicated in the following diagram:

PMAC (DB-9S) PC (DB-9)

1 (No connect) 1 (No connect)

DB-9 Female DB-9 Male

1 1

2 (TXD/) 2 (RXD)
3 (RXD/) 3 (TXD)

4 (DSR) 4 (DTR)

5 (Gnd) 5 (Gnd)
6 (DTR) 6 (DSR)
7 (CTS) 7 (RTS)
8 (RTS) 8 (CTS)

9 (No connect) 9 (No connect)

Machine Connections Example: Using Analog ±10V Amplifier

Machine Connections 13

PMAC2A PC104 Hardware Reference Manual

4

Machine Connections Example: Using Pulse and Direction Drivers

Machine Connections

1

PMAC2A PC104 Hardware Reference Manual

SOFTWARE SETUP

Note:

The PMAC2A PC/104 requires the use of V1.17 or newer firmware. There are
few differences between the previous V1.16H firmware and the V1.17 firmware
other than the addition of internal support for the Flex CPU design.

PMAC I-Variables

PMAC has a large set of Initialization parameters (I-variables) that determine the "personality" of the card
for a specific application. Many of these are used to configure a motor properly. Once set up, these
variables may be stored in non-volatile EAROM memory (using the SAVE command) so the card is
always configured properly (PMAC loads the EAROM I-variable values into RAM on power-up).

The programming features and configuration variables for the PMAC2A PC/104 are described fully in the
PMAC2 User and Software manuals.

Communications

Delta Tau provides software tools that allow communicating with of the PMAC2A PC/104 board by
either its standard RS-232 port or the optional USB or Ethernet ports. PEWIN is the most important in
the series of software accessories, and it allows configuring and programming the PMAC for any
particular application.

Operational Frequency and Baud Rate Setup

Note:

Older PMAC boards required a start-up PLC for setting the operational frequency
at 80 MHz. That method is not compatible with the PMAC2A PC/104 board and
will shutdown the board when used.

The operational frequency of the CPU can be set in software by the variable I46. If this variable is set to
0, PMAC firmware looks at the jumpers E2 and E4 to set the operational frequency for 40, 60, and 80
MHz operation. If I46 is set to a value greater than 0, the operational frequency is set to 10MHz * (I46 +

1), regardless of the jumper setting. If the desired operational frequency is higher than the maximum
rated frequency for that CPU, the operational frequency will be reduced to the rated maximum. It is
always possible to operate the Flex CPU board at a frequency below its rated maximum. I46 is used only
at power-up/reset, so to change the operational frequency, set a new value of I46, issue a SAVE command
to store this value in non-volatile flash memory, then issue a $$$ command to reset the controller.

To determine the frequency at which the CPU is actually operating, issue the TYPE command to the
PMAC. The PMAC will respond with five data items, the last of which is CLK Xn, where n is the
multiplication factor from the 20 MHz crystal frequency (not 10 MHz). n should be equivalent to
(I46+1)/2 if I46 is not requesting a frequency greater than the maximum rated for that CPU board. n will
be 2 for 40 MHz operation, 4 for 80 MHz operation, and 8 for 160 MHz operation.

Software Setup 15

PMAC2A PC104 Hardware Reference Manual

If the CPU’s operational frequency has been determined by (a non-zero setting of) I46, the serial
communications baud rate is determined at power-up/reset by variable I54 alone according to the
following table:

I54 Baud Rate I54 Baud Rate

0 600 8 9600
1 900 9 14,400
2 1200 10 19,200
3 1800 11 28,800
4 2400 12 38,400
5 3600 13 57,600
6 4800 14 76,800
7 7200 15 115,200

For a saved value of 0 for I46, the serial baud rate is determined by the combination of I54 and the CPU
frequency as shown in the following table.

I54

0 600 Disabled 1200
1 900* (-0.05%) 900 1800* (-0.1%)
2 1200 1200 2400
3 1800* (-0.1%) 1800 3600* (-0.19%)
4 2400 2400 4800
5 3600* (-0.19%) 3600 7200* (-0.38%)
6 4800 4800 9600
7 7200* (-0.38%) 7200 14,400*(-0.75%)
8 9600 9600 19,200

9 14,400*(-0.75%) 14,400 28,800*(-1.5%)
10 19,200 19,200 38,400
11 28,800*(-1.5%) 28,800 57,600*(-3.0%)
12 38,400 38,400 76,800
13 57,600*(-3.0%) 57,600 115,200*(-6.0%)
14 76,800 76,800 153,600
15 Disabled 115,200 Disabled

* Not an exact baud rate

Baud Rate for

40 MHz CPU

Baud Rate for

60 MHz CPU

Baud Rate for

80 MHz CPU

Filtered DAC Output Configuration

The PMAC2 PC104 is a PMAC2 style board with default +/-10V outputs produced by filtering a PWM
signal. This technique has been used been for some time now by many of our competitors. Although this
technique does not contain the same levels of performance as a true Digital to Analog converter, for most
servo applications it is more than adequate. Many of our customers using this product have migrated over
from the PMAC1 style board with a true 16-bit DAC. This document is meant for explaining the
tradeoffs of PWM frequency vs. resolution in the PMAC2PC104 base configuration as well as a
comparison to the PMAC1 style 16 bit DACs.

Both the resolution and the frequency of the Filtered PWM outputs are configured in software on the
PMAC2PC104 through the variable I900. This I900 variable also effects the phase and servo interrupts.
Therefore as we change I900 we will also have to change I901 (phase clock divider), I902 (servo clock
divider), and I10 (servo interrupt time). These four variables are all related and must be understood
before adjusting parameters.

Software Setup

16

PMAC2A PC104 Hardware Reference Manual

Since the PMAC2PC104 uses standard PMAC2 firmware the following I-variables must be set properly
to use the digital-to-analog (filtered DAC) outputs:

I900 = 1001 ; PWM frequency 29.4kHz, PWM 1-4
I901 = 5 ; Phase Clock 9.8059kHz
I902 = 3 ; Servo frequency 2.451kHz
I903 = 1746 ; ADC frequency
I906 = 1001 ; PWM frequency 29.4kHz, PWM 5-8
I907 = 1746 ; ADC frequency
I9n6 = 0 ; Output mode: PWM
Ix69 = 1001 ; DAC limit 10Vdc
I10 = 3421867 ; Servo interrupt time

n = channel number from 1 to 8
x = motor number from 1 to 8

Parameters to Set up Global Hardware Signals

I900

I900 determines the frequency of the MaxPhase clock signal from which the actual phase clock
signal is derived. It also determines the PWM cycle frequency for Channels 1 to 4. This variable
is set according to the equation:

I900 = INT[117,964.8/(4*PWMFreq(KHz)) - 1]

The PMAC2 PC/104 filtered PWM circuits were optimized for 30KHz. I900 should be set to
1088 (calculated as 27.06856KHz)

I901

I901 determines how the actual phase clock is generated from the MaxPhase clock, using the
equation:

PhaseFreq(kHz) = MaxPhaseFreq(kHz)/(I901+1)

I901 is an integer value with a range of 0 to 15, permitting a division range of 1 to 16. Typically,
the phase clock frequency is in the range of 8 kHz to 12 kHz. 9KHz is standard, set I901 = 5
(calculated as 9.02285 KHz).

I902

I902 determines how the servo clock is generated from the phase clock, using the equation:

ServoFreq(KHz) = PhaseFreq(KHz)/(I902+1)

I902 is an integer value with a range of 0 to 15, permitting a division range of 1 to 16. On the
servo update, which occurs once per servo clock cycle, PMAC2 updates commanded position
(interpolates) and closes the position/velocity servo loop for all active motors, whether or not
commutation and/or a digital current loop is closed by PMAC2. Typical servo clock frequencies
are 1 to 4 kHz. The PMAC standard is 2.26 KHz, set I902 = 3 (calculated as 2.25571 KHz).

I10 tells the PMAC2 interpolation routines how much time there is between servo clock cycles. It
must be changed any time I900, I901, or I902 is changed. I10 can be set according to the
formula:

I10 = (2*I900+3)(I901+1)(I902+1)*640/9

I10 should be set to 3718827.

Software Setup 17

PMAC2A PC104 Hardware Reference Manual

I903

I903 determines the frequency of four hardware clock signals used for machine interface channels 1-4;
This can be left at the default value (I903=*). The four hardware clock signals are SCLK (encoder sample
clock), PFM_CLK (pulse frequency modulator clock), DAC_CLK (digital-to-analog converter clock),
and ADC_CLK (analog-to-digital converter clock).

Parameters to Set Up Per-Channel Hardware Signals

I9n6

I9n6 is the output mode; “n” is the output channel number (i.e. for channel 1 the variable to set would be
i916, i926 for channel 2 etc.). On Pmac1 there is only one output and one output mode, DAC output. On
PMAC2 boards, each channel has 3 outputs, and there are 4 output modes. Since this is board was
designed to output filtered PWM signals we want to configure at least the first output as PWM. Therefore
the default value of 0 is the choice. For information on this variable consult the PMAC1/PMAC2
software reference manual.

Ix69

Ix69 is the motor output command limit. The analog outputs on PMAC1 style boards and some PMAC2
accessories are 16-bit DACs, which map a numerical range of -32,768 to +32,767 into a voltage range of ­10V to +10V relative to analog ground (AGND). For our purposes of a filtered PWM output this value
still represents the maximum voltage output; however the ratio is slightly different. With a true DAC,
Ix69=32767 allows a maximum voltage of 10V output. With the filtered PWM circuit, Ix69 is a function
of I900. A 10V signal in the output register is no longer 32767 as was in PMAC1, a 10V signal is
corresponds to a value equal to I900. Anything over I900 will just rail the Dac at 10V. For Example:

Desired Maximum Output Value = 6V

Ix69=6/10 * i900

Desired Maximum Output Value = 10V

Ix69= I900 + 10 ; add a little headroom to assure a full 10V

Effects of Changing I900 on the System

It should now be understood that a full 10 volts is output when the output register is equal to i900. The
output register is suggested m-variable Mx02 (I.e. M102-> Y:$C002,8,16,S ; OUT1A command value;
DAC or PWM). With default setting of I900, 10Volts is output when m102 is equal to i900, or 1001.
Since the output register is an integer value the smallest increment of change is about 10mV (1/1001 *
10V). Some users may want to calibrate their analog output using Ix29. Ix29 is an integer similar to
Mx02 except the value is added to the output register every servo cycle to apply a digital offset to the
output register. Therefore the resolution of our output signal affects how Ix29 should be set. As
mentioned earlier, with the default parameters, 1 bit change in the output register changes the analog
output by about 10mV. Therefore if there is an analog output offset less than 5mV, Ix29 cannot decrease
your offset. By increasing I900 you increase your resolution, so if you double i900, 1 bit change in the
output register corresponds to about 5mV. So with Ix29 you can only change the offset in increments of
5mV.

You can see above that by increasing I900 you increase the resolution of our command output register.
This sounds like a good thing, right? There are tradeoffs when you change I900 between resolution and
ripple.

Software Setup

18

PMAC2A PC104 Hardware Reference Manual

By increasing I900 we are essentially decreasing our PWM Frequency. The two are related by the
following equation:

I900 = INT[117,964.8/(4*PWMFreq(KHz)) - 1]

Passing the PWM signal through a 10KHz low pass filter creates the +/-10V signal output. The duty
cycle of the PWM signal is what generates the magnitude the voltage output. The frequency of the PWM
signal determines the magnitude and frequency of ripple on that +/-10V signal. As you lower the PWM
frequency and subsequently increase your output resolution, you increase the magnitude of the ripple as
well as slow down the frequency of the ripple as well. Depending on the system, this ripple can affect
performance at different levels.

So what do we mean by ripple? Ripple is the small signal that will you will see on top of the +/-10V
signal if you put an oscilloscope on it. In other words if I command a 4V signal out of the PMAC2PC104
and scope it, I will see a small sinusoidal type wave centered on 4V. At the default PWM frequency and
output resolution this will have a magnitude of about 230mV and a frequency of about 33kHz. This is
typically faster than any of the control loops so the amplifier essentially filters it out of the system.

Say I wanted to double the resolution of my output signal, I would merely double my I900 value from
1001 to 2002. How does this affect the ripple? From a test I calculated the ripple magnitude to increase
from around 230mV to about 700mV. The frequency of the ripple decreased from about @30kHz to
@15kHz. Here are some measurements taken with a PMAC2PC104:

I900 Value Output

Resolution

Signed

1001 @11 bit 9.9mV 29.4177 KHz 230mV 30KHz

2002 @12 bit 4.99mV 14.72 Khz 700mV 15KHz

4004 @13bit 2.49mV 7.36 Khz 2V 7Khz

Voltage

Output Change

Per 1bit increment

In output register

PWM

Frequency

Approximate

Ripple

Magnitude

Approximate

Ripple

Frequency

How does the ripple affect servo performance? It really depends on the system. For most servo systems
the mechanics can’t respond anywhere near these frequencies. Some systems with linear amplifiers it will
effect the performance especially as you lower the PWM frequency and effectively the ripple frequency,
i.e. galvanometers, etc. In the overall majority of the servo world, these ripple frequencies will not show
in the system due to mechanical and electrical time constants of most systems. This will happen
regardless of the amplifier used.

So why is the recommended setup for 30KHz? A few reasons, the first is aesthetics. Nobody wants to
put a scope on an output signal and see 1 or 2V of hash. If you increase that frequency the hash is
minimized. The second reason is response of the output with respect to the servo filter. If you increase
the output resolution and thus lower the PWM frequency far enough you will notice some lag in the
system from the delays between the output register value actually being picked up by the slower PWM
frequency.

For high response systems we suggest using Acc8es and a true 18bit DAC. However the filtered PWM
technique will be more than adequate for most applications.

Software Setup 19

PMAC2A PC104 Hardware Reference Manual

0

How does changing I900 effect other settings in PMAC

I900 is does not only set the PWM frequency for the PWM outputs but it also sets the Max Phase
Frequency.

MaxPhase Frequency = 117,964.8 kHz / [2*I900+3]

PWM Frequency = 117,964.8 kHz / [4*I900+6]

The Max Phase Frequency is then divided by I901 to generate the frequency for the phase interrupt and its
routines. If you change I900 you have to change I901 to keep the same phase interrupt.

PHASE Clock Frequency = MaxPhase Frequency / (I901+1)

The Phase Clock Frequency setting also effects the servo interrupt frequency. If you change the phase

interrupt frequency then you must change I902 to keep the same servo interrupt.

Servo Clock Frequency = PHASE Clock Frequency / (I902+1)

When you change the servo interrupt you must always change the servo interrupt time, i10, to match or all
of your timing will be off in PMAC.

I10=8388608/(Servo Frequency (KHz)) = 8388608 * ServoTime(msec)

If you decide to change I900 be sure to reset Ix69 to the proper safety setting per the following formula:

Ix69=MaxVolts/10 * I900

Examples:

Default Example:

I900=1001

I901=2

I902=3

Ix69=1024

I10=1710933

MaxPhase Frequency = 117,964.8 kHz / [2*1001+3] = 58.835KHz

PWM Frequency = 117,964.8 kHz / [4*1001+6] = 29.418KHz

PHASE Clock Frequency = MaxPhase Frequency / (2+1) = 19.61KHz

Servo Clock Frequency = PHASE Clock Frequency / (3+1) = 4.90KHz

I10=8388608/(4.902943) = 1710933

Ix69=10V/10 * I900 = 1001 add headroom to 1024

Now lets say I wanted to double my resolution:

I900=2002

MaxPhase Frequency = 117,964.8 kHz / [2*2002+3] = 29.44KHz

PWM Frequency = 117,964.8 kHz / [4*2002+6] = 14.72KHz

In order to save headroom on firmware routines that trigger off the phase and servo interrupts it is best to
keep those frequencies about the same as above. Some systems may want higher phase and servo

Software Setup

2

PMAC2A PC104 Hardware Reference Manual

interrupt frequencies for better servo performance, but our default frequencies are typically more than fast
enough for many applications. We will discuss tuning parameter a bit later in this document.

I901= 29.44KHz/19.61KHz -1 = @0.5 set it at 1 or 14.72KHz

This is not exactly the same since I901 is an integer value but pretty close. Since we are doing any
commutation with a +/-10V signal it doesn’t make that much of a difference. The Servo Frequency we
will be able to get close though:

I902=14.72KHz/4.9 – 1 = 2.004 or 2 which is @4.9KHz

For a 10V max signal output:

Ix69=i900 + headroom = 2024

We must set I10 whenever we change the servo clock but since we kept it basically the same, I19 stays
pretty much the same. Without rounding it works out to the following:

I10 = 8388608/4.906613 = 1709653

For precise timing within your motion application it is important not to round off when calculating I10.

Effects of Output Resolution and Servo Interrupt Frequency on Servo
Gains

When you change your output resolution and/or servo interrupt timing your tuning parameters will no
longer respond the same. The system will have to be tuned again in order to achieve the desired
performance. There is an approximate relation of output resolution to servo loop gains . If you were
switching an application from a PMAC style 16bit Dac to a PMAC2Pc104 with default resolution of
about 11bits you can expect a change of your gains in order to get similar response.

The max output value of the output command with a 16bit Dac is 32767. With the PMAC2Pc104 at its
default parameters the max output value is 1001. If you had equal servo interrupt frequencies the
proportional gain on the PC104 system would have a proportional gain 1001/32767 or about 1/32 smaller.
This is more a rule of thumb than an exact formula. It is always recommended to go through a full tuning
procedure when changing output resolution.

If you decide to change the Servo Interrupt Frequency, then you are also changing the dynamics of the
servo filter and thus the system. You will need to retune the system in order to get the desired
performance. If you increase the servo frequency you will need to lower the proportional gain in order to
achieve similar performance. The reason you increased the frequency in the first place was more likely to
achieve a higher performance so relations here are not very helpful.

If you desire to change servo interrupt frequency in order to have your foreground PLCs execute more
often you can also adjust Ix60 to keep your gains the same, see the Pmac1/2 Software Reference Manual
for a further description of this parameter.

Software Setup 21

PMAC2A PC104 Hardware Reference Manual

Using Flag I/O as General-Purpose I/O

Either the user flags or other not assigned axes flag on the base board can be used as general-purpose I/O
for up to 20 inputs and 4 outputs at 5-24Vdc levels. The indicated suggested M-variables definitions,
which are defined in the PMAC2 Software reference, allows accessing each particular line according to
the following table:

Flag Type

HOME

PLIM

MLIM

USER

AENA

5-24 VDC Input M120 M220 M320 M420
5-24 VDC Input M121 M221 M321 M421
5-24 VDC Input M122 M222 M322 M422
5-24 VDC Input M115 M215 M315 M415

5-24 VDC Output M114 M214 M314 M414

#1 #2 #3 #4

Channel Number

Note:

When using these lines as regular I/O points the appropriate setting of the Ix25
variable must be used to enable or disable the safety flags feature.

Analog Inputs Setup

The optional analog-to-digital converter inputs are ordered either through Option-12 on the CPU or Option­2 on the axes expansion board. Each option provides two 12-bit analog inputs with a ±10Vdc range. The
M-variables associated with these inputs provided a range of values between +2048 and –2048 for the
respective ±10Vdc input range. The following is the software procedure to setup and read these ports.

CPU Analog Inputs

I903 = 1746 ;Set ADC clock frequency at 4.9152 MHz
WX:$C014, $1FFFFF ;Clock strobe set for bipolar inputs
M105->X:$0710,12,12,S ;ADCIN_1 on JMACH1 connector pin 45
M205->X:$0711,12,12,S ;ADCIN_2 on JMACH1 connector pin 46

Software Setup

22

PMAC2A PC104 Hardware Reference Manual

HARDWARE REFERENCE SUMMARY

The following information is based on the PMAC2A PC/104 board, part number 603670-100.

Board Dimensions

From v106 to 107

(E20-23 added and 15A is in a different location:

Hardware Reference Summary 23

PMAC2A PC104 Hardware Reference Manual

4

From v107 to 108

W1 removed:

Hardware Reference Summary

2

PMAC2A PC104 Hardware Reference Manual

From v108 to 109

E20 in same location but rotated 90 degrees:

Hardware Reference Summary 25

PMAC2A PC104 Hardware Reference Manual

Board Layout

1

2

3

4

5

6

BACD E F

Feature Location Feature Location Feature Location

E0
E1
E2
E3
E4
E8

E9
E10
E11
E12

B3
B4
B4
C4
C4
B1
B1
E5
E5
E5

E13

E14
E15A
E15B
E15C

E16

E18

E19

W1

E5
B3
E4
E4
E4
D1
D4
D4
E6

RP30
RP31
RP36
RP37

D1
D2

TB1

JRS232
JMACH1
JMACH2

E2
E2
E3
E3
A2
A3
B6
A2
F3
A4

Hardware Reference Summary

26

PMAC2A PC104 Hardware Reference Manual

Connectors and Indicators

J3 - Machine Connector (JMACH1 Port)

The primary machine interface connector is JMACH1, labeled J3 on the PMAC. It contains the pins for
four channels of machine I/O: analog outputs, incremental encoder inputs, amplifier fault and enable
signals and power-supply connections.

1. 50-pin female flat cable connector T&B Ansley P/N 609-5041

2. Standard flat cable stranded 50-wire T&B Ansley P/N 171-50

3. Phoenix varioface module type FLKM 50 (male pins) P/N 22 81 08 9

J4 - Machine Connector (JMACH2 Port)

This machine interface connector is labeled JMACH2 or J4 on the PMAC. It contains the pins for four
channels of machine I/O: end-of-travel input flags, home flag and pulse-and-direction output signals. In
addition, the B_WDO output allows monitoring the state of the Watchdog safety feature.

1. 34-pin female flat cable connector T&B Ansley P/N 609-3441

2. Standard flat cable stranded 34-wire T&B Ansley P/N 171-34

3. Phoenix varioface module type FLKM 34 (male pins) P/N 22 81 06 3

J8 - Serial Port (JRS232 Port)

This connector allows communicating with PMAC from a host computer through a RS-232 port. Delta
Tau provides the Accessory 3L cable that connects the PMAC to a DB-9 connector.

1. 10-pin female flat cable connector T&B Ansley P/N 609-1041

2. Standard flat cable stranded 10-wire T&B Ansley P/N 171-10

TB1 – Power Supply Terminal Block (JPWR Connector)

In almost in all cases the PMAC2A PC/104 will be powered from the PC/104 bus, when it is installed in a
host computer’s bus, or from the JMACH1 connector. This terminal block may be used as an alternative
power supply connector or to easily measure the voltages applied to the board.

1. 4-pin terminal block, 0.150 pitch

LED Indicators

D1: when this red LED is lit, it indicates that the watchdog timer has tripped and shut down the PMAC.
D2: when this green LED is lit, it indicates that power is applied to the +5V input.

Hardware Reference Summary 27

PMAC2A PC104 Hardware Reference Manual

Hardware Reference Summary

28

PMAC2A PC104 Hardware Reference Manual

E-POINT JUMPER DESCRIPTIONS

E0: Forced Reset Control

E Point and

Physical Layout

E0

Location Description Default

B3 Factory use only; the board will not operate

with E0 installed.

E1: Servo and Phase Clock Direction Control

E Point and

Physical Layout

E1

If the E1 jumper is ON and the servo and phase clocks are not brought in on the J8
serial port, the watchdog timer will trip immediately.

Location Description Default

B4 Remove jumper for PMAC to use its

internally generated servo and phase clock
signals and to output these signals on the J8
serial port connector.

Jump pins 1 and 2 for PMAC to expect to
receive its servo and phase clock signals on
the J8 serial port connector.

Note:

E2: CPU Frequency Select

No jumper

No jumper installed

E Point and

Physical Layout

E2

Location Description Default

B4 Remove jumper for 40 MHz operation (E4

OFF also) or for 80 MHz operation (E4
ON).

Jump pin 1 to 2 for 60 MHz operation (E4
OFF).

E3: Normal/Re-Initializing Power-Up/Reset

E Point and Physical

Layout

E3

Location Description Default

C4 Jump pin 1 to 2 to re-initialize on power-

up/reset, loading factory default settings.

Remove jumper for normal power-up/reset,
loading user-saved settings.

No jumper installed

No jumper installed

E-Point Jumper Descriptions 29

PMAC2A PC104 Hardware Reference Manual

E4: CPU Frequency Select

E Point and

Physical Layout

E4

Location Description Default

C4 Remove jumper for 40 MHz operation (E2

OFF also) or for 60 MHz operation (E4 ON).

Jump pin 1 to 2 for 80 MHz operation (E2
OFF).

E8: Phase Clock Lines Output Enable

E Point and

Physical Layout

E8

Location Description Default

B1 Jump pin 1 to 2 to enable the PHASE clock

line on the J8 connector, allowing
synchronization with another PMAC.

Remove jumper to disable the PHASE clock
line on the J8 connector.

E9: Servo Clock Lines Output Enable

E Point and

Physical Layout

E9

Location Description Default

Jump pin 1 to 2 to enable the SERVO clock
line on the J8 connector, allowing

B1

synchronization with another PMAC.

Remove jumper to disable the SERVO clock
line on the J8 connector.

No jumper installed
(standard or Option 5EF)

Jumper installed (Option
5CF)

No Jumper

No Jumper

E10 – E12: Power-Up State Jumpers

E Point and

Physical Layout

E10

E12

Location Description Default

E5 Remove jumper E10;

Jump E11;
Jump E12;

To read flash IC on power-up/reset
Other combinations are for factory use only;
the board will not operate in any other
configuration.

No E10 jumper installed;

Jump E11 and E12

E-Point Jumper Descriptions

30

PMAC2A PC104 Hardware Reference Manual

E13: Power-Up/Reset Load Source

E Point and

Physical Layout

E13

Location Description Default

E5 Jump pin 1 to 2 to reload firmware through

serial or bus port.

Remove jumper for normal operation.

E14: Watchdog Disable Jumper

E Point and

Physical Layout

E14

Location Description Default

B3 Jump pin 1 to 2 to disable Watchdog timer

(for test purposes only).

Remove jumper to enable Watchdog timer.

E15A, B, C: Flash Memory Bank Select

E Point and

Physical Layout

E15A

Location Description Default

E4 Remove all 3 jumpers to select flash memory

bank with factory-installed firmware.

Use other configuration to select one of the 7
other flash memory banks.

No jumper

No jumper

No jumpers installed

E15C

E16: ADC Inputs Enable

E Point and

Physical Layout

E16

Location Description Default

D1 Jump pin 1 to 2 to enable the Option-12

No jumper

ADC inputs.

Remove jumper to disable the ADC inputs,
which might be necessary for reading
current feedback signals from digital
amplifiers.

E-Point Jumper Descriptions 31

PMAC2A PC104 Hardware Reference Manual

E18 – E19: PC/104 Bus Address

E Point and Physical

Layout

E18

E19

Location Description

D4

Jumpers E18 and E19 select the PC/104 bus
address for communications according to
the following table:

E18 E19

OFF OFF $200 512

OFF ON $210 528

ON OFF $220 544

ON ON $230 560

Address

(Hex)

Address

(Dec)

No E18 jumper installed;

Jumper E19 installed

Default

Note:

Jumper E18 must be removed and jumper E19 must be installed for using either
the Ethernet or USB optional methods of communication.

E20-E23: ENCODER SINGLE ENDED/DIFFERENTIAL SELECT

(Note: v107 and above only)

E Point and

Physical Layout

E20

E21

E22

E23

Location Description Default

Jump pin 2 to 3 to obtain differential

1-2 Jumper installed

encoder input mode. This will bias
encoder negative inputs to VCC = 5V

Jump pin 1 to 2 to obtain non-differential
encoder input mode. This will bias
encoder negative inputs to 1/2 VCC =

2.5V

E-Point Jumper Descriptions

32

PMAC2A PC104 Hardware Reference Manual

CONNECTOR PINOUTS

TB1 (JPWR): Power Supply

(4-Pin Terminal Block)

Top View

Pin# Symbol Function Description Notes

1 GND Common Digital Common
2 +5V Input Logic Voltage Supplies all PMAC digital circuits
3 +12V Input DAC Supply Voltage Ref to Digital GND

4 -12V Input DAC Supply Voltage Ref to Digital GND
This terminal block can be used to provide the input for the power supply for the circuits on the PMAC board
when it is not in a bus configuration. When the PMAC is in a bus configuration, these supplies automatically
come through the bus connector from the bus power supply; in this case, this terminal block should not be used.

J4 (JRS232) Serial Port Connector

(10-PIN CONNECTOR)

Front View

Pin# Symbol Function Description Notes

1 PHASE Output Phasing Clock

2 DTR Bidirect Data Terminal Ready Tied to "DSR"

3 TXD/ Input Receive Data Host transmit data

4 CTS Input Clear to Send Host ready bit

5 RXD/ Output Send Data Host receive data

6 RTS Output Request to Send PMAC ready bit

7 DSR Bidirect Data Set Ready Tied to "DTR"

8 SERVO Output Servo Clock

9 GND Common Digital Common

10 +5V Output +5Vdc Supply Power supply out

Connector Pinouts 33

PMAC2A PC104 Hardware Reference Manual

J3 (JMACH1): Machine Port Connector

(50-Pin Header)

Top View

Pin# Symbol Function Description Notes

1 +5V Output +5V Power For encoders, 1
2 +5V Output +5V Power For encoders, 1
3 GND Common Digital Common For encoders, 1
4 GND Common Digital Common For encoders, 1
5 CHA1 Input Encoder A Channel Positive 2
6 CHA2 Input Encoder A Channel Positive 2
7 CHA1/ Input Encoder A Channel Negative 2,3
8 CHA2/ Input Encoder A Channel Negative 2,3

9 CHB1 Input Encoder B Channel Positive 2
10 CHB2 Input Encoder B Channel Positive 2
11 CHB1/ Input Encoder B Channel Negative 2,3
12 CHB2/ Input Encoder B Channel Negative 2,3
13 CHC1 Input Encoder C Channel Positive 2
14 CHC2 Input Encoder C Channel Positive 2
15 CHC1/ Input Encoder C Channel Negative 2,3
16 CHC2/ Input Encoder C Channel Negative 2,3
17 CHA3 Input Encoder A Channel Positive 2
18 CHA4 Input Encoder A Channel Positive 2
19 CHA3/ Input Encoder A Channel Negative 2,3
20 CHA4/ Input Encoder A Channel Negative 2,3
21 CHB3 Input Encoder B Channel Positive 2
22 CHB4 Input Encoder B Channel Positive 2
23 CHB3/ Input Encoder B Channel Negative 2,3
24 CHB4/ Input Encoder B Channel Negative 2,3
25 CHC3 Input Encoder C Channel Positive 2
26 CHC4 Input Encoder C Channel Positive 2
27 CHC3/ Input Encoder C Channel Negative 2,3
28 CHC4/ Input Encoder C Channel Negative 2,3
29 DAC1 Output Analog Output Positive 1 4
30 DAC2 Output Analog Output Positive 2 4
31 DAC1/ Output Analog Output Negative 1 4,5
32 DAC2/ Output Analog Output Negative 2 4,5
33 AENA1/ Output Amplifier-Enable 1
34 AENA2/ Output Amplifier -Enable 2
35 FAULT1/ Input Amplifier -Fault 1 6
36 FAULT2/ Input Amplifier -Fault 2 6
37 DAC3 Output Analog Output Positive 3 4
38 DAC4 Output Analog Output Positive 4 4
39 DAC3/ Output Analog Output Negative 3 4,5

34 Connector Pinouts

PMAC2A PC104 Hardware Reference Manual

J3 JMACH1 (50-Pin Header)

(Continued)

Top View

Pin# Symbol Function Description Notes

40 DAC4/ Output Analog Output Negative 4 4,5
41 AENA3/ Output Amplifier -Enable 3
42 AENA4/ Output Amplifier -Enable 4
43 FAULT3/ Input Amplifier -Fault 3 6
44 FAULT4/ Input Amplifier -Fault 4 6
45 ADCIN_1 Input Analog Input 1 Option-12 required
46 ADCIN_2 Input Analog Input 2 Option-12 required
47 FLT_FLG_V Input Amplifier Fault pull-up V+
48 GND Common Digital Common
49 +12V Input DAC Supply Voltage 7

50 -12V Input DAC Supply Voltage 7
The J3 connector is used to connect PMAC to the first 4 channels (Channels 1, 2, 3, and 4) of servo amps
and encoders.
Note 1: In standalone applications, these lines can be used as +5V power supply inputs to power PMAC’s

digital circuitry.

Note 2: Referenced to digital common (GND). Maximum of ±12V permitted between this signal and its

complement.

Note 3: Leave this input floating if not used (i.e. digital single-ended encoders).
Note 4: ±10V, 10 mA max, referenced to common ground (GND).
Note 5: Leave floating if not used. Do not tie to GND.
Note 6: Functional polarity controlled by variable Ix25. Must be conducting to 0V (usually GND) to

produce a 0 in PMAC software. Automatic fault function can be disabled with Ix25.

Note 7: Can be used to provide input power when the PC/104 bus connector is not being used. When the

bus configuratio is used, these supply voltages automatically come through the bus connector
from the PC power supply.

Connector Pinouts 35

PMAC2A PC104 Hardware Reference Manual

J4 (JMACH2): Machine Port CPU
Connector

(34-Pin Header)

Pin# Symbol Function Description Notes

1 FLG_1_2_V Input Flags 1-2 Pull-Up
2 FLG_3_4_V Input Flags 3-4 Pull-Up
3 GND Common Digital Common
4 GND Common Digital Common
5 HOME1 Input Home-Flag 1 10
6 HOME2 Input Home-Flag 2 10
7 PLIM1 Input Positive End Limit 1 8,9
8 PLIM2 Input Positive End Limit 2 8,9

9 MLIM1 Input Negative End Limit 1 8,9
10 MLIM2 Input Negative End Limit 2 8,9
11 USER1 Input User Flag 1
12 USER2 Input User Flag 2
13 PUL_1 Output Pulse Output 1
14 PUL_2 Output Pulse Output 2
15 DIR_1 Output Direction Output 1
16 DIR_2 Output Direction Output 2
17 EQU1 Output Encoder Comp-Equal 1
18 EQU2 Output Encoder Comp-Equal 2
19 HOME3 Input Home-Flag 3 10
20 HOME4 Input Home-Flag 4 10
21 PLIM3 Input Positive End Limit 3 8,9
22 PLIM4 Input Positive End Limit 4 8,9
23 MLIM3 Input Negative End Limit 3 8,9
24 MLIM4 Input Negative End Limit 4 8,9
25 USER1 Input User Flag 3
26 USER2 Input User Flag 4
27 PUL_3 Output Pulse Output 3
28 PUL_4 Output Pulse Output 4
29 DIR_3 Output Direction Output 3
30 DIR_4 Output Direction Output 4
31 EQU3 Output Encoder Comp-Equal 3
32 EQU4 Output Encoder Comp-Equal 4
33 B_WDO Output Watchdog Out Indicator/driver
34 No Connect

Note 8: Pins marked PLIMn should be connected to switches at the positive end of travel. Pins marked MLIMn

should be connected to switches at the negative end of travel.

Note 9: Must be conducting to 0V (usually GND) for PMAC to consider itself not into this limit. Automatic limit

function can be disabled with Ix25.

Note 10: Functional polarity for homing or other trigger use of HOMEn controlled by Encoder/Flag Variable I9n2.

HMFLn selected for trigger by Encoder/Flag Variable I9n3. Must be conducting to 0V (usually GND) to
produce a 0 in PMAC software.

Front View

36 Connector Pinouts

PMAC2A PC104 Hardware Reference Manual

Connector Pinouts 37

PMAC2A PC104 Hardware Reference Manual

SCHEMATICS

38 Connector Pinouts

PMAC2A PC104 Hardware Reference Manual

Connector Pinouts 39

GND

D2

DSW05

DRQ7

+12V

PA17

SRD0

BB-

T/R-

OF DELTA TAU DATA SYSTEMS INC. ALL RIGHTS TO DESIGNS AND

+12V

A14

D9

SIOR-

TBD_3

CS_4-

E4

21

+

C18

10UF

16V

(TANT)

GND

|Link

RESTDRV

GND

X/Y

DSW04

CS4-

RP5C
1KSIP6I

56

C22

.1UF

OF DELTA TAU DATA SYSTEMS INC. ALL RIGHTS TO DESIGNS AND

+3P3V

GND

D23

SA00

BCTS-

TMS_U6

U36

PI74FCT16245ATA

(TSSOP48)

2
3

5
6

8
9

11
12

46

44
43

41
40

38
37
36

1

4

7

10

47

48

13
14
15
16
17
18
19
20
21
22
23
2425

26

27

28

29

30

31

32

33

34

35

39

42

45

B0
B1

B2
B3

B4
B5

B6
B7

A1

A2
A3

A4
A5

A6
A7
A8

T/R1

GND

VCC

GND

A0

OE1

B8
B9

GND

B10
B11

VCC

B12
B13

GND

B14
B15

T/R2

OE2

A15

A14

GND

A13

A12

VCC

A11

A10

GND

A9

GND

VCC

GND

IRQ12

+5V

GND

PHASE

D5

1SMC5.0AT3

GND

DRQ2

+3P3V

SA06

RP5B

1KSIP6I

3 4

INSTALL `F2' ONLY

TDO

+5V

GND

A1

D5

D13

TCK_U6

SIOR-

A7

SYSCLK

IRQ5

GND

INVENTIONS ARE RESERVED BY DELTA TAU DATA SYSTEMS INC.

PHASE

GND

SA13

BALE

GND

GND

SD00

GND

SMEMW-

GND

RESET

EXTAL

PHA

PHA

RESET

R1

10

CE2

.1UF

*

GND

SD10

BD04_A

BD06_A

SA01

SD04

BOOTEN-

BD05_A

A0

A15

BRST_A-

RP50

3.3KSIP10C

12

3456789 10

U9

SN75240PW

1
2
3
4 5

6

7

8
GND
C
GND
D GND

B

GND

A

DPRCS-

BA06_A

BA09_A

PHASE

SD05

U35C

74ACT14
(SO14)

5 6

RP4

10KSIP10C

1 2

3
4
5
6
7
8
910

GND

GND

SA04

D6

CS4-

A10

CS_4-

U4D

74ACT14

(SO14)

9 8

RP2

3.3KSIP10C

12
3
4
5
6
7
8
9 10

LA21

SERVO

A12

PA18

+

C96

22UF

35V

NOTE2:

E10

TRST-

CPUCLK

BHR/W

CS_0-

ABOVE AGREEMENT.

PWR

LBEN-

RESET-

BSC11

ONLY PURSUANT TO WRITTEN LICENSE OR WRITTEN INSTRUCTIONS

MEMR-

SD05

BD01_A

E14

+3P3V

BRTS-

C35

.01UF

PHA

SA03

A13

E8

2 1

(jisp)

REFRESH-

DACK7-

SHEET2

670-0SH2

A3

BH2

D14

C20

.1UF

M4

HOLE

U4E

74ACT14

(SO14)

11 10

RP3

10KSIP10C

1 2

3
4
5
6
7
8
910

+5V

IRQ14

D21

SA09

SD06

SA11

SA05

A5

DP_RCS-

XIN_1

IRQ7

GND

SA08

BH7

BA08_A

RESET-

A4

BHDS-

PA21

SER

M3

HOLE

U6

ISPLSI2064E-100LT100-PC104

1
2
3
4
5
6
7
8
9

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50 51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100
VCC10
GND
S6
S7
S8
S9
S10
S11
BRCLK

GND

VCCIO

A8

A7

A6

A5

A4

A3

A0

TDI

RESET-

BSCAN-

GND

VCC

CPUCLK

N.C.

N.C.
N.C.
A9
A10
A11
A12
A13
A14
A15
RD­WR­TMS
GND
TDO
DB0
PA16
PA17
PA18
PA19
PA20
PA21
WDTC
PROMCS­N.C.
N.C. GND

VCCIO

IOCS-

CS00-

CS4-

CS1-

CS0-

DPRCS-

VMECS-

TCK

N.C.

Y2

GND

VCC

SYSCLK

GOE0

INRD-

HA0

HA1

HA2

HDS-

HRW

I/O38

GND

VCCIO

N.C.

N.C.

OEL

LBEN-

IOR-

IOW-

SA0

SA1

SA2

SA3

SA4

GOE1

GND

N.C.

SA5

SA6

SA7

SA8

SA9

SA10

SA11

S4

S5

N.C.

N.C.

E2

21

U2

NC7SZ08M5
(SOT23-5)

1

2

4

53

603670-320

B

PMAC-PC104, DSP56311 CPU & PC104 I/O SECTION

Delta Tau Data Systems, Inc.

D

12Monday, July 02, 2001

Title

Size Document Number Rev

Date: Sheet

of

D18

TRANSFERRED FOR ANY REASON. THIS DOCUMENT IS TO BE USED

DSR

LA19
LA18

GND

D3

D2
LED
GRN

+5V

GND

A4

WDO-

PHASE

SIOW-

SA09

XIN_6

CS0-

RXD-

SD14

DACK0-

DACK6-

GND

VCC

-12V

BSCK1

+5V

+5V

GND

VMECS-

A11

C87

.1UF

VR1
LM1117MPX-3.3
MC33269ST-3.3

(SOT-223)

312

IN

GND

OUT

U35D

74ACT14
(SO14)

9 8

+5V

D11

C88

.1UF

POSSESSION OF THIS DOCUMENT INDICATES ACCEPTANCE OF THE

DACK1-

A13

BSTD1

SA07

SA19

RESET-

SA02

BH1

BA10_A

A7

D20

T/R-

LA23

SA12

D19

BD03_A

19.6608Mhz

D4

D17

SOT23

Q4
2N7002

(SOT23)

3

12

THIS DOCUMENT IS THE CONFIDENTIAL PROPERTY OF DELTA TAU

GND

D4

WDO-

RP8

220SIP4X2

1 2
3 4
5 6
7 8

CE1

.1UF

A16

LBEN-

BHA2

E12

2 1

CE3

.1UF

CE4

.1UF

BHACK-

D15

CS_1-

J9

HSIP8NO5

1
2
3
4

6
7
8

MASTER-

+5V

A2

SD06

A17

SYSCLK

BTA

TDO_U6

XIN_3

NOTE1:

A6

BH4

A12

D22

40/60

PA17

C36

.1UF

TP1
GND

D12

BA09_A

X/Y

A0

+

C34
1UF
35V
tant

C44

.1UF

Y1

MHR13FAJ19.6608

(4 PIN SMT)

1

2 3

4

N.C.

GND CLK

VCC

TDI

RD-

BD05_A

SD00

CTS-

SD01

BD03_A

BD07_A

A15

C19

.1UF

E14

21

J8

GND

DRQ5

OEL

SA05

SD07

BA06_A

D0

TCK_U1

BHA0

SA18

D20

A11

D16

EXTAL

SA10

WDTC

R5
1K

(JRS232)

BD00_A

WR-

PWDO-

CS1-

R4

1K

IOCHCHK-

GND

D11

MODA/IRQA-

BD02_A

D1
LED
RED

DEMAND. TITLE TO THIS DOCUMENT IS NEVER SOLD OR

SD08

SA15

-5V

FLASHCS-

SA10

A3

TDI_U6

BWDO_A-

SD09

+3P3V

+12V

D18

SD02

`VR2,C17,C18'

+5V

TDO_U1

SA02

XIN_5

OEL

RD-

WDO

E9

2 1

C42

.1UF

+

C17

10UF
16V

(TANT)

DRQ1

GND

+5V

A11

PA20

+

C98

22UF

35V

GUARD BAND

DACK5-

GND

D2

RESET

GND

A17

BH3

VR2
LM1117MPX-1.8
MC33269ST-1.8

(SOT-223)

312

IN

GND

OUT

DATA SYSTEMS INC. AND IS LOANED SUBJECT TO RETURN UPON

A2

SC01

BX/Y_A

D19

CTS-

U35A

74ACT14
(SO14)

1 2

+

C97

22UF

35V

C33

.1UF

TC

GND

X/Y

E3

21

DEMAND. TITLE TO THIS DOCUMENT IS NEVER SOLD OR

RTS

-5V

(KEY)

+5V

A4

CS_0-

U35B

74ACT14
(SO14)

3 4

INVENTIONS ARE RESERVED BY DELTA TAU DATA SYSTEMS INC.

AND `DSP56311GC150'

IOCHRDY

BD01_A

BH6

D1

XIN_4

D6

1SMC18AT3

C1

.1UF

TO LOAD `isp' PART

SA16

SA03

CARD0

D13

U8

74HC126C
(SO14)

14

2

5

9

12

1

4

10

13

7

3

6

8

11

VDD

1A

2A

3A

4A

1OE

2OE

3OE

4OE

VSS

1Y

2Y

3Y

4Y

A8

TCK_U6

C40

.1UF

E19

2 1

TXD-

DTR

+3P3V

A12

A13

TDI_U6

TRANSFERRED FOR ANY REASON. THIS DOCUMENT IS TO BE USED

SD12

OSC

D0

SA07

A6

U4A

74ACT14
(SO14)

1 2

WR-

A10

RESET-

TMS_U6

C43

.1UF

IRQ9

+5V

BX/Y_A

SA08

IOCS-

D7

1SMC18AT3

GUARD BAND

TMS

VCCQL

BRST_A-

MODD/IRQD-

A9

E11

2 1

(KEY)

SBHE-

IRQ10

BH0

TDI_U1

J1A

PC/104/HEADER_A32

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

+3.3V

FOR `DSP56303PW80'

GND

D10

A6

D8

BSCAN-

C23

.1UF

+3P3V

A10

A5

A8

A14

D3

U34

74LCX245
(TSSOP20)

2
3
4
5
6
7
8
9

1
19

18
17
16
15
14
13
12
11

20
10

A0
A1
A2
A3
A4
A5
A6
A7

T/R
OE

B0
B1
B2
B3
B4
B5
B6
B7

VCC
GND

U4F

74ACT14

(SO14)

13 12

-12V

GND

MEMW-

BA07_A

SD03

PA19

OR

LA17

+5V

RP7

3.3KSIP10C

12

3456789 10

GND

BSCAN-

TBD_0

PA16

0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19

J2D

PC/104/HEADER/D20

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20

BSCAN-

GND

D16

BA07_A

D23

R2

10K

GND

SERVO

(KEY)

WDO

CS1-

A10

RP5A

1KSIP6I

1 2

GUARD BAND

GUARD BAND

MEMCS16-

PA18

BD07_A

A7

SCK0

D10

E1

21

THIS DOCUMENT IS THE CONFIDENTIAL PROPERTY OF DELTA TAU

SD15

SA14

+3P3V

GND

A9

BA11_A

PHA

ABOVE AGREEMENT.

GND

SD01

SD03

STD0

SA06

SIOW-

CS_00-

RP1

3.3KSIP10C

12

3456789 10

|670-0SH2.sch

KEY

GND

A15

PHA_A

TBD_2

M2

HOLE

GND

A8

D1

WAIT-

A0

SER

SA04

Q1

MMBT3906LT1

(SOT23)

1

23

R3
100K

D8

BRTS-

A9

WAIT-

CARD0

RESET-

+12V

IRQ15

BD02_A

VM_ECS- VMECS-

VM_ECS-

PA20

E0

21

C46

.1UF

NOTE2:

IRQ11

CS00-

C47

.1UF

J1B

PC/104/HEADER_B32

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

+

C16

10UF
16V

(TANT)

OR

A7

D17

U33

IDT74FCT164245TPA

(TSSOP48)

2
3

5
6

8
9

11
12

46

44
43

41
40

38
37
36

1

4

7

10

47

48

13
14
15
16
17
18
19
20
21
22
23
24 25

26

27

28

29

30

31

32

33

34

35

39

42

45

B0
B1

B2
B3

B4
B5

B6
B7

A1

A2
A3

A4
A5

A6
A7
A8

T/R1

GND

VCCB

GND

A0

OE1

B8
B9
GND
B10
B11
VCCB
B12
B13
GND
B14
B15
T/R2

OE2

A15

A14

GND

A13

A12

VCCA

A11

A10

GND

A9

GND

VCCA

GND

FOR `DSP56303PW80'

A5

19.6608Mhz

BHREQ-

D12

TRST-

BD06_A

DATA SYSTEMS INC. AND IS LOANED SUBJECT TO RETURN UPON

GUARD BAND

DRQ6

+3P3V

+5V

BSC12

A6

AEN

IRQ6

+5V

A9

SERVO

BA11_A

BH5

BD04_A

A14

XIN_2

C38

.1UF

ONLY PURSUANT TO WRITTEN LICENSE OR WRITTEN INSTRUCTIONS

D9

BTXD

WR-

C37

.1UF

SOT23

Q2

2N7002

(SOT23)

3

12

(KEY)

PA19

TDO_U6

C21

.01UF

E13

+5V

SD04

D5

+

C15

10UF

16V

(TANT)

J8

HEADER 10

(BOX)

1
2
3
4
5
6
7
8
9
10

E12

SD11

GND

DE-

BRCLK

IOCS16-

A16

D14

CS0-

PA21

D7

SA00

XIN_7

DP_RCS-

C41

.1UF

SOT23

Q3
2N7002
(SOT23)

3

12

SMEMR-

ENDXFR-

IOCS-

SA11

A1

INIT-

CS_1-

M1

HOLE

LA22

DACK2-

+5V

GND

C2

.1UF

INSTALL

SA17

GND

SD07

SER

BTXD

SA01

PWDO-

0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19

J2C

PC/104/HEADER/D20

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20

FOR `DSP56309PW80'

(KEY)

GND

-12V

RXD

BSRD1

U4C

74ACT14

(SO14)

5 6

SER

PA16

SD02

SC02

SER_A

INRD-

RXD

GND

LA20

A3

U4B

74ACT14

(SO14)

3 4

J9

DO NOT INSTALL

E11

+5V

DRQ3

+5V

E_51

CS_00-

FLASHCS-

RP6

3.3KSIP10C

12

3456789 10

U7

LTC1384CS

(SOL18)

3

2

4

12

13

11

10

17

7

5

6

15

14

8

9

16

1 18

+V

C1+

C1-

TXD

RXD

RTS

CTS

VCC

V-

C2+

C2-

TXD

RXD

RTS

CTS

VSS

RXEN TXEN

E13

2 1

JUMP `E0'

SD13

DACK3-

GND

BWDO_A-

TMS_U1
BG-

IRQB-

U35F

74ACT14
(SO14)

13 12

D4

MMBD301LT1

1 3

U3

DS1231S
(SOL16)

1
2
3
4
5
6
7
8

16
15
14
13
12
11
10
9

N.C.
IN
N.C.
MODE
N.C.
TOL
N.C.
GND

N.C.
VCC
N.C.
NMI
N.C.
RST
N.C.
RST

TCK

DRQ0

BA08_A

BA10_A

MODB/IRQB-

A11

POSSESSION OF THIS DOCUMENT INDICATES ACCEPTANCE OF THE

D15

MODC/IRQC-

BHA1

U35E

74ACT14
(SO14)

11 10

C39

.1UF

`VR2,C17,C18'

IRQ3
IRQ4

XIN_0

DPRCS-

C45

.1UF

+5V

D22

BTA

D3

MMBD301LT1

1 3

WD

E0

+5V

CS00-

SERVO

RD-

TA-

TBD_1

E18

2 1

-12V

BD00_A

+5V

D7

BSC11

A8

BRXD

D21

CTS

WDTC

CPUCLK

INRD-

E10

2 1

DO NOT INSTALL `F2'

D6

PMAC2A PC104 Hardware Reference Manual

40 Connector Pinouts

PWM_A_T3

ADC_B3

PA17

D6

BD23_A

HOME1+

CHC1-

RP31

2.2KSIP6C

2

3

4

5

6

1

C100

.1UF

SSM-120-L-DV-LC

DEMAND. TITLE TO THIS DOCUMENT IS NEVER SOLD OR

GND

ADC_A2

FLAG_D3

EQU_3+

D2

BD12_A

DAC4-

U12

IDT74FCT164245TPA

(TSSOP48)

2
3

5
6

8
9

11
12

46

44
43

41
40

38
37
36

1

4

7

10

47

48

13
14
15
16
17
18
19
20
21
22
23
2425

26

27

28

29

30

31

32

33

34

35

39

42

45

B0
B1

B2
B3

B4
B5

B6
B7

A1

A2
A3

A4
A5

A6
A7
A8

T/R1

GND

VCCB

GND

A0

OE1

B8
B9

GND

B10
B11

VCCB

B12
B13

GND

B14
B15

T/R2

OE2

A15

A14

GND

A13

A12

VCCA

A11

A10

GND

A9

GND

VCCA

GND

U27B

DS75452N

(DIP8)

(SOCKET)

6

7

5

+5V

+5V

BD01_A

ADC_A2

FLAG_T2

EQU_1+

BD22_A

BA00_A

RP20C

47KSIP8I

5 6

U27A

DS75452N

(DIP8)

(SOCKET)

1

2

3

+5V

+12V

PWM_A_T1

FALT3­FALT4-

CHB3-

RP20B

47KSIP8I

34

CHC4-

DIR_4+

BD20_A

PWM_C_B4

PLIM2+

C121 100PF

RP18C

100KSIP8I

5 6

RP18D

100KSIP8I

7 8

+3P3V

+5V

+5V

D4

CHA3+

+

-

U18B

LF347M

(SO14)

5

6

7

U22

74ACA6245
(dgg)

2
3

5
6

8
9

11
12

46

44
43

41
40

38
37
36

1

4

7

10

47

48

13
14
15
16
17
18
19
20
21
22
23
2425

26

27

28

29

30

31

32

33

34

35

39

42

45

B0
B1

B2
B3

B4
B5

B6
B7

A1

A2
A3

A4
A5

A6
A7
A8

T/R1

GND

VCC

GND

A0

OE1

B8
B9

GND

B10
B11

VCC

B12
B13

GND

B14
B15

T/R2

OE2

A15

A14

GND

A13

A12

VCC

A11

A10

GND

A9

GND

VCC

GND

RP12B

100KSIP8I

3 4

GND

-12V

+12V

A5

EQU_4+

BD14_A

PWM_A_B2

BD17_A

D19

FALT1-

C106

.1UF

R22

20.0K/1%

PWM_B_B3

BD03_A

PHASE

FLAG_T1

ADC_CS-

FLAG_A4

CHC4+

MLIM1+

+

-

U17C

LF347M

(SO14)

10

9

8

U13

IDT74FCT164245TPA

(TSSOP48)

2
3

5
6

8
9

11
12

46

44
43

41
40

38
37
36

1

4

7

10

47

48

13
14
15
16
17
18
19
20
21
22
23
2425

26

27

28

29

30

31

32

33

34

35

39

42

45

B0
B1

B2
B3

B4
B5

B6
B7

A1

A2
A3

A4
A5

A6
A7
A8

T/R1

GND

VCCB

GND

A0

OE1

B8
B9

GND

B10
B11

VCCB

B12
B13

GND

B14
B15

T/R2

OE2

A15

A14

GND

A13

A12

VCCA

A11

A10

GND

A9

GND

VCCA

GND

POSSESSION OF THIS DOCUMENT INDICATES ACCEPTANCE OF THE

+3P3V

PWM_A_T2

BD13_A

PWM~A~T3

DAC1-

PUL_3+

ADCIN_1

BD08_A

BD16_A

BD22_A

FLAG_U3

MLIM1+

DAC4+

PWM_C_B3

A5

CHA4+

MLIM2+

C71

.1UF

C80

.1UF

BD12_A

BD01_A

BD09_A

PWM_A_B1

BA08_A

USER4+

CHC3-

C60

.1UF

D15

CS4-

MLIM3+

PWM_C_T3

BA03_A

RP24

3.3KSIP10C

12

3456789 10

RP18A

100KSIP8I

1 2

THIS DOCUMENT IS THE CONFIDENTIAL PROPERTY OF DELTA TAU

D5

A4

D0

FAULT~1

PWM_A_T2

CHB4-

D21

PWM_C_B2

BD05_A

BX/Y_A

HOME4+

C118

220PF

-

+

U19A

LM6132AIM

(SO8)

3

2

1

84

+5V

BA12_A

PWM_C_B4

ENC_B4

FLAG_B1

FAULT_2

WDO

C67

.1UF

SSM-125-L-DV-LC

GND

A15

PLIM4+

BD01_A

BD07_A

D9

D11

BD00_A

R36

3.3K

RP22B

47KSIP8I

3 4

GND

WAIT-

BD20_A

ADC_B2

DAC3-

CHC4-

BD19_A

C75

.1UF

BA06_A

BRD_A-

ADC_A1

PWM~A~B4

PWM_C_B3

BA01_A

RP23C

220SIP8I

5 6

GND

ADC_A3

AENA_1

PRDY

PLIM1+

FLAG_B4

CHC2-

U24

ST34C86CF16
(SO16)

3 2

16

7

15

10

8

1

6

14

5

4

9

11

13

12

OUT-A IN-A

VCC

IN-C

IN-B

IN-D

GND

IN-A

IN-C

IN-B

OUT-C

EN-A,C

IN-D

OUT-D

OUT-B

EN-B,D

R17

24K

C61

.1UF

RP15C

47KSIP8I

5 6

RP23D

220SIP8I

7 8

POSSESSION OF THIS DOCUMENT INDICATES ACCEPTANCE OF THE

+5V

CS00-

PWM~A~B4

FAULT~3

BD08_A

DIR_3+

CHC2+

BA00_A

USER3+

RP21A

47KSIP8I

1 2

ONLY PURSUANT TO WRITTEN LICENSE OR WRITTEN INSTRUCTIONS

+3p3V

A8

ADC_STR

BD10_A

CHB1-

D2

CHC1+

BD16_A

MLIM4+

C69

.1UF

(JMACH1)

ENC_A1

PWM_C_B3

BD13_A

ADC_A3

FLAG_D1

D5

C112

47PF

THIS DOCUMENT IS THE CONFIDENTIAL PROPERTY OF DELTA TAU

D8

CHC1-

EQU_4+

CHA1+

BD01_A

PWM_C_T1

EQU_2+

CHA4-

EQU_2

C74

.1UF

E16

21

E15A

21

D9

FLAG_W3

A15

AENA1-

BD02_A

BD12_A

RP32

2.2KSIP10C

12

3456789 10

U20

ADS7861E
(SSOP24)

1
2
3
4
5
6
7
8

9
10
11
12 13

14

15

16

17

18

19

20

21

22

23

24
DGND
CH_B1+
CH_B1­CH_B0+
CH_B0­CH_A1+
CH_A1­CH_A0+
CH_A0­REF_IN
REF_OUT
AGND +VA

M1

M0

A0

CONVST

RD

CS-

CLOCK

BUSY

SDO_B

SDO_A

+VD

+12V

FAULT~3

ENC_C2

CHA2-

RP13B

47KSIP8I

3 4

(JEXPB)

BD00_A

BD04_A

BA10_A

A3

CHA4-

BD18_A

CHB3+

AENA3-

C63

.1UF

RP17A

220SIP8I

1 2

RP17D

220SIP8I

7 8

BA02_A

BD07_A

FLAG_C1

CHB3-

CHA1-

DATA SYSTEMS INC. AND IS LOANED SUBJECT TO RETURN UPON

TRANSFERRED FOR ANY REASON. THIS DOCUMENT IS TO BE USED

D3

PWM_B_B1
PWM_B_T2

BA09_A

HOME1+

USER1+

RP38

2.2KSIP10C

12

3456789 10

DEMAND. TITLE TO THIS DOCUMENT IS NEVER SOLD OR

+5V

BRST_A-

BD23_A

A1

EQU_3

RP18B

100KSIP8I

3 4

`W1'= 1 TO 2 FOR 28F320J3A

+5V

WDO

PWM_A_B1

AENA_3

A3

CHA2+

PWM_C_T1

BA05_A

EQU_4

603670-320

B

PMAC-PC104, MACHINE I/O & "JEXP" SECTION

Delta Tau Data Systems, Inc.

D

22Monday, July 02, 2001

Title

Size Document Number Rev

Date: Sheet

of

+5V

GND

D10

HOME4+

BD15_A

BA12_A

C124

.1UF

C102

.1UF

GND

CS1-

BD15_A

CHC2-

PWM_C_B1

R27

4.99K/1%

BD14_A

BD11_A

PA16

BD21_A

D18

AENA4-

DIR_4+

CHB4+

J4

HEADER 17X2

12
34
56
78
910
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34

C64

.1UF

R32 3.3K

PA17

A4

CHA2+

PWM_A_B4

RP12C

100KSIP8I

5 6

RP15D

47KSIP8I

78

OF DELTA TAU DATA SYSTEMS INC. ALL RIGHTS TO DESIGNS AND

PWM_B_B2

WDO-

RP21B

47KSIP8I

34

R16

200.0K
1%

U21

74ACA6245
(dgg)

2
3

5
6

8
9

11
12

46

44
43

41
40

38
37
36

1

4

7

10

47

48

13
14
15
16
17
18
19
20
21
22
23
24 25

26

27

28

29

30

31

32

33

34

35

39

42

45

B0
B1

B2
B3

B4
B5

B6
B7

A1

A2
A3

A4
A5

A6
A7
A8

T/R1

GND

VCC

GND

A0

OE1

B8
B9
GND
B10
B11
VCC
B12
B13
GND
B14
B15
T/R2

OE2

A15

A14

GND

A13

A12

VCC

A11

A10

GND

A9

GND

VCC

GND

JUMP E16 TO ENABLE ATD

GND

CHA2-

ADC_A4

D5

DIR_2+

DIR_1+

PWM_C_T2

BA04_A

C101

.1UF

D1

A12

SCLK

CHA1-

CHA3-

CHA2+

+

-

U16B

LF347M

(SO14)

5

6

7

R30 3.3K

GND

D11

D18

BA08_A

BD23_A

FLAG_T3

A11

FLAG_C2

HOME3+

CHB1+

A0

GND

GND

D20

FLAG_W1

FLAG_T4

FLAG_V4

FAULT_3

BA02_A

C65

.1UF

R20

20.0K/1%

OF DELTA TAU DATA SYSTEMS INC. ALL RIGHTS TO DESIGNS AND

+5V

BX/Y_A

A10

AENA_1

CHB4-

D3

PWM_C_T2

PUL_2+

B_WDO

CHB2-

RP12D

100KSIP8I

7 8

+

-

U16D

LF347M

(SO14)

12

13

14

R24

20.0K/1%

RP19C

47KSIP8I

5 6

BD02_A

BD05_A

ENC_B2

ENC_B3

DAC4+

BD20_A

C104

.1UF

RP22C

47KSIP8I

5 6

R26

20.0K/1%

GND

BA05_A

WAIT-

ADC_A1

MLIM3+

CHB1-

RP30

2.2KSIP6C

2

3

4

5

6

1

GND

ENC_A3

BD14_A

A13

PWM_A_T3

BA05_A

C111

470PF

+

-

U17D

LF347M

(SO14)

12

13

14

+5V

GND

BA10_A

ADC_B1

A5

EQU_3+

C117

220PF

U25

ST34C86CF16
(SO16)

3 2

16

7

15

10

8

1

6

14

5

4

9

11

13

12

OUT-A IN-A

VCC

IN-C

IN-B

IN-D

GND

IN-A

IN-C

IN-B

OUT-C

EN-A,C

IN-D

OUT-D

OUT-B

EN-B,D

+

-

U17A

LF347M

(SO14)

3

2

1

411

GND

BA11_A

DPRCS-

PRDY

BD06_A

D13

+

-

U17B

LF347M

(SO14)

5

6

7

GND

VMECS-

BWDO_A-

FLAG_U1

D15

D22

PLIM3+

RP20D

47KSIP8I

78

RP39

1KSIP10C

12

3456789 10

R25

4.99K/1%

(JEXP_A)

RESET-

BD11_A

ENC_C3

D14

WDO

RD-

RP19A

47KSIP8I

1 2

C123 100PF

GND

BD02_A

PWM_C_B1

ENC_B1

FAULT~4

PWM_C_T4

ADC_CS-

C105

.1UF

RP16D

47KSIP8I

7 8

J6

HEADER 25X2(FEM)

CLS125LDDV

12
34
56
78
910
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
41 42
43 44
45 46
47 48
49 50

RP13C

47KSIP8I

5 6

BD09_A

R35

3.3K

+

-

U15A

LF347M

(SO14)

3

2

1

411

A9

PWM_A_B3

BD04_A

USER4+

PWM~A~B3

R11

24K

C109

470PF

RP28

10KSIP8I

1 2
3 4
5 6
7 8

PWM_A_T1

BD16_A

D1

USER1+

DIR_1+

WDO

BD17_A

R15

24K

+5V

Flag_3_4_V

CHA3+

D20

PWM_C_B4

+

-

U15C

LF347M

(SO14)

10

9

8

C116

220PF

U32

74AC541
(SOL20)

2
3
4
5
6
7
8
9

1
19

18
17
16
15
14
13
12
11

20
10

A1
A2
A3
A4
A5
A6
A7
A8

G1
G2

Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8

VCC
GND

+5V

Flag_3_4_V

BA01_A

D6

BWDO_A-

PWM~A~B1

FAULT~4

CHB2-

BD02_A

CHC4+

BA02_A

BA07_A

W1

SOLDER
JUMPER

2

3

1

`W1'= 2 TO 3 FOR 28F320J5A

DAC1-

BA01_A

FLAG_V2

FAULT_1

+

-

U18D

LF347M

(SO14)

12

13

14

C70

.1UF

U14A

DS75451M

(SO8)

(SOCKET)

1

2

3

C72

.1UF

ADCIN_2

FLAG_D2

MLIM4+

FALT2-

A2

BD04_A

BD14_A

D21

FAULT_4

D12

D23

R13

24K

GND

PWM_B_T3

BD12_A

DPRCS-

CHC2+

PWM_A_B3

BWR_A-

BA09_A

BA07_A

PWM_C_B2

A6

PWM~A~T2

RP13D

47KSIP8I

7 8

RP45

3.3KSIP10C

1 2

3
4
5
6
7
8
910

RP10

3.3KSIP10C

1 2

3
4
5
6
7
8
910

-12V

FLASHCS-

BRST_A-

FLAG_U2

PA18

PUL_1+

A3

C120 100PF

DAC2+

ENC_C4

AENA_4

AENA4-

BD03_A

FAULT~2

RP21C

47KSIP8I

5 6

BD03_A

BD07_A

CHA1-

PWM_C_T4

CHB1+

ADC_A4

PWM~A~B3

D1

PHASE

D17

C79

.1UF

RP16A

47KSIP8I

1 2

(JMACH2)

Flag_1_2_V

CS00-

PUL_1+

EQU_1+

CHC3-

RP33

1KSIP10C

12

3456789 10

C115

470PF

RP23A

220SIP8I

1 2

GND

SERVO

D6
D7

DAC3-

C62

.1UF

-12V

+5V

BA00_A

BA03_A

BA09_A

A8

PLIM2+

A0

SERVO

BD22_A

BA11_A

RP19D

47KSIP8I

7 8

D0

ADC_STR

C78

.1UF

RP17B

220SIP8I

3 4

D2

CHA2-

DAC2-

BD21_A

DAC3+

CHC3+

BD11_A

BA03_A

R12

200.0K
1%

RP46

3.3KSIP10C

1 2

3
4
5
6
7
8
910

RP22A

47KSIP8I

1 2

+5V

D7

PWM~A~T2

VMECS-

RD-

CHC2+

PWM~A~T4

C77

.1UF

RP14C

47KSIP8I

5 6

SSM-125-L-DV-LC

GND

D19

WR-

ADC_B4

AENA_2

AENA3-

PA16

+

-

U18C

LF347M

(SO14)

10

9

8

INVENTIONS ARE RESERVED BY DELTA TAU DATA SYSTEMS INC.

+12V

A11

CHA1+

DIR_3+

BD10_A

EQU_1

ADC_A1

CHB3-

D3

RP17C

220SIP8I

5 6

+3P3V

D14

A2

CHA3-

AENA1-

CHC1+

FLAG_B3

BA13_A

+

-

U15D

LF347M

(SO14)

12

13

14

+3P3V

GND

BA13_A

RESET-

PWM~A~B1

CHB3+

BD15_A

BD00_A

PWM~A~T3

PWM_C_B2

BA10_A

RP43

4.7KSIP10C

12

3456789 10

J5

HEADER 25X2(FEM)

CLS125LDDV

12
34
56
78
910
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
41 42
43 44
45 46
47 48
49 50

D13

BD19_A

BA11_A

BD09_A

CHC1-

CHC3+

E15B

21

RP25

10KSIP8I

1 2
3 4
5 6
7 8

C73

.1UF

SIP SOCKET

GND

PA20

PWM_B_T1

PWM_B_T4

BWR_A-

CHC3-

ADC_CLK

A1

USER3+

USER2+

TRANSFERRED FOR ANY REASON. THIS DOCUMENT IS TO BE USED

BD06_A

BD10_A

BD06_A

CHA1+

RP13A

47KSIP8I

1 2

RP14A

47KSIP8I

1 2

SIP SOCKET

ABOVE AGREEMENT.

+5V

-12V

PWM_A_T4

AENA_4

SCLK_DIR

FLAG_V1

PWM_C_T1

U10

E28F320J3A

(TSOP56)

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28 29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56
A22
CE1­A21
A20
A19
A18
A17
A16
VCC
A15
A14
A13
A12
CE0
VPEN
RP­A11
A10
A09
A08
GND
A07
A06
A05
A04
A03
A02
A01 CE2

A23

BYTE-

A00

DQ0

DQ8

DQ1

DQ9

VCC

DQ2

DQ10

DQ3

DQ11

GND

VCCQ

DQ4

DQ12

DQ5

DQ13

GND

DQ6

DQ14

DQ7

DQ15

STS

OE-

WE-

A24_WP

RP22D

47KSIP8I

7 8

+5V

RD-

ENC_A4

DAC3+

WR-

DAC2+

ADCIN_2

PLIM4+

R23

4.99K/1%

C114

47PF

RP14B

47KSIP8I

34

A13

WDO-

FLAG_A1

BD04_A

CHB2+

PUL_4+

WDO

WR-

PLIM1+

+

-

U18A

LF347M

(SO14)

3

2

1

411

RP15A

47KSIP8I

1 2

RP15B

47KSIP8I

34

PA20

MLIM2+

PWM~A~B2

U23

ST34C86CF16
(SO16)

3 2

16

7

15

10

8

1

6

14

5

4

9

11

13

12

OUT-A IN-A

VCC

IN-C

IN-B

IN-D

GND

IN-A

IN-C

IN-B

OUT-C

EN-A,C

IN-D

OUT-D

OUT-B

EN-B,D

GUARD BANDING REQ'D

GND

D23

BD08_A BD09_A

DAC1+

PWM~A~B2

BD05_A

CHB4+

C107

.1UF

RP44

3.3KSIP10C

12

3456789 10

C66

.1UF

guard band

Flag_1_2_V

+5V

+12V

PWM~A~T1

PWM_B_B4

ADCIN_1

FLAG_C3

BD00_A

D16

BD07_A

R31 3.3K

R10

200.0K
1%

BD05_A

DAC4-

PWM_C_T3

DATA SYSTEMS INC. AND IS LOANED SUBJECT TO RETURN UPON

BA03_A

A2 FLAG_A3

D8

CHA4+

CHB3+

BA04_A

C122 100PF

CHA4+

AENA_2

BA05_A

PWM_C_T4

RP42

10KSIP8I

1 2
3 4
5 6
7 8

R14

200.0K
1%

ADC_B1

CHB2-

BD18_A

DIR_2+

FALT4-

CHA4-

U26A

DS75452N

(DIP8)

(SOCKET)

1

2

3

GND

BA08_A

A7

ADC_CLK

CHC3+

PA19

IOCS-

C68

.1UF

GND

ADC_B3

WAIT-

AENA_3

PUL_4+

FLAG_D4

CHA3-

RP20A

47KSIP8I

1 2

+

-

U16A

LF347M

(SO14)

3

2

1

411

"E15" FLASH BANK SELECT

ONLY PURSUANT TO WRITTEN LICENSE OR WRITTEN INSTRUCTIONS

PWM_A_B2

BA04_A

BD11_A

AENA2-

BD03_A

BD10_A

BD13_A

-

+

U19B

LM6132AIM

(SO8)

5

6

7

+5V

IOCS-

D16

ADC_A2

FLAG_W4

A14

A9

FLAG_A2

CHC4-

+5V

BA07_A

BD18_A

FALT2-

U14B

DS75451M

(SO8)

(SOCKET)

6

7

5

GND

PWM_C_T2

FAULT~2

PWM_C_B1

A4

+

-

U16C

LF347M

(SO14)

10

9

8

C119

220PF

E15C

21

J3

HEADER 25X2

12
34
56
78
910
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
41 42
43 44
45 46
47 48
49 50

+5V

D10

CHC1+

CHB4-

C113

470PF

RP14D

47KSIP8I

78

C103

.1UF

C85

.1UF

ABOVE AGREEMENT.

FLT_FLG_V

D22

A0

ADC_B2

BX/Y_A

CHC2-

PLIM3+

PWM_A_B4

RP16C

47KSIP8I

5 6

C108

47PF

BD13_A

BX/Y_A

A6

PWM_C_T3

BA02_A

DAC2-

A10

D0

BA06_A

HOME3+

+5V

PA19

CS4-

CS1-

FLAG_C4

BD06_A

R21

4.99K/1%

+

-

U15B

LF347M

(SO14)

5

6

7

RP23B

220SIP8I

3 4

W1

670-0SH2.sch

BA04_A

PA21

A12

FAULT~1

CHB4+

FLASHCS-

FLAG_B2

USER2+

DAC1+

RP37

2.2KSIP6C

2

3

4

5

6

1

RP29

10KSIP8I

1 2
3 4
5 6
7 8

BD08_A

D12

CHC4+

PA21

FLAG_V3

D4

FLAG_W2

PWM~A~T1

RP19B

47KSIP8I

3 4

(JEXPA)

FLT_FLG_V

D17

PWM~A~T4

CHB1-

FALT3-

BRD_A-

RP12A

100KSIP8I

1 2

R37

3.3K

INVENTIONS ARE RESERVED BY DELTA TAU DATA SYSTEMS INC.

+12V

ENC_A2

ADC_B4

FLAG_U4

D4

PWM_A_T4

J11

HEADER 20X2(FEM)
CLS120LDDV

12
34
56
78
910
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40

A1

CHB2+

AENA2-

CHA3+

C76

.1UF

RP36

2.2KSIP6C

2

3

4

5

6

1

RP16B

47KSIP8I

3 4

PA18

19.6608Mhz

EQU_2+

CHB1+

C110

47PF

RP21D

47KSIP8I

78

RP27

3.3KSIP10C

12

3456789 10

+3P3V

+5V

PUL_2+

-12V

BA06_A

BD17_A

BA00_A

ENC_C1

PUL_3+

FALT1-

CHB2+

HOME2+

-12V

A14

BD15_A

A7

HOME2+

BD19_A

BD21_A

+

C127

10UF/10V

U26B

DS75452N

(DIP8)

(SOCKET)

6

7

5

C125

.1UF

D7

BA01_A

C126

.1UF

RP26

10KSIP8I

1 2
3 4
5 6
7 8