Dell VOSTRO 3500 Schematics

5

D D

4

3

2

1

Winery CALPELLA N11M-GE Schematics

Mobile Arrandale Intel Ibex Peak-M

C C

2009-09-09

REV : SA

B B

A A

5

DY : Nopop Component

UMA : Pop when schematic is UMA DIS : Pop when schematic is DIS

4

3

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Custom

Date: Sheet of

2

Date: Sheet of

Vostro Calpella

Taipei Hsien 221, Taiwan, R.O.C.

Cover Page

1 88Wednesday, September 09, 2009

1

SA

5

Winery CALPELLA Block Diagram

PCB LAYER

L1: Top L2: VCC

D D

L3: Signal L4: Signal L5: GND L6: Bottom

Clock Generator

SLG8SP585

4

7

3

Project code : 91.4ET01.001 Part Number : 48.4ET05.0SA PCB P/N : 09289 Revision : SA

2

1

CPU DC/DC

ISL62883

INPUTS

+PWR_SRC

OUTPUTS

+VCC_CORE

SYSTEM DC/DC

TPS51125

INPUTS

+PWR_SRC

OUTPUTS

+15V_ALW +3.3V_RTC_LDO +5V_ALW +3.3V_ALW

47,48

46

100MHz/

RGB CRT

75

74

2.5Gbps

PCIe x 16

Bandwidth :8GB

RGB CRT

LVDS

2.5 GT/s 2.7 GT/s

RGB CRT

VRAM(gDDR3)

64Mbx16x4 (512MB)

4

84,85

HDMI

C C

CRT

LCD

VRAM

57

HDMI

RGB CRT

55

LVDS

54

Nvidia N11M-GE(40nm)

80,81,82,83

HDMI

LVDS

Switchable Switchable

Intel CPU

Arrandale

8,9,10,11,12,13,14

DMIx4 FDI(UMA)

DDRIII 1066 Channel A

800/1066MHz

DDR III 1066 Channel B

800/1066MHz

PCIE x 1

PCIE

DDRIII 1066

PCIE x 1 & USB 2.0 x 1

10/100/1000LOM

RTL8111DL

(On daughter board)

100MHz

CardReader

LVDS

B B

(8 in 1)SD/MMC MS/MS Pro/xD

(On daughter board)

Realtek RTS5138

USB 2.0

480Mbps

Intel

PCH

14 USB 2.0/1.1 ports

ETHERNET (10/100/1000Mb)

High Definition Audio

SATA ports (6) PCIE ports (8)

LPC I/F ACPI 1.1

PCI/PCI BRIDGE

Digital Mic Array

Azalia CODEC

AZALIA

24MHz

20,21,22,23,24,25,26,27,28

MIC IN

OP AMP

HP OUT

(On daughter board)

A A

2CH SPEAKER

60

5

IDT 92HD81

3Gbps

Flash ROM

4MB

SPI

62

ODD HDD

SATA

59

30

USB,ESATA Multi-Port x1

4

SATA,USB

63

2.5Gbps

USB 2.0

480Mbps

SPI

Flash ROM

256kB

3

SM Bus

Free fall sensor

400KHz

LPC Bus

33MHz

TPM

(On daughter board)

KBC

NUVOTON

NPCE781BA0DX

Touch PAD

62 68 39,58

68

37

Int. KB

76

SM Bus

Slot 0

18

Slot 1

19

35

USB 2.0 x 1

40

Thermal & Fan

EMC2102

Capacity Board

(On daughter board)

2

PCIE x 1

USB 2.0 x 1

USB 2.0 x 2

USB 2.0 x 1

SYSTEM DC/DC

Power SW

TPS2231R

New Card

(On daughter board)

RJ45 CONN

61

TPS51116

OUTPUTSINPUTS

+PWR_SRC

+1.5V_SUS +0.75V_DDR_VTT +V_DDR_MCH_REF

SYSTEM DC/DC

ADP3211

OUTPUTSINPUTS

+PWR_SRC +CPU_GFXCORE

SYSTEM DC/DC

INPUTS

+PWR_SRC

TPS51218

OUTPUTS

+VCC_GFX_CORE

Mini-Card

802.11a/b/g/n

Mini-Card

WWAN/ WiMAX

65

64

CHARGER

Touch Panel (only for 15")

Left Side: USB x 2

Right Side: USB x 1

CAMERA

Bluetooth

Biometric

76

63

73

78

BQ24745

INPUTS

+DC_IN +PBATT

OUTPUTS

+PWR_SRC

SYSTEM DC/DC

TPS51218

OUTPUTSINPUTS

+PWR_SRC

VTT_CORE

LDO

APL5930

INPUTS

OUTPUTS

+1.8V_RUN+3.3V_ALW

LDO

RT9025

2 88Wednesday, September 09, 2009

OUTPUTS

+1.8V_RUN_GPU+3.3V_ALW

INPUTS

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Custom

Date: Sheet of

Vostro Calpella

Taipei Hsien 221, Taiwan, R.O.C.

Block Diagram

1

50

53

86

49

51

87

SA

5

D D

Adapter

AO4407A

45

+PWR_SRC

Charger

BQ24745

Battery

+PBATT

45

TPS51125

C C

+5V_ALW

+5V_ALW2

+3.3V_RTC_LDO

+15V_ALW

4

ISL62883

+VCC_CORE

46

+5V_ALW

3

47、48 86

ADP3211

53

+CPU_GFXCORE

TPS51218

+VCC_GFX_CORE

For NVIDIA GPUFor Intel GPU

+3.3V_ALW

2

TPS51218DSCR

+1.05V_VTT

Arrandale : 1.05V

FDS8880

+1.05V_GFX_PCIE

87

1

TPS51116PWPRG4

49

FDS8880

50

+0.75V_DDR_VTT+V_DDR_MCH_REF

87

+1.5V_SUS

+1.5V_RUN_GPU

P2703

52

AO4468

42

+1.5V_CPU

+1.5V_RUN

TPS2062AD

Daughter BD 6342

+5V_USB0

B B

For USB Port1 For USB Port2,3 For ESATA

AO4468

+5V_RUN

TPS2062AD

+5V_USB1

TPS2062AD

+5V_USB2

63

AO3403

+3.3V_LAN

RTL8111DL

DVDD12

35

TPS2231R

Daughter BD

G5285T11U

+LCDVDD

AO4468

+3.3V_RUN+3.3V_CARDAUX

54

42

TPS2231R

Daughter BD

+3.3V_CARD

APL5930

+1.8V_RUN

51

RT9025

+1.8V_RUN_GPU

87

FDS8880

+3.3V_RUN_GPU

TPS2231R

87

Daughter BD

+1.5V_CARD

Power Shape

Regulator LDO Switch

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Power Block Diagram

Size Document Number Rev

Custom

Date: Sheet of

Power Block Diagram

Vostro Calpella

Taipei Hsien 221, Taiwan, R.O.C.

3 88Wednesday, September 09, 2009

1

SA

5

PCH SMBus Block Diagram

+3.3V_ALW

‧

SRN2K2J-1-GP

PCH

D D

SMBCLK

SMBDATA

SMB_CLK SMB_DATA

22

‧

2N7002SPT

+3.3V_RUN

‧

+3.3V_RUN

‧

SRN2K2J-1-GP

PCH_SMBCLK PCH_SMBDATA

Express Card

SMB_CLK

SMB_DATA

C C

PCH_SMBCLK

‧

PCH_SMBDATA

‧

76

PCH_SMBCLK

‧

PCH_SMBDATA

‧

PCH_SMBCLK

‧

PCH_SMBDATA

‧

KBC SMBus Block Diagram

+5V_RUN

‧

SRN10KJ-5-GP

TPDATA

PSDAT1

TPCLK

B B

PSCLK1

+3.3V_RTC_LDO

‧

SRN4K7J-8-GP

BAT_SCL

SCL1

SDA1

BAT_SDA

‧

SRN100J-3-GP

KBC

KBC_SCL1 KBC_SDA1

+3.3V_RTC_LDO

‧

SRN4K7J-8-GP

‧

5

2N7002DW-1-GP

NPCE781

A A

GPIO73/SCL2

GPIO74/SDA2

TouchPad Conn.

TPDATA

TPCLK

SMBus address:12

PBAT_SMBCLK1 PBAT_SMBDAT1

+3.3V_RUN

Battery Conn.

CLK_SMB DAT_SMB

SMBus address:16

‧

SRN4K7J-8-GP

+3.3V_RUN

‧

THERM_SCL

‧

THERM_SDA

‧

THERM_SCL THERM_SDA

4

DIMM 1

SCL SDA

SMBus Address:A0

DIMM 2

SCL

SDA

SMBus Address:A2

Clock Generator

SMBCLK SMBDATA

SMBus address:D2

Minicard WLAN

SMB_CLK

SMB_DATA

Minicard WWAN

SMB_CLK SMB_DATA

Free fall sensor

SCL/SPC SDA/SDI/SDO

BQ24745

SCL SDA

Thermal

SMCLK

SMDATA

SMBus address:7A

Capacity Board

SCL

(On daughter board)

SDA

SMBus address:0A

4

3

2

1

Switchable Graphic SMBus Block Diagram

+3.3V_RUN

PCH

SRN2K2J-1-GP

_DDC_CLK

18

19

07

64

L_DDC_CLK

L_DDC_DATA

CRT_DDC_CLK

L

LDDC_CLK

L_DDC_DATA

LDDC_DATA

CRT_DDC_DATA

65

40

SRN2K2J-1-GP

GMCH_DDCCLK CRT_CLK_DDC

SDVO_CTRLCLK

SDVO_CTRLDATA

N11M-GE

I2CC_SCL I2CC_SDA

68

45

44

39

I2CA_SCL

I2CA_SDA

IFPC_AUX_I2CW_SCL

IFPC_AUX_I2CW_SDA#

SRN2K2J-1-GP

HDMI_SDATA_DDC

3

‧

+3.3V_RUN

GMCH_DDCDATA CRT_DAT_DDC

+3.3V_RUN

SDVO_CLK HDMI_SCLK_DDC

SDVO_DAT

‧

+3.3V_RUN

‧

+3.3V_RUN

‧

SRN2K2J-1-GP

B1 B0 GND NC7SB3157P6X-1GP

B1 B0

GND

NC7SB3157P6X-1GP

‧

B1 B0

GND

NC7SB3157P6X-1GP

B1 B0

‧

GND

NC7SB3157P6X-1GP

+3.3V_RUN

‧

SRN2K2J-1-GP

B1 B0

‧

GND NC7SB3157P6X-1GP

B1 B0

‧‧

GND

NC7SB3157P6X-1GP

VCC

A S

VCC

A S

VCC

A S

VCC

A S

VCC

A S

VCC

A

S

+3.3V_RUN

SRN2K2J-1-GP

+3.3V_RUN

DDC_CLK_CON2

+3.3V_RUN

DDC_DATA_CON2

SRN2K2J-1-GP

+3.3V_RUN

HDMI_SCLK_CON_L

+3.3V_RUN

HDMI_SDATA_CON_L

LDDC_CLK_CON

LDDC_DATA_CON

+3.3V_RUN

DY

‧

+3.3V_RUN

‧

DY

‧

2

+3.3V_RUN

‧

SRN2K2J-1-GP

LCD Conn.

2N7002DW-1-GP

54

+3.3V_RUN_GPU

‧

DDC_CLK_CON

DDC_DATA_CON

+3.3V_RUN

‧

HDMI_SCLK_CON

HDMI_SDATA_CON

+5V_CRT_RUN

‧

SRN2K2J-1-GP

‧

+5V_RUN

‧

Title

Size Document Number Rev

C

Date: Sheet of

CRT CONN

SRN2K2J-1-GP

HDMI

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

SMBUS Block Diagram

Vostro Calpella

4 88Wednesday, September 09, 2009

1

55

SA

A

B

C

D

E

Thermal Block Diagram

1 1

DP1

EMC2102_DN1

2 2

DN1

EMC2102_DP1

Thermal

SC470P50V3JN-2GP

WWAN

EMC2102

DP2

VGA_THERMDA

SC470P50V3JN-2GP

DN2

VGA_THERMDC

3 3

DPLUS

DMINUS

MMBT3904-3-GP

GPU

54

Audio Block Diagram

SPKR_PORT_D_L+ SPKR_PORT_D_LSPKR_PORT_D_RSPKR_PORT_D_R+

HP1_PORT_B_L HP1_PORT_B_R

Codec 92HD81

HP0_PORT_A_L HP0_PORT_A_R VREFOUT_A_OR_F

AUD_SPK_L1 AUD_SPK_L2 AUD_SPK_R2 AUD_SPK_R1

AUD_HP1_JACK_L AUD_HP1_JACK_R

AUD_EXT_MIC_L AUD_EXT_MIC_R AUD_VREFOUT_B

0R3-0-U-GP

0R3-0-U-V-GP

AUD_SPK_L1_R AUD_SPK_L2_R AUD_SPK_R2_R AUD_SPK_R1_R

SPEAKER

44

HP

OUT

50

MIC

IN

50

CPU_THERMDA

DP3

DN3

CPU_THERMDC

SC470P50V3JN-2GP

MMBT3904-3-GP

DMIC_CLK/GPIO1

DMIC0/GPIO2

AUD_DMIC_CLK

AUD_DMIC_IN0

HW T8 sensor

28

4 4

A

B

( CPU )

22

C

33R2J-2-GP

33R2J-2-GP AUD_DMIC_IN0_R

Title

Size Document Number Rev

Date: Sheet of

D

Date: Sheet of

AUD_DMIC_CLK_G_R

Thermal/Audio Block Diagram

Custom

Vostro Calpella

Digital MIC Array

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

E

47

5 88Wednesday, September 09, 2009

SA

A

B

C

D

E

Processor Strapping

PCH Strapping

Name Schematics Notes

Calpella Schematic Checklist Rev.0_7

SPKR

4 4

INIT3_3V# Weak internal pull-down. Do not pull high. GNT3#/

GPIO55

INTVRMEN

GNT0#, GNT1#/GPIO51

GNT2#/ GPIO53

GPIO33

3 3

SPI_MOSI

NV_ALE

NC_CLE Weak internal pull-up. Do not pull low. HAD_DOCK_EN#

/GPIO[33] HDA_SDO Weak internal pull-down. Do not pull high.

HDA_SYNC GPIO15 GPIO8 GPIO27

Reboot option at power-up

Internal weak Pull-down.

Default Mode:

Connect to Vcc3_3 with 8.2-kΩ

No Reboot Mode with TCO Disabled:

- 10-kΩ weak pull-up resistor.

Internal pull-up.

Default Mode:

Note: Connect to ground with 4.7-k?

Low (0) = Top Block Swap Mode

weak pull-down resistor. CRB uses a 1 k do not stuff resistor.

High (1) = Integrated VRM is enabled Low (0) = Integrated VRM is disabled

Left both GNT0# and GNT1# floating. No pull up

Default (SPI):

required. Connect GNT1# to ground with 1-kΩ pull-down

Boot from PCI:

resistor. Leave GNT0# Floating. Connect both GNT0# and GNT1# to ground with 1-kΩ

Boot from LPC:

pull-down resistor.

Default - Internal pull-up.

= Configures DMI for ESI compatible operation (for servers

Low (0)

only. Not for mobile/desktops). Do not pull low.

Default:

Connect to ground with 1-kΩ

Disable ME in Manufacturing Mode:

pull-down resistor. Connect to Vcc3_3 with 8.2-kΩ weak pull-up resistor.

Enable iTPM:

Left floating, no pull-down required.

Disable iTPM:

Connect to Vcc3_3 with 8.2-kΩ weak pull-up

Enable Danbury:

resistor. Connect to ground with 4.7-kΩ weak pull-down

Disable Danbury:

resistor.

Flash Descriptor Security will be overridden.

Low (0):

Flash Descriptor Security will be in effect.

High (1) :

Weak internal pull-down. Do not pull high. Weak internal pull-down. Do not pull high. Weak internal pull-up. Do not pull low.

Default = Do not connect (floating)

High(1) = Enables the internal VccVRM to have a clean supply for analog rails. No need to use on-board filter circuit. Low (0) = Disables the VccVRM. Need to use on-board filter circuits for analog rails.

2 2

Pin Name Strap Description Configuration (Default value for each bit is

CFG[4] Disabled - No Physical Display Port attached to

CFG[3]

CFG[0]

CFG[7]

DisplayPort Presence

PCI-Express Static Lane Reversal

PCI-Express Configuration Select

Reserved Temporarily used for early Clarksfield samples.

1 unless specified otherwise)

1:Embedded

Embedded DisplayPort. Enabled - An external Display Port device is

0:

connected to the Embedded Display Port. Normal Operation.

1:

Lane Numbers Reversed 15 -> 0, 14 -> 1, ...

0:

Single PCI-Express Graphics

1:

Bifurcation enabled

0:

-

Clarksfield (only for early samples pre-ES1)

Connect to GND with 3.01K Ohm/5% resistor Only temporary for early CFD samples

Note:

(rPGA/BGA) [For details please refer to the WW33 MoW and sighting report]. For a common motherboard design (for AUB and CFD), the pull-down resistor should be used. Does not impact AUB functionality.

Calpella Schematic Checklist Rev.0_7

Default Value

1

0

PCIE Routing

LANE1 LANE2 LANE3 LAN

1 1

Card reader MiniCard WLAN

MiniCard WWANLANE4 New CardLANE5

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Custom

Date: Sheet of

Vostro Calpella

Taipei Hsien 221, Taiwan, R.O.C.

Table of Content

6 88Wednesday, September 09, 2009

SA

5

D D

4

3

2

1

+3.3V_RUN +3.3V_RUN_SL585

DY

C701

C701 SC1U10V2KX-1GP

SC1U10V2KX-1GP

C C

B B

68.00119.131 0603

68.00084.521 0805

R708 0R3J-0-U-GPR708 0R3J-0-U-GP

1 2

12

DREFCLK#[23]

DREFCLK[23]

CLKIN_DMI#[23]

CLKIN_DMI[23]

CLK_PCIE_SATA#[23]

CLK_PCIE_SATA[23]

CLK_CPU_BCLK#[23]

CLK_CPU_BCLK[23]

12

DY

C702

C702 SC10U10V5ZY-1GP

SC10U10V5ZY-1GP

12

C703

C703 SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

TP701TPAD14-GP TP701TPAD14-GP TP702TPAD14-GP TP702TPAD14-GP

12

C704

C704 SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

DREFCLK# DREFCLK

CLKIN_DMI# CLKIN_DMI

CLK_PCIE_SATA# CLK_PCIE_SATA

CLK_CPU_BCLK# CLK_CPU_BCLK

TP_CPU_1#

1

TP_CPU_1

1

12

C705

C705 SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

1st Silego 71.08585.003 2nd ICS 71.93197.003

12

C707

C707 SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

U701

4

DOT_96#

3

DOT_96

14

SRC_2#

13

SRC_2

11

SRC_1/SATA#

10

SRC_1/SATA

22

CPU_0#

23

CPU_0

19

CPU_1#

20

CPU_1

SLG8SP585VTR-GP

+1.05V_VTT

12

C708

C708 SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

+3.3V_RUN_SL585 +1.05V_RUN_SL585_IO

29

5

1

17

24

VDD_27

VDD_REF

VDD_DOT

VDD_SRC

VDD_CPU

VSS_DOT

VSS_SRC

VSS_CPU

VSS_REF

GND

26

33

2

12

21

68.00119.131

R709 0R3J-0-U-GPR709 0R3J-0-U-GP

1 2

12

C709

C709 SC1U10V2KX-1GP

SC1U10V2KX-1GP

DY

15

18

VDD_SRC_IO

VDD_CPU_IO

27MHZ

27MHZ_SS

CPU_STOP#

CKPWRGD/PD#

REF_0/CPU_SEL

XTAL_IN

XTAL_OUT

VSS_278VSS_SATA

9

+1.05V_VTT

SDA SCL

6 7

16 25 30

28 27

31 32

12

C710

C710 SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

CLK_27M CLK_27M_SS

CPU_STOP# CK_PWRGD FSC

CLK_XTAL_IN CLK_XTAL_OUT

PCH_SMBDATA [18,19,23,40,64,65] PCH_SMBCLK [18,19,23,40,64,65]

X701

1 2

X-14D31818M-50GP

C714

C714 SC12P50V2JN-3GP

SC12P50V2JN-3GP

+1.05V_RUN_SL585_IO

12

C711

C711 SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

VGA 27M SS

DY Mount

NON-SS Mount DY

R706 33R2J-2-GP

R706 33R2J-2-GP R710 33R2J-2-GP

R710 33R2J-2-GP

R701 2K2R2J-2-GPR701 2K2R2J-2-GP R703 33R2J-2-GPR703 33R2J-2-GP

12

DY

12

DY

12 12

CLK_XTAL_IN

CLK_XTAL_OUT

12

C715

C715 SC12P50V2JN-3GP

SC12P50V2JN-3GP

12

C712

C712 SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

R710R706

+3.3V_RUN

12

EC701

DY

SC4D7P50V2CN-1GP

CLK_VGA_27M [81]

CLK_PCH_14M [23]

R705

R705 10KR2J-3-GP

10KR2J-3-GP

CK_PWRGD

+3.3V_RUN_SL585

1 2

G

Q701

Q701 2N7002A-7-GP

2N7002A-7-GP

VR_CLKEN# [47]

SD

R704

R704 4K7R2J-2-GP

4K7R2J-2-GP

R707

R707 10KR2J-3-GP

10KR2J-3-GP

A A

5

4

DY

1 2

FSC

1 2

3

FSC 0 1

SPEED

133MHz

(Default)

100MHz

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Clock Generator SLG8SP585

ize Document Number Rev

Size Document Number Rev

S

Date: Sheet of

2

Date: Sheet of

Vostro Calpella

7 88Wednesday, September 09, 2009

1

X00

5

A

4

3

2

1

D D

1 OF 9

CPU1A

DMI_PTX_CRXN0[22] DMI_PTX_CRXN1[22] DMI_PTX_CRXN2[22] DMI_PTX_CRXN3[22]

DMI_PTX_CRXP0[22] DMI_PTX_CRXP1[22] DMI_PTX_CRXP2[22] DMI_PTX_CRXP3[22]

DMI_CTX_PRXN0[22] DMI_CTX_PRXN1[22] DMI_CTX_PRXN2[22] DMI_CTX_PRXN3[22]

DMI_CTX_PRXP0[22] DMI_CTX_PRXP1[22] DMI_CTX_PRXP2[22] DMI_CTX_PRXP3[22]

C C

FDI_TXN0[22] FDI_TXN1[22] FDI_TXN2[22] FDI_TXN3[22] FDI_TXN4[22] FDI_TXN5[22] FDI_TXN6[22] FDI_TXN7[22]

FDI_TXP0[22] FDI_TXP1[22] FDI_TXP2[22] FDI_TXP3[22] FDI_TXP4[22] FDI_TXP5[22] FDI_TXP6[22] FDI_TXP7[22]

FDI_FSYNC0[22] FDI_FSYNC1[22]

FDI_INT[22] FDI_LSYNC0[22]

FDI_LSYNC1[22]

FDI_TXN0 FDI_TXN1 FDI_TXN2 FDI_TXN3 FDI_TXN4 FDI_TXN5 FDI_TXN6 FDI_TXN7

FDI_TXP0 FDI_TXP1 FDI_TXP2 FDI_TXP3 FDI_TXP4 FDI_TXP5 FDI_TXP6 FDI_TXP7

A24 C23 B22 A21

B24 D23 B23 A22

D24 G24 F23 H23

D25 F24 E23 G23

E22 D21 D19 D18 G21 E19 F21 G18

D22 C21 D20 C18 G22 E20 F20 G19

F17 E17

C17 F18

D17

DMI_RX#0 DMI_RX#1 DMI_RX#2 DMI_RX#3

DMI_RX0 DMI_RX1 DMI_RX2 DMI_RX3

DMI_TX#0 DMI_TX#1 DMI_TX#2 DMI_TX#3

DMI_TX0 DMI_TX1 DMI_TX2 DMI_TX3

FDI_TX#0 FDI_TX#1 FDI_TX#2 FDI_TX#3 FDI_TX#4 FDI_TX#5 FDI_TX#6 FDI_TX#7

FDI_TX0 FDI_TX1 FDI_TX2 FDI_TX3 FDI_TX4 FDI_TX5 FDI_TX6 FDI_TX7

FDI_FSYNC0 FDI_FSYNC1

FDI_INT FDI_LSYNC0

FDI_LSYNC1

CLARKSFIELD

B B

PCI EXPRESS -- GRAPHICS

Calpella Platform Design Guide Revision 1.6

2.4 Arrandale Graphics Disable Guideline

Page 89

CLARKUNF

It applies to Arrandale and Clarksfield discrete graphic designs.

FDI_TX[7:0] and FDI_TX#[7:0] can be left floating on the Arrandale. The GFX_IMON, FDI_FSYNC[0], FDI_FSYNC[1], FDI_LSYNC[0], FDI_LSYNC[1], and FDI_INT signals on the Arrandale side should be tied to GND (through 1-kΩ ±5% resistors).

DW

07/02 Added

1.Added Flexible Display Interface (IntelR FDI) commentariat

1 OF 9

PEG_RX#0 PEG_RX#1 PEG_RX#2 PEG_RX#3 PEG_RX#4 PEG_RX#5 PEG_RX#6 PEG_RX#7 PEG_RX#8 PEG_RX#9

PEG_RX0 PEG_RX1 PEG_RX2 PEG_RX3 PEG_RX4 PEG_RX5 PEG_RX6 PEG_RX7 PEG_RX8

PEG_RX9 PEG_RX10 PEG_RX11 PEG_RX12 PEG_RX13 PEG_RX14 PEG_RX15

PEG_TX#0 PEG_TX#1 PEG_TX#2 PEG_TX#3 PEG_TX#4 PEG_TX#5 PEG_TX#6 PEG_TX#7 PEG_TX#8 PEG_TX#9

PEG_TX0

PEG_TX1

PEG_TX2

PEG_TX3

PEG_TX4

PEG_TX5

PEG_TX6

PEG_TX7

PEG_TX8

PEG_TX9 PEG_TX10 PEG_TX11 PEG_TX12 PEG_TX13 PEG_TX14 PEG_TX15

B26 A26 B27 A25

K35 J34 J33 G35 G32 F34 F31 D35 E33 C33 D32 B32 C31 B28 B30 A31

J35 H34 H33 F35 G33 E34 F32 D34 F33 B33 D31 A32 C30 A28 B29 A30

L33 M35 M33 M30 L31 K32 M29 J31 K29 H30 H29 F29 E28 D29 D27 C26

L34 M34 M32 L30 M31 K31 M28 H31 K28 G30 G29 F28 E27 D28 C27 C25

PEG_ICOMPI

PEG_ICOMPO

PEG_RCOMPO

PEG_RBIAS

DMI

PEG_RX#10 PEG_RX#11 PEG_RX#12 PEG_RX#13 PEG_RX#14 PEG_RX#15

Intel(R) FDI

PEG_TX#10 PEG_TX#11 PEG_TX#12 PEG_TX#13 PEG_TX#14 PEG_TX#15

PEG_IRCOMP_R

EXP_RBIAS

PCIE_MRX_GTX_N15 PCIE_MRX_GTX_N14 PCIE_MRX_GTX_N13 PCIE_MRX_GTX_N12 PCIE_MRX_GTX_N11 PCIE_MRX_GTX_N10 PCIE_MRX_GTX_N9 PCIE_MRX_GTX_N8 PCIE_MRX_GTX_N7 PCIE_MRX_GTX_N6 PCIE_MRX_GTX_N5 PCIE_MRX_GTX_N4 PCIE_MRX_GTX_N3 PCIE_MRX_GTX_N2 PCIE_MRX_GTX_N1 PCIE_MRX_GTX_N0

PCIE_MRX_GTX_P15 PCIE_MRX_GTX_P14 PCIE_MRX_GTX_P13 PCIE_MRX_GTX_P12 PCIE_MRX_GTX_P11 PCIE_MRX_GTX_P10 PCIE_MRX_GTX_P9 PCIE_MRX_GTX_P8 PCIE_MRX_GTX_P7 PCIE_MRX_GTX_P6 PCIE_MRX_GTX_P5 PCIE_MRX_GTX_P4 PCIE_MRX_GTX_P3 PCIE_MRX_GTX_P2 PCIE_MRX_GTX_P1 PCIE_MRX_GTX_P0

PCIE_MTX_GRX_C_N15 PCIE_MTX_GRX_C_N14 PCIE_MTX_GRX_C_N13 PCIE_MTX_GRX_C_N12 PCIE_MTX_GRX_C_N11 PCIE_MTX_GRX_C_N10 PCIE_MTX_GRX_C_N9 PCIE_MTX_GRX_C_N8 PCIE_MTX_GRX_C_N7 PCIE_MTX_GRX_C_N6 PCIE_MTX_GRX_C_N5 PCIE_MTX_GRX_C_N4 PCIE_MTX_GRX_C_N3 PCIE_MTX_GRX_C_N2 PCIE_MTX_GRX_C_N1 PCIE_MTX_GRX_C_N0

PCIE_MTX_GRX_C_P15 PCIE_MTX_GRX_C_P14 PCIE_MTX_GRX_C_P13 PCIE_MTX_GRX_C_P12 PCIE_MTX_GRX_C_P11 PCIE_MTX_GRX_C_P10 PCIE_MTX_GRX_C_P9 PCIE_MTX_GRX_C_P8 PCIE_MTX_GRX_C_P7 PCIE_MTX_GRX_C_P6 PCIE_MTX_GRX_C_P5 PCIE_MTX_GRX_C_P4 PCIE_MTX_GRX_C_P3 PCIE_MTX_GRX_C_P2 PCIE_MTX_GRX_C_P1 PCIE_MTX_GRX_C_P0

DW

07/10 Reversal

1.PCI-Express Static Lane Reversal (15 -> 0, 14 -> 1, ...)

C829 SCD1U10V2KX-5GP

C829 SCD1U10V2KX-5GP C827 SCD1U10V2KX-5GP

C827 SCD1U10V2KX-5GP C832 SCD1U10V2KX-5GP

C832 SCD1U10V2KX-5GP C812 SCD1U10V2KX-5GP

C812 SCD1U10V2KX-5GP C803 SCD1U10V2KX-5GP

C803 SCD1U10V2KX-5GP C811 SCD1U10V2KX-5GP

C811 SCD1U10V2KX-5GP C828 SCD1U10V2KX-5GP

C828 SCD1U10V2KX-5GP C810 SCD1U10V2KX-5GP

C810 SCD1U10V2KX-5GP C823 SCD1U10V2KX-5GP

C823 SCD1U10V2KX-5GP C804 SCD1U10V2KX-5GP

C804 SCD1U10V2KX-5GP C831 SCD1U10V2KX-5GP

C831 SCD1U10V2KX-5GP C825 SCD1U10V2KX-5GP

C825 SCD1U10V2KX-5GP C821 SCD1U10V2KX-5GP

C821 SCD1U10V2KX-5GP C813 SCD1U10V2KX-5GP

C813 SCD1U10V2KX-5GP C806 SCD1U10V2KX-5GP

C806 SCD1U10V2KX-5GP C816 SCD1U10V2KX-5GP

C816 SCD1U10V2KX-5GP C826 SCD1U10V2KX-5GP

C826 SCD1U10V2KX-5GP C822 SCD1U10V2KX-5GP

C822 SCD1U10V2KX-5GP C818 SCD1U10V2KX-5GP

C818 SCD1U10V2KX-5GP C815 SCD1U10V2KX-5GP

C815 SCD1U10V2KX-5GP C808 SCD1U10V2KX-5GP

C808 SCD1U10V2KX-5GP C802 SCD1U10V2KX-5GP

C802 SCD1U10V2KX-5GP C820 SCD1U10V2KX-5GP

C820 SCD1U10V2KX-5GP C805 SCD1U10V2KX-5GP

C805 SCD1U10V2KX-5GP C817 SCD1U10V2KX-5GP

C817 SCD1U10V2KX-5GP C801 SCD1U10V2KX-5GP

C801 SCD1U10V2KX-5GP C814 SCD1U10V2KX-5GP

C814 SCD1U10V2KX-5GP C824 SCD1U10V2KX-5GP

C824 SCD1U10V2KX-5GP C830 SCD1U10V2KX-5GP

C830 SCD1U10V2KX-5GP C809 SCD1U10V2KX-5GP

C809 SCD1U10V2KX-5GP C807 SCD1U10V2KX-5GP

C807 SCD1U10V2KX-5GP C819 SCD1U10V2KX-5GP

C819 SCD1U10V2KX-5GP

R801 49D9R2F-GPR801 49D9R2F-GP

1 2

R802 750R2F-GPR802 750R2F-GP

1 2

PCIE_MRX_GTX_N[0..15]

PCIE_MRX_GTX_P[0..15]

1 2

DIS

1 2

DIS

1 2

DIS

1 2

DIS

1 2

DIS

1 2

DIS

1 2

DIS

1 2

DIS

1 2

DIS

1 2

DIS

1 2

DIS

1 2

DIS

1 2

DIS

1 2

DIS

1 2

DIS

1 2

DIS

1 2

DIS

1 2

DIS

1 2

DIS

1 2

DIS

1 2

DIS

1 2

DIS

1 2

DIS

1 2

DIS

1 2

DIS

1 2

DIS

1 2

DIS

1 2

DIS

1 2

DIS

1 2

DIS

1 2

DIS

1 2

DIS

PCIE_MRX_GTX_N[0..15] [80]

PCIE_MRX_GTX_P[0..15] [80]

PCIE_MTX_GRX_N15 PCIE_MTX_GRX_N14 PCIE_MTX_GRX_N13 PCIE_MTX_GRX_N12 PCIE_MTX_GRX_N11 PCIE_MTX_GRX_N10 PCIE_MTX_GRX_N9 PCIE_MTX_GRX_N8 PCIE_MTX_GRX_N7 PCIE_MTX_GRX_N6 PCIE_MTX_GRX_N5 PCIE_MTX_GRX_N4 PCIE_MTX_GRX_N3 PCIE_MTX_GRX_N2 PCIE_MTX_GRX_N1 PCIE_MTX_GRX_N0

PCIE_MTX_GRX_P15 PCIE_MTX_GRX_P14 PCIE_MTX_GRX_P13 PCIE_MTX_GRX_P12 PCIE_MTX_GRX_P11 PCIE_MTX_GRX_P10 PCIE_MTX_GRX_P9 PCIE_MTX_GRX_P8 PCIE_MTX_GRX_P7 PCIE_MTX_GRX_P6 PCIE_MTX_GRX_P5 PCIE_MTX_GRX_P4 PCIE_MTX_GRX_P3 PCIE_MTX_GRX_P2 PCIE_MTX_GRX_P1 PCIE_MTX_GRX_P0

Title

Size Document Number Rev

Date: Sheet of

PCIE_MTX_GRX_N[0..15]

PCIE_MTX_GRX_P[0..15]

CPU (PCIE/DMI/FDI)

PCIE_MTX_GRX_N[0..15] [80]

PCIE_MTX_GRX_P[0..15] [80]

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Vostro Calpella

8 88Wednesday, September 09, 2009

X00

A

5

A

+1.05V_VTT

D D

C C

B B

+1.05V_VTT

DY

Processor Pullups

R902 49D9R2F-GPR902 49D9R2F-GP

1 2

R933 68R2-GPR933 68R2-GP

1 2

R904 68R2-GP

1 2

DY

+1.5V_CPU

12

PM_DRAM_PWRGD

PM_PWRBTN#_R[22]

12

C902

C902 SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

12

H_PWRGOOD

H_PWRGD_XDP

H_CATERR#

H_PROCHOT_R#

H_CPURST#

H_PROCHOT#[47]

H_PWRGOOD[25,42]

PM_DRAM_PWRGD[22]

H_VTTPWRGD[49]

S3 circuit

R919

R919 1K27R2F-L-GP

1K27R2F-L-GP

Normal 1.27k 3k

XDP Connector

R920

R920 3KR2F-GP

3KR2F-GP

1 2

DY

R927 1KR2J-1-GP

1 2

DY

R929 0R2J-2-GP

1 2

DY

R930 0R2J-2-GP

SML0_DATA[23]

SML0_CLK[23]

Processor Compensation Signals

1 2

R901 20R2F-GPR901 20R2F-GP

1 2

R903 20R2F-GPR903 20R2F-GP

1 2

R905 49D9R2F-GPR905 49D9R2F-GP

1 2

R906 49D9R2F-GPR906 49D9R2F-GP

TP901TPAD14-GP TP901TPAD14-GP

R936

R936 0R2J-2-GP

0R2J-2-GP

1 2

DY

R931

R931 1KR2J-1-GP

1KR2J-1-GP

XDP_RST#_R

1 2

R908 0R2J-2-GPR908 0R2J-2-GP

PLT_RST#[21,37,64,65,70,76,77,80]

R920R919

1.1k

No Stuff

0.75k

XDP_PREQ# XDP_PRDY#

XDP_OBS0 XDP_OBS1

XDP_OBS2 XDP_OBS3

XDP_OBS4 XDP_OBS5

XDP_OBS6 XDP_OBS7

H_CPUPWRGD_XDP PM_PWRBTN#_XDP

H_PWRGD_XDP_R

XDP_TCLK

1

H_THRMTRIP#[25,37,42]

1 2

DY

R913

R913 1K6R2F-GP

1K6R2F-GP

1 2

SKTOCC#_R

H_CATERR#

H_PECI[25]

H_PROCHOT_R#

H_PM_SYNC[22]

11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

STC-CONN60A-GP-U1

5

4

H_COMP3 H_COMP2 H_COMP1 H_COMP0

H_CPURST#

VCCPWRGOOD

PM_DRAM_PWRGD

H_PWRGD_XDP

PLT_RST#_R

12

R915

R915 750R2F-GP

750R2F-GP

XDP1

1 2 3 4

5 6 7 8 9 10

DY

4

NP1 61

62

63 64 NP2

AT23 AT24

G16

AT26

AH24

AK14

AT15

AN26

AK15

AP26

AL15

AN14

AN27

AK13

AM15

AM26

AL14

CPU1B

COMP3 COMP2 COMP1 COMP0

SKTOCC#

CATERR#

PECI

PROCHOT#

THERMTRIP#

RESET_OBS#

PM_SYNC

VCCPWRGOOD_1

VCCPWRGOOD_0

SM_DRAMPWROK

VTTPWRGOOD

TAPPWRGOOD

RSTIN#

CLARKUNF

BCLK_ITP_P BCLK_ITP_N

XDP_RST#_R

XDP_TRST# XDP_TDI XDP_TMS

3

2 OF 9

MISC THERMAL

CLOCKS

CLARKSFIELD

DDR3

MISC

DDR3

MISC

PWR MANAGEMENT

JTAG & BPM

+1.05V_VCCP use Decoupling Capacitor close ITP connector 100 mil ( max )

BCLK

BCLK#

BCLK_ITP

BCLK_ITP#

PEG_CLK

PEG_CLK#

DPLL_REF_SSCLK

DPLL_REF_SSCLK#

SM_DRAMRST#

SM_RCOMP0 SM_RCOMP1 SM_RCOMP2

PM_EXT_TS#0 PM_EXT_TS#1

PRDY# PREQ#

TCK TMS

TRST#

TDO

TDI_M

TDO_M

DBR#

BPM#0 BPM#1 BPM#2 BPM#3 BPM#4 BPM#5 BPM#6 BPM#7

TDI

CPU

TCK(PIN AN28)

SCD1U16V2KX-3GP

XDP_RST#_R

1 2

DY

R932 0R2J-2-GP

DPLL_REF_SSCLK#_R DPLL_REF_SSCLK_R

A16 B16

BCLK_ITP_P

AR30

BCLK_ITP_N

AT30 E16

D16

DPLL_REF_SSCLK_R

A18

DPLL_REF_SSCLK#_R

A17

SM_DRAMRST#

F6

SM_RCOMP_0

AL1

SM_RCOMP_1

AM1

SM_RCOMP_2

AN1

PM_EXTTS#0_C

AN15

PM_EXTTS#1_C

AP15

XDP_PRDY#

AT28

XDP_PREQ#

AP27

XDP_TCLK

AN28

XDP_TMS

AP28

XDP_TRST#

AT27

XDP_TDI_R

AT29

XDP_TDO_R

AR27

XDP_TDI_M

AR29

XDP_TDO_M

AP29

H_DBR#_R

AN25

XDP_OBS0

AJ22

XDP_OBS1

AK22

XDP_OBS2

AK24

XDP_OBS3

AJ24

XDP_OBS4

AJ25

XDP_OBS5

AH22

XDP_OBS6

AK23

XDP_OBS7

AH23

VTT_PWRGD[25,37,49,50]

XDP Connector

TCK(PIN 57)

+1.05V_VTT

12

C901

DY

12

R928

R928 51R2J-2-GP

51R2J-2-GP

3

1 2 3

DY

2 3 1

R909

XDP_DBRESET#

1 2

0R2J-2-GP

DW

07/10 Change

1. Change U927 from Operating v oltage Range 5 to 3 V .

R2114 10KR2J-3-GPR2114 10KR2J-3-GP

U927_B

1 2 3

XDP_TDO

PLT_RST# [21,37,64,65,70,76,77,80]

XDP_DBRESET# [22]

RN907

RN907 SRN1KJ-11-GP-U

SRN1KJ-11-GP-U

4

RN904

RN904 SRN0J-6-GP

SRN0J-6-GP

4

RN905

4

SRN10KJ-5-GP

1 2 3

RN906

SRN0J-6-GP

1 2

U927

B

5

VCC

A

4

Y

GND

74LVC1G08GW-1-GP

2

C915

BCLK_CPU_P [25] BCLK_CPU_N [25]

CLK_EXP_P [23] CLK_EXP_N [23]

CLK_DP_P [23] CLK_DP_N [23]

+1.05V_VTT

1 23

4

PM_EXTTS#0 [18] PM_EXTTS#1 [19]

+3.3V_ALW

VTT_PWRGD_R3 PM_DRAM_PWRGD

XDP_TDI_R

XDP_TDO_M

XDP_TDI_M

XDP_TDO_R

Scan Chain (Default) CPU Only

GMCH Only

S

DDR3 Compensation Signals

SM_RCOMP_0 SM_RCOMP_1 SM_RCOMP_2

Calpella Platform S3 Power Reduction Platform S3 Power Reduction CRB Implementation Design Details

R977

R977 1K6R2F-GP

1K6R2F-GP

12

DY

R921 0R2J-2-GPR921 0R2J-2-GP

R922 0R2J-2-GP

12

R924

R924 0R2J-2-GP

0R2J-2-GP

R925 0R2J-2-GP

R926 0R2J-2-GPR926 0R2J-2-GP

Stuff --> R921, R924, R926 No Stuff --> R922, R925 Stuff --> R921, R922 No Stuff --> R924, R926, R925 Stuff --> R926, R925 No Stuff --> R921, R922, R924

C915

12

SCD047U10V2KX1N2-GP

DY

G

1

2 3

DY

Vgs(th)<=1.5V

Q901

Q901 BSS138LT1

BSS138LT1

1 2

R935

R935 0R2J-2-GP

0R2J-2-GP

R907 100R2F-L1-GP-UR907 100R2F-L1-GP-U

1 2

R910 24D9R2F-L-GPR910 24D9R2F-L-GP

1 2

R911 130R2F-1-GPR911 130R2F-1-GP

1 2

DW

07/07 Added

1.Added discharge circuit 08/05 Changed

1.Changed Q901 from 2N7002 to B SS138 MOSFET,For Vgs(th)<=1.5V.

1 2

DY

1 2

DY

1 2

Title

ize Document Number Rev

Size Document Number Rev

S

Date: Sheet of

2

1

DDR_RST_GATE [25]

+1.5V_SUS

12

R934

DY

1KR2J-1-GP

D

0611

DDR3_DRAMRST# [18,19]

SM_DRAMRST#

Revision 0.1

XDP_TMS XDP_TDI_R XDP_PREQ#

XDP_TCLK

XDP_TDI

XDP_TDO

1 2

DY

R914 51R2J-2-GP

1 2

DY

R916 51R2J-2-GP

1 2

DY

R917 51R2J-2-GP

1 2

DY

R918 51R2J-2-GP

XDP_TRST#

JTAG MAPPING

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

CPU (THERMAL/CLOCK/PM )

Vostro Calpella

9 88Wednesday, September 09, 2009

1

1 2

DY

R988

R988 100KR2J-1-GP

100KR2J-1-GP

12

R923

R923 51R2J-2-GP

51R2J-2-GP

+1.05V_VTT

X00

A

5

CPU1C

4

3 OF 9

3

CPU1D

2

4 OF 9

1

W8

AA6

SA_CK0

AA7

M_A_DQ[63..0][18]

D D

C C

B B

M_A_DQ[63..0]

M_A_BS0[18] M_A_BS1[18] M_A_BS2[18]

M_A_CAS#[18] M_A_RAS#[18] M_A_WE#[18]

M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63

A10 C10

B10 D10 E10

F10

H10

G10

AH5 AF5 AK6 AK7 AF6 AG5 AJ7 AJ6

AJ10

AJ9 AL10 AK12

AK8

AL7 AK11

AL8

AN8

AM10 AR11

AL11

AM9

AN9 AT11 AP12

AM12 AN12 AM13

AT14 AT12 AL13

AR14

AP14

AC3

AB2

AE1

AB3

AE9

SA_DQ0 SA_DQ1

C7

SA_DQ2

A7

SA_DQ3 SA_DQ4 SA_DQ5 SA_DQ6

A8

SA_DQ7

D8

SA_DQ8 SA_DQ9

E6

SA_DQ10

F7

SA_DQ11

E9

SA_DQ12

B7

SA_DQ13

E7

SA_DQ14

C6

SA_DQ15 SA_DQ16

G8

SA_DQ17

K7

SA_DQ18

J8

SA_DQ19

G7

SA_DQ20 SA_DQ21

J7

SA_DQ22

J10

SA_DQ23

L7

SA_DQ24

M6

SA_DQ25

M8

SA_DQ26

L9

SA_DQ27

L6

SA_DQ28

K8

SA_DQ29

N8

SA_DQ30

P9

SA_DQ31 SA_DQ32 SA_DQ33 SA_DQ34 SA_DQ35 SA_DQ36 SA_DQ37 SA_DQ38 SA_DQ39 SA_DQ40 SA_DQ41 SA_DQ42 SA_DQ43 SA_DQ44 SA_DQ45 SA_DQ46 SA_DQ47 SA_DQ48 SA_DQ49 SA_DQ50 SA_DQ51 SA_DQ52 SA_DQ53 SA_DQ54 SA_DQ55 SA_DQ56 SA_DQ57 SA_DQ58 SA_DQ59 SA_DQ60 SA_DQ61 SA_DQ62 SA_DQ63

SA_BS0 SA_BS1

U7

SA_BS2

SA_CAS# SA_RAS# SA_WE#

SA_CK#0

P7

SA_CKE0

Y6

SA_CK1

Y5

SA_CK#1

P6

SA_CKE1

AE2

SA_CS#0

AE8

SA_CS#1

CLARKSFIELD

AD8

SA_ODT0

AF9

SA_ODT1

M_A_DM0

B9

SA_DM0 SA_DM1 SA_DM2 SA_DM3 SA_DM4 SA_DM5 SA_DM6 SA_DM7

SA_DQS#0 SA_DQS#1 SA_DQS#2 SA_DQS#3 SA_DQS#4 SA_DQS#5 SA_DQS#6 SA_DQS#7

SA_DQS0 SA_DQS1 SA_DQS2 SA_DQS3 SA_DQS4 SA_DQS5 SA_DQS6 SA_DQS7

DDR SYSTEM MEMORY A

SA_MA0 SA_MA1 SA_MA2 SA_MA3 SA_MA4 SA_MA5 SA_MA6 SA_MA7 SA_MA8

SA_MA9 SA_MA10 SA_MA11 SA_MA12 SA_MA13 SA_MA14 SA_MA15

D7 H7 M7 AG6 AM7 AN10 AN13

C9 F8 J9 N9 AH7 AK9 AP11 AT13

C8 F9 H9 M9 AH8 AK10 AN11 AR13

Y3 W1 AA8 AA3 V1 AA9 V8 T1 Y9 U6 AD4 T2 U3 AG8 T3 V9

M_A_DM1 M_A_DM2 M_A_DM3 M_A_DM4 M_A_DM5 M_A_DM6 M_A_DM7

M_A_DQS#0 M_A_DQS#1 M_A_DQS#2 M_A_DQS#3 M_A_DQS#4 M_A_DQS#5 M_A_DQS#6 M_A_DQS#7

M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6 M_A_DQS7

M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14 M_A_A15

M_CLK_DDR0 [18] M_CLK_DDR#0 [18] M_CKE0 [18]

M_CLK_DDR1 [18] M_CLK_DDR#1 [18] M_CKE1 [18]

M_CS0# [18] M_CS1# [18]

M_ODT0 [18] M_ODT1 [18]

M_B_DQ[63..0][19]

M_A_DM[7..0] [18] M_A_DQS#[7..0] [18]

M_A_DQS[7..0] [18] M_A_A[15..0] [18]

M_B_DQ[63..0]

M_B_BS0[19] M_B_BS1[19] M_B_BS2[19]

M_B_CAS#[19] M_B_RAS#[19] M_B_WE#[19]

M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63

AF3 AG1

AK1 AG4 AG3

AH4 AK3 AK4 AM6 AN2 AK5 AK2 AM4 AM3 AP3 AN5 AT4 AN6 AN4 AN3 AT5 AT6 AN7 AP6 AP8 AT9 AT7

AP9 AR10 AT10

AC5

AC6

AJ3

AJ4

AB1

B5

SB_DQ0

A5

SB_DQ1

C3

SB_DQ2

B3

SB_DQ3

E4

SB_DQ4

A6

SB_DQ5

A4

SB_DQ6

C4

SB_DQ7

D1

SB_DQ8

D2

SB_DQ9

F2

SB_DQ10

F1

SB_DQ11

C2

SB_DQ12

F5

SB_DQ13

F3

SB_DQ14

G4

SB_DQ15

H6

SB_DQ16

G2

SB_DQ17

J6

SB_DQ18

J3

SB_DQ19

G1

SB_DQ20

G5

SB_DQ21

J2

SB_DQ22

J1

SB_DQ23

J5

SB_DQ24

K2

SB_DQ25

L3

SB_DQ26

M1

SB_DQ27

K5

SB_DQ28

K4

SB_DQ29

M4

SB_DQ30

N5

SB_DQ31 SB_DQ32 SB_DQ33 SB_DQ34 SB_DQ35 SB_DQ36 SB_DQ37 SB_DQ38 SB_DQ39 SB_DQ40 SB_DQ41 SB_DQ42 SB_DQ43 SB_DQ44 SB_DQ45 SB_DQ46 SB_DQ47 SB_DQ48 SB_DQ49 SB_DQ50 SB_DQ51 SB_DQ52 SB_DQ53 SB_DQ54 SB_DQ55 SB_DQ56 SB_DQ57 SB_DQ58 SB_DQ59 SB_DQ60 SB_DQ61 SB_DQ62 SB_DQ63

SB_BS0

W5

SB_BS1

R7

SB_BS2

SB_CAS#

Y7

SB_RAS# SB_WE#

CLARKSFIELD

DDR SYSTEM MEMORY - B

SB_CK0 SB_CK#0 SB_CKE0

SB_CK1 SB_CK#1 SB_CKE1

SB_CS#0 SB_CS#1

SB_ODT0 SB_ODT1

SB_DM0 SB_DM1 SB_DM2 SB_DM3 SB_DM4 SB_DM5 SB_DM6 SB_DM7

SB_DQS#0 SB_DQS#1 SB_DQS#2 SB_DQS#3 SB_DQS#4 SB_DQS#5 SB_DQS#6 SB_DQS#7

SB_DQS0 SB_DQS1 SB_DQS2 SB_DQS3 SB_DQS4 SB_DQS5 SB_DQS6 SB_DQS7

SB_MA0

SB_MA1

SB_MA2

SB_MA3

SB_MA4

SB_MA5

SB_MA6

SB_MA7

SB_MA8

SB_MA9 SB_MA10 SB_MA11 SB_MA12 SB_MA13 SB_MA14 SB_MA15

W9 M3

V7 V6 M2

AB8 AD6

AC7 AD1

D4 E1 H3 K1 AH1 AL2 AR4 AT8

D5 F4 J4 L4 AH2 AL4 AR5 AR8

C5 E3 H4 M5 AG2 AL5 AP5 AR7

U5 V2 T5 V3 R1 T8 R2 R6 R4 R5 AB5 P3 R3 AF7 P5 N1

M_B_DM0 M_B_DM1 M_B_DM2 M_B_DM3 M_B_DM4 M_B_DM5 M_B_DM6 M_B_DM7

M_B_DQS#0 M_B_DQS#1 M_B_DQS#2 M_B_DQS#3 M_B_DQS#4 M_B_DQS#5 M_B_DQS#6 M_B_DQS#7

M_B_DQS0 M_B_DQS1 M_B_DQS2 M_B_DQS3 M_B_DQS4 M_B_DQS5 M_B_DQS6 M_B_DQS7

M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14 M_B_A15

M_CLK_DDR2 [19] M_CLK_DDR#2 [19] M_CKE2 [19]

M_CLK_DDR3 [19] M_CLK_DDR#3 [19] M_CKE3 [19]

M_CS2# [19] M_CS3# [19]

M_ODT2 [19] M_ODT3 [19]

M_B_DM[7..0] [19] M_B_DQS#[7..0] [19]

M_B_DQS[7..0] [19] M_B_A[15..0] [19]

CLARKUNF

A A

5

4

3

CLARKUNF

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU (DDR)

Size Document Number Rev

Date: Sheet of

2

Date: Sheet of

CPU (DDR)

Vostro Calpella

1

X00

10 88Wednesday, September 09, 2009

X00

5

D D

CFG0

CFG3

C C

CFG4

B B

DIS

12

R1101

R1101 3KR2F-GP

3KR2F-GP

DY

改改改改

5%

12

R1102

R1102 3KR2F-GP

3KR2F-GP

DW

07/10 Reversal

1.PCI-Express Static Lane Reversal

12

R1103

R1103 3KR2F-GP

3KR2F-GP

DY

PCI-Express Configuration Select

1:Single PEG

CFG0

0:Bifurcation enabled

CFG3 - PCI-Express Static Lane Reversal

1 :Normal Operation

CFG3

0 :Lane Numbers Reversed 15 -> 0, 14 -> 1, ...

CFG4 - Display Port Presence

1:Disabled; No Physical Display Port

CFG4

attached to Embedded Display Port 0:Enabled; An external Display Port device is connected to the Embedded Display Port

Calpella Platform Design Guide Revision 1.6

4.8.3.1 LVDS Switching

Switchable GFX, just like integrated GFX only, to enable LVDS it is required that the OEM set the LDVS (L_DDC_DATA) strap to present (pulled up) and the eDP strap (CFG[4]) to disabled (not pulled down).

4.8.3.2 eDP Switching

eDP for Switchable GFX can only be driven out of Port D of PCH. To configure Port D for embedded DP it is required to set the DDPD_CTRLDATA strap high to 3.3V Core rail through 2.2 kΩ ±5% resistor, LVDS (L_DDC_DATA) strap as no connect and the eDP strap CFG[4] as no connect.

CFG7

TP1118

TP1118 TPAD14-GP

TPAD14-GP

1

DW

07/02 Del R1104

1.DW50 Only support Arrandale

A A

5

CFG7(Reserved) - Temporarily used for early Clarksfield samples.

CFG7 Clarksfield (only for early samples pre-ES1) -

Connect to GND with 3.01K Ohm/5% resistor. Note: Only temporary for early CFD sample

(rPGA/BGA) [For details please refer to the WW33 MoW and sighting report]. For a common M/B design (for AUB and CFD), the pull-down resistor shouble be used. Does not impact AUB functionality.

4

Page 482,486

DW

07/02 Added

1.Added display Switchable strap commentariat

4

3

AP25

AL25 AL24 AL22 AJ33

AG9 M27

CFG0

CFG3 CFG4

CFG7

AM30 AM28

AP31

AL32 AL30

AM31

AN29

AM32

AK32 AK31 AK28

AJ28 AN30 AN32

AJ32

AJ29

AJ30 AK30

L28

J17 H17 G25 G17 E31 E30

H16

B19 A19

A20 B20

U9 T9

AC9

AB9

J29

J28

TP1116TP1116 TP1117TP1117

3

SA_DIMM_VREF#

1

SB_DIMM_VREF#

1

CPU1E

RSVD#AP25 RSVD#AL25 RSVD#AL24 RSVD#AL22 RSVD#AJ33 RSVD#AG9 RSVD#M27 RSVD#L28 SA_DIMM_VREF SB_DIMM_VREF RSVD#G25 RSVD#G17 RSVD#E31 RSVD#E30

CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15 CFG16 CFG17 RSVD_TP_86

RSVD#B19 RSVD#A19

RSVD#A20 RSVD#B20

RSVD#U9 RSVD#T9

RSVD#AC9 RSVD#AB9

RSVD#J29 RSVD#J28

CLARKUNF

2

CLARKSFIELD

RESERVED

2

5 OF 9

RSVD#AJ13 RSVD#AJ12

RSVD#AH25 RSVD#AK26

RSVD#AL26

RSVD_NCTF_37

RSVD#AJ26 RSVD#AJ27

RSVD#AL28 RSVD#AL29 RSVD#AP30 RSVD#AP32 RSVD#AL27 RSVD#AT31 RSVD#AT32 RSVD#AP33 RSVD#AR33

RSVD#AR32

RSVD_TP#E15 RSVD_TP#F15

RSVD#D15 RSVD#C15

RSVD#AJ15

RSVD#AH15

SA_CK2 SA_CK#2 SA_CKE2 SA_CS#2 SA_ODT2

SA_CK3 SA_CK#3 SA_CKE3 SA_CS#3 SA_ODT3

SB_CK2 SB_CK#2 SB_CKE2 SB_CS#2 SB_ODT2

SB_CK3 SB_CK#3 SB_CKE3 SB_CS#3 SB_ODT3

1

AJ13 AJ12

AH25 AK26

AL26 AR2

AJ26 AJ27

AL28 AL29 AP30 AP32 AL27 AT31 AT32 AP33 AR33

AR32

E15 F15 A2

KEY

D15 C15 AJ15 AH15

AA5 AA4 R8 AD3 AD2 AA2 AA1 R9 AG7 AE3

V4 V5 N2 AD5 AD7 W3 W2 N3 AE5 AD9

AP34

VSS

VSS (AP34) can be left NC is CRB implementation; EDS/DG recommendation to GND.

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Date: Sheet of

CPU (RESERVED)

Taipei Hsien 221, Taiwan, R.O.C.

Vostro Calpella

11 88Wednesday, September 09, 2009

1

X00

5

4

CPU1F

3

6 OF 9

2

1

+VCC_CORE

PROCESSOR CORE POWER

+VCC_CORE

D D

C C

B B

DY

C1206

C1207

12

SC10U6D3V5MX-3GP

C1212

C1213

12

SC10U6D3V5MX-3GP

C1226

C1225

12

C1243

12

SC10U6D3V5MX-3GP

C1235

SC10U6D3V5MX-3GP

C1236

12

SC10U6D3V5MX-3GP

12

C1214

12

C1208

C1227

C1237

C1209

C1220

C1210

12

SC10U6D3V5MX-3GP

C1215

12

SC22U6D3V5MX-2GP

C1228

12

SC10U6D3V5MX-3GP

C1238

12

SC10U6D3V5MX-3GP

C1210

12

SC10U6D3V5MX-3GP

C1224

C1223

12

C1229

C1239

SC10U6D3V5MX-3GP

C1231

C1230

12

SC10U6D3V5MX-3GP

12

SC22U6D3V5MX-2GP

C1240

SC10U6D3V5MX-3GP

C1241

12

SC22U6D3V5MX-2GP

48A

C1232

12

SC10U6D3V5MX-3GP

C1242

12

SC22U6D3V5MX-2GP

AG35 AG34 AG33 AG32 AG31 AG30 AG29 AG28 AG27 AG26

AF35 AF34 AF33 AF32 AF31 AF30 AF29 AF28 AF27

AF26 AD35 AD34 AD33 AD32 AD31 AD30 AD29 AD28 AD27 AD26 AC35 AC34 AC33 AC32 AC31 AC30 AC29 AC28 AC27 AC26

AA35

AA34

AA33

AA32

AA31

AA30

AA29

AA28

AA27

AA26

VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC

Y35

VCC

Y34

VCC

Y33

VCC

Y32

VCC

Y31

VCC

Y30

VCC

Y29

VCC

Y28

VCC

Y27

VCC

Y26

VCC

V35

VCC

V34

VCC

V33

VCC

V32

VCC

V31

VCC

V30

VCC

V29

VCC

V28

VCC

V27

VCC

V26

VCC

U35

VCC

U34

VCC

U33

VCC

U32

VCC

U31

VCC

U30

VCC

U29

VCC

U28

VCC

U27

VCC

U26

VCC

R35

VCC

R34

VCC

R33

VCC

R32

VCC

R31

VCC

R30

VCC

R29

VCC

R28

VCC

R27

VCC

R26

VCC

P35

VCC

P34

VCC

P33

VCC

P32

VCC

P31

VCC

P30

VCC

P29

VCC

P28

VCC

P27

VCC

P26

VCC

CLARKSFIELD

1.1V RAIL POWER

CPU CORE SUPPLY

PROC_DPRSLPVR

CPU VIDS

POWER

VTT_SELECT

VSS_SENSE_VTT

SENSE LINES

VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0

VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0

PSI#

ISENSE

VCC_SENSE

VSS_SENSE

VTT_SENSE

VID VID VID VID VID VID VID

AH14 AH12 AH11 AH10 J14 J13 H14 H12 G14 G13 G12 G11 F14 F13 F12 F11 E14 E12 D14 D13 D12 D11 C14 C13 C12 C11 B14 B12 A14 A13 A12 A11

AF10 AE10 AC10 AB10 Y10 W10 U10 T10 J12 J11 J16 J15

AN33

CPU_VID0

AK35

CPU_VID1

AK33

CPU_VID2

AK34

CPU_VID3

AL35

CPU_VID4

AL33

CPU_VID5

AM33

CPU_VID6

AM35 AM34

TP_H_VTTVID1

G15

AN35

VCC_SENSE

AJ34

VSS_SENSE

AJ35

B15

TP_VSS_SENSE_VTT

A15

12

C1201

C1216

SC10U10V5ZY-1GP

C1233

12

SC10U6D3V5MX-3GP

PSI# [47] CPU_VID[6..0] [47]

PM_DPRSLPVR [47]

1

TP1203

TPAD14-GP

IMVP_IMON [47]

1

TPAD14-GP

VTT_SENSE [49]

TP1202

TP1202 TPAD14-GP

TPAD14-GP

H_VTTVID1 = Low, 1.1V H_VTTVID1 = High, 1.05V

12

C1218

C1217

SC22U6D3V5MX-2GP

C1211

12

SC10U6D3V5MX-3GP

C1234

12

SC10U6D3V5MX-3GP

SC10U10V5ZY-1GP

C1221

SC10U6D3V5MX-3GP

12

C1222

12

SC10U6D3V5MX-3GP

+1.05V_VTT

SC22U6D3V5MX-2GP

+1.05V_VTT

12

C1204

C1205

SC10U10V5ZY-1GP

DY

The decoupling capacitors, filter recommendations and sense resistors on the CPU/PCH Rails are specific to the CRB Implementation. Customers need to follow the recommendations in the Calpella Platform Design Guide.

C1203

12

Please note that the VTT Rail Values are Arrandale VTT=1.05V; Clarksfield VTT=1.1V

+VCC_CORE

12

R1201

R1201 100R2F-L1-GP-U

100R2F-L1-GP-U

VCC_SENSE [47]

12

R1204

R1204 100R2F-L1-GP-U

100R2F-L1-GP-U

VSS_SENSE [47]

+1.05V_VTT

12

A A

CLARKUNF

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Date: Sheet of

CPU (VCC_CORE)

Taipei Hsien 221, Taiwan, R.O.C.

Vostro Calpella

12 88Wednesday, September 09, 2009

1

X00

5

4

3

2

1

+1.5V_CPU

12

DY

C1376

C1376 SCD1U10V2KX-4GP

+CPU_GFXCORE

D D

C C

22A

TC1303

SE330U2VDM-L-GP

12

DY

C1327

C1326

12

SC22U6D3V5MX-2GP

C1328

SC22U6D3V5MX-2GP

12

SC10U6D3V5MX-3GP

Please note that the VTT Rail Values are Arrandale VTT=1.05V; Clarksfield VTT=1.1V

+1.05V_VTT

12

C1309

C1309 SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

+1.05V_VTT

B B

18A

12

C1312

12

C1314

C1315

SC10U6D3V5MX-3GP

AT21 AT19 AT18 AT16 AR21 AR19 AR18 AR16 AP21 AP19 AP18 AP16 AN21 AN19 AN18 AN16 AM21 AM19 AM18 AM16

AL21 AL19 AL18

AL16 AK21 AK19 AK18 AK16

AJ21

AJ19

AJ18

AJ16 AH21 AH19 AH18 AH16

J24 J23 H25

K26 J27 J26 J25 H27 G28 G27 G26 F26 E26 E25

CPU1G

VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG

VTT1 VTT1 VTT1

VTT1 VTT1 VTT1 VTT1 VTT1 VTT1 VTT1 VTT1 VTT1 VTT1 VTT1

SENSE

GRAPHICS

CLARKSFIELD

FDI PEG & DMI

POWER

LINES

GRAPHICS VIDs

7 OF 9

GFX_VID GFX_VID GFX_VID GFX_VID GFX_VID GFX_VID GFX_VID

GFX_IMON

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VTT0 VTT0 VTT0 VTT0

VTT1 VTT1 VTT1 VTT1 VTT1 VTT1

VCCPLL VCCPLL VCCPLL

AR22 AT22

AM22 AP22 AN22 AP23 AM23 AP24 AN24

AR25

TP_GFX_DPRSLPVR

AT25 AM24

AJ1 AF1 AE7 AE4 AC1 AB7 AB4 Y1 W7 W4 U1 T7 T4 P1 N7 N4 L1 H1

P10 N10 L10 K10

J22 J20 J18 H21 H20 H19

L26 L27 M26

SC10U6D3V5MX-3GP

VAXG_SENSE

VSSAXG_SENSE

GFX_VR_EN

GFX_DPRSLPVR

DDR3 - 1.5V RAILS

1.1V1.8V

VCCPLL1 VCCPLL2 VCCPLL3

12

C1301

SC1U10V2KX-1GP

C1310

C1316

SCD1U10V2KX-4GP

+1.5V_SUS

VCC_AXG_SENSE [53] VSS_AXG_SENSE [53]

GFX_VID0 [53] GFX_VID1 [53] GFX_VID2 [53] GFX_VID3 [53] GFX_VID4 [53] GFX_VID5 [53] GFX_VID6 [53]

GFX_VR_EN [53]

TP1303TPAD14-GPTP1303TPAD14-GP

1

GFX_IMON [53]

12

C1302

C1303

SC1U10V2KX-1GP

12

C1318

SC1U25V5KX-1GP

12

SC1U10V2KX-1GP

12

C1311

C1311 SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

C1319

SC1U25V5KX-1GP

C1304

12

SC1U10V2KX-1GP

C1320

SC4D7U6D3V5KX-3GP

+1.5V_CPU

12

DY

+1.5V_SUS

C1377

C1377 SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

+1.5V_CPU

12

DY

+1.5V_SUS

C1378

C1378 SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

425302_425302_Calpella_S3PowerReduction_WhitePape

+1.5V_CPU

12

C1307

C1306

SC10U6D3V5MX-3GP

12

C1322

C1322 SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

12

TC1301

TC1301 SE330U2D5VDM-2GP

SE330U2D5VDM-2GP

+1.8V_RUN

12

3A

C1305

12

SC1U10V2KX-1GP

+1.05V_VTT

1.35A

C1321

SC2D2U10V3KX-1GP

+1.5V_CPU

12

DY

C1379

C1379 SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

+1.5V_SUS

Revision 0.7

CLARKUNF

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU (VCC_GFXCORE)

ize Document Number Rev

Size Document Number Rev

S

Date: Sheet of

CPU (VCC_GFXCORE)

Vostro Calpella

13 88Wednesday, September 09, 2009

1

X00

5

CPU1H

AT20

VSS

AT17

VSS

AR31

VSS

AR28

VSS

AR26

VSS

AR24

VSS

D D

C C

B B

AR23 AR20 AR17 AR15 AR12

AR9 AR6

AR3 AP20 AP17 AP13 AP10

AP7

AP4

AP2 AN34 AN31 AN23 AN20 AN17 AM29 AM27 AM25 AM20 AM17 AM14 AM11

AM8

AM5

AM2

AL34 AL31 AL23 AL20 AL17 AL12

AL9 AL6

AL3 AK29 AK27 AK25 AK20 AK17

AJ31 AJ23 AJ20 AJ17 AJ14 AJ11

AJ8

AJ5

AJ2 AH35 AH34 AH33 AH32 AH31 AH30 AH29 AH28 AH27 AH26 AH20 AH17 AH13

AH9 AH6 AH3

AG10

AF8

AF4

AF2 AE35

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

4

CLARKSFIELD

VSS

8 OF 9

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

AE34 AE33 AE32 AE31 AE30 AE29 AE28 AE27 AE26 AE6 AD10 AC8 AC4 AC2 AB35 AB34 AB33 AB32 AB31 AB30 AB29 AB28 AB27 AB26 AB6 AA10 Y8 Y4 Y2 W35 W34 W33 W32 W31 W30 W29 W28 W27 W26 W6 V10 U8 U4 U2 T35 T34 T33 T32 T31 T30 T29 T28 T27 T26 T6 R10 P8 P4 P2 N35 N34 N33 N32 N31 N30 N29 N28 N27 N26 N6 M10 L35 L32 L29 L8 L5 L2 K34 K33 K30

3

CPU1I

K27

VSS

K9

VSS

K6

VSS

K3

VSS

J32

VSS

J30

VSS

J21

VSS

J19

VSS

H35

VSS

H32

VSS

H28

VSS

H26

VSS

H24

VSS

H22

VSS

H18

VSS

H15

VSS

H13

VSS

H11

VSS

H8

VSS

H5

VSS

H2

VSS

G34

VSS

G31

VSS

G20

VSS

G9

VSS

G6

VSS

G3

VSS

F30

VSS

F27

VSS

F25

VSS

F22

VSS

F19

VSS

F16

VSS

E35

VSS

E32

VSS

E29

VSS

E24

VSS

E21

VSS

E18

VSS

E13

VSS

E11

VSS

E8

VSS

E5

VSS

E2

VSS

D33

VSS

D30

VSS

D26

VSS

D9

VSS

D6

VSS

D3

VSS

C34

VSS

C32

VSS

C29

VSS

C28

VSS

C24

VSS

C22

VSS

C20

VSS

C19

VSS

C16

VSS

B31

VSS

B25

VSS

B21

VSS

B18

VSS

B17

VSS

B13

VSS

B11

VSS

B8

VSS

B6

VSS

B4

VSS

A29

VSS

A27

VSS

A23

VSS

A9

VSS

2

9 OF 9

CLARKSFIELD

VSS

VSS_NCTF VSS_NCTF VSS_NCTF

NCTF

VSS_NCTF#A35

VSS_NCTF#AT1

VSS_NCTF#AT35

VSS_NCTF#B1

RSVD_NCTF#A3 RSVD_NCTF#A33 RSVD_NCTF#A34 RSVD_NCTF#AP1

RSVD_NCTF#AP35

RSVD_NCTF#AR1

RSVD_NCTF#AR35

RSVD_NCTF#AT2 RSVD_NCTF#AT3

RSVD_NCTF#AT33 RSVD_NCTF#AT34

RSVD_NCTF#C1 RSVD_NCTF#C35

NCYF TEST PIN:

A35,AT1,AT35,B1,A3,A33,A34,

NCYF TEST PIN:

A35,AT1,AT35,B1,A3,A33,A34,

RSVD_NCTF#B35

AP1,AP35,AR1,AR35,AT2,AT3,

AT33,AT34,C1,C35,B35

AP1,AP35,AR1,AR35,AT2,AT3,

AT33,AT34,C1,C35,B35

AR34 B34 B2

A35 AT1 AT35 B1 A3 A33 A34 AP1 AP35 AR1 AR35 AT2 AT3 AT33 AT34 C1 C35 B35

TP_MCP_VSS_NCTF2 TP_MCP_VSS_NCTF3 TP_MCP_VSS_NCTF4 TP_MCP_VSS_NCTF1

1

TP1402TP1402

1

TP1406TP1406

1

TP1405TP1405

1

TP1401TP1401

1

CLARKUNF

A A

5

4

3

CLARKUNF

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Date: Sheet of

2

Date: Sheet of

CPU (VSS)

Vostro Calpella

1

X00

14 88Wednesday, September 09, 2009

X00

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved

Size Document Number Rev

A3

Date: Sheet of

Reserved

Vostro Calpella

15 88Wednesday, September 09, 2009

1

X00

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved

Size Document Number Rev

A3

Date: Sheet of

Reserved

Vostro Calpella

16 88Wednesday, September 09, 2009

1

X00

5

D D

C C

4

3

2

1

(Blank)

B B

A A

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Custom

Date: Sheet of

5

4

3

2

Date: Sheet of

Vostro Calpella

Taipei Hsien 221, Taiwan, R.O.C.

(Reserve)

1

SA

17 88Wednesday, September 09, 2009

SA

5

SSID = MEMORY

M_A_DQS#[7..0][10]

12

C1804

C1804 SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

5

M_A_DQ[63..0][10] M_A_DM[7..0][10] M_A_DQS[7..0][10] M_A_A[15..0][10]

12

Layout Note: Place near DM1

12

C1812

C1812 SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

C1802

C1802 SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

+0.75V_DDR_VTT

12

C1814

C1814 SC1U10V2KX-1GP

SC1U10V2KX-1GP

12

C1873

C1873 SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

12

C1811

C1811 SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

C1816

C1816 SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

Layout Note: Put close to VTT1,VTT2.

12

C1813

C1813 SC1U10V2KX-1GP

SC1U10V2KX-1GP

12

C1801

C1801 SC1U10V2KX-1GP

SC1U10V2KX-1GP

C1815

C1815 SC1U10V2KX-1GP

SC1U10V2KX-1GP

DW

07/10 Added

1.Added Power Decoupling Cap C1822,C1823 Bason on design guide

C1874

C1874 SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

425302_425302_Calpella_S3PowerReduction_WhitePape

+V_DDR_REF

C1810

C1810 SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

C1817

C1817 SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

12

+V_DDR_REF

12

D D

+1.5V_SUS

C C

C1803

C1803 SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

B B

+1.5V_SUS

12

C1872

C1872 SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

A A

4

12

C1875

C1875 SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

12

C1809

C1809 SC2D2U10V3KX-1GP

SC2D2U10V3KX-1GP

12

C1805

C1805 SC2D2U10V3KX-1GP

SC2D2U10V3KX-1GP

4

12

TC1803

TC1803 ST330U2D5VBM-1-GP

ST330U2D5VBM-1-GP

12

C1823

C1823 SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

Revision 0.7

M_A_BS2[10] M_A_BS0[10]

M_A_BS1[10]

+0.75V_DDR_VTT

3

DM1

3

98 97 96 95 92 91 90 86 89 85

107

84 83

119

80 78 79

109 108

5

7 15 17

4

6 16 18 21 23 33 35 22 24 34 36 39 41 51 53 40 42 50 52 57 59 67 69 56 58 68 70

129 131 141 143 130 132 140 142 147 149 157 159 146 148 158 160 163 165 175 177 164 166 174 176 181 183 191 193 180 182 192 194

10 27 45 62

135 152 169 186

12 29 47 64

137 154 171 188

116 120

126

1 30

203 204

DM1

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15 A16/BA2

BA0 BA1

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32

Height 5.2mm

DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63

DQS0# DQS1# DQS2# DQS3# DQS4# DQS5# DQS6# DQS7#

DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7

ODT0 ODT1

VREF_CA VREF_DQ

RESET#

VTT1 VTT2

DDR3-204P-47-GP

NP1 NP2

RAS#

WE#

CAS# CS0#

CS1# CKE0

CKE1

CK0

CK0#

CK1

CK1#

DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7

SDA

SCL

EVENT#

VDDSPD

SA0 SA1

NC#1 NC#2

NC#/TEST

VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8

VDD9 VDD10 VDD11 VDD12 VDD13 VDD14 VDD15 VDD16 VDD17 VDD18

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

NP1 NP2

110 113 115

114 121

73 74

101 103

102 104

11 28 46 63 136 153 170 187

200 202

198 199 197

201 77

122 125

75 76 81 82 87 88 93 94 99 100 105 106 111 112 117 118 123 124

2 3 8 9 13 14 19 20 25 26 31 32 37 38 43 44 48 49 54 55 60 61 65 66 71 72 127 128 133 134 138 139 144 145 150 151 155 156 161 162 167 168 172 173 178 179 184 185 189 190 195 196 205 206

M_CLK_DDR0 M_CLK_DDR#0

M_CLK_DDR1 M_CLK_DDR#1

M_A_DM0 M_A_DM1 M_A_DM2 M_A_DM3 M_A_DM4 M_A_DM5 M_A_DM6 M_A_DM7

PCH_SMBDATA PCH_SMBCLK

SA0_DM1 SA1_DM1

+1.5V_SUS

62.10017.P31

M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14 M_A_A15 M_A_BS2

M_A_BS0 M_A_BS1

M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63

M_A_DQS#0 M_A_DQS#1 M_A_DQS#2 M_A_DQS#3 M_A_DQS#4 M_A_DQS#5 M_A_DQS#6 M_A_DQS#7

M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6 M_A_DQS7

M_ODT0[10] M_ODT1[10]

M_ODT0 M_ODT1

DDR3_DRAMRST#[9,19]

2

M_A_RAS# [10]

M_A_WE# [10]

M_A_CAS# [10] M_CS0# [10]

M_CS1# [10] M_CKE0 [10]

M_CKE1 [10] M_CLK_DDR0 [10]

M_CLK_DDR#0 [10] M_CLK_DDR1 [10]

M_CLK_DDR#1 [10]

PCH_SMBDATA [7,19,23,40,64,65] PCH_SMBCLK [7,19,23,40,64,65]

PM_EXTTS#0 [9]

C1806

C1806 SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

2

1

SA0_DM1 SA1_DM1

12

R1802

R1802 10KR2J-3-GP

10KR2J-3-GP

12

R1801

R1801 10KR2J-3-GP

10KR2J-3-GP

SMBUS address:A0

DW

07/02 Reserve

+3.3V_RUN

12

DY

C1807

C1807 SC2D2U10V3KX-1GP

SC2D2U10V3KX-1GP

Title

DDRIII-SODIMM SLOT1

ize Document Number Rev

Size Document Number Rev

S

Custom

Date: Sheet of

DDRIII-SODIMM SLOT1

Vostro Calpella

1.Added SA0_DM1 pull-up resistor 07/07

2.Reserve pull-hi,lo resistor

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

18 88Wednesday, September 09, 2009

1

SA

5

SSID = MEMORY

M_B_DQS#[7..0][10]

D D

C C

B B

A A

M_B_DQ[63..0][10] M_B_DM[7..0][10] M_B_DQS[7..0][10] M_B_A[15..0][10]

+1.5V_SUS

12

C1919

C1919 SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

+0.75V_DDR_VTT

12

C1908

C1908 SC1U10V2KX-1GP

SC1U10V2KX-1GP

+1.5V_SUS

12

C1976

C1976 SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

5

12

C1911

C1911 SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

C1905

C1905 SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

12

C1909

C1909 SC1U10V2KX-1GP

SC1U10V2KX-1GP

C1917

C1917 SC1U10V2KX-1GP

SC1U10V2KX-1GP

Layout Note: Place near DM2

12

Layout Note: Put close to VTT1,VTT2.

12

C1977

C1977 SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

12

C1913

C1913 SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

C1916

C1916 SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

12

C1918

C1918 SC1U10V2KX-1GP

SC1U10V2KX-1GP

12

C1920

C1920 SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

12

C1978

C1978 SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

425302_425302_Calpella_S3PowerReduction_WhitePape

+V_DDR_REF

C1907

C1907 SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

+V_DDR_REF

C1910

C1910 SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

12

4

12

C1914

C1914 SC2D2U10V3KX-1GP

SC2D2U10V3KX-1GP

12

C1912

C1912 SC2D2U10V3KX-1GP

SC2D2U10V3KX-1GP

4

12

TC1903

TC1903 ST330U2D5VBM-1-GP

ST330U2D5VBM-1-GP

C1979

C1979 SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

Revision 0.7

3

M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14 M_B_A15

M_B_BS2[10] M_B_BS0[10]

M_B_BS1[10]

M_ODT2[10]

M_ODT3[10]

DDR3_DRAMRST#[9,18]

M_B_BS2 M_B_BS0

M_B_BS1 M_B_DQ0

M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63

M_B_DQS#0 M_B_DQS#1 M_B_DQS#2 M_B_DQS#3 M_B_DQS#4 M_B_DQS#5 M_B_DQS#6 M_B_DQS#7

M_B_DQS0 M_B_DQS1 M_B_DQS2 M_B_DQS3 M_B_DQS4 M_B_DQS5 M_B_DQS6 M_B_DQS7

M_ODT2 M_ODT3

+0.75V_DDR_VTT

3

DM2

98

A0

97

A1

96

A2

95

A3

92

A4

91

A5

90

A6

86

A7

89

A8

85

A9

107

A10/AP

84

A11

83

A12

119

A13

80

A14

78

A15

79

A16/BA2

109

BA0

108

BA1

5

DQ0

7

DQ1

15

DQ2

17

DQ3

4

DQ4

6

DQ5

16

DQ6

18

DQ7

21

DQ8

23

DQ9

33

DQ10

35

DQ11

22

DQ12

24

DQ13

34

DQ14

36

DQ15

39

DQ16

41

DQ17

51

DQ18

53

DQ19

40

DQ20

42

DQ21

50

DQ22

52

DQ23

57

DQ24

59

DQ25

67

DQ26

69

DQ27

56

DQ28

58

DQ29

68

DQ30

70

DQ31

129

DQ32

131

DQ33

141

DQ34

143

DQ35

130

DQ36

132

DQ37

140

DQ38

142

DQ39

147

DQ40

149

DQ41

157

DQ42

159

DQ43

146

DQ44

148

DQ45

158

DQ46

160

DQ47

163

DQ48

165

DQ49

175

DQ50

177

DQ51

164

DQ52

166

DQ53

174

DQ54

176

DQ55

181

DQ56

183

DQ57

191

DQ58

193

DQ59

180

DQ60

182

DQ61

192

DQ62

194

DQ63

10

DQS0#

27

DQS1#

45

DQS2#

62

DQS3#

135

DQS4#

152

DQS5#

169

DQS6#

186

DQS7#

12

DQS0

29

DQS1

47

DQS2

64

DQS3

137

DQS4

154

DQS5

171

DQS6

188

DQS7

116

ODT0

120

ODT1

126

VREF_CA

1

VREF_DQ

30

RESET#

203

VTT1

204

VTT2

DDR3-204P-55-GP

NP1

NP2

110

RAS#

113

WE#

115

CAS#

114

CS0#

121

CS1#

73

CKE0

74

CKE1

101

CK0

103

CK0#

102

CK1

104

CK1#

11

DM0

28

DM1

46

DM2

63

DM3

136

DM4

153

DM5

170

DM6

187

DM7

200

SDA

202

SCL

198

EVENT#

199

VDDSPD

197

SA0

201

SA1

77

NC#1

122

NC#2

125

NC#/TEST

75

VDD1

76

VDD2

81

VDD3

82

VDD4

87

VDD5

88

VDD6

93

VDD7

94

VDD8

99

VDD9

100

VDD10

105

VDD11

106

VDD12

111

VDD13

112

VDD14

117

VDD15

118

VDD16

123

VDD17

124

VDD18

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

2 3 8 9 13 14 19 20 25 26 31 32 37 38 43 44 48 49 54 55 60 61 65 66 71 72 127 128 133 134 138 139 144 145 150 151 155 156 161 162 167 168 172 173 178 179 184 185 189 190 195 196 205 206

Height 9.2mm

Change CONN 2009/06/01 2009/08/04

M_CLK_DDR2 M_CLK_DDR#2

M_CLK_DDR3 M_CLK_DDR#3

M_B_DM0 M_B_DM1 M_B_DM2 M_B_DM3 M_B_DM4 M_B_DM5 M_B_DM6 M_B_DM7

PCH_SMBDATA PCH_SMBCLK

SA0_DM2 SA1_DM2

+1.5V_SUS

62.10017.Q31

2

M_B_RAS# [10]

M_B_WE# [10]

M_B_CAS# [10] M_CS2# [10]

M_CS3# [10]

M_CKE2 [10]

M_CKE3 [10] M_CLK_DDR2 [10]

M_CLK_DDR#2 [10] M_CLK_DDR3 [10]

M_CLK_DDR#3 [10]

PCH_SMBDATA [7,18,23,40,64,65] PCH_SMBCLK [7,18,23,40,64,65]

PM_EXTTS#1 [9]

2

1

+3.3V_RUN

12

DY

12

R1904

R1904 10KR2J-3-GP

10KR2J-3-GP

12

R1902

DY

10KR2J-3-GP

R1903

R1903 10KR2J-3-GP

10KR2J-3-GP

SA1_DM2 SA0_DM2

R1901

R1901 10KR2J-3-GP

10KR2J-3-GP

SMBUS address:A4

+3.3V_RUN

12

C1906

C1906 SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

Title

ize Document Number Rev

Size Document Number Rev

S

Custom

Date: Sheet of

DDRIII-SODIMM SLOT2

Vostro Calpella

DW

07/02 Reserve

1.Added SA1_DM2 pull-down resistor 07/07

2.Reserve pull-hi,lo resistor

12

DY

C1921

C1921 SC2D2U10V3KX-1GP

SC2D2U10V3KX-1GP

Note: If SA0_DIM0 = 0, SA1_DIM0 = 0 SO-DIMMA SPD Address is 0xA0 If SA0_DIM0 = 1, SA1_DIM0 = 0 SO-DIMMA SPD Address is 0xA2 If SA0_DIM0 = 0, SA1_DIM0 = 1 SO-DIMMA SPD Address is 0xA4

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

19 88Wednesday, September 09, 2009

1

SA

5

DW

07/05

1. LCD brightness control are separated by GPU,PCH,EC

2. LCD Power Enable control are separated by GPU,PCH,EC

3. LCD Backlight On/Off Status are separated by GPU,PCH,EC 07/07

4. Dummy R2003

D D

12

R2002

R2002 2K37R2F-GP

2K37R2F-GP

C C

MCH_BLUE[74] MCH_GREEN[74] MCH_RED[74]

R2007

R2007 150R2F-1-GP

150R2F-1-GP

B B

MCH_BLUE MCH_GREEN MCH_RED

R2006

R2006 150R2F-1-GP

150R2F-1-GP

4

PANEL_BKEN_PCH[37] LCDVDD_EN_PCH[54]

LBKLT_CTL_PCH[54] L_DDC_CLK[54]

L_DDC_DATA[54]

+3.3V_RUN

Place near PCH

MCH_LVDSA_CLK#[74] MCH_LVDSA_CLK[74]

MCH_LVDSA_DAT0#[74] MCH_LVDSA_DAT1#[74] MCH_LVDSA_DAT2#[74]

MCH_LVDSA_DAT0[74] MCH_LVDSA_DAT1[74] MCH_LVDSA_DAT2[74]

50 ohm trace to filter

37.5 ohm trace to 150R resistor

R2005

R2005 150R2F-1-GP

150R2F-1-GP

1 2

Place near PCH

RN2001

RN2001 SRN10KJ-5-GP

SRN10KJ-5-GP

TP2001

TP2001 TPAD14-GP

TPAD14-GP

1 2

R2011

R2011 0R2J-2-GP

0R2J-2-GP

1 2

1 2 3

GMCH_DDCCLK[55] GMCH_DDCDATA[55]

GMCH_HSYNC[74] GMCH_VSYNC[74]

R2004

R2004 1KR2D-1-GP

1KR2D-1-GP

LCDVDD_EN_PCH

4

1

CRT_IREF

LCDVDD_EN_PCH

PANEL_BKEN_PCHR

AB48

LCTLA_CLK LCTLB_DATA

LIBG TP_LVDS_VBG

AB46

AP39 AP41

AT43 AT42

AV53 AV51

BB47 BA52 AY48 AV47

BB48 BA50 AY49 AV48

AP48 AP47

AY53

AT49

AU52

AT53

AY51

AT48

AU50

AT51

AA52 AB53 AD53

AD48 AB51

3

1 2

DY

R2003

R2003 100KR2J-1-GP

100KR2J-1-GP

U2001D

T48

L_BKLTEN

T47

L_VDD_EN

Y48

L_BKLTCTL L_DDC_CLK

Y45

L_DDC_DATA L_CTRL_CLK

V48

L_CTRL_DATA LVD_IBG

LVD_VBG LVD_VREFH

LVD_VREFL

LVDSA_CLK# LVDSA_CLK

LVDSA_DATA#0 LVDSA_DATA#1 LVDSA_DATA#2 LVDSA_DATA#3

LVDSA_DATA0 LVDSA_DATA1 LVDSA_DATA2 LVDSA_DATA3

LVDSB_CLK# LVDSB_CLK

LVDSB_DATA#0 LVDSB_DATA#1 LVDSB_DATA#2 LVDSB_DATA#3

LVDSB_DATA0 LVDSB_DATA1 LVDSB_DATA2 LVDSB_DATA3

CRT_BLUE CRT_GREEN CRT_RED

V51

CRT_DDC_CLK

V53

CRT_DDC_DATA

Y53

CRT_HSYNC

Y51

CRT_VSYNC

DAC_IREF CRT_IRTN

IBEXPEAK-M-GP-NF

4 OF 10

DDPB_0N DDPB_0P DDPB_1N DDPB_1P DDPB_2N DDPB_2P DDPB_3N DDPB_3P

DDPC_0N

DDPC_0P

DDPC_1N

DDPC_1P

DDPC_2N

DDPC_2P

DDPC_3N

DDPC_3P

DDPD_0N

DDPD_0P

DDPD_1N

DDPD_1P

DDPD_2N

DDPD_2P

DDPD_3N

DDPD_3P

BJ46 BG46

BJ48 BG48

BF45 BH45

T51 T53

BG44 BJ44 AU38

BD42 BC42 BJ42 BG42 BB40 BA40 AW38 BA38

Y49 AB49

BE44 BD44 AV40

BE40 BD40 BF41 BH41 BD38 BC38 BB36 BA36

U50 U52

BC46 BD46 AT38

BJ40 BG40 BJ38 BG38 BF37 BH37 BE36 BD36

SDVO_TVCLKINN SDVO_TVCLKINP

SDVO_STALLN SDVO_STALLP

SDVO_INTN SDVO_INTP

SDVO_CTRLCLK

SDVO_CTRLDATA

DDPB_AUXN DDPB_AUXP

DDPB_HPD

LVDS

DDPC_CTRLCLK

DDPC_CTRLDATA

DDPC_AUXN

DDPC_AUXP

DDPC_HPD

Digital Display Interface

DDPD_CTRLCLK

DDPD_CTRLDATA

DDPD_AUXN

DDPD_AUXP

DDPD_HPD

CRT

2

HDMI_DATA2-_C HDMI_DATA2+_C HDMI_DATA1-_C HDMI_DATA1+_C HDMI_DATA0-_C HDMI_DATA0+_C HDMI_CLK-_C HDMI_CLK+_C

SDVO_CLK [57] SDVO_DAT [57]

HDMI_HP_DET [21,57]

HDMI_DATA2-_C [57] HDMI_DATA2+_C [57] HDMI_DATA1-_C [57] HDMI_DATA1+_C [57] HDMI_DATA0-_C [57] HDMI_DATA0+_C [57] HDMI_CLK-_C [57] HDMI_CLK+_C [57]

1

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

ize Document Number Rev

Size Document Number Rev

S

Date: Sheet of

PCH (LVDS/CRT/DDI)

Vostro Calpella

20 88Wednesday, September 09, 2009

1

X00

5

RN2101

1 2 1 2 1 2 1 2

RN2101

1 2 3 4 5 6

SRN8K2J-2-GP-U

RN2102

1 2 3 4 5 6

SRN8K2J-2-GP-U

10

PCI_IRDY#

9 8

INT_PIRQC#

7

DGPU_SELECT#

10 9

PCI_DEVSEL#

8

PCI_PLOCK#PCI_PERR#

7

PCI_TRDY#

INT_PIRQE# DGPU_PWM_SELECT# PCH_GPIO5 PCH_GPIO4

+3.3V_RUN

PCI_REQ1# PCI_FRAME# PCI_STOP# INT_PIRQD#

+3.3V_RUN

D D

+3.3V_RUN

C C

INT_PIRQA#

PCI_REQ3# INT_PIRQB# PCI_SERR# PCI_REQ0#

+3.3V_RUN

R2115 10KR2J-3-GPR2115 10KR2J-3-GP R2113 10KR2J-3-GPR2113 10KR2J-3-GP R2116 10KR2J-3-GPR2116 10KR2J-3-GP R2117 10KR2J-3-GPR2117 10KR2J-3-GP

BOOT BIOS Strap

PCI_GNT#1 BOOT BIOS LocationPCI_GNT#0

0 0 LPC 0 1 Reserved

01 11

B B

A16 swap override Strap/Top-Block Swap Override jumper

PCI_GNT#3 Low = A16 swap

A A

PCI_GNT3#

override/Top-Block Swap Override enabled High = Default

R2109

1 2

DY

4K7R2J-2-GP

5

PCI SPI(Default)

4

DW

07/02 Added

1. using the single buffers for 4 device with equivalent capability.

2.Rename PCI_PLTRST#

+3.3V_RUN

C2101

C2101 SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

PLT_RST#[9,37,64,65,70,76,77,80]

DW

07/23 SWAP

1. Swapped the capacitors from signal to power decoupling 08/11

1.Removed U2103 DGPU_SELECT# buffer

12

U2101

5 4

74LVC1G08GW-1-GP

R2104 0R2J-2-GP

DGPU_SELECT#[54,74]

DGPU_PWM_SELECT#[54]

HDD_FALL_INT1[40]

WWAN_RF_EN[65]

HDMI_HP_DET[20,57]

R2110 22R2J-2-GP

PCLK_FWH[70] CLK_PCI_FB[23] PCLK_KBC[37] PCLK_TPM[76]

R2110 22R2J-2-GP R2108 22R2J-2-GPR2108 22R2J-2-GP R2111 22R2J-2-GPR2111 22R2J-2-GP R2112 22R2J-2-GPR2112 22R2J-2-GP

Calpella Platform Design Guide Revision 1.6

VCC Y

GND

1 2

DY

TP2116TPAD14-GPTP2116TPAD14-GP

1 2

DY

1 2 1 2 1 2

B A

R2121

R2121 0R2J-2-GP

0R2J-2-GP

1 2 1 2

Table 111. Overcurrent Pin Example Configuration

These OC7# pins are not used for USB overcurrent protection and should be configured as GPIOs. The unused USB ports can be left as no connect.

4

1

PLTRST#_PCH

2 3

1

DY

R2122

R2122 0R2J-2-GP

0R2J-2-GP

TP2108TPAD14-GP TP2108TPAD14-GP

TP2115TPAD14-GPTP2115TPAD14-GP

INT_PIRQA# INT_PIRQB# INT_PIRQC# INT_PIRQD#

PCI_REQ0# PCI_REQ1#

DGPU_SELECT#

PCI_REQ3# PCI_GNT0#

DGPU_PWM_SELECT#

PCI_GNT3# INT_PIRQE#

WWAN_RF_EN

PCH_GPIO4 PCH_GPIO5

PCIRST#

1

PCI_SERR# PCI_PERR#

PCI_IRDY# PCI_DEVSEL#

PCI_FRAME# PCI_PLOCK# PCI_STOP#

PCI_TRDY# PCH_PME#

1

PLTRST#_PCH PCLK_FWH_R

CLK_PCI_FB_R PCLK_KBC_R PCLK_TPM_R

+3.3V_ALW

3

U2001E

H40

AD0

N34

AD1

C44

AD2

A38

AD3

C36

AD4

J34

AD5

A40

AD6

D45

AD7

E36

AD8

H48

AD9

E40

AD10

C40

AD11

M48

AD12

M45

AD13

F53

AD14

M40

AD15

M43

AD16

J36

AD17

K48

AD18

F40

AD19

C42

AD20

K46

AD21

M51

AD22

J52

AD23

K51

AD24

L34

AD25

F42

AD26

J40

AD27

G46

AD28

F44

AD29

M47

AD30

H36

AD31

J50

C/BE0#

G42

C/BE1#

H47

C/BE2#

G34

C/BE3#

G38

PIRQA#

H51

PIRQB#

B37

PIRQC#

A44

PIRQD#

F51

REQ0#

A46

REQ1#/GPIO50

B45

REQ2#/GPIO52

M53

REQ3#/GPIO54

F48

GNT0#

K45

GNT1#/GPIO51

F36

GNT2#/GPIO53

H53

GNT3#/GPIO55

B41

PIRQE#/GPIO2

K53

PIRQF#/GPIO3

A36

PIRQG#/GPIO4

A48

PIRQH#/GPIO5

K6

PCIRST#

E44

SERR#

E50

PERR#

A42

IRDY#

H44

PAR

F46

DEVSEL#

C46

FRAME#

D49

PLOCK#

D41

STOP#

C48

TRDY#

M7

PME#

D5

PLTRST#

N52

CLKOUT_PCI0

P53

CLKOUT_PCI1

P46

CLKOUT_PCI2

P51

CLKOUT_PCI3

P48

CLKOUT_PCI4

IBEXPEAK-M-GP-NF

USB_OC#10_11

USB_OC#4_5 USB_OC#8_9 USB_OC#12_13

PCI

RP2101

1 2 3 4 5 6

SRN10KJ-L3-GP

NV_CE#0 NV_CE#1 NV_CE#2 NV_CE#3

NV_DQS0 NV_DQS1

NV_DQ0/NV_IO0 NV_DQ1/NV_IO1 NV_DQ2/NV_IO2 NV_DQ3/NV_IO3 NV_DQ4/NV_IO4 NV_DQ5/NV_IO5 NV_DQ6/NV_IO6 NV_DQ7/NV_IO7 NV_DQ8/NV_IO8

NV_DQ9/NV_IO9 NV_DQ10/NV_IO10 NV_DQ11/NV_IO11

NVRAM

NV_DQ12/NV_IO12 NV_DQ13/NV_IO13 NV_DQ14/NV_IO14 NV_DQ15/NV_IO15

NV_RCOMP

NV_WR#0_RE# NV_WR#1_RE#

NV_WE#_CK0 NV_WE#_CK1

USB

USBP10N USBP10P USBP11N USBP11P USBP12N USBP12P USBP13N USBP13P

USBRBIAS#

USBRBIAS

OC0#/GPIO59 OC1#/GPIO40 OC2#/GPIO41 OC3#/GPIO42 OC4#/GPIO43

OC5#/GPIO9 OC6#/GPIO10 OC7#/GPIO14

Page 233

10

USB_OC#2_3

9

PCH_OC7#

8

USB_OC#6_7

7

USB_OC#0_1

5 OF 10

NV_ALE NV_CLE

NV_RB#

USBP0N USBP0P USBP1N USBP1P USBP2N USBP2P USBP3N USBP3P USBP4N USBP4P USBP5N USBP5P USBP6N USBP6P USBP7N USBP7P USBP8N USBP8P USBP9N USBP9P

2

AY9 BD1 AP15 BD8

AV9 BG8

AP7 AP6 AT6 AT9 BB1 AV6 BB3 BA4 BE4 BB6 BD6 BB7 BC8 BJ8 BJ6 BG6

BD3 AY6

AU2 AV7 AY8

AY5 AV11

BF5

H18 J18 A18 C18 N20 P20 J20 L20 F20 G20 A20 C20

TP_USB_PN6

M22

TP_USB_PP6

N22

TP_USB_PN7

B21

TP_USB_PP7

D21 H22 J22 E22 F22 A22 C22 G24 H24 L24 M24 A24 C24

B25 D25

N16 J16 F16 L16 E14 G16 F12 T15

+3.3V_ALW

2

TP_NV_ALE TP_NV_CLE

TP_NV_RCOMP

USB_RBIAS_PN

USB_OC#0_1 USB_OC#2_3 USB_OC#4_5 USB_OC#6_7 USB_OC#8_9 USB_OC#10_11 USB_OC#12_13 PCH_OC7#

1

DW

07/28

1.Removed Braidwood, Update Spec 07/29

1.Moved HW straps on NV_CLE, NV_ALE Connect 07/30

1.Removed R2103

TP2122TP2122 TP2123TP2123

TP2124TP2124

USB_PN0 [76] USB_PP0 [76] USB_PN1 [64] USB_PP1 [64] USB_PN2 [63] USB_PP2 [63] USB_PN3 [63] USB_PP3 [63] USB_PN4 [63] USB_PP4 [63] USB_PN5 [65]

USB_PP5 [65]

TP2118TP2118 TP2119TP2119 TP2120TP2120 TP2121TP2121

USB_PN8 [77]

USB_PP8 [77]

USB_PN9 [76]

USB_PP9 [76]

USB_PN10 [73]

USB_PP10 [73]

USB_PN11 [78]

USB_PP11 [78]

USB_PN12 [77]

USB_PP12 [77]

USB_PN13 [77]

USB_PP13 [77]

1 2

R2106

R2106 22D6R2F-L1-GP

22D6R2F-L1-GP

USB_OC#0_1 [76] USB_OC#2_3 [63] USB_OC#4_5 [63]

DW

07/02 Added

1.Added OC7# commentariat Rename

2.Rename USB Port to depend on Chipset netname

3.PCLK_TPM connected to CLKOUT_PCI3

4.Change R2110,R2111 Value to 22ohm. 07/14 Updated Spec

5.Deleted USB Port-5 07/23

6. Swapped the USB Port for WLAN and Felica 07/28

6. Swapped the USB Port for Felica and WLAN 08/11

1. Removed Felica USB Port,Reserved Test Point.

Title

ize Document Number Rev

Size Document Number Rev

S

Date: Sheet of

PCH (PCI/USB/NVRAM)

Pair

0 1 2 3 4 5 6 7 8 9 10 11 12 13

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Vostro Calpella

USB

Device

USB1 WLAN USB2 USB3 USB for ESATA WWAN

RESERVED

(Not available for HM55)

RESERVED

(Not available for HM55)

BlUETOOTH Touch Panel CAMERA Biometric New Card CardReader

21 88Wednesday, September 09, 2009

1

X00

5

DMI_CTX_PRXN0[8] DMI_CTX_PRXN1[8] DMI_CTX_PRXN2[8] DMI_CTX_PRXN3[8]

DMI_CTX_PRXP0[8]

D D

+1.05V_VTT

C C

AC_PRESENT_EC[37]

B B

XDP_DBRESET#[9]

R2207 0R2J-2-GPR2207 0R2J-2-GP

PM_PWROK[37]

PM_DRAM_PWRGD[9]

RSMRST#_KBC[37] PM_SLP_S4# [37,50,77]

SUS_PWR_DN_ACK[37]

PM_PWRBTN#_R[9]

PM_PWRBTN#[37]

AC_PRESENT_EC

1 2

R2208

1 2

R2209 10KR2J-3-GPR2209 10KR2J-3-GP

1 2

PM_DRAM_PWRGD

1 2

R2213 0R2J-2-GPR2213 0R2J-2-GP

PM_BATLOW#_R

PM_RI#

DMI_CTX_PRXP1[8] DMI_CTX_PRXP2[8] DMI_CTX_PRXP3[8]

DMI_PTX_CRXN0[8] DMI_PTX_CRXN1[8] DMI_PTX_CRXN2[8] DMI_PTX_CRXN3[8]

DMI_PTX_CRXP0[8] DMI_PTX_CRXP1[8] DMI_PTX_CRXP2[8] DMI_PTX_CRXP3[8]

R2204

1 2

49D9R2F-GP

10KR2J-3-GP

R2210

R2210 0R2J-2-GP

0R2J-2-GP

1 2

R2218

R2218 0R2J-2-GP

0R2J-2-GP

1 2

R2216 0R2J-2-GPR2216 0R2J-2-GP

DMI_IRCOMP_R

+3.3V_RUN

12

R2205

R2205 10KR2J-3-GP

10KR2J-3-GP

XDP_DBRESET#

PM_PWRGD

LAN_RST#1

PM_RSMRST#_R

SUS_PWR_ACK

PM_PWRBTN#_R

AC_PRESENT

4

U2001C

BC24

DMI0RXN

BJ22

DMI1RXN

AW20

DMI2RXN

BJ20

DMI3RXN

BD24

DMI0RXP

BG22

DMI1RXP

BA20

DMI2RXP

BG20

DMI3RXP

BE22

DMI0TXN

BF21

DMI1TXN

BD20

DMI2TXN

BE18

DMI3TXN

BD22

DMI0TXP

BH21

DMI1TXP

BC20

DMI2TXP

BD18

DMI3TXP

BH25

DMI_ZCOMP

BF25

DMI_IRCOMP

T6

SYS_RESET#

M6

SYS_PWROK

B17

PWROK

K5

MEPWROK

A10

LAN_RST#

D9

DRAMPWROK

C16

RSMRST#

M1

SUS_PWR_DN_ACK/GPIO30

P5

PWRBTN#

P7

ACPRESENT/GPIO31

A6

BATLOW#/GPIO72

F14

RI#

IBEXPEAK-M-GP-NF

DMI

FDI

DMI

FDI

CLKRUN#/GPIO32

SUS_STAT#/GPIO61

SUSCLK/GPIO62

SLP_S5#/GPIO63

System Power Management

SLP_LAN#/GPIO29

3 OF 10

FDI_RXN0 FDI_RXN1 FDI_RXN2 FDI_RXN3 FDI_RXN4 FDI_RXN5 FDI_RXN6 FDI_RXN7

FDI_RXP0 FDI_RXP1 FDI_RXP2 FDI_RXP3 FDI_RXP4 FDI_RXP5 FDI_RXP6 FDI_RXP7

FDI_INT FDI_FSYNC0 FDI_FSYNC1 FDI_LSYNC0 FDI_LSYNC1

WAKE#

SLP_S4#

SLP_S3#

SLP_M#

TP23

PMSYNCH

3

FDI_TXN0

BA18 BH17 BD16 BJ16 BA16 BE14 BA14 BC12

BB18 BF17 BC16 BG16 AW16 BD14 BB14 BD12

BJ14 BF13 BH13 BJ12 BG14

J12

Y1

FDI_TXN1 FDI_TXN2 FDI_TXN3 FDI_TXN4 FDI_TXN5 FDI_TXN6 FDI_TXN7

FDI_TXP0 FDI_TXP1 FDI_TXP2 FDI_TXP3 FDI_TXP4 FDI_TXP5 FDI_TXP6 FDI_TXP7

PM_CLKRUN#

FDI_TXN0 [8] FDI_TXN1 [8] FDI_TXN2 [8] FDI_TXN3 [8] FDI_TXN4 [8] FDI_TXN5 [8] FDI_TXN6 [8] FDI_TXN7 [8]

FDI_TXP0 [8] FDI_TXP1 [8] FDI_TXP2 [8] FDI_TXP3 [8] FDI_TXP4 [8] FDI_TXP5 [8] FDI_TXP6 [8] FDI_TXP7 [8]

PCIE_WAKE# [76,77]

PM_CLKRUN# [37]

2

FDI_INT [8] FDI_FSYNC0 [8] FDI_FSYNC1 [8] FDI_LSYNC0 [8] FDI_LSYNC1 [8]

1

RN2201

PM_RI# SUS_PWR_ACK

PM_BATLOW#_R PCIE_WAKE#

AC_PRESENT_EC

PM_RSMRST#_R

DW

07/02 Modified

1.Modified PM_RSMRST#_R signal to on pull-down resistor connect

RN2201

4

SRN10KJ-5-GP

1 2

R2201 10KR2J-3-GPR2201 10KR2J-3-GP

1 2

R2202 1KR2J-1-GPR2202 1KR2J-1-GP

1 2

R2217 10KR2J-3-GPR2217 10KR2J-3-GP

R2203

1 2

10KR2J-3-GP

+3.3V_ALW

1 23

0616

TP_SUS_STAT#

P8

F3

E4

H7

P12

K8

N2

BJ10

F6

PCH_SUSCLK

PCH_SLP_S5#

PM_SLP_S4#_R

PM_SLP_S3#_R

SIO_SLP_M#_R

PM_SLP_DSW#

H_PM_SYNC

1

TP2205 TPAD14-GPTP2205 TPAD14-GP

1

TP2202TPAD14-GPTP2202TPAD14-GP

1 2

R2211 0R2J-2-GPR2211 0R2J-2-GP

1 2

R2212 0R2J-2-GPR2212 0R2J-2-GP

1

TP2203TPAD14-GPTP2203TPAD14-GP

1

TP2204TPAD14-GPTP2204TPAD14-GP

1 2

R2219 0R2J-2-GPR2219 0R2J-2-GP

1 2

R2220 0R2J-2-GPR2220 0R2J-2-GP

PM_SLP_S3# [37,42,50,51,77,86]

H_PM_SYNC [9]

PCH_SUSCLK_2102 [39]

PCH_SUSCLK_KBC [37]

+3.3V_RUN

R2214

PM_CLKRUN#

12

R2215

A A

Option to " Disable " clkrun. Pulling it down will keep the clks running.

5

R2215

10KR2J-3-GP

DY

4

R2214

1 2

10KR2J-3-GP

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

ize Document Number Rev

Size Document Number Rev

S

Date: Sheet of

3

2

Date: Sheet of

PCH (DM I/FDI/PM)

Vostro Calpella

22 88Wednesday, September 09, 2009

1

X00

5

D D

PCIE_IRXN2_MTXN2[64]

PCIE_IRXP2_MTXP2[64] PCIE_ITXN2_MRXN2[64] PCIE_ITXP2_MRXP2[64]

PCIE_IRXN3_LTXN3[76] PCIE_IRXP3_LTXP3[76]

PCIE_ITXN3_LRXN3[76] PCIE_ITXP3_LRXP3[76]

PCIE_IRXN4_MTXN4[65]

PCIE_IRXP4_MTXP4[65] PCIE_ITXN4_MRXN4[65] PCIE_ITXP4_MRXP4[65]

PCIE_IRXN5_NTXN5[77]

PCIE_IRXP5_NTXP5[77] PCIE_ITXN5_NRXN5[77] PCIE_ITXP5_NRXP5[77]

C2318 SCD1U16V2KX-3GPC2318 SCD1U16V2KX-3GP

12

C2310 SCD1U16V2KX-3GPC2310 SCD1U16V2KX-3GP

12

C2303 SCD1U16V2KX-3GPC2303 SCD1U16V2KX-3GP

12

C2309 SCD1U16V2KX-3GPC2309 SCD1U16V2KX-3GP

12

C2302 SCD1U16V2KX-3GPC2302 SCD1U16V2KX-3GP

12

C2311 SCD1U16V2KX-3GPC2311 SCD1U16V2KX-3GP

12

C2308 SCD1U16V2KX-3GPC2308 SCD1U16V2KX-3GP

12

C2304 SCD1U16V2KX-3GPC2304 SCD1U16V2KX-3GP

12

PCIE_ITXN2_MRXN2_C PCIE_ITXP2_MRXP2_C

PCIE_ITXN3_LRXN3_C PCIE_ITXP3_LRXP3_C

PCIE_ITXN4_MRXN4_C PCIE_ITXP4_MRXP4_C

PCIE_ITXN5_NRXN5_C PCIE_ITXP5_NRXP5_C

(Not available for HM55)

C C

PCIECLKRQ{0,3,4,5,6,7}# should have a 10K pull-up to +3.3V_ALW. PCIECLKRQ{1,2} should have a 10K pull-up to +3.3_RUN

RN2311

CLK_PCIE_NEW#[77]

CLK_PCIE_NEW[77]

NEWCARD_CLKREQ#[77]

CLK_PCIE_MINI1#[64] CLK_PCIE_MINI1[64]

MINI1_CLKREQ#[64]

CLK_PCIE_LAN#[76] CLK_PCIE_LAN[76]

B B

A A

CLKREQ#_LAN[76]

CLK_PCIE_MINI2#[65]

CLK_PCIE_MINI2[65]

DW

07/02 Added

1.PCIECLKRQ3~4 external weak pull-up resistor on the signal

2.PCIECLKRQ5 pull-down resistor on the signal for always output clk 07/16 Added

1.Added BJT Gate Q2306 ,For prevent electric leakage issue 08/05 Swapped

1.Swapped Q2306 C,E Pin ,For correct.

Q2306

Q2306 MMBT3904-7-F-GP

MMBT3904-7-F-GP

MINI2_CLKREQ_R#[65]

RN2311 SRN0J-6-GP

SRN0J-6-GP

RN2305

RN2305 SRN0J-6-GP

SRN0J-6-GP

RN2304

RN2304 SRN0J-6-GP

SRN0J-6-GP

RN2309

RN2309 SRN0J-6-GP

SRN0J-6-GP

+3.3V_RUN

2

R2309 0R2J-2-GP

5

(Not available for HM55)

1 2 3

2 3 1

+3.3V_ALW

12

R2333

R2333 2K2R2J-2-GP

2K2R2J-2-GP

Q2306_1

1

MINI2_CLKREQ#

3

1 2

DY

CLK_PCIE_NEW1#

4

CLK_PCIE_NEW1 NEWCARD_CLKREQ#

CLK_PCIE_MINI1_1# CLK_PCIE_MINI1_1

4

MINI1_CLKREQ#

CLK_PCIE_LAN1# CLK_PCIE_LAN1

4

CLKREQ#_LAN

CLK_PCIE_MINI2_1# CLK_PCIE_MINI2_1

4

MINI2_CLKREQ#

PCIE_CLK_RQ5#

PEG_B_CLKRQ#

RN2307

8 7 6

SRN10KJ-7GP

CLKREQ#_LAN

1

PEG_B_CLKRQ#

2

PCIE_CLK_RQ5#

3

MINI2_CLKREQ#

45

4

U2001B

BG30

PERN1

BJ30

PERP1

BF29

PETN1

BH29

PETP1

AW30

PERN2

BA30

PERP2

BC30

PETN2

BD30

PETP2

AU30

PERN3

AT30

PERP3

AU32

PETN3

AV32

PETP3

BA32

PERN4

BB32

PERP4

BD32

PETN4

BE32

PETP4

BF33

PERN5

BH33

PERP5

BG32

PETN5

BJ32

PETP5

BA34

PERN6

AW34

PERP6

BC34

PETN6

BD34

PETP6

AT34

PERN7

AU34

PERP7

AU36

PETN7

AV36

PETP7

BG34

PERN8

BJ34

PERP8

BG36

PETN8

BJ36

PETP8

AK48

CLKOUT_PCIE0N

AK47

CLKOUT_PCIE0P

P9

PCIECLKRQ0#/GPIO73

AM43

CLKOUT_PCIE1N

AM45

CLKOUT_PCIE1P

U4

PCIECLKRQ1#/GPIO18

AM47

CLKOUT_PCIE2N

AM48

CLKOUT_PCIE2P

N4

PCIECLKRQ2#/GPIO20

AH42

CLKOUT_PCIE3N

AH41

CLKOUT_PCIE3P

A8

PCIECLKRQ3#/GPIO25

AM51

CLKOUT_PCIE4N

AM53

CLKOUT_PCIE4P

M9

PCIECLKRQ4#/GPIO26

AJ50

CLKOUT_PCIE5N

AJ52

CLKOUT_PCIE5P

H6

PCIECLKRQ5#/GPIO44

AK53

CLKOUT_PEG_B_N

AK51

CLKOUT_PEG_B_P

P13

PEG_B_CLKRQ#/GPIO56

IBEXPEAK-M-GP-NF

+3.3V_RUN

4

WLAN

LAN

WWAN

New Card

1 2 3

RN2308

SRN10KJ-5-GP

SMBus

PCI-E*

Link

Controller

PEG_A_CLKRQ#/GPIO47

PEG

CLKOUT_DP_N/CLKOUT_BCLK1_N

CLKOUT_DP_P/CLKOUT_BCLK1_P

From CLK BUFFER

CLKIN_SATA_N/CKSSCD_N CLKIN_SATA_P/CKSSCD_P

Clock Flex

NEWCARD_CLKREQ#

4

MINI1_CLKREQ#

2 OF 10

SMBALERT#/GPIO11

SMBCLK

SMBDATA

SML0ALERT#/GPIO60

SML0CLK

SML0DATA

SML1ALERT#/GPIO74

SML1CLK/GPIO58

SML1DATA/GPIO75

CL_CLK1

CL_DATA1

CL_RST1#

CLKOUT_PEG_A_N CLKOUT_PEG_A_P

CLKOUT_DMI_N CLKOUT_DMI_P

CLKIN_DMI_N CLKIN_DMI_P

CLKIN_BCLK_N CLKIN_BCLK_P

CLKIN_DOT_96N CLKIN_DOT_96P

REFCLK14IN

CLKIN_PCILOOPBACK

XTAL25_IN

XTAL25_OUT

XCLK_RCOMP

CLKOUTFLEX0/GPIO64

CLKOUTFLEX1/GPIO65

CLKOUTFLEX2/GPIO66

CLKOUTFLEX3/GPIO67

+3.3V_RUN

B9 H14 C8

J14 C6 G8

M14 E10 G12

T13 T11 T9

H1

AD43 AD45

AN4 AN2

AT1 AT3

AW24 BA24

AP3 AP1

F18 E18

AH13 AH12

P41

J42

AH51 AH53

AF38

T45

P43

T42

N50

3

1 2

3

SMBALERT# PCH_SMB_CLK PCH_SMB_DATA

SML0ALERT# SML0_CLK SML0_DATA

SML1ALERT# SML1CLK SML1DAT

CL_CLK

1

CL_DATA

1

CL_RST#

1

PEG_CLKREQ#

CLK_PCIE_VGA1# CLK_PCIE_VGA1

CLK_EXP_N CLK_EXP_P

CLK_DP_N CLK_DP_P

CLKIN_DMI# CLKIN_DMI

CLK_CPU_BCLK# CLK_CPU_BCLK

DREFCLK# DREFCLK

CLK_PCIE_SATA# CLK_PCIE_SATA

CLK_PCH_14M

CLK_PCI_FB

XTAL25_IN XTAL25_OUT

XCLK_RCOMP

TP_CLK_OUTFLEX0

TP_CLK_PCI_LPC

EDID_SELECT_R#

CLK48M/EDID_SEL

EDID_SELECT_R#

R2314

R2314 10KR2J-3-GP

10KR2J-3-GP

R2301

R2301 10KR2J-3-GP

10KR2J-3-GP

12

+3.3V_ALW

PCH_SMB_CLK [77] PCH_SMB_DATA [77]

R2302

12

10KR2J-3-GP

R2303

10KR2J-3-GP

TP2301TPAD14-GPTP2301TPAD14-GP TP2302TPAD14-GPTP2302TPAD14-GP TP2303TPAD14-GPTP2303TPAD14-GP

RN2327

RN2327 SRN0J-6-GP

SRN0J-6-GP

R2306 90D9R2F-1-GPR2306 90D9R2F-1-GP

1

EDID_SELECT#[54,55,57]

+3.3V_ALW

SML0_CLK [9] SML0_DATA [9]

12

+3.3V_ALW

SML1CLK [37] SML1DAT [37]

+3.3V_ALW

1

DIS

2 3

CLK_EXP_N [9] CLK_EXP_P [9]

CLK_DP_N [9] CLK_DP_P [9]

CLKIN_DMI# [7] CLKIN_DMI [7]

CLK_CPU_BCLK# [7] CLK_CPU_BCLK [7]

DREFCLK# [7] DREFCLK [7]

CLK_PCIE_SATA# [7] CLK_PCIE_SATA [7]

CLK_PCH_14M [7]

CLK_PCI_FB [21]

1 2

TP2307

TP2307 TPAD14-GP

TPAD14-GP TP2305

TP2305 TPAD14-GP

TPAD14-GP

R2307 33R2J-2-GPR2307 33R2J-2-GP

1 2

+3.3V_RUN

12

R2304

R2304 10KR2J-3-GP

10KR2J-3-GP

4

12

DY

C2312

C2312 SC220P50V2KX-3GP

SC220P50V2KX-3GP

2

DW

07/29

1.Changed RN2313 from 4.7k to 2.2k ohm

PEG_CLKREQ# [80]

CLK_PCIE_VGA# [80] CLK_PCIE_VGA [80]

DGPU_PGOOD[25,86,87]

+1.05V_VTT

CLK_PCH_48M [77]

U2302

5

VCC

4

Y

74LVC1G08GW-1-GP

R2305 0R2J-2-GP

GND

1 2

DY

1

B

2

A

3

2

1

23

RN2313

RN2313 SRN2K2J-1-GP

SRN2K2J-1-GP

4

SML0_CLK

SML0_DATA

+3.3V_RUN

PCH_SMB_DATA

PCH_SMB_CLK

G

DIS

6 5

S D

SML1CLK SML1DAT

Q2301

Q2301 DMN66D0LDW-7-GP

DMN66D0LDW-7-GP

PEG_CLKREQ#

Q2305

Q2305 2N7002A-7-GP

2N7002A-7-GP

Display Clock Integration

C2313

Normal

0R2J-2-GP SC18Pdale DCI

XTAL25_IN

R2380

R2380 1MR2J-1-GP

1MR2J-1-GP

XTAL25_OUT

X2301

X2301 XTAL-25MHZ-67GP

XTAL-25MHZ-67GP

EDID_SELECT_R#

Title

PCH (PCI-E/SMBUS/CLOCK/CL)

ize Document Number Rev

Size Document Number Rev

S

Date: Sheet of

1

+3.3V_ALW

1

23

RN2306

RN2306 SRN2K2J-1-GP

SRN2K2J-1-GP

4

PCH_SMB_CLK PCH_SMB_DATA

1 2 34

PCH_SMBDATA [7,18,19,40,64,65]

PCH_SMBCLK [7,18,19,40,64,65]

C2307 X2301 R2380 DY DY DY

DY

SC18P

12

DY

25MHZ 1MR

C2313

C2313 0R2J-2-GP

0R2J-2-GP

1 2

12

DY

C2307

C2307 SC18P50V2JN-1-GP

SC18P50V2JN-1-GP

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Vostro Calpella

1

+3.3V_ALW+3.3V_ALW

+3.3V_RUN

PCH_SMBDATA PCH_SMBCLK

CLK_PCH_14M

DY

CLK_PCH_14M_RC

1 2

DY

1 2

12

23 88Wednesday, September 09, 2009

1

23

RN2302

RN2302 SRN2K2J-1-GP

SRN2K2J-1-GP

4

1

23

RN2303

RN2303 SRN2K2J-1-GP

SRN2K2J-1-GP

4

R2350

R2350 0R2J-2-GP

0R2J-2-GP

C2324

C2324 SC4D7P50V2CN-1GP

SC4D7P50V2CN-1GP

X00

5

4

3

2

1

PCH_RTCX1

1 2

R2401

R2401 10MR2J-L-GP

10MR2J-L-GP

X2401

1

C2402

C2402 SC18P50V2JN-1-GP

SC18P50V2JN-1-GP

D D

12

X-32D768KHZ-38GPU

DW

07/23 Added

1.Added "ME in Manufacturing Mode" strap

2.Added CardReader_Wake# to sent Card detect signal for PCH . ( Only For JMB380 ) 07/30

1.Changed R2403 tolerance from 5% to 1%.

Flash Descriptor Security Override/ ME Debug Mode

ME_UNLOCK#

C C

1 2

DY

R2419 1KR2J-1-GP

+3.3V_RUN

NO REBOOT STRAP

1 2

DY

R2410 1KR2J-1-GP

1 2

R2411 10KR2J-3-GPR2411 10KR2J-3-GP

4

2 3

This strap should only be asserted low via external pull down in manufacturing/debug environments ONLY.

SB_SPKR

INT_SERIRQ

PCH_RTCX2

C2403

C2403 SC18P50V2JN-1-GP

SC18P50V2JN-1-GP

12

ME_UNLOCK_R#

No Reboot Strap R23

HDA_SPKR

Low = Default High = No Reboot

+RTC_CELL

R2402

R2402 20KR2J-L2-GP

20KR2J-L2-GP

1 2

C2401

C2401 SC1U6D3V3KX-2GP

SC1U6D3V3KX-2GP

R2403

R2403 20KR2F-L-GP

20KR2F-L-GP

1 2

C2404

C2404 SC1U6D3V3KX-2GP

SC1U6D3V3KX-2GP

INTVRMEN- Integrated SUS

12

21

12

G2401

G2401 GAP-OPEN

GAP-OPEN

+RTC_CELL

PCH_AZ_CODEC_BITCLK[77] PCH_AZ_CODEC_SYNC[77]

SB_SPKR[77]

PCH_AZ_CODEC_RST#[77]

PCH_SDIN_CODEC[77]

PCH_SDOUT_CODEC[77]

ME_UNLOCK#[37]

1.1V VRM Enable High - Enable internal VRs

1 2

R2406 1MR2J-1-GPR2406 1MR2J-1-GP

1 2

R2404 330KR2F-L-GPR2404 330KR2F-L-GP

1 2 1 2

1 2

R2417 0R2J-2-GPR2417 0R2J-2-GP

1 2

33R2J-2-GPR2405 33R2J-2-GPR2405 33R2J-2-GPR2407 33R2J-2-GPR2407

33R2J-2-GPR2408 33R2J-2-GPR2408

33R2J-2-GPR2409 33R2J-2-GPR2409

TP2404TP2404 TP2405TP2405 TP2406TP2406 TP2407TP2407 TP2408TP2408

PCH_RTCX1 PCH_RTCX2

PCH_RTCRST# SRTCRST# SM_INTRUDER# PCH_INTVRMEN

ACZ_BIT_CLK ACZ_SYNC_R

ACZ_RST#_R

ACZ_SDATAOUT_R

ME_UNLOCK_R#

PCH_JTAG_TCK

1

PCH_JTAG_TMS

1

PCH_JTAG_TDI

1

PCH_JTAG_TDO

1

PCH_JTAG_RST#

1

U2001A

B13

RTCX1

D13

RTCX2

C14

RTCRST#

D17

SRTCRST#

A16

INTRUDER#

A14

INTVRMEN

A30

HDA_BCLK

D29

HDA_SYNC

P1

SPKR

C30

HDA_RST#

G30

HDA_SDIN0

F30

HDA_SDIN1

E32

HDA_SDIN2

F32

HDA_SDIN3

B29

HDA_SDO

H32

HDA_DOCK_EN#/GPIO33

J30

HDA_DOCK_RST#/GPIO13

M3

JTAG_TCK

K3

JTAG_TMS

K1

JTAG_TDI

J2

JTAG_TDO

J4

TRST#

RTCIHDA

FWH4/LFRAME#

LDRQ1#/GPIO23

LPC

SATA

SATAICOMPO

1 OF 10

FWH0/LAD0 FWH1/LAD1 FWH2/LAD2 FWH3/LAD3

LDRQ0#

SERIRQ

SATA0RXN SATA0RXP SATA0TXN SATA0TXP

SATA1RXN SATA1RXP SATA1TXN SATA1TXP

SATA2RXN SATA2RXP SATA2TXN SATA2TXP

SATA3RXN SATA3RXP SATA3TXN SATA3TXP

SATA4RXN SATA4RXP SATA4TXN SATA4TXP

SATA5RXN SATA5RXP SATA5TXN SATA5TXP

SATAICOMPI

LPC_LAD0

D33

LPC_LAD1

B33

LPC_LAD2

C32

LPC_LAD3

A32 C34 A34

F34 AB9

AK7 AK6

SATA_ITXN0_HRXN0_C

AK11

SATA_ITXP0_HRXP0_C

AK9

AH6 AH5

SATA_ITXN1_ORXN1_C

AH9

SATA_ITXP1_ORXP1_C

AH8 AF11

AF9 AF7 AF6

AH3 AH1 AF3 AF1

AD9 AD8

ESATA_TXN4_C

AD6

ESATA_TXP4_C

AD5 AD3

AD1 AB3 AB1

AF16

SATAICOMP

AF15

LPC_LAD[0..3]

LPC_LFRAME# [37,70,76]

INT_SERIRQ [37,76]

LPC_LAD[0..3] [37,70,76]

C2405 SCD01U50V2KX-1GPC2405 SCD01U50V2KX-1GP

1 2

C2406 SCD01U50V2KX-1GPC2406 SCD01U50V2KX-1GP

1 2

C2407 SCD01U50V2KX-1GPC2407 SCD01U50V2KX-1GP

1 2

C2408 SCD01U50V2KX-1GPC2408 SCD01U50V2KX-1GP

1 2

(Not available for HM55)

C2410 SCD01U50V2KX-1GPC2410 SCD01U50V2KX-1GP

1 2

C2411 SCD01U50V2KX-1GPC2411 SCD01U50V2KX-1GP

1 2

DW

07/28

1. Swapped the ESATA Port form Port-5 to Port-4

2. Added SATA Port2 and Port3 TestPoint 07/30

1.Removed TestPoint on SATA2 and SATA3

R2412 37D4R2F-GPR2412 37D4R2F-GP

1 2

+1.05V_VTT

SATA_IRXN0_HTXN0_C [59] SATA_IRXP0_HTXP0_C [59] SATA_ITXN0_HRXN0 [59] SATA_ITXP0_HRXP0 [59]

SATA_IRXN1_OTXN1_C [59] SATA_IRXP1_OTXP1_C [59] SATA_ITXN1_ORXN1 [59] SATA_ITXP1_ORXP1 [59]

HDD

ODD

ESATA

ESATA_IRX_DTX_N4_C [63]

ESATA_IRX_DTX_P4_C [63]

ESATA_ITX_DRX_N4 [63] ESATA_ITX_DRX_P4 [63]

R2413 15R2J-GPR2413 15R2J-GP

DW

B B

07/02 Change

1.Change R2410 to dummy 08/18

1.Removed PCH_GPIO13 not in use

PCH_AZ_CODEC_BITCLK

12

DY

EC2429

SCD1U25V2ZY-1GP

PCH_SPI_CLK[62] PCH_SPI_CS0#[62]

PCH_SPI_DO[62]

PCH_SPI_DI[62]

1 2

R2414 15R2J-GPR2414 15R2J-GP

1 2

R2415 15R2J-GPR2415 15R2J-GP

1 2

EMI Request

A A

5

4

SPI_CLK_R SPI_CS#0_R

SPI_MOSI_R

3

BA2

SPI_CLK

AV3

SPI_CS0#

AY3

SPI_CS1#

AY1

SPI_MOSI

AV1

SPI_MISO

IBEXPEAK-M-GP-NF

SPI JTAG

SATALED#

SATA0GP/GPIO21 SATA1GP/GPIO19

T3

GPO_DSM

Y9

PCH_GPIO19

V1

DW

07/10 assign GPIO

1.assign GPIO GPIO_DSM,Felic_DETECT# 08/05 STUFF

1.R2416 made STUFF ,For Lan chip connecter senser Pin. 08/11

1.Removed FELICA_DETECT# GPIO Pin ,Update Spec

Title

Size Document Number Rev

Date: Sheet of

2

Date: Sheet of

SATA_LED# [66]

GPO_DSM [76]

PCH (SPI/RTC/LPC/SATA/IHDA)

R2418

R2418 10KR2J-3-GP

1

10KR2J-3-GP

1 2

R2416

R2416 10KR2J-3-GP

10KR2J-3-GP

1 2

24 88Wednesday, September 09, 2009

PCH_GPIO19

GPO_DSM

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Vostro Calpella

+3.3V_RUN

X00

5

+3.3V_RUN_GPU +3.3V_RUN

R2552

R2552 10KR2J-3-GP

10KR2J-3-GP

DEEPIDLE_WAKE_INT_R#[81]

D D

VTT_PWRGD[9,37,49,50] DGPU_PGOOD[23,86,87]

LCD_CBL_DET#[54]

DW

07/02 Change

1.Change CLK_SATA_OE# to pull-down

DW

07/08 Del

1. Not reserve PCH_GPIO12

2. Not reserve PCH_GPIO24

3. Not reserve PCH_GPIO39 Pull-down resister

C C

4. Not reserve PCH_GPIO22 de-coupling Cap 07/23 Rename

1.Changed net-name S_GPIO to PCH_GPIO0

DW

07/10 Added

1.Changed PCH GPIO DDR_RST_GATE from GPIO57 to GPIO46 , Bason on design guide 07/23 Added

1.Added Finger Printer Detect Pin, control by PCH

2.Change KB_DET signal from EC to PCH control

3.Change LCD_CBL_DET signal from EC to PCH control

DDR_RST_GATE ECSMI#

B B

A A

PCH_GPIO27

ECSCI#

DGPU_PWR_EN# DGPU_PWROK

FFS_INT2_R KB_DET_R# ECSWI#

STP_PCI# BIO_DET# PCH_GPIO38 LCD_CBL_DET_R#

PCH_GPIO28 PCH_GPIO57 PCH_GPIO15 PCIECLKRQ6#

R2526 10KR2J-3-GP

R2512 10KR2J-3-GPR2512 10KR2J-3-GP

R2529 10KR2J-3-GPR2529 10KR2J-3-GP R2507 10KR2J-3-GPR2507 10KR2J-3-GP

R2517 10KR2J-3-GP

R2517 10KR2J-3-GP R2518 10KR2J-3-GPR2518 10KR2J-3-GP R2519 10KR2J-3-GPR2519 10KR2J-3-GP

R2521 10KR2J-3-GPR2521 10KR2J-3-GP R2522 10KR2J-3-GPR2522 10KR2J-3-GP R2523 10KR2J-3-GPR2523 10KR2J-3-GP R2524 10KR2J-3-GPR2524 10KR2J-3-GP

R2530 10KR2J-3-GPR2530 10KR2J-3-GP R2531 10KR2J-3-GPR2531 10KR2J-3-GP R2532 1KR2J-1-GPR2532 1KR2J-1-GP R2533 10KR2J-3-GPR2533 10KR2J-3-GP

5

DIS

1 2

C2501

C2501 SC47P50V2JN-3GP

SC47P50V2JN-3GP

RN2512

1 2 3

SRN10KJ-5-GP

DY

1 2

DY

1 2 1 2

1 2 1 2 1 2 1 2

+3.3V_RUN_GPU

12

R2555

DIS

2K2R2J-2-GP

Q2515_1

1

Q2515

Q2515 MMBT3904-7-F-GP

MMBT3904-7-F-GP

3

2

DIS

ECSWI#[37]

R2505

R2505 0R2J-2-GP

0R2J-2-GP

1 2

DY

R2525

R2525 10KR2J-3-GP

10KR2J-3-GP

1 2

+3.3V_ALW

4

12

+3.3V_RUN

+3.3V_ALW

12

R2503

R2503 10KR2J-3-GP

10KR2J-3-GP

12

DY

DGPU_HOLD_RST#[80]

R2506 0R2J-2-GPR2506 0R2J-2-GP

1 2

R3749 100R2J-2-GPR3749 100R2J-2-GP

1 2

PCH_GPIO35

DGPU_PWR_EN#[37]

R2548 100R2J-2-GPR2548 100R2J-2-GP

KB_DET#[68]

DDR_RST_GATE[9]

TURBO_BOOST_ALERT#[37]

+3.3V_RUN

DW

07/23

1.Combine GPIO pull-up and pull-down resistors from single to series resistor 07/27

2.Changed GPIO pull-up and pull-down resistors from series to single resistor. 08/12

1.Changed R2528 pull-lo resistor value from 100k to 10k ohm.

1 2

FFS_INT2_R[40]

ECSCI#[37] BIO_DET#[78]

ECSMI#[37]

TP2508TPAD14-GP TP2508TPAD14-GP

1 2

TP2510TPAD14-GP TP2510TPAD14-GP

TP2511TPAD14-GP TP2511TPAD14-GP TP2512TPAD14-GP TP2512TPAD14-GP

TP2509TPAD14-GP TP2509TPAD14-GP

4

R2508

R2508 0R2J-2-GP

0R2J-2-GP

1

1 1

1

4

DEEPIDLE_WAKE_INT#

ECSCI# BIO_DET# ECSWI# ECSMI#

PCH_GPIO15 DGPU_HOLD_RST#

DGPU_PWROK LCD_CBL_DET_R#

PCH_GPIO27 PCH_GPIO28

1

STP_PCI#

DGPU_PWR_EN# DGPU_PRSNT# PCH_GPIO38 KB_DET_R# PCIECLKRQ6# DDR_RST_GATE FFS_INT2_R T_B_ALERT_R# PCH_GPIO57

PCH_NCTF_1

PCH_NCTF_2 PCH_NCTF_3

PCH_NCTF_4

Y3 C38 D37

J32

F10

K9

AA2 F38

Y7 H10

AB12

V13 M11

V6 AB7

AB13

V3

P3

H3

AB6 AA4

A4 A49

A5 A50 A52 A53

B2

B4 B52 B53 BE1

BE53

BF1

BF53

BH1 BH2

BH52 BH53

BJ1 BJ2 BJ4

BJ49

BJ5

BJ50 BJ52 BJ53

D1

D2 D53

E1 E53

DGPU_PRSNT#

U2001F

BMBUSY#/GPIO0 TACH1/GPIO1 TACH2/GPIO6 TACH3/GPIO7 GPIO8 LAN_PHY_PWR_CTRL/GPIO12

T7

GPIO15 SATA4GP/GPIO16 TACH0/GPIO17 SCLOCK/GPIO22 GPIO24 GPIO27 GPIO28 STP_PCI#/GPIO34 SATACLKREQ#/GPIO35 SATA2GP/GPIO36 SATA3GP/GPIO37 SLOAD/GPIO38 SDATAOUT0/GPIO39 PCIECLKRQ6#/GPIO45

F1

PCIECLKRQ7#/GPIO46 SDATAOUT1/GPIO48 SATA5GP/GPIO49

F8

GPIO57

VSS_NCTF_1 VSS_NCTF_2 VSS_NCTF_3 VSS_NCTF_4 VSS_NCTF_5 VSS_NCTF_6 VSS_NCTF_7 VSS_NCTF_8 VSS_NCTF_9 VSS_NCTF_10 VSS_NCTF_11 VSS_NCTF_12 VSS_NCTF_13 VSS_NCTF_14 VSS_NCTF_15 VSS_NCTF_16 VSS_NCTF_17 VSS_NCTF_18 VSS_NCTF_19 VSS_NCTF_20 VSS_NCTF_21 VSS_NCTF_22 VSS_NCTF_23 VSS_NCTF_24 VSS_NCTF_25 VSS_NCTF_26 VSS_NCTF_27 VSS_NCTF_28 VSS_NCTF_29 VSS_NCTF_30 VSS_NCTF_31

IBEXPEAK-M-GP-NF

+3.3V_RUN

12

R2527

DY

10KR2J-3-GP

12

R2528

R2528 10KR2J-3-GP

10KR2J-3-GP

MISC

GPIO

CPU

NCTF

RSVD

DGPU_HOLD_RST#

3

6 OF 10

CLKOUT_PCIE6N

CLKOUT_PCIE6P

CLKOUT_PCIE7N

CLKOUT_PCIE7P

A20GATE

CLKOUT_BCLK0_N/CLKOUT_PCIE8N CLKOUT_BCLK0_P/CLKOUT_PCIE8P

PECI

RCIN#

PROCPWRGD

THRMTRIP#

TP1 TP2 TP3 TP4 TP5 TP6 TP7 TP8

TP9 TP10 TP11 TP12 TP13 TP14 TP15 TP16 TP17 TP18 TP19

NC_1 NC_2 NC_3 NC_4 NC_5

INIT3_3V#

TP24

+3.3V_RUN

R2516

DY

10KR2J-3-GP

1 2 12

R2534

R2534 10KR2J-3-GP

10KR2J-3-GP

3

AH45 AH46

AF48 AF47

U2

AM3 AM1 BG10 T1 BE10 BD10

BA22 AW22 BB22 AY45 AY46 AV43 AV45 AF13 M18 N18 AJ24 AK41 AK42 M32 N32 M30 N30 H12 AA23 AB45 AB38 AB42 AB41 T39

P6 C10

INIT3_3V#

2

KA20GATE [37]

BCLK_CPU_N [9] BCLK_CPU_P [9]

H_PECI [9]

H_PWRGOOD [9,42]

PCH_THERMTRIP_R

TP2506TPAD14-GPTP2506TPAD14-GP

1

2

1

+1.05V_VTT

R2509

R2509 56R2J-4-GP

KBRCIN# [37]

1 2

R2511

56R2J-4-GP

Placed Within 2" from PCH

Title

ize Document Number Rev

Size Document Number Rev

S

Date: Sheet of

56R2J-4-GP

1 2

H_THRMTRIP# [9,37,42]

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

PCH (GPIO/CPU)

Vostro Calpella

1

X00

25 88Wednesday, September 09, 2009

X00

5

4

3

2

1

+1.05V_VTT

1.432A

C2601

SC10U10V5ZY-1GP

D D

+1.05V_VTT

40mA

+1.05V_VTT

C C

+1.05V_VTT

B B

1 2

DY

L2602

L2602 IND-1UH-2-GP

IND-1UH-2-GP

3.062A

+1.05V_VTT

+1.05VS_VCCAPLL_FDI

DY

SC10U10V5ZY-1GP

1 2

DY

L2601

L2601 IND-1UH-2-GP

IND-1UH-2-GP

12

C2608

SC10U6D3V5MX-3GP

12

C2616

C2616 SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

12

C2609

SC1U10V3KX-3GP

SCD1U10V2KX-4GP

12

+1.8V_RUN

C2610

SC1U10V3KX-3GP

12

C2614

12

C2602

C2602 SC1U10V2KX-1GP

SC1U10V2KX-1GP

+1.05V_VTT

+1.05VS_VCCAPLL_EXP

12

C2606

C2606 SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

DY

12

C2611

R2606

SC1U10V3KX-3GP

12

C2612

SC1U10V3KX-3GP

+3.3V_RUN

357mA

+VCC_VRM

12

0R2J-2-GP

+VCC_VRM

U2001G

AB24 AB26 AB28 AD26 AD28

AF26 AF28 AF30

AF31 AH26 AH28 AH30 AH31

AJ30

AJ31

AK24

BJ24

AN20 AN22 AN23 AN24 AN26 AN28

BJ26

BJ28 AT26 AT28 AU26 AU28 AV26 AV28

AW26 AW28

BA26 BA28 BB26 BB28 BC26 BC28 BD26 BD28 BE26 BE28

BG26 BG28

BH27 AN30

AN31

AN35

AT22

BJ18

AM23

IBEXPEAK-M-GP-NF

VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE

VCCIO

VCCAPLLEXP

VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO

VCCIO VCCIO

VCC3_3

VCCVRM[1] VCCFDIPLL VCCIO

1.432A

3.062A

POWER

VCC CORE

DMI

PCI E*

156mA

NAND / SPI

FDI

CRTLVDS

<1mA

59mA

HVCMOS

85mA

VCCTX_LVDS VCCTX_LVDS VCCTX_LVDS VCCTX_LVDS

357mA

7 OF 10

VCCADAC

VCCADAC VSSA_DAC VSSA_DAC

VCCALVDS

VSSA_LVDS

VCC3_3 VCC3_3 VCC3_3

VCCVRM

VCCDMI VCCDMI

VCCPNAND VCCPNAND VCCPNAND VCCPNAND VCCPNAND VCCPNAND VCCPNAND VCCPNAND VCCPNAND

VCCME3_3 VCCME3_3 VCCME3_3 VCCME3_3

L2603

+VCCA_DAC_1_2

AE50 AE52 AF53 AF51

+3VS_VCCA_LVD +3.3V_RUN

AH38 AH39

AP43 AP45 AT46 AT45

AB34 AB35 AD35

AT24

AT16 AU16

AM16 AK16 AK20 AK19 AK15 AK13 AM12 AM13 AM15

AM8 AM9 AP11 AP9

SCD1U10V2KX-5GP

SCD01U16V2KX-3GP

12

C2625

12

35mA

12

C2604

SCD01U16V2KX-3GP

C2623

1 2

DY

+1.8VS_VCCTX_LVDS

SCD01U16V2KX-3GP

12

C2624

357mA

C2607

C2607 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

+VCC_VRM

12

C2613

C2613 SC1U10V3KX-3GP

SC1U10V3KX-3GP

156mA

C2615

C2615 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

85mA

PCH_VCCME3_3

C2622

C2622 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

12

C2605

DY

12

C2603

SCD1U10V2KX-5GP

SC10U6D3V5MX-3GP

12

C2626

C2626 SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

+3.3V_RUN

R2601

1 2

0R2J-2-GP

+3.3V_RUN

12

R2605

R2605 0R2J-2-GP

0R2J-2-GP

L2603

1 2

BLM18PG181SN1D-GP

1 2

L2604

L2604 IND-D1UH-21-GP

IND-D1UH-21-GP

SC10U6D3V5MX-3GP

12

R2609 0R3J-0-U-GPR2609 0R3J-0-U-GP

58mA

<1mA

59mA

C2628

+1.05V_VTT+1.05VS_VCC_DMI

+3.3V_RUN

+3.3V_CRT_LDO

+1.8V_RUN

12

DY

07/28

1.Added Line power +1.8V_RUN_PCH for PCH 07/29

1.Changed +V_NVRAM_VCCQ_PCH power rail from 1.8V to 3.3V

1.Changed VCCVRM[1] power rail from 1.8V_RUN to 1.8V_PCH

69mA

R2602

1 2

0R2J-2-GP

U2601

5

OUT

GND

DY

4

SHDN#

NC#4

MAX8511EXK33-T-GP

DW

IN

1 2 3

+3.3V_RUN

+5V_RUN+3.3V_CRT_LDO

C2629

SC1U10V3KX-3GP

DY

12

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Date: Sheet of

Date: Sheet

PCH (POWER1)

Vostro Calpella

1

of

26 88Wednesday, September 09, 2009

X00

5

+1.05V_VTT +1.05VS_VCCA_CLK

52mA

D D

DW

07/23

1. Added 0-Ohms resistors for GND on processor balls AF23 and AF24

L2701

1 2

IND-10UH-30-GP

+1.05V_VTT

DY

R2708

1 2

0R2J-2-GP

1.849A

C2705

SC10U6D3V5MX-3GP

L2702

+1.05V_VTT

C C

B B

L2702 IND-10UH-203-GP

IND-10UH-203-GP

1 2

SC10U6D3V5MX-3GP

1 2

L2703

L2703 IND-10UH-203-GP

IND-10UH-203-GP

SC10U6D3V5MX-3GP

+1.05VS_VCCA_A_DPL

+1.05VS_VCCA_B_DPL

12

C2734

DY

12

DY

C2735

SC1U10V2KX-1GP

C2726

C2726 SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

+1.05V_VTT

+3.3V_ALW

SC10U6D3V5MX-3GP

12

C2711

C2711 SC1U10V2KX-1GP

SC1U10V2KX-1GP

12

C2714

C2714 SC1U10V2KX-1GP

SC1U10V2KX-1GP

+1.05V_VTT

C2718

C2723

SCD1U10V2KX-4GP

163mA

12

<1mA

SC4D7U6D3V5KX-3GP

A A

+RTC_CELL

C2705

C2704

SCD1U10V2KX-4GP

68mA 69mA

12

SC1U10V2KX-1GP

12

C2728

C2719

SCD1U10V2KX-4GP

2mA

5

4

SC10U6D3V5MX-3GP

12

C2701

DY

PCH_VCC_LAN

C2707

SCD1U10V2KX-4GP

12

C2713

C2707

C2708

SC1U10V2KX-1GP

12

+VCC_VRM

+1.05VS_VCCA_A_DPL

+1.05VS_VCCA_B_DPL

12

SC1U10V2KX-1GP

+VCCSST

+1.05VALW_INT_VCCSUS

12

C2724

C2724 SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

+3.3V_RUN

C2727

SCD1U10V2KX-4GP

12

C2729

SCD1U10V2KX-4GP

12

C2732

4

SC1U10V2KX-1GP

12

DY

DCPSUSBYP

12

C2710

DY

+VCCRTCEXT

C2720

12

C2730

12

C2733

C2702

12

U2001J

AP51

VCCACLK

AP53

VCCACLK

AF23

VCCLAN

AF24

VCCLAN

Y20

DCPSUSBYP

AD38

VCCME

AD39

VCCME

AD41

VCCME

AF43

VCCME

AF41

VCCME

AF42

VCCME

V39

VCCME

V41

VCCME

V42

VCCME

Y39

VCCME

Y41

VCCME

Y42

VCCME

V9

DCPRTC

AU24

VCCVRM

BB51

VCCADPLLA

BB53

VCCADPLLA

BD51

VCCADPLLB

BD53

VCCADPLLB

AH23

VCCIO

AJ35

VCCIO

AH35

VCCIO

AF34

VCCIO

AH34

VCCIO

AF32

VCCIO

V12

DCPSST

Y22

DCPSUS

P18

VCCSUS3_3

U19

VCCSUS3_3

U20

VCCSUS3_3

U22

VCCSUS3_3

V15

VCC3_3

V16

VCC3_3

Y16

VCC3_3

AT18

V_CPU_IO

AU18

V_CPU_IO

A12

VCCRTC

IBEXPEAK-M-GP-NF

3

10 OF 10

POWER

10 OF 10

52mA

USB

163mA

<1mA

VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3

VCCSUS3_3

V5REF_SUS

320mA

1.849A

<1mA

68mA

Clock and Miscellaneous

69mA

PCI/GPIO/LPC

VCCSATAPLL VCCSATAPLL

196mA

SATA

PCI/GPIO/LPC

<1mA

CPU

2mA

RTC

6mA

HDA

VCCSUSHDA

3

VCCIO VCCIO VCCIO VCCIO

VCCIO

V5REF

VCC3_3

VCCIO

VCCVRM

VCCIO VCCIO VCCIO VCCIO

VCCIO VCCIO VCCIO

VCCIO VCCIO VCCIO VCCIO

VCCME

V24 V26 Y24 Y26

V28 U28 U26 U24 P28 P26 N28 N26 M28 M26 L28 L26 J28 J26 H28 H26 G28 G26 F28 F26 E28 E26 C28 C26 B27 A28 A26

U23 V23

+5VALW_PCH_VCC5REFSUS

F24

+5VS_PCH_VCC5REF

K49

J38 L38 M36 N36 P36 U35

AD13

AK3 AK1

SC1U10V2KX-1GP

AH22

AT20

AH19 AD20 AF22 AD19

AF20 AF19 AH20

AB19 AB20 AB22 AD22

AA34 Y34 Y35 AA35

6mA

L30

+3VS_+1.5VS_HDA_IO

+3.3V_ALW

12

+3.3V_RUN

12

C2721

DY

+VCC_VRM

12

C2731

C2731 SC1U10V2KX-1GP

SC1U10V2KX-1GP

12

C2706

C2706 SC1U10V2KX-1GP

SC1U10V2KX-1GP

12

C2703

C2703 SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

C2709

C2709 SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

+1.05V_VTT

C2716

C2716 SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

12

C2722

C2722 SC1U10V2KX-1GP

SC1U10V2KX-1GP

DY

1 2

R2707 0R2J-2-GPR2707 0R2J-2-GP

2

+3.3V_ALW

21

12

+3.3V_RUN

+1.05V_VTT

2

D2701

D2701 CH751H-40PT-GP

CH751H-40PT-GP

1 2

R2701

R2701 100R2J-2-GP

100R2J-2-GP

C2712

C2712 SC1U10V2KX-1GP

SC1U10V2KX-1GP

12

C2717

C2717 SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

L2704

1 2

DY

IND-10UH-30-GP

+3.3V_ALW

1

+1.05V_VTT

+3.3V_ALW

DW

07/10 Change resistor Value

1.R2701,R2702 value corrected to 100 Ohms following PDG doc

+5V_ALW

+3.3V_RUN

21

D2702

D2702 CH751H-40PT-GP

CH751H-40PT-GP

1 2

R2702

12

+1.05V_VTT+1.05VS_VCCAPLL

R2702 100R2J-2-GP

100R2J-2-GP

C2715

C2715 SC1U10V2KX-1GP

SC1U10V2KX-1GP

31mA

+1.05V_VTT

12

C2725

C2725 SC1U10V2KX-1GP

SC1U10V2KX-1GP

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

PCH (POWER2)

Size Document Number Rev

Date: Sheet of

PCH (POWER2)

Vostro Calpella

1

27 88Wednesday, September 09, 2009

+5V_RUN

X00

Dell VOSTRO 3500 Schematics

Specifications and Main Features

Frequently Asked Questions

User Manual