DELL V3700 Schematics

5

D D

4

3

2

1

DW70 CALPELLA N11P-GE1 Schematics

uFCPGA Mobile Arrandale/Clarksfield

Intel Ibex Peak-M

C C

2009-09-03

REV : SA

B B

DY : Nopop Component UMA : Pop when schematic is UMA DIS : Pop when schematic is DIS

A A

5

ARD : Pop when schematic is Arrandale CFD : Pop when schematic is Clarksfield

4

3

2

UMA

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Custom

Date: Sheet of

Vostro Calpella

Taipei Hsien 221, Taiwan, R.O.C.

Cover Page

1

1 90Thursday, September 03, 2009

SA

5

Winery CALPELLA Block Diagram

PCB LAYER

L1: Top L2: VCC L3: Signal

D D

C C

B B

A A

L4: Signal L5: GND L6: Bottom

VRAM(gDDR3)

64Mbx16x8 (1GB)

HDMI

CRT

2CH SPEAKER

84,85,89,90

LCD

1394 Connector

(8 in 1)SD/MMC MS/MS Pro/xD

(On I/O board)

Digital Mic Array (Option)

HP OUT

4

HDMI

57

RGB CRT

55

LVDS

54

MIC IN

(On Audio board)

5

Clock Generator

SLG8SP585

Nvidia

VRAM

N11P-GE1(40nm)

HDMI

Switchable

CardReader 1394

RICOH R5U230

HD AUDIO CODEC

OP AMP

IDT 92HD81-UA

80,81,82,83

LVDS

(Dual Channel)

RGB CRT

4

7

100MHz/

2.5Gbps

Bandwidth :8GB

RGB CRT

LVDS

PCIE

100MHz

2.5Gbps

HD AUDIO

4

PCIe x 16

RGB CRT

LVDS

HDMI

USB,ESATA Multi-Port x1

Intel CPU

Arrandale Clarksfield

8,9,10,11,12,13,14

DMIx4 FDI

Intel

PCH

14 USB 2.0/1.1 ports

ETHERNET (10/100/1000Mb)

High Definition Audio

SATA ports (6) PCIE ports (8)

LPC I/F ACPI 1.1

PCI/PCI BRIDGE

20,21,22,23,24,25,26,27,28

SATA,USB

SATA

ODD HDD

63

Flash ROM

4MB

59

SPI

3

DDRIII Channel A

Arrandale 800/1066MHz Clarksfield 1066/1333MHz

DDRIII Channel B

Arrandale 800/1066MHz Clarksfield 1066/1333MHz

PCIE

100MHz 2

.5Gbps

USB 2.0

480Mbps

SM Bus

400KHz

LPC Bus

33MHz

SPI

Flash ROM

256kB

3

NUVOTON

NPCE781BA0DX

Touch PAD

62 68

2

Project code : 91.4RU01.001 Part Number : 48.4RU06.0SA PCB P/N : 09290 Revision : SA

18

DM1

19

DM2

(On LAN board)

USB 2.0 x 1

USB 2.0 x 2

USB 2.0 x 1

Thermal & Fan

EMC2102

Capacity Board

2

RJ45 CONN

Power SW

TPS2231R

New Card

(On I/O board)

39,58

UMA

Title

Size Document Number Rev

Custom

Date: Sheet of

PCIE x 1

KBC

68

DDRIII Arrandale 1066MHz Clarksfield 1333MHz

10/100/1000LOM

RTL8111DL

PCIE x 1

Free fall sensor

TPM CONN

DEBUG BOARD GOLDEN FINGER

SM Bus

37

Int. KB

USB 2.0 x 1

40

76

70

Mini-Card

802.11a/b/g/n

Touch Panel

(On LAN board)

Left Side: USB x 2

Right Side: USB x 2 (On LAN board)

CAMERA (Option)

Bluetooth

(On Audio board)

Biometric

Vostro Calpella

1

CPU DC/DC

ISL62883

INPUTS

+PWR_SRC

SYSTEM DC/DC

TPS51125

INPUTS

+PWR_SRC

SYSTEM DC/DC

TPS51116

+PWR_SRC

SYSTEM DC/DC

ADP3211

+PWR_SRC +CPU_GFXCORE

SYSTEM DC/DC

TPS51218

INPUTS

+PWR_SRC

CHARGER

BQ24745

INPUTS

+DC_IN +PBATT

64

SYSTEM DC/DC

TPS51218

+PWR_SRC

63

SYSTEM DC/DC

TPS51117

+PWR_SRC

73

APL5930

INPUTS

78

RT9025

INPUTS

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Block Diagram

1

OUTPUTS

+VCC_CORE

OUTPUTS

+15V_ALW +3.3V_RTC_LDO +5V_ALW +3.3V_ALW

OUTPUTSINPUTS

+1.5V_SUS +0.75V_DDR_VTT +V_DDR_REF

OUTPUTSINPUTS

OUTPUTS

+VCC_GFX_CORE

OUTPUTS

+PWR_SRC

OUTPUTSINPUTS

+1.05V_VTT

OUTPUTSINPUTS

+1.05V_PCH

LDO

OUTPUTS

+1.8V_RUN+3.3V_ALW

LDO

OUTPUTS

+1.8V_RUN_GPU+3.3V_ALW

2 90Tuesday, September 08, 2009

47,48

46

50

53

86

45

49

52

51

87

SA

5

4

3

2

1

D D

Adapter

AO4407A

45

Battery

C C

+5V_ALW2

+3.3V_RTC_LDO

+15V_ALW

B B

+PWR_SRC

ISL62883

ADP3211

47、48 86

Charger

BQ24745

+PBATT

45

TPS51125

+VCC_CORE

46

+CPU_GFXCORE

+5V_ALW

TPS2062AD

Daughter BD 6342

+5V_USB0

AO4468

+5V_RUN

TPS2062AD

+5V_USB1

TPS2062AD

+5V_USB2

For USB Port1,4 For USB Port2,3 For ESATA

TPS51218

53

+VCC_GFX_CORE

For NVIDIA GPUFor Intel GPU

TPS51218DSCR

+1.05V_VTT

Arrandale : 1.05V Clarksfield:1.1V

49

TPS51117RGYR-GP

52

+1.05V_PCH

FDS8880

87

For Clarksfield

+1.05V_GFX_PCIE

+3.3V_ALW

63

AO3403

Daughter BD

TPS2231R

Daughter BD

+3.3V_LAN

FDS8880

+3.3V_RUN+3.3V_CARDAUX

APL5930

42

+1.8V_RUN

51

+1.8V_RUN_GPU

TPS51116RGER-GP-U

P2703

42

+1.5V_CPU

RT9025

87

+V_DDR_REF

FDS8880

+1.5V_RUN_GPU

FDS8880

+3.3V_RUN_GPU

50

+1.5V_SUS

AO4468

87

42

+1.5V_RUN

TPS2231R

87

Daughter BD

+1.5V_CARD

RTL8111DL

DVDD12

35

SI3456BDV

+LCDVDD

TPS2231R

54

Daughter BD

+3.3V_CARD

Power Shape

Regulator LDO Switch

A A

5

4

3

2

UMA

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Power Block Diagram

Size Document Number Rev

Custom

Date: Sheet of

Power Block Diagram

Vostro Calpella

Taipei Hsien 221, Taiwan, R.O.C.

3 90Tuesday, September 08, 2009

1

SA

A

PCH SMBus Block Diagram

+3.3V_ALW

‧

SRN2K2J-1-GP

PCH

SMBCLK (H14)

PCH_SMB_CLK

1 1

SMBDATA (C8)

23

PCH_SMB_DATA

‧

2N7002SPT

+3.3V_RUN

‧

+3.3V_RUN

‧

SRN2K2J-1-GP

PCH_SMBCLK PCH_SMBDATA

DIMM 1

SCL (202) SDA (200)

SMBus Address:A0

DIMM 2

SCL (202) SDA (200)

SMBus Address:A2

SMB_CLK SMB_DATA

Express Card

SMB_CLK SMB_DATA

‧

76

‧

PCH_SMBCLK PCH_SMBDATA

Clock Generator

SCL (32) SDA (31)

SMBus address:D2

2 2

‧

PCH_SMBCLK PCH_SMBDATA

Minicard WLAN

SMB_CLK SMB_DATA

Free fall sensor

PCH_SMBCLK

SCL/SPC (14)

PCH_SMBDATA

SDA/SDI/SDO (13)

B

18

19

64

40

NPCE781

07

C

KBC SMBus Block Diagram

+5V_RUN

‧

SRN10KJ-5-GP

TPDATA

PSDAT1 PSCLK1

TPCLK

KBC_PWR

‧

TPDATA TPCLK

‧

SRN4K7J-8-GP

Battery Conn.

CLK_SMB DAT_SMB

BQ24745

BAT_SCL

SCL

B

AT_SDA

SDA

+3.3V_RUN

‧

KBC

SCL1 SDA1

GPIO73/SCL2 GPIO74/SDA2

BAT_SCL BAT_SDA

‧

KBC_PWR

‧

SRN100J-3-GP

‧

PBAT_SMBCLK1 PBAT_SMBDAT1

‧

SRN4K7J-8-GP

KBC_SCL1

‧

KBC_SDA1

‧

37

2N7002DW-1-GP

D

TouchPad Conn.

TPDATA TPCLK

SMBus address:16

44

SMBus address:12

45

+3.3V_RUN

‧

SRN4K7J-8-GP

THERM_SCL

‧

THERM_SDA

‧

THERM_SCL THERM_SDA

68

Thermal

SMCLK SMDATA

Capacity Board

(On daughter board)

SCL SDA

E

SMBus address:7A

39

SMBus address:0A

3 3

+3.3V_RUN_GPU

VGA SMBus Block Diagram

LDDC_CLK

I2CC_SCL

LDDC_DATA

I2CC_SDA

CRT_CLK_DDC

I2CA_SCL

CRT_DAT_DDC

VGA

I2CA_SDA

N11P-GE1

4 4

IFPC_AUX_I2CW_SCL

IFPC_AUX_I2CW_SDA#

A

B

HDMI_SCLK_DDC HDMI_SDATA_DDC

81

‧

+3.3V_RUN_GPU

‧

+3.3V_RUN

‧

SRN2K2J-1-GP

NC7SB3157P6X

C

‧

NC7SB3157P6X

DDC_CLK_CON2 DDC_DATA_CON2

HDMI_SCLK_CON_L HDMI_SDATA_CON_L

SRN2K2J-1-GP

LDDC_CLK_CON LDDC_DATA_CON

2N7002DW-1-GP

+3.3V_RUN

‧

LCD Conn.

+3.3V_RUN

‧

+5V_RUN

D

‧

SRN2K2J-1-GP

HDMI_SCLK_CON

‧

HDMI_SDATA_CON

‧

+5V_CRT_RUN

‧

SRN2K2J-1-GP

‧

54

DDC_CLK_CON DDC_DATA_CON

CRT CONN

HDMI

57

55

UMA

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd ., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd ., Hsichih, Taipei Hsie n 221, Taiwan, R.O .C.

Taipei Hsie n 221, Taiwan, R.O .C.

Title

Size Document Num ber Rev

A2

Date: Sheet of

Taipei Hsie n 221, Taiwan, R.O .C.

SMBUS Block Diagram

Vostro Calpella

E

4 90Tuesday, Septem ber 08, 2009

SA

A

B

C

D

E

Thermal Block Diagram

1 1

DP1

EMC2102_DN1

2 2

DN1

EMC2102_DP1

SC470P50V3JN-2GP

Thermal EMC2102

DP2

VGA_THERMDA

SC470P50V3JN-2GP

DN2

VGA_THERMDC

3 3

DPLUS

DMINUS

GPU

Q3905 MMBT3904-3-GP

System

54

DIS

Q3904 MMBT3904-3-GP

Audio Block Diagram

SPKR_PORT_D_L+ SPKR_PORT_D_LSPKR_PORT_D_RSPKR_PORT_D_R+

HP1_PORT_B_L HP1_PORT_B_R

Codec

92HD81-UA

HP0_PORT_A_L HP0_PORT_A_R VREFOUT_A_OR_F

AUD_SPK_L1 AUD_SPK_L2 AUD_SPK_R2 AUD_SPK_R1

AUD_HP1_JACK_L AUD_HP1_JACK_R

AUD_EXT_MIC_L AUD_EXT_MIC_R AUD_VREFOUT_B

0R3-0-U-GP

0R3-0-U-V-GP

AUD_SPK_L1_R AUD_SPK_L2_R AUD_SPK_R2_R AUD_SPK_R1_R

SPEAKER

44

HP

OUT

50

MIC

IN

50

UMA

DP3

DN3

CPU_THERMDA

CPU_THERMDC

SC470P50V3JN-2GP

Q3901 MMBT3904-3-GP

HW T8 sensor

DMIC_CLK/GPIO1

DMIC0/GPIO2

AUD_DMIC_CLK

AUD_DMIC_IN0

33R2J-2-GP

33R2J-2-GP AUD_DMIC_IN0_R

AUD_DMIC_CLK_G_R

Digital MIC Array

47

28

22

CPU Sockt

4 4

A

B

C

D

UMA

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Thermal/Audio Block Diagram

Size Document Number Rev

Custom

Date: Sheet of

Vostro Calpella

Taipei Hsien 221, Taiwan, R.O.C.

5 90Tuesday, September 08, 2009

E

SA

PCH Strapping

A

Calpella Schematic Checklist Rev.1_6

Name Schematics Notes

SPKR

INIT3_3V# Internal pull-up. Leave as "No Connect"

4 4

GNT3#/ GPIO55

INTVRMEN

GNT0#, GNT1#

GNT2#/ GPIO53

SPI_MOSI

3 3

NV_ALE

NC_CLE DMI termination voltage. Weak internal pull-up. Do not pull low.

HAD_DOCK_EN# /GPIO[33]

2 2

HDA_SDO Weak internal pull-down. Do not pull high.

HDA_SYNC

GPIO15

GPIO8

1 1

GPIO27

Reboot option at power-up

Internal weak Pull-down.

Default Mode:

Connect to Vcc3_3 with 8.2-kΩ

No Reboot Mode with TCO Disabled:

- 10-kΩ weak pull-up resistor.

Internal pull-up.

Default Mode: Low (0) = Top Block Swap Mode

Note: Connect to ground with 4.7-kΩ weak pull-down resistor. C

RB uses a 1 kΩ; do not stuff resistor.

High (1) = Integrated VRM is enabled Low (0) = Integrated VRM is disabled Note:

CRB uses a 330-kΩ resistor.

Leave both GNT0# and GNT1# floating. No pull up

Default (SPI):

required. Connect GNT1# to ground with 1-kΩ pull-down

Boot from PCI:

esistor. Leave GNT0# Floating.

r Connect both GNT0# and GNT1# to ground with 1-kΩ

Boot from LPC:

pull-down resistor.

Default - Internal pull-up.

= Configures DMI for ESI compatible operation (for servers

Low (0)

only. Not for mobile/desktops).

Connect to Vcc3_3

E

nable Intel Anti-Theft Technology:

with 8.2-kΩ weak pull-up resistor. Left floating, no pull-down

Disable Intel Anti-Theft Technology:

required.

Connect to +NVRAM_Vccq with

Enable Intel Anti-Theft Technology:

8.2-kΩ weak pull-up resistor.[CRB has it pulled up with 1-kΩ no-stuff resistor] Leave floating.

Disable Intel Anti-Theft Technology:

(internal pull-down)

Flash Descriptor Security will be overridden. Also, when

Low (0)-

this signals is sampled on the rising edge of PWROK then it will also disable Intel ME and its features. Security measure defined in the Flash Descriptor

High (1)-:

will be enabled.

Platform design should provide appropriate pull-up or pull-down depending on the desired settings. If a jumper option is used to tie this signal to GND as required by the functional strap, the signal should be pulled low through a weak pull-down in order to avoid asserting HDA_DOCK_EN# inadvertently. CRB recommends 1-kΩ pull-down for FD Override.

Note:

There is an internal pull-up of 20 kΩ for HDA_DOCK_EN# which is only enabled at boot/reset for strapping functions.

Sampled at rising edge of RSMRST#.

Weak internal pull-down. Do not pull high. Sampled at rising edge of RSMRST#.

Intel ME Crypto Transport Layer Security (TLS) cipher suite

Low (0)-

with no confidentiality Intel ME Crypto Transport Layer Security (TLS) cipher suite

High (1)-:

with confidentiality

Note:

This is an unmuxed signal. This signal has a weak internal pull-down of 20 KΩ which is enabled

hen PWROK is low.

w Sampled at rising edge of RSMRST#. CRB has a 1-kΩ pull-up on this signal to +3.3VA rail.

Weak internal pull-up. Do not pull low. Sampled at rising edge of RSMRST#.

Default = Do not connect (floating). Internal pull-up.

High(1) = Enables the internal VccVRM to have a clean supply for analog rails. No need to use on-board filter circuit. Low (0) = Disables the VccVRM. Need to use on-board filter circuits for analog rails.

B

C

Processor Strapping

Pin Name Strap Description Configuration (Default value for each bit is

CFG[4] Disabled - No Physical Display Port attached to

CFG[3]

CFG[0]

DisplayPort Presence

PCI-Express Static Lane Reversal

PCI-Express Configuration Select

1 unless specified otherwise)

1:Embedded

Embedded DisplayPort. Enabled - An external Display Port device is

0:

connected to the Embedded Display Port. Normal Operation.

1:

Lane Numbers Reversed 15 -> 0, 14 -> 1, ...

0:

Single PCI-Express Graphics

1:

Bifurcation enabled

0:

D

Calpella Schematic Checklist Rev.1_6

E

Default Value

1

PCIE Routing

LANE1 LANE2 LANE3 LAN

Card reader MiniCard WLAN

NCLANE4 New CardLANE5

USB Table

Pair

0 1 2 3 4 5 6 7 8 9 10 11 12 13

USB

Device

USB1 > LAN BOARD USB4 > LAN BOARD USB2 > M/B USB3 > M/B USB for ESATA

RESERVED RESERVED

(Not available for HM55)

RESERVED

(Not available for HM55)

BlUETOOTH Touch Panel Biometric CAMERA New Card WLAN

UMA

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Custom

Date: Sheet of

Vostro Calpella

Taipei Hsien 221, Taiwan, R.O.C.

Table of Content

6 90Tuesday, September 08, 2009

SA

5

D D

4

3

2

1

+3.3V_RUN +3.3V_RUN_SL585

DY

C C

DREFCLK#23

DREFCLK23

CLKIN_DMI#23

CLKIN_DMI23

CLK_PCIE_SATA#23 CLK_PCH_14M 23

CLK_PCIE_SATA23

CLK_CPU_BCLK#23

CLK_CPU_BCLK23

B B

68.00119.131 0603

68.00084.521 0805

R708 0R3J-0-U-GPR708 0R3J-0-U-GP

1 2

C701

SC1U10V2KX-1GPDYC701

SC1U10V2KX-1GP

12

C702

12

DY

RN701

RN701 SRN0J-6-GP

SRN0J-6-GP RN702

RN702 SRN0J-6-GP

SRN0J-6-GP RN703

RN703 SRN0J-6-GP

SRN0J-6-GP RN704

RN704 SRN0J-6-GP

SRN0J-6-GP

SC10U10V5ZY-1GPDYC702

SC10U10V5ZY-1GP

2 3 1

1 2 3

TP0701Do Not Stuff TP0701Do Not Stuff TP702Do Not Stuff TP702Do Not Stuff

C703

SCD1U10V2KX-4GP

C703

SCD1U10V2KX-4GP

12

SCD1U10V2KX-4GP

12

CLK_MCH_DREFCLK1# CLK_MCH_DREFCLK1

4

CLK_IN_DMI# CLK_IN_DMI

4

CLK_PCIE_SATA1# CLK_PCIE_SATA1

4

CLK_CPU_BCLK1#

4

CLK_CPU_BCLK1 TP_CPU_1#

1

TP_CPU_1

1

C705

12

C704

SCD1U10V2KX-4GP

C704

1st Silego 71.08585.003 2nd ICS 71.93197.003

C707

SCD1U10V2KX-4GP

C707

SCD1U10V2KX-4GP

12

U701

4

DOT_96#

3

DOT_96

14

SRC_2#

13

SRC_2

11

SRC_1/SATA#

10

SRC_1/SATA

22

CPU_0#

23

CPU_0

19

CPU_1#

20

CPU_1

SLG8SP585VTR-GP

+1.05V_PCH

C708

SCD1U10V2KX-4GP

C708

SCD1U10V2KX-4GP

12

68.00119.131

R709 0R3J-0-U-GPR709 0R3J-0-U-GP

1 2

C709

SC1U10V2KX-1GPDYC709

SC1U10V2KX-1GP

12

DY

+3.3V_RUN_SL585 +1.05V_RUN_SL585_IO

29

15

18

5

1

17

24

VDD_27

VDD_REF

VDD_DOT

VDD_SRC

VDD_CPU

VSS_CPU

VSS_REF

GND

21

26

33

VDD_SRC_IO

VDD_CPU_IO

27MHZ

27MHZ_SS

CPU_STOP#

CKPWRGD/PD#

REF_0/CPU_SEL

XTAL_IN

XTAL_OUT

VSS_DOT

VSS_278VSS_SATA

VSS_SRC

2

9

12

+1.05V_PCH

SDA SCL

6 7

16 25 30

28 27

31 32

12

C710

SC10U10V5ZY-1GP

C710

SC10U10V5ZY-1GP

12

CLK_27M CLK_27M_SS

CPU_STOP# CK_PWRGD FSC

CLK_XTAL_IN CLK_XTAL_OUT

PCH_SMBDATA 18,19,23,40,64 PCH_SMBCLK 18,19,23,40,64

X701

1 2

X-14D31818M-37GP

X-14D31818M-37GP C714

C714 SC12P50V2JN-3GP

SC12P50V2JN-3GP

+1.05V_RUN_SL585_IO

C711

SCD1U10V2KX-4GP

C711

SCD1U10V2KX-4GP

C712

SCD1U10V2KX-4GP

C712

12

SCD1U10V2KX-4GP

12

VGA 27M SS

DY Mount

NON-SS Mount DY

R706 33R2J-2-GP

R706 33R2J-2-GP R710 33R2J-2-GP

R710 33R2J-2-GP

R701 2K2R2J-2-GPR701 2K2R2J-2-GP R703 33R2J-2-GPR703 33R2J-2-GP

12

DY

12

DY

12 12

CLK_XTAL_IN

CLK_XTAL_OUT

12

C715

C715 SC12P50V2JN-3GP

SC12P50V2JN-3GP

R710R706

+3.3V_RUN

12

EC701

DY

SC4D7P50V2CN-1GP

CLK_VGA_27M 81

+3.3V_RUN_SL585

R705

R705 10KR2J-3-GP

10KR2J-3-GP

CLK_VGA_27M

R749

DY

0R2J-2-GP

CLK_VGA_27M_RC

1 2

2009/07/28 Change 2N7002 ESD pretect from standard to 1KV type P/N:84.2N702.E31

CK_PWRGD

2009/07/15 Added R,C For CLK_VGA_27M EMI

G

2N7002A-7-GP

2N7002A-7-GP Q701

Q701

VR_CLKEN# 47

SD

R704

R704 4K7R2J-2-GP

4K7R2J-2-GP

R707

R707 10KR2J-3-GP

10KR2J-3-GP

A A

5

4

DY

1 2

FSC

1 2

3

FSC 0 1

SPEED

133MHz

(Default)

100MHz

C718

DY

SC4D7P50V2CN-1GP

1 2

UMA

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Clock Generator SLG8SP585

ize Document Number Rev

Size Document Number Rev

S

Date: Sheet of

2

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

Vostro Calpella

7 90Tuesday, September 08, 2009

1

SA

5

4

3

2

1

D D

1 OF 9

CPU1A

DMI_PTX_CRXN022 DMI_PTX_CRXN122 DMI_PTX_CRXN222 DMI_PTX_CRXN322

DMI_PTX_CRXP022 DMI_PTX_CRXP122 DMI_PTX_CRXP222 DMI_PTX_CRXP322

DMI_CTX_PRXN022 DMI_CTX_PRXN122 DMI_CTX_PRXN222 DMI_CTX_PRXN322

DMI_CTX_PRXP022 DMI_CTX_PRXP122 DMI_CTX_PRXP222 DMI_CTX_PRXP322

C C

B B

Calpella Platform Design Guide Revision 1.6

2.4 Arrandale Graphics Disable Guideline

FDI_FSYNC022 FDI_FSYNC122

FDI_INT22 FDI_LSYNC022

FDI_LSYNC122

Page 89

FDI_TXN022 FDI_TXN122 FDI_TXN222 FDI_TXN322 FDI_TXN422 FDI_TXN522 FDI_TXN622 FDI_TXN722

FDI_TXP022 FDI_TXP122 FDI_TXP222 FDI_TXP322 FDI_TXP422 FDI_TXP522 FDI_TXP622 FDI_TXP722

FDI_TXN0 FDI_TXN1 FDI_TXN2 FDI_TXN3 FDI_TXN4 FDI_TXN5 FDI_TXN6 FDI_TXN7

FDI_TXP0 FDI_TXP1 FDI_TXP2 FDI_TXP3 FDI_TXP4 FDI_TXP5 FDI_TXP6 FDI_TXP7

It applies to Arrandale and Clarksfield discrete graphic designs.

FDI_TX[7:0] and FDI_TX#[7:0] can be left floating on the Arrandale. The GFX_IMON, FDI_FSYNC[0], FDI_FSYNC[1], FDI_LSYNC[0], FDI_LSYNC[1], and FDI_INT signals on the Arrandale side should be tied to GND (through 1-kΩ ±5% resistors).

A24 C23 B22 A21

B24 D23 B23 A22

D24 G24 F23 H23

D25 F24 E23 G23

E22 D21 D19 D18 G21 E19 F21 G18

D22 C21 D20 C18 G22 E20 F20 G19

F17 E17

C17 F18

D17

DMI_RX#0 DMI_RX#1 DMI_RX#2 DMI_RX#3

DMI_RX0 DMI_RX1 DMI_RX2 DMI_RX3

DMI_TX#0 DMI_TX#1 DMI_TX#2 DMI_TX#3

DMI_TX0 DMI_TX1 DMI_TX2 DMI_TX3

FDI_TX#0 FDI_TX#1 FDI_TX#2 FDI_TX#3 FDI_TX#4 FDI_TX#5 FDI_TX#6 FDI_TX#7

FDI_TX0 FDI_TX1 FDI_TX2 FDI_TX3 FDI_TX4 FDI_TX5 FDI_TX6 FDI_TX7

FDI_FSYNC0 FDI_FSYNC1

FDI_INT FDI_LSYNC0

FDI_LSYNC1

DMI

CLARKSFIELD

PCI EXPRESS -- GRAPHICS

1 OF 9

PEG_RX#0 PEG_RX#1 PEG_RX#2 PEG_RX#3 PEG_RX#4 PEG_RX#5 PEG_RX#6 PEG_RX#7 PEG_RX#8 PEG_RX#9

PEG_RX0 PEG_RX1 PEG_RX2 PEG_RX3 PEG_RX4 PEG_RX5 PEG_RX6 PEG_RX7 PEG_RX8

PEG_RX9 PEG_RX10 PEG_RX11 PEG_RX12 PEG_RX13 PEG_RX14 PEG_RX15

PEG_TX#0 PEG_TX#1 PEG_TX#2 PEG_TX#3 PEG_TX#4 PEG_TX#5 PEG_TX#6 PEG_TX#7 PEG_TX#8 PEG_TX#9

PEG_TX0

PEG_TX1

PEG_TX2

PEG_TX3

PEG_TX4

PEG_TX5

PEG_TX6

PEG_TX7

PEG_TX8

PEG_TX9 PEG_TX10 PEG_TX11 PEG_TX12 PEG_TX13 PEG_TX14 PEG_TX15

B26 A26 B27 A25

K35 J34 J33 G35 G32 F34 F31 D35 E33 C33 D32 B32 C31 B28 B30 A31

J35 H34 H33 F35 G33 E34 F32 D34 F33 B33 D31 A32 C30 A28 B29 A30

L33 M35 M33 M30 L31 K32 M29 J31 K29 H30 H29 F29 E28 D29 D27 C26

L34 M34 M32 L30 M31 K31 M28 H31 K28 G30 G29 F28 E27 D28 C27 C25

PEG_ICOMPI

PEG_ICOMPO

PEG_RCOMPO

PEG_RBIAS

DMI

PEG_RX#10 PEG_RX#11 PEG_RX#12 PEG_RX#13 PEG_RX#14 PEG_RX#15

Intel(R) FDI

PEG_TX#10 PEG_TX#11 PEG_TX#12 PEG_TX#13 PEG_TX#14 PEG_TX#15

PEG_IRCOMP_R

EXP_RBIAS

PCIE_MRX_GTX_N15 PCIE_MRX_GTX_N14 PCIE_MRX_GTX_N13 PCIE_MRX_GTX_N12 PCIE_MRX_GTX_N11 PCIE_MRX_GTX_N10 PCIE_MRX_GTX_N9 PCIE_MRX_GTX_N8 PCIE_MRX_GTX_N7 PCIE_MRX_GTX_N6 PCIE_MRX_GTX_N5 PCIE_MRX_GTX_N4 PCIE_MRX_GTX_N3 PCIE_MRX_GTX_N2 PCIE_MRX_GTX_N1 PCIE_MRX_GTX_N0

PCIE_MRX_GTX_P15 PCIE_MRX_GTX_P14 PCIE_MRX_GTX_P13 PCIE_MRX_GTX_P12 PCIE_MRX_GTX_P11 PCIE_MRX_GTX_P10 PCIE_MRX_GTX_P9 PCIE_MRX_GTX_P8 PCIE_MRX_GTX_P7 PCIE_MRX_GTX_P6 PCIE_MRX_GTX_P5 PCIE_MRX_GTX_P4 PCIE_MRX_GTX_P3 PCIE_MRX_GTX_P2 PCIE_MRX_GTX_P1 PCIE_MRX_GTX_P0

PCIE_MTX_GRX_C_N15 PCIE_MTX_GRX_C_N14 PCIE_MTX_GRX_C_N13 PCIE_MTX_GRX_C_N12 PCIE_MTX_GRX_C_N11 PCIE_MTX_GRX_C_N10 PCIE_MTX_GRX_C_N9 PCIE_MTX_GRX_C_N8 PCIE_MTX_GRX_C_N7 PCIE_MTX_GRX_C_N6 PCIE_MTX_GRX_C_N5 PCIE_MTX_GRX_C_N4 PCIE_MTX_GRX_C_N3 PCIE_MTX_GRX_C_N2 PCIE_MTX_GRX_C_N1 PCIE_MTX_GRX_C_N0

PCIE_MTX_GRX_C_P15 PCIE_MTX_GRX_C_P14 PCIE_MTX_GRX_C_P13 PCIE_MTX_GRX_C_P12 PCIE_MTX_GRX_C_P11 PCIE_MTX_GRX_C_P10 PCIE_MTX_GRX_C_P9 PCIE_MTX_GRX_C_P8 PCIE_MTX_GRX_C_P7 PCIE_MTX_GRX_C_P6 PCIE_MTX_GRX_C_P5 PCIE_MTX_GRX_C_P4 PCIE_MTX_GRX_C_P3 PCIE_MTX_GRX_C_P2 PCIE_MTX_GRX_C_P1 PCIE_MTX_GRX_C_P0

R801 49D9R2F-GPR801 49D9R2F-GP

1 2

R802 750R2F-GPR802 750R2F-GP

1 2

PCIE_MRX_GTX_N[0..15]

PCIE_MRX_GTX_P[0..15]

C829 SCD1U10V2KX-5GP

1 2

DIS

C827 SCD1U10V2KX-5GP

1 2

DIS

C832 SCD1U10V2KX-5GP

1 2

DIS

C812 SCD1U10V2KX-5GP

1 2

DIS

C803 SCD1U10V2KX-5GP

1 2

DIS

C811 SCD1U10V2KX-5GP

1 2

DIS

C828 SCD1U10V2KX-5GP

1 2

DIS

C810 SCD1U10V2KX-5GP

1 2

DIS

C823 SCD1U10V2KX-5GP

1 2

DIS

C804 SCD1U10V2KX-5GP

1 2

DIS

C831 SCD1U10V2KX-5GP

1 2

DIS

C825 SCD1U10V2KX-5GP

1 2

DIS

C821 SCD1U10V2KX-5GP

1 2

DIS

C813 SCD1U10V2KX-5GP

1 2

DIS

C806 SCD1U10V2KX-5GP

1 2

DIS

C816 SCD1U10V2KX-5GP

1 2

DIS

C826 SCD1U10V2KX-5GP

1 2

DIS

C822 SCD1U10V2KX-5GP

1 2

DIS

C818 SCD1U10V2KX-5GP

1 2

DIS

C815 SCD1U10V2KX-5GP

1 2

DIS

C808 SCD1U10V2KX-5GP

1 2

DIS

C802 SCD1U10V2KX-5GP

1 2

DIS

C820 SCD1U10V2KX-5GP

1 2

DIS

C805 SCD1U10V2KX-5GP

1 2

DIS

C817 SCD1U10V2KX-5GP

1 2

DIS

C801 SCD1U10V2KX-5GP

1 2

DIS

C814 SCD1U10V2KX-5GP

1 2

DIS

C824 SCD1U10V2KX-5GP

1 2

DIS

C830 SCD1U10V2KX-5GP

1 2

DIS

C809 SCD1U10V2KX-5GP

1 2

DIS

C807 SCD1U10V2KX-5GP

1 2

DIS

C819 SCD1U10V2KX-5GP

1 2

DIS

PCIE_MRX_GTX_N[0..15] 80

PCIE_MRX_GTX_P[0..15] 80

PCIE_MTX_GRX_N15 PCIE_MTX_GRX_N14 PCIE_MTX_GRX_N13 PCIE_MTX_GRX_N12 PCIE_MTX_GRX_N11 PCIE_MTX_GRX_N10 PCIE_MTX_GRX_N9 PCIE_MTX_GRX_N8 PCIE_MTX_GRX_N7 PCIE_MTX_GRX_N6 PCIE_MTX_GRX_N5 PCIE_MTX_GRX_N4 PCIE_MTX_GRX_N3 PCIE_MTX_GRX_N2 PCIE_MTX_GRX_N1 PCIE_MTX_GRX_N0

PCIE_MTX_GRX_P15 PCIE_MTX_GRX_P14 PCIE_MTX_GRX_P13 PCIE_MTX_GRX_P12 PCIE_MTX_GRX_P11 PCIE_MTX_GRX_P10

PCIE_MTX_GRX_P9 PCIE_MTX_GRX_P8 PCIE_MTX_GRX_P7 PCIE_MTX_GRX_P6 PCIE_MTX_GRX_P5 PCIE_MTX_GRX_P4 PCIE_MTX_GRX_P3 PCIE_MTX_GRX_P2 PCIE_MTX_GRX_P1 PCIE_MTX_GRX_P0

PCIE_MTX_GRX_N[0..15]

PCIE_MTX_GRX_P[0..15]

PCIE_MTX_GRX_N[0..15] 80

PCIE_MTX_GRX_P[0..15] 80

CLARKUNF

CPU SKT:1st:Molex P/N:62.10053.561 2nd:Foxconn P/N:62.10055.321

A A

for Discrete

UMA

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU (PCIE/DMI/FDI)

Size Document Number Rev

Date: Sheet of

CPU (PCIE/DMI/FDI)

Taipei Hsien 221, Taiwan, R.O.C.

Vostro Calpella

8 90Tuesday, September 08, 2009

SA

5

+1.05V_VTT

Processor Pullups

R902 49D9R2F -GPR902 49D9R2F -GP

1 2

R933 68R2-GPR933 68R2-GP

1 2

R904 68R2-GP

1 2

DY

H_CATERR #

H_PROCHO T_R#

H_CPURST #

D D

H_PROCHO T#47

H_PWRG OOD25,42

PM_DRAM_PW RGD22

H_VTTPW RGD49

C C

4

Processor Compensation Signals

1 2

R901 20R2F-G PR 901 20R2F-GP

1 2

R903 20R2F-G PR 903 20R2F-GP

1 2

R905 49D9R2F -GPR905 49D9R2F -GP

1 2

R906 49D9R2F -GPR906 49D9R2F -GP

TP901D o Not Stuff TP901D o Not Stuff

R936

R936 0R2J-2-GP

0R2J-2-GP

1 2

DY

XDP_RST#_R

1 2

R908 0R2J-2-GPR908 0R2J-2-GP

PLT_RST#21,37,64,70,76,77,80

R913:ARD = 1K6R2F-GP P/N:64.160 15.6DL CFD = 1K5R2F-2-GP P/N:64.1 5015.6DL

1 2

1

H_PECI25

H_THRMTR IP#25,37,42

R931

R931 1KR2J-1-GP

1KR2J-1-GP

1 2

H_PM_SYNC22

R913

1K6R2F-GP

DY

H_COMP3 H_COMP2 H_COMP1 H_COMP0

SKTOCC#_R

H_CATERR #

H_PROCHO T_R#

H_CPURST #

VCCPWR GOOD

PM_DRAM_PW RGD

H_PWRG D_XDP

PLT_RST#_R

12

R915

R915 750R2F-GP

750R2F-GP

AT23 AT24

AT26

AH24

AK14

AT15

AN26

AK15

AP26

AL15

AN14

AN27

AK13

AM15

AM26

AL14

G16

CPU1B

COMP3 COMP2 COMP1 COMP0

SKTOCC#

CATERR#

PECI

PROCHOT#

THERMTRIP#

RESET_OBS#

PM_SYNC

VCCPWRGOOD_1

VCCPWRGOOD_0

SM_DRAMPWROK

VTTPWRGOOD

TAPPWRGOOD

RSTIN#

CLARKUNF

3

MISC THERMAL

BCLK_ITP

BCLK_ITP#

PEG_CLK

PEG_CLK#

DPLL_REF_SSCLK

DPLL_REF_SSCLK#

CLOCKS

SM_DRAMRST#

SM_RCOMP0

CLARKSFIELD

PWR MANAGEMENT

SM_RCOMP1 SM_RCOMP2

PM_EXT_TS#0 PM_EXT_TS#1

DDR3

MISC

DDR3

MISC

JTAG & BPM

2 OF 9

BCLK

BCLK#

PRDY# PREQ#

TRST#

TDI_M

TDO_M

DBR#

BPM#0 BPM#1 BPM#2 BPM#3 BPM#4 BPM#5 BPM#6 BPM#7

2

BCLK_CPU_P_R

A16

BCLK_CPU_N _R

B16

BCLK_ITP_P

AR30

BCLK_ITP_N

AT30

PEG_CLK_R

E16

PEG_CLK#_R

D16

DPLL_REF_SSC LK_R

A18

DPLL_REF_SSC LK#_R

A17

SM_DRAMRST #

F6

SM_RCOMP_0

AL1

SM_RCOMP_1

AM1

SM_RCOMP_2

AN1

PM_EXTTS#0_C

AN15

PM_EXTTS#1_C

AP15

XDP_PRDY#

AT28

XDP_PREQ#

AP27

XDP_TCLK

AN28

TCK

XDP_TMS

AP28

TMS

TDO

XDP_TRST#

AT27

XDP_TDI_R

AT29

TDI

XDP_TDO_R

AR27

XDP_TDI_M

AR29

XDP_TDO_M

AP29 AN25

AJ22 AK22 AK24 AJ24 AJ25 AH22 AK23 AH23

H_DBR#_R

XDP_OBS0 XDP_OBS1 XDP_OBS2 XDP_OBS3 XDP_OBS4 XDP_OBS5 XDP_OBS6 XDP_OBS7

R909

1 2

0R2J-2-GP

1 2 3

UMA

XDP_DBRESE T#

4

RN901

RN901 SRN0J-6-GP

SRN0J-6-GP

RN903

RN903 SRN0J-6-GP

SRN0J-6-GP RN904

RN904 SRN0J-6-GP

SRN0J-6-GP

4

1 2 3

RN905

SRN10KJ-5-G P

RN906

RN906 SRN0J-6-GP

SRN0J-6-GP

1 23

4

+1.05V_VTT

2009/07/28 Change 2N7002 ESD pretect from standard to 1KV type P/N:84.2N702.E31 2009/08/06 Changed Q901 from 2N7002 to BSS 138 MOSFET,For Vgs(th)<=1.5V.

BCLK_CPU_P 25 BCLK_CPU_N 25

CLK_EXP_P 23 CLK_EXP_N 23

CLK_DP_P 23 CLK_DP_N 23

PM_EXTTS#0 18 PM_EXTTS#1 19

DDR3 Compensation Signals

SM_RCOMP_0 SM_RCOMP_1 SM_RCOMP_2

Calpella Platform S3 Power Reduction Platform S3 Power Reduction CRB Implementation Design Details

DPLL_REF_SSC LK_R DPLL_REF_SSC LK#_R

DDR_RST _GATE 11,25

C915

SCD1U10V2KX-5GPDYC915

SCD1U10V2KX-5GP

12

+1.5V_SUS

DY

G

DY

1

S

D

S

D

2 3

DY

Q901

Q901 BSS138LT1

BSS138LT1

1 2

R935

R935 0R2J-2-GP

0R2J-2-GP

R907 100R2F-L 1-GP-UR907 100R2F-L 1-GP-U

1 2

R910 24D9R2F -L-GPR910 24D9R2F-L -GP

1 2

R911 130R2F-1 -GPR911 130R2F -1-GP

1 2

RN907

RN907 SRN0J-6-GP

SRN0J-6-GP

1 2 3

DIS

12

R934

R934 1KR2J-1-GP

1KR2J-1-GP

4

DDR3_DR AMRST# 18,1 9

SM_DRAMRST #

1 2

DY

R988

R988 100KR2J-1-GP

100KR2J-1-GP

1

425302_425302_Calpella_S3PowerReduction_WhitePape Revision 0.9

+3.3V_ALW

R937

R937 10KR2J-3-GP

10KR2J-3-GP

1 2

U927

U927_B

1

B

VCC

VTT_PWR GD37,49,50

2

A

3

GND

74LVC1G08GW -1-GP

Y

5 4

12

C903

C903 SCD1U10V2KX- 4GP

SCD1U10V2KX- 4GP

VTT_PWR GD_R3

R977

R977 1K6R2F-GP

1K6R2F-GP

DY

12

PM_DRAM_PW RGD

1K27R2F-L-GP

3KR2F-GP

+1.5V_CPU

R919

R920

12

B B

XDP Connector

XDP1

NP1 61

1 2

XDP_PREQ# XDP_PRDY#

XDP_OBS0 XDP_OBS1

XDP_OBS2 XDP_OBS3

XDP_OBS4 XDP_OBS5

+1.05V_VTT

H_PWRG OOD

R927 1KR2J-1- GP

1 2

DY

R929 0R2J-2- GP

PM_PWRBT N#_R22

H_PWRG D_XDP

12

C902

C902 SCD1U16V2KX- 3GP

A A

DY

SCD1U16V2KX- 3GP

1 2

DY

R930 0R2J-2- GP

1 2

DY

SML0_DATA23

SML0_CLK23

5

XDP_OBS6 XDP_OBS7

H_CPUPW RGD_XDP PM_PWRBT N#_XDP

H_PWRG D_XDP_R

XDP_TCLK

4

Do Not Stuff

3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28

DY

29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

62

63 64 NP2

BCLK_ITP_N_R

XDP_RST#_R

XDP_TRST# XDP_TDI XDP_TMS

R912 Do Not StuffR912 Do Not Stuff

12

R938 Do Not StuffR938 Do Not Stuff

12

XDP_RST#_R

+1.05V_VCCP use Decoupling Capacitor close ITP connector 100 mil ( max )

CPU

TCK(PIN AN28)

+1.05V_VTT

12

C901

SCD1U16V2KX- 3GP

BCLK_ITP_PBCLK_ITP_P_R BCLK_ITP_N

SCD1U16V2KX- 3GP

1 2

DY

R932 0R2J-2-GP

12

DY

R928

R928 51R2J-2-GP

51R2J-2-GP

3

XDP Connector

TCK(PIN 57)

XDP_TDO

PLT_RST# 21,37,64,70,76,77,8 0

XDP_DBRESE T# 22

Normal

AUB

1.27k

CFD

1.1k 3k

S3 Power Reduction circuit

AUB

1.1k(DY)

CFD

1.1k(DY) 0.75k

XDP_TMS XDP_TDI_R XDP_PREQ#

XDP_TCLK

XDP_TDI_R

XDP_TDO_M

XDP_TDI_M

XDP_TDO_R

Scan Chain (Default) CPU Only

GMCH Only

1 2

DY

R914 51R2J-2-G P

1 2

DY

R916 51R2J-2-G P

1 2

DY

R917 51R2J-2-G P

1 2

DY

R918 51R2J-2-G P

1 2

R921 0R2J-2-GPR921 0R2J-2-GP

1 2

R922 0R2J-2-GP

12

R924

R924 0R2J-2-GP

0R2J-2-GP

1 2

R925 0R2J-2-GP

1 2

R926 0R2J-2-GPR926 0R2J-2-GP

Stuff --> R921, R924, R926 No Stuff --> R922, R925 Stuff --> R921, R922 No Stuff --> R924, R926, R925 Stuff --> R926, R925 No Stuff --> R921, R922, R924

2

R920R919

3k

R920R919

0.75k

DY

R977

1.6k(DY)

1.5k(DY)

R977

1.6k

1.5k

+1.05V_VTT

XDP_TDI

XDP_TDO

XDP_TRST#

12

R923

R923 51R2J-2-GP

51R2J-2-GP

JTAG MAPPING

UMA

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd ., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd ., Hsichih, Taipei Hsie n 221, Taiwan, R.O .C.

Taipei Hsie n 221, Taiwan, R.O .C.

Title

CPU (THERMAL/CLOCK/PM )

ize Document Num ber Rev

Size Document Num ber Rev

S

Date: Sheet of

Taipei Hsie n 221, Taiwan, R.O .C.

Vostro Calpella

1

SA

9 90Tuesday, Septem ber 08, 2009

SA

5

CPU1C

4

3 OF 9

3

CPU1D

2

4 OF 9

1

W8

AA6

SA_CK0

AA7

M_A_DQ[63..0]18

D D

C C

B B

M_A_DQ[63..0]

M_A_BS018 M_A_BS118 M_A_BS218

M_A_CAS#18 M_A_RAS#18 M_A_WE#18

M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63

A10 C10

B10 D10 E10

F10

H10

G10

AH5

AF5 AK6 AK7

AF6 AG5

AJ7

AJ6

AJ10

AJ9

AL10 AK12

AK8

AL7

AK11

AL8 AN8

AM10 AR11

AL11

AM9 AN9

AT11

AP12 AM12 AN12 AM13

AT14

AT12

AL13 AR14

AP14

AC3 AB2

AE1 AB3 AE9

SA_DQ0 SA_DQ1

C7

SA_DQ2

A7

SA_DQ3 SA_DQ4 SA_DQ5 SA_DQ6

A8

SA_DQ7

D8

SA_DQ8 SA_DQ9

E6

SA_DQ10

F7

SA_DQ11

E9

SA_DQ12

B7

SA_DQ13

E7

SA_DQ14

C6

SA_DQ15 SA_DQ16

G8

SA_DQ17

K7

SA_DQ18

J8

SA_DQ19

G7

SA_DQ20 SA_DQ21

J7

SA_DQ22

J10

SA_DQ23

L7

SA_DQ24

M6

SA_DQ25

M8

SA_DQ26

L9

SA_DQ27

L6

SA_DQ28

K8

SA_DQ29

N8

SA_DQ30

P9

SA_DQ31 SA_DQ32 SA_DQ33 SA_DQ34 SA_DQ35 SA_DQ36 SA_DQ37 SA_DQ38 SA_DQ39 SA_DQ40 SA_DQ41 SA_DQ42 SA_DQ43 SA_DQ44 SA_DQ45 SA_DQ46 SA_DQ47 SA_DQ48 SA_DQ49 SA_DQ50 SA_DQ51 SA_DQ52 SA_DQ53 SA_DQ54 SA_DQ55 SA_DQ56 SA_DQ57 SA_DQ58 SA_DQ59 SA_DQ60 SA_DQ61 SA_DQ62 SA_DQ63

SA_BS0 SA_BS1

U7

SA_BS2

SA_CAS# SA_RAS# SA_WE#

SA_CK#0

P7

SA_CKE0

Y6

SA_CK1

Y5

SA_CK#1

P6

SA_CKE1

AE2

SA_CS#0

AE8

SA_CS#1

CLARKSFIELD

DDR SYSTEM MEMORY A

SA_ODT0 SA_ODT1

SA_DM0 SA_DM1 SA_DM2 SA_DM3 SA_DM4 SA_DM5 SA_DM6 SA_DM7

SA_DQS#0 SA_DQS#1 SA_DQS#2 SA_DQS#3 SA_DQS#4 SA_DQS#5 SA_DQS#6 SA_DQS#7

SA_DQS0 SA_DQS1 SA_DQS2 SA_DQS3 SA_DQS4 SA_DQS5 SA_DQS6 SA_DQS7

SA_MA0 SA_MA1 SA_MA2 SA_MA3 SA_MA4 SA_MA5 SA_MA6 SA_MA7 SA_MA8

SA_MA9 SA_MA10 SA_MA11 SA_MA12 SA_MA13 SA_MA14 SA_MA15

AD8 AF9

B9 D7 H7 M7 AG6 AM7 AN10 AN13

C9 F8 J9 N9 AH7 AK9 AP11 AT13

C8 F9 H9 M9 AH8 AK10 AN11 AR13

Y3 W1 AA8 AA3 V1 AA9 V8 T1 Y9 U6 AD4 T2 U3 AG8 T3 V9

M_A_DM0 M_A_DM1 M_A_DM2 M_A_DM3 M_A_DM4 M_A_DM5 M_A_DM6 M_A_DM7

M_A_DQS#0 M_A_DQS#1 M_A_DQS#2 M_A_DQS#3 M_A_DQS#4 M_A_DQS#5 M_A_DQS#6 M_A_DQS#7

M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6 M_A_DQS7

M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14 M_A_A15

M_CLK_DDR0 18 M_CLK_DDR#0 18 M_CKE0 18

M_CLK_DDR1 18 M_CLK_DDR#1 18 M_CKE1 18

M_CS0# 18 M_CS1# 18

M_ODT0 18 M_ODT1 18

M_B_DQ[63..0]19

M_A_DM[7..0] 18 M_A_DQS#[7..0] 18

M_A_DQS[7..0] 18 M_A_A[15..0] 18

M_B_DQ[63..0]

M_B_BS019 M_B_BS119 M_B_BS219

M_B_CAS#19 M_B_RAS#19 M_B_WE#19

M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63

AF3 AG1

AK1 AG4 AG3

AH4 AK3

AK4 AM6 AN2

AK5

AK2 AM4 AM3

AP3 AN5

AT4 AN6 AN4 AN3

AT5

AT6 AN7

AP6

AP8

AT9

AT7

AP9

AR10

AT10

AB1

AC5

AC6

B5

SB_DQ0

A5

SB_DQ1

C3

SB_DQ2

B3

SB_DQ3

E4

SB_DQ4

A6

SB_DQ5

A4

SB_DQ6

C4

SB_DQ7

D1

SB_DQ8

D2

SB_DQ9

F2

SB_DQ10

F1

SB_DQ11

C2

SB_DQ12

F5

SB_DQ13

F3

SB_DQ14

G4

SB_DQ15

H6

SB_DQ16

G2

SB_DQ17

J6

SB_DQ18

J3

SB_DQ19

G1

SB_DQ20

G5

SB_DQ21

J2

SB_DQ22

J1

SB_DQ23

J5

SB_DQ24

K2

SB_DQ25

L3

SB_DQ26

M1

SB_DQ27

K5

SB_DQ28

K4

SB_DQ29

M4

SB_DQ30

N5

SB_DQ31 SB_DQ32 SB_DQ33

AJ3

SB_DQ34 SB_DQ35 SB_DQ36 SB_DQ37

AJ4

SB_DQ38 SB_DQ39 SB_DQ40 SB_DQ41 SB_DQ42 SB_DQ43 SB_DQ44 SB_DQ45 SB_DQ46 SB_DQ47 SB_DQ48 SB_DQ49 SB_DQ50 SB_DQ51 SB_DQ52 SB_DQ53 SB_DQ54 SB_DQ55 SB_DQ56 SB_DQ57 SB_DQ58 SB_DQ59 SB_DQ60 SB_DQ61 SB_DQ62 SB_DQ63

SB_BS0

W5

SB_BS1

R7

SB_BS2

SB_CAS#

Y7

SB_RAS# SB_WE#

CLARKSFIELD

DDR SYSTEM MEMORY - B

SB_CK0 SB_CK#0 SB_CKE0

SB_CK1 SB_CK#1 SB_CKE1

SB_CS#0 SB_CS#1

SB_ODT0 SB_ODT1

SB_DM0 SB_DM1 SB_DM2 SB_DM3 SB_DM4 SB_DM5 SB_DM6 SB_DM7

SB_DQS#0 SB_DQS#1 SB_DQS#2 SB_DQS#3 SB_DQS#4 SB_DQS#5 SB_DQS#6 SB_DQS#7

SB_DQS0 SB_DQS1 SB_DQS2 SB_DQS3 SB_DQS4 SB_DQS5 SB_DQS6 SB_DQS7

SB_MA0

SB_MA1

SB_MA2

SB_MA3

SB_MA4

SB_MA5

SB_MA6

SB_MA7

SB_MA8

SB_MA9

SB_MA10 SB_MA11 SB_MA12 SB_MA13 SB_MA14 SB_MA15

W9 M3

V7 V6 M2

AB8 AD6

AC7 AD1

D4 E1 H3 K1 AH1 AL2 AR4 AT8

D5 F4 J4 L4 AH2 AL4 AR5 AR8

C5 E3 H4 M5 AG2 AL5 AP5 AR7

U5 V2 T5 V3 R1 T8 R2 R6 R4 R5 AB5 P3 R3 AF7 P5 N1

M_B_DM0 M_B_DM1 M_B_DM2 M_B_DM3 M_B_DM4 M_B_DM5 M_B_DM6 M_B_DM7

M_B_DQS#0 M_B_DQS#1 M_B_DQS#2 M_B_DQS#3 M_B_DQS#4 M_B_DQS#5 M_B_DQS#6 M_B_DQS#7

M_B_DQS0 M_B_DQS1 M_B_DQS2 M_B_DQS3 M_B_DQS4 M_B_DQS5 M_B_DQS6 M_B_DQS7

M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14 M_B_A15

M_CLK_DDR2 19 M_CLK_DDR#2 19 M_CKE2 19

M_CLK_DDR3 19 M_CLK_DDR#3 19 M_CKE3 19

M_CS2# 19 M_CS3# 19

M_ODT2 19 M_ODT3 19

M_B_DM[7..0] 19 M_B_DQS#[7..0] 19

M_B_DQS[7..0] 19 M_B_A[15..0] 19

CLARKUNF

A A

5

4

3

CLARKUNF

UMA

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Date: Sheet of

2

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

CPU (DDR)

Vostro Calpella

1

SA

10 90Tuesday, September 08, 2009

SA

5

R1104 0R2J-2-GP

1 2

DY

Q1101

Q1101 AO3418-GP

M_VREF_DQ_DIMM0

DDR_RST_GATE9,25

CFG0

PCI-Express Configuration Select

1:Single PEG

CFG0

0:Bifurcation enabled

CFG3

CFG3 - PCI-Express Static Lane Reversal

1 :Normal Operation

CFG3

0 :Lane Numbers Reversed 15 -> 0, 14 -> 1, ...

CFG4 - Display Port Presence

CFG4

1:Disabled; No Physical Display Port

CFG4

attached to Embedded Display Port 0:Enabled; An external Display Port device is connected to the Embedded Display Port

Calpella Platform Design Guide Revision 1.6

3KR2F-GP

R1102

3KR2F-GP

R1103

3KR2F-GP

R1101

DY

M_VREF_DQ_DIMM018

M_VREF_DQ_DIMM119

DY

DIS

12

改改改改

5%

D D

C C

B B

AO3418-GP

D S

CFD

R1105 0R2J-2-GP

1 2

DY

Q1102

Q1102 AO3418-GP

AO3418-GP

D S

CFD

4.8.3.1 LVDS Switching

Switchable GFX, just like integrated GFX only, to enable LVDS it is required that the OEM set the LDVS (L_DDC_DATA) strap to present (pulled up) and the eDP strap (CFG[4]) to disabled (not pulled down).

4

SA_DIMM_VREF#

12

R1108

G

CFD

12

CFD

R1108 100KR2J-1-GP

100KR2J-1-GP

SB_DIMM_VREF#M_VREF_DQ_DIMM1

R1110

R1110 100KR2J-1-GP

100KR2J-1-GP

3

AP25

AL25 AL24 AL22 AJ33

AG9 M27

TP1101Do Not Stuff TP1101Do Not Stuff TP1102Do Not Stuff TP1102Do Not Stuff

TP1104Do Not Stuff TP1104Do Not Stuff TP1105Do Not Stuff TP1105Do Not Stuff

TP1106Do Not Stuff TP1106Do Not Stuff TP1107Do Not Stuff TP1107Do Not Stuff TP1108Do Not Stuff TP1108Do Not Stuff TP1109Do Not Stuff TP1109Do Not Stuff TP1110Do Not Stuff TP1110Do Not Stuff TP1111Do Not Stuff TP1111Do Not Stuff TP1112Do Not Stuff TP1112Do Not Stuff TP1113Do Not Stuff TP1113Do Not Stuff TP1114Do Not Stuff TP1114Do Not Stuff TP1115Do Not Stuff TP1115Do Not Stuff

SA_DIMM_VREF# SB_DIMM_VREF#

1 1

1 1 1 1 1 1 1 1 1 1

CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15 CFG16 CFG17

G25 G17

AM30 AM28 AP31

AL32

AL30 AM31 AN29 AM32 AK32 AK31 AK28

AJ28 AN30 AN32

AJ32

AJ29

AJ30 AK30

AC9 AB9

L28

J17

H17

E31 E30

H16

B19 A19

A20 B20

U9

T9

J29 J28

CPU1E

RSVD#AP25 RSVD#AL25 RSVD#AL24 RSVD#AL22 RSVD#AJ33 RSVD#AG9 RSVD#M27 RSVD#L28 SA_DIMM_VREF SB_DIMM_VREF RSVD#G25 RSVD#G17 RSVD#E31 RSVD#E30

CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15 CFG16 CFG17 RSVD_TP_86

RSVD#B19 RSVD#A19

RSVD#A20 RSVD#B20

RSVD#U9 RSVD#T9

RSVD#AC9 RSVD#AB9

RSVD#J29 RSVD#J28

CLARKUNF

2

CLARKSFIELD

RESERVED

5 OF 9

RSVD#AJ13 RSVD#AJ12

RSVD#AH25 RSVD#AK26

RSVD#AL26

RSVD_NCTF_37

RSVD#AJ26 RSVD#AJ27

RSVD#AL28

RSVD#AL29 RSVD#AP30 RSVD#AP32

RSVD#AL27 RSVD#AT31 RSVD#AT32 RSVD#AP33 RSVD#AR33

RSVD#AR32

RSVD_TP#E15 RSVD_TP#F15

RSVD#D15 RSVD#C15

RSVD#AJ15 RSVD#AH15

SA_CK2 SA_CK#2 SA_CKE2 SA_CS#2 SA_ODT2

SA_CK3 SA_CK#3 SA_CKE3 SA_CS#3 SA_ODT3

SB_CK2 SB_CK#2 SB_CKE2 SB_CS#2 SB_ODT2

SB_CK3 SB_CK#3 SB_CKE3 SB_CS#3 SB_ODT3

1

AJ13 AJ12

AH25 AK26

AL26 AR2

AJ26 AJ27

AL28 AL29 AP30 AP32 AL27 AT31 AT32 AP33 AR33

AR32

E15 F15 A2

KEY

D15 C15

RSVD#AJ15

AJ15

RSVD#AH15

AH15

AA5 AA4 R8 AD3 AD2 AA2 AA1 R9 AG7 AE3

V4 V5 N2 AD5 AD7 W3 W2 N3 AE5 AD9

AP34

VSS

VSS (AP34) can be left NC is CRB implementation; EDS/DG recommendation to GND.

1 1

TP1120 Do Not StuffTP1120 Do Not Stuff TP1121 Do Not StuffTP1121 Do Not Stuff

4.8.3.2 eDP Switching

eDP for Switchable GFX can only be driven out of Port D of PCH. To configure Port D for embedded DP it is required to set the DDPD_CTRLDATA strap high to 3.3V Core rail through 2.2 kΩ ±5% resistor, LVDS (L_DDC_DATA) strap as no connect and the eDP strap CFG[4] as no connect.

CFG7(Reserved) - Temporarily used for early Clarksfield samples.

DY

CFG7

12

5

CFG7 Clarksfield (only for early samples pre-ES1) -

Connect to GND with 3.01K Ohm/5% resistor. Note: Only temporary for early CFD sample

(rPGA/BGA) [For details please refer to the WW33 MoW and sighting report]. For a common M/B design (for AUB and CFD), the pull-down resistor shouble be used. Does not impact AUB functionality.

4

A A

R1109

3KR2F-GP

Page 482,486

UMA

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

ize Document Number Rev

Size Document Number Rev

S

Date: Sheet of

3

2

Date: Sheet of

CPU (RESERVED)

Taipei Hsien 221, Taiwan, R.O.C.

Vostro Calpella

11 90Tuesday, September 08, 2009

1

SA

5

4

CPU1F

3

6 OF 9

2

1

+VCC_CORE

PROCESSOR CORE POWER

+VCC_CORE

D D

C C

C1243

12

DY

B B

C1207

C1206

12

SC10U6D3V5MX-3GP

C1212

C1225

C1235

SC10U6D3V5MX-3GP

C1213

12

SC10U6D3V5MX-3GP

C1226

12

SC22U6D3V5MX-2GP

C1236

12

SC10U6D3V5MX-3GP

C1209

C1208

12

SC10U6D3V5MX-3GP

C1214

12

SC10U6D3V5MX-3GP

C1227

12

SC22U6D3V5MX-2GP

C1237

12

SC10U6D3V5MX-3GP

12

SC10U6D3V5MX-3GP

C1215

12

SC10U6D3V5MX-3GP

C1228

12

SC10U6D3V5MX-3GP

C1238

12

SC10U6D3V5MX-3GP

Clarksfield = 52A

Arrandale = 48A

C1210

C1220

12

SC10U6D3V5MX-3GP

C1223

C1224

12

SC10U6D3V5MX-3GP

C1229

C1230

12

SC10U6D3V5MX-3GP

C1239

C1240

12

SC10U6D3V5MX-3GP

C1231

C1232

12

SC10U6D3V5MX-3GP

SC22U6D3V5MX-2GP

C1242

C1241

12

SC22U6D3V5MX-2GP

AG35 AG34 AG33 AG32 AG31 AG30 AG29 AG28 AG27 AG26

AF35 AF34 AF33 AF32 AF31 AF30 AF29 AF28 AF27 AF26 AD35 AD34 AD33 AD32 AD31 AD30 AD29 AD28 AD27 AD26 AC35 AC34 AC33 AC32 AC31 AC30 AC29 AC28 AC27 AC26 AA35 AA34 AA33 AA32 AA31 AA30 AA29 AA28 AA27 AA26

VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC

Y35

VCC

Y34

VCC

Y33

VCC

Y32

VCC

Y31

VCC

Y30

VCC

Y29

VCC

Y28

VCC

Y27

VCC

Y26

VCC

V35

VCC

V34

VCC

V33

VCC

V32

VCC

V31

VCC

V30

VCC

V29

VCC

V28

VCC

V27

VCC

V26

VCC

U35

VCC

U34

VCC

U33

VCC

U32

VCC

U31

VCC

U30

VCC

U29

VCC

U28

VCC

U27

VCC

U26

VCC

R35

VCC

R34

VCC

R33

VCC

R32

VCC

R31

VCC

R30

VCC

R29

VCC

R28

VCC

R27

VCC

R26

VCC

P35

VCC

P34

VCC

P33

VCC

P32

VCC

P31

VCC

P30

VCC

P29

VCC

P28

VCC

P27

VCC

P26

VCC

CLARKSFIELD

1.1V RAIL POWER

CPU CORE SUPPLY

PROC_DPRSLPVR

CPU VIDS

POWER

VTT_SELECT

VSS_SENSE_VTT

SENSE LINES

VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0

VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0

PSI#

ISENSE

VCC_SENSE

VSS_SENSE

VTT_SENSE

AH14 AH12 AH11 AH10 J14 J13 H14 H12 G14 G13 G12 G11 F14 F13 F12 F11 E14 E12 D14 D13 D12 D11 C14 C13 C12 C11 B14 B12 A14 A13 A12 A11

AF10 AE10 AC10 AB10 Y10 W10 U10 T10 J12 J11 J16 J15

AN33

CPU_VID0

AK35

VID

CPU_VID1

AK33

VID

CPU_VID2

AK34

VID

CPU_VID3

AL35

VID

CPU_VID4

AL33

VID

CPU_VID5

AM33

VID

CPU_VID6

AM35

VID

AM34

TP_VTT_SELECT

G15

VTT_SELECT = Low, 1.1V VTT_SELECT = High, 1.05V

AN35

VCC_SENSE

AJ34

VSS_SENSE

AJ35

B15

TP_VSS_SENSE_VTT

A15

1

12

C1202

C1201

SC10U10V5ZY-1GP

PSI# 47 CPU_VID[6..0] 47

PM_DPRSLPVR 47

TP1203

Do Not Stuff

IMVP_IMON 47

VTT_SENSE 49

TP1202

TP1202 Do Not Stuff

Do Not Stuff

12

C1217

SC10U10V5ZY-1GP

12

C1218

SC10U10V5ZY-1GP

12

C1205

C1204

SC10U10V5ZY-1GP

The decoupling capacitors, filter recommendations and sense resistors on the CPU/PCH Rails are specific to the CRB Implementation. Customers need to follow the recommendations in the Calpella Platform Design Guide.

Please note that the VTT Rail

+1.05V_VTT

C1234

12

SC10U6D3V5MX-3GP

+VCC_CORE

12

R1201

R1201 100R2F-L1-GP-U

100R2F-L1-GP-U

12

R1204

R1204 100R2F-L1-GP-U

100R2F-L1-GP-U

Values are Arrandale VTT=1.05V; Clarksfield VTT=1.1V

DIS(Clarksfield +1.05V_VTT) = 14.4A

DIS(Arrandale +1.05V_VTT) = 20.95A

UMA(Arrandale +1.05V_VTT) = 19.84A

VCC_SENSE 47 VSS_SENSE 47

+1.05V_VTT

12

A A

CLARKUNF

5

4

3

2

UMA

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Date: Sheet of

CPU (VCC_CORE)

Taipei Hsien 221, Taiwan, R.O.C.

Vostro Calpella

12 90Tuesday, September 08, 2009

1

SA

5

4

3

2

1

+1.5V_CPU

12

DY

C1376

C1376 SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

+CPU_GFXCORE

D D

C C

TC1303

SE330U2VDM-L-GP

22A

12

DY

C1324

C1328

C1327

C1326

12

SC10U6D3V5MX-3GP

DY

+1.05V_VTT

C1326

12

SC10U6D3V5MX-3GP

12

SC10U6D3V5MX-3GP

DY

C1328

12

SC10U6D3V5MX-3GP

C1325

C1323

12

SC10U6D3V5MX-3GP

Please note that the VTT Rail Values are Arrandale VTT=1.05V; Clarksfield VTT=1.1V

+1.05V_VTT

B B

18A

12

C1312

12

C1313

SC10U6D3V5MX-3GP

12

C1309

C1309 SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

12

C1314

C1315

SC10U6D3V5MX-3GP

AT21 AT19 AT18

AT16 AR21 AR19 AR18 AR16 AP21 AP19 AP18 AP16 AN21 AN19 AN18 AN16 AM21 AM19 AM18 AM16

AL21

AL19

AL18

AL16 AK21 AK19 AK18 AK16

AJ21

AJ19

AJ18

AJ16 AH21 AH19 AH18 AH16

J24 J23 H25

K26 J27 J26 J25

H27 G28 G27 G26

F26 E26 E25

CPU1G

VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG

VTT1 VTT1 VTT1

VTT1 VTT1 VTT1 VTT1 VTT1 VTT1 VTT1 VTT1 VTT1 VTT1 VTT1

SENSE

GRAPHICS

CLARKSFIELD

FDI PEG & DMI

POWER

LINES

GRAPHICS VIDs

7 OF 9

GFX_VID GFX_VID GFX_VID GFX_VID GFX_VID GFX_VID GFX_VID

GFX_IMON

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VTT0 VTT0 VTT0 VTT0

VTT1 VTT1 VTT1 VTT1 VTT1 VTT1

VCCPLL VCCPLL VCCPLL

AR22 AT22

AM22 AP22 AN22 AP23 AM23 AP24 AN24

AR25

TP_GFX_DPRSLPVR

AT25 AM24

R1302

R1302 1KR2J-1-GP

1KR2J-1-GP

AJ1 AF1 AE7 AE4 AC1 AB7 AB4 Y1 W7 W4 U1 T7 T4 P1 N7 N4 L1 H1

P10 N10 L10 K10

J22 J20 J18 H21 H20 H19

L26 L27 M26

GFX_IMON_R

1 2

DIS

SC10U6D3V5MX-3GP

VAXG_SENSE

VSSAXG_SENSE

GFX_VR_EN

GFX_DPRSLPVR

DDR3 - 1.5V RAILS

1.1V1.8V

+1.5V_SUS

2009/08/12 Follow Intel "425302_Calpella_S3PowerReduction_WhitePaper_Rev0.9. pdf" document.

VCC_AXG_SENSE 53 VSS_AXG_SENSE 53

GFX_VID0 53 GFX_VID1 53 GFX_VID2 53 GFX_VID3 53 GFX_VID4 53 GFX_VID5 53 GFX_VID6 53

GFX_VR_EN 53

1

TP1303 Do Not StuffTP1303 Do Not Stuff

1 2

UMA

R1301

R1301 0R2J-2-GP

0R2J-2-GP

12

SC1U10V2KX-1GP

C1310

C1316

C1302

12

C1318

12

C1303

SC1U10V2KX-1GP

12

C1319

SC1U25V5KX-1GP

C1301

+1.5V_CPU

DY

+1.5V_SUS

GFX_IMON 53

ARD=3A CFD=6A

12

C1305

C1304

SC1U10V2KX-1GP

+1.05V_VTT

C1311

C1311 SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

+1.05V_VTT

C1317

C1317 SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

12

C1320

C1321

SC4D7U6D3V5KX-3GP

SC2D2U10V3KX-1GP

12

C1377

C1377 SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

12

C1306

C1307

SC10U6D3V5MX-3GP

ARD=1.35A CFD=1.1A

12

C1322

C1322 SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

+1.5V_CPU

12

SC10U6D3V5MX-3GP

+1.8V_RUN

+1.5V_CPU

12

DY

C1378

C1378 SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

+1.5V_SUS

TC1301

TC1301 SE330U2D5VDM-2GP

SE330U2D5VDM-2GP

+1.5V_CPU

12

DY

+1.5V_SUS

C1379

C1379 SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

CLARKUNF

A A

5

4

3

2

UMA

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU (VCC_GFXCORE)

ize Document Number Rev

Size Document Number Rev

S

Date: Sheet of

CPU (VCC_GFXCORE)

Taipei Hsien 221, Taiwan, R.O.C.

Vostro Calpella

13 90Tuesday, September 08, 2009

1

SA

5

CPU1H

AT20

VSS

AT17

VSS

AR31

VSS

AR28

VSS

AR26

VSS

AR24

VSS

D D

C C

B B

AR23 AR20 AR17 AR15 AR12

AP20 AP17 AP13 AP10

AN34 AN31 AN23 AN20

AN17 AM29 AM27 AM25 AM20 AM17 AM14 AM11

AM8 AM5

AM2 AL34 AL31 AL23 AL20 AL17 AL12

AK29 AK27 AK25 AK20 AK17

AJ31 AJ23 AJ20 AJ17 AJ14 AJ11

AH35 AH34 AH33 AH32 AH31 AH30 AH29 AH28 AH27 AH26 AH20 AH17 AH13

AH9

AH6

AH3 AG10

AE35

AR9 AR6 AR3

AP7 AP4 AP2

AL9 AL6 AL3

AJ8 AJ5 AJ2

AF8 AF4 AF2

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

4

CLARKSFIELD

VSS

8 OF 9

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

AE34 AE33 AE32 AE31 AE30 AE29 AE28 AE27 AE26 AE6 AD10 AC8 AC4 AC2 AB35 AB34 AB33 AB32 AB31 AB30 AB29 AB28 AB27 AB26 AB6 AA10 Y8 Y4 Y2 W35 W34 W33 W32 W31 W30 W29 W28 W27 W26 W6 V10 U8 U4 U2 T35 T34 T33 T32 T31 T30 T29 T28 T27 T26 T6 R10 P8 P4 P2 N35 N34 N33 N32 N31 N30 N29 N28 N27 N26 N6 M10 L35 L32 L29 L8 L5 L2 K34 K33 K30

3

CPU1I

K27

VSS

K9

VSS

K6

VSS

K3

VSS

J32

VSS

J30

VSS

J21

VSS

J19

VSS

H35

VSS

H32

VSS

H28

VSS

H26

VSS

H24

VSS

H22

VSS

H18

VSS

H15

VSS

H13

VSS

H11

VSS

H8

VSS

H5

VSS

H2

VSS

G34

VSS

G31

VSS

G20

VSS

G9

VSS

G6

VSS

G3

VSS

F30

VSS

F27

VSS

F25

VSS

F22

VSS

F19

VSS

F16

VSS

E35

VSS

E32

VSS

E29

VSS

E24

VSS

E21

VSS

E18

VSS

E13

VSS

E11

VSS

E8

VSS

E5

VSS

E2

VSS

D33

VSS

D30

VSS

D26

VSS

D9

VSS

D6

VSS

D3

VSS

C34

VSS

C32

VSS

C29

VSS

C28

VSS

C24

VSS

C22

VSS

C20

VSS

C19

VSS

C16

VSS

B31

VSS

B25

VSS

B21

VSS

B18

VSS

B17

VSS

B13

VSS

B11

VSS

B8

VSS

B6

VSS

B4

VSS

A29

VSS

A27

VSS

A23

VSS

A9

VSS

2

9 OF 9

CLARKSFIELD

VSS

VSS_NCTF VSS_NCTF VSS_NCTF

NCTF

VSS_NCTF#A35

VSS_NCTF#AT1

VSS_NCTF#AT35

VSS_NCTF#B1

RSVD_NCTF#A3 RSVD_NCTF#A33 RSVD_NCTF#A34 RSVD_NCTF#AP1

RSVD_NCTF#AP35

RSVD_NCTF#AR1

RSVD_NCTF#AR35

RSVD_NCTF#AT2 RSVD_NCTF#AT3

RSVD_NCTF#AT33 RSVD_NCTF#AT34

RSVD_NCTF#C1 RSVD_NCTF#C35

NCYF TEST PIN:

A35,AT1,AT35,B1,A3,A33,A34,

NCYF TEST PIN:

A35,AT1,AT35,B1,A3,A33,A34,

RSVD_NCTF#B35

AP1,AP35,AR1,AR35,AT2,AT3,

AT33,AT34,C1,C35,B35

AP1,AP35,AR1,AR35,AT2,AT3,

AT33,AT34,C1,C35,B35

AR34 B34 B2

A35 AT1 AT35 B1 A3 A33 A34 AP1 AP35 AR1 AR35 AT2 AT3 AT33 AT34 C1 C35 B35

TP_MCP_VSS_NCTF1 TP_MCP_VSS_NCTF2 TP_MCP_VSS_NCTF3 TP_MCP_VSS_NCTF4

1

TP1401TP1401

1

TP1402TP1402

1

TP1406TP1406

1

TP1405TP1405

1

CLARKUNF

A A

5

4

3

CLARKUNF

UMA

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Date: Sheet of

2

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

CPU (VSS)

Vostro Calpella

1

SA

14 90Tuesday, September 08, 2009

SA

5

D D

C C

4

3

2

1

(Blank)

B B

A A

5

4

3

2

UMA

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

Vostro Calpella

15 90Tuesday, September 08, 2009

1

SA

5

D D

C C

4

3

2

1

(Blank)

B B

A A

5

4

3

2

UMA

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

Vostro Calpella

1

16 90Tuesday, September 08, 2009

SA

5

D D

C C

4

3

2

1

(Blank)

B B

A A

5

4

3

2

UMA

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

(Reserve)

Vostro Calpella

1

17 90Tuesday, September 08, 2009

SA

5

SSID = MEMORY

M_A_DQS#[7..0]10

D D

+1.5V_SUS

C1803

SC10U6D3V5MX-3GP

C1803

SC10U6D3V5MX-3GP

12

C C

+0.75V_DDR_VTT

C1814

SC1U10V2KX-1GP

C1814

SC1U10V2KX-1GP

12

+1.5V_SUS

C1872

SCD1U10V2KX-4GP

C1872

SCD1U10V2KX-4GP

12

B B

2009/08/12 Follow Intel "425302_Calpella_S3PowerReduction_WhitePaper_Rev0.9. pdf" document.

+V_DDR_REF

12

R1803

A A

C1817

C1817 SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

ARD

12

R1803 0R2J-2-GP

0R2J-2-GP

M_A_DQ[63..0]10 M_A_DM[7..0]10 M_A_DQS[7..0]10 M_A_A[15..0]10

Layout Note: Place near DM1

C1812

SC10U6D3V5MX-3GP

C1812

SC10U6D3V5MX-3GP

C1802

SC10U6D3V5MX-3GP

C1802

C1804

SC10U6D3V5MX-3GP

C1804

SC10U6D3V5MX-3GP

12

Layout Note: Put close to VTT1,VTT2.

C1813

SC1U10V2KX-1GP

C1813

SC1U10V2KX-1GP

12

C1873

SCD1U10V2KX-4GP

C1873

SCD1U10V2KX-4GP

12

C1805

C1805 SC2D2U10V3KX-1GP

SC2D2U10V3KX-1GP

5

12

C1815

SC1U10V2KX-1GP

C1815

SC1U10V2KX-1GP

12

C1874

SCD1U10V2KX-4GP

C1874

SCD1U10V2KX-4GP

12

SC10U6D3V5MX-3GP

C1801

SC1U10V2KX-1GP

C1801

SC1U10V2KX-1GP

C1875

C1875 SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

M_VREF_DQ_DIMM0 11

C1811

SC10U6D3V5MX-3GP

C1811

SC10U6D3V5MX-3GP

12

C1810

C1810 SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

C1816

SC10U6D3V5MX-3GP

C1816

SC10U6D3V5MX-3GP

12

C1823

12

SC10U6D3V5MX-3GP

+V_DDR_REF

TC1803

TC1803 ST330U2D5VBM-1-GP

ST330U2D5VBM-1-GP

12

4

12

C1809

C1809 SC2D2U10V3KX-1GP

SC2D2U10V3KX-1GP

4

M_A_BS210 M_A_BS010

M_A_BS110

M_VREF_DQ_DIMM0

+0.75V_DDR_VTT

3

DM1

3

DM1

98

A0

97

A1

96

A2

95

A3

92

A4

91

A5

90

A6

86

A7

89

A8

85

A9

107

A10/AP

84

A11

83

A12

119

A13

80

A14

78

A15

79

A16/BA2

109

BA0

108

BA1

5

DQ0

7

DQ1

15

DQ2

17

DQ3

4

DQ4

6

DQ5

16

DQ6

18

DQ7

21

DQ8

23

DQ9

33

DQ10

35

DQ11

22

DQ12

24

DQ13

34

DQ14

36

DQ15

39

DQ16

41

DQ17

51

DQ18

53

DQ19

40

DQ20

42

DQ21

50

DQ22

52

DQ23

57

DQ24

59

DQ25

67

DQ26

69

DQ27

56

DQ28

58

DQ29

68

DQ30

70

DQ31

129

DQ32

131

DQ33

141

DQ34

143

DQ35

130

DQ36

132

DQ37

140

DQ38

142

DQ39

147

DQ40

149

DQ41

157

DQ42

159

DQ43

146

DQ44

148

DQ45

158

DQ46

160

DQ47

163

DQ48

165

DQ49

175

DQ50

177

DQ51

164

DQ52

166

DQ53

174

DQ54

176

DQ55

181

DQ56

183

DQ57

191

DQ58

193

DQ59

180

DQ60

182

DQ61

192

DQ62

194

DQ63

10

DQS0#

27

DQS1#

45

DQS2#

62

DQS3#

135

DQS4#

152

DQS5#

169

DQS6#

186

DQS7#

12

DQS0

29

DQS1

47

DQS2

64

DQS3

137

DQS4

154

DQS5

171

DQS6

188

DQS7

116

ODT0

120

ODT1

126

VREF_CA

1

VREF_DQ

30

RESET#

203

VTT1

204

VTT2

DDR3-204P-25-GP

62.10017.K11

Height 5.2mm

NP1 NP2

RAS#

WE#

CAS# CS0#

CS1# CKE0

CKE1

CK0

CK0#

CK1

CK1#

DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7

SDA

SCL

EVENT#

VDDSPD

SA0 SA1

NC#1 NC#2

NC#/TEST

VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8

VDD9 VDD10 VDD11 VDD12 VDD13 VDD14 VDD15 VDD16 VDD17 VDD18

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

NP1 NP2

110 113 115

114 121

73 74

101 103

102 104

11 28 46 63 136 153 170 187

200 202

198 199 197

201 77

122 125

75 76 81 82 87 88 93 94 99 100 105 106 111 112 117 118 123 124

2 3 8 9 13 14 19 20 25 26 31 32 37 38 43 44 48 49 54 55 60 61 65 66 71 72 127 128 133 134 138 139 144 145 150 151 155 156 161 162 167 168 172 173 178 179 184 185 189 190 195 196 205 206

M_CLK_DDR0 M_CLK_DDR#0

M_CLK_DDR1 M_CLK_DDR#1

M_A_DM0 M_A_DM1 M_A_DM2 M_A_DM3 M_A_DM4 M_A_DM5 M_A_DM6 M_A_DM7

PCH_SMBDATA PCH_SMBCLK

SA0_DM1 SA1_DM1

+1.5V_SUS

2009/07/30 Change connect or to 62.10017 .K11

M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14 M_A_A15 M_A_BS2

M_A_BS0 M_A_BS1

M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63

M_A_DQS#0 M_A_DQS#1 M_A_DQS#2 M_A_DQS#3 M_A_DQS#4 M_A_DQS#5 M_A_DQS#6 M_A_DQS#7

M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6 M_A_DQS7

M_ODT010 M_ODT110

M_ODT0 M_ODT1

DDR3_DRAMRST#9,19

2

M_A_RAS# 10

M_A_WE# 10

M_A_CAS# 10 M_CS0# 10

M_CS1# 10

M_CKE0 10

M_CKE1 10 M_CLK_DDR0 10

M_CLK_DDR#0 10 M_CLK_DDR1 10

M_CLK_DDR#1 10

PCH_SMBDATA 7,19,23,40,64 PCH_SMBCLK 7,19,23,40,64

PM_EXTTS#0 9

M_CLK_DDR0 M_CLK_DDR#0 M_CLK_DDR1 M_CLK_DDR#1

2

1

SA0_DM1 SA1_DM1

R1802

R1802 10KR2J-3-GP

10KR2J-3-GP

SMBUS address:A0

Note: If SA0_DIM0 = 0, SA1_DIM0 = 0 SO-DIMMA SPD Address is 0xA0 If SA0_DIM0 = 1, SA1_DIM0 = 0 SO-DIMMA SPD Address is 0xA2 If SA0_DIM0 = 0, SA1_DIM0 = 1 SO-DIMMA SPD Address is 0xA4

+3.3V_RUN

C1807

SC2D2U10V3KX-1GPDYC1807

SC2D2U10V3KX-1GP

C1806

SCD1U16V2KX-3GP

C1806

SCD1U16V2KX-3GP

12

DY

put near connector

12

C1821

Do Not Stuff

12

C1819

C1820

C1818

Do Not Stuff

UMA

Title

Size Document Number Rev

Custom

Date: Sheet of

C1818

Do Not Stuff

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

DDRIII-SODIMM SLOT1

Vostro Calpella

1

12

R1801

R1801 10KR2J-3-GP

10KR2J-3-GP

SA

18 90Tuesday, September 08, 2009

SA

5

SSID = MEMORY

M_B_DQS#[7..0]10

D D

C C

B B

2009/08/12 Follow Intel "425302_Calpella_S3PowerReduction_WhitePaper_Rev0.9. pdf" document.

A A

M_B_DQ[63..0]10 M_B_DM[7..0]10 M_B_DQS[7..0]10 M_B_A[15..0]10

+1.5V_SUS

C1919

12

+0.75V_DDR_VTT

C1908

12

+1.5V_SUS

C1976

12

+V_DDR_REF

C1910

C1910 SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

5

SC10U6D3V5MX-3GP

SC1U10V2KX-1GP

SCD1U10V2KX-4GP

12

ARD

12

Layout Note: Place near DM2

C1905

SC10U6D3V5MX-3GP

C1905

SC10U6D3V5MX-3GP

C1911

SC10U6D3V5MX-3GP

C1911

SC10U6D3V5MX-3GP

12

Layout Note: Put close to VTT1,VTT2.

C1909

SC1U10V2KX-1GP

C1909

SC1U10V2KX-1GP

C1917

SC1U10V2KX-1GP

C1917

SC1U10V2KX-1GP

12

C1977

SCD1U10V2KX-4GP

C1977

SCD1U10V2KX-4GP

C1978

SCD1U10V2KX-4GP

C1978

SCD1U10V2KX-4GP

12

R1905

R1905 0R2J-2-GP

0R2J-2-GP

12

C1912

C1912 SC2D2U10V3KX-1GP

SC2D2U10V3KX-1GP

C1916

SC10U6D3V5MX-3GP

C1916

SC10U6D3V5MX-3GP

12

C1918

SC1U10V2KX-1GP

C1918

SC1U10V2KX-1GP

12

C1979

C1979 SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

12

C1907

C1907 SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

M_VREF_DQ_DIMM1 11

C1913

SC10U6D3V5MX-3GP

C1913

SC10U6D3V5MX-3GP

+V_DDR_REF

12

C1920

SC10U6D3V5MX-3GP

C1920

SC10U6D3V5MX-3GP

12

4

TC1903

TC1903 ST330U2D5VBM-1-GP

ST330U2D5VBM-1-GP

12

C1914

C1914 SC2D2U10V3KX-1GP

SC2D2U10V3KX-1GP

4

M_B_BS210 M_B_BS010

M_B_BS110

M_ODT210

M_ODT310

M_VREF_DQ_DIMM1

DDR3_DRAMRST#9,18

M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14 M_B_A15 M_B_BS2

M_B_BS0 M_B_BS1

M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63

M_B_DQS#0 M_B_DQS#1 M_B_DQS#2 M_B_DQS#3 M_B_DQS#4 M_B_DQS#5 M_B_DQS#6 M_B_DQS#7

M_B_DQS0 M_B_DQS1 M_B_DQS2 M_B_DQS3 M_B_DQS4 M_B_DQS5 M_B_DQS6 M_B_DQS7

M_ODT2 M_ODT3

+0.75V_DDR_VTT

3

DM2

98

A0

97

A1

96

A2

95

A3

92

A4

91

A5

90

A6

86

A7

89

A8

85

A9

107

A10/AP

84

A11

83

A12

119

A13

80

A14

78

A15

79

A16/BA2

109

BA0

108

BA1

5

DQ0

7

DQ1

15

DQ2

17

DQ3

4

DQ4

6

DQ5

16

DQ6

18

DQ7

21

DQ8

23

DQ9

33

DQ10

35

DQ11

22

DQ12

24

DQ13

34

DQ14

36

DQ15

39

DQ16

41

DQ17

51

DQ18

53

DQ19

40

DQ20

42

DQ21

50

DQ22

52

DQ23

57

DQ24

59

DQ25

67

DQ26

69

DQ27

56

DQ28

58

DQ29

68

DQ30

70

DQ31

129

DQ32

131

DQ33

141

DQ34

143

DQ35

130

DQ36

132

DQ37

140

DQ38

142

DQ39

147

DQ40

149

DQ41

157

DQ42

159

DQ43

146

DQ44

148

DQ45

158

DQ46

160

DQ47

163

DQ48

165

DQ49

175

DQ50

177

DQ51

164

DQ52

166

DQ53

174

DQ54

176

DQ55

181

DQ56

183

DQ57

191

DQ58

193

DQ59

180

DQ60

182

DQ61

192

DQ62

194

DQ63

10

DQS0#

27

DQS1#

45

DQS2#

62

DQS3#

135

DQS4#

152

DQS5#

169

DQS6#

186

DQS7#

12

DQS0

29

DQS1

47

DQS2

64

DQS3

137

DQS4

154

DQS5

171

DQS6

188

DQS7

116

ODT0

120

ODT1

126

VREF_CA

1

VREF_DQ

30

RESET#

203

VTT1

204

VTT2

DDR3-204P-24-GP

62.10017.K01

VDDSPD

NC#/TEST

Height 9.2mm

NP1 NP2

RAS#

WE#

CAS#

CS0# CS1#

CKE0 CKE1

CK0

CK0#

CK1

CK1#

DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7

SDA SCL

EVENT#

SA0 SA1

NC#1 NC#2

VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8

VDD9 VDD10 VDD11 VDD12 VDD13 VDD14 VDD15 VDD16 VDD17 VDD18

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

NP1 NP2

110 113 115

114 121

73 74

101 103

102 104

11 28 46 63 136 153 170 187

200 202

198 199 197

201 77

122 125

75 76 81 82 87 88 93 94 99 100 105 106 111 112 117 118 123 124

2 3 8 9 13 14 19 20 25 26 31 32 37 38 43 44 48 49 54 55 60 61 65 66 71 72 127 128 133 134 138 139 144 145 150 151 155 156 161 162 167 168 172 173 178 179 184 185 189 190 195 196 205 206

M_CLK_DDR2 M_CLK_DDR#2

M_CLK_DDR3 M_CLK_DDR#3

M_B_DM0 M_B_DM1 M_B_DM2 M_B_DM3 M_B_DM4 M_B_DM5 M_B_DM6 M_B_DM7

PCH_SMBDATA PCH_SMBCLK

SA0_DM2 SA1_DM2

+1.5V_SUS

2009/07/30 Change connect or to 62.10017 .K01

2

M_B_RAS# 10

M_B_WE# 10

M_B_CAS# 10 M_CS2# 10

M_CS3# 10 M_CKE2 10

M_CKE3 10 M_CLK_DDR2 10

M_CLK_DDR#2 10 M_CLK_DDR3 10

M_CLK_DDR#3 10

PCH_SMBDATA 7,18,23,40,64 PCH_SMBCLK 7,18,23,40,64

PM_EXTTS#1 9

put near connector

M_CLK_DDR2 M_CLK_DDR#2 M_CLK_DDR3 M_CLK_DDR#3

12

C1901

2

1

+3.3V_RUN

12

DY

12

R1904

R1904 10KR2J-3-GP

10KR2J-3-GP

12

R1902

R1902 10KR2J-3-GP

10KR2J-3-GP

DY

R1903

R1903 10KR2J-3-GP

10KR2J-3-GP

SA1_DM2 SA0_DM2

R1901

R1901 10KR2J-3-GP

10KR2J-3-GP

SMBUS address:A4

+3.3V_RUN

C1906

SCD1U16V2KX-3GP

C1906

SCD1U16V2KX-3GP12C1921

SC2D2U10V3KX-1GPDYC1921

12

C1904

Do Not Stuff

UMA

Title

Size Document Number Rev

Custom

Date: Sheet of

12

C1902

Do Not Stuff

DDRIII-SODIMM SLOT2

Vostro Calpella

SC2D2U10V3KX-1GP

DY

C1903

Do Not Stuff

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

1

SA

19 90Tuesday, September 08, 2009

SA

5

4

3

2

1

R2011

R2011 0R2J-2-GP

0R2J-2-GP

1

CRT_IREF

R2004

R2004 1KR2D-1-GP

1KR2D-1-GP

LCDVDD_EN_PCH

PANEL_BKEN_PCHR LCDVDD_EN_PCH

LCTLA_CLK LCTLB_DATA

4

LIBG TP_LVDS_VBG

D D

PANEL_BKEN_PCH37 LCDVDD_EN_PCH54

LBKLT_CTL_PCH54 L_DDC_CLK54

L_DDC_DATA54

+3.3V_RUN

12

R2002

Place near PCH

2K37R2F-GP

MCH_LVDSA_CLK#74 MCH_LVDSA_CLK74

C C

50 ohm trace to filter

MCH_BLUE74 MCH_GREEN74

B B

MCH_RED74

MCH_BLUE MCH_GREEN MCH_RED

37.5 ohm trace to 150R resistor

1 2

MCH_LVDSA_DAT0#74 MCH_LVDSA_DAT1#74 MCH_LVDSA_DAT2#74

MCH_LVDSA_DAT074 MCH_LVDSA_DAT174 MCH_LVDSA_DAT274

MCH_LVDSB_CLK#74 MCH_LVDSB_CLK74

MCH_LVDSB_DAT0#74 MCH_LVDSB_DAT1#74 MCH_LVDSB_DAT2#74

MCH_LVDSB_DAT074 MCH_LVDSB_DAT174 MCH_LVDSB_DAT274

R2007

150R2F-1-GP

R2007

150R2F-1-GP

R2005

150R2F-1-GP

R2005

150R2F-1-GP

R2006

150R2F-1-GP

R2006

150R2F-1-GP

1 2

GMCH_HSYNC74 GMCH_VSYNC74

Place near PCH

1 2

RN2001

2 3 1

SRN10KJ-5-GP

TP2001Do Not Stuff TP2001Do Not Stuff

GMCH_DDCCLK55 GMCH_DDCDATA55

1 2

DY

R2003

R2003 100KR2J-1-GP

100KR2J-1-GP

U2001D

T48

L_BKLTEN

T47

L_VDD_EN

Y48

L_BKLTCTL

AB48

L_DDC_CLK

Y45

L_DDC_DATA

AB46

L_CTRL_CLK

V48

L_CTRL_DATA

AP39

LVD_IBG

AP41

LVD_VBG

AT43

LVD_VREFH

AT42

LVD_VREFL

AV53

LVDSA_CLK#

AV51

LVDSA_CLK

BB47

LVDSA_DATA#0

BA52

LVDSA_DATA#1

AY48

LVDSA_DATA#2

AV47

LVDSA_DATA#3

BB48

LVDSA_DATA0

BA50

LVDSA_DATA1

AY49

LVDSA_DATA2

AV48

LVDSA_DATA3

AP48

LVDSB_CLK#

AP47

LVDSB_CLK

AY53

LVDSB_DATA#0

AT49

LVDSB_DATA#1

AU52

LVDSB_DATA#2

AT53

LVDSB_DATA#3

AY51

LVDSB_DATA0

AT48

LVDSB_DATA1

AU50

LVDSB_DATA2

AT51

LVDSB_DATA3

AA52

CRT_BLUE

AB53

CRT_GREEN

AD53

CRT_RED

V51

CRT_DDC_CLK

V53

CRT_DDC_DATA

Y53

CRT_HSYNC

Y51

CRT_VSYNC

AD48

DAC_IREF

AB51

CRT_IRTN

IBEXPEAK-M-GP-NF

4 OF 10

DDPB_0N DDPB_0P DDPB_1N DDPB_1P DDPB_2N DDPB_2P DDPB_3N DDPB_3P

DDPC_0N

DDPC_0P

DDPC_1N

DDPC_1P

DDPC_2N

DDPC_2P

DDPC_3N

DDPC_3P

DDPD_0N

DDPD_0P

DDPD_1N

DDPD_1P

DDPD_2N

DDPD_2P

DDPD_3N

DDPD_3P

BJ46 BG46

BJ48 BG48

BF45 BH45

T51 T53

BG44 BJ44 AU38

BD42 BC42 BJ42 BG42 BB40 BA40 AW38 BA38

Y49 AB49

BE44 BD44 AV40

BE40 BD40 BF41 BH41 BD38 BC38 BB36 BA36

U50 U52

BC46 BD46 AT38

BJ40 BG40 BJ38 BG38 BF37 BH37 BE36 BD36

SDVO_TVCLKINN SDVO_TVCLKINP

SDVO_STALLN

SDVO_STALLP

SDVO_INTN SDVO_INTP

SDVO_CTRLCLK

SDVO_CTRLDATA

DDPB_AUXN DDPB_AUXP

DDPB_HPD

LVDS

DDPC_CTRLCLK

DDPC_CTRLDATA

DDPC_AUXN DDPC_AUXP

DDPC_HPD

Digital Display Interface

DDPD_CTRLCLK

DDPD_CTRLDATA

DDPD_AUXN DDPD_AUXP

DDPD_HPD

CRT

HDMI_DATA2-_C HDMI_DATA2+_C HDMI_DATA1-_C HDMI_DATA1+_C HDMI_DATA0-_C HDMI_DATA0+_C HDMI_CLK-_C HDMI_CLK+_C

SDVO_CLK 57,75 SDVO_DAT 57,75

HDMI_HP_DET 21,57,75 HDMI_DATA2-_C 75

HDMI_DATA2+_C 75 HDMI_DATA1-_C 75 HDMI_DATA1+_C 75 HDMI_DATA0-_C 75 HDMI_DATA0+_C 75 HDMI_CLK-_C 75 HDMI_CLK+_C 75

A A

5

4

3

2

UMA

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

ize Document Number Rev

Size Document Number Rev

S

Date: Sheet of

PCH (LVDS/CRT/DDI)

Taipei Hsien 221, Taiwan, R.O.C.

Vostro Calpella

20 90Tuesday, September 08, 2009

1

SA

5

RN2101

PCI_SERR# PCI_REQ1# PCI_FRAME# DGPU_SEL_BUF_#

+3.3V_RUN

PCI_REQ3#

D D

+3.3V_RUN

C C

INT_PIRQB# PCI_REQ0# PCI_PERR#

+3.3V_RUN

R2107

10KR2J-3-GP

R2113

10KR2J-3-GP

RN2101

1 2 3 4 5 6

SRN8K2J-2-GP-U

RN2102

1 2 3 4 5 6

SRN8K2J-2-GP-U

RN2103

1 2 3 4 5

SRN10KJ-7GP

12

UMA

DGPU_SELECT#

12

DIS

10 9 8 7

PCH_GPIO3

8

INT_PIRQE#

7

HDMI_HP_DET_R

6

PCH_GPIO5

R2117

10KR2J-3-GP

INT_PIRQC# PCI_STOP# PCI_IRDY# INT_PIRQD#

INT_PIRQA# PCI_PLOCK# PCI_TRDY# PCI_DEVSEL#

+3.3V_RUN

12

UMA

12

DIS

+3.3V_RUN

R2114

R2114 10KR2J-3-GP

10KR2J-3-GP

DGPU_PW M_SELECT#

C2102

SCD1U16V2KX-3GP

PLT_RST#9,37,64,70,76,77,80

C2104

SCD1U16V2KX-3GP

DGPU_SELECT#54,74

DGPU_PW M_SELECT#54

BOOT BIOS Strap

PCI_GNT#1 BOOT BIOS LocationPCI_GNT#0

B B

0 0 LPC 0 1 Reserved

01 11

A16 swap override Strap/Top-Block Swap Override jumper

A A

PCI_GNT#3 Low = A16 swap

PCI_GNT3#

override/Top-Block

Swap Override enabled

High = Default

R2109

1 2

DY

4K7R2J-2-GP

5

PCI SPI(Default)

PLTRST#_PCH

12

C2103

C2103 SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

DY

12

4

+3.3V_RUN

12

DY

+3.3V_RUN

12

DY

PCLK_FW H70 CLK_PCI_FB23 PCLK_KBC37 PCLK_TPM76

4

3

U2001E

H40

AD0

N34

AD1

C44

U2101

5

VCC

4

Y

74LVC1G08GW-1-GP

1 2

R2104 0R2J-2-GP

C2101

C2101 SC220P50V2KX-3GP

SC220P50V2KX-3GP

U2103

5

VCC

4

Y

74LVC1G08GW-1-GP

1 2

R2115 0R2J-2-GP

C2113

C2113 SC220P50V2KX-3GP

SC220P50V2KX-3GP

DGPU_PW M_SELECT#

Calpella Platform Design Guide Revision 1.6

1

B

PLTRST#_PCH

2

A

3

GND

DY

1

B

DGPU_SEL_BUF_#

2

A

DY

3

GND

DY

R2116

R2116 0R2J-2-GP

0R2J-2-GP

HDD_FALL_INT140 HDMI_HP_DET20,57,75

Do Not Stuff

R2110 22R2J-2-GP

1 2

DY

R2108 22R2J-2-GPR2108 22R2J-2-GP

1 2

R2111 22R2J-2-GPR2111 22R2J-2-GP

1 2

R2112 22R2J-2-GPR2112 22R2J-2-GP

1 2

TP2116

TP2116 Do Not Stuff

Do Not Stuff

1 2

DY

R2121

R2121 0R2J-2-GP

0R2J-2-GP

1 2

R2122

1 2

DY

0R2J-2-GP

TP2108

TP2115Do Not Stuff TP2115Do Not Stuff

INT_PIRQA# INT_PIRQB# INT_PIRQC# INT_PIRQD#

PCI_REQ0# PCI_REQ1#

DGPU_SEL_BUF_#

PCI_REQ3# PCI_GNT0#

1

DGPU_PW M_SELECT#_R

PCI_GNT3# INT_PIRQE#

PCH_GPIO3 HDMI_HP_DET_R PCH_GPIO5

PCIRST#

1

PCI_SERR# PCI_PERR#

PCI_IRDY# PCI_DEVSEL#

PCI_FRAME# PCI_PLOCK# PCI_STOP#

PCI_TRDY# PCH_PME#

1

PLTRST#_PCH PCLK_FW H_R

CLK_PCI_FB_R PCLK_KBC_R PCLK_TPM_R

Table 111. Overcurrent Pin Example Configuration

These OC7# pins are not used for USB overcurrent protection and should be configured as GPIOs. The unused USB ports can be left as no connect.

+3.3V_ALW

3

AD2

A38

AD3

C36

AD4

J34

AD5

A40

AD6

D45

AD7

E36

AD8

H48

AD9

E40

AD10

C40

AD11

M48

AD12

M45

AD13

F53

AD14

M40

AD15

M43

AD16

J36

AD17

K48

AD18

F40

AD19

C42

AD20

K46

AD21

M51

AD22

J52

AD23

K51

AD24

L34

AD25

F42

AD26

J40

AD27

G46

AD28

F44

AD29

M47

AD30

H36

AD31

J50

C/BE0#

G42

C/BE1#

H47

C/BE2#

G34

C/BE3#

G38

PIRQA#

H51

PIRQB#

B37

PIRQC#

A44

PIRQD#

F51

REQ0#

A46

REQ1#/GPIO50

B45

REQ2#/GPIO52

M53

REQ3#/GPIO54

F48

GNT0#

K45

GNT1#/GPIO51

F36

GNT2#/GPIO53

H53

GNT3#/GPIO55

B41

PIRQE#/GPIO2

K53

PIRQF#/GPIO3

A36

PIRQG#/GPIO4

A48

PIRQH#/GPIO5

K6

PCIRST#

E44

SERR#

E50

PERR#

A42

IRDY#

H44

PAR

F46

DEVSEL#

C46

FRAME#

D49

PLOCK#

D41

STOP#

C48

TRDY#

M7

PME#

D5

PLTRST#

N52

CLKOUT_PCI0

P53

CLKOUT_PCI1

P46

CLKOUT_PCI2

P51

CLKOUT_PCI3

P48

CLKOUT_PCI4

IBEXPEAK-M-GP-NF

USB_OC#4_5

USB_OC#8_9

USB_OC#6_7

USB_OC#12_13 USB_OC#0_1

PCI

RP2101

1 2 3 4 5 6

SRN10KJ-L3-GP

NV_DQ0/NV_IO0 NV_DQ1/NV_IO1 NV_DQ2/NV_IO2 NV_DQ3/NV_IO3 NV_DQ4/NV_IO4 NV_DQ5/NV_IO5 NV_DQ6/NV_IO6 NV_DQ7/NV_IO7 NV_DQ8/NV_IO8

NV_DQ9/NV_IO9 NV_DQ10/NV_IO10 NV_DQ11/NV_IO11

NVRAM

NV_DQ12/NV_IO12 NV_DQ13/NV_IO13 NV_DQ14/NV_IO14 NV_DQ15/NV_IO15

NV_RCOMP

NV_WR#0_RE# NV_WR#1_RE#

NV_WE#_CK0 NV_WE#_CK1

USB

USBRBIAS#

OC0#/GPIO59 OC1#/GPIO40 OC2#/GPIO41 OC3#/GPIO42 OC4#/GPIO43

OC5#/GPIO9 OC6#/GPIO10 OC7#/GPIO14

Page 233

10

USB_OC#10_11

9

USB_OC#2_3

8 7

PCH_OC7#

5 OF 10

NV_CE#0 NV_CE#1 NV_CE#2 NV_CE#3

NV_DQS0 NV_DQS1

NV_ALE NV_CLE

NV_RB#

USBP0N USBP0P USBP1N USBP1P USBP2N USBP2P USBP3N USBP3P USBP4N USBP4P USBP5N USBP5P USBP6N USBP6P USBP7N USBP7P USBP8N USBP8P USBP9N USBP9P

USBP10N

USBP10P

USBP11N

USBP11P

USBP12N

USBP12P

USBP13N

USBP13P

USBRBIAS

2

AY9 BD1 AP15 BD8

AV9 BG8

AP7 AP6 AT6 AT9 BB1 AV6 BB3 BA4 BE4 BB6 BD6 BB7 BC8 BJ8 BJ6 BG6

BD3 AY6

AU2 AV7 AY8

AY5 AV11

BF5

H18 J18 A18 C18 N20 P20 J20 L20 F20 G20

TP_USB_PN5

A20

TP_USB_PP5

C20

TP_USB_PN6

M22

TP_USB_PP6

N22

TP_USB_PN7

B21

TP_USB_PP7

D21 H22 J22

TP_USB_PN9

E22

TP_USB_PP9

F22 A22 C22 G24 H24 L24 M24 A24 C24

B25 D25

N16 J16 F16 L16 E14 G16 F12 T15

+3.3V_ALW

2

TP_NV_ALE TP_NV_CLE

TP_NV_RCOMP

USB_RBIAS_PN

USB_OC#0_1 USB_OC#2_3 USB_OC#4_5 USB_OC#6_7 USB_OC#8_9 USB_OC#10_11 USB_OC#12_13 PCH_OC7#

1

TP2117Do Not StuffTP2117Do Not Stuff

1

TP2119Do Not StuffTP2119Do Not Stuff

1

TP2118Do Not StuffTP2118Do Not Stuff

1

Add USB Port for right side board 2009/07/13

USB_PN0 76 USB_PP0 76 USB_PN1 76 USB_PP1 76 USB_PN2 63 USB_PP2 63 USB_PN3 63 USB_PP3 63 USB_PN4 63

USB_PP4 63

TP2129TP2129 TP2130TP2130 TP2128TP2128 TP2127TP2127 TP2126TP2126 TP2125TP2125

USB_PN8 77

USB_PP8 77

TP2131TP2131 TP2132TP2132

USB_PN10 78

USB_PP10 78

USB_PN11 73

USB_PP11 73

USB_PN12 77

USB_PP12 77

USB_PN13 64

USB_PP13 64

1 2

R2106

R2106 22D6R2F-L1-GP

22D6R2F-L1-GP

UMA

Title

ize Document Number Rev

Size Document Number Rev

S

Date: Sheet of

Pair

0 1 2 3 4 5 6 7 8 9 10 11 12 13

USB_OC#0_1 76 USB_OC#2_3 63 USB_OC#4_5 63

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

PCH (PCI/USB/NVRAM)

Vostro Calpella

USB

Device

USB1 > LAN BOARD USB4 > LAN BOARD USB2 > M/B USB3 > M/B USB for ESATA

RESERVED

(Not available for HM55)

RESERVED

(Not available for HM55)

BlUETOOTH

RESERVED

Biometric CAMERA New Card WLAN

21 90Tuesday, September 08, 2009

1

SA

5

DMI_CTX_PRXN08 DMI_CTX_PRXN18 DMI_CTX_PRXN28 DMI_CTX_PRXN38

DMI_CTX_PRXP08

D D

+1.05V_PCH

C C

B B

XDP_DBRESET#9

R2207 0R2J-2-GPR2207 0R2J-2-GP

PM_PWROK37

PM_DRAM_PWRGD9

RSMRST#_KBC37 PM_SLP_S4# 37,50,77

SUS_PW R_DN_ACK37

PM_PWRBTN#_R9

PM_PWRBTN#37

AC_PRESENT_EC37

1 2

R2208

1 2

R2209 10KR2J-3-GPR2209 10KR2J-3-GP

1 2

PM_DRAM_PWRGD

1 2

R2213 0R2J-2-GPR2213 0R2J-2-GP

AC_PRESENT_EC

DMI_CTX_PRXP18 DMI_CTX_PRXP28 DMI_CTX_PRXP38

DMI_PTX_CRXN08 DMI_PTX_CRXN18 DMI_PTX_CRXN28 DMI_PTX_CRXN38

DMI_PTX_CRXP08 DMI_PTX_CRXP18 DMI_PTX_CRXP28 DMI_PTX_CRXP38

R2204

1 2

49D9R2F-GP

R2210 0R2J-2-GPR2210 0R2J-2-GP

R2218 0R2J-2-GPR2218 0R2J-2-GP

DMI_IRCOMP_R

10KR2J-3-GP

1 2

R2216 0R2J-2-GPR2216 0R2J-2-GP

+3.3V_RUN

12

R2205

R2205 10KR2J-3-GP

10KR2J-3-GP

XDP_DBRESET#

PM_PWRGD

LAN_RST#1

PM_RSMRST#_R

SUS_PW R_ACK

PM_PWRBTN#_R

AC_PRESENT

PM_BATLOW#_R

PM_RI#

4

U2001C

BC24

DMI0RXN

BJ22

DMI1RXN

AW20

DMI2RXN

BJ20

DMI3RXN

BD24

DMI0RXP

BG22

DMI1RXP

BA20

DMI2RXP

BG20

DMI3RXP

BE22

DMI0TXN

BF21

DMI1TXN

BD20

DMI2TXN

BE18

DMI3TXN

BD22

DMI0TXP

BH21

DMI1TXP

BC20

DMI2TXP

BD18

DMI3TXP

BH25

DMI_ZCOMP

BF25

DMI_IRCOMP

T6

SYS_RESET#

M6

SYS_PWROK

B17

PWROK

K5

MEPWROK

A10

LAN_RST#

D9

DRAMPWROK

C16

RSMRST#

M1

SUS_PWR_DN_ACK/GPIO30

P5

PWRBTN#

P7

ACPRESENT/GPIO31

A6

BATLOW#/GPIO72

F14

RI#

IBEXPEAK-M-GP-NF

DMI

FDI

DMI

FDI

CLKRUN#/GPIO32

SUS_STAT#/GPIO61

SUSCLK/GPIO62

SLP_S5#/GPIO63

System Power Management

SLP_LAN#/GPIO29

3 OF 10

FDI_RXN0 FDI_RXN1 FDI_RXN2 FDI_RXN3 FDI_RXN4 FDI_RXN5 FDI_RXN6 FDI_RXN7

FDI_RXP0 FDI_RXP1 FDI_RXP2 FDI_RXP3 FDI_RXP4 FDI_RXP5 FDI_RXP6 FDI_RXP7

FDI_INT FDI_FSYNC0 FDI_FSYNC1 FDI_LSYNC0 FDI_LSYNC1

WAKE#

SLP_S4#

SLP_S3#

SLP_M#

TP23

PMSYNCH

3

FDI_TXN0

BA18 BH17 BD16 BJ16 BA16 BE14 BA14 BC12

BB18 BF17 BC16 BG16 AW16 BD14 BB14 BD12

BJ14 BF13 BH13 BJ12 BG14

J12

Y1

P8

F3

E4

H7

P12

K8

N2

BJ10

F6

FDI_TXN1 FDI_TXN2 FDI_TXN3 FDI_TXN4 FDI_TXN5 FDI_TXN6 FDI_TXN7

FDI_TXP0 FDI_TXP1 FDI_TXP2 FDI_TXP3 FDI_TXP4 FDI_TXP5 FDI_TXP6 FDI_TXP7

FDI_INT FDI_FSYNC0 FDI_FSYNC1 FDI_LSYNC0 FDI_LSYNC1

PM_CLKRUN#

TP_SUS_STAT#

PCH_SUSCLK

PCH_SLP_S5#

PM_SLP_S4#_R

PM_SLP_S3#_R

SIO_SLP_M#_R

PM_SLP_DSW#

H_PM_SYNC

FDI_TXN0 8 FDI_TXN1 8 FDI_TXN2 8 FDI_TXN3 8 FDI_TXN4 8 FDI_TXN5 8 FDI_TXN6 8 FDI_TXN7 8

FDI_TXP0 8 FDI_TXP1 8 FDI_TXP2 8 FDI_TXP3 8 FDI_TXP4 8 FDI_TXP5 8 FDI_TXP6 8 FDI_TXP7 8

FDI_INT 8 FDI_FSYNC0 8 FDI_FSYNC1 8 FDI_LSYNC0 8 FDI_LSYNC1 8

1

TP2205 Do Not StuffTP2205 Do Not Stuff

1

TP2202Do Not StuffTP2202Do Not Stuff

1 2

R2211 0R2J-2-GPR2211 0R2J-2-GP

1 2

R2212 0R2J-2-GPR2212 0R2J-2-GP

1

TP2203Do Not StuffTP2203Do Not Stuff

1

TP2204Do Not StuffTP2204Do Not Stuff

PCIE_WAKE# 76,77

PM_CLKRUN# 37

2

1 2

R2219 0R2J-2-GPR2219 0R2J-2-GP

1 2

R2220 0R2J-2-GPR2220 0R2J-2-GP

PM_SLP_S3# 37,42,50,51,52,77,86

H_PM_SYNC 9

PM_RI# SUS_PW R_ACK

PM_BATLOW#_R PCIE_WAKE# AC_PRESENT_EC

PM_RSMRST#_R

PCH_SUSCLK_2102 39

PCH_SUSCLK_KBC 37

1

RN2201

RN2201 SRN10KJ-5-GP

SRN10KJ-5-GP

1

4

23

R2201 10KR2J-3-GPR2201 10KR2J-3-GP

1 2

R2202 1KR2J-1-GPR2202 1KR2J-1-GP

1 2

R2217 10KR2J-3-GPR2217 10KR2J-3-GP

1 2

R2203 10KR2J-3-GPR2203 10KR2J-3-GP

1 2

+3.3V_ALW

+3.3V_RUN

R2214

R2214 10KR2J-3-GP

PM_CLKRUN#

12

R2215

R2215 10KR2J-3-GP

A A

Option to " Disable " clkrun. Pulling it down will keep the clks running.

5

10KR2J-3-GP

DY

4

10KR2J-3-GP

1 2

UMA

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

ize Document Number Rev

Size Document Number Rev

S

Date: Sheet of

3

2

Date: Sheet of

PCH (DM I/FDI/PM)

Taipei Hsien 221, Taiwan, R.O.C.

Vostro Calpella

22 90Tuesday, September 08, 2009

1

SA

5

4

3

2

1

+3.3V_ALW+3.3V_ALW

2 OF 10

U2001B

PCIE_IRXN1_CTXN177 PCIE_IRXP1_CTXP177

PCIE_ITXN1_CRXN177 PCIE_ITXP1_CRXP177

D D

PCIE_IRXN2_MTXN264

PCIE_IRXP2_MTXP264 PCIE_ITXN2_MRXN264 PCIE_ITXP2_MRXP264

PCIE_IRXN3_LRTXN376 PCIE_IRXP3_LRTXP376

PCIE_ITXN3_LRXN376 PCIE_ITXP3_LRXP376

PCIE_IRXN5_NTXN577

PCIE_IRXP5_NTXP577 PCIE_ITXN5_NRXN577 PCIE_ITXP5_NRXP577

C2306 SCD1U16V2KX-3GPC2306 SCD1U16V2KX-3GP

12

C2305 SCD1U16V2KX-3GPC2305 SCD1U16V2KX-3GP

12

C2318 SCD1U16V2KX-3GPC2318 SCD1U16V2KX-3GP

12

C2310 SCD1U16V2KX-3GPC2310 SCD1U16V2KX-3GP

12

C2303 SCD1U16V2KX-3GPC2303 SCD1U16V2KX-3GP

12

C2309 SCD1U16V2KX-3GPC2309 SCD1U16V2KX-3GP

12

C2308 SCD1U16V2KX-3GPC2308 SCD1U16V2KX-3GP

12

C2304 SCD1U16V2KX-3GPC2304 SCD1U16V2KX-3GP

12

PCIE_ITXN1_CRXN1_C PCIE_ITXP1_CRXP1_C

PCIE_ITXN2_MRXN2_C PCIE_ITXP2_MRXP2_C

PCIE_ITXN3_LRXN3_C PCIE_ITXP3_LRXP3_C

PCIE_ITXN5_NRXN5_C PCIE_ITXP5_NRXP5_C

(Not available for HM55)

C C

PCIECLKRQ{0,3,4,5,6,7}# should have a 10K pull-up to +3.3V_ALW. PCIECLKRQ{1,2} should have a 10K pull-up to +3.3_RUN

RN2311

RN2307

8 7 6

SRN10KJ-7GP

RN2308

SRN10KJ-5-GP

5

RN2311 SRN0J-6-GP

SRN0J-6-GP

RN2305

RN2305 SRN0J-6-GP

SRN0J-6-GP

RN2304

RN2304 SRN0J-6-GP

SRN0J-6-GP

RN2310

RN2310 SRN0J-6-GP

SRN0J-6-GP

4

CLK_PCIE_NEW#77 CLK_PCIE_NEW77

NEWCARD_CLKREQ#77

CLK_PCIE_MINI1#64 CLK_PCIE_MINI164

MINI1_CLKREQ#64

CLK_PCIE_LAN#76 CLK_PCIE_LAN76

B B

A A

CLKREQ#_LAN76

CLK_PCIE_R5U230#77 CLK_PCIE_R5U23077

PCIE_CLK_RQ5#77

+3.3V_ALW

+3.3V_RUN

1 2 3

(Not available for HM55)

1 2 3

2 3 1

1 2 3

PCIE_CLK_RQ5#

1

PEG_B_CLKRQ#

2

CLKREQ#_LAN

3

PCIE_CLK_RQ4#

45

NEWCARD_CLKREQ# MINI1_CLKREQ#

CLK_PCIE_NEW1#

4

CLK_PCIE_NEW1 NEWCARD_CLKREQ#

CLK_PCIE_MINI1_1# CLK_PCIE_MINI1_1

4

MINI1_CLKREQ#

CLK_PCIE_LAN1#

4

CLK_PCIE_LAN1 CLKREQ#_LAN

PCIE_CLK_RQ4#

CLK_PCIE_R5U230_1#

4

CLK_PCIE_R5U230_1 PCIE_CLK_RQ5#

PEG_B_CLKRQ#

BG30

PERN1

BJ30

PERP1

BF29

PETN1

BH29

PETP1

AW30

PERN2

BA30

PERP2

BC30

PETN2

BD30

PETP2

AU30

PERN3

AT30

PERP3

AU32

PETN3

AV32

PETP3

BA32

PERN4

BB32

PERP4

BD32

PETN4

BE32

PETP4

BF33

PERN5

BH33

PERP5

BG32

PETN5

BJ32

PETP5

BA34

PERN6

AW34

PERP6

BC34

PETN6

BD34

PETP6

AT34

PERN7

AU34

PERP7

AU36

PETN7

AV36

PETP7

BG34

PERN8

BJ34

PERP8

BG36

PETN8

BJ36

PETP8

AK48

CLKOUT_PCIE0N

AK47

CLKOUT_PCIE0P

P9

PCIECLKRQ0#/GPIO73

AM43

CLKOUT_PCIE1N

AM45

CLKOUT_PCIE1P

U4

PCIECLKRQ1#/GPIO18

AM47

CLKOUT_PCIE2N

AM48

CLKOUT_PCIE2P

N4

PCIECLKRQ2#/GPIO20

AH42

CLKOUT_PCIE3N

AH41

CLKOUT_PCIE3P

A8

PCIECLKRQ3#/GPIO25

AM51

CLKOUT_PCIE4N

AM53

CLKOUT_PCIE4P

M9

PCIECLKRQ4#/GPIO26

AJ50

CLKOUT_PCIE5N

AJ52

CLKOUT_PCIE5P

H6

PCIECLKRQ5#/GPIO44

AK53

CLKOUT_PEG_B_N

AK51

CLKOUT_PEG_B_P

P13

PEG_B_CLKRQ#/GPIO56

IBEXPEAK-M-GP-NF

4

Card Reader

WLAN

LAN

New Card

SMBus

PCI-E*

Link

Controller

PEG_A_CLKRQ#/GPIO47

PEG

CLKOUT_DP_N/CLKOUT_BCLK1_N

CLKOUT_DP_P/CLKOUT_BCLK1_P

From CLK BUFFER

CLKIN_SATA_N/CKSSCD_N CLKIN_SATA_P/CKSSCD_P

Clock Flex

CLKIN_PCILOOPBACK

CLKOUTFLEX0/GPIO64

CLKOUTFLEX1/GPIO65

CLKOUTFLEX2/GPIO66

CLKOUTFLEX3/GPIO67

2 OF 10

SMBALERT#/GPIO11

SMBCLK

SMBDATA

SML0ALERT#/GPIO60

SML0CLK

SML0DATA

SML1ALERT#/GPIO74

SML1CLK/GPIO58

SML1DATA/GPIO75

CL_CLK1 CL_DATA1 CL_RST1#

CLKOUT_PEG_A_N CLKOUT_PEG_A_P

CLKOUT_DMI_N CLKOUT_DMI_P

CLKIN_DMI_N CLKIN_DMI_P

CLKIN_BCLK_N CLKIN_BCLK_P

CLKIN_DOT_96N

CLKIN_DOT_96P

REFCLK14IN

XTAL25_IN

XTAL25_OUT

XCLK_RCOMP

B9 H14 C8

J14 C6 G8

M14 E10 G12

T13 T11 T9

H1

AD43 AD45

AN4 AN2

AT1 AT3

AW24 BA24

AP3 AP1

F18 E18

AH13 AH12

P41

J42

AH51 AH53

AF38

T45

P43

T42

N50

SCD1U16V2KX-3GP

3

SMBALERT# PCH_SMB_CLK PCH_SMB_DATA

SML0ALERT# SML0_CLK SML0_DATA

SML1ALERT# SML1CLK SML1DAT

CL_CLK

1

CL_DATA

1

CL_RST#

1

PEG_CLKREQ#

CLK_PCIE_VGA1# CLK_PCIE_VGA1

CLK_EXP_N CLK_EXP_P

CLK_DP_N CLK_DP_P

CLKIN_DMI# CLKIN_DMI

CLK_CPU_BCLK# CLK_CPU_BCLK

DREFCLK# DREFCLK

CLK_PCIE_SATA# CLK_PCIE_SATA

CLK_PCH_14M

CLK_PCI_FB

XTAL25_IN XTAL25_OUT

XCLK_RCOMP

TP_CLK_OUTFLEX0

TP_CLK_OUTFLEX1

EDID_SELECT_R#

TP_CLK_OUTFLEX3

C2301

EDID_SELECT#54,55,57

R2301

R2301 10KR2J-3-GP

10KR2J-3-GP

12

PCH_SMB_CLK 77 PCH_SMB_DATA 77

R2302

R2302 10KR2J-3-GP

10KR2J-3-GP

12

SML0_CLK 9 SML0_DATA 9

R2303

R2303 10KR2J-3-GP

10KR2J-3-GP

12

SML1CLK 37 SML1DAT 37

TP2301Do Not StuffTP2301Do Not Stuff TP2302Do Not StuffTP2302Do Not Stuff TP2303Do Not StuffTP2303Do Not Stuff

RN709

RN709 SRN0J-6-GP

1 2 3

R2306 90D9R2F-1-GPR2306 90D9R2F-1-GP

1

+3.3V_RUN

12

DY

SRN0J-6-GP

4

DIS

1 2

TP2307

TP2307 Do Not Stuff

Do Not Stuff TP2305

TP2305 Do Not Stuff

Do Not Stuff

TP2306

TP2306 Do Not Stuff

Do Not Stuff

U2302

5 4

74LVC1G08GW-1-GP

R2311 0R2J-2-GP

12

C2312

DY

SC220P50V2KX-3GP

CLK_EXP_N 9 CLK_EXP_P 9

CLK_DP_N 9 CLK_DP_P 9

CLKIN_DMI# 7 CLKIN_DMI 7

CLK_CPU_BCLK# 7 CLK_CPU_BCLK 7

DREFCLK# 7 DREFCLK 7

CLK_PCIE_SATA# 7 CLK_PCIE_SATA 7

CLK_PCH_14M 7

CLK_PCI_FB 21

VCC Y

1 2

+3.3V_ALW

DY

GND

DY

+3.3V_ALW

12

R2304

R2304 10KR2J-3-GP

10KR2J-3-GP

1

B

2

A

3

+1.05V_PCH

CLK_PCIE_VGA# 80 CLK_PCIE_VGA 80

EDID_SELECT_R#

2

SML0_CLK SML0_DATA

+3.3V_RUN

PCH_SMB_DATA

PCH_SMB_CLK

DGPU_PW RGD25,86,87

1

23

RN2313

RN2313 SRN2K2J-1-GP

SRN2K2J-1-GP

4

PCH_SMB_CLK PCH_SMB_DATA

RN2303

2 3 1

SRN2K2J-1-GP

6 5

Q2301

Q2301 DMN66D0LDW-7-GP

DMN66D0LDW-7-GP

2009/08/10 Modify 25MHz crystal schematic for Intel design guideline on PCH.

XTAL25_IN

R2305

R2305 1MR2J-1-GP

1MR2J-1-GP

XTAL25_OUT

R2312

10KR2J-3-GP

UMA

Title

PCH (PCI-E/SMBUS/CLOCK/CL)

Size Document Number Rev

Date: Sheet of

23

RN2302

RN2302 SRN2K2J-1-GP

SRN2K2J-1-GP

4

2009/07/28 Change 2N7002 ESD pretect from standard to 1KV type P/N:84.2N702.E31

4

1 2 34

2009/07/28 Change 2N7002 ESD pretect from standard to 1KV type P/N:84.2N702.E31

PEG_CLKREQ#

G

S D

R2308

R2308 0R2J-2-GP

0R2J-2-GP

12

X2301

X2301 XTAL-25MHZ-67GP

XTAL-25MHZ-67GP

UMA

C2307

C2307 SC18P50V2JN-1-GP

SC18P50V2JN-1-GP

12

R2307

DY

R2307

10KR2J-3-GP

EDID_SELECT#EDID_SELECT_R#

R2309

10KR2J-3-GP

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Vostro Calpella

+3.3V_ALW

SML1CLK SML1DAT

PCH_SMBDATA 7,18,19,40,64

PCH_SMBCLK 7,18,19,40,64

Q2305

Q2305 2N7002A-7-GP

2N7002A-7-GP

1 2

DIS

C2311

C2311 SC18P50V2JN-1-GP

SC18P50V2JN-1-GP

12

UMA

12

UMA

+3.3V_RUN+3.3V_RUN

12

UMA

12

DIS

23 90Tuesday, September 08, 2009

1

23

4

RN2306

RN2306 SRN2K2J-1-GP

SRN2K2J-1-GP

SA

5

4

3

2

1

PCH_RTCX1

1 2

R2401

R2401 10MR2J-L-GP

10MR2J-L-GP

X2401

1

12

C2402

D D

SC18P50V2JN-1-GP

C C

C2402

Flash Descriptor Security Override/ ME Debug Mode

ME_UNLOCK#

1 2

DY

R2419 1KR2J-1-GP

+3.3V_RUN

NO REBOOT STRAP

1 2

DY

R2410 1KR2J-1-GP

1 2

R2411 10KR2J-3-GPR2411 10KR2J-3-GP

2 3

X-32D768KHZ-38GPU

This strap should only be asserted low via external pull down in manufacturing/debug environments ONLY.

SB_SPKR

INT_SERIRQ

4

ME_UNLOCK_R#

PCH_RTCX2

12

C2403

C2403 SC18P50V2JN-1-GP

SC18P50V2JN-1-GP

No Reboot Strap R23

HDA_SPKR

Low = Default High = No Reboot

+RTC_CELL

SC1U6D3V3KX-2GP

1 2

R2402

R2402 20KR2J-L2-GP

20KR2J-L2-GP

R2403

R2403 20KR2J-L2-GP

20KR2J-L2-GP

C2404

C2401

SC1U6D3V3KX-2GP

C2401

SC1U6D3V3KX-2GP

12

21

12

G2401

G2401 Do Not Stuff

Do Not Stuff

+RTC_CELL

PCH_AZ_CODEC_BITCLK30 PCH_AZ_CODEC_SYNC30

SB_SPKR30

PCH_AZ_CODEC_RST#30

PCH_SDIN_CODEC30

PCH_SDOUT_CODEC30

ME_UNLOCK#37

INTVRMEN- Integrated SUS

1.1V VRM Enable High - Enable internal VRs

1 2

R2406 1MR2J-1-GPR2406 1MR2J-1-GP

1 2

R2404 330KR2F-L-GPR2404 330KR2F-L-GP

1 2 1 2

1 2

R2417 0R2J-2-GPR2417 0R2J-2-GP

1 2

33R2J-2-GPR2405 33R2J-2-GPR2405 33R2J-2-GPR2407 33R2J-2-GPR2407

33R2J-2-GPR2408 33R2J-2-GPR2408

33R2J-2-GPR2409 33R2J-2-GPR2409

TP2404Do Not Stuff TP2404Do Not Stuff TP2405Do Not Stuff TP2405Do Not Stuff TP2406Do Not Stuff TP2406Do Not Stuff TP2407Do Not Stuff TP2407Do Not Stuff TP2408Do Not Stuff TP2408Do Not Stuff

PCH_RTCX1 PCH_RTCX2

PCH_RTCRST# SRTCRST# SM_INTRUDER# PCH_INTVRMEN

ACZ_BIT_CLK ACZ_SYNC_R

ACZ_RST#_R

ACZ_SDATAOUT_R

ME_UNLOCK_R#

PCH_JTAG_TCK

1

PCH_JTAG_TMS

1

PCH_JTAG_TDI

1

PCH_JTAG_TDO

1

PCH_JTAG_RST#

1

U2001A

B13

RTCX1

D13

RTCX2

C14

RTCRST#

D17

SRTCRST#

A16

INTRUDER#

A14

INTVRMEN

A30

HDA_BCLK

D29

HDA_SYNC

P1

SPKR

C30

HDA_RST#

G30

HDA_SDIN0

F30

HDA_SDIN1

E32

HDA_SDIN2

F32

HDA_SDIN3

B29

HDA_SDO

H32

HDA_DOCK_EN#/GPIO33

J30

HDA_DOCK_RST#/GPIO13

M3

JTAG_TCK

K3

JTAG_TMS

K1

JTAG_TDI

J2

JTAG_TDO

J4

TRST#

RTCIHDA

FWH4/LFRAME#

LDRQ1#/GPIO23

LPC

SATA

SATAICOMPO

1 OF 10

FWH0/LAD0 FWH1/LAD1 FWH2/LAD2 FWH3/LAD3

LDRQ0#

SERIRQ

SATA0RXN SATA0RXP SATA0TXN SATA0TXP

SATA1RXN SATA1RXP SATA1TXN SATA1TXP

SATA2RXN SATA2RXP SATA2TXN SATA2TXP

SATA3RXN SATA3RXP SATA3TXN SATA3TXP

SATA4RXN SATA4RXP SATA4TXN SATA4TXP

SATA5RXN SATA5RXP SATA5TXN SATA5TXP

SATAICOMPI

LPC_LAD[0..3]

LPC_LAD0

D33

LPC_LAD1

B33

LPC_LAD2

C32

LPC_LAD3

A32 C34 A34

F34 AB9

AK7 AK6 AK11 AK9

AH6 AH5 AH9 AH8

AF11 AF9 AF7 AF6

AH3 AH1 AF3 AF1

AD9 AD8 AD6 AD5

AD3 AD1 AB3 AB1

AF16 AF15

CAP place near connector

(Not available for HM55)

CAP place near connector

SATAICOMP

LPC_LFRAME# 37,70,76

INT_SERIRQ 37,76

R2412 37D4R2F-GPR2412 37D4R2F-GP

1 2

LPC_LAD[0..3] 37,70,76

+1.05V_PCH

SATA_IRXN0_HTXN0_C 59 SATA_IRXP0_HTXP0_C 59 SATA_ITXN0_HRXN0_C 59 SATA_ITXP0_HRXP0_C 59

SATA_IRXN1_OTXN1_C 59 SATA_IRXP1_OTXP1_C 59 SATA_ITXN1_ORXN1_C 59 SATA_ITXP1_ORXP1_C 59

ESATA_IRX_DTX_N4_C 63 ESATA_IRX_DTX_P4_C 63

HDD

ODD

ESATA

ESATA_ITX_DRX_N4_C 63 ESATA_ITX_DRX_P4_C 63

R2413 15R2J-GPR2413 15R2J-GP

PCH_SPI_CLK62

B B

A A

5

PCH_SPI_CS0#62

PCH_SPI_DO62

PCH_SPI_DI62

4

1 2

R2414 15R2J-GPR2414 15R2J-GP

1 2

R2415 15R2J-GPR2415 15R2J-GP

1 2

SPI_CLK_R SPI_CS#0_R

SPI_MOSI_R

3

BA2

SPI_CLK

AV3

SPI_CS0#

AY3

SPI_CS1#

AY1

SPI_MOSI

AV1

SPI_MISO

IBEXPEAK-M-GP-NF

SPI JTAG

SATALED#

SATA0GP/GPIO21 SATA1GP/GPIO19

2

T3

Y9 V1

GPIO_DSM PCH_GPIO19

SATA_LED# 66

GPIO_DSM 76

+3.3V_RUN

R2418

R2418 10KR2J-3-GP

PCH_GPIO19

GPIO_DSM

UMA

Title

PCH (SPI/RTC/LPC/SATA/IHDA)

Size Document Number Rev

Date: Sheet of

10KR2J-3-GP

1 2

R2416

R2416 10KR2J-3-GP

10KR2J-3-GP

1 2

2009/08/06 R2416 made STUFF ,For Lan chip connecter senser Pin.

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Vostro Calpella

24 90Tuesday, September 08, 2009

1

SA

5

+3.3V_RUN_GPU +3.3V_RUN

R2552

R2552 10KR2J-3-GP

10KR2J-3-GP

DEEPIDLE_WAKE_INT_R#81

D D

C C

+3.3V_ALW

+3.3V_RUN

B B

DY

DY DY

DY

+3.3V_RUN

12

R2527

R2527 10KR2J-3-GP

10KR2J-3-GP

DIS

A A

DY

12

DGPU_PRSNT#

R2528

R2528 10KR2J-3-GP

10KR2J-3-GP

ECSWI#37

PCH_GPIO28

R253010KR2J-3-GP R253010KR2J-3-GP

12

PCH_GPIO57

R252310KR2J-3-GP R252310KR2J-3-GP

12

PCH_GPIO15

R25321KR2J-1-GP R25321KR2J-1-GP

12

PCIECLKRQ6#

R252110KR2J-3-GP R252110KR2J-3-GP

12

DDR_RST_GATE

R252210KR2J-3-GP R252210KR2J-3-GP

12

ECSMI#

R253110KR2J-3-GP R253110KR2J-3-GP

12

ECSWI#

R252410KR2J-3-GP R252410KR2J-3-GP

12

KB_DET_R#

R251510KR2J-3-GP R251510KR2J-3-GP

12

STP_PCI#

R251710KR2J-3-GP R251710KR2J-3-GP

12

BIO_DET#

R251810KR2J-3-GP R251810KR2J-3-GP

12

PCH_GPIO38

R251910KR2J-3-GP R251910KR2J-3-GP

12

DGPU_PW R_EN#

R252910KR2J-3-GP R252910KR2J-3-GP

12

DGPU_PW RGD_R

R250710KR2J-3-GP R250710KR2J-3-GP

12

LCD_CBL_DET_R#

R251010KR2J-3-GP R251010KR2J-3-GP

12

ECSCI#

R251210KR2J-3-GP R251210KR2J-3-GP

12

PCH_GPIO27

R252610KR2J-3-GP

12

FFS_INT2_R INIT3_3V#

R252010KR2J-3-GP

12

+3.3V_RUN

12

R2516

R2516 10KR2J-3-GP

10KR2J-3-GP

DY

12

R2533

R2533 10KR2J-3-GP

10KR2J-3-GP

5

+3.3V_RUN_GPU

12

Q2515_1

1

Q2515

1 2

MMBT3904-7-F-GP

2

C2501

12

SC47P50V2JN-3GP

DY

DGPU_HOLD_RST#80

DGPU_PW RGD23,86,87

LCD_CBL_DET#54

R2525

R2525 10KR2J-3-GP

10KR2J-3-GP

1 2

KB_DET#68

DGPU_HOLD_RST#

R2555

R2555 2K2R2J-2-GP

2K2R2J-2-GP

3

12

R2508

R2508 10KR2J-3-GP

10KR2J-3-GP

R2506 0R2J-2-GPR2506 0R2J-2-GP

1 2

R3749 100R2J-2-GPR3749 100R2J-2-GP

1 2

DGPU_PW R_EN#37

R2548

R2548 100R2J-2-GP

100R2J-2-GP

DDR_RST_GATE9,11

TURBO_BOOST_ALERT#37

ECSCI#37

BIO_DET#78

ECSMI#37

1 2

FFS_INT2_R40

TP2510Do Not Stuff TP2510Do Not Stuff

TP2511Do Not Stuff TP2511Do Not Stuff TP2512Do Not Stuff TP2512Do Not Stuff

TP2509Do Not Stuff TP2509Do Not Stuff

4

DEEPIDLE_WAKE_INT#

ECSCI# BIO_DET# ECSWI# ECSMI#

PCH_GPIO15 DGPU_HOLD_RST# DGPU_PW RGD_R LCD_CBL_DET_R#

PCH_GPIO27 PCH_GPIO28 STP_PCI# PCH_GPIO35 DGPU_PW R_EN# DGPU_PRSNT# PCH_GPIO38 KB_DET_R# PCIECLKRQ6#

DDR_RST_GATE FFS_INT2_R TURBO_BOOST_ALERT# PCH_GPIO57

PCH_NCTF_1

1

PCH_NCTF_2

1

PCH_NCTF_3

1

PCH_NCTF_4

1

4

U2001F

Y3

BMBUSY#/GPIO0

C38

TACH1/GPIO1

D37

TACH2/GPIO6

J32

TACH3/GPIO7

F10

GPIO8

K9

LAN_PHY_PWR_CTRL/GPIO12

T7

GPIO15

AA2

SATA4GP/GPIO16

F38

TACH0/GPIO17

Y7

SCLOCK/GPIO22

H10

GPIO24

AB12

GPIO27

V13

GPIO28

M11

STP_PCI#/GPIO34

V6

SATACLKREQ#/GPIO35

AB7

SATA2GP/GPIO36

AB13

SATA3GP/GPIO37

V3

SLOAD/GPIO38

P3

SDATAOUT0/GPIO39

H3

PCIECLKRQ6#/GPIO45

F1

PCIECLKRQ7#/GPIO46

AB6

SDATAOUT1/GPIO48

AA4

SATA5GP/GPIO49

F8

GPIO57

A4

VSS_NCTF_1

A49

VSS_NCTF_2

A5

VSS_NCTF_3

A50

VSS_NCTF_4

A52

VSS_NCTF_5

A53

VSS_NCTF_6

B2

VSS_NCTF_7

B4

VSS_NCTF_8

B52

VSS_NCTF_9

B53

VSS_NCTF_10

BE1

VSS_NCTF_11

BE53

VSS_NCTF_12

BF1

VSS_NCTF_13

BF53

VSS_NCTF_14

BH1

VSS_NCTF_15

BH2

VSS_NCTF_16

BH52

VSS_NCTF_17

BH53

VSS_NCTF_18

BJ1

VSS_NCTF_19

BJ2

VSS_NCTF_20

BJ4

VSS_NCTF_21

BJ49

VSS_NCTF_22

BJ5

VSS_NCTF_23

BJ50

VSS_NCTF_24

BJ52

VSS_NCTF_25

BJ53

VSS_NCTF_26

D1

VSS_NCTF_27

D2

VSS_NCTF_28

D53

VSS_NCTF_29

E1

VSS_NCTF_30

E53

VSS_NCTF_31

IBEXPEAK-M-GP-NF

3

MISC

CLKOUT_BCLK0_N/CLKOUT_PCIE8N

CLKOUT_BCLK0_P/CLKOUT_PCIE8P

GPIO

CPU

NCTF

RSVD

3

6 OF 10

CLKOUT_PCIE6N CLKOUT_PCIE6P

CLKOUT_PCIE7N CLKOUT_PCIE7P

A20GATE

PECI

RCIN#

PROCPWRGD

THRMTRIP#

TP1 TP2 TP3 TP4 TP5 TP6 TP7 TP8

TP9 TP10 TP11 TP12 TP13 TP14 TP15 TP16 TP17 TP18 TP19

NC_1 NC_2 NC_3 NC_4 NC_5

INIT3_3V#

TP24

AH45 AH46

AF48 AF47

U2

AM3 AM1 BG10 T1 BE10 BD10

BA22 AW22 BB22 AY45 AY46 AV43 AV45 AF13 M18 N18 AJ24 AK41 AK42 M32 N32 M30 N30 H12 AA23 AB45 AB38 AB42 AB41 T39

P6 C10

2

KA20GATE 37

BCLK_CPU_N 9 BCLK_CPU_P 9

H_PECI 9

H_PWRGOOD 9,42

PCH_THERMTRIP_R

TP2506Do Not StuffTP2506Do Not Stuff

1

2

1

+1.05V_VTT

R2509

R2509 56R2J-4-GP

KBRCIN# 37

1 2

R2511

56R2J-4-GP

Placed Within 2" from PCH

UMA

Title

ize Document Number Rev

Size Document Number Rev

S

Date: Sheet of

56R2J-4-GP

1 2

H_THRMTRIP# 9,37,42

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

PCH (GPIO/CPU)

Vostro Calpella

1

SA

25 90Tuesday, September 08, 2009

SA

5

4

3

2

1

+1.05V_PCH

1.432A

D D

+1.05V_PCH

40mA

1 2

DY

12

L2601

L2601 IND-1UH-2-GP

IND-1UH-2-GP

C2601

SC10U10V5ZY-1GP

C2601

SC10U10V5ZY-1GP

C2602

SC1U10V2KX-1GP

C2602

SC1U10V2KX-1GP

12

+1.05V_PCH

+1.05VS_VCCAPLL_EXP

C2606

12

SC10U6D3V5MX-3GPDYC2606

SC10U6D3V5MX-3GP

DY

+1.05V_PCH

L2602

L2602 IND-1UH-2-GP

IND-1UH-2-GP

1 2

DY

3.062A

+1.05VS_VCCAPLL_FDI

C2608

SC10U6D3V5MX-3GP

C2608

SC10U6D3V5MX-3GP

12

C2616

C2616 SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

DY

C2609

SC1U10V3KX-3GP

C2609

SC1U10V3KX-3GP

C2610

SC1U10V3KX-3GP

C2610

12

SC1U10V3KX-3GP

12

+1.8V_RUN

12

C2611

SC1U10V3KX-3GP

C2611

SC1U10V3KX-3GP

C2614

12

R2606

R2606 0R2J-2-GP

0R2J-2-GP

+1.05V_PCH

C2612

SC1U10V3KX-3GP

C2612

SC1U10V3KX-3GP

12

+3.3V_RUN

SCD1U10V2KX-4GP

357mA

+VCC_VRM

12

+VCC_VRM

C C

B B

U2001G

AB24

VCCCORE

AB26

VCCCORE

AB28

VCCCORE

AD26

VCCCORE

AD28

VCCCORE

AF26

VCCCORE

AF28

VCCCORE

AF30

VCCCORE

AF31

VCCCORE

AH26

VCCCORE

AH28

VCCCORE

AH30

VCCCORE

AH31

VCCCORE

AJ30

VCCCORE

AJ31

VCCCORE

AK24

VCCIO

BJ24

VCCAPLLEXP

AN20

VCCIO

AN22

VCCIO

AN23

VCCIO

AN24

VCCIO

AN26

VCCIO

AN28

VCCIO

BJ26

VCCIO

BJ28

VCCIO

AT26

VCCIO

AT28

VCCIO

AU26

VCCIO

AU28

VCCIO

AV26

VCCIO

AV28

VCCIO

AW26

VCCIO

AW28

VCCIO

BA26

VCCIO

BA28

VCCIO

BB26

VCCIO

BB28

VCCIO

BC26

VCCIO

BC28

VCCIO

BD26

VCCIO

BD28

VCCIO

BE26

VCCIO

BE28

VCCIO

BG26

VCCIO

BG28

VCCIO

BH27

VCCIO

AN30

VCCIO

AN31

VCCIO

AN35

VCC3_3

AT22

VCCVRM[1]

BJ18

VCCFDIPLL

AM23

VCCIO

IBEXPEAK-M-GP-NF

1.432A

3.062A

POWER

VCC CORE

DMI

PCI E*

NAND / SPI

FDI

CRTLVDS

HVCMOS

156mA

<1mA

59mA

357mA

85mA

7 OF 10

VCCADAC

VCCADAC VSSA_DAC VSSA_DAC

VCCALVDS

VSSA_LVDS

VCCTX_LVDS VCCTX_LVDS VCCTX_LVDS VCCTX_LVDS

VCC3_3 VCC3_3 VCC3_3

VCCVRM

VCCDMI VCCDMI

VCCPNAND VCCPNAND VCCPNAND VCCPNAND VCCPNAND VCCPNAND VCCPNAND VCCPNAND VCCPNAND

VCCME3_3 VCCME3_3 VCCME3_3 VCCME3_3

L2603

+VCCA_DAC_1_2

AE50 AE52 AF53 AF51

+3VS_VCCA_LVD +3.3V_RUN

AH38 AH39

AP43 AP45 AT46 AT45

AB34 AB35 AD35

35mA

AT24

AT16 AU16

AM16 AK16 AK20 AK19 AK15 AK13 AM12 AM13 AM15

AM8 AM9 AP11 AP9

C2604

SCD01U16V2KX-3GP

C2604

SCD01U16V2KX-3GP

12

C2623

1 2

DY

SCD1U10V2KX-5GP

C2625

SCD01U16V2KX-3GP

C2625

SCD01U16V2KX-3GP

12

C2607

C2607 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

+VCC_VRM

+1.05VS_VCC_DMI

12

C2613

C2613 SC1U10V3KX-3GP

SC1U10V3KX-3GP

12

C2615

C2615 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

PCH_VCCME3_3

12

C2622

C2622 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

12

+1.8VS_VCCTX_LVDS

C2624

SCD01U16V2KX-3GP

C2624

SCD01U16V2KX-3GP

357mA

85mA

C2605

DY

SCD1U10V2KX-5GP

12

C2626

SC10U6D3V5MX-3GPDYC2626

SC10U6D3V5MX-3GP

+3.3V_RUN

C2603

SC10U6D3V5MX-3GP

C2603

SC10U6D3V5MX-3GP

+3.3V_RUN

R2601

R2601 0R2J-2-GP

0R2J-2-GP

1 2

12

R2605

R2605 0R2J-2-GP

0R2J-2-GP

L2603

1 2

BLM18PG181SN1D-GP

1 2

SC10U6D3V5MX-3GP

12

R2609 0R3J-0-U-GPR2609 0R3J-0-U-GP

L2604 IND-D1UH-17-GPL2604 IND-D1UH-17-GP

58mA

156mA

+3.3V_CRT_LDO

<1mA

+1.8V_RUN

59mA

12

C2628

DY

2009/07/29 Change power rail to +1.05V_VTT for CFD.

+1.05V_VTT

+3.3V_RUN

69mA

R2602

1 2

0R2J-2-GP

U2601

5

OUT

4

NC#4

MAX8511EXK33-T-GP

2009/07/31 Changed +V_NVRAM_VCCQ_PCH power rail from 1.8V to 3.3V, Removed Braidwood Changed power rail.

DY

IN

GND

SHDN#

+3.3V_RUN

+5V_RUN+3.3V_CRT_LDO

1 2 3

DY

C2629

12

SC1U10V3KX-3GP

A A

5

4

3

2

UMA

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Date: Sheet of

Date: Sheet

PCH (POWER1)

Taipei Hsien 221, Taiwan, R.O.C.

Vostro Calpella

26 90Tuesday, September 08, 2009

1

of

SA

5

+1.05V_PCH

52mA

D D

IND-10UH-30-GP

+1.05V_PCH

L2701

1 2

DY

R2708

1 2

0R2J-2-GP

SCD1U10V2KX-4GP

1.849A

+1.05V_PCH

1 2

L2702

C C

L2702 IND-10UH-81-GP

IND-10UH-81-GP

+1.05VS_VCCA_A_DPL

12

C2734

SC10U6D3V5MX-3GPDYC2734

SC10U6D3V5MX-3GP

C2711

SC1U10V2KX-1GP

C2711

SC1U10V2KX-1GP

12

DY

SCD1U10V2KX-4GP

1 2

L2703

L2703 IND-10UH-81-GP

IND-10UH-81-GP

B B

A A

+1.05VS_VCCA_B_DPL

12

DY

SCD1U10V2KX-4GP

+1.05V_VTT

C2714

C2735

SC10U6D3V5MX-3GP

12

+1.05V_PCH

C2718

SC1U10V2KX-1GP

C2726

C2718

SCD1U10V2KX-4GP

+3.3V_ALW

12

<1mA

SC1U10V2KX-1GP

12

SC1U10V2KX-1GP

C2723

163mA

+RTC_CELL

68mA 69mA

12

C2719

SCD1U10V2KX-4GP

C2728

SC4D7U6D3V5KX-3GP

C2728

SC4D7U6D3V5KX-3GP

2mA

5

4

12

DY

PCH_VCC_LAN

C2707

C2705

SC10U6D3V5MX-3GP

C2705

SC10U6D3V5MX-3GP

12

C2704

SC10U6D3V5MX-3GP

C2704

SC10U6D3V5MX-3GP

12

DY

12

+VCC_VRM

C2713

+1.05VS_VCCA_A_DPL

+1.05VS_VCCA_B_DPL

12

SC1U10V2KX-1GP

+VCCSST

+1.05VALW_INT_VCCSUS

12

C2724

C2724 SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

C2727

C2729

SCD1U10V2KX-4GP

C2729

SCD1U10V2KX-4GP

12

C2732

SCD1U10V2KX-4GP

C2732

SCD1U10V2KX-4GP

12

4

C2701

SC10U6D3V5MX-3GPDYC2701

SC10U6D3V5MX-3GP

DY

DCPSUSBYP

12

C2708

SC1U10V2KX-1GP

C2708

SC1U10V2KX-1GP

C2710

SC1U10V2KX-1GPDYC2710

SC1U10V2KX-1GP

+VCCRTCEXT

C2720

+3.3V_RUN

12

C2730

12

C2733

12

+1.05VS_VCCA_CLK

C2702

SC1U10V2KX-1GPDYC2702

SC1U10V2KX-1GP

12

AP51 AP53

AF23 AF24

AD38 AD39 AD41

AF43 AF41 AF42

AU24

BB51 BB53

BD51 BD53

AH23

AJ35

AH35

12

AF34

AH34

AF32

SCD1U10V2KX-4GP

AT18

AU18

SCD1U10V2KX-4GP

U2001J

VCCACLK VCCACLK

VCCLAN VCCLAN

Y20

DCPSUSBYP

VCCME VCCME VCCME VCCME VCCME VCCME

V39

VCCME

V41

VCCME

V42

VCCME

Y39

VCCME

Y41

VCCME

Y42

VCCME

V9

DCPRTC

VCCVRM

VCCADPLLA VCCADPLLA

VCCADPLLB VCCADPLLB

VCCIO VCCIO VCCIO

V12

DCPSST

Y22

DCPSUS

P18

VCCSUS3_3

U19

VCCSUS3_3

U20

VCCSUS3_3

U22

VCCSUS3_3

V15

VCC3_3

V16

VCC3_3

Y16

VCC3_3

V_CPU_IO

A12

VCCRTC

IBEXPEAK-M-GP-NF

3

10 OF 10

POWER

10 OF 10

52mA

163mA

<1mA

VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3

VCCSUS3_3

V5REF_SUS

320mA

1.849A

USB

<1mA

68mA

Clock and Miscellaneous

69mA

PCI/GPIO/LPC

VCCSATAPLL VCCSATAPLL

196mA

SATA

PCI/GPIO/LPC

<1mA

CPU

2mA

RTC

6mA

HDA

VCCSUSHDA

3

VCCIO VCCIO VCCIO VCCIO

VCCIO

V5REF

VCC3_3

VCCIO

VCCVRM

VCCIO VCCIO VCCIO VCCIO

VCCIO VCCIO VCCIO

VCCIO VCCIO VCCIO VCCIO

VCCME

V24 V26 Y24 Y26

V28 U28 U26 U24 P28 P26 N28 N26 M28 M26 L28 L26 J28 J26 H28 H26 G28 G26 F28 F26 E28 E26 C28 C26 B27 A28 A26

U23 V23

+5VALW _PCH_VCC5REFSUS

F24

+5VS_PCH_VCC5REF

K49

J38 L38 M36 N36 P36 U35

AD13

AK3 AK1

SC1U10V2KX-1GP

AH22

AT20

AH19 AD20 AF22 AD19

AF20 AF19 AH20

AB19 AB20 AB22 AD22

AA34 Y34 Y35 AA35

+3VS_+1.5VS_HDA_IO

L30

+3.3V_ALW

12

+3.3V_RUN

12

+1.05VS_VCCAPLL

12

C2721

DY

+VCC_VRM

12

C2731

C2731 SC1U10V2KX-1GP

SC1U10V2KX-1GP

12

C2706

C2706 SC1U10V2KX-1GP

SC1U10V2KX-1GP

12

C2703

C2703 SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

C2709

C2709 SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

+1.05V_PCH

C2716

C2716 SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

12

C2722

C2722 SC1U10V2KX-1GP

SC1U10V2KX-1GP

DY

6mA

1 2

R2707 0R2J-2-GPR2707 0R2J-2-GP

2

+3.3V_ALW

21

12

+3.3V_RUN

+1.05V_PCH

2

+1.05V_PCH

+3.3V_ALW

D2701

D2701 CH751H-40PT

CH751H-40PT

1 2

R2701

R2701 100R2J-2-GP

100R2J-2-GP

C2712

C2712 SC1U10V2KX-1GP

SC1U10V2KX-1GP

12

C2717

C2717 SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

L2704

1 2

DY

IND-10UH-30-GP

+3.3V_ALW

1

+5V_ALW

+3.3V_RUN

+1.05V_PCH

21

D2702

D2702 CH751H-40PT

CH751H-40PT

12

C2715

C2715 SC1U10V2KX-1GP

SC1U10V2KX-1GP

1 2

R2702

R2702 100R2J-2-GP

100R2J-2-GP

+5V_RUN

32mA

+1.05V_PCH

12

C2725

C2725 SC1U10V2KX-1GP

SC1U10V2KX-1GP

UMA

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

PCH (POWER2)

Vostro Calpella

1

27 90Tuesday, September 08, 2009

SA