Dell Precision M6600 Schematics
5
WWW.MANUALS.CLAN.SU
System Block Diagram of Brooks 17.3"
4
3
MXM3 Type B
card
2
1
PEG
PG 19
UPD720200AF1
SMSC SIO
Thermal
EMC4002
KBC
ECE1117
eDP[D]
DP [A]
DP [C]
dGPU_LVDS
dGPU_VGA
DP [B]
LAN
WG82579LM
PG 49
USB 3.0
PG 31
2 x SPI ROM
DOCK_LPC
PG 40
PG 46
2+8 MByte
PG 42
BT Conn
Camera
LCD Touch
CPU FAN CONN
MXM FAN CONN
Keyboard
Touch Pad
MUX for HDMI
PS8312
LVDS MUX
TS3DV520ERUAR
CRT MUX
MAX14885EETL+
LAN S/W
PI3L720ZHE
PG 50
USB 3.0 X2
PG 32
USB/P eSATA
PG 30
PG 33
PG 22
PG 22
KBC Module and TP Module
2
PG 25
PG 21
PG 24
RJ-45
MAG
eDP Panel
DP CONN
HDMI CONN
LVDS CONN
VGA CONN
DOCK_DP1
DOCK_VGA
DOCK_DP2
Dock-I2S
PG 50
E DOCKING
CONNECTOR
Ever Light
Ever Light
Ever Light
Technology Limited
Technology Limited
Technology Limited
Title
Title
Title
01 -- BLOCK DIAGRAM
01 -- BLOCK DIAGRAM
01 -- BLOCK DIAGRAM
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet of
Date: Sheet of
1
PG 27
1 84Thursday, Januar y 27, 2011
1 84Thursday, Januar y 27, 2011
1 84Thursday, Januar y 27, 2011
of
POWER
CHARGER
D D
LDO
0.75V_DDR_VTT, 1.8V_RUN
DC/DC
+3.3V_ALW/+5V_ALW/+15V_ALW
DC/DC
1.1V_VCCP and 1.5V_MEM
VCORE
VCC_VCO RE
Power Good
Misc. Power
C C
SIM
MINI-CARD-4
NVRAM
Card Reader
B B
1394 Port
Express Card Slot
USB Conn
USB Conn
Smart Card Slot
A A
PG 40
PG 47
PG 49
PG 48
PG 51
PG 38
MINI-CARD-1
WWAN,UWB
Half MINI-CARD-2
WLAN/WiMAX
Half MINI-CARD-3
Flash, PP
PG 37
PI2DBS212 PG 37
MMI/1394
OZ600RJ1LN
Express Card
R5538D001 USB[10]
Smart Card
TDA8034HN
HD Audio
92HD90B
Speaker X2MIC/HP Jack
5
PG 36
PG 33
PG 34
MUX
DDR3-SODIMM_A0
DDR3-SODIMM_A1
DDR3-SODIMM_B1
DDR3-SODIMM_B0
ODD
Second HDD
Main HDD
PCIE[8]
PCIE[3]
IOL
CONN.
USB[0]
USB[1]
PG 14,15
PG 16,17
PG 28
PG 28
PG 28
PG 60
1333 MHz DDR III
1333 MHz DDR III
SATA Re-driver
MAX4951
Free Fall Sensor
DE351DLTR8
PG 28
Smart Card
Sgnals
IHDA
Dock-I2S
PG 28
SPI ROM
2 MByte
BIO Sensor
Contactless
Smart Card
4
SATA [3]
SATA [1]
SATA [0]
SMBus
USB [5]
PCIE[3]
USB[4]
PCIE[2]
USB[6]
PCIE[5]
SATA[2]
PCIE[6]
PCIE[8]
PCIE[3]
USB[10]
USB[0]
USB[1]
USB[7]
PG 55
PG 55
PG 56
Current Sensor
Current Sensor
FDI
(Support AMT7.0)
EMC 1701
PG 38
EMC 1701
PG 38
Sandy Bridge
(55W XE QC)
(45W QC)
(35W DC)
Socket S 989
USH 2.0
BCM5882
PG 55,56,57
PG 2,3,4,5
DMI
Cougar Point
QM67
PCH
PG 07,08,09,10,11,12,13.
SMSC KBC
MEC5055-LZY
SMBus
LPC
PG 39
PEG
PCH_LVDS
PCH_VGA
PCIE [7]
SATA[5]
USB[8,9]
PCIE [4]
USB[2]
SATA [4]
SPI
BC bus
BC bus
BC bus
PS/2
3
MXM Card
Conn
USB [11]
USB [12]
USB [13]
ECE5028-LZY
1A
1A
1A
5
WWW.MANUALS.CLAN.SU
PEG_ICOMPO (J21)
DMI_CRX_PTX_N0(7)
DMI_CRX_PTX_N1(7)
DMI_CRX_PTX_N2(7)
DMI_CRX_PTX_N3(7)
DMI_CRX_PTX_P0(7)
DMI_CRX_PTX_P1(7)
DMI_CRX_PTX_P2(7)
DMI_CRX_PTX_P3(7)
DMI_CTX_PRX_N0(7)
DMI_CTX_PRX_N1(7)
DMI_CTX_PRX_N2(7)
DMI_CTX_PRX_N3(7)
DMI_CTX_PRX_P0(7)
DMI_CTX_PRX_P1(7)
DMI_CTX_PRX_P2(7)
DMI_CTX_PRX_P3(7)
FDI_CTX_PRX_N0(7)
FDI_CTX_PRX_N1(7)
FDI_CTX_PRX_N2(7)
FDI_CTX_PRX_N3(7)
FDI_CTX_PRX_N4(7)
FDI_CTX_PRX_N5(7)
FDI_CTX_PRX_N6(7)
FDI_CTX_PRX_N7(7)
FDI_CTX_PRX_P0(7)
FDI_CTX_PRX_P1(7)
FDI_CTX_PRX_P2(7)
FDI_CTX_PRX_P3(7)
FDI_CTX_PRX_P4(7)
FDI_CTX_PRX_P5(7)
FDI_CTX_PRX_P6(7)
FDI_CTX_PRX_P7(7)
FDI_FSYNC0(7)
FDI_FSYNC1(7)
FDI_INT(7)
FDI_LSYNC0(7)
FDI_LSYNC1(7)
+/-1%
+/-1%
1.
R57 *10K_NC +/-5%R57 *10K_NC +/-5%
PEG_ICOMPI (J22)
EDP_COMP
R_COMP place close to CPU
width 4 mils
width 12 mils
Trace l ength Ma x is 5 00 mils
D D
C C
+1.05V_RUN_VTT
R19 24.9
R19 24.9
+1.05V_RUN_VTT
Trace length Max is 500 mils
B B
eDP_COMPIO (A18)
B27
B25
A25
B24
B28
B26
A24
B23
G21
E22
F21
D21
G22
D22
F20
C21
A21
H19
E19
F18
B21
C20
D18
E17
A22
G19
E20
G18
B20
C19
D19
F17
J18
J17
H20
J19
H17
A18
A17
B16
C15
D15
C17
F16
C16
G15
C18
E16
D16
F15
JCPU1A
JCPU1A
DMI_RX#[0]
DMI_RX#[1]
DMI_RX#[2]
DMI_RX#[3]
DMI_RX[0]
DMI_RX[1]
DMI_RX[2]
DMI_RX[3]
DMI_TX#[0]
DMI_TX#[1]
DMI_TX#[2]
DMI_TX#[3]
DMI_TX[0]
DMI_TX[1]
DMI_TX[2]
DMI_TX[3]
FDI0_TX#[0]
FDI0_TX#[1]
FDI0_TX#[2]
FDI0_TX#[3]
FDI1_TX#[0]
FDI1_TX#[1]
FDI1_TX#[2]
FDI1_TX#[3]
FDI0_TX[0]
FDI0_TX[1]
FDI0_TX[2]
FDI0_TX[3]
FDI1_TX[0]
FDI1_TX[1]
FDI1_TX[2]
FDI1_TX[3]
FDI0_FSYNC
FDI1_FSYNC
FDI_INT
FDI0_LSYNC
FDI1_LSYNC
eDP_COMPIO
eDP_ICOMPO
eDP_HPD
eDP_AUX
eDP_AUX#
eDP_TX[0]
eDP_TX[1]
eDP_TX[2]
eDP_TX[3]
eDP_TX#[0]
eDP_TX#[1]
eDP_TX#[2]
eDP_TX#[3]
CPU socket
CPU socket
R_COMPeDP_ICOMPO (A17)
R_COMP place close to CPU
W/S=4/15
W/S=12/15
VCC_IO
VCC_IO
R_COMPPEG_RCOMPO (H22)
PEG_ICOMPI
PEG_ICOMPO
PEG_RCOMPO
PEG_RX#[0]
PEG_RX#[1]
PEG_RX#[2]
PEG_RX#[3]
PEG_RX#[4]
PEG_RX#[5]
PEG_RX#[6]
PEG_RX#[7]
DMI
DMI
PEG_RX#[8]
PEG_RX#[9]
PEG_RX#[10]
PEG_RX#[11]
PEG_RX#[12]
PEG_RX#[13]
PEG_RX#[14]
PEG_RX#[15]
PEG_RX[0]
PEG_RX[1]
PEG_RX[2]
PEG_RX[3]
PEG_RX[4]
PEG_RX[5]
PEG_RX[6]
PEG_RX[7]
PEG_RX[8]
PEG_RX[9]
PEG_RX[10]
PEG_RX[11]
PEG_RX[12]
PEG_RX[13]
PEG_RX[14]
PEG_RX[15]
PEG_TX#[0]
PEG_TX#[1]
PEG_TX#[2]
PEG_TX#[3]
PEG_TX#[4]
PEG_TX#[5]
Intel(R) FDI
Intel(R) FDI
PEG_TX#[6]
PEG_TX#[7]
PEG_TX#[8]
PEG_TX#[9]
PEG_TX#[10]
PEG_TX#[11]
PEG_TX#[12]
PCI EXPRESS* - GRAPHICS
PCI EXPRESS* - GRAPHICS
PEG_TX#[13]
PEG_TX#[14]
PEG_TX#[15]
PEG_TX[0]
PEG_TX[1]
PEG_TX[2]
PEG_TX[3]
PEG_TX[4]
PEG_TX[5]
PEG_TX[6]
PEG_TX[7]
PEG_TX[8]
PEG_TX[9]
eDP
eDP
PEG_TX[10]
PEG_TX[11]
PEG_TX[12]
PEG_TX[13]
PEG_TX[14]
PEG_TX[15]
Each FDI pipeline can be configured according to required display bandwidth
requirements. 1, 2, 3 or 4 Lanes may be used to transport frame data over the link.
Each Lane transports at a rate of 2.7 Gbps and uses ANSI 8b10b encoding.
DG(V0.7) P49: FDI Disable
FDI_TX[7:0] FDI_TX#[7:0] Can float on the processor.
FDI_FSYNC[0..1],FDI_LSYNC[0..1],FDI_INT
Can be tied to GND (through 1K ±5% resistors); In addition,
FDI_FSYNC[0], FDI_FSYNC[1], FDI_LSYNC[0],
FDI_LSYNC[1] can be ganged together with one resistor.
If left as no connect, there is no functional impact, but power
(~15 mW) may be wasted.
J22
J21
H22
K33
M35
L34
J35
J32
H34
H31
G33
G30
F35
E34
E32
D33
D31
B33
C32
J33
L35
K34
H35
H32
G34
G31
F33
F30
E35
E33
F32
D34
E31
C33
B32
M29
M32
M31
L32
L29
K31
K28
J30
J28
H29
G27
E29
F27
D28
F26
E25
M28
M33
M30
L31
L28
K30
K27
J29
J27
H28
G28
E28
F28
D27
E26
D25
PEG_COMP
PEG_CRX_GTX_N15
PEG_CRX_GTX_N14
PEG_CRX_GTX_N13
PEG_CRX_GTX_N12
PEG_CRX_GTX_N11
PEG_CRX_GTX_N10
PEG_CRX_GTX_N9
PEG_CRX_GTX_N8
PEG_CRX_GTX_N7
PEG_CRX_GTX_N6
PEG_CRX_GTX_N5
PEG_CRX_GTX_N4
PEG_CRX_GTX_N3
PEG_CRX_GTX_N2
PEG_CRX_GTX_N1
PEG_CRX_GTX_N0
PEG_CRX_GTX_P15
PEG_CRX_GTX_P14
PEG_CRX_GTX_P13
PEG_CRX_GTX_P12
PEG_CRX_GTX_P11
PEG_CRX_GTX_P10
PEG_CRX_GTX_P9
PEG_CRX_GTX_P8
PEG_CRX_GTX_P7
PEG_CRX_GTX_P6
PEG_CRX_GTX_P5
PEG_CRX_GTX_P4
PEG_CRX_GTX_P3
PEG_CRX_GTX_P2
PEG_CRX_GTX_P1
PEG_CRX_GTX_P0
PEG_CTX_GRX_N15
PEG_CTX_GRX_N14
PEG_CTX_GRX_N13
PEG_CTX_GRX_N12
PEG_CTX_GRX_N11
PEG_CTX_GRX_N10
PEG_CTX_GRX_N9
PEG_CTX_GRX_N8
PEG_CTX_GRX_N7
PEG_CTX_GRX_N6
PEG_CTX_GRX_N5
PEG_CTX_GRX_N4
PEG_CTX_GRX_N3
PEG_CTX_GRX_N2
PEG_CTX_GRX_N1
PEG_CTX_GRX_N0
PEG_CTX_GRX_P15
PEG_CTX_GRX_P14
PEG_CTX_GRX_P13
PEG_CTX_GRX_P12
PEG_CTX_GRX_P11
PEG_CTX_GRX_P10
PEG_CTX_GRX_P9
PEG_CTX_GRX_P8
PEG_CTX_GRX_P7
PEG_CTX_GRX_P6
PEG_CTX_GRX_P5
PEG_CTX_GRX_P4
PEG_CTX_GRX_P3
PEG_CTX_GRX_P2
PEG_CTX_GRX_P1
PEG_CTX_GRX_P0
4
3
SANDY BRIDGE PROCESSOR HOST, PEG, Others
+1.05V_RUN_VTT
R1 24.9 +/-1%R1 24.9 +/-1%
PEG_CRX_GTX_N[0..15] (19)
PEG_CRX_GTX_P[0..15] (19)
H_SNB_IVB#(11)
CPU_DETECT#(40)
H_PECI(11)
H_PROCHOT#(39,71)
H_THERMTRIP#(11,46)
H_PM_SYNC(7)
H_CPUPWRGD(6,11)
VCCPWRGOOD_0_R
R16
R16
10K
10K
+/-5%
+/-5%
Avoid stub in the PWRGD path
while placing resistors R2006 & R2009
PCH_PLTRST#(9)
R6 56+/-5%R6 56+/-5%
R7 0 +/-5%R7 0 +/-5 %
place R7 near CPU
R8 0
R8 0
DRAMPWROK. DG v0.7 P252
The PCH asserts this pin in S0-S3 to indicate
when DRAM po wer is o n.
The PCH deasserts this pin in S4 and S5.
Pull-high to 1.5V thru 4.75K
CRB v0.7 is 1.1K
+3.3V_RUN
C1
C1
0.1uF
0.1uF
16V,Y5V
16V,Y5V
53
U1
U1
2 4
PCH_PLTRST#_BUF
NC
NC
74LVC1G07GW
74LVC1G07GW
1
H_CATERR#
H_PROCHOT#_R
H_THERMTRIP#_R
VCCPWRGOOD_0_R
+/-5%
+/-5%
PM_DRAM_PWRGD_CPU
PCH_PLTRST#_R
+1.05V_RUN_VTT
R27
R27
75
75
+/-1%
+/-1%
R31 43
R31 43
+/-1%
+/-1%
JCPU1B
JCPU1B
C26
SNB_IVB#
AN34
SKTOCC#
AL33
CATERR#
AN33
PECI
AL32
PROCHOT#
AN32
THERMTRIP#
AM34
PM_SYNC
AP33
UNCOREPWRGOOD
V8
SM_DRAMPWROK
AR33
RESET#
CPU socket
CPU socket
PCH_PLTRST#_R
2
A28
CPU_DMI
BCLK
BCLK#
MISCTHERMALPWR MANAGEMENT
MISCTHERMALPWR MANAGEMENT
DPLL_REF_SSCLK
DPLL_REF_SSCLK#
CLOCKS
CLOCKS
SM_DRAMRST#
SM_RCOMP[0]
SM_RCOMP[1]
SM_RCOMP[2]
DDR3
MISC
DDR3
MISC
PRDY#
PREQ#
TCK
TMS
TRST#
TDI
TDO
DBR#
BPM#[0]
BPM#[1]
JTAG & BPM
JTAG & BPM
BPM#[2]
BPM#[3]
BPM#[4]
BPM#[5]
BPM#[6]
BPM#[7]
+1.05V_RUN_VTT
R22 *56_NC
R22 *56_NC
R24 *49.9_NC
R24 *49.9_NC
R28 62
R28 62
R32
R32
*0_NC
*0_NC
+/-5%
+/-5%
H_THERMTRIP#
+/-5%
+/-5%
H_CATERR#
+/-1%
+/-1%
H_PROCHOT#
+/-5%
+/-5%
R2 0 +/-5%R2 0 +/-5%
A27
CPU_DMI#
R3 0 +/-5%R3 0 +/-5%
A16
CPU_DPLL
A15
CPU_DPLL#
R8
DDR3_DRAMRST#_CPU
AK1
SM_RCOMP0
A5
SM_RCOMP1
A4
SM_RCOMP2
Max 500mils
AP29
XDP_PRDY#
AP27
XDP_PREQ#
AR26
XDP_TCLK
AR27
XDP_TMS
AP30
XDP_TRST#
AR28
XDP_TDI_R
AP26
XDP_TDO_R
AL35
XDP_DBRESET#_R
AT28
AR29
AR30
AT30
AP32
AR31
AT31
AR32
R9 0 +/-5%R9 0 +/-5%
XDP_OBS0_R
R10 0 +/-5 %R1 0 0 +/-5%
XDP_OBS1_R
R11 0 +/-5 %R1 1 0 +/-5%
XDP_OBS2_R
R12 0 +/-5 %R1 2 0 +/-5%
XDP_OBS3_R
R13 0 +/-5 %R1 3 0 +/-5%
XDP_OBS4_R
R14 0 +/-5 %R1 4 0 +/-5%
XDP_OBS5_R
R15 0 +/-5 %R1 5 0 +/-5%
XDP_OBS6_R
R17 0 +/-5 %R1 7 0 +/-5%
XDP_OBS7_R
R18 0 +/-5 %R1 8 0 +/-5%
XDP_TDI_R XDP_TDI
R20 0 +/-5%R20 0 +/-5%
XDP_TDO_R
R21 0 +/-5%R21 0 +/-5%
XDP_TMS
XDP_TDI_R
XDP_PREQ#
XDP_TCLK
XDP_TRST#
SM_RCOMP0
SM_RCOMP1
SM_RCOMP2
XDP_PRDY# (6)
XDP_PREQ# (6)
XDP_TCLK (6)
XDP_TMS (6)
XDP_TRST# (6)
1
CLK_CPU_DMI (10)
CLK_CPU_DMI# (10)
CPU_DPLL#
R5 1K +/-5%R5 1K +/-5%
CPU_DPLL
R4 1K +/-5%R4 1K +/-5%
XDP_OBS0
XDP_OBS1
XDP_OBS2
XDP_OBS3
XDP_OBS4
XDP_OBS5
XDP_OBS6
XDP_OBS7
XDP_TDO
R23 51+/-1%R23 51+/-1%
R25 51+/-1%R25 51+/-1%
R26 *51_NC +/ -1%R26 *51_NC +/-1%
R29 51+/-1%R29 51+/-1%
R30 51+/-1%R30 51+/-1%
XDP_DBRESET# (6,7)
XDP_OBS[0..7] (6)
XDP_TDI (6)
XDP_TDO (6)
+1.05V_RUN_VTT
R33140+/-1% R33140+/-1%
R3425.5+/ -1% R3425.5+/ -1%
R35200+/-1% R35200+/-1%
+1.05V_RUN_VTT
Follow 0.9 DG
Cap need close to MXM Connector
PEG bus TX cap : 0.22uF for Gen 3, 0.1uF for Gen2
PEG_CTX_GRX_N15
PEG_CTX_GRX_N14
PEG_CTX_GRX_N13
PEG_CTX_GRX_N12
PEG_CTX_GRX_N11
PEG_CTX_GRX_N10
PEG_CTX_GRX_N9
PEG_CTX_GRX_N8
PEG_CTX_GRX_N7
PEG_CTX_GRX_N6
PEG_CTX_GRX_N5
PEG_CTX_GRX_N4
PEG_CTX_GRX_N3
PEG_CTX_GRX_N2
PEG_CTX_GRX_N1
PEG_CTX_GRX_N0
PEG_CTX_GRX_P15
A A
PEG_CTX_GRX_P14
PEG_CTX_GRX_P13
PEG_CTX_GRX_P12
PEG_CTX_GRX_P11
PEG_CTX_GRX_P10
PEG_CTX_GRX_P9
PEG_CTX_GRX_P8
PEG_CTX_GRX_P7
PEG_CTX_GRX_P6
PEG_CTX_GRX_P5
PEG_CTX_GRX_P4
PEG_CTX_GRX_P3
PEG_CTX_GRX_P2
PEG_CTX_GRX_P1
PEG_CTX_GRX_P0
C2 220nF 16V,X7RC2 220nF 16V,X7R
C3 220nF 16V,X7RC3 220nF 16V,X7R
C4 220nF 16V,X7RC4 220nF 16V,X7R
C5 220nF 16V,X7RC5 220nF 16V,X7R
C6 220nF 16V,X7RC6 220nF 16V,X7R
C7 220nF 16V,X7RC7 220nF 16V,X7R
C8 220nF 16V,X7RC8 220nF 16V,X7R
C11 220nF 16 V,X7RC11 220nF 16 V,X7R
C12 220nF 16 V,X7RC12 220nF 16 V,X7R
C13 220nF 16 V,X7RC13 220nF 16 V,X7R
C14 220nF 16 V,X7RC14 220nF 16 V,X7R
C15 220nF 16 V,X7RC15 220nF 16 V,X7R
C16 220nF 16 V,X7RC16 220nF 16 V,X7R
C17 220nF 16 V,X7RC17 220nF 16 V,X7R
C18 220nF 16 V,X7RC18 220nF 16 V,X7R
C19 220nF 16 V,X7RC19 220nF 16 V,X7R
C20 220nF 16 V,X7RC20 220nF 16 V,X7R
C21 220nF 16 V,X7RC21 220nF 16 V,X7R
C22 220nF 16 V,X7RC22 220nF 16 V,X7R
C23 220nF 16 V,X7RC23 220nF 16 V,X7R
C24 220nF 16 V,X7RC24 220nF 16 V,X7R
C25 220nF 16 V,X7RC25 220nF 16 V,X7R
C26 220nF 16 V,X7RC26 220nF 16 V,X7R
C27 220nF 16 V,X7RC27 220nF 16 V,X7R
C28 220nF 16 V,X7RC28 220nF 16 V,X7R
C29 220nF 16 V,X7RC29 220nF 16 V,X7R
C30 220nF 16 V,X7RC30 220nF 16 V,X7R
C31 220nF 16 V,X7RC31 220nF 16 V,X7R
C32 220nF 16 V,X7RC32 220nF 16 V,X7R
C33 220nF 16 V,X7RC33 220nF 16 V,X7R
C34 220nF 16 V,X7RC34 220nF 16 V,X7R
C35 220nF 16 V,X7RC35 220nF 16 V,X7R
5
PEG_CTX_GRX_N15_C (19)
PEG_CTX_GRX_N14_C (19)
PEG_CTX_GRX_N13_C (19)
PEG_CTX_GRX_N12_C (19)
PEG_CTX_GRX_N11_C (19)
PEG_CTX_GRX_N10_C (19)
PEG_CTX_GRX_N9_C (19)
PEG_CTX_GRX_N8_C (19)
PEG_CTX_GRX_N7_C (19)
PEG_CTX_GRX_N6_C (19)
PEG_CTX_GRX_N5_C (19)
PEG_CTX_GRX_N4_C (19)
PEG_CTX_GRX_N3_C (19)
PEG_CTX_GRX_N2_C (19)
PEG_CTX_GRX_N1_C (19)
PEG_CTX_GRX_N0_C (19)
PEG_CTX_GRX_P15_C (19)
PEG_CTX_GRX_P14_C (19)
PEG_CTX_GRX_P13_C (19)
PEG_CTX_GRX_P12_C (19)
PEG_CTX_GRX_P11_C (19)
PEG_CTX_GRX_P10_C (19)
PEG_CTX_GRX_P9_C (19)
PEG_CTX_GRX_P8_C (19)
PEG_CTX_GRX_P7_C (19)
PEG_CTX_GRX_P6_C (19)
PEG_CTX_GRX_P5_C (19)
PEG_CTX_GRX_P4_C (19)
PEG_CTX_GRX_P3_C (19)
PEG_CTX_GRX_P2_C (19)
PEG_CTX_GRX_P1_C (19)
PEG_CTX_GRX_P0_C (19)
+3.3V_ALW_PCH
need to confirm component of AND gate and MOS
Follow DG Rev0.71 SM_DRAMPWROK topology
4
RUNPWROK_R1(39,40)
R42 200 +/-1%R4 2 200 +/-1%
PM_DRAM_PWRGD(7)
SUS_ON(39,72)
RUN_ON_CPU1.5VS3#(4,72)
C9 0.1uF 16V,Y5VC9 0.1uF 16V,Y5V
U2
2
1
74AHC1G09GWU274AHC1G09GW
3 5
R44 *0_NC +/-5%R44 *0_NC +/-5%
R45 *0_NC +/-5%R45 *0_NC +/-5%
+1.5V_CPU_VDDQ+3.3V_ALW_PCH
R40
R40
200
200
+/-1%
+/-1%
4
G
3
R41 130 +/-5%R4 1 130 +/-5%
R43
R43
*39_NC
*39_NC
+/-1%
+/-1%
D
Q2
Q2
*2N7002W-7-F_NC
*2N7002W-7-F_NC
S
PM_DRAM_PWRGD_CPURUNPWROK_AND
For CPU S3 Power Reduce
DDR3_DRAMRST#(14,15,16,17)
DDR_HVREF_RST_PCH(10)
DDR_HVREF_RST_GATE(39)
2
R356 1K +/-5%R356 1K +/-5%
+1.5V_MEM
R197 *0_NC +/-5%R197 *0_NC +/-5 %
Q1
R36
R36
BSS138Q1BSS138
1K
1K
+/-5%
+/-5%
D S
DDR3_DRAMRST#_CPU
R37 0 +/-5%R37 0 +/-5%
R38 *0_NC +/-5%R38 *0_NC +/-5%
Title
Title
Title
02 -- SNB (rPGA) 1/4 H OST, PEG
02 -- SNB (rPGA) 1/4 H OST, PEG
02 -- SNB (rPGA) 1/4 H OST, PEG
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet
G
2.
R39
R39
4.99K
4.99K
C10
C10
+/-1%
+/-1%
47nF
47nF
16V,X7R
16V,X7R
Ever Light
Ever Light
Ever Light
Technology Limited
Technology Limited
Technology Limited
2 84Thursday, Janua ry 27 , 20 11
2 84Thursday, Janua ry 27 , 20 11
2 84Thursday, Janua ry 27 , 20 11
1
of
1A
1A
1A
5
WWW.MANUALS.CLAN.SU
4
3
2
1
D D
JCPU1C
JCPU1C
DDR_A_D[0..63](14,15)
C C
B B
DDR_A_BS0(14,15)
DDR_A_BS1(14,15)
DDR_A_BS2(14,15)
DDR_A_CAS#(14, 15)
DDR_A_RAS#(14, 15)
DDR_A_WE#(14,15)
DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63
C5
SA_DQ[0]
D5
SA_DQ[1]
D3
SA_DQ[2]
D2
SA_DQ[3]
D6
SA_DQ[4]
C6
SA_DQ[5]
C2
SA_DQ[6]
C3
SA_DQ[7]
F10
SA_DQ[8]
F8
SA_DQ[9]
G10
SA_DQ[10]
G9
SA_DQ[11]
F9
SA_DQ[12]
F7
SA_DQ[13]
G8
SA_DQ[14]
G7
SA_DQ[15]
K4
SA_DQ[16]
K5
SA_DQ[17]
K1
SA_DQ[18]
J1
SA_DQ[19]
J5
SA_DQ[20]
J4
SA_DQ[21]
J2
SA_DQ[22]
K2
SA_DQ[23]
M8
SA_DQ[24]
N10
SA_DQ[25]
N8
SA_DQ[26]
N7
SA_DQ[27]
M10
SA_DQ[28]
M9
SA_DQ[29]
N9
SA_DQ[30]
M7
SA_DQ[31]
AG6
SA_DQ[32]
AG5
SA_DQ[33]
AK6
SA_DQ[34]
AK5
SA_DQ[35]
AH5
SA_DQ[36]
AH6
SA_DQ[37]
AJ5
SA_DQ[38]
AJ6
SA_DQ[39]
AJ8
SA_DQ[40]
AK8
SA_DQ[41]
AJ9
SA_DQ[42]
AK9
SA_DQ[43]
AH8
SA_DQ[44]
AH9
SA_DQ[45]
AL9
SA_DQ[46]
AL8
SA_DQ[47]
AP11
SA_DQ[48]
AN11
SA_DQ[49]
AL12
SA_DQ[50]
AM12
SA_DQ[51]
AM11
SA_DQ[52]
AL11
SA_DQ[53]
AP12
SA_DQ[54]
AN12
SA_DQ[55]
AJ14
SA_DQ[56]
AH14
SA_DQ[57]
AL15
SA_DQ[58]
AK15
SA_DQ[59]
AL14
SA_DQ[60]
AK14
SA_DQ[61]
AJ15
SA_DQ[62]
AH15
SA_DQ[63]
AE10
SA_BS[0]
AF10
SA_BS[1]
V6
SA_BS[2]
AE8
SA_CAS#
AD9
SA_RAS#
AF9
SA_WE#
CPU socket
CPU socket
SA_CLK#[0]
SA_CLK#[1]
SA_CLK#[2]
SA_CLK#[3]
SA_DQS#[0]
SA_DQS#[1]
SA_DQS#[2]
SA_DQS#[3]
SA_DQS#[4]
SA_DQS#[5]
SA_DQS#[6]
SA_DQS#[7]
DDR SYSTEM MEMORY A
DDR SYSTEM MEMORY A
SANDY BRIDGE PROCESSOR (DDR3)
SA_CLK[0]
SA_CKE[0]
SA_CLK[1]
SA_CKE[1]
SA_CLK[2]
SA_CKE[2]
SA_CLK[3]
SA_CKE[3]
SA_CS#[0]
SA_CS#[1]
SA_CS#[2]
SA_CS#[3]
SA_ODT[0]
SA_ODT[1]
SA_ODT[2]
SA_ODT[3]
SA_DQS[0]
SA_DQS[1]
SA_DQS[2]
SA_DQS[3]
SA_DQS[4]
SA_DQS[5]
SA_DQS[6]
SA_DQS[7]
SA_MA[0]
SA_MA[1]
SA_MA[2]
SA_MA[3]
SA_MA[4]
SA_MA[5]
SA_MA[6]
SA_MA[7]
SA_MA[8]
SA_MA[9]
SA_MA[10]
SA_MA[11]
SA_MA[12]
SA_MA[13]
SA_MA[14]
SA_MA[15]
AB6
AA6
V9
AA5
AB5
V10
AB4
AA4
W9
AB3
AA3
W10
AK3
AL3
AG1
AH1
AH3
AG3
AG2
AH2
C4
G6
J3
M6
AL6
AM8
AR12
AM15
D4
F6
K3
N6
AL5
AM9
AR11
AM14
AD10
W1
W2
W7
V3
V2
W3
W6
V1
W5
AD8
V4
W4
AF8
V5
V7
DDR_A_CLK0 (15)
DDR_A_CLK#0 (15 )
DDR_A_CKE0 (1 5)
DDR_A_CLK1 (15)
DDR_A_CLK#1 (15 )
DDR_A_CKE1 (1 5)
DDR_A_CLK2 (14)
DDR_A_CLK#2 (14 )
DDR_A_CKE2 (1 4)
DDR_A_CLK3 (14)
DDR_A_CLK#3 (14 )
DDR_A_CKE3 (1 4)
DDR_A_CS#0 (15)
DDR_A_CS#1 (15)
DDR_A_CS#2 (14)
DDR_A_CS#3 (14) DDR_B_CS#3 (16)
DDR_A_ODT0 (15)
DDR_A_ODT1 (15)
DDR_A_ODT2 (14)
DDR_A_ODT3 (14)
DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7
DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_MA15
DDR_A_DQS#[0..7] (1 4,15)
DDR_A_DQS[0..7] (14 ,15)
DDR_A_MA[0..15] (14 ,15)
JCPU1D
JCPU1D
AE2
SB_CLK[0]
DDR_B_D[0..63](16,1 7)
DDR_B_BS0(16,17)
DDR_B_BS1(16,17)
DDR_B_BS2(16,17)
DDR_B_CAS#(16, 17)
DDR_B_RAS#(16, 17)
DDR_B_WE#(16,17)
DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63
C9
SB_DQ[0]
A7
SB_DQ[1]
D10
SB_DQ[2]
C8
SB_DQ[3]
A9
SB_DQ[4]
A8
SB_DQ[5]
D9
SB_DQ[6]
D8
SB_DQ[7]
G4
SB_DQ[8]
F4
SB_DQ[9]
F1
SB_DQ[10]
G1
SB_DQ[11]
G5
SB_DQ[12]
F5
SB_DQ[13]
F2
SB_DQ[14]
G2
SB_DQ[15]
J7
SB_DQ[16]
J8
SB_DQ[17]
K10
SB_DQ[18]
K9
SB_DQ[19]
J9
SB_DQ[20]
J10
SB_DQ[21]
K8
SB_DQ[22]
K7
SB_DQ[23]
M5
SB_DQ[24]
N4
SB_DQ[25]
N2
SB_DQ[26]
N1
SB_DQ[27]
M4
SB_DQ[28]
N5
SB_DQ[29]
M2
SB_DQ[30]
M1
SB_DQ[31]
AM5
SB_DQ[32]
AM6
SB_DQ[33]
AR3
SB_DQ[34]
AP3
SB_DQ[35]
AN3
SB_DQ[36]
AN2
SB_DQ[37]
AN1
SB_DQ[38]
AP2
SB_DQ[39]
AP5
SB_DQ[40]
AN9
SB_DQ[41]
AT5
SB_DQ[42]
AT6
SB_DQ[43]
AP6
SB_DQ[44]
AN8
SB_DQ[45]
AR6
SB_DQ[46]
AR5
SB_DQ[47]
AR9
SB_DQ[48]
AJ11
SB_DQ[49]
AT8
SB_DQ[50]
AT9
SB_DQ[51]
AH11
SB_DQ[52]
AR8
SB_DQ[53]
AJ12
SB_DQ[54]
AH12
SB_DQ[55]
AT11
SB_DQ[56]
AN14
SB_DQ[57]
AR14
SB_DQ[58]
AT14
SB_DQ[59]
AT12
SB_DQ[60]
AN15
SB_DQ[61]
AR15
SB_DQ[62]
AT15
SB_DQ[63]
AA9
SB_BS[0]
AA7
SB_BS[1]
R6
SB_BS[2]
AA10
SB_CAS#
AB8
SB_RAS#
AB9
SB_WE#
CPU socket
CPU socket
DDR SYSTEM MEMORY B
DDR SYSTEM MEMORY B
SB_CLK#[0]
SB_CKE[0]
SB_CLK[1]
SB_CLK#[1]
SB_CKE[1]
SB_CLK[2]
SB_CLK#[2]
SB_CKE[2]
SB_CLK[3]
SB_CLK#[3]
SB_CKE[3]
SB_CS#[0]
SB_CS#[1]
SB_CS#[2]
SB_CS#[3]
SB_ODT[0]
SB_ODT[1]
SB_ODT[2]
SB_ODT[3]
SB_DQS#[0]
SB_DQS#[1]
SB_DQS#[2]
SB_DQS#[3]
SB_DQS#[4]
SB_DQS#[5]
SB_DQS#[6]
SB_DQS#[7]
SB_DQS[0]
SB_DQS[1]
SB_DQS[2]
SB_DQS[3]
SB_DQS[4]
SB_DQS[5]
SB_DQS[6]
SB_DQS[7]
SB_MA[0]
SB_MA[1]
SB_MA[2]
SB_MA[3]
SB_MA[4]
SB_MA[5]
SB_MA[6]
SB_MA[7]
SB_MA[8]
SB_MA[9]
SB_MA[10]
SB_MA[11]
SB_MA[12]
SB_MA[13]
SB_MA[14]
SB_MA[15]
AD2
R9
AE1
AD1
R10
AB2
AA2
T9
AA1
AB1
T10
AD3
AE3
AD6
AE6
AE4
AD4
AD5
AE5
D7
F3
K6
N3
AN5
AP9
AK12
AP15
C7
G3
J6
M3
AN6
AP8
AK11
AP14
AA8
T7
R7
T6
T2
T4
T3
R2
T5
R3
AB7
R1
T1
AB10
R5
R4
DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7
DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7
DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14
DDR_B_MA15
DDR_B_CLK0 (17)
DDR_B_CLK#0 (17 )
DDR_B_CKE0 (1 7)
DDR_B_CLK1 (17)
DDR_B_CLK#1 (17 )
DDR_B_CKE1 (1 7)
DDR_B_CLK2 (16)
DDR_B_CLK#2 (16 )
DDR_B_CKE2 (1 6)
DDR_B_CLK3 (16)
DDR_B_CLK#3 (16 )
DDR_B_CKE3 (1 6)
DDR_B_CS#0 (17)
DDR_B_CS#1 (17)
DDR_B_CS#2 (16)
DDR_B_ODT0 (17)
DDR_B_ODT1 (17)
DDR_B_ODT2 (16)
DDR_B_ODT3 (16)
DDR_B_DQS#[0..7] (1 6,17)
DDR_B_DQS[0..7] (16 ,17)
DDR_B_MA[0..15] (16,17)
A A
Ever Light
Ever Light
Ever Light
Technology Limited
Technology Limited
Technology Limited
Title
Title
Title
03 -- SNB (rPGA) 2/4 D DR
03 -- SNB (rPGA) 2/4 D DR
03 -- SNB (rPGA) 2/4 D DR
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet
1
of
3 84Thursday, Janua ry 27 , 20 11
3 84Thursday, Janua ry 27 , 20 11
3 84Thursday, Janua ry 27 , 20 11
1A
1A
1A
5
WWW.MANUALS.CLAN.SU
SANDY BRIDGE PROCESSOR (POWER)
POWER
POWER
JCPU1F
+VCC_CORE
C104
C104
22uF
22uF
4V,X6S
4V,X6S
c0805h14
c0805h14
C109
C109
22uF
22uF
4V,X6S
4V,X6S
c0805h14
c0805h14
AG35
AG34
AG33
AG32
AG31
AG30
AG29
AG28
AG27
AG26
AF35
AF34
AF33
AF32
AF31
AF30
AF29
AF28
AF27
AF26
AD35
AD34
AD33
AD32
AD31
AD30
AD29
AD28
AD27
AD26
AC35
AC34
AC33
AC32
AC31
AC30
AC29
AC28
AC27
AC26
AA35
AA34
AA33
AA32
AA31
AA30
AA29
AA28
AA27
AA26
Y35
Y34
Y33
Y32
Y31
Y30
Y29
Y28
Y27
Y26
V35
V34
V33
V32
V31
V30
V29
V28
V27
V26
U35
U34
U33
U32
U31
U30
U29
U28
U27
U26
R35
R34
R33
R32
R31
R30
R29
R28
R27
R26
P35
P34
P33
P32
P31
P30
P29
P28
P27
P26
Place top socket cavity
C105
C105
22uF
22uF
4V,X6S
4V,X6S
c0805h14
c0805h14
C110
C110
22uF
22uF
4V,X6S
4V,X6S
c0805h14
c0805h14
JCPU1F
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCC8
VCC9
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16
VCC17
VCC18
VCC19
VCC20
VCC21
VCC22
VCC23
VCC24
VCC25
VCC26
VCC27
VCC28
VCC29
VCC30
VCC31
VCC32
VCC33
VCC34
VCC35
VCC36
VCC37
VCC38
VCC39
VCC40
VCC41
VCC42
VCC43
VCC44
VCC45
VCC46
VCC47
VCC48
VCC49
VCC50
VCC51
VCC52
VCC53
VCC54
VCC55
VCC56
VCC57
VCC58
VCC59
VCC60
VCC61
VCC62
VCC63
VCC64
VCC65
VCC66
VCC67
VCC68
VCC69
VCC70
VCC71
VCC72
VCC73
VCC74
VCC75
VCC76
VCC77
VCC78
VCC79
VCC80
VCC81
VCC82
VCC83
VCC84
VCC85
VCC86
VCC87
VCC88
VCC89
VCC90
VCC91
VCC92
VCC93
VCC94
VCC95
VCC96
VCC97
VCC98
VCC99
VCC100
CPU socket
CPU socket
CORE SUPPLY
CORE SUPPLY
C107
C107
C106
C106
22uF
22uF
22uF
22uF
4V,X6S
4V,X6S
4V,X6S
4V,X6S
c0805h14
c0805h14
c0805h14
c0805h14
C111
C111
22uF
22uF
4V,X6S
4V,X6S
c0805h14
c0805h14
5
VCCIO1
VCCIO2
VCCIO3
VCCIO4
VCCIO5
VCCIO6
VCCIO7
VCCIO8
VCCIO9
VCCIO10
VCCIO11
VCCIO12
VCCIO13
VCCIO14
VCCIO15
VCCIO16
VCCIO17
VCCIO18
VCCIO19
VCCIO20
VCCIO21
VCCIO22
VCCIO23
VCCIO24
VCCIO25
VCCIO26
VCCIO27
VCCIO28
VCCIO29
VCCIO30
PEG AND DDR
PEG AND DDR
VCCIO31
VCCIO32
VCCIO33
VCCIO34
VCCIO35
VCCIO36
VCCIO37
VCCIO38
VCCIO39
VCCIO40
VIDALERT#
VIDSCLK
VIDSOUT
VCC_SENSE
VSS_SENSE
VCCIO_SENSE
VSSIO_SENSE
SENSE LINES SVID
SENSE LINES SVID
+VCC_CORE
C108
C108
22uF
22uF
4V,X6S
4V,X6S
c0805h14
c0805h14
+VCC_CORE
+1.05V_RUN_VTT
AH13
AH10
AG10
AC10
Y10
U10
P10
L10
J14
J13
J12
J11
H14
H12
H11
G14
G13
G12
F14
F13
F12
F11
E14
E12
E11
D14
D13
D12
D11
C14
C13
C12
C11
B14
B12
A14
A13
A12
A11
J23
AJ29
H_CPU_SVIDALRT# ALERT
VDIO
VCCSENS E_R
VSSSENS E_R
VTT_S ENSE _R
VSSIO_SE NSE_ R
C112
C112
22uF
22uF
4V,X6S
4V,X6S
c0805h14
c0805h14
C117
C117
22uF
22uF
4V,X6S
4V,X6S
c0805h14
c0805h14
C124
C124
10uF
10uF
4V,X6S
4V,X6S
c0805h14
c0805h14
C130
C130
10uF
10uF
4V,X6S
4V,X6S
c0805h14
c0805h14
R47 43 +/-1%R47 43 +/-1%
Place PU resistors close
to processor
R56 0 +/-5%R56 0 +/-5%
R59 0 +/-5%R59 0 +/-5%
R60 0 +/-5%R60 0 +/-5%
R61 0 +/-5%R61 0 +/-5%
Place top socket edge
C113
C113
22uF
22uF
4V,X6S
4V,X6S
c0805h14
c0805h14
C118
C118
22uF
22uF
4V,X6S
4V,X6S
c0805h14
c0805h14
Place bot socket cavity
C125
C125
10uF
10uF
4V,X6S
4V,X6S
c0805h14
c0805h14
C131
C131
10uF
10uF
4V,X6S
4V,X6S
c0805h14
c0805h14
AJ30
AJ28
18-mil witdh,and shoulde use differential
routing with 7-milseparation.
Signals must have equal trace length
within 25 mils and are to be routed using external layer and
GND referencing (no split plane referencing). VSS_SENSE,
VCC_SENSE are to use 25-mils separation from any other
signal or rail.
AJ35
AJ34
B10
A10
VCCCORE = (SV) xxA max
D D
C C
B B
+VCC_CORE
A A
ALERT
Place PU resistors close to VR
C114
C114
22uF
22uF
4V,X6S
4V,X6S
c0805h14
c0805h14
C119
C119
22uF
22uF
4V,X6S
4V,X6S
c0805h14
c0805h14
C126
C126
10uF
10uF
4V,X6S
4V,X6S
c0805h14
c0805h14
C132
C132
10uF
10uF
4V,X6S
4V,X6S
c0805h14
c0805h14
4
R46 75 +/-1%R46 75 +/-1%
+VCC_CORE
VSSSENS E
VSSSENS E
C120
C120
22uF
22uF
4V,X6S
4V,X6S
c0805h14
c0805h14
C127
C127
10uF
10uF
4V,X6S
4V,X6S
c0805h14
c0805h14
C133
C133
10uF
10uF
4V,X6S
4V,X6S
c0805h14
c0805h14
4
R55
R55
100
100
+/-1%
+/-1%
VTT_S ENSE (68)
VTT_G ND (68)
R62
R62
100
100
+/-1%
+/-1%
C121
C121
22uF
22uF
4V,X6S
4V,X6S
c0805h14
c0805h14
C128
C128
10uF
10uF
4V,X6S
4V,X6S
c0805h14
c0805h14
C134
C134
10uF
10uF
4V,X6S
4V,X6S
c0805h14
c0805h14
+VCC_GFXCORE
Place top
socket cavity
C36
C36
22uF
22uF
4V,X6S
4V,X6S
c0805h14
c0805h14
socket cavity
C42
C42
22uF
22uF
4V,X6S
4V,X6S
c0805h14
c0805h14
+1.05V_RUN_VTT
ALERT (71)
CLK (71)
VDIO (71)
+1.05V_RUN_VTT
R50
R50
130
130
+/-1%
+/-1%
VDIO
VCC_SENSE & VSS_SENSE:
xxxxxx
100- ±1% pull-down to GND near processor
VCCSENS E ( 71)
VSSSENS E (71)
+1.05V_RUN_VTT
Voltage Rail Voltage
VCC
VCCIO
VAXG
VCCPLL
VDDQ
VCCSA
+1.5V_MEM
* Description
5A to Mem controller(+1.5V_CPU_VDDQ)
5-6A to 2 DIMMs/channel
2-5A to +1.5V_RUN & +0.75V_DDR_VTT
3
SANDY BRIDGE PROCESSOR (GRAPHICS POWER)
22uF x 16
470uF x 2 on VR side
C37
C37
22uF
22uF
4V,X6S
4V,X6S
c0805h14
c0805h14
C43
C43
22uF
22uF
4V,X6S
4V,X6S
c0805h14
c0805h14
+1.8V_RUN
R49 0 +/-5% r1206h7R49 0 +/-5% r1206h7
CPU Power Rail Table
0.65-1.3
1.05
0.0-1.1
1.8
1.5
0.65-0.9
1.5
Place top socket edge
C38
C38
22uF
22uF
4V,X6S
4V,X6S
c0805h14
c0805h14
C45
C45
22uF
22uF
4V,X6S
4V,X6S
c0805h14
c0805h14
need changed to 0.002 ohm(1206)
C72
C72
*22uF_NC
*22uF_NC
4V,X6S
4V,X6S
c0805h14
c0805h14
C83
C83
22uF
22uF
4V,X6S
4V,X6S
c0805h14
c0805h14
C40
C40
C41
22uF
22uF
4V,X6S
4V,X6S
c0805h14
c0805h14
C47
C47
22uF
22uF
4V,X6S
4V,X6S
c0805h14
c0805h14
C68
C68
10uF
10uF
4V,X6S
4V,X6S
c0805h14
c0805h14
Place bot socket edge
C74
C74
*22uF_NC
*22uF_NC
4V,X6S
4V,X6S
c0805h14
c0805h14
C85
C85
*22uF_NC
*22uF_NC
4V,X6S
4V,X6S
c0805h14
c0805h14
Place bot socket cavity
C41
22uF
22uF
4V,X6S
4V,X6S
c0805h14
c0805h14
C48
C48
22uF
22uF
4V,X6S
4V,X6S
c0805h14
c0805h14
C69
C69
1uF
1uF
6.3V,X5R
6.3V,X5R
c0402h6
c0402h6
C75
C75
22uF
22uF
4V,X6S
4V,X6S
c0805h14
c0805h14
C86
C86
*22uF_NC
*22uF_NC
4V,X6S
4V,X6S
c0805h14
c0805h14
Power page :
22uF x 3
EE page :
330uF x 1, NC x 1
22uF x 12, NC x 7
Intel DG :
330uF x 2 near CPU
22uF x 5, NC x 5 Bottom Socket Cavity
22uF x 7, NC x 2 Top Socket Cavity
for 2012 capable designs
330 µF x3
3
C39
C39
22uF
22uF
4V,X6S
4V,X6S
c0805h14
c0805h14
Place bot socket edgePlace bot
C46
C46
22uF
22uF
4V,X6S
4V,X6S
c0805h14
c0805h14
C67
C67
330uF
330uF
2.5V,<9mOhm
2.5V,<9mOhm
Place bot socket cavity Place top socket cavity
C73
C73
22uF
22uF
4V,X6S
4V,X6S
c0805h14
c0805h14
C84
C84
*22uF_NC
*22uF_NC
4V,X6S
4V,X6S
c0805h14
c0805h14
Place top socket cavity
S0 Iccmax
Current (A)
53
8.5
26
3
5
6
12-16 *
+1.8V_VCCPLL
C70
C70
1uF
1uF
6.3V,X5R
6.3V,X5R
c0402h6
c0402h6
C76
C76
*22uF_NC
*22uF_NC
4V,X6S
4V,X6S
c0805h14
c0805h14
C87
C87
22uF
22uF
4V,X6S
4V,X6S
c0805h14
c0805h14
C77
C77
22uF
22uF
4V,X6S
4V,X6S
c0805h14
c0805h14
C88
C88
*22uF_NC
*22uF_NC
4V,X6S
4V,X6S
c0805h14
c0805h14
Place bot socket cavity
Place top socket cavity
JCPU1G
JCPU1G
AT24
VAXG1
AT23
VAXG2
AT21
VAXG3
AT20
VAXG4
AT18
VAXG5
AT17
VAXG6
AR24
VAXG7
AR23
VAXG8
AR21
VAXG9
AR20
VAXG10
AR18
VAXG11
AR17
VAXG12
AP24
VAXG13
AP23
VAXG14
AP21
VAXG15
AP20
VAXG16
AP18
VAXG17
AP17
VAXG18
AN24
VAXG19
AN23
VAXG20
AN21
VAXG21
AN20
VAXG22
AN18
VAXG23
AN17
VAXG24
AM24
VAXG25
AM23
VAXG26
AM21
VAXG27
AM20
VAXG28
AM18
VAXG29
AM17
VAXG30
AL24
VAXG31
AL23
VAXG32
AL21
VAXG33
AL20
VAXG34
AL18
VAXG35
AL17
VAXG36
AK24
VAXG37
AK23
VAXG38
AK21
VAXG39
AK20
VAXG40
AK18
VAXG41
AK17
VAXG42
AJ24
VAXG43
AJ23
VAXG44
AJ21
VAXG45
AJ20
VAXG46
AJ18
VAXG47
AJ17
VAXG48
AH24
VAXG49
AH23
VAXG50
AH21
VAXG51
AH20
VAXG52
AH18
VAXG53
AH17
VAXG54
B6
VCCPLL1
A6
VCCPLL2
A2
VCCPLL3
CPU socket
CPU socket
C79
C79
C78
C78
22uF
22uF
22uF
22uF
4V,X6S
4V,X6S
4V,X6S
4V,X6S
c0805h14
c0805h14
c0805h14
c0805h14
C90
C90
C89
C89
22uF
22uF
*22uF_NC
*22uF_NC
4V,X6S
4V,X6S
4V,X6S
4V,X6S
c0805h14
c0805h14
c0805h14
c0805h14
POWER
POWER
VAXG_SENSE
VSSAXG_SENSE
SENSE
LINES
SENSE
LINES
VREFMISC
VREFMISC
GRAPHICS
GRAPHICS
DDR3 -1.5V RAILS
DDR3 -1.5V RAILS
SA RAIL
SA RAIL
VCCSA_SENSE
VCCSA_VID1
1.8V RAIL
1.8V RAIL
+1.05V_RUN_VTT
C82
C82
C80
C80
C81
C81
*22uF_NC
*22uF_NC
22uF
22uF
*22uF_NC
*22uF_NC
4V,X6S
4V,X6S
4V,X6S
4V,X6S
4V,X6S
4V,X6S
c0805h14
c0805h14
c0805h14
c0805h14
c0805h14
c0805h14
C103
C103
C102
C102
330uF
330uF
330uF
330uF
2V,+/-20%
2V,+/-20%
2V,+/-20%
2V,+/-20%
RUN_ON(40,60,66,67,72,73)
CPU1.5V_S3_GATE(39)
SM_VREF
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
VCCSA1
VCCSA2
VCCSA3
VCCSA4
VCCSA5
VCCSA6
VCCSA7
VCCSA8
FC_C22
R65 *0_NC
R65 *0_NC
R66 0 +/-5%R66 0 +/-5%
2
2
AK35
AK34
AL1
AF7
AF4
AF1
AC7
AC4
AC1
Y7
Y4
Y1
U7
U4
U1
P7
P4
P1
M27
M26
L26
J26
J25
J24
H26
H25
H23
C22
C24
+/-5%
+/-5%
+V_SM_VREF_CNT
H_FC_C22
VCCSA_VID1
18-mil witdh,and shoulde use differential routing with 7-milseparation.
Signals must have equal trace length
within 25 mils and are to be routed using external layer and
GND referencing (no split plane referencing). VSS_SENSE,
VCC_SENSE are to use 25-mils separation from any other
signal or rail.
VAXG_SENS E ( 71)
VSSAXG_SE NSE (71 )
+V_SM_VREF should
have 10 mil trace width
C58
C58
C57
C57
C56
C56
10uF
10uF
4V,X6S
4V,X6S
c0805h14
c0805h14
C62
C62
330uF
330uF
2.5V,<9mOhm
2.5V,<9mOhm
10uF
10uF
4V,X6S
4V,X6S
c0805h14
c0805h14
10uF
10uF
4V,X6S
4V,X6S
c0805h14
c0805h14
10uF x 6
330uF x 1
C59
C59
10uF
10uF
4V,X6S
4V,X6S
c0805h14
c0805h14
10uF x 2, NC x 2
C65
C64
C64
10uF
10uF
4V,X6S
4V,X6S
c0805h14
c0805h14
R48 0 +/-5%R48 0 +/-5%
R51 *0_NC +/-5%R51 *0_NC +/-5%
R749 *0_NC +/-5%R749 *0_NC +/-5%
R53 *0_NC +/-5%R53 *0_NC +/-5%
R52
R52
1K
1K
+/-5%
+/-5%
C65
10uF
10uF
4V,X6S
4V,X6S
c0805h14
c0805h14
C66
C66
*10uF_NC
*10uF_NC
4V,X6S
4V,X6S
c0805h14
c0805h14
VCCSA_SE NSE ( 67)
+V_SM_VREF_CNT
C63
C63
*10uF_NC
*10uF_NC
4V,X6S
4V,X6S
c0805h14
c0805h14
R1041
R1041
1K
1K
+/-5%
+/-5%
For CPU S3 Power Reduce
+3.3V_ALW2
R64
R64
100K
100K
+/-5%
+/-5%
G
RUN_ON_CPU1.5VS3#
D
Q5
2N7002W-7-FQ52N7002W-7-F
S
2N7002W-7-FQ42N7002W-7-F
1
+1.5V_CPU_VDDQ
R1042
R1042
*1K_NC
*1K_NC
+/-1%
SM_VREF_RES+V_SM_VREF_CNT
C978
C978
*0.1uF_NC
*0.1uF_NC
16V,X7R
16V,X7R
C44 100nF 10V,Y5VC44 100nF 10V,Y5V
C53 100nF 10V,Y5VC53 100nF 10V,Y5V
C54 100nF 10V,Y5VC54 100nF 10V,Y5V
C55 100nF 10V,Y5VC55 100nF 10V,Y5V
Q3
FDMS7670Q3FDMS7670
2
4
C94
C94
4.7nF
4.7nF
50V,X7R
50V,X7R
+/-1%
R1044
R1044
*1K_NC
*1K_NC
+/-1%
+/-1%
+1.5V_MEM
+V_DDR_REF
531
4 84Thursday, January 27, 2011
4 84Thursday, January 27, 2011
4 84Thursday, January 27, 2011
+1.5V_MEM
of
R1043 *0_NC
R1043 *0_NC
+/-5%
+/-5%
+1.5V_CPU_VDDQ
C61
C61
C60
C60
10uF
10uF
10uF
10uF
4V,X6S
4V,X6S
4V,X6S
4V,X6S
c0805h14
c0805h14
c0805h14
c0805h14
+0.85V_RUN
C115
C115
330uF
330uF
2V,+/-20%
2V,+/-20%
VCCSA_SE NSE_ GND (67)
VCCSA_CN TRL 0 (4 0,67 )
VCCSA_CN TRL 1 (4 0,67 )
R54 *0_NC +/-5%R54 *0_NC +/-5%
PQ1
PQ1
2N7002W-7-F
2N7002W-7-F
G
+1.5V_CPU_VDDQ
RUN_ON_CPU1.5VS3
+15V_ALW
R63
R63
100K
100K
+/-5%
+/-5%
D
S
RUN_ON_CPU1.5VS3# (2,72)
Ever Light
Ever Light
Ever Light
Technology Limited
Technology Limited
Technology Limited
04 -- SNB (rPGA) 3/4 POWER
04 -- SNB (rPGA) 3/4 POWER
04 -- SNB (rPGA) 3/4 POWER
1
DS
R58
R58
100K
100K
+/-5%
+/-5%
Q4
G
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet of
Date: Sheet of
C71
C71
0.1uF
0.1uF
16V,X7R
16V,X7R
1A
1A
1A
5
WWW.MANUALS.CLAN.SU
4
3
2
1
D D
C C
B B
SANDY BRIDGE PROCESSOR (GND)
JCPU1H
JCPU1H
AT35
VSS1
AT32
VSS2
AT29
VSS3
AT27
VSS4
AT25
VSS5
AT22
VSS6
AT19
VSS7
AT16
VSS8
AT13
VSS9
AT10
VSS10
AT7
VSS11
AT4
VSS12
AT3
VSS13
AR25
VSS14
AR22
VSS15
AR19
VSS16
AR16
VSS17
AR13
VSS18
AR10
VSS19
AR7
VSS20
AR4
VSS21
AR2
VSS22
AP34
VSS23
AP31
VSS24
AP28
VSS25
AP25
VSS26
AP22
VSS27
AP19
VSS28
AP16
VSS29
AP13
VSS30
AP10
VSS31
AP7
VSS32
AP4
VSS33
AP1
VSS34
AN30
VSS35
AN27
VSS36
AN25
VSS37
AN22
AN19
AN16
AN13
AN10
AN7
AN4
AM29
AM25
AM22
AM19
AM16
AM13
AM10
AM7
AM4
AM3
AM2
AM1
AL34
AL31
AL28
AL25
AL22
AL19
AL16
AL13
AL10
AL7
AL4
AL2
AK33
AK30
AK27
AK25
AK22
AK19
AK16
AK13
AK10
AK7
AK4
AJ25
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
CPU socket
CPU socket
VSS
VSS
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99
AJ22
AJ19
AJ16
AJ13
AJ10
AJ7
AJ4
AJ3
AJ2
AJ1
AH35
AH34
AH32
AH30
AH29
AH28
AH26
AH25
AH22
AH19
AH16
AH7
AH4
AG9
AG8
AG4
AF6
AF5
AF3
AF2
AE35
AE34
AE33
AE32
AE31
AE30
AE29
AE28
AE27
AE26
AE9
AD7
AC9
AC8
AC6
AC5
AC3
AC2
AB35
AB34
AB33
AB32
AB31
AB30
AB29
AB28
AB27
AB26
Y9
Y8
Y6
Y5
Y3
Y2
W35
W34
W33
W32
W31
W30
W29
W28
W27
W26
U9
U8
U6
U5
U3
U2
JCPU1I
JCPU1I
T35
VSS161
T34
VSS162
T33
VSS163
T32
VSS164
T31
VSS165
T30
VSS166
T29
VSS167
T28
VSS168
T27
VSS169
T26
VSS170
P9
VSS171
P8
VSS172
P6
VSS173
P5
VSS174
P3
VSS175
P2
VSS176
N35
VSS177
N34
VSS178
N33
VSS179
N32
VSS180
N31
VSS181
N30
VSS182
N29
VSS183
N28
VSS184
N27
VSS185
N26
VSS186
M34
VSS187
L33
VSS188
L30
VSS189
L27
VSS190
L9
VSS191
L8
VSS192
L6
VSS193
L5
VSS194
L4
VSS195
L3
L2
L1
K35
K32
K29
K26
J34
J31
H33
H30
H27
H24
H21
H18
H15
H13
H10
H9
H8
H7
H6
H5
H4
H3
H2
H1
G35
G32
G29
G26
G23
G20
G17
G11
F34
F31
F29
VSS196
VSS197
VSS198
VSS199
VSS200
VSS201
VSS202
VSS203
VSS204
VSS205
VSS206
VSS207
VSS208
VSS209
VSS210
VSS211
VSS212
VSS213
VSS214
VSS215
VSS216
VSS217
VSS218
VSS219
VSS220
VSS221
VSS222
VSS223
VSS224
VSS225
VSS226
VSS227
VSS228
VSS229
VSS230
VSS231
VSS232
VSS233
CPU socket
CPU socket
VSS
VSS
VSS234
VSS235
VSS236
VSS237
VSS238
VSS239
VSS240
VSS241
VSS242
VSS243
VSS244
VSS245
VSS246
VSS247
VSS248
VSS249
VSS250
VSS251
VSS252
VSS253
VSS254
VSS255
VSS256
VSS257
VSS258
VSS259
VSS260
VSS261
VSS262
VSS263
VSS264
VSS265
VSS266
VSS267
VSS268
VSS269
VSS270
VSS271
VSS272
VSS273
VSS274
VSS275
VSS276
VSS277
VSS278
VSS279
VSS280
VSS281
VSS282
VSS283
VSS284
VSS285
F22
F19
E30
E27
E24
E21
E18
E15
E13
E10
E9
E8
E7
E6
E5
E4
E3
E2
E1
D35
D32
D29
D26
D20
D17
C34
C31
C28
C27
C25
C23
C10
C1
B22
B19
B17
B15
B13
B11
B9
B8
B7
B5
B3
B2
A35
A32
A29
A26
A23
A20
A3
Intel review feed back
+VCC_GFXCORE
R67 *49.9_NC +/-1%R67 *49.9 _NC+/-1 %
+VCC_CORE
R68 *49.9_NC +/-1%R6 8 *49.9_NC +/-1%
R69 *49.9_NC +/-1%R6 9 *49.9_NC +/-1%
R70 *49.9_NC +/-1%R7 0 *49.9_NC +/-1%
R71 *1K_NC +/-5%R71 *1K_NC +/-5%
R72 *1K_NC +/-5%R72 *1K_NC +/-5%
CFG2
(PEG Static
Lane Reversal)
CFG4
(Display Port
Presence strap)
Disabled; No Physical Display Port
attach ed to E mbedded Diplay Port
RSVD3
RSVD2
RSVD4
+M_VREF_DQ_DIMM0_1
+M_VREF_CA_DIMM0_1
Lan# definition matches
socket pin map d efinition
(Default Value)
(Default Value)
SANDY BRIDGE PROCESSOR( RESERVED, CFG)
CFG0(6)
CFG1(6)
CFG2
CFG2(6)
CFG3(6)
CFG4
CFG4(6)
CFG5
CFG5(6)
CFG6
CFG6(6)
CFG7
CFG7(6)
CFG8(6)
CFG9(6)
CFG10(6)
CFG11(6)
T6T6
T7T7
T9T9
T11T11
CFG16(6)
CFG17(6)
RSVD1
RSVD2
RSVD3
RSVD1
+M_VREF_DQ_DIMM0_1
+M_VREF_CA_DIMM0_1
+3.3V_ALW
R1079
R1079
10K
10K
+/-5%
+/-5%
T22T22
T28T28
T29T29
T30T30
T31T31
T33T33
T35T35
T36T36
T37T37
T38T38
T40T40
T41T41
T42T42
T43T43
T44T44
T45T45
T46T46
T47T47
T48T48
R73 0 +/-5 %R7 3 0 +/-5%
T52T52
RSVD4
+M_VREF_DQ_DIMM0_1
+M_VREF_CA_DIMM0_1
H_VCCP_SEL
JCPU1E
JCPU1E
AK28
CFG[0]
AK29
CFG[1]
AL26
CFG[2]
AL27
CFG[3]
AK26
CFG[4]
AL29
CFG[5]
AL30
CFG[6]
AM31
CFG[7]
AM32
CFG[8]
AM30
CFG[9]
AM28
CFG[10]
AM26
CFG[11]
AN28
CFG[12]
AN31
CFG[13]
AN26
CFG[14]
AM27
CFG[15]
AK31
CFG[16]
AN29
CFG[17]
AJ31
RSVD1
AH31
RSVD2
AJ33
RSVD3
AH33
RSVD4
AJ26
RSVD5
B4
RSVD6
D1
RSVD7
F25
RSVD8
F24
RSVD9
F23
RSVD10
D24
RSVD11
G25
RSVD12
G24
RSVD13
E23
RSVD14
D23
RSVD15
C30
RSVD16
A31
RSVD17
B30
RSVD18
B29
RSVD19
D30
RSVD20
B31
RSVD21
A30
RSVD22
C29
RSVD23
J20
RSVD24
B18
RSVD25
A19
RSVD26
J15
RSVD27
CPU socket
CPU socket
1 0
Lan Reversed
Enabled; An external Display port
device is connected to the Embedded
Display port
RSVD28
RSVD29
RSVD30
RSVD31
RSVD32
RSVD33
RSVD34
RSVD35
RSVD37
RSVD38
RSVD39
RSVD40
RSVD41
RSVD42
RSVD43
RSVD44
RSVD45
RSVD46
RSVD47
RSVD48
RSVD49
RSVD50
RESERVED
RESERVED
RSVD51
RSVD52
RSVD53
RSVD54
RSVD55
RSVD56
RSVD57
RSVD58
KEY
L7
AG7
AE7
AK2
W8
AT26
AM33
AJ27
T8
J16
H16
G16
AR35
AT34
AT33
AP35
AR34
B34
A33
A34
B35
C35
AJ32
AK32
AH27
AN35
AM35
AT2
AT1
AR1
B1
CLK_XDP_ITP (6)
CLK_XDP_ITP# (6)
CFG2
R74 1K +/-5%R74 1K +/-5%
CFG4
R75 *1K_NC +/-5%R75 *1K_NC +/-5%
CFG5
R76 *1K_NC +/-5%R76 *1K_NC +/-5%
CFG6
R77 *1K_NC +/-5%R77 *1K_NC +/-5%
CFG7
R78 *1K_NC +/-5%R78 *1K_NC +/-5%
T1T1
T2T2
T12T12
T3T3
T4T4
T13T13
T14T14
T5T5
T8T8
T10T10
T15T15
T16T16
T17T17
T18T18
T19T19
T20T20
T21T21
T23T23
T24T24
T25T25
T26T26
T27T27
T32T32
T34T34
T39T39
T49T49
T50T50
T51T51
T53T53
CFG[6:5]
A A
5
4
CFG7
(PEG Defer Training)
CFG[6:5]
(PCIe Port
Bifurcation Straps)
PEG Train immediately following
xxRESE TB d e assert ion
(Default Value)
11
x16 - Devic e 1 fu ncti ons 1 and 2 disabl e
10
x8, x8 - Dev ice 1 func tion 1 enabl e; fu nctio n 2 d isable
Reserved - (Device 1 function 1 disable; funct ion 2 enable)
01
x8, x8 , x4 - Devi ce 1 funct ion 1 and 2 enable
00
3
PEG Wait for BIOS for training
(Default Value)
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Title
05 -- SNB (rPGA) 4/4( GND)
05 -- SNB (rPGA) 4/4( GND)
05 -- SNB (rPGA) 4/4( GND)
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
2
Date: Sheet
1
of
5 84Thursday, Janua ry 27 , 20 11
5 84Thursday, Janua ry 27 , 20 11
5 84Thursday, Janua ry 27 , 20 11
1A
1A
1A
5
WWW.MANUALS.CLAN.SU
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3
2
1
R79 *0_NC +/ -5%R79 *0_NC +/-5%
XDP_DBRESET#
XDP_DBRESET#
R80 *0_NC +/ -5%R80 *0_NC +/-5%
PCH_PLTRST1# (9,19,31,49,5 5)
XDP_FN8
PCH_RSMRST# (7,39)
XDP_DBRESET# (2,7)
PCH_JTAG_TDO (8)
PCH_JTAG_TDI (8)
PCH_JTAG_TMS (8)
CLK_XDP
R81 0 +/-5%R81 0 +/-5%
CLK_XDP#
CFG16 (5)
CFG17 (5)
CFG0 (5)
CFG1 (5)
CFG2 (5)
CFG3 (5)
CFG8 (5)
CFG9 (5)
CFG4 (5)
CFG5 (5)
CFG6 (5)
CFG7 (5)
R88 1K
R88 1K
XDP_TRST# (2)
XDP_TDI (2)
XDP_TMS (2)
R95 1K
R95 1K
R82 0 +/-5%R82 0 +/-5%
+/-1%
+/-1%
+/-1%
+/-1%
+1.05V_RUN_VTT
D D
The resistor
for HOOK2 should be
placed such that the
stub is very small
on CFG0 net
C C
B B
C135
C135
0.1uF
0.1uF
16V,X7R
16V,X7R
C136
C136
0.1uF
0.1uF
16V,X7R
16V,X7R
+1.05V_RUN_VTT
MEM_SMBCLK
MEM_SMBCLK(10,14,15,16,17,18,28,3 6)
MEM_SMBDAT
MEM_SMBDAT(10,14,15,16,17,18,28,36)
+3.3V_ALW_PCH +3.3V_ALW_PCH
C137
C137
0.1uF
0.1uF
16V,X7R
16V,X7R
+3.3V_ALW
R92 *1K_NC +/-5%R92 *1K_NC +/-5%
1.05V_0.8V_PWROK(39,71)
SIO_PWRBTN#_R(7)
PCH_JTAG_TCK(8)
XDP_PREQ#(2)
XDP_PRDY#(2)
XDP_OBS[0..7](2)
H_CPUPWRGD(2,11)
SIO_PWRBTN#_R(7)
CFG0(5)
SYS_PWROK(7,40)
XDP_TCLK(2)
MEM_SMBDAT
MEM_SMBCLK
MEM_SMBDAT
MEM_SMBCLK
R85 1K +/-1%R85 1K +/-1%
R86 0 +/-5%R86 0 +/-5 %
R87 1K +/-1%R87 1K +/-1%
R89 0 +/-5%R89 0 +/-5 %
R90 0 +/-5%R90 0 +/-5 %
R91 0 +/-5%R91 0 +/-5 %
SYS_PWROK_XDP
R93 1K+/-5%R9 3 1K+/-5%
R94 0 +/-5%R94 0 +/-5%
R96 0 +/-5%R96 0 +/-5 %
R97 0 +/-5%R97 0 +/-5 %
PCH_JTAG_TCK
XDP_OBS0
XDP_OBS1
XDP_OBS2
XDP_OBS3
CFG10(5)
CFG11(5)
XDP_OBS4
XDP_OBS5
XDP_OBS6
XDP_OBS7
H_CPUPWRGD_XDP
CFD_PWRBTN#_XDP
XDP_HOOK2
SYS_PWROK_XDP
DDR_XDP_SMBDAT_R1
DDR_XDP_SMBCLK_R1
1.05V_0.8V_PWROK_R
PCH_PWRBTN#_XDP
DDR_XDP_SMBDAT_R2
DDR_XDP_SMBCLK_R2
XDP_FN0
XDP_FN1
XDP_FN2
XDP_FN3
XDP_FN4
XDP_FN5
XDP_FN6
XDP_FN7
CPU XDP
JXDP1
JXDP1
1
GND0
3
OBSFN_A0
5
OBSFN_A1
7
GND2
OBSDATA_A09OBSDATA_C0
OBSDATA_A111OBSDATA_C1
13
GND4
OBSDATA_A215OBSDATA_C2
OBSDATA_A317OBSDATA_C3
19
GND6
21
OBSFN_B0
23
OBSFN_B1
25
GND8
OBSDATA_B027OBSDATA_D0
OBSDATA_B129OBSDATA_D1
31
GND10
OBSDATA_B233OBSDATA_D2
OBSDATA_B335OBSDATA_D3
37
GND12
PWRGOOD/HOOK039ITPCLK/HOOK4
41
HOOK1
VCC_OBS_AB43VCC_OBS_CD
45
HOOK2
47
HOOK3
49
GND14
51
SDA
53
SCL
55
TCK1
57
TCK0
59
GND16
*Header_2X30_NC
*Header_2X30_NC
PCH XDP
JXDP2
JXDP2
1
GND0
3
OBSFN_A0
5
OBSFN_A1
7
GND2
OBSDATA_A09OBSDATA_C0
OBSDATA_A111OBSDATA_C1
13
GND4
OBSDATA_A215OBSDATA_C2
OBSDATA_A317OBSDATA_C3
19
GND6
21
OBSFN_B0
23
OBSFN_B1
25
GND8
OBSDATA_B027OBSDATA_D0
OBSDATA_B129OBSDATA_D1
31
GND10
OBSDATA_B233OBSDATA_D2
OBSDATA_B335OBSDATA_D3
37
GND12
PWRGOOD/HOOK039ITPCLK/HOOK4
41
HOOK1
VCC_OBS_AB43VCC_OBS_CD
45
HOOK2
47
HOOK3
49
GND14
51
SDA
53
SCL
55
TCK1
57
TCK0
59
GND16
*Header_2X30_NC
*Header_2X30_NC
OBSFN_C0
OBSFN_C1
OBSFN_D0
OBSFN_D1
ITPCLK#/HOOK5
RESET#/HOOK6
DBR#/HOOK7
OBSFN_C0
OBSFN_C1
OBSFN_D0
OBSFN_D1
GND11
GND13
ITPCLK#/HOOK5
RESET#/HOOK6
DBR#/HOOK7
GND15
TRSTN
GND17
GND1
GND3
GND5
GND7
GND9
GND11
GND13
GND15
TRSTN
GND17
TDO
TMS
2
GND1
4
6
8
GND3
10
12
14
GND5
16
18
20
GND7
22
24
26
GND9
28
30
32
34
36
38
40
CLK_XDP
42
CLK_XDP#
44
46
XDP_RST#_R
48
50
52
TDO
54
56
XDP_TDI
TDI
58
XDP_TMS
TMS
60
2
4
XDP_FN16
6
XDP_FN17
8
10
XDP_FN8
12
XDP_FN9
14
16
XDP_FN10
18
XDP_FN11
20
22
24
26
28
XDP_FN12
30
XDP_FN13
32
34
XDP_FN14
36
XDP_FN15
38
40
42
44
46
RSMRST#_XDP
48
50
52
PCH_JTAG_TDO
54
56
PCH_JTAG_TDI
TDI
58
PCH_JTAG_TMS
60
+1.05V_RUN_VTT
+3.3V_ALW_PCH
R307
R307
*4.7K_NC
*4.7K_NC
+/-5%
+/-5%
CLK_XDP_ITP (5)
CLK_XDP_ITP# (5)
CLK_CPU_ITP (10 )
CLK_CPU_ITP# (1 0)
+3.3V_RUN
R83
R83
51
51
+/-1%
+/-1%
XDP_TDO
R84
R84
1K
1K
+/-1%
+/-1%
XDP_DBRESET# (2,7)
XDP_TDO (2)
USB_OC0#_R(9)
USB_OC1#_R(9)
USB_OC2#(9)
USB_OC3#(9)
USB_OC4#(9)
USB_OC5#(9)
USB_OC6#(9)
SIO_EXT_SMI#(9, 39)
SLP_ME_CSW_DEV#(11,40)
PCH_GPIO35(11)
HDD_DET#_R(8)
BBS_BIT0_R(8,9)
GPIO36(11)
FDI_OVRVLTG(11)
PCH_GPIO16(11)
A A
5
4
TEMP_ALERT#(11,40)
PCH_GPIO15(11)
SIO_EXT_SCI#_R(11)
R98 *33_NC +/-5%R98 *33_NC +/-5%
R99 *33_NC +/-5%R99 *33_NC +/-5%
R100 *33_NC +/-5%R100 *3 3_NC +/ -5%
R101 *33_NC +/-5%R101 *3 3_NC +/ -5%
R102 *33_NC +/-5%R102 *3 3_NC +/ -5%
R103 *33_NC +/-5%R103 *3 3_NC +/ -5%
R104 *33_NC +/-5%R104 *3 3_NC +/ -5%
R105 *33_NC +/-5%R105 *3 3_NC +/ -5%
R106 *33_NC +/-5%R106 *3 3_NC +/ -5%
R107 *33_NC +/-5%R107 *3 3_NC +/ -5%
R108 *33_NC +/-5%R108 *3 3_NC +/ -5%
R109 *33_NC +/-5%R109 *3 3_NC +/ -5%
R110 *33_NC +/-5%R110 *3 3_NC +/ -5%
R111 *33_NC +/-5%R111 *3 3_NC +/ -5%
R112 *33_NC +/-5%R112 *3 3_NC +/ -5%
R113 *33_NC +/-5%R113 *3 3_NC +/ -5%
R114 *33_NC +/-5%R114 *3 3_NC +/ -5%
R115 *33_NC +/-5%R115 *3 3_NC +/ -5%
XDP_FN0
XDP_FN1
XDP_FN2
XDP_FN3
XDP_FN4
XDP_FN5
XDP_FN6
XDP_FN7
XDP_FN8
XDP_FN9
XDP_FN10
XDP_FN11
XDP_FN12
XDP_FN13
XDP_FN14
XDP_FN15
XDP_FN16
XDP_FN17
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Title
Title
06 -- XDP Connecto r
06 -- XDP Connecto r
06 -- XDP Connecto r
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Thunder 1A
Thunder 1A
Thunder 1A
Date: Sheet of
Date: Sheet of
3
2
Date: Sheet
1
of
6 84Thursday, Janua ry 27 , 20 11
6 84Thursday, Janua ry 27 , 20 11
6 84Thursday, Janua ry 27 , 20 11
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1
SDVO_INTN
SDVO_INTP
DDPB_AUXN
DDPB_AUXP
DDPB_HPD
DDPB_0N
DDPB_0P
DDPB_1N
DDPB_1P
DDPB_2N
DDPB_2P
DDPB_3N
DDPB_3P
DDPC_AUXN
DDPC_AUXP
DDPC_HPD
DDPC_0N
DDPC_0P
DDPC_1N
DDPC_1P
DDPC_2N
DDPC_2P
DDPC_3N
DDPC_3P
DDPD_AUXN
DDPD_AUXP
DDPD_HPD
DDPD_0N
DDPD_0P
DDPD_1N
DDPD_1P
DDPD_2N
DDPD_2P
DDPD_3N
DDPD_3P
AP43
AP45
AM42
AM40
AP39
AP40
P38
M39
AT49
AT47
AT40
AV42
AV40
AV45
AV46
AU48
AU47
AV47
AV49
P46
P42
AP47
AP49
AT38
AY47
AY49
AY43
AY45
BA47
BA48
BB47
BB49
M43
M36
AT45
AT43
BH41
BB43
BB45
BF44
BE44
BF42
BE42
BJ42
BG42
ENVDD_PCH
+3.3V_RUN
R116 100K +/-5%R116 100K +/-5%
COUGAR POINT (DMI,FDI,GPIO)
U3C
U3C
DMI_COMP_R
RBIAS_CPY
SUSACK#_R
SYS_PWROK_R
PCH_PWROK
PM_DRAM_PWRGD_R
PCH_RSMRST#_R
ME_SUS_PWR_ACK_R
SIO_PWRBTN#_R
PCH_BATLOW#
PCH_RI#
SUSACK#_RME_SUS_PWR_ACK_R
BC24
DMI0RXN
BE20
DMI1RXN
BG18
DMI2RXN
BG20
DMI3RXN
BE24
DMI0RXP
BC20
DMI1RXP
BJ18
DMI2RXP
BJ20
DMI3RXP
AW24
DMI0TXN
AW20
DMI1TXN
BB18
DMI2TXN
AV18
DMI3TXN
AY24
DMI0TXP
AY20
DMI1TXP
AY18
DMI2TXP
AU18
DMI3TXP
BJ24
DMI_ZCOMP
BG25
DMI_IRCOMP
BH21
DMI2RBIAS
C12
SUSACK#
K3
SYS_RESET#
P12
SYS_PWROK
L22
PWROK
L10
APWROK
B13
DRAMPWROK
C21
RSMRST#
K16
SUSWARN#/SUSPWRDNACK/GPIO30
E20
PWRBTN#
H20
ACPRESENT / GPIO31
E10
BATLOW# / GPIO72
A10
RI#
BD82QM67[VER.B3,SLH9B]
BD82QM67[VER.B3,SLH9B]
APWROK, DG v0.7 P248
This is a input signal to the PCH from power monitoring circuit to indicate that all Active
Sleep Well (ASW) rails, i.e. Intel ME sub-system and LAN power rails are stable on the
platform. Connect to ASW power rail monitoring circuit on motherboard. For platform
not supporting Intel AMT it can be connected to PWROK. The ASW power must be
stable for at least 1ms before platform logic asserts APW ROK.
DPWROK, DG v0.7 P252
This is an input signal to the PCH from platform power monitoring logic to indicate that
all power rails associated with the PCH Deep Sx well (DSW) are valid and stable.
Connect to VccDSW3_3 power rail monitoring circuit on mother board for platforms
that support Deep Sx state. This signal can be tied to RSMRST# for platforms that do
not support the Deep Sx state. The DSW rails must be stable for at least 10ms be fore
DPWROK is asserted to PCH.
PCH_RSMRST#
DMI
DMI
SUS_STAT# / GPIO61
System Power Management
System Power Management
R148 10K +/-5%R148 10K +/-5%
D D
Width = 10 mil, Spacing = 20 mil
Close PCH within 500 mil
From EC
SYS_PWROK, DG v0.7 P248
This signal should be used on the platform to indicate
that the processor VR power is good and therefore
C C
it can be connected to the same source as PWROK on PCH.
Follow DG 0.9
B B
A A
SUSACK#(40)
SYS_PWROK(6,40)
RESET_OUT#(39)
PM_APWROK(39)
PM_DRAM_PWRGD(2) SIO_SLP_S5# (3 9)
PCH_RSMRST#(6,39)
ME_SUS_PWR_ACK(39)
SIO_PWRBTN#_R(6)
SIO_PWRBTN#(39)
AC_PRESENT(39 )
CLKRUN#
SUS_STAT#/LPCPD#
SIO_SLP_LAN#
PCH_RI#
PCH_PCIE_WAKE#
ME_SUS_PWR_ACK
DMI_CTX_PRX_N0(2)
DMI_CTX_PRX_N1(2)
DMI_CTX_PRX_N2(2)
DMI_CTX_PRX_N3(2)
DMI_CTX_PRX_P0(2)
DMI_CTX_PRX_P1(2)
DMI_CTX_PRX_P2(2)
DMI_CTX_PRX_P3(2)
DMI_CRX_PTX_N0(2)
DMI_CRX_PTX_N1(2)
DMI_CRX_PTX_N2(2)
DMI_CRX_PTX_N3(2)
DMI_CRX_PTX_P0(2)
DMI_CRX_PTX_P1(2)
DMI_CRX_PTX_P2(2)
DMI_CRX_PTX_P3(2)
+1.05V_RUN
R121 49.9 +/-1%R1 21 49.9 +/ -1%
R122 750 +/-1 %R1 22 750 +/-1%
R123 *0_NC +/-5%R123 *0_NC +/-5 %
Deep Sleep not implemented
SUSACK# unconnected
XDP_DBRESET#(2,6)
R125 0 +/-5%R125 0 +/-5%
R126 0 +/-5%R126 0 +/-5%
R127 0 +/-5%R127 0 +/-5%
R128 0 +/-5%R128 0 +/-5%
R129 0 +/-5%R129 0 +/-5%
R130 0 +/-5%R130 0 +/-5%
R131 0 +/-5%R131 0 +/-5%
R132 8.2K +/-5%R13 2 8.2K +/-5%
+3.3V_ALW_PCH
R136 0 +/-5%R136 0 +/-5 %
DG v0.7 P248
SUSACK# and SUSWARN# can be tied together
if EC does not want to involve in the
handshake mechanism for the Dee p Sleep state entry and exit.
R137 8.2K +/-1%R137 8.2K +/-1%
R141 *10K_NC +/-5%R141 *10K_NC +/-5%
R144 10K +/-5%R144 10K +/-5%
R147 10K +/-5%R147 10K +/-5%
R146 10K +/-5%R146 10K +/-5%
R151 10K +/-5%R151 10K +/-5%
R152 *0_NC +/-5%R152 *0_NC +/-5%
+3.3V_RUN
+3.3V_ALW_PCH
SYS_PWROKRESET_OUT#
FDI_RXN0
FDI_RXN1
FDI_RXN2
FDI_RXN3
FDI_RXN4
FDI_RXN5
FDI_RXN6
FDI_RXN7
FDI_RXP0
FDI_RXP1
FDI_RXP2
FDI_RXP3
FDI_RXP4
FDI_RXP5
FDI_RXP6
FDI
FDI
FDI_RXP7
FDI_INT
FDI_FSYNC0
FDI_FSYNC1
FDI_LSYNC0
FDI_LSYNC1
DSWVRMEN
DPWROK
WAKE#
CLKRUN# / GPIO32
SUSCLK / GPIO62
SLP_S5# / GPIO63
SLP_S4#
SLP_S3#
SLP_A#
SLP_SUS#
PMSYNCH
SLP_LAN# / GPIO29
BJ14
AY14
BE14
BH13
BC12
BJ12
BG10
BG9
BG14
BB14
BF14
BG13
BE12
BG12
BJ10
BH9
AW16
FDI_INT (2)
AV12
FDI_FSYNC0 (2)
BC10
FDI_FSYNC1 (2)
AV14
FDI_LSYNC0 (2)
BB10
FDI_LSYNC1 (2)
A18
DSWODVREN
E22
PCH_DPWROK
R124 *0_NC +/-5%R124 *0_NC +/-5%
B9
PCH_PCIE_WAKE#
N3
CLKRUN#
G8
SUS_STAT#/LPCPD#
N14
SUSCLK
D10
H4
F4
G10
G16
AP14
K14
SIO_SLP_LAN#
DSWODVREN
R142 330K +/-5%R142 330K +/-5 %
R145 *330K_NC +/-5%R145 *330K_NC +/- 5%
DSWODVREN - On Die DSW VR Enable
Enabled (DEFAULT)
HIGH: R728 STUFFED,
R986 UNSTUFFED
Disabled
LOW: R986 STUFFED,
R728 UNSTUFFED
FDI_CTX_PRX_N0 (2)
FDI_CTX_PRX_N1 (2)
FDI_CTX_PRX_N2 (2)
FDI_CTX_PRX_N3 (2)
FDI_CTX_PRX_N4 (2)
FDI_CTX_PRX_N5 (2)
FDI_CTX_PRX_N6 (2)
FDI_CTX_PRX_N7 (2)
FDI_CTX_PRX_P0 (2)
FDI_CTX_PRX_P1 (2)
FDI_CTX_PRX_P2 (2)
FDI_CTX_PRX_P3 (2)
FDI_CTX_PRX_P4 (2)
FDI_CTX_PRX_P5 (2)
FDI_CTX_PRX_P6 (2)
FDI_CTX_PRX_P7 (2)
Deep Sleep not implemented
DPWROK connect to RSMRST#
PCH_DPWROK (40)
PCH_RSMRST#_R
PCH_PCIE_WAKE# (40)
CLKRUN# (39,40)
T55T55
T56T56
T57T57
T58T58
SIO_SLP_S4# (1 8,40)
T59T59
SIO_SLP_S3# (4 0)
T60T60
SIO_SLP_A# (40,69)
T61T61
SIO_SLP_SUS# (40)
T62T62
H_PM_SYNC (2)
SIO_SLP_LAN# (40,49)
PDG v0.7 P166
If the LVDS interface is not implemented,
all signals associated with the interface can
be left as No Connects
R118 *2.2K_NC +/-5%R118 *2.2K_NC +/-5%
R120 *2.2K_NC +/-5%R120 *2.2K_NC +/-5%
4.
R119 2.37K +/-1%R119 2.37K +/-1%
R133 10+/-1%R133 10+/-1%
R134 10+/-1%R134 10+/-1%
R135 1K+/-1%R135 1K+/-1%
PANEL_BKEN_PCH
ENVDD_PCH
LDDC_CLK_PCH
LDDC_DATA_PCH
T54T54
PCH_CRT_BLU
PCH_CRT_GRN
PCH_CRT_RED
PCH_CRT_DDC_CLK
PCH_CRT_DDC_DAT
R138 150 +/ -1%R138 150 +/ -1%
R139 150 +/ -1%R139 150 +/ -1%
R140 150 +/ -1%R140 150 +/ -1%
LVD_VBG
HSYNC
VSYNC
CRT_IREF
PANEL_BKEN_PCH(22)
ENVDD_PCH(22,40)
BIA_PWM_PCH(22)
LDDC_CLK_PCH(22)
LDDC_DATA_PCH(22)
+3.3V_RUN
LCD_ACLK-_PCH(21)
LCD_ACLK+_PCH(21)
LCD_A0-_PCH(21)
LCD_A1-_PCH(21)
LCD_A2-_PCH(21)
LCD_A3-_PCH(21)
LCD_A0+_PCH(21)
LCD_A1+_PCH(21)
LCD_A2+_PCH(21)
LCD_A3+_PCH(21)
LCD_BCLK-_PCH(21)
LCD_BCLK+_PCH(21)
LCD_B0-_PCH(21)
LCD_B1-_PCH(21)
LCD_B2-_PCH(21)
LCD_B3-_PCH(21)
LCD_B0+_PCH(21)
LCD_B1+_PCH(21)
LCD_B2+_PCH(21)
LCD_B3+_PCH(21)
PCH_CRT_BLU(24)
PCH_CRT_GRN(24)
PCH_CRT_RED(24 )
PCH_CRT_DDC_CLK(24)
PCH_CRT_DDC_DAT(24)
PCH_CRT_HSYNC(24)
PCH_CRT_VSYNC(24)
CRT_HSYNC and CRT_VSYNC resistor
33 ohm for Direct Connect
20 ohm for Dock Support
20 ohm for Switchable Graphics Device Down Topology
10 ohm for Switchable Graphics Dock Support
PCH_CRT_BLU
PCH_CRT_GRN
PCH_CRT_RED
+RTC_CELL
COUGAR POINT (LVDS,DDI)
U3D
U3D
J47
L_BKLTEN
M45
L_VDD_EN
P45
L_BKLTCTL
T40
L_DDC_CLK
K47
L_DDC_DATA
T45
L_CTRL_CLK
P39
L_CTRL_DATA
AF37
LVD_IBG
AF36
LVD_VBG
AE48
LVD_VREFH
AE47
LVD_VREFL
AK39
LVDSA_CLK#
AK40
LVDSA_CLK
AN48
LVDSA_DATA#0
AM47
LVDSA_DATA#1
AK47
LVDSA_DATA#2
AJ48
LVDSA_DATA#3
AN47
LVDSA_DATA0
AM49
LVDSA_DATA1
AK49
LVDSA_DATA2
AJ47
LVDSA_DATA3
AF40
LVDSB_CLK#
AF39
LVDSB_CLK
AH45
LVDSB_DATA#0
AH47
LVDSB_DATA#1
AF49
LVDSB_DATA#2
AF45
LVDSB_DATA#3
AH43
LVDSB_DATA0
AH49
LVDSB_DATA1
AF47
LVDSB_DATA2
AF43
LVDSB_DATA3
N48
CRT_BLUE
P49
CRT_GREEN
T49
CRT_RED
T39
CRT_DDC_CLK
M40
CRT_DDC_DATA
M47
CRT_HSYNC
M49
CRT_VSYNC
T43
DAC_IREF
T42
CRT_IRTN
BD82QM67[VER.B3,SLH9B]
BD82QM67[VER.B3,SLH9B]
SDVO_TVCLKINN
SDVO_TVCLKINP
SDVO_STALLN
SDVO_STALLP
SDVO_CTRLCLK
SDVO_CTRLDATA
LVDS
LVDS
DDPC_CTRLCLK
DDPC_CTRLDATA
Digital Display Interface
Digital Display Interface
DDPD_CTRLCLK
DDPD_CTRLDATA
CRT
CRT
PCH_CRT_DDC_DAT
R149 2.2K +/-5%R149 2.2K +/-5%
PCH_CRT_DDC_CLK
R150 2.2K +/-5%R150 2.2K +/-5%
LDDC_CLK_PCH
R1111 2.2K +/-5%R1111 2.2K +/-5%
LDDC_DATA_PCH
R1112 2.2K +/-5%R1112 2.2K +/-5%
Ever Light
Ever Light
Ever Light
Technology Limited
Technology Limited
Technology Limited
Title
Title
Title
07 -- CBT 1/6 (DMI&VIDEO )
07 -- CBT 1/6 (DMI&VIDEO )
07 -- CBT 1/6 (DMI&VIDEO )
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet
1
1A
1A
1A
of
7 84Thursday, Janua ry 27 , 20 11
7 84Thursday, Janua ry 27 , 20 11
7 84Thursday, Janua ry 27 , 20 11
5
WWW.MANUALS.CLAN.SU
D D
INTVRMEN :
Integrated 1.05 V VRM Enable / Disable.
Integrated 1.05 V VRMs is enabled when high
NOTE: This signal should always be pulled high
C C
+RTC_CELL +3.3V_ALW_PCH
R155
R155
330K
330K
+/-5%
+/-5%
PCH_INTVRMEN PCH_AZ_SYNC
R159
R159
*330K_NC
*330K_NC
+/-5%
+/-5%
PLL ODVR VOLTAGE (HDA_SYNC have Internal PD 20k)
LOW - SET VCCVRM TO 1.8 V (DEFAULT)
HDA_SYNC
R156
R156
1K
1K
+/-5%
+/-5%
R160
R160
*100K_NC
*100K_NC
+/-5%
+/-5%
HIGH - SET VCCVRM TO 1.5 V
Audio (need to check)
+3.3V_ALW_PCH
B B
PCH_AZ_CODEC_SDOUT(60)
PCH_AZ_CODEC_SYNC(60)
PCH_AZ_CODEC_RST#(60)
PCH_AZ_CODEC_BITCLK(60)
+3.3V_ALW_PCH
4
R170 210 +/-1%R170 210 +/-1%
R172 210 +/-1%R172 210 +/-1%
R175 210 +/-1%R175 210 +/-1%
R169 51+/-1%R169 51+/-1%
R171 100 +/-1%R171 100 +/-1%
R174 100 +/-1%R174 100 +/-1%
R176 100 +/-1%R176 100 +/-1%
R1129 100K +/-5%R1129 100K +/-5 %
+3.3V_RUN
R1113
R1113
10K
10K
+/-5%
+/-5%
BSS138
+5V_RUN
R157 20K +/-1%R157 20K +/-1%
R161 20K +/-1%R161 20K +/-1%
R163 33+/-5%R163 33+/-5%
R164 33+/-5%R164 33+/-5%
R165 33+/-5%R165 33+/-5%
R166 33+/-5%R166 33+/-5%
C143
C143
27pF
27pF
50V,NPO
50V,NPO
PCH_JTAG_TMS
PCH_JTAG_TDI
PCH_JTAG_TDO
PCH_JTAG_TCK
PCH_JTAG_TMS
PCH_JTAG_TDI
PCH_JTAG_TDO
USB30_SMI#
BSS138
C139
C139
1uF
1uF
6.3V,X5R
6.3V,X5R
C142
C142
1uF
1uF
6.3V,X5R
6.3V,X5R
PCH_AZ_SYNC_G
+RTC_CELL
Direct Connection to S PI ROM
Due to DELL E3 inform ation
1.
Q125
Q125
DS
G
PCH_AZ_SDOUT
PCH_AZ_SYNC_G
PCH_AZ_RST#
PCH_AZ_BITCLK
PCH_AZ_SYNC
+3.3V_M
PCH_SPI_CLK(42)
PCH_SPI_CS0#(4 2)
PCH_SPI_CS1#(4 2)
PCH_SPI_DO(42)
PCH_SPI_DIN(42)
ME_FWP(4 0)
R186
R186
*8.2K_NC
*8.2K_NC
+/-5%
+/-5%
PCH_AZ_CODEC_SDIN0(60)
3
C138 18pF 50V,NPOC138 18pF50V,NPO
C140 18pF 50V,NPOC140 18pF50V,NPO
C141 *27pF_NC 50V,NPOC141 *27pF_ NC 50V,NPO
+3.3V_ALW_PCH
USB30_SMI#(31)
PCH_JTAG_TCK(6)
PCH_JTAG_TMS(6)
PCH_JTAG_TDI(6)
PCH_JTAG_TDO(6)
PCH_SPI_DO
R154 0 +/-5%R154 0 +/-5%
23
Y1
XTAL 32.768KHzY1XTAL 32.768KHz
4 1
R162 1M +/-5 %R1 62 1M +/-5 %
SPKR(60 )
R167 *1K_NC +/-5%R167 *1K_NC +/-5%
R168 1K +/ -5%R168 1 K +/-5%
T63T63
T64T64
T65T65
T66T66
R178 0 +/-5%R178 0 +/-5%
R180 0 +/-5%R180 0 +/-5%
R181 0 +/-5%R181 0 +/-5%
PCH_SPI_DO
R182 0 +/-5%R182 0 +/-5%
R184 0 +/-5%R184 0 +/-5%
No series resistor required
if routing length is 1.5”-6.5” if using 1 SPI d evice
Cougar Point (HDA,JTAG,SATA)
R158
R158
10M
10M
+/-5%
+/-5%
PCH_AZ_BITCLK
PCH_AZ_SYNC
SPKR
PCH_AZ_RST#
PCH_AZ_SDOUT
USB30_SMI#
PCH_RTCRST#
SRTCRST#
INTRUDER#
PCH_INTVRMEN
T67T67
PCH_JTAG_TCK
PCH_JTAG_TMS
PCH_JTAG_TDI
PCH_JTAG_TDO
PCH_SPI_CLK_R
PCH_SPI_CS0#_R
PCH_SPI_CS1#_R
PCH_SPI_SI_R
PCH_SPI_SO_R
PCH_RTCX1
PCH_RTCX2
U3A
U3A
A20
RTCX1
C20
RTCX2
D20
RTCRST#
G22
SRTCRST#
K22
INTRUDER#
C17
INTVRMEN
N34
HDA_BCLK
L34
HDA_SYNC
T10
SPKR
K34
HDA_RST#
E34
HDA_SDIN0
G34
HDA_SDIN1
C34
HDA_SDIN2
A34
HDA_SDIN3
A36
HDA_SDO
C36
HDA_DOCK_EN# / GPIO33
N32
HDA_DOCK_RST# / GPIO13
J3
JTAG_TCK
H7
JTAG_TMS
K5
JTAG_TDI
H1
JTAG_TDO
T3
SPI_CLK
Y14
SPI_CS0#
T1
SPI_CS1#
V4
SPI_MOSI
U3
SPI_MISO
BD82QM67[VER.B3,SLH9B]
BD82QM67[VER.B3,SLH9B]
HDD_DET#_R
BBS_BIT0_R
2
LPC
LPC
FWH4 / LFRAME #
LDRQ1# / GPIO23
RTCIHDA
RTCIHDA
SATA 6G
SATA 6G
SATA
SATA
SATAICOMPO
JTAG
JTAG
SATA3RCOMPO
SPI
SPI
SATA0GP / GPIO21
SATA1GP / GPIO19
R187 10K +/-5%R187 10K +/-5 %
R188 10K +/-5%R188 10K +/-5 %
FWH0 / LAD0
FWH1 / LAD1
FWH2 / LAD2
FWH3 / LAD3
LDRQ0#
SERIRQ
SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP
SATA1RXN
SATA1RXP
SATA1TXN
SATA1TXP
SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP
SATA3RXN
SATA3RXP
SATA3TXN
SATA3TXP
SATA4RXN
SATA4RXP
SATA4TXN
SATA4TXP
SATA5RXN
SATA5RXP
SATA5TXN
SATA5TXP
SATAICOMPI
SATA3COMPI
SATA3RBIAS
SATALED#
+3.3V_RUN
+3.3V_RUN
C38
A38
B37
C37
D36
E36
K36
V5
AM3
AM1
AP7
AP5
AM10
AM8
AP11
AP10
AD7
AD5
AH5
AH4
AB8
AB10
AF3
AF1
Y7
Y5
AD3
AD1
Y3
Y1
AB3
AB1
Y11
Y10
AB12
AB13
AH1
P3
V14
P1
IRQ_SERIRQ
HDD_DET#_R
SATA_COMP
Width = 10 mil, Spacing = 20 mil
Close PCH within 500 mil
SATA3_COMP
RBIAS_SATA3
SATA_ACT# (44)
R183 0 +/-5%R183 0 +/-5%
BBS_BIT0_R
R185 0 +/-5%R185 0 +/-5%
LPC_LAD0 (34,39,40,55)
LPC_LAD1 (34,39,40,55)
LPC_LAD2 (34,39,40,55)
LPC_LAD3 (34,39,40,55)
LPC_LFRAME# (34,39,4 0,55)
LPC_LDRQ0# (40)
LPC_LDRQ1# (40)
IRQ_SERIRQ (39,40,55)
PSATA_PRX_DTX_N0_C (28)
PSATA_PRX_DTX_P0_C (28)
PSATA_PTX_DRX_N0_C (28)
PSATA_PTX_DRX_P0_C (28)
PSATA_PRX_DTX_N1_C (28)
PSATA_PRX_DTX_P1_C (28)
PSATA_PTX_DRX_N1_C (28)
PSATA_PTX_DRX_P1_C (28)
SATA_PRX_WWANTX_N2_C (37)
SATA_PRX_WWANTX_P2_C (37)
SATA_PTX_WWANRX_N2_C (37)
SATA_PTX_WWANRX_P2_C (37)
SATA_ODD_PRX_DTX_N3_C (28 )
SATA_ODD_PRX_DTX_P3_C (28)
SATA_ODD_PTX_DRX_N3_C (28 )
SATA_ODD_PTX_DRX_P3_C (28)
ESATA_PRX_DTX_N4_C (30)
ESATA_PRX_DTX_P4_C (30)
ESATA_PTX_DRX_N4_C (30)
ESATA_PTX_DRX_P4_C (30)
SATA_PRX_DKTX_N5_C (27)
SATA_PRX_DKTX_P5_C (27)
SATA_PTX_DKRX_N5_C (27)
SATA_PTX_DKRX_P5_C (27)
+1.05V_RUN
R173 37.4 +/-1%R1 73 37.4 +/ -1%
+1.05V_RUN
R177 49.9 +/-1%R1 77 49.9 +/ -1%
R179 750 +/-1 %R1 79 750 +/-1%
G
D S
2N7002W-7-F
2N7002W-7-F
Q27
Q27
1
HDD 1st
HDD 2nd
MINI CARD
ODD
E-SATA
Docking
HDD_DET# (28)
HDD_DET#_R (6)
BBS_BIT0_R (6,9)
PCH_PLTRST2# (9,11,33,34,3 6,37,39,40)
HDD2_DET# (28 )
R190
R190
R189
R189
*10K_NC
*10K_NC
10K
10K
+/-5%
+/-5%
+/-5%
A A
5
4
3
No Reboot strap.
Low = Default.
SPKR
High = No Reboot.
Note1, Sampled at rising edge of PWROK
The signa l has a wea k inte rnal pull- down.
(the internal pull-down is disabled after PLTRST# deasserts.)
If the signal is sampled high, this indicate that
the system is strapped to the "No Reboot" mode
IRQ_SERIRQ
SPKR
+/-5%
Ever Light
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Technology Limited
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Technology Limited
Title
Title
Title
08 -- CBT 2/6 (SATA)
08 -- CBT 2/6 (SATA)
08 -- CBT 2/6 (SATA)
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
2
Date: Sheet
1
of
8 84Thursday, Janua ry 27 , 20 11
8 84Thursday, Janua ry 27 , 20 11
8 84Thursday, Janua ry 27 , 20 11
1A
1A
1A
5
WWW.MANUALS.CLAN.SU
4
3
2
1
Cougar Point (PCI,USB,NVRAM)
R191 *1K_NC +/-5%R1 91 *1K_NC +/-5%
R192 *1K_NC +/-5%R1 92 *1K_NC +/-5%
D D
Boot BIOS Stra p
BBS_BIT[0]BBS_BIT[1]
0 0
0
1
0
1
1 1
C C
EMI request
B B
A A
C778
C778
*10pF_NC
*10pF_NC
50V,NPO
50V,NPO
PCI_REQ1#
PCI_REQ3#
PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
PCI_REQ2#
CAM_MIC_CBL_DET#
C779
C779
*10pF_NC
*10pF_NC
50V,NPO
50V,NPO
Boot BIOS Location
LPC
Reserved (NAND)
PCI
SPI
C790
C790
*10pF_NC
*10pF_NC
50V,NPO
50V,NPO
R209 10K +/-5%R209 10 K +/-5 %
R213 10K +/-5%R213 10 K +/-5 %
R214 8.2K +/-5%R21 4 8.2K +/-5%
R215 8.2K +/-5%R21 5 8.2K +/-5%
R216 8.2K +/-5%R21 6 8.2K +/-5%
R217 8.2K +/-5%R21 7 8.2K +/-5%
R1105 10K +/-5%R1105 10K +/-5%
R1917 10K +/-5%R1917 10K +/-5%
5
BBS_BIT0_R (6,8)
BBS_BIT1
CLK_PCI0
CLK_PCI1
CLK_PCI2
CLK_PCI4
C811
C811
*10pF_NC
*10pF_NC
50V,NPO
50V,NPO
+3.3V_RUN
5.
GNT2# : Strap for ESI mode
This si gnal has a we ak int ernal p ull-up.
Note : The int erna l pull- up is dis able
after PLTRST# deasserts.
Tying thi s st rap low confi gures DMI fo r
ESI compatible opeartion.
Note : ESI compatible mode is for server
platform only .
This si gnal sho uld not be pulled low fo r
desktop a nd mobile.
REQ# functionality is not available on Mobile
GNT# functionality i s not avai lable on Mobile
PIRQ[H:E]# functionality is not available on Mobile
CLK_DEBUG(34)
CLK_PCI_5048(40)
CLK_PCI_5055(39)
CLK_PCI_DOCK(27)
CLK_PCI_LOOPBACK(10)
PCH_PLTRST1#(6,19, 31,49,55)
R218 *1K_NC +/-1%R2 18 *1K_NC +/-1%
A16 swap override Strap/Top-Block
Swap Override j umper
Low = A16 swap
override/Top-Block
GNT3#
Swap Override enabled
High = Default
U3E
U3E
BG26
TP1
BJ26
TP2
BH25
TP3
BJ16
TP4
BG16
TP5
AH38
TP6
AH37
TP7
AK43
TP8
AK45
TP9
C18
TP10
N30
TP11
H3
TP12
AH12
TP13
AM4
TP14
AM5
TP15
Y13
TP16
K24
TP17
L24
TP18
AB46
TP19
AB45
TP20
RSVD
TP21
TP22
TP23
TP24
TP25
TP26
TP27
TP28
TP29
TP30
TP31
TP32
TP33
TP34
TP35
TP36
TP37
TP38
TP39
TP40
PIRQA#
PIRQB#
PIRQC#
PIRQD#
REQ1# / GPIO50
REQ2# / GPIO52
REQ3# / GPIO54
GNT1# / GPIO51
GNT2# / GPIO53
GNT3# / GPIO55
PIRQE# / GPIO2
PIRQF# / GPIO3
PIRQG# / GPIO4
PIRQH# / GPIO5
PME#
C6
PLTRST#
CLKOUT_PCI0
CLKOUT_PCI1
CLKOUT_PCI2
CLKOUT_PCI3
CLKOUT_PCI4
BD82QM67[VER.B3,SLH9B]
BD82QM67[VER.B3,SLH9B]
PCH_PLTRST1#
RSVD
PCI
PCI
R1106
R1106
100K
100K
+/-5%
+/-5%
USB
USB
3
B21
M20
AY16
BG46
BE28
BC30
BE32
BJ32
BC28
BE30
BF32
BG32
AV26
BB26
AU28
AY30
AU26
AY26
AV28
AW30
FFS_PCH_INT
CLK_PCI0
CLK_PCI1
CLK_PCI2
CLK_PCI4
+3.3V_RUN
U4
K40
K38
H38
G38
C46
C44
E40
D47
E42
F46
G42
G40
C42
D44
K10
H49
H43
J48
K42
H40
2
1
PCH_PLTRST#
3 5
PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
PCI_REQ1#
PCI_REQ2#
PCI_REQ3#
BBS_BIT1
PCI_GNT3#
CAM_MIC_CBL_DET#(22)
HDD_FAL L_I NT(28)
PCI_GNT3#
CAM_MIC_CBL_DET#
R194 0 +/-5%R1 94 0 +/-5%
T103T103
PCH_PLTRST#
PCH_PLTRST#(2)
R1107 22+/-1%R1107 22+/-1%
R198 22+/-1%R198 22+/-1%
R199 22+/-1%R199 22+/-1%
R200 22+/-1%R200 22+/-1%
R202 22+/-1%R202 22+/-1%
C144 0.1uF
C144 0.1uF
16V,Y5V
16V,Y5V
4
PCH_PLTRST1#
74AHC1G08GWU474AHC1G08GW
PLTRST_IOL#(60)
4
R204 0 +/-5%R204 0 +/-5%
PLTRST1# for USH, OZ600, EXP, XDP, LAN, USB3.0, MXM.
AY7
RSVD1
AV7
RSVD2
AU3
RSVD3
BG4
RSVD4
AT10
RSVD5
BC8
RSVD6
AU2
RSVD7
AT4
RSVD8
AT3
RSVD9
AT1
RSVD10
AY3
RSVD11
AT5
RSVD12
AV3
RSVD13
AV1
RSVD14
BB1
RSVD15
BA3
RSVD16
BB5
RSVD17
BB3
RSVD18
BB7
RSVD19
BE8
RSVD20
BD4
RSVD21
BF6
RSVD22
AV5
RSVD23
AV10
RSVD24
AT8
RSVD25
AY5
RSVD26
BA2
RSVD27
AT12
RSVD28
BF3
RSVD29
C24
USBP0N
A24
USBP0P
C25
USBP1N
B25
USBP1P
C26
USBP2N
A26
USBP2P
K28
USBP3N
H28
USBP3P
E28
USBP4N
D28
USBP4P
C28
USBP5N
A28
USBP5P
C29
USBP6N
B29
USBP6P
N28
USBP7N
M28
USBP7P
L30
USBP8N
K30
USBP8P
G30
USBP9N
E30
USBP9P
C30
USBP10N
A30
USBP10P
L32
USBP11N
K32
USBP11P
G32
USBP12N
E32
USBP12P
C32
USBP13N
A32
USBP13P
C33
USBRBIAS
USBRBIAS#
B33
USBRBIAS
A14
USB_OC0#_R
OC0# / GPIO59
K20
USB_OC1#_R
OC1# / GPIO40
B17
OC2# / GPIO41
C16
OC3# / GPIO42
L16
OC4# / GPIO43
A16
OC5# / GPIO9
D14
OC6# / GPIO10
C14
OC7# / GPIO14
C145 0.1uF
C145 0.1uF
16V,Y5V
16V,Y5V
PCH_PLTRST#
PLTRST2# for 5055,5028,WLAN,PP,WWAN,NVRAM.
USBP0- (60)
USBP0+ (60)
USBP1- (60)
USBP1+ (60)
USBP2- (30)
USBP2+ (30)
USBP4- (33)
USBP4+ (33)
USBP5- (36)
USBP5+ (36)
USBP6- (34)
USBP6+ (3 4)
USBP7- (55)
USBP7+ (5 5)
USBP8- (27)
USBP8+ (27)
USBP9- (27)
USBP9+ (27)
USBP10- (60)
USBP10+ (60)
USBP11- (33)
USBP11+ (33)
USBP12- (22)
USBP12+ (22)
USBP13- (22)
R193 22.6 +/-1%R193 22.6 +/-1 %
Net USB_BIAS route impedacnes should be 50-ohm
and length less than 500-mil spacing is 15-mil.
R195 0 +/-5%R195 0 +/-5%
R196 0 +/-5%R196 0 +/-5%
+3.3V_RUN
U5
2
1
74AHC1G08GWU574AHC1G08GW
3 5
USBP13+ (22)
USB_OC0# (60)
USB_OC1# (30)
USB_OC2#
USB_OC2# (6)
USB_OC3#
USB_OC3# (6)
USB_OC4#
USB_OC4# (6)
USB_OC5#
USB_OC5# (6)
USB_OC6#
USB_OC6# (6)
SIO_EXT_SMI#
SIO_EXT_SMI# (6,39)
USB_OC0#_R (6)
USB_OC1#_R (6)
Add Buffers as needed for
Loading and fanout concerns.
4
PCH_PLTRST2#
PCH_PLTRST2#
R1108
R1108
100K
100K
+/-5%
+/-5%
2
Right Side pair top
Right Side pair bottom
Back Side
AUX m odule (Rem oved)
2nd Mini Card (WLAN/WIMAX)
1st Mini Card (WWAN)
3rd Mini Card
USH
DOCK
DOCK
Express Card
BlueT ooth
Camera
LCD Touch or Nvidia 3D IR
USB_OC0#
USB_OC1#
USB_OC3#
USB_OC4#
SIO_EXT_SMI#
USB_OC6#
USB_OC5#
USB_OC2#
PCH_PLTRST2# (8,11,33,34,3 6,37,39,40)
+3.3V_ALW_PCH
RN1
RN1
1
2
3
4
5
6
7 8
10K
10K
+/-5%
+/-5%
RN2
RN2
1
2
3
4
5
6
7 8
10K
10K
+/-5%
+/-5%
Ever Light
Ever Light
Ever Light
Technology Limited
Technology Limited
Technology Limited
Title
Title
Title
09 -- CBT 3/6 (USB, PCI, NVRAM)
09 -- CBT 3/6 (USB, PCI, NVRAM)
09 -- CBT 3/6 (USB, PCI, NVRAM)
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet
1
of
9 84Thursday, Janua ry 27 , 20 11
9 84Thursday, Janua ry 27 , 20 11
9 84Thursday, Janua ry 27 , 20 11
1A
1A
1A
5
WWW.MANUALS.CLAN.SU
PCIE_PRX_WANTX_N1(36)
1st Mini Card WWAN
D D
2ed Mini Card WLAN
Express Card
USB 3.0
3rd Mini-Card
4th Mini-Card
LAN
Card Reader
1st Mini Card WWAN
C C
10/100/LAN
Card Reader
3rd Mini-Card
Express Card
2nd Mini Card WLAN
4th Mini-Card
B B
USB 3.0
A A
PCIE_PRX_WANTX_P1(36)
PCIE_PTX_WANRX_N1_C(36)
PCIE_PTX_WANRX_P1_C(36)
PCIE_PRX_WLANTX_N2(33)
PCIE_PRX_WLANTX_P2(33)
PCIE_PTX_WLANRX_N2_C(33)
PCIE_PTX_WLANRX_P2_C(33)
PCIE_PRX_EXPTX_N3(60)
PCIE_PRX_EXPTX_P3(60)
PCIE_PTX_EXPRX_N3_C(60)
PCIE_PTX_EXPRX_P3_C(60)
PCIE_PRX_USB30TX_N4(31)
PCIE_PRX_USB30TX_P4(31)
PCIE_PTX_USB30RX_N4_C(31)
PCIE_PTX_USB30RX_P4_C(31)
PCIE_PRX_CARDTX_N5(34)
PCIE_PRX_CARDTX_P5(34 )
PCIE_PTX_CARDRX_N5_C(34)
PCIE_PTX_CARDRX_P5_C(3 4)
PCIE_PRX_CARDTX_N6(37)
PCIE_PRX_CARDTX_P6(37 )
PCIE_PTX_CARDRX_N6_C(37)
PCIE_PTX_CARDRX_P6_C(3 7)
PCIE_PRX_GLANTX_N7(49)
PCIE_PRX_GLANTX_P7(49)
PCIE_PTX_GLANRX_N7_C(49)
PCIE_PTX_GLANRX_P7_C(49)
PCIE_PRX_CARDTX_N8(60)
PCIE_PRX_CARDTX_P8(60 )
PCIE_PTX_CARDRX_N8_C(60)
PCIE_PTX_CARDRX_P8_C(6 0)
CLK_PCIE_MINI1#(36)
CLK_PCIE_MINI1(36)
+3.3V_ALW_PCH
MINI1CLK_REQ#(36)
CLK_PCIE_LAN#(49)
CLK_PCIE_LAN(4 9)
LANCLK_REQ#(49)
CLK_PCIE_CARD#(60)
CLK_PCIE_CARD(60)
+3.3V_RUN
CARDCLK_REQ#(60)
CLK_PCIE_MINI3#(34)
CLK_PCIE_MINI3(34)
+3.3V_ALW_PCH
MINI3CLK_REQ#(34)
CLK_PCIE_EXP#(60)
CLK_PCIE_EXP(60)
+3.3V_RUN
EXPCLK_REQ#(60)
CLK_PCIE_MINI2#(33)
CLK_PCIE_MINI2(33)
+3.3V_RUN
MINI2CLK_REQ#(33)
CLK_PCIE_MINI4#(37)
CLK_PCIE_MINI4(37)
+3.3V_ALW_PCH
MINI4CLK_REQ#(37)
+3.3V_ALW_PCH
CLK_PCIE_USB30#(31)
CLK_PCIE_USB30(3 1)
+3.3V_ALW_PCH
USB30CLK_REQ#(31)
CLK_CPU_ITP#(6 )
CLK_CPU_ITP(6)
4
Cougar Point (PCI-E,SMBUS,CLK)
U3B
Place TX DC blocking caps close PCH.
10K+/-1%
10K+/-1%
PCIE_PTX_WANRX_N1
PCIE_PTX_WANRX_P1
PCIE_PTX_WLANRX_N2
PCIE_PTX_WLANRX_P2
PCIE_PTX_EXPRX_N3
PCIE_PTX_EXPRX_P3
PCIE_PTX_USB30RX_N4
PCIE_PTX_USB30RX_P4
PCIE_PTX_CARDRX_N5
PCIE_PTX_CARDRX_P5
PCIE_PTX_CARDRX_N6
PCIE_PTX_CARDRX_P6
PCIE_PTX_GLANRX_N7
PCIE_PTX_GLANRX_P7
PCIE_PTX_CARDRX_N8
PCIE_PTX_CARDRX_P8
CLK_PCIE_MINI1#_C
CLK_PCIE_MINI1_C
CLK_PCIE_LAN#_C
CLK_PCIE_LAN_C
CLK_PCIE_CARD#_C
CLK_PCIE_CARD_C
CLK_PCIE_MINI3#_C
CLK_PCIE_MINI3_C
CLK_PCIE_EXP#_C
CLK_PCIE_EXP_C
CLK_PCIE_MINI2#_C
CLK_PCIE_MINI2_C
CLK_PCIE_MINI4#_C
CLK_PCIE_MINI4_C
CLK_PCIE_USB30#_C
CLK_PCIE_USB30_C
CLK_BCLK_ITP#
CLK_BCLK_ITP
C152 0.1uF 16V,X7RC152 0.1uF 16V,X7R
C153 0.1uF 16V,X7RC153 0.1uF 16V,X7R
C146 0.1uF 16V,X7RC146 0.1uF 16V,X7R
C154 0.1uF 16V,X7RC154 0.1uF 16V,X7R
C147 0.1uF 16V,X7RC147 0.1uF 16V,X7R
C155 0.1uF 16V,X7RC155 0.1uF 16V,X7R
C148 0.1uF 16V,X7RC148 0.1uF 16V,X7R
C149 0.1uF 16V,X7RC149 0.1uF 16V,X7R
C150 0.1uF 16V,X7RC150 0.1uF 16V,X7R
C151 0.1uF 16V,X7RC151 0.1uF 16V,X7R
C156 0.1uF 16V,X7RC156 0.1uF 16V,X7R
C157 0.1uF 16V,X7RC157 0.1uF 16V,X7R
C158 0.1uF 16V,X7RC158 0.1uF 16V,X7R
C159 0.1uF 16V,X7RC159 0.1uF 16V,X7R
C160 0.1uF 16V,X7RC160 0.1uF 16V,X7R
C161 0.1uF 16V,X7RC161 0.1uF 16V,X7R R228 2.2K +/-5%R228 2.2K +/-5%
R229 0 +/-5%R2 29 0 +/-5%
R230 0 +/-5%R2 30 0 +/-5%
R231 10K +/-5%R231 10K +/-5 %
R257 0 +/-5%R2 57 0 +/-5%
R258 0 +/-5%R2 58 0 +/-5%
PU at 82579
R261 0 +/-5%R2 61 0 +/-5%
R262 0 +/-5%R2 62 0 +/-5%
R263
R263
R250 0 +/-5%R2 50 0 +/-5%
R251 0 +/-5%R2 51 0 +/-5%
R252 10K +/-5%R252 10K +/-5 %
R240 0 +/-5%R2 40 0 +/-5%
R242 0 +/-5%R2 42 0 +/-5%
R243 10K +/-5%R243 10K +/-5 %
R233 0 +/-5%R2 33 0 +/-5%
R235 0 +/-5%R2 35 0 +/-5%
R236 10K +/-5%R236 10K +/-5 %
R253 0 +/-5%R2 53 0 +/-5%
R254 0 +/-5%R2 54 0 +/-5%
R255 10K +/-5%R255 10K +/-5 %
R267 10K +/-5%R267 10K +/-5 %
R247 0 +/-5%R2 47 0 +/-5%
R248 0 +/-5%R2 48 0 +/-5%
R249 10K +/-5%R249 10K +/-5 %
R265 0 +/-5%R265 0 +/-5%
R266 0 +/-5%R266 0 +/-5%
PCIE REQ power rai l:
suspend: 0 3 4 5 6 7
core: 1 2
U3B
BG34
PERN1
BJ34
PERP1
AV32
PETN1
AU32
PETP1
BE34
PERN2
BF34
PERP2
BB32
PETN2
AY32
PETP2
BG36
PERN3
BJ36
PERP3
AV34
PETN3
AU34
PETP3
BF36
PERN4
BE36
PERP4
AY34
PETN4
BB34
PETP4
BG37
PERN5
BH37
PERP5
AY36
PETN5
BB36
PETP5
BJ38
PERN6
BG38
PERP6
AU36
PETN6
AV36
PETP6
BG40
PERN7
BJ40
PERP7
AY40
PETN7
BB40
PETP7
BE38
PERN8
BC38
PERP8
AW38
PETN8
AY38
PETP8
Y40
CLKOUT_PCIE0N
Y39
CLKOUT_PCIE0P
J2
PCIECLKRQ0# / GPIO73
AB49
CLKOUT_PCIE1N
AB47
CLKOUT_PCIE1P
M1
PCIECLKRQ1# / GPIO18
AA48
CLKOUT_PCIE2N
AA47
CLKOUT_PCIE2P
V10
PCIECLKRQ2# / GPIO20
Y37
CLKOUT_PCIE3N
Y36
CLKOUT_PCIE3P
A8
PCIECLKRQ3# / GPIO25
Y43
CLKOUT_PCIE4N
Y45
CLKOUT_PCIE4P
L12
PCIECLKRQ4# / GPIO26
V45
CLKOUT_PCIE5N
V46
CLKOUT_PCIE5P
L14
PCIECLKRQ5# / GPIO44
AB42
CLKOUT_PEG_B_N
AB40
CLKOUT_PEG_B_P
E6
PEG_B_CLKRQ# / GPIO56
V40
CLKOUT_PCIE6N
V42
CLKOUT_PCIE6P
T13
PCIECLKRQ6# / GPIO45
V38
CLKOUT_PCIE7N
V37
CLKOUT_PCIE7P
K12
PCIECLKRQ7# / GPIO46
AK14
CLKOUT_ITPXDP_N
AK13
CLKOUT_ITPXDP_P
BD82QM67[VER.B3,SLH9B]
BD82QM67[VER.B3,SLH9B]
SMBUSController
SMBUSController
SML1ALERT# / PCHHOT# / GPIO74
PCI-E*
PCI-E*
CLOCKS
CLOCKS
3
SMBALERT# / GPIO11
SML0ALERT# / GPIO60
SML1CLK / GPIO58
SML1DATA / GPIO75
Link
Link
PEG_A_CLKRQ# / GPIO47
CLKOUT_PEG_A_N
CLKOUT_PEG_A_P
CLKOUT_DMI_N
CLKOUT_DMI_P
CLKIN_DOT_96N
CLKIN_DOT_96P
CLKIN_PCILOOPBACK
CLKOUTFLEX0 / GPIO64
CLKOUTFLEX1 / GPIO65
CLKOUTFLEX2 / GPIO66
CLKOUTFLEX3 / GPIO67
FLEX CLOCKS
FLEX CLOCKS
SMBCLK
SMBDATA
SML0CLK
SML0DATA
CL_CLK1
CL_DATA1
CL_RST1#
CLKOUT_DP_N
CLKOUT_DP_P
CLKIN_DMI_N
CLKIN_DMI_P
CLKIN_GND1_N
CLKIN_GND1_P
CLKIN_SATA_N
CLKIN_SATA_P
REFCLK14IN
XTAL25_IN
XTAL25_OUT
XCLK_RCOMP
E12
H14
C9
A12
C8
G12
C13
E14
M16
M7
T11
P10
M10
AB37
AB38
AV22
AU22
AM12
AM13
BF18
BE18
BJ30
BG30
G24
E24
AK7
AK5
K45
H45
V47
V49
Y47
K43
F47
H47
K49
XCLK_RCOMP
CLKOUTFLEX0
CLKOUTFLEX1
CLKOUTFLEX2
CLKOUTFLEX3
PCH_SMB_ALERT#
PCH_SMBCLK
PCH_SMBDAT
DDR_HVREF_RST_PCH
LAN_SMBCLK
LAN_SMBDATA
GPIO74
SML1_SMBCLK
SML1_SMBDAT
PEG_CLKREQ#
CLK_BUF_EXP#
CLK_BUF_EXP
CLK_BUF_BCLK#
CLK_BUF_BCLK
CLK_BUF_DOT96#
CLK_BUF_DOT96
CLK_BUF_CKSSCD#
CLK_BUF_CKSSCD
CLK_PCH_14M
XTAL25_IN
XTAL25_OUT
Width = 10 mil, Spacing = 20 mil
Close PCH within 500 mil
DDR_HVREF_RST_PCH (2)
LAN_SMBCLK (49)
LAN_SMBDATA (49)
SML1_SMBCLK (39)
SML1_SMBDAT (39)
PCH_CL_CLK1 (33)
PCH_CL_DATA1 (33 )
PCH_CL_RST1# (3 3)
PEG_CLKREQ# (19)
CLK_PCIE_PEG# (19)
CLK_PCIE_PEG (19)
CLK_CPU_DMI# (2)
CLK_CPU_DMI (2)
CLK_PCI_LOOPBACK (9)
R260 90.9Ohm +/-1%R260 90.9Ohm +/-1%
T105T105
R264 22+/-1%R264 22+/-1%
R201 22+/-1%R201 22+/-1%
T107T107
+1.05V_RUN
CLK_SIO_14M (40)
CLK_PCI_TPM (55)
2
PCH_SMBDAT
PCH_SMBCLK
R1077 *0_NC +/-5%R1077 *0_NC +/-5%
D S
Q123
Q123
2N7002W-7-F
2N7002W-7-F
Q124
Q124
2N7002W-7-F
2N7002W-7-F
D S
R1078 *0_NC +/-5%R1078 *0_NC +/-5%
XTAL25_IN
XTAL25_OUT
G
G
LAN_SMBCLK
LAN_SMBDATA
PEG_CLKREQ#
PCH_SMB_ALERT#
PCH_SMBCLK
PCH_SMBDAT
GPIO74
DDR_HVREF_RST_PCH
SML1_SMBCLK
SML1_SMBDAT
CLK_BUF_EXP#
CLK_BUF_EXP
CLK_BUF_BCLK#
CLK_BUF_BCLK
CLK_BUF_DOT96#
CLK_BUF_DOT96
CLK_BUF_CKSSCD#
CLK_BUF_CKSSCD
CLK_PCH_14M
CLOCK TERMINATION for FCIM
R256 0 +/-5%R256 0 +/-5%
R259
R259
1M
1M
+/-5%
+/-5%
R1080
R1080
10K
10K
+/-5%
+/-5%
R1081
R1081
10K
10K
+/-5%
+/-5%
R219 2.2K +/-5%R219 2.2K +/-5%
R220 2.2K +/-5%R220 2.2K +/-5%
R221 10K +/-5%R221 10K +/-5 %
R222 10K +/-5%R222 10K +/-5 %
R223 2.2K +/-5%R223 2.2K +/-5%
R224 2.2K +/-5%R224 2.2K +/-5%
R647 10K +/-5%R647 10K +/-5 %
R226 1K +/ -1%R226 1K +/-1%
R227 2.2K +/-5%R227 2.2K +/-5%
R232 10K +/-5%R232 10K +/-5 %
R234 10K +/-5%R234 10K +/-5 %
R237 10K +/-5%R237 10K +/-5 %
R238 10K +/-5%R238 10K +/-5 %
R239 10K +/-5%R239 10K +/-5 %
R241 10K +/-5%R241 10K +/-5 %
R244 10K +/-5%R244 10K +/-5 %
R245 10K +/-5%R245 10K +/-5 %
R246 10K +/-5%R246 10K +/-5 %
XTA25L_IN_R
MEM_SMBDAT (6,14,15, 16,17,18,28,36)
+3.3V_RUN
MEM_SMBCLK (6,14 ,15,16,17,18,28,36)
1
+3.3V_LAN
+3.3V_ALW_PCH
C162 30pF50V,NPOC162 30pF50V,NPO
X1
XTAL 25MHzX1XTAL 25MHz
1 2
C163 30pF50V,NPOC163 30pF50V,NPO
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Title
Title
10 -- CBT 4/7 (PCIE, CL K)
10 -- CBT 4/7 (PCIE, CL K)
10 -- CBT 4/7 (PCIE, CL K)
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet
1
1A
1A
1A
of
10 84Thursday , Ja nuary 27, 2 011
10 84Thursday , Ja nuary 27, 2 011
10 84Thursday , Ja nuary 27, 2 011
5
WWW.MANUALS.CLAN.SU
+3.3V_ALW_PCH
SLP_ME_CSW_DEV#
Ra
PCH_SATA_MOD_EN#(28)
SIO_EXT_WAKE#
PCH_GPIO1
PCH_GPIO1
R299 0 +/-5%R299 0 +/-5%
PCH_PLTRST2#(8,9,33,34,36,37,39,40)
R283 10K +/-5%R283 10 K +/-5 %
SLP_ME_CSW_DEV#(6,40)
DS
Q28
Q28
2N7002W-7-F
2N7002W-7-F
G
R295 10K +/-5%R295 10 K +/-5 %
R270 *1K_NC +/-1%R270 *1K_NC +/-1%
D D
+3.3V_ALW_PCH
R790
R790
4.7K
4.7K
+/-5%
+/-5%
R276
R276
*1K_NC
*1K_NC
+/-1%
+/-1%
PLL ON DIE VR ENABLE
ENABLED - HIGH (Ra UNSTUFFED) DEFAULT
DISABLED - LOW (Ra STUFFED)
C C
EC_PCH_SATA_MOD_EN#(28,39)
GPIO15 (SIO_EXT_WAKE#)
Low - Intel ME Crypto Transport Layer Security (TLS)
cipher suite with no confidentiality
High - Intel ME Crypto Transport Layer Security (TLS)
cipher suite with confidentiality
B B
R304 *100K_NC +/-1%R304 *100K_NC +/-1%
FDI_OVRVLTG
FDI TERMINATION VOLTAGE OVERRIDE
GPIO37
(FDI_OVRVLTG)
LOW - Tx, Rx terminated
to same voltage
(DC Coupling Mode)
DEFAULT
+3.3V_RUN
SIO_EXT_SCI#_R(6)
SIO_EXT_SCI#(39)
IOL_DET#(60)
MXM_PRESENT1#(19)
SIO_EXT_WAKE#(40)
PM_LANPHY_ENABLE(49)
PCH_GPIO15(6)
PCH_GPIO16(6)
SLP_ME_CSW_DEV#
DGPU_HOLD_RST#(19)
PCH_GPIO35(6)
GPIO36(6)
FDI_OVRVLTG(6)
R296 0 +/-5%R296 0 +/-5%
4
3
2
1
COUGAR POINT (GPIO,VSS_NCTF,RSVD)
U3F
U3F
TPM_ID0(6 0)
TPM_ID1(6 0)
TEMP_ALERT#
KB_DET#
T7
BMBUSY# / GPIO0
A42
TACH1 / GPIO1
H36
TACH2 / GPIO6
E38
TACH3 / GPIO7
C10
GPIO8
C4
LAN_PHY_PWR_CTRL / GPIO12
G2
GPIO15
U2
SATA4GP / GPIO16
D40
TACH0 / GPIO17
T5
SCLOCK / GPIO22
E8
GPIO24 / MEM_LED
E16
GPIO27
P8
GPIO28
K1
STP_PCI# / GPIO34
K4
GPIO35
V8
SATA2GP / GPIO36
M5
SATA3GP / GPIO37
N2
SLOAD / GPIO38
M3
SDATAOUT0 / GPIO39
V13
SDATAOUT1 / GPIO48
V3
SATA5GP / GPIO49
D6
GPIO57
A4
VSS_NCTF_1
A44
VSS_NCTF_2
A45
VSS_NCTF_3
A46
VSS_NCTF_4
A5
VSS_NCTF_5
A6
VSS_NCTF_6
B3
VSS_NCTF_7
B47
VSS_NCTF_8
BD1
VSS_NCTF_9
BD49
VSS_NCTF_10
BE1
VSS_NCTF_11
BE49
VSS_NCTF_12
BF1
VSS_NCTF_13
BF49
VSS_NCTF_14
BD82QM67[VER.B3,SLH9B]
BD82QM67[VER.B3,SLH9B]
GPIO
GPIO
NCTF
NCTF
R275 0 +/-5%R2 75 0 +/-5%
PCH_GPIO1
IOL_DET#
MXM_PRESENT1#
SIO_EXT_WAKE#
PCH_GPIO15
PCH_GPIO16
GPIO17
GPIO22
T110T110
GPIO27
GPIO36
FDI_OVRVLTG
FFS_INT2(28)
TEMP_ALERT#(6, 40)
KB_DET#(41)
TACH4 / GPIO68
TACH5 / GPIO69
TACH6 / GPIO70
TACH7 / GPIO71
A20GATE
RCIN#
PROCPWRGD
THRMTRIP#
INIT3_3V#
DF_TVS
CPU/MISC
CPU/MISC
TS_VSS1
TS_VSS2
TS_VSS3
TS_VSS4
NC_1
VSS_NCTF_15
VSS_NCTF_16
VSS_NCTF_17
VSS_NCTF_18
VSS_NCTF_19
VSS_NCTF_20
VSS_NCTF_21
VSS_NCTF_22
VSS_NCTF_23
VSS_NCTF_24
VSS_NCTF_25
VSS_NCTF_26
VSS_NCTF_27
VSS_NCTF_28
VSS_NCTF_29
VSS_NCTF_30
VSS_NCTF_31
VSS_NCTF_32
C40
CONTACTLESS_DET#
B41
C41
A40
T111T111
P4
SIO_A20GATE
AU16
H_PECI_R
PECI
P5
AY11
AY10
PCH_THRMTRIP#_R
T14
INIT_3.3V#
AY1
NV_CLE
AH8
AK11
AH10
AK10
P37
BG2
BG48
BH3
BH47
BJ4
BJ44
BJ45
BJ46
BJ5
BJ6
C2
C48
D1
D49
E1
E49
F1
F49
R278 *0_NC
R278 *0_NC
SIO_RCIN#
CONTACTLESS_DET# (56)
DGPU_PWROK (1 9,40)
R277 0 +/-5%R277 0 +/-5%
+/-5%
+/-5%
T108T108
MXM_PRESENT2# (19)
SIO_A20GATE (39)
PECI_EC (39)
H_PECI (2)
SIO_RCIN# (39)
H_CPUPWRGD (2,6)
R282 56 +/-5%R282 56 +/-5%
C164
C164
R284 *390_NC +/-5%R284 *390_NC +/-5%
0.1uF
0.1uF
16V,X7R
16V,X7R
PLACE R638 CLOSE TO THE BRANCHING POINT
( TO CPU and NVRAM CONNECTOR)
DMI & FDI Termination Voltage
Set to Vss when LOW
NV_CLE
Set to Vcc when HIGH
PCH_GPIO15
KB_DET#
GPIO27
+1.05V_RUN_VTT
H_THERMTRIP# (2,46)
IOL_DET#
MXM_PRESENT1#
SIO_RCIN#
SIO_EXT_SCI#
SIO_A20GATE
CONTACTLESS_DET#
PCH_GPIO16
TEMP_ALERT#
GPIO22
FDI_OVRVLTG
GPIO17
GPIO36
GPIO36
R293 1K+/-5%R293 1K+/-5%
R1832 10K +/-5%R1832 10K +/-5%
R1127 100K +/-5%R1127 100 K +/-5%
R1101 100K +/-5%R1101 100 K +/-5%
R286 10K +/-5%R286 10 K +/-5 %
R280 10K +/-5%R280 10 K +/-5 %
R281 10K +/-5%R281 10 K +/-5 %
R287 8.2K +/-5%R28 7 8.2K +/-5%
R288 200K+/-5%R28 8 200K+/-5%
R289 10K +/-5%R289 10 K +/-5 %
R290 10K +/-5%R290 10 K +/-5 %
R291 10K +/-5%R291 10 K +/-5 %
R297 *200K_NC +/-5%R297 *200K_NC +/-5%
R298 8.2K +/-5%R29 8 8.2K +/-5%
R294 *10K_NC +/-5%R294 *10K_NC +/-5%
R292 10K +/-5%R2 92 10K +/-5%
NV_CLE
+3.3V_ALW_PCH
+VCCPNAND
0827 Update by DG1.2
R305
R305
2.2K
2.2K
+/-5%
+/-5%
R306
R306
1K
1K
+/-5%
+/-5%
+3.3V_RUN
H_SNB_IVB# (2)
A A
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Title
11 -- CBT 5/7 (GPIO)
11 -- CBT 5/7 (GPIO)
11 -- CBT 5/7 (GPIO)
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet
1
of
11 84Thursday , Ja nuary 27, 2 011
11 84Thursday , Ja nuary 27, 2 011
11 84Thursday , Ja nuary 27, 2 011
1A
1A
1A
5
WWW.MANUALS.CLAN.SU
+1.05V_RUN
VCCCORE=1.3A max
C170
C170
C167
1uF
1uF
6.3V,X5R
6.3V,X5R
L2 *1uH_NCL2 *1uH_NC
close PCH
100mil
C189
C189
1uF
1uF
6.3V,X5R
6.3V,X5R
r0805h6
r0805h6
R342 0 +/-5%
R342 0 +/-5%
r0603h6
r0603h6
R345 *0_NC +/-5%
R345 *0_NC +/-5%
r0603h6
r0603h6
R348 *0_NC +/-5%
R348 *0_NC +/-5%
r0603h6
r0603h6
+3.3V_RUN
R1833 1 +/-1%
R1833 1 +/-1%
C167
1uF
1uF
6.3V,X5R
6.3V,X5R
C185
C185
10uF
10uF
6.3V,X5R
6.3V,X5R
c0603h9
c0603h9
C190
C190
1uF
1uF
6.3V,X5R
6.3V,X5R
+3.3V_RUN
+1.05V_+1.5V_1.8V_RUN
+VCCAPLL_FDI
C205
C205
*10uF_NC
*10uF_NC
6.3V,X5R
6.3V,X5R
r0603h6
r0603h6
C166
C166
10uF
10uF
6.3V,X5R
6.3V,X5R
c0603h9
+1.05V_RUN
+1.05V_RUN
+1.05V_RUN
+1.8V_RUN
+1.05V_RUN
c0603h9
R333 *0_NC +/-5%
R333 *0_NC +/-5%
D D
C C
B B
A A
C171
C171
1uF
1uF
6.3V,X5R
6.3V,X5R
+1.05V_RUN
+VCCAPLLEXP
C180
C180
*10uF_NC
*10uF_NC
6.3V,X5R
6.3V,X5R
c0603h9
c0603h9
C186
C186
1uF
1uF
6.3V,X5R
6.3V,X5R
C191
C191
1uF
1uF
6.3V,X5R
6.3V,X5R
C198
C198
0.1uF
0.1uF
16V,Y5V
16V,Y5V
+1.05V_RUN
+1.05V_RUN_VTT_DMI
+1.05V_+1.5V_1.8V_RUN
+1.05V_RUN
AA23
AC23
AD21
AD23
AF21
AF23
AG21
AG23
AG24
AG26
AG27
AG29
AJ23
AJ26
AJ27
AJ29
AJ31
AN19
BJ22
AN16
AN17
AN21
AN26
AN27
AP21
AP23
AP24
AP26
AT24
AN33
AN34
BH29
AP16
BG6
AP17
AU20
+1.05V_+1.5V_1.8V_RUN+1.5V_RUN
L6
L6
*
*
10uH 150mA
10uH 150mA
POWER
POWER
U3G
U3G
VCCCORE[1]
VCCCORE[2]
VCCCORE[3]
VCCCORE[4]
VCCCORE[5]
VCCCORE[6]
VCCCORE[7]
VCCCORE[8]
VCCCORE[9]
VCCCORE[10]
VCCCORE[11]
VCC CORE
VCC CORE
VCCCORE[12]
VCCCORE[13]
VCCCORE[14]
VCCCORE[15]
VCCCORE[16]
VCCCORE[17]
VCCIO[28]
VCCAPLLEXP
VCCIO[15]
VCCIO[16]
VCCIO[17]
VCCIO[18]
VCCIO[19]
VCCIO[20]
VCCIO[21]
VCCIO[22]
VCCIO[23]
VCCIO[24]
VCCIO
VCCIO
VCCIO[25]
VCCIO[26]
VCC3_3[3]
VCCVRM[2]
VccAFDIPLL
VCCIO[27]
FDI
FDI
VCCDMI[2]
BD82QM67[VER.B3,SLH9B]
BD82QM67[VER.B3,SLH9B]
Follow Power Delivery
Design Guide Rev 0.5(chapter 7)
+1.05V_RUN
R1684 0 +/-5%
R1684 0 +/-5%
r0603h6
r0603h6
R1685 0 +/-5%
R1685 0 +/-5%
r0603h6
r0603h6
close PCH 100mil,
trace width 20mil of L35,L36 & R1699
+3.3V_RUN_VCC_CLKF33
C233
C233
C232
C232
1uF
1uF
10uF
10uF
6.3V,X5R
6.3V,X5R
6.3V,X5R
6.3V,X5R
c0603h9
c0603h9
close PCH 100mil
5
CRTLVDS
CRTLVDS
VCCTX_LVDS[1]
VCCTX_LVDS[2]
VCCTX_LVDS[3]
VCCTX_LVDS[4]
DMI
DMI
DFT / SPI HVCMOS
DFT / SPI HVCMOS
C212
C212
*330uF_NC
*330uF_NC
2V,<=9mOhm
2V,<=9mOhm
L4
L4
*
*
10uH 150mA
10uH 150mA
L5
L5
*
*
10uH 150mA
10uH 150mA
VCCADAC
VSSADAC
VCCALVDS
VSSALVDS
VCC3_3[6]
VCC3_3[7]
VCCVRM[3]
VCCDMI[1]
VCCCLKDMI
VCCDFTERM[1]
VCCDFTERM[2]
VCCDFTERM[3]
VCCDFTERM[4]
VCCSPI
4
U48
U47
AK36
AK37
AM37
AM38
AP36
AP37
V33
V34
AT16
AT20
AB36
AG16
AG17
AJ16
AJ17
V1
C213
C213
*330uF_NC
*330uF_NC
2V,<=9mOhm
2V,<=9mOhm
C223
C223
220uF
220uF
2.5V,<=15mOhm
2.5V,<=15mOhm
4
close PCH 100mil
+VCCADAC
VCCALVDS = 1mA max
VCCTX_LVDS = 60mA max
+3.3V_RUN
C181
C181
0.1uF
0.1uF
16V,Y5V
16V,Y5V
+1.05V_+1.5V_1.8V_RUN
+1.05V_RUN_VTT_DMI
+1.05V_RUN_DMI
C193
C193
1uF
1uF
6.3V,X5R
6.3V,X5R
+VCCPNAND
+3.3V_M_VCCSPI
C207
C207
1uF
1uF
6.3V,X5R
6.3V,X5R
+1.05V_M
C224
C224
1uF
1uF
6.3V,X5R
6.3V,X5R
C165
C165
C168
C168
10uF
10uF
0.1uF
0.1uF
10V,X7R
10V,X7R
16V,Y5V
16V,Y5V
c0805h14
c0805h14
C177
C177
C176
C176
10nF
10nF
10nF
10nF
25V,X7R
25V,X7R
25V,X7R
25V,X7R
*
*
10uH 150mA
10uH 150mA
C194
C194
*10uF_NC
*10uF_NC
6.3V,X5R
6.3V,X5R
close PCH 100mil
R330 0 +/-5%
R330 0 +/-5%
r0805h6
r0805h6
R331 *0_NC +/-5%
R331 *0_NC +/-5%
r0805h6
r0805h6
C202
C202
0.1uF
0.1uF
16V,Y5V
16V,Y5V
R334 0 +/-5%
R334 0 +/-5%
r0805h6
r0805h6
C214
C214
*330uF_NC
*330uF_NC
2V,<=9mOhm
2V,<=9mOhm
+1.05V_RUN_VCCA_A_DPL
+1.05V_RUN_VCCA_B_DPL
C225
C225
220uF
220uF
2.5V,<=15mOhm
2.5V,<=15mOhm
COGAR POINT (POWER)
+3.3V_RUN
FB1
FB1
FB 1K Ohm, 300mA
FB 1K Ohm, 300mA
1 2
0603h10
0603h10
C169
C169
10nF
10nF
25V,X7R
25V,X7R
C173
C173
0.1uF
0.1uF
16V,Y5V
16V,Y5V
R324 0 +/-5%
R324 0 +/-5%
C187
C187
1uF
1uF
6.3V,X5R
6.3V,X5R
L19
L19
+1.05V_RUN
+3.3V_M
+3.3V_RUN
C178
C178
22uF
22uF
6.3V,X5R
6.3V,X5R
c0805h14
c0805h14
C226
C226
1uF
1uF
6.3V,X5R
6.3V,X5R
+3.3V_ALW_PCH
L1
+/-10%
L1
+/-10%
0.1uH,250mA
0.1uH,250mA
0805h11
0805h11
+1.05V_RUN_VTT
r0805h6
r0805h6
R1834 1 +/-1%
R1834 1 +/-1%
r0603h6
r0603h6
+1.8V_RUN
+3.3V_RUN
need changed to 0.002 ohm(1206)
+1.05V_RUN
+1.05V_M
+1.05V_RUN_VTT
L43
L43
*
*
*10uH_NC
*10uH_NC
close PCH
width 100mil
R314 0 +/-5%
R314 0 +/-5%
+1.8V_RUN
trace width
40mil
R338 0 +/-5%
R338 0 +/-5%
r0603h6
r0603h6
R341 0 +/-5%
R341 0 +/-5%
r0603h6
r0603h6
R343 *0_NC
R343 *0_NC
r0603h6
r0603h6
R349 0 +/-5%
R349 0 +/-5%
r0603h6
r0603h6
+VCCAPLL_CPY_PCH
C234
C234
*10uF_NC
*10uF_NC
6.3V,X5R
6.3V,X5R
c0603h9
c0603h9
3
+1.05V_RUN
+/-5%
+/-5%
3
r0603h6
r0603h6
+1.05V_RUN
+V_CPU_IO
+1.05V_M
C210
C210
1uF
1uF
6.3V,X5R
6.3V,X5R
C217
C217
1uF
1uF
6.3V,X5R
6.3V,X5R
C219
C219
*1uF_NC
*1uF_NC
6.3V,X5R
6.3V,X5R
C220
C220
4.7uF
4.7uF
10V,X5R
10V,X5R
c0805h14
c0805h14
C172
C172
0.1uF
0.1uF
16V,Y5V
16V,Y5V
+PCH_VCCDSW
C174
C174
*0.1uF_NC
*0.1uF_NC
16V,Y5V
16V,Y5V
C199
C199
1uF
1uF
6.3V,X5R
6.3V,X5R
+RTC_CELL
+1.05V_RUN
+VCCPDSW
C221
C221
0.1uF
0.1uF
16V,Y5V
16V,Y5V
C228
C228
1uF
1uF
6.3V,X5R
6.3V,X5R
C200
C200
1uF
1uF
6.3V,X5R
6.3V,X5R
C208 0.1uF
C208 0.1uF
R313 *0_NC +/-5%
R313 *0_NC +/-5%
+VCCSUS1
C182
C182
*1uF_NC
*1uF_NC
6.3V,X5R
6.3V,X5R
C195
C195
22uF
22uF
6.3V,X5R
6.3V,X5R
c0805h14
c0805h14
C215 1uF
C215 1uF
r0805h6
r0805h6
+VCCACLK
+3.3V_RUN_VCC_CLKF33
+VCCAPLL_CPY_PCH
C196
C196
22uF
22uF
6.3V,X5R
6.3V,X5R
c0805h14
c0805h14
C201
C201
1uF
1uF
6.3V,X5R
6.3V,X5R
+VCCRTCEXT
16V,X7R
16V,X7R
+1.05V_+1.5V_1.8V_RUN
+1.05V_RUN_VCCA_A_DPL
+1.05V_RUN_VCCA_B_DPL
+1.05V_RUN_VCCDIFFCLKN
6.3V,X5R
6.3V,X5R
+1.05V_RUN_SSCVCC
C218 0.1uF
C218 0.1uF
16V,Y5V
16V,Y5V
+1.05V_M_VCCSUS
C222
C222
0.1uF
0.1uF
16V,Y5V
16V,Y5V
C229
C229
C230
C230
0.1uF
0.1uF
0.1uF
0.1uF
16V,Y5V
16V,Y5V
16V,Y5V
16V,Y5V
+VCCSST
U3J
U3J
AD49
VCCACLK
T16
VCCDSW3_3
V12
DCPSUSBYP
T38
VCC3_3[5]
BH23
VCCAPLLDMI2
AL29
VCCIO[14]
AL24
DCPSUS[3]
AA19
VCCASW[1]
AA21
VCCASW[2]
AA24
VCCASW[3]
AA26
VCCASW[4]
AA27
VCCASW[5]
AA29
VCCASW[6]
AA31
VCCASW[7]
AC26
VCCASW[8]
AC27
VCCASW[9]
AC29
VCCASW[10]
AC31
VCCASW[11]
AD29
VCCASW[12]
AD31
VCCASW[13]
W21
VCCASW[14]
W23
VCCASW[15]
W24
VCCASW[16]
W26
VCCASW[17]
W29
VCCASW[18]
W31
VCCASW[19]
W33
VCCASW[20]
N16
DCPRTC
Y49
VCCVRM[4]
BD47
VCCADPLLA
BF47
VCCADPLLB
AF17
VCCIO[7]
AF33
VCCDIFFCLKN[1]
AF34
VCCDIFFCLKN[2]
AG34
VCCDIFFCLKN[3]
AG33
VCCSSC
V16
DCPSST
T17
DCPSUS[1]
V19
DCPSUS[2]
BJ8
V_PROC_IO
A22
VCCRTC
BD82QM67[VER.B3,SLH9B]
BD82QM67[VER.B3,SLH9B]
R355 *0_NC +/-5%
R355 *0_NC +/-5%
r0805h6
r0805h6
2
POWER
POWER
Clock and Miscellaneous
Clock and Miscellaneous
PCI/GPIO/LPCMISC
PCI/GPIO/LPCMISC
SATA USB
SATA USB
CPURTC
CPURTC
HDA
HDA
+1.05V_RUN_VCCA_B_DPL+1.05V_RUN_VCCA_A_DPL
2
VCCIO[29]
VCCIO[30]
VCCIO[31]
VCCIO[32]
VCCIO[33]
VCCSUS3_3[7]
VCCSUS3_3[8]
VCCSUS3_3[9]
VCCSUS3_3[10]
VCCSUS3_3[6]
VCCIO[34]
V5REF_SUS
DCPSUS[4]
VCCSUS3_3[1]
V5REF
VCCSUS3_3[2]
VCCSUS3_3[3]
VCCSUS3_3[4]
VCCSUS3_3[5]
VCC3_3[1]
VCC3_3[8]
VCC3_3[4]
VCC3_3[2]
VCCIO[5]
VCCIO[12]
VCCIO[13]
VCCIO[6]
VCCAPLLSATA
VCCVRM[1]
VCCIO[2]
VCCIO[3]
VCCIO[4]
VCCASW[22]
VCCASW[23]
VCCASW[21]
VCCSUSHDA
N26
P26
P28
T27
T29
T23
T24
V23
V24
P24
T26
M26
AN23
AN24
P34
N20
N22
P20
P22
AA16
W16
T34
AJ2
AF13
AH13
AH14
AF14
AK1
AF11
AC16
AC17
AD17
T21
V21
T19
P32
1
+1.05V_RUN
C183
C183
1uF
1uF
close PCH
6.3V,X5R
6.3V,X5R
width 100mil
+3.3V_ALW_PCH
C175
C175
0.1uF
0.1uF
16V,Y5V
16V,Y5V
+3.3V_ALW_PCH
+1.05V_RUN
+PCH_V5REF_SUS
+VCCA_USBSUS
+PCH_V5REF_RUN
+3.3V_RUN_VCCPPCI
+VCCSATAPLL
+1.05V_+1.5V_1.8V_RUN
+1.05V_M
+VCCSUSHDA
C179 0.1uF16V,Y5VC179 0.1uF16V,Y5V
R319 10+/-5% r0603h6R319 10+/-5% r0603h6
C A
C184
C184
D1 SDM10K45-7-FD1 SDM10K45-7-F
0.1uF
0.1uF
16V,Y5V
16V,Y5V
+3.3V_ALW_PCH
R325 10+/-5% r0603h6R325 10+/-5% r0603h6
C A
C192
C192
D2 SDM10K45-7-FD2 SDM10K45-7-F
1uF
1uF
6.3V,X5R
6.3V,X5R
+3.3V_ALW_PCH
C197
C197
1uF
1uF
6.3V,X5R
6.3V,X5R
+3.3V_RUN
C203
C203
0.1uF
0.1uF
16V,Y5V
16V,Y5V
+3.3V_RUN
C206 0.1uF16V,Y5VC206 0.1uF16V,Y5V
+1.05V_RUN
trace width
40mil
C209
C209
1uF
1uF
close PCH 100mil
6.3V,X5R
6.3V,X5R
+1.05V_RUN_VCC_SATA
R351 0 +/-5%
R351 0 +/-5%
C227
C227
0.1uF
0.1uF
16V,Y5V
16V,Y5V
+3.3V_RUN_VCCPPCI
Ever Light
Ever Light
Ever Light
Technology Limited
Technology Limited
Technology Limited
Title
Title
Title
12 -- CBT 6/7 (POWE R)
12 -- CBT 6/7 (POWE R)
12 -- CBT 6/7 (POWE R)
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet
6.
C204 0.1uF 16V,Y5VC204 0.1uF 16 V,Y5V
close PCH 100mil
L3
L3
*
*
*10uH_NC
*10uH_NC
C211
C211
*10uF_NC
*10uF_NC
6.3V,X5R
6.3V,X5R
c0603h9
c0603h9
R340 0 +/-5%
R340 0 +/-5%
r0805h6
r0805h6
C216
C216
1uF
1uF
6.3V,X5R
6.3V,X5R
r0603h6
r0603h6
R352 0 +/-5%
R352 0 +/-5%
C231
C231
0.1uF
0.1uF
16V,Y5V
16V,Y5V
1
V5REF_SUS = 1mA max
+3.3V_ALW_PCH
+VCCA_USBSUS
+5V_RUN
+3.3V_RUN
+1.05V_RUN
r0805h6
r0805h6
+3.3V_RUN
12 84Thursday , Ja nuary 27, 2 011
12 84Thursday , Ja nuary 27, 2 011
12 84Thursday , Ja nuary 27, 2 011
+5V_ALW_PCH
+3.3V_ALW_PCH
C188
C188
*1uF_NC
*1uF_NC
6.3V,X5R
6.3V,X5R
+1.05V_RUN
of
1A
1A
1A
5
WWW.MANUALS.CLAN.SU
4
3
2
1
Cougar Point (GND)
U3I
U3I
AY4
VSS[159]
AY42
VSS[160]
AY46
VSS[161]
AY8
VSS[162]
D D
C C
B B
B11
VSS[163]
B15
VSS[164]
B19
VSS[165]
B23
VSS[166]
B27
VSS[167]
B31
VSS[168]
B35
VSS[169]
B39
VSS[170]
B7
VSS[171]
F45
VSS[172]
BB12
VSS[173]
BB16
VSS[174]
BB20
VSS[175]
BB22
VSS[176]
BB24
VSS[177]
BB28
VSS[178]
BB30
VSS[179]
BB38
VSS[180]
BB4
VSS[181]
BB46
VSS[182]
BC14
VSS[183]
BC18
VSS[184]
BC2
VSS[185]
BC22
VSS[186]
BC26
VSS[187]
BC32
VSS[188]
BC34
VSS[189]
BC36
VSS[190]
BC40
VSS[191]
BC42
VSS[192]
BC48
VSS[193]
BD46
VSS[194]
BD5
VSS[195]
BE22
VSS[196]
BE26
VSS[197]
BE40
VSS[198]
BF10
VSS[199]
BF12
VSS[200]
BF16
VSS[201]
BF20
VSS[202]
BF22
VSS[203]
BF24
VSS[204]
BF26
VSS[205]
BF28
VSS[206]
BD3
VSS[207]
BF30
VSS[208]
BF38
VSS[209]
BF40
VSS[210]
BF8
VSS[211]
BG17
VSS[212]
BG21
VSS[213]
BG33
VSS[214]
BG44
VSS[215]
BG8
VSS[216]
BH11
VSS[217]
BH15
VSS[218]
BH17
VSS[219]
BH19
VSS[220]
H10
VSS[221]
BH27
VSS[222]
BH31
VSS[223]
BH33
VSS[224]
BH35
VSS[225]
BH39
VSS[226]
BH43
VSS[227]
BH7
VSS[228]
D3
VSS[229]
D12
VSS[230]
D16
VSS[231]
D18
VSS[232]
D22
VSS[233]
D24
VSS[234]
D26
VSS[235]
D30
VSS[236]
D32
VSS[237]
D34
VSS[238]
D38
VSS[239]
D42
VSS[240]
D8
VSS[241]
E18
VSS[242]
E26
VSS[243]
G18
VSS[244]
G20
VSS[245]
G26
VSS[246]
G28
VSS[247]
G36
VSS[248]
G48
VSS[249]
H12
VSS[250]
H18
VSS[251]
H22
VSS[252]
H24
VSS[253]
H26
VSS[254]
H30
VSS[255]
H32
VSS[256]
H34
VSS[257]
F3
VSS[258]
BD82QM67[VER.B3,SLH9B]
BD82QM67[VER.B3,SLH9B]
VSS[259]
VSS[260]
VSS[261]
VSS[262]
VSS[263]
VSS[264]
VSS[265]
VSS[266]
VSS[267]
VSS[268]
VSS[269]
VSS[270]
VSS[271]
VSS[272]
VSS[273]
VSS[274]
VSS[275]
VSS[276]
VSS[277]
VSS[278]
VSS[279]
VSS[280]
VSS[281]
VSS[282]
VSS[283]
VSS[284]
VSS[285]
VSS[286]
VSS[287]
VSS[288]
VSS[289]
VSS[290]
VSS[291]
VSS[292]
VSS[293]
VSS[294]
VSS[295]
VSS[296]
VSS[297]
VSS[298]
VSS[299]
VSS[300]
VSS[301]
VSS[302]
VSS[303]
VSS[304]
VSS[305]
VSS[306]
VSS[307]
VSS[308]
VSS[309]
VSS[310]
VSS[311]
VSS[312]
VSS[313]
VSS[314]
VSS[315]
VSS[316]
VSS[317]
VSS[318]
VSS[319]
VSS[320]
VSS[321]
VSS[322]
VSS[323]
VSS[324]
VSS[325]
VSS[328]
VSS[329]
VSS[330]
VSS[331]
VSS[333]
VSS[334]
VSS[335]
VSS[337]
VSS[338]
VSS[340]
VSS[342]
VSS[343]
VSS[344]
VSS[345]
VSS[346]
VSS[347]
VSS[348]
VSS[349]
VSS[350]
VSS[351]
VSS[352]
H46
K18
K26
K39
K46
K7
L18
L2
L20
L26
L28
L36
L48
M12
P16
M18
M22
M24
M30
M32
M34
M38
M4
M42
M46
M8
N18
P30
N47
P11
P18
T33
P40
P43
P47
P7
R2
R48
T12
T31
T37
T4
W34
T46
T47
T8
V11
V17
V26
V27
V29
V31
V36
V39
V43
V7
W17
W19
W2
W27
W48
Y12
Y38
Y4
Y42
Y46
Y8
BG29
N24
AJ3
AD47
B43
BE10
BG41
G14
H16
T36
BG22
BG24
C22
AP13
M14
AP3
AP1
BE16
BC16
BG28
BJ28
U3H
U3H
H5
VSS[0]
AA17
VSS[1]
AA2
VSS[2]
AA3
VSS[3]
AA33
VSS[4]
AA34
VSS[5]
AB11
VSS[6]
AB14
VSS[7]
AB39
VSS[8]
AB4
VSS[9]
AB43
VSS[10]
AB5
VSS[11]
AB7
VSS[12]
AC19
VSS[13]
AC2
VSS[14]
AC21
VSS[15]
AC24
VSS[16]
AC33
VSS[17]
AC34
VSS[18]
AC48
VSS[19]
AD10
VSS[20]
AD11
VSS[21]
AD12
VSS[22]
AD13
VSS[23]
AD19
VSS[24]
AD24
VSS[25]
AD26
VSS[26]
AD27
VSS[27]
AD33
VSS[28]
AD34
VSS[29]
AD36
VSS[30]
AD37
VSS[31]
AD38
VSS[32]
AD39
VSS[33]
AD4
VSS[34]
AD40
VSS[35]
AD42
VSS[36]
AD43
VSS[37]
AD45
VSS[38]
AD46
VSS[39]
AD8
VSS[40]
AE2
VSS[41]
AE3
VSS[42]
AF10
VSS[43]
AF12
VSS[44]
AD14
VSS[45]
AD16
VSS[46]
AF16
VSS[47]
AF19
VSS[48]
AF24
VSS[49]
AF26
VSS[50]
AF27
VSS[51]
AF29
VSS[52]
AF31
VSS[53]
AF38
VSS[54]
AF4
VSS[55]
AF42
VSS[56]
AF46
VSS[57]
AF5
VSS[58]
AF7
VSS[59]
AF8
VSS[60]
AG19
VSS[61]
AG2
VSS[62]
AG31
VSS[63]
AG48
VSS[64]
AH11
VSS[65]
AH3
VSS[66]
AH36
VSS[67]
AH39
VSS[68]
AH40
VSS[69]
AH42
VSS[70]
AH46
VSS[71]
AH7
VSS[72]
AJ19
VSS[73]
AJ21
VSS[74]
AJ24
VSS[75]
AJ33
VSS[76]
AJ34
VSS[77]
AK12
VSS[78]
AK3
VSS[79]
BD82QM67[VER.B3,SLH9B]
BD82QM67[VER.B3,SLH9B]
VSS[80]
VSS[81]
VSS[82]
VSS[83]
VSS[84]
VSS[85]
VSS[86]
VSS[87]
VSS[88]
VSS[89]
VSS[90]
VSS[91]
VSS[92]
VSS[93]
VSS[94]
VSS[95]
VSS[96]
VSS[97]
VSS[98]
VSS[99]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
AK38
AK4
AK42
AK46
AK8
AL16
AL17
AL19
AL2
AL21
AL23
AL26
AL27
AL31
AL33
AL34
AL48
AM11
AM14
AM36
AM39
AM43
AM45
AM46
AM7
AN2
AN29
AN3
AN31
AP12
AP19
AP28
AP30
AP32
AP38
AP4
AP42
AP46
AP8
AR2
AR48
AT11
AT13
AT18
AT22
AT26
AT28
AT30
AT32
AT34
AT39
AT42
AT46
AT7
AU24
AU30
AV16
AV20
AV24
AV30
AV38
AV4
AV43
AV8
AW14
AW18
AW2
AW22
AW26
AW28
AW32
AW34
AW36
AW40
AW48
AV11
AY12
AY22
AY28
A A
Ever Light
Ever Light
Ever Light
Technology Limited
Technology Limited
Technology Limited
Title
Title
Title
13 -- CBT 7/7 (GND)
13 -- CBT 7/7 (GND)
13 -- CBT 7/7 (GND)
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet
1
of
13 84Thursday , Ja nuary 27, 2 011
13 84Thursday , Ja nuary 27, 2 011
13 84Thursday , Ja nuary 27, 2 011
1A
1A
1A
5
WWW.MANUALS.CLAN.SU
4
3
2
1
DDR3 Length Matching Formulas
B (A2)
D (A6)
JDIMM1
CPU
0
110
SA0SA1
00
1
1
C239
C239
10uF
10uF
6.3V,X5R
6.3V,X5R
A (A0)
D D
C C
CHA0
CHA1
CHB0
CHB1
B B
JDIMM3
JDIMM2
JDIMM4
C (A4)
DDR_A_MA[0..15](3,15)
+3.3V_RUN
R1053 10K +/-5%R1053 10K +/-5%
R357 *10K_NC +/-5%R357 *10K_NC +/-5%
R358 10K +/-5%R358 10K +/-5%
Addres s:0xA2
DDR_A_DQS[0..7](3,15)
DDR_A_DQS#[0..7](3,15)
+1.5V_SUS decoupling caps be located at the VDD pins of each SO-DIMM connector in the
vicinity of the CMD, Clock and Control signals
Those c apaci tors should be place d on t he sa me side of t he mothe rboard as t he
SO-DIMM connector
330uF x 1
10uF x 6
Place these Caps near So-DimmA.
0.1uF x 4
C242
C242
C241
C241
C243
10uF
10uF
6.3V,X5R
6.3V,X5R
10uF
10uF
6.3V,X5R
6.3V,X5R
C243
10uF
10uF
6.3V,X5R
6.3V,X5R
C244
C244
10uF
10uF
6.3V,X5R
6.3V,X5R
C240
C240
10uF
10uF
6.3V,X5R
6.3V,X5R
DDR_A_BS0(3,15)
DDR_A_BS1(3,15)
DDR_A_BS2(3,15)
DDR_A_CS#2(3)
DDR_A_CS#3(3)
DDR_A_CLK2(3)
DDR_A_CLK#2(3)
DDR_A_CLK3(3)
DDR_A_CLK#3(3)
DDR_A_CKE2(3)
DDR_A_CKE3(3)
DDR_A_CAS#(3,15)
DDR_A_RAS#(3,15)
DDR_A_WE#(3,15)
MEM_SMBCLK(6,10,15,16,17,18,28,36 )
MEM_SMBDAT(6,10,15,16,17,18,28,36)
DDR_A_ODT2(3)
DDR_A_ODT3(3)
C245
C245
1uF
1uF
6.3V,X5R
6.3V,X5R
CHA_DIMM1_TOP_SIDE
JDIMM1 is RVS type.(H=100)
JDIMM1A
JDIMM1A
98
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_MA15
DDR_A_DQS1
DDR_A_DQS0
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7
DDR_A_DQS#1
DDR_A_DQS#0
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5 DDR_A_D61
DDR_A_DQS#6
DDR_A_DQS#7
C246
C246
C247
C247
1uF
1uF
1uF
1uF
6.3V,X5R
6.3V,X5R
6.3V,X5R
6.3V,X5R
A0
97
A1
96
A2
95
A3
92
A4
91
A5
90
A6
86
A7
89
A8
85
A9
107
A10/AP
84
A11
83
A12/BC#
119
A13
80
A14
78
A15
109
BA0
108
BA1
79
BA2
114
S0#
121
S1#
101
CK0
103
CK0#
102
CK1
104
CK1#
73
CKE0
74
CKE1
115
CAS#
110
RAS#
113
WE#
197
SA0
201
SA1
202
SCL
200
SDA
116
ODT0
120
ODT1
11
DM0
28
DM1
46
DM2
63
DM3
136
DM4
153
DM5
170
DM6
187
DM7
12
DQS0
29
DQS1
47
DQS2
64
DQS3
137
DQS4
154
DQS5
171
DQS6
188
DQS7
10
DQS#0
27
DQS#1
45
DQS#2
62
DQS#3
135
DQS#4
152
DQS#5
169
DQS#6
186
DQS#7
DDRIII
DDRIII
+1.5V_MEM +0.75V_DDR_VTT+3.3V_RUN
C248
C248
C249
C249
1uF
1uF
330uF
330uF
6.3V,X5R
6.3V,X5R
2.5V,<9mOhm
2.5V,<9mOhm
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
5
DDR_A_D11
7
DDR_A_D8
15
DDR_A_D9
17
DDR_A_D14
4
DDR_A_D10
6
DDR_A_D12
16
DDR_A_D15
18
DDR_A_D13
21
DDR_A_D4
23
DDR_A_D5
33
DDR_A_D6
35
DDR_A_D3
22
DDR_A_D0
24
DDR_A_D1
34
DDR_A_D7
36
DDR_A_D2
39
DDR_A_D21
41
DDR_A_D17
51
DDR_A_D22
53
DDR_A_D18
40
DDR_A_D20
42
DDR_A_D16
50
DDR_A_D19
52
DDR_A_D23
57
DDR_A_D25
59
DDR_A_D31
67
DDR_A_D27
69
DDR_A_D26
56
DDR_A_D29
58
DDR_A_D24
68
DDR_A_D28
70
DDR_A_D30
129
DDR_A_D36
131
DDR_A_D32
141
DDR_A_D34
143
DDR_A_D39
130
DDR_A_D33
132
DDR_A_D38
140
DDR_A_D35
142
DDR_A_D37
147
DDR_A_D47
149
DDR_A_D45
157
DDR_A_D46
159
DDR_A_D43
146
DDR_A_D44
148
DDR_A_D41
158
DDR_A_D42
160
DDR_A_D40
163
DDR_A_D49
165
DDR_A_D48
175
DDR_A_D50
177
DDR_A_D51
164
DDR_A_D53
166
DDR_A_D52
174
DDR_A_D54
176
DDR_A_D55
181
DDR_A_D56
183
DDR_A_D60
191
DDR_A_D58
193
DDR_A_D62
180
DDR_A_D57
182
192
DDR_A_D63
194
DDR_A_D59
For VDDSPD
DDR_A_D[0..63] (3,15)
DDR3_DRAMRST#(2, 15,16,17)
M_VREF_DQ_DIMM0(1 5,18)
+M_VREF_DQ_DIMM0_1
M_VREF_CA_DIMM0(15,18)
+M_VREF_CA_DIMM0_1
C250
C250
C251
C251
0.1uF
0.1uF
2.2uF
2.2uF
16V,X7R
16V,X7R
10V,X5R
10V,X5R
R679 *0_NC +/-5%R679 *0_NC +/-5%
R680 *0_NC +/-5%R680 *0_NC +/-5%
1uF x 4
C252
C252
C253
C253
1uF
1uF
1uF
1uF
6.3V,X5R
6.3V,X5R
6.3V,X5R
6.3V,X5R
10V,X5R
10V,X5R
10V,X5R
10V,X5R
+1.5V_MEM
JDIMM1B
JDIMM1B
75
VDD1
VSS16
76
VDD2
VSS17
81
VDD3
VSS18
82
VDD4
VSS19
87
VDD5
VSS20
88
VDD6
VSS21
93
VDD7
VSS22
94
VDD8
VSS23
99
VDD9
VSS24
100
VDD10
VSS25
105
VDD11
VSS26
106
VDD12
VSS27
111
VDD13
VSS28
112
VDD14
VSS29
117
VDD15
VSS30
118
VDD16
VSS31
123
VDD17
VSS32
124
VDD18
VSS33
VSS34
199
+3.3V_RUN
T146T146
DRAMRST_DIMMA0
C235
C235
C236
C236
2.2uF
2.2uF
0.1uF
0.1uF
16V,X7R
16V,X7R
C237
C237
C238
C238
2.2uF
2.2uF
0.1uF
0.1uF
16V,X7R
16V,X7R
C254
C254
C255
C255
1uF
1uF
1uF
1uF
6.3V,X5R
6.3V,X5R
6.3V,X5R
6.3V,X5R
TS#_DIMMA1
VDDSPD
VSS35
VSS36
77
NC1
VSS37
122
NC2
VSS38
125
NCTEST
VSS39
VSS40
198
EVENT#
VSS41
30
RESET#
VSS42
VSS43
VSS44
1
VREF_DQ
VSS45
126
VREF_CA
VSS46
VSS47
VSS48
2
VSS1
VSS49
3
VSS2
VSS50
8
VSS3
VSS51
9
VSS4
VSS52
13
VSS5
14
VSS6
19
VSS7
20
VSS8
25
VSS9
26
VSS10
VTT1
31
VSS11
VTT2
32
VSS12
37
VSS13
GND
38
VSS14
GND#2-G2
43
VSS15
DDRIII
DDRIII
Signal Group Min Length Max Length
Control-to-Clock
Command-to-Clock
Strobe-to-Clock
Data-to-Strobe (per byte lane)
44
48
49
54
55
60
61
65
66
71
72
127
128
133
134
138
139
144
145
150
151
155
156
161
162
167
168
172
173
178
179
184
185
189
190
195
196
+0.75V_DDR_VTT
203
204
G1
G2
Clock - 0.5"
Clock - 0.5"
Clock - 0.5"
Strobe - 20 mils
Clock - 0.0"
Clock - 0.5"
Clock - 1.0"
Strobe + 20 mils
A A
Ever Light
Ever Light
Ever Light
Technology Limited
Technology Limited
Technology Limited
Title
Title
Title
15 -- SODIMM-204P-A1
15 -- SODIMM-204P-A1
15 -- SODIMM-204P-A1
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Thunder 1A
Thunder 1A
Thunder 1A
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet
1
of
14 84Thursday , Ja nuary 27, 2 011
14 84Thursday , Ja nuary 27, 2 011
14 84Thursday , Ja nuary 27, 2 011
5
WWW.MANUALS.CLAN.SU
B (A2)
D (A6)
JDIMM1
C260
C260
10uF
10uF
6.3V,X5R
6.3V,X5R
SA0
0
1
0
1
JDIMM2
330uF x 1
10uF x 6
0.1uF x 4
C261
C261
10uF
10uF
6.3V,X5R
6.3V,X5R
JDIMM3
JDIMM4
C (A4)
DDR_A_MA[0..15](3,14)
DDR_A_BS0(3,14)
DDR_A_BS1(3,14)
DDR_A_BS2(3,14)
DDR_A_CS#0(3)
DDR_A_CS#1(3)
DDR_A_CLK0(3)
DDR_A_CLK#0(3)
DDR_A_CLK1(3)
DDR_A_CLK#1(3)
+3.3V_RUN
R360 *10K_NC +/-5%R360 *10K_NC +/-5%
R1032 10K +/-5%R1032 10K +/-5%
R1037 10K +/-5%R1037 10K +/-5%
Addres s:0xA0
+1.5V_SUS decoupling caps be located at the VDD pins of each SO-DIMM connector in the
vicinity of the CMD, Clock and Control signals
Those c apaci tors should be place d on t he sa me side of t he mothe rboard as t he
SO-DIMM connector
DDR_A_CKE0(3)
DDR_A_CKE1(3)
DDR_A_CAS#(3,14)
DDR_A_RAS#(3,14)
DDR_A_WE#(3,14)
MEM_SMBCLK(6,10,14,16,17,18,28,36 )
MEM_SMBDAT(6,10,14,16,17,18,28,36)
DDR_A_ODT0(3)
DDR_A_ODT1(3)
DDR_A_DQS[0..7](3,14)
DDR_A_DQS#[0..7](3,14)
Place these Caps near So-DimmA.
C266
C262
C262
10uF
10uF
6.3V,X5R
6.3V,X5R
C263
C263
10uF
10uF
6.3V,X5R
6.3V,X5R
C264
C264
10uF
10uF
6.3V,X5R
6.3V,X5R
C265
C265
10uF
10uF
6.3V,X5R
6.3V,X5R
C266
1uF
1uF
6.3V,X5R
6.3V,X5R
CPU
A (A0)
D D
C C
SA1
CHA0
0
CHA1
0
1
CHB0
1
CHB1
B B
4
CHA_DIMM0_BOT_SIDE
JDIMM2 is RVS type.
0510GC: CIS OK
JDIMM2A
JDIMM2A
98
DDR_A_MA0
A0
97
DDR_A_MA1
A1
96
DDR_A_MA2
A2
95
DDR_A_MA3
A3
92
DDR_A_MA4
A4
91
DDR_A_MA5
A5
90
DDR_A_MA6
A6
86
DDR_A_MA7
A7
89
DDR_A_MA8
A8
85
DDR_A_MA9
A9
107
DDR_A_MA10
A10/AP
84
DDR_A_MA11
A11
83
DDR_A_MA12
A12/BC#
119
DDR_A_MA13
A13
80
DDR_A_MA14
A14
78
DDR_A_MA15
A15
109
BA0
108
BA1
79
BA2
114
S0#
121
S1#
101
CK0
103
CK0#
102
CK1
104
CK1#
73
CKE0
74
CKE1
115
CAS#
110
RAS#
113
WE#
197
SA0
201
SA1
202
SCL
200
SDA
116
ODT0
120
ODT1
11
DM0
28
DM1
46
DM2
63
DM3
136
DM4
153
DM5
170
DM6
187
DM7
12
DDR_A_DQS1
DQS0
29
DDR_A_DQS0
DQS1
47
DDR_A_DQS2
DQS2
64
DDR_A_DQS3
DQS3
137
DDR_A_DQS4
DQS4
154
DDR_A_DQS5
DQS5
171
DDR_A_DQS6
DQS6
188
DDR_A_DQS7
DQS7
10
DDR_A_DQS#1
DQS#0
27
DDR_A_DQS#0
DQS#1
45
DDR_A_DQS#2
DQS#2
62
DDR_A_DQS#3
DQS#3
135
DDR_A_DQS#4
DQS#4
152
DDR_A_DQS#5
DQS#5
169
DDR_A_DQS#6
DQS#6
186
DDR_A_DQS#7
DQS#7
DDRIII
DDRIII
+1.5V_MEM +0.75V_DDR_VTT+3.3V_RUN
C268
C268
C269
1uF
1uF
6.3V,X5R
6.3V,X5R
C269
1uF
1uF
6.3V,X5R
6.3V,X5R
C267
C267
1uF
1uF
6.3V,X5R
6.3V,X5R
C270
C270
330uF
330uF
2.5V,<9mOhm
2.5V,<9mOhm
3
2
1
DDR3 Length Matching Formulas
Signal Group Min Length Max Length
Control-to-Clock
Command-to-Clock
Strobe-to-Clock
Data-to-Strobe (per byte lane)
5
DDR_A_D10
DQ0
7
DDR_A_D12
DQ1
15
DDR_A_D13
DQ2
17
DDR_A_D15
DQ3
4
DDR_A_D11
DQ4
6
DDR_A_D8
DQ5
16
DDR_A_D9
DQ6
18
DDR_A_D14
DQ7
21
DDR_A_D1
DQ8
23
DDR_A_D0
DQ9
33
DDR_A_D7
DQ10
35
DDR_A_D2
DQ11
22
DDR_A_D4
DQ12
24
DDR_A_D5
DQ13
34
DDR_A_D6
DQ14
36
DDR_A_D3
DQ15
39
DDR_A_D20
DQ16
41
DDR_A_D16
DQ17
51
DDR_A_D19
DQ18
53
DDR_A_D23
DQ19
40
DDR_A_D21
DQ20
42
DDR_A_D17
DQ21
50
DDR_A_D22
DQ22
52
DDR_A_D18
DQ23
57
DDR_A_D29
DQ24
59
DDR_A_D24
DQ25
67
DDR_A_D28
DQ26
69
DDR_A_D30
DQ27
56
DDR_A_D25
DQ28
58
DDR_A_D31
DQ29
68
DDR_A_D27
DQ30
70
DDR_A_D26
DQ31
129
DDR_A_D33
DQ32
131
DDR_A_D38
DQ33
141
DDR_A_D35
DQ34
143
DDR_A_D37
DQ35
130
DDR_A_D36
DQ36
132
DDR_A_D32
DQ37
140
DDR_A_D34
DQ38
142
DDR_A_D39
DQ39
147
DDR_A_D44
DQ40
149
DDR_A_D41
DQ41
157
DDR_A_D42
DQ42
159
DDR_A_D40
DQ43
146
DDR_A_D47
DQ44
148
DDR_A_D45
DQ45
158
DDR_A_D46
DQ46
160
DDR_A_D43
DQ47
163
DDR_A_D53
DQ48
165
DDR_A_D52
DQ49
175
DDR_A_D54
DQ50
177
DDR_A_D55
DQ51
164
DDR_A_D49
DQ52
166
DDR_A_D48
DQ53
174
DDR_A_D50
DQ54
176
DDR_A_D51
DQ55
181
DDR_A_D57
DQ56
183
DDR_A_D61
DQ57
191
DDR_A_D63
DQ58
193
DDR_A_D59
DQ59
180
DDR_A_D56
DQ60
182
DDR_A_D60
DQ61
192
DDR_A_D58
DQ62
194
DDR_A_D62
DQ63
DDR_A_D[0..63] (3,14)
+M_VREF_DQ_DIMM0_1
+M_VREF_CA_DIMM0_1
All VREF traces should have 10 mil trace width
DDR3_DRAMRST#(2, 14,16,17)
M_VREF_DQ_DIMM0(1 4,18)
R761 *0_NC +/-5%R761 *0_NC +/-5% C256
M_VREF_CA_DIMM0(14,18)
R739 *0_NC +/-5%R739 *0_NC +/-5%
10V,X5R
10V,X5R
10V,X5R
10V,X5R
2.2uF
2.2uF
2.2uF
2.2uF
T147T147
DRAMRST_DIMMA1
C256
C258
C258
+3.3V_RUN
C257
C257
0.1uF
0.1uF
16V,X7R
16V,X7R
C259
C259
0.1uF
0.1uF
16V,X7R
16V,X7R
+1.5V_MEM
TS#_DIMMA0
JDIMM2B
JDIMM2B
75
76
81
82
87
88
93
94
99
100
105
106
111
112
117
118
123
124
199
77
122
125
198
30
1
126
2
3
8
9
13
14
19
20
25
26
31
32
37
38
43
DDRIII
DDRIII
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11
VDD12
VDD13
VDD14
VDD15
VDD16
VDD17
VDD18
VDDSPD
NC1
NC2
NCTEST
EVENT#
RESET#
VREF_DQ
VREF_CA
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
GND#2-G2
VTT1
VTT2
GND
44
48
49
54
55
60
61
65
66
71
72
127
128
133
134
138
139
144
145
150
151
155
156
161
162
167
168
172
173
178
179
184
185
189
190
195
196
+0.75V_DDR_VTT
203
204
G1
G2
1uF x 4
C275
C275
C274
C271
C271
2.2uF
2.2uF
10V,X5R
10V,X5R
C272
C272
0.1uF
0.1uF
16V,X7R
16V,X7R
C273
C273
1uF
1uF
6.3V,X5R
6.3V,X5R
C274
1uF
1uF
6.3V,X5R
6.3V,X5R
1uF
1uF
6.3V,X5R
6.3V,X5R
C276
C276
1uF
1uF
6.3V,X5R
6.3V,X5R
Clock - 0.5"
Clock - 0.5"
Clock - 0.5"
Strobe - 20 mils
Clock - 0.0"
Clock - 0.5"
Clock - 1.0"
Strobe + 20 mils
A A
Ever Light
Ever Light
Ever Light
Technology Limited
Technology Limited
Technology Limited
Title
Title
Title
14 -- SODIMM-204P-A0
14 -- SODIMM-204P-A0
14 -- SODIMM-204P-A0
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Thunder 1A
Thunder 1A
Thunder 1A
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet
1
of
15 84Thursday , Ja nuary 27, 2 011
15 84Thursday , Ja nuary 27, 2 011
15 84Thursday , Ja nuary 27, 2 011
5
WWW.MANUALS.CLAN.SU
B (A2)
D (A6)
JDIMM3
CHA0
CHA1
CHB0
CHB1
JDIMM1
JDIMM4
JDIMM2
A (A0)
C (A4)
R1039 *10K_NC +/-5%R1039 *10K_NC +/-5%
R1055 10K +/-5%R1055 10K +/-5%
R1040 10K +/-5%R1040 10K +/-5%
+3.3V_RUN
Addres s:0xA6
SA1
SA0
0
0
1
0
1
0
1
1
+1.5V_SUS decoupling caps be located at the VDD pins of each SO-DIMM connector in the
vicinity of the CMD, Clock and Control signals
Those c apaci tors should be place d on t he sa me side of t he mothe rboard as t he
SO-DIMM connector
330uF x 1
10uF x 6
0.1uF x 4
C284
C284
C283
C283
C282
C282
C281
C281
10uF
10uF
6.3V,X5R
6.3V,X5R
10uF
10uF
6.3V,X5R
6.3V,X5R
10uF
10uF
6.3V,X5R
6.3V,X5R
10uF
10uF
6.3V,X5R
6.3V,X5R
DDR_B_MA[0..15](3,17)
DDR_B_BS0(3,17)
DDR_B_BS1(3,17)
DDR_B_BS2(3,17)
DDR_B_CS#2(3)
DDR_B_CS#3(3)
DDR_B_CLK2(3)
DDR_B_CLK#2(3)
DDR_B_CLK3(3)
DDR_B_CLK#3(3)
DDR_B_CKE2(3)
DDR_B_CKE3(3)
DDR_B_CAS#(3,17)
DDR_B_RAS#(3,17)
DDR_B_WE#(3,17)
MEM_SMBCLK(6,10,14,15,17,18,28,36 )
MEM_SMBDAT(6,10,14,15,17,18,28,36)
DDR_B_ODT2(3)
DDR_B_ODT3(3)
DDR_B_DQS[0..7](3,17)
DDR_B_DQS#[0..7](3,17)
Place these Caps near So-DimmB.
C286
C286
C285
C285
10uF
10uF
10uF
10uF
6.3V,X5R
6.3V,X5R
6.3V,X5R
6.3V,X5R
CPU
D D
C C
B B
4
CHB_DIMM1_TOP_SIDE
JDIMM3 is RVS t ype.
98
DDR_B_MA0
97
DDR_B_MA1
96
DDR_B_MA2
95
DDR_B_MA3
92
DDR_B_MA4
91
DDR_B_MA5
90
DDR_B_MA6
86
DDR_B_MA7
89
DDR_B_MA8
85
DDR_B_MA9
107
DDR_B_MA10
84
DDR_B_MA11
83
DDR_B_MA12
119
DDR_B_MA13
80
DDR_B_MA14
78
DDR_B_MA15
109
108
79
114
121
101
103
102
104
73
74
115
110
113
197
201
202
200
116
120
11
28
46
63
136
153
170
187
12
DDR_B_DQS0
29
DDR_B_DQS1
47
DDR_B_DQS2
64
DDR_B_DQS3
137
DDR_B_DQS4
154
DDR_B_DQS5
171
DDR_B_DQS6
188
DDR_B_DQS7
10
DDR_B_DQS#0
27
DDR_B_DQS#1
45
DDR_B_DQS#2
62
DDR_B_DQS#3
135
DDR_B_DQS#4
152
DDR_B_DQS#5
169
DDR_B_DQS#6
186
DDR_B_DQS#7
C289
C289
C288
C288
C287
C287
1uF
1uF
6.3V,X5R
6.3V,X5R
1uF
1uF
6.3V,X5R
6.3V,X5R
1uF
1uF
6.3V,X5R
6.3V,X5R
0526GC: change to RVS type
JDIMM3A
JDIMM3A
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC#
A13
A14
A15
BA0
BA1
BA2
S0#
S1#
CK0
CK0#
CK1
CK1#
CKE0
CKE1
CAS#
RAS#
WE#
SA0
SA1
SCL
SDA
ODT0
ODT1
DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS#0
DQS#1
DQS#2
DQS#3
DQS#4
DQS#5
DQS#6
DQS#7
DDRIII
DDRIII
5
DDR_B_D0
DQ0
7
DDR_B_D1
DQ1
15
DDR_B_D6
DQ2
17
DDR_B_D7
DQ3
4
DDR_B_D5
DQ4
6
DDR_B_D4
DQ5
16
DDR_B_D3
DQ6
18
DDR_B_D2
DQ7
21
DDR_B_D13
DQ8
23
DDR_B_D12
DQ9
33
DDR_B_D14
DQ10
35
DDR_B_D10
DQ11
22
DDR_B_D9
DQ12
24
DDR_B_D8
DQ13
34
DDR_B_D15
DQ14
36
DDR_B_D11
DQ15
39
DDR_B_D21
DQ16
41
DDR_B_D17
DQ17
51
DDR_B_D23
DQ18
53
DDR_B_D18
DQ19
40
DDR_B_D20
DQ20
42
DDR_B_D16
DQ21
50
DDR_B_D19
DQ22
52
DDR_B_D22
DQ23
57
DDR_B_D28
DQ24
59
DDR_B_D25
DQ25
67
DDR_B_D31
DQ26
69
DDR_B_D30
DQ27
56
DDR_B_D24
DQ28
58
DDR_B_D29
DQ29
68
DDR_B_D26
DQ30
70
DDR_B_D27
DQ31
129
DDR_B_D36
DQ32
131
DDR_B_D37
DQ33
141
DDR_B_D34
DDR_B_D39
DDR_B_D33
DDR_B_D32
DDR_B_D35
DDR_B_D38
DDR_B_D40
DDR_B_D41
DDR_B_D43
DDR_B_D46
DDR_B_D45
DDR_B_D44
DDR_B_D47
DDR_B_D42
DDR_B_D51
DDR_B_D48
DDR_B_D54
DDR_B_D55
DDR_B_D53
DDR_B_D50
DDR_B_D49
DDR_B_D52
DDR_B_D56
DDR_B_D60
DDR_B_D62
DDR_B_D63
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D61
+M_VREF_DQ_DIMM0_1
+M_VREF_CA_DIMM0_1
DQ34
143
DQ35
130
DQ36
132
DQ37
140
DQ38
142
DQ39
147
DQ40
149
DQ41
157
DQ42
159
DQ43
146
DQ44
148
DQ45
158
DQ46
160
DQ47
163
DQ48
165
DQ49
175
DQ50
177
DQ51
164
DQ52
166
DQ53
174
DQ54
176
DQ55
181
DQ56
183
DQ57
191
DQ58
193
DQ59
180
DQ60
182
DQ61
192
DQ62
194
DQ63
+1.5V_MEM +0.75V_DDR_VTT+3.3V_RUN
C291
C291
C290
C290
330uF
330uF
1uF
1uF
2.5V,<9mOhm
2.5V,<9mOhm
6.3V,X5R
6.3V,X5R
3
DDR_B_D[0..63] (3,17 )
All VREF traces should have 10 mil trace width
DDR3_DRAMRST#(2, 14,15,17)
M_VREF_DQ_DIMM1(1 7,18)
R807 *0_NC +/-5%R807 *0_NC +/-5%
M_VREF_CA_DIMM1(17,18)
R763 *0_NC +/-5%R763 *0_NC +/-5%
C292
C292
C293
C293
2.2uF
2.2uF
0.1uF
0.1uF
10V,X5R
10V,X5R
16V,X7R
16V,X7R
2.2uF
2.2uF
10V,X5R
10V,X5R
2.2uF
2.2uF
10V,X5R
10V,X5R
C974
C974
1uF
1uF
6.3V,X5R
6.3V,X5R
2
1
DDR3 Length Matching Formulas
Signal Group Min Length Max Length
Control-to-Clock
Command-to-Clock
Strobe-to-Clock
Data-to-Strobe (per byte lane)
+1.5V_MEM
JDIMM3B
JDIMM3B
75
76
81
82
87
88
93
94
99
100
105
106
111
112
117
118
123
124
199
+3.3V_RUN
77
122
125
198
TS#_DIMMB
T148T148
DRAMRST_DIMMB0
C277
C277
C279
C279
C278
C278
0.1uF
0.1uF
16V,X7R
16V,X7R
C280
C280
0.1uF
0.1uF
16V,X7R
16V,X7R
30
1
126
2
3
8
9
13
14
19
20
25
26
31
32
37
38
43
DDRIII
DDRIII
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11
VDD12
VDD13
VDD14
VDD15
VDD16
VDD17
VDD18
VDDSPD
NC1
NC2
NCTEST
EVENT#
RESET#
VREF_DQ
VREF_CA
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
GND#2-G2
VTT1
VTT2
GND
44
48
49
54
55
60
61
65
66
71
72
127
128
133
134
138
139
144
145
150
151
155
156
161
162
167
168
172
173
178
179
184
185
189
190
195
196
+0.75V_DDR_VTT
203
204
G1
G2
1uF x 4
C976
C976
C975
C975
1uF
1uF
6.3V,X5R
6.3V,X5R
1uF
1uF
6.3V,X5R
6.3V,X5R
C977
C977
1uF
1uF
6.3V,X5R
6.3V,X5R
Clock - 0.5"
Clock - 0.5"
Clock - 0.5"
Strobe - 20 mils
Clock - 0.0"
Clock - 0.5"
Clock - 1.0"
Strobe + 20 mils
A A
Ever Light
Ever Light
Ever Light
Technology Limited
Technology Limited
Technology Limited
Title
Title
Title
17 -- SODIMM-204P-B0
17 -- SODIMM-204P-B0
17 -- SODIMM-204P-B0
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Thunder 1A
Thunder 1A
Thunder 1A
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet
1
of
16 84Thursday , Ja nuary 27, 2 011
16 84Thursday , Ja nuary 27, 2 011
16 84Thursday , Ja nuary 27, 2 011
5
WWW.MANUALS.CLAN.SU
B (A2)
D (A6)
JDIMM1
CPU
A (A0)
D D
C C
CHA0
CHA1
CHB0
CHB1
B B
JDIMM3
JDIMM2
JDIMM4
C (A4)
DDR_B_MA[0..15](3,16)
R1054 10K +/-5%R1054 10K +/-5%
R362 *10K_NC +/-5%R362 *10K_NC +/-5%
R363 10K +/-5%R363 10K +/-5%
Addres s:0xA4
SA0
0
1
0
1
+1.5V_SUS decoupling caps be located at the VDD pins of each SO-DIMM connector in the
vicinity of the CMD, Clock and Control signals
Those c apaci tors should be place d on t he sa me side of t he mothe rboard as t he
SO-DIMM connector
330uF x 1
C299
C299
10uF
10uF
6.3V,X5R
6.3V,X5R
10uF x 6
0.1uF x 4
C300
C300
10uF
10uF
6.3V,X5R
6.3V,X5R
Place these Caps near So-DimmB.
C301
C301
C302
C302
10uF
10uF
10uF
10uF
6.3V,X5R
6.3V,X5R
6.3V,X5R
6.3V,X5R
SA1
0
0
1
1
C298
C298
10uF
10uF
6.3V,X5R
6.3V,X5R
+3.3V_RUN
DDR_B_BS0(3,16)
DDR_B_BS1(3,16)
DDR_B_BS2(3,16)
DDR_B_CS#0(3)
DDR_B_CS#1(3)
DDR_B_CLK0(3)
DDR_B_CLK#0(3)
DDR_B_CLK1(3)
DDR_B_CLK#1(3)
DDR_B_CKE0(3)
DDR_B_CKE1(3)
DDR_B_CAS#(3,16)
DDR_B_RAS#(3,16)
DDR_B_WE#(3,16)
MEM_SMBCLK(6,10,14,15,16,18,28,36 )
MEM_SMBDAT(6,10,14,15,16,18,28,36)
DDR_B_ODT0(3)
DDR_B_ODT1(3)
DDR_B_DQS[0..7](3,16)
DDR_B_DQS#[0..7](3,16)
C303
C303
10uF
10uF
6.3V,X5R
6.3V,X5R
4
CHB_DIMM0_BOT_SIDE
JDIMM4 is STD type.
98
DDR_B_MA0
97
DDR_B_MA1
96
DDR_B_MA2
95
DDR_B_MA3
92
DDR_B_MA4
91
DDR_B_MA5
90
DDR_B_MA6
86
DDR_B_MA7
89
DDR_B_MA8
85
DDR_B_MA9
107
DDR_B_MA10
84
DDR_B_MA11
83
DDR_B_MA12
119
DDR_B_MA13
80
DDR_B_MA14
78
DDR_B_MA15
109
108
79
114
121
101
103
102
104
73
74
115
110
113
197
201
202
200
116
120
11
28
46
63
136
153
170
187
12
DDR_B_DQS0
29
DDR_B_DQS1
47
DDR_B_DQS2
64
DDR_B_DQS3
137
DDR_B_DQS4
154
DDR_B_DQS5
171
DDR_B_DQS6
188
DDR_B_DQS7
10
DDR_B_DQS#0
27
DDR_B_DQS#1
45
DDR_B_DQS#2
62
DDR_B_DQS#3
135
DDR_B_DQS#4
152
DDR_B_DQS#5
169
DDR_B_DQS#6
186
DDR_B_DQS#7
C305
C305
C306
1uF
1uF
6.3V,X5R
6.3V,X5R
C306
1uF
1uF
6.3V,X5R
6.3V,X5R
C304
C304
1uF
1uF
6.3V,X5R
6.3V,X5R
0510GC: CIS OK
JDIMM4A
JDIMM4A
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC#
A13
A14
A15
BA0
BA1
BA2
S0#
S1#
CK0
CK0#
CK1
CK1#
CKE0
CKE1
CAS#
RAS#
WE#
SA0
SA1
SCL
SDA
ODT0
ODT1
DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS#0
DQS#1
DQS#2
DQS#3
DQS#4
DQS#5
DQS#6
DQS#7
DDRIII
DDRIII
5
DDR_B_D5
DQ0
7
DDR_B_D4
DQ1
15
DDR_B_D3
DQ2
17
DDR_B_D2
DQ3
4
DDR_B_D0
DQ4
6
DDR_B_D1
DQ5
16
DDR_B_D6
DQ6
18
DDR_B_D7
DQ7
21
DDR_B_D9
DQ8
23
DDR_B_D8
DQ9
33
DDR_B_D15
DQ10
35
DDR_B_D11
DQ11
22
DDR_B_D13
DQ12
24
DDR_B_D12
DQ13
34
DDR_B_D14
DQ14
36
DDR_B_D10
DQ15
39
DDR_B_D20
DQ16
41
DDR_B_D16
DQ17
51
DDR_B_D22
DQ18
53
DDR_B_D19
DQ19
40
DDR_B_D21
DQ20
42
DDR_B_D17
DQ21
50
DDR_B_D23
DQ22
52
DDR_B_D18
DQ23
57
DDR_B_D24
DQ24
59
DDR_B_D29
DQ25
67
DDR_B_D26
DQ26
69
DDR_B_D27
DQ27
56
DDR_B_D28
DQ28
58
DDR_B_D25
DQ29
68
DDR_B_D31
DQ30
70
DDR_B_D30
DQ31
129
DDR_B_D33
DQ32
131
DDR_B_D32
DQ33
141
DDR_B_D35
DDR_B_D38
DDR_B_D36
DDR_B_D37
DDR_B_D34
DDR_B_D39
DDR_B_D45
DDR_B_D44
DDR_B_D47
DDR_B_D42
DDR_B_D40
DDR_B_D41
DDR_B_D43
DDR_B_D46
DDR_B_D53
DDR_B_D50
DDR_B_D49
DDR_B_D52
DDR_B_D51
DDR_B_D48
DDR_B_D54
DDR_B_D55
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D61
DDR_B_D56
DDR_B_D60
DDR_B_D62
DDR_B_D63
+M_VREF_DQ_DIMM0_1
+M_VREF_CA_DIMM0_1
DQ34
143
DQ35
130
DQ36
132
DQ37
140
DQ38
142
DQ39
147
DQ40
149
DQ41
157
DQ42
159
DQ43
146
DQ44
148
DQ45
158
DQ46
160
DQ47
163
DQ48
165
DQ49
175
DQ50
177
DQ51
164
DQ52
166
DQ53
174
DQ54
176
DQ55
181
DQ56
183
DQ57
191
DQ58
193
DQ59
180
DQ60
182
DQ61
192
DQ62
194
DQ63
+1.5V_MEM +0.75V_DDR_VTT+3.3V_RUN
C307
C307
C308
C308
1uF
1uF
330uF
330uF
6.3V,X5R
6.3V,X5R
2.5V,<9mOhm
2.5V,<9mOhm
3
DDR_B_D[0..63] (3,16 )
All VREF traces should have 10 mil trace width
DDR3_DRAMRST#(2, 14,15,16)
M_VREF_DQ_DIMM1(1 6,18)
R810 *0_NC +/-5%R810 *0_NC +/-5%
M_VREF_CA_DIMM1(16,18)
R808 *0_NC +/-5%R808 *0_NC +/-5%
C309
C309
2.2uF
2.2uF
10V,X5R
10V,X5R
C310
C310
0.1uF
0.1uF
16V,X7R
16V,X7R
10V,X5R
10V,X5R
10V,X5R
10V,X5R
C311
C311
1uF
1uF
6.3V,X5R
6.3V,X5R
2
1
DDR3 Length Matching Formulas
Signal Group Min Length Max Length
Control-to-Clock
Command-to-Clock
Strobe-to-Clock
Data-to-Strobe (per byte lane)
+1.5V_MEM
JDIMM4B
JDIMM4B
75
76
81
82
87
88
93
94
99
100
105
106
111
112
117
118
123
124
199
+3.3V_RUN
77
122
125
198
TS#_DIMMB0
T149T149
DRAMRST_DIMMB1
C294
C294
2.2uF
2.2uF
C296
C296
2.2uF
2.2uF
C295
C295
0.1uF
0.1uF
16V,X7R
16V,X7R
C297
C297
0.1uF
0.1uF
16V,X7R
16V,X7R
30
1
126
2
3
8
9
13
14
19
20
25
26
31
32
37
38
43
DDRIII
DDRIII
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11
VDD12
VDD13
VDD14
VDD15
VDD16
VDD17
VDD18
VDDSPD
NC1
NC2
NCTEST
EVENT#
RESET#
VREF_DQ
VREF_CA
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
GND#2-G2
VTT1
VTT2
GND
44
48
49
54
55
60
61
65
66
71
72
127
128
133
134
138
139
144
145
150
151
155
156
161
162
167
168
172
173
178
179
184
185
189
190
195
196
+0.75V_DDR_VTT
203
204
G1
G2
1uF x 4
C312
C312
1uF
1uF
6.3V,X5R
6.3V,X5R
C313
C313
1uF
1uF
6.3V,X5R
6.3V,X5R
C314
C314
1uF
1uF
6.3V,X5R
6.3V,X5R
Clock - 0.5"
Clock - 0.5"
Clock - 0.5"
Strobe - 20 mils
Clock - 0.0"
Clock - 0.5"
Clock - 1.0"
Strobe + 20 mils
A A
Ever Light
Ever Light
Ever Light
Technology Limited
Technology Limited
Technology Limited
Title
Title
Title
16 -- SODIMM-204P-B0
16 -- SODIMM-204P-B0
16 -- SODIMM-204P-B0
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Thunder 1A
Thunder 1A
Thunder 1A
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet
1
of
17 84Thursday , Ja nuary 27, 2 011
17 84Thursday , Ja nuary 27, 2 011
17 84Thursday , Ja nuary 27, 2 011
5
WWW.MANUALS.CLAN.SU
M1: Fixed SO-DIMM VREF_DQ (Default)
+1.5V_MEM
R364
R364
1K
1K
+/-1%
D D
C C
+/-1%
M_VREF_DQ_DIMM0_L
R369
R369
1K
1K
+/-1%
+/-1%
+1.5V_MEM
R372
R372
1K
1K
+/-1%
+/-1%
M_VREF_DQ_DIMM1_L
R379
R379
1K
1K
+/-1%
+/-1%
C317
C317
0.1uF
0.1uF
16V,X7R
16V,X7R
C322
C322
0.1uF
0.1uF
16V,X7R
16V,X7R
R366 0
R366 0
R375 0
R375 0
+/-5%
+/-5%
+/-5%
+/-5%
M_VREF_DQ_DIMM0 (1 4,15)
M_VREF_DQ_DIMM1 (1 6,17)
For CH A SO-DIMM VREF_DQ
For CH B SO-DIMM VREF_DQ
4
3
2
1
M2: Programmable SODIMM VREFDQ
+3.3V_SUS
C315
C315
*1uF_NC
*1uF_NC
U6
U6
6.3V,X5R
6.3V,X5R
*ISL90727WIE627Z-TK_NC
*ISL90727WIE627Z-TK_NC
1
VDD
MEM_SMBCLK(6,10,14,15,16,17,28,36 )
MEM_SMBDAT(6,10,14,15,16,17,28,36)
MEM_SMBCLK(6,10,14,15,16,17,28,36 )
MEM_SMBDAT(6,10,14,15,16,17,28,36)
3
SCL
4
SDA
Potentiometers 90727
SMBus Addr = 5Ch
+3.3V_SUS +1.5V_MEM +3.3V_SUS
C319
C319
*1uF_NC
*1uF_NC
U8
U8
6.3V,X5R
6.3V,X5R
*ISL90728WIE627Z-TK_NC
*ISL90728WIE627Z-TK_NC
1
VDD
3
SCL
4
SDA
Potentiometers 90728
SMBus Addr = 7Ch
+1.5V_MEM +3.3V_SUS
R365
R365
6
*12.1K_NC
*12.1K_NC
RH
+/-1%
+/-1%
5
+VREF_RW_PO0
RW
2
GND
R370
R370
*12.1K_NC
*12.1K_NC
+/-1%
+/-1%
R373
R373
6
*12.1K_NC
*12.1K_NC
RH
+/-1%
+/-1%
5
+VREF_RW_PO1
RW
2
GND
R377
R377
*12.1K_NC
*12.1K_NC
+/-1%
+/-1%
C316
C316
*1uF_NC
*1uF_NC
6.3V,X5R
6.3V,X5R
U7
U7
5
*LMV321SQ3T2G_NC
*LMV321SQ3T2G_NC
1
+
+
4
+VREF_OPA_PO0 +VREF_OPA_POT0_R
3
-
-
2
C320
C320
*1uF_NC
*1uF_NC
6.3V,X5R
6.3V,X5R
U9
U9
5
*LMV321SQ3T2G_NC
*LMV321SQ3T2G_NC
1
+
+
4
+VREF_OPA_PO1 +VREF_OPA_POT1_R
3
-
-
2
R367
R367
*2.2_NC +/ -5%
*2.2_NC +/ -5%
Discharge Circuits
PP_S4GT
R374
R374
*2.2_NC +/ -5%
*2.2_NC +/ -5%
Discharge Circuits
PP_S4GT
All VREF traces should have 10 mil trace width
R368 *0_NC
R368 *0_NC
R371
R371
*10_NC
*10_NC
+/-5%
+/-5%
D
Q10
Q10
*2N7002W-7-F_NC
*2N7002W-7-F_NC
G
S
All VREF traces should have 10 mil trace width
R376 *0_NC
R376 *0_NC
R378
R378
*10_NC
*10_NC
+/-5%
+/-5%
D
Q11
Q11
*2N7002W-7-F_NC
*2N7002W-7-F_NC
G
S
+/-5%
+/-5%
+/-5%
+/-5%
M_VREF_DQ_DIMM0 (1 4,15)
C318
C318
*1uF_NC
*1uF_NC
6.3V,X5R
6.3V,X5R
M_VREF_DQ_DIMM1 (1 6,17)
C321
C321
*1uF_NC
*1uF_NC
6.3V,X5R
6.3V,X5R
B B
A A
+1.5V_MEM
R381
R381
1K
1K
+/-1%
+/-1%
C323
C323
R384
R384
0.1uF
0.1uF
1K
1K
16V,X7R
16V,X7R
+/-1%
+/-1%
+1.5V_MEM
R385
R385
1K
1K
+/-1%
+/-1%
C324
C324
R387
R387
0.1uF
0.1uF
1K
1K
16V,X7R
16V,X7R
+/-1%
+/-1%
5
For CH A SO-DIMM VREF_CA
R382 0
R382 0
M_VREF_CA_DIMM0 (14, 15)
+/-5%
+/-5%
For CH B SO-DIMM VREF_CA
R386 0
R386 0
M_VREF_CA_DIMM1 (16, 17)
+/-5%
+/-5%
SIO_SLP_S4#(7,40)
4
3
+5V_ALW
R380
R380
*100K_NC
*100K_NC
+/-5%
+/-5%
PP_S4GT
D
G
S
Q12
Q12
*2N7002W-7-F_NC
*2N7002W-7-F_NC
2
R383
R383
*1M_NC
*1M_NC
+/-5%
+/-5%
Ever Light
Ever Light
Ever Light
Technology Limited
Technology Limited
Technology Limited
Title
Title
Title
18 -- DDR3 VREF
18 -- DDR3 VREF
18 -- DDR3 VREF
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Thunder 1A
Thunder 1A
Thunder 1A
Date: Sheet of
Date: Sheet of
Date: Sheet
1
of
18 84Thursday , Ja nuary 27, 2 011
18 84Thursday , Ja nuary 27, 2 011
18 84Thursday , Ja nuary 27, 2 011
5
WWW.MANUALS.CLAN.SU
+PWR_SRC_MXM
+5V_RUN_MXM
2.5 A
C326
C326
10uF
10uF
6.3V,X5R
PEX swing slect
0: High swing.
NC: Lowing swing
6.3V,X5R
MXM_LCDVCC_EN(22)
PANEL_BKEN_DGPU(22)
MXM_LCD_BL_PWM(22)
CEC MXM Internal PU.
MXM_LCD_DDC_DATA(22)
MXM_LCD_DDC_CLK(22)
PEG_CRX_GTX_N15_C
PEG_CRX_GTX_P15_C
PEG_CRX_GTX_N14_C
PEG_CRX_GTX_P14_C
PEG_CRX_GTX_N13_C
PEG_CRX_GTX_P13_C
PEG_CRX_GTX_N12_C
PEG_CRX_GTX_P12_C
PEG_CRX_GTX_N11_C
PEG_CRX_GTX_P11_C
PEG_CRX_GTX_N10_C
PEG_CRX_GTX_P10_C
PEG_CRX_GTX_N9_C
PEG_CRX_GTX_P9_C
PEG_CRX_GTX_N8_C
PEG_CRX_GTX_P8_C
PEG_CRX_GTX_N7_C
PEG_CRX_GTX_P7_C
PEG_CRX_GTX_N6_C
PEG_CRX_GTX_P6_C
PEG_CRX_GTX_N5_C
PEG_CRX_GTX_P5_C
PEG_CRX_GTX_N4_C
PEG_CRX_GTX_P4_C
PEG_CRX_GTX_N3_C
PEG_CRX_GTX_P3_C
PEG_CRX_GTX_N2_C
PEG_CRX_GTX_P2_C
PEG_CRX_GTX_N1_C
PEG_CRX_GTX_P1_C
PEG_CRX_GTX_N0_C
PEG_CRX_GTX_P0_C
CLK_PCIE_PEG#(10)
CLK_PCIE_PEG(10)
1.Whole TX & RX AC decoupling
Cap(64 pcs) need to place within
0.5" of MXM Conn
2.TX cap at CPU Side
PEG_CTX_GRX_N15_C
PEG_CTX_GRX_N14_C
PEG_CTX_GRX_N13_C
PEG_CTX_GRX_N12_C
PEG_CTX_GRX_N11_C
PEG_CTX_GRX_N10_C
PEG_CTX_GRX_N9_C
PEG_CTX_GRX_N8_C
PEG_CTX_GRX_N7_C
PEG_CTX_GRX_N6_C
PEG_CTX_GRX_N5_C
PEG_CTX_GRX_N4_C
PEG_CTX_GRX_N3_C
PEG_CTX_GRX_N2_C
PEG_CTX_GRX_N1_C
PEG_CTX_GRX_N0_C
PEG_CTX_GRX_P15_C
PEG_CTX_GRX_P14_C
PEG_CTX_GRX_P13_C
PEG_CTX_GRX_P12_C
PEG_CTX_GRX_P11_C
PEG_CTX_GRX_P10_C
PEG_CTX_GRX_P9_C
PEG_CTX_GRX_P8_C
PEG_CTX_GRX_P7_C
PEG_CTX_GRX_P6_C
PEG_CTX_GRX_P5_C
PEG_CTX_GRX_P4_C
PEG_CTX_GRX_P3_C
PEG_CTX_GRX_P2_C
PEG_CTX_GRX_P1_C
PEG_CTX_GRX_P0_C
D D
C C
B B
A A
C325
C325
22uF
22uF
25V,X5R
25V,X5R
C327
C327
2.2uF
2.2uF
10V,X5R
10V,X5R
R391 0R391 0
R392 *0_NCR392 *0_NC
MXM SPEC:
7~20V, Up to 10A
JMXM1A
JMXM1A
E1
PWR_SRC_E1
E3
GND_E3
1
5V_1
3
5V_3
5
5V_5
7
5V_7
9
5V_9
11
GND_11
13
GND_13
15
GND_15
17
GND_17
19
PEX_STD_SW#_19
21
VGA_DISABLE#_21
23
PNL_PWR_EN_23
25
PNL_BL_EN_25
27
PNL_BL_PWM_27
29
HDMI_CEC _29
31
DVI_HPD_31
33
LVDS_DDC_DAT_33
35
LVDS_DDC_CLK_35
37
GND_37
39
OEM_39
41
OEM_41
43
OEM_43
45
OEM_45
47
GND_47
49
PEX_RX15#_49
51
PEX_RX15_51
53
GND_53
55
PEX_RX14#_55
57
PEX_RX14_57
59
GND_59
61
PEX_RX13#_61
63
PEX_RX13_63
65
GND_65
67
PEX_RX12#_67
69
PEX_RX12_69
71
GND_71
73
PEX_RX11#_73
75
PEX_RX11_75
77
GND_77
79
PEX_RX10#_79
81
PEX_RX10_81
83
GND_83
85
PEX_RX9#_85
87
PEX_RX9_87
89
GND_89
91
PEX_RX8#_91
93
PEX_RX8_93
95
GND_95
97
PEX_RX7#_97
99
PEX_RX7_99
101
GND_101
103
PEX_RX6#_103
105
PEX_RX6_105
107
GND_107
109
PEX_RX5#_109
111
PEX_RX5_111
113
GND_113
115
PEX_RX4#_115
117
PEX_RX4_117
119
GND_119
121
PEX_RX3#_121
123
PEX_RX3_123
125
GND_125
133
GND_133
135
PEX_RX2#_135
137
PEX_RX2_137
139
GND_139
141
PEX_RX1#_141
143
PEX_RX1_143
145
GND_145
147
PEX_RX0#_147
149
PEX_RX0_149
151
GND_151
153
PEX_REFCLK#_153
155
PEX_REFCLK_155
CONN-PCI-X
CONN-PCI-X
PEG_CTX_GRX_N15_C (2)
PEG_CTX_GRX_N14_C (2)
PEG_CTX_GRX_N13_C (2)
PEG_CTX_GRX_N12_C (2)
PEG_CTX_GRX_N11_C (2)
PEG_CTX_GRX_N10_C (2)
PEG_CTX_GRX_N9_C (2)
PEG_CTX_GRX_N8_C (2)
PEG_CTX_GRX_N7_C (2)
PEG_CTX_GRX_N6_C (2)
PEG_CTX_GRX_N5_C (2)
PEG_CTX_GRX_N4_C (2)
PEG_CTX_GRX_N3_C (2)
PEG_CTX_GRX_N2_C (2)
PEG_CTX_GRX_N1_C (2)
PEG_CTX_GRX_N0_C (2)
PEG_CTX_GRX_P15_C (2)
PEG_CTX_GRX_P14_C (2)
PEG_CTX_GRX_P13_C (2)
PEG_CTX_GRX_P12_C (2)
PEG_CTX_GRX_P11_C (2)
PEG_CTX_GRX_P10_C (2)
PEG_CTX_GRX_P9_C (2)
PEG_CTX_GRX_P8_C (2)
PEG_CTX_GRX_P7_C (2)
PEG_CTX_GRX_P6_C (2)
PEG_CTX_GRX_P5_C (2)
PEG_CTX_GRX_P4_C (2)
PEG_CTX_GRX_P3_C (2)
PEG_CTX_GRX_P2_C (2)
PEG_CTX_GRX_P1_C (2)
PEG_CTX_GRX_P0_C (2)
5
0524GC: CIS OK
Part 1 of 2
Part 1 of 2
Mechanical Key
Mechanical Key
PEX_CLK_REQ#_154
+PWR_SRC_MXM
E2
PWR_SRC_E2
E4
GND_E4
2
PRSNT_R#_2
4
R389 *0_NCR389 *0_NC
WAKE#_4
6
PWR_GOOD_6
8
PWR_EN_8
10
RSVD_10
12
RSVD_12
14
RSVD_14
16
RSVD_16
18
PWR_LEVEL_18
20
TH_OVERT#_20
22
TH_ALERT#_22
24
TH_PWM_24
26
T152T152
GPIO0_26
28
T153T153
GPIO1_28
30
GPIO2_30
32
SMB_DAT_32
34
SMB_CLK_34
36
GND_36
38
OEM_38
40
OEM_40
42
OEM_42
44
OEM_44
46
GND_46
48
PEX_TX15#_48
50
PEX_TX15_50
52
GND_52
54
PEX_TX14#_54
56
PEX_TX14_56
58
GND_58
60
PEX_TX13#_60
62
PEX_TX13_62
64
GND_64
66
PEX_TX12#_66
68
PEX_TX12_68
70
GND_70
72
PEX_TX11#_72
74
PEX_TX11_74
76
GND_76
78
PEX_TX10#_78
80
PEX_TX10_80
82
GND_82
84
PEX_TX9#_84
86
PEX_TX9_86
88
GND_88
90
PEX_TX8#_90
92
PEX_TX8_92
94
GND_94
96
PEX_TX7#_96
98
PEX_TX7_98
100
GND_100
102
PEX_TX6#_102
104
PEX_TX6_104
106
GND_106
108
PEX_TX5#_108
110
PEX_TX5_110
112
GND_112
114
PEX_TX4#_114
116
PEX_TX4_116
118
GND_118
120
PEX_TX3#_120
122
PEX_TX3_122
124
GND_124
134
GND_134
136
PEX_TX2#_136
138
PEX_TX2_138
140
GND_140
142
PEX_TX1#_142
144
PEX_TX1_144
146
GND_146
148
PEX_TX0#_148
150
PEX_TX0_150
152
GND_152
154
156
PEX_RST#_156
PEG_CLK_REQ#
MXM PEG SPEC
Length Low swin g: 7 inches High swi ng: 10 inches
PEG_CRX_GTX_N15_C
C331 220nF 16V,X7RC331 220nF 16V,X7R
PEG_CRX_GTX_N14_C
C332 220nF 16V,X7RC332 220nF 16V,X7R
PEG_CRX_GTX_N13_C
C333 220nF 16V,X7RC333 220nF 16V,X7R
PEG_CRX_GTX_N12_C
C334 220nF 16V,X7RC334 220nF 16V,X7R
PEG_CRX_GTX_N11_C
C335 220nF 16V,X7RC335 220nF 16V,X7R
PEG_CRX_GTX_N10_C
C336 220nF 16V,X7RC336 220nF 16V,X7R
PEG_CRX_GTX_N9_C
C337 220nF 16V,X7RC337 220nF 16V,X7R
PEG_CRX_GTX_N8_C
C339 220nF 16V,X7RC339 220nF 16V,X7R
PEG_CRX_GTX_N7_C
C340 220nF 16V,X7RC340 220nF 16V,X7R
PEG_CRX_GTX_N6_C
C341 220nF 16V,X7RC341 220nF 16V,X7R
PEG_CRX_GTX_N5_C
C342 220nF 16V,X7RC342 220nF 16V,X7R
PEG_CRX_GTX_N4_C
C343 220nF 16V,X7RC343 220nF 16V,X7R
PEG_CRX_GTX_N3_C
C344 220nF 16V,X7RC344 220nF 16V,X7R
PEG_CRX_GTX_N2_C
C345 220nF 16V,X7RC345 220nF 16V,X7R
PEG_CRX_GTX_N1_C
C346 220nF 16V,X7RC346 220nF 16V,X7R
PEG_CRX_GTX_N0_C
C347 220nF 16V,X7RC347 220nF 16V,X7R
PEG_CRX_GTX_P15_C
C348 220nF 16V,X7RC348 220nF 16V,X7R
PEG_CRX_GTX_P14_C
C349 220nF 16V,X7RC349 220nF 16V,X7R
PEG_CRX_GTX_P13_C
C350 220nF 16V,X7RC350 220nF 16V,X7R
PEG_CRX_GTX_P12_C
C351 220nF 16V,X7RC351 220nF 16V,X7R
PEG_CRX_GTX_P11_C
C352 220nF 16V,X7RC352 220nF 16V,X7R
PEG_CRX_GTX_P10_C
C354 220nF 16V,X7RC354 220nF 16V,X7R
PEG_CRX_GTX_P9_C
C353 220nF 16V,X7RC353 220nF 16V,X7R
PEG_CRX_GTX_P8_C
C355 220nF 16V,X7RC355 220nF 16V,X7R
PEG_CRX_GTX_P7_C
C356 220nF 16V,X7RC356 220nF 16V,X7R
PEG_CRX_GTX_P6_C
C357 220nF 16V,X7RC357 220nF 16V,X7R
PEG_CRX_GTX_P5_C
C358 220nF 16V,X7RC358 220nF 16V,X7R
PEG_CRX_GTX_P4_C
C359 220nF 16V,X7RC359 220nF 16V,X7R
PEG_CRX_GTX_P3_C
C360 220nF 16V,X7RC360 220nF 16V,X7R
PEG_CRX_GTX_P2_C
C361 220nF 16V,X7RC361 220nF 16V,X7R
PEG_CRX_GTX_P1_C
C362 220nF 16V,X7RC362 220nF 16V,X7R
PEG_CRX_GTX_P0_C
C363 220nF 16V,X7RC363 220nF 16V,X7R
4
MXM 3.0 C0NNECTOR
+3.3V_RUN
R388
T150T150
T151T151
GPU internal PU.
MXM_PWR_LEVEL
MXM_OVERT#
MXM_ALERT#
T154T154
MXM_SMBDAT_C
MXM_SMBCLK_C
R398 0R398 0
PEG_CTX_GRX_N15_C
PEG_CTX_GRX_P15_C
PEG_CTX_GRX_N14_C
PEG_CTX_GRX_P14_C
PEG_CTX_GRX_N13_C
PEG_CTX_GRX_P13_C
PEG_CTX_GRX_N12_C
PEG_CTX_GRX_P12_C
PEG_CTX_GRX_N11_C
PEG_CTX_GRX_P11_C
PEG_CTX_GRX_N10_C
PEG_CTX_GRX_P10_C
PEG_CTX_GRX_N9_C
PEG_CTX_GRX_P9_C
PEG_CTX_GRX_N8_C
PEG_CTX_GRX_P8_C
PEG_CTX_GRX_N7_C
PEG_CTX_GRX_P7_C
PEG_CTX_GRX_N6_C
PEG_CTX_GRX_P6_C
PEG_CTX_GRX_N5_C
PEG_CTX_GRX_P5_C
PEG_CTX_GRX_N4_C
PEG_CTX_GRX_P4_C
PEG_CTX_GRX_N3_C
PEG_CTX_GRX_P3_C
PEG_CTX_GRX_N2_C
PEG_CTX_GRX_P2_C
PEG_CTX_GRX_N1_C
PEG_CTX_GRX_P1_C
PEG_CTX_GRX_N0_C
PEG_CTX_GRX_P0_C
PEG_CLK_REQ#
+3.3V_RUN_MXM
R767
R767
10K
10K
+/-5%
+/-5%
R388
100K
100K
+/-5%
+/-5%
DGPU_PWR_GOOD
DGPU_PWREN
PEX_TX : connect to CPU TX
connect to MXM RX
PEX_RX : connect to CPU RX
connect to MXM TX
MXM_RST#
+3.3V_RUN_MXM
G
Q24
Q24
DS
2N7002W-7-F
2N7002W-7-F
PEG_CRX_GTX_N15
PEG_CRX_GTX_N14
PEG_CRX_GTX_N13
PEG_CRX_GTX_N12
PEG_CRX_GTX_N11
PEG_CRX_GTX_N10
PEG_CRX_GTX_N9
PEG_CRX_GTX_N8
PEG_CRX_GTX_N7
PEG_CRX_GTX_N6
PEG_CRX_GTX_N5
PEG_CRX_GTX_N4
PEG_CRX_GTX_N3
PEG_CRX_GTX_N2
PEG_CRX_GTX_N1
PEG_CRX_GTX_N0
PEG_CRX_GTX_P15
PEG_CRX_GTX_P14
PEG_CRX_GTX_P13
PEG_CRX_GTX_P12
PEG_CRX_GTX_P11
PEG_CRX_GTX_P10
PEG_CRX_GTX_P9
PEG_CRX_GTX_P8
PEG_CRX_GTX_P7
PEG_CRX_GTX_P6
PEG_CRX_GTX_P5
PEG_CRX_GTX_P4
PEG_CRX_GTX_P3
PEG_CRX_GTX_P2
PEG_CRX_GTX_P1
PEG_CRX_GTX_P0
4
MXM_PIN44 (36)
PEG_CLKREQ# (10)
To GPIO
module s ide is GND
MXM_PRESENT2# (11)
PCIE_WAKE# (31,33,34,40,60)
+3.3V_RUN_MXM
SDM10K45-7-F
SDM10K45-7-F
D66
D66
C A
R390
R390
100K
100K
+/-5%
+/-5%
+3.3V_RUN_MXM
5
4
VCC
Y
GND
74LVC1G08
74LVC1G08
3
R1071
R1071
100K
100K
+/-5%
+/-5%
PEG_CRX_GTX_N[0..15] (2)
PEG_CRX_GTX_P[0..15] (2)
G
Q32
Q32
DS
2N7002W-7-F
2N7002W-7-F
DOCK_DP2_HPD_GATE
R1072
R1072
100K
100K
+/-5%
+/-5%
MXM_MBDP_HPD_GATE
R1082
R1082
100K
100K
+/-5%
+/-5%
MXM_DPC_HPD_GATE
R1083
R1083
100K
100K
+/-5%
+/-5%
C988 0.1uF 16V,Y5VC988 0.1uF 16V,Y5V
U70
U70
1
PCH_PLTRST1# (6,9,31,49,55)
B
2
A
C1006 0.1uF
+3.3V_RUN_MXM
4
R1064
R1064
100K
100K
+/-5%
+/-5%
C1006 0.1uF
R801 10K +/-5%R801 10K +/-5%
DGPU_PWR_GOOD
DGPU_PWR_EN
+3.3V_RUN_MXM
R802
R802
10K
10K
+/-5%
+/-5%
DGPU_PWREN DGPU_PWR_EN
from GPIO
DGPU_PWR_LEVEL (40)
+3.3V_RUN_MXM
C985 0.1uF 16V,Y5VC985 0.1uF 16V,Y5V
5
U71
U71
1
DOCK_DP2_HPD (27,40)
B
4
VCC
Y
2
DGPU_PWROK
A
GND
74LVC1G08
74LVC1G08
3
+3.3V_RUN_MXM
C986 0.1uF 16V,Y5VC986 0.1uF 16V,Y5V
5
U72
U72
1
MXM_MBDP_HPD (23, 40)
B
4
VCC
Y
2
DGPU_PWROK
A
GND
74LVC1G08
74LVC1G08
3
+3.3V_RUN_MXM
C987 0.1uF 16V,Y5VC987 0.1uF 16V,Y5V
5
U73
U73
1
MXM_DPC_HPD (25,40)
B
VCC
Y
2
DGPU_PWROK
A
GND
74LVC1G08
74LVC1G08
3
DGPU_HOLD_RST# (11)
MXM_OVERT# MXM_ALERT#
GPU internal PU.
MXM_SMBCLK_C
GPU internal PU.
MXM_SMBDAT_C
3
+3.3V_RUN
9.
16V,Y5V
16V,Y5V
U78
U78
74LVC1G08
74LVC1G08
5
1
B
4
Y
GND
MXM_PRESENT1#(11)
To GPIO
module s ide is GND
+3.3V_RUN_MXM
2.
DGPU_PWROK (11,40)
DGPU_PWR_EN (40)
DOCK DP1
MB HDMI
D74
D74
*SDM10K45-7-F_NC
*SDM10K45-7-F_NC
C A
R1841 *2.2K_NC +/-5%R1841 *2.2K_NC +/-5%
R1842 *2.2K_NC +/-5%R1842 *2.2K_NC +/-5%
MB DP Port
MXM_MBDP_AUX#(23)
MXM_MBDP_AUX(23)
MXM_DPC_TX0#(25)
MXM_DPC_TX0(25)
MXM_DPC_TX1#(25)
MXM_DPC_TX1(25)
MXM_DPC_TX2#(25)
MXM_DPC_TX2(25)
MXM_DPC_TX3#(25)
MXM_DPC_TX3(25)
MXM_DPC_AUX#(25)
MXM_DPC_AUX(25)
PU at PCH.
MXM_LVDS_UCLK#(21)
MXM_LVDS_UCLK(21)
MXM_LVDS_UTX3#(21)
MXM_LVDS_UTX3(21)
MXM_LVDS_UTX2#(21)
MXM_LVDS_UTX2(21)
MXM_LVDS_UTX1#(21)
MXM_LVDS_UTX1(21)
MXM_LVDS_UTX0#(21)
MXM_LVDS_UTX0(21)
MXM_MBDP_AUX
MXM_MBDP_AUX#
MXM_MBDP_TX0#(23)
MXM_MBDP_TX0(23)
MXM_MBDP_TX1#(23)
MXM_MBDP_TX1(23)
MXM_MBDP_TX2#(23)
MXM_MBDP_TX2(23)
MXM_MBDP_TX3#(23)
MXM_MBDP_TX3(23)
MXM_MBDP_AUX#
MXM_MBDP_AUX
+5V_ALW
R1067
R1067
100K
100K
+/-5%
+/-5%
VCC
2
A
3
9.
D71
D71
SDM10K45-7-F
SDM10K45-7-F
CA
DPA and DPC output on MXM3.0 is must
DPB and DPD output is optional.
D
G
RUN_GFX_ON(40)
+3.3V_RUN_MXM +3.3V_RUN_MXM
SDM10K45-7-F
SDM10K45-7-F
D67
D67
C A
R393
R393
G
100K
100K
+/-5%
+/-5%
RUN_GFX_ON
Thermal T rip
Q14
Q14
DS
DGPU_THERMTRIP# (46) DGPU_ALERT# (40)
2N7002W-7-F
2N7002W-7-F
S
Q122
Q122
2N7002W-7-F
2N7002W-7-F
GPU internal PU.
R401 *0_NC +/-5%R401 *0_NC +/-5%
DS
MXM_SMBCLK (39)
Q17
Q17
2N7002W-7-F
2N7002W-7-F
G
Q18
Q18
G
+3.3V_RUN_MXM
3
2N7002W-7-F
2N7002W-7-F
R404 *0_NC +/-5%R404 *0_NC +/-5%
DS
MXM_SMBDAT (39)
G
C A
2
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203
205
207
209
211
213
215
217
219
221
223
225
227
229
231
233
235
237
239
241
243
245
247
249
251
253
255
257
259
261
263
265
267
269
271
273
275
277
279
281
+15V_ALW
SDM10K45-7-F
SDM10K45-7-F
D68
D68
R394
R394
100K
100K
+/-5%
+/-5%
2
JMXM1BJMXM1B
GND_157
RSVD_159
RSVD_161
RSVD_163
RSVD_165
RSVD_167
LVDS_UCLK#_169
LVDS_UCLK_171
GND_173
LVDS_UTX3#_175
LVDS_UTX3_177
GND_179
LVDS_UTX2#_181
LVDS_UTX2_183
GND_185
LVDS_UTX1#_187
LVDS_UTX1_189
GND_191
LVDS_UTX0#_193
LVDS_UTX0_195
GND_197
DP_C_L0#_199
DP_C_L0_201
GND_203
DP_C_L1#_205
DP_C_L1_207
GND_209
DP_C_L2#_211
DP_C_L2_213
GND_215
DP_C_L3#_217
DP_C_L3_219
GND_221
DP_C_AUX#_223
DP_C_AUX_225
RSVD_227
RSVD_229
RSVD_231
RSVD_233
RSVD_235
RSVD_237
RSVD_239
RSVD_241
RSVD_243
RSVD_245
RSVD_247
RSVD_249
GND_251
DP_A_L0#_253
DP_A_L0_255
GND_257
DP_A_L1#_259
DP_A_L1_261
GND_263
DP_A_L2#_265
DP_A_L2_267
GND_269
DP_A_L3#_271
DP_A_L3_273
GND_275
DP_A_AUX#_277
DP_A_AUX_279
PRSNT_L#_281
R1063
R1063
100K
100K
+/-5%
+/-5%
D
Q111
Q111
2N7002W-7-F
2N7002W-7-F
S
1
158
VGA_DDC_DAT_158
VGA_DDC_CLK_160
VGA_VSYNC_162
VGA_HSYNC_164
GND_166
VGA_RED_168
VGA_GREEN_170
VGA_BLUE_172
GND_174
LVDS_LCLK#_176
LVDS_LCLK_178
GND_180
LVDS_LTX3#_182
LVDS_LTX3_184
GND_186
LVDS_LTX2#_188
LVDS_LTX2_190
GND_192
LVDS_LTX1#_194
LVDS_LTX1_196
GND_198
LVDS_LTX0#_200
LVDS_LTX0_202
GND_204
DP_D_L0#_206
DP_D_L0_208
GND_210
DP_D_L1#_212
DP_D_L1_214
GND_216
DP_D_L2#_218
DP_D_L2_220
GND_222
DP_D_L3#_224
DP_D_L3_226
GND_228
DP_D_AUX#_230
DP_D_AUX_232
DP_C_HPD_234
DP_D_HPD_236
RSVD_238
RSVD_240
RSVD_242
GND_244
DP_B_L0#_246
DP_B_L0_248
GND_250
DP_B_L1#_252
DP_B_L1_254
GND_256
DP_B_L2#_258
DP_B_L2_260
GND_262
DP_B_L3#_264
DP_B_L3_266
GND_268
DP_B_AUX#_270
DP_B_AUX_272
DP_B_HPD_274
DP_A_HPD_276
3V3_278
3V3_280
ME1
ME2
+5V_ALW
Q109
Q109
FDC655BN
FDC655BN
6
524
1
3
C981
C981
4.7nF
4.7nF
50V,X7R
50V,X7R
Thermal Aler t
G
Q16
Q16
DS
2N7002W-7-F
2N7002W-7-F
MXM_G_DAT_DDC2 (24)
160
MXM_G_CLK_DDC2 (24)
162
MXM_VGA_VSYNC (24)
164
MXM_VGA_HSYNC (24)
166
168
MXM_VGA_RED (24)
170
MXM_VGA_GRN (24)
172
MXM_VGA_BLU (24)
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
206
208
210
212
214
216
218
220
222
224
226
228
230
232
234
236
238
240
242
244
246
248
250
252
254
256
258
260
262
264
266
268
270
272
274
276
278
280
ME1
ME2
MXM_LVDS_LCLK# ( 21)
MXM_LVDS_LCLK (2 1)
MXM_LVDS_LTX3# (21)
MXM_LVDS_LTX3 (21)
MXM_LVDS_LTX2# (21)
MXM_LVDS_LTX2 (21)
MXM_LVDS_LTX1# (21)
MXM_LVDS_LTX1 (21)
MXM_LVDS_LTX0# (21)
MXM_LVDS_LTX0 (21)
EDP_MXM_TX0# (20)
EDP_MXM_TX0 (20)
EDP_MXM_TX1# (20)
EDP_MXM_TX1 (20)
EDP_MXM_TX2# (20)
EDP_MXM_TX2 (20)
EDP_MXM_TX3# (20)
EDP_MXM_TX3 (20)
MXM_DPC_HPD_GATE
EDP_MXM_HPD (20)
DOCK_DP2_HPD_GATE
MXM_MBDP_HPD_GATE
C328
C328
C329
C329
0.1uF
0.1uF
4.7uF
4.7uF
16V,X7R
16V,X7R
10V,X5R
10V,X5R
+3.3V_ALW+5V_RUN_MXM +3.3V_RUN_MXM
Q110
Q110
FDC655BN
FDC655BN
6
524
1
C979
C979
0.1uF
0.1uF
16V,X7R
16V,X7R
3
C982
C982
4.7nF
4.7nF
50V,X7R
50V,X7R
EMC1700_SENSE_N(38)
EMC1700_SENSE_P(38)
+PWR_SRC
SI4835DDY-T1-E3
SI4835DDY-T1-E3
3
1
C330
C330
R395
R395
0.1uF
0.1uF
100K
100K
25V,X7R
25V,X7R
+/-5%
+/-5%
R397
R397
100K
100K
+/-5%
+/-5%
D
Q15
Q15
G
RUN_GFX_ON
2N7002W-7-F
2N7002W-7-F
S
Ever Light
Ever Light
Ever Light
Technology Limited
Technology Limited
Technology Limited
Title
Title
Title
19 -- MXM3.0 Connector
19 -- MXM3.0 Connector
19 -- MXM3.0 Connector
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
eDP Panel
EDP_MXM_AUX# (20)
EDP_MXM_AUX (20)
1 A
C980
C980
0.1uF
0.1uF
16V,X7R
16V,X7R
Q13
Q13
4
1
DOCK_DP2_TX0# (27)
DOCK_DP2_TX0 (27)
DOCK_DP2_TX1# (27)
DOCK_DP2_TX1 (27)
DOCK_DP2_TX2# (27)
DOCK_DP2_TX2 (27)
DOCK_DP2_TX3# (27)
DOCK_DP2_TX3 (27)
DOCK_DP2_AUX# (27)
DOCK_DP2_AUX (27)
+3.3V_RUN_MXM
1 2
782
6
5
5m
PR295mPR29
From 5048
DOCK DP2
+PWR_SRC_MXM
3
4
R396
R396
20K
20K
+/-5%
+/-5%
19 84Thursday, January 27, 2011
19 84Thursday, January 27, 2011
19 84Thursday, January 27, 2011
1A
1A
1A
5
WWW.MANUALS.CLAN.SU
D D
4
3
2
1
eDP_TX3N_R
eDP_TX3P_R
eDP_TX2N_R
eDP_TX2P_R
eDP_TX1N_R
eDP_TX1P_R
eDP_TX0N_R
eDP_TX0P_R
eDP_AUXP_R
eDP_AUXN_R
LCD_GND
4 Lane eDP
0507GC: update CIS part
SMDFIX8
SMDFIX8
G2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
BL_GND
35
36
37
38
39
40
41
42
43
44
G1
SMDFIX9
SMDFIX9
JEDP1
JEDP1
SMDFIX2
SMDFIX2
G3
SMDFIX3 SMDFIX4
SMDFIX3 SMDFIX4
G4
G5
SMDFIX5
SMDFIX5
G6
SMDFIX6
SMDFIX6
G7
Header_1X44
Header_1X44
eDP_AUXP_R
R1086100K+/-5% R1086100K+/-5%
eDP_AUXN_R
+3.3V_RUN
R1085100K+/-5% R1085100K+/-5%
21.
EDP_DET#(40)
+3.3V_RUN
EDP_MXM_HPD
LCD_SMBCLK
LCD_SMBDAT
C368 0.1uF 16V,X7RC368 0. 1uF 16V,X7R
C364 0.1uF 16V,X7RC364 0. 1uF 16V,X7R
C365 0.1uF 16V,X7RC365 0. 1uF 16V,X7R
C369 0.1uF 16V,X7RC369 0. 1uF 16V,X7R
C366 0.1uF 16V,X7RC366 0. 1uF 16V,X7R
C367 0.1uF 16V,X7RC367 0. 1uF 16V,X7R
C370 0.1uF 16V,X7RC370 0. 1uF 16V,X7R
C371 0.1uF 16V,X7RC371 0. 1uF 16V,X7R
C372 0.1uF 16V,X7RC372 0. 1uF 16V,X7R
C373 0.1uF 16V,X7RC373 0. 1uF 16V,X7R
R811 0 +/-5%R811 0 +/-5 %
EDP_MXM_TX3#(19)
EDP_MXM_TX3(1 9)
EDP_MXM_TX2#(19)
EDP_MXM_TX2(1 9)
C C
+EDPVCC+5V_RUN
Q128
Q128
FDC655BN
FDC655BN
6
524
1
+3.3V_ALW
R681 2.2K +/-5%R681 2.2 K +/-5%
R682 2.2K +/-5%R682 2.2 K +/-5%
3
LCDVCC_ON(22)
B B
2.4A
C992
C992
0.1uF
0.1uF
16V,X7R
16V,X7R
LCD_SMBDAT
LCD_SMBCLK
Pin 44 +3.3V_RUN is for 10 bit DB only.
EDP_MXM_TX1#(19)
EDP_MXM_TX1(1 9)
EDP_MXM_TX0#(19)
EDP_MXM_TX0(1 9)
EDP_MXM_AUX(19)
EDP_MXM_AUX#(19)
+EDPVCC
LCD_TST(22,40)
EDP_MXM_HPD(19)
DISP_ON(22)
LCD_PWM_VADJ(22)
LCD_SMBCLK(38,39)
LCD_SMBDAT(38,39)
+BL_PWR_SRC
For 3D Panel is NC.
+3.3V_RUN
1
2
D47
D47
DA204UT106
DA204UT106
3
EDP_MXM_HPD
Placement sequence.
A A
Connecter -> R811 -> D47 -> R1087 -> MXM
EDP_MXM_HPD
R1087
R1087
100K
100K
+/-5%
+/-5%
Ever Light
Ever Light
Ever Light
Technology Limited
Technology Limited
Technology Limited
Title
Title
Title
20 -- 17" eDP for PANE L
20 -- 17" eDP for PANE L
20 -- 17" eDP for PANE L
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Thunder 1A
Thunder 1A
Thunder 1A
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet
1
of
20 84Thursday , Ja nuary 27, 2 011
20 84Thursday , Ja nuary 27, 2 011
20 84Thursday , Ja nuary 27, 2 011
5
WWW.MANUALS.CLAN.SU
D D
C C
4
3
2
1
LVDS MUX for Panel
U10
U10
R735
R735
*10K_NC
*10K_NC
+/-5%
+/-5%
39
0B1
38
1B1
35
2B1
34
3B1
30
4B1
29
5B1
26
6B1
25
7B1
16
8B1
18
9B1
37
0B2
36
1B2
33
2B2
32
3B2
28
4B2
27
5B2
24
6B2
23
7B2
20
8B2
21
9B2
12
SEL
TS3DV520ERUAR
TS3DV520ERUAR
VIA144VIA245VIA346VIA447VIA548VIA1053VIA952VIA851VIA750VIA6
49
SEL = L , Port B1 active.
SEL = H , Port B2 active.
MXM_LVDS_LTX0(19)
MXM_LVDS_LTX0#(19)
MXM_LVDS_LTX1(19)
MXM_LVDS_LTX1#(19)
from MXM
B B
from PCH
MXM_LVDS_LTX2(19)
MXM_LVDS_LTX2#(19)
MXM_LVDS_LTX3(19)
MXM_LVDS_LTX3#(19)
MXM_LVDS_LCLK(19)
MXM_LVDS_LCLK#(19)
LCD_A0+_PCH(7)
LCD_A0-_PCH(7)
LCD_A1+_PCH(7)
LCD_A1-_PCH(7)
LCD_A2+_PCH(7)
LCD_A2-_PCH(7)
LCD_A3+_PCH(7)
LCD_A3-_PCH(7)
LCD_ACLK+_PCH(7)
LCD_ACLK-_PCH(7)
DGPU_SELECT#(22,24,40)
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
NC1
NC2
NC3
NC4
thermal pad
TS3DV520ERUAR
TS3DV520ERUAR
+3.3V_RUN
1
4
7
13
22
31
40
2
3
5
6
8
9
10
11
14
15
17
19
41
42
43
C374
C374
0.1uF
0.1uF
16V,Y5V
16V,Y5V
LCD_A0+ (22)
LCD_A0- (22)
LCD_A1+ (22)
LCD_A1- (22)
LCD_A2+ (22)
LCD_A2- (22)
LCD_A3+ (22)
LCD_A3- (22)
LCD_ACLK+ (22)
LCD_ACLK- (22)
C375
C375
0.1uF
0.1uF
16V,Y5V
16V,Y5V
to Panel
from MXM
from PCH
U11
U11
MXM_LVDS_UTX0(19)
MXM_LVDS_UTX0#(19)
MXM_LVDS_UTX1(19)
MXM_LVDS_UTX1#(19)
MXM_LVDS_UTX2(19)
MXM_LVDS_UTX2#(19)
MXM_LVDS_UTX3(19)
MXM_LVDS_UTX3#(19)
MXM_LVDS_UCLK(19)
MXM_LVDS_UCLK#(19)
LCD_B0+_PCH(7)
LCD_B0-_PCH(7)
LCD_B1+_PCH(7)
LCD_B1-_PCH(7)
LCD_B2+_PCH(7)
LCD_B2-_PCH(7)
LCD_B3+_PCH(7)
LCD_B3-_PCH(7)
LCD_BCLK+_PCH(7)
LCD_BCLK-_PCH(7)
DGPU_SELECT#(22,24,40)
39
0B1
38
1B1
35
2B1
34
3B1
30
4B1
29
5B1
26
6B1
25
7B1
16
8B1
TS3DV520ERUAR
TS3DV520ERUAR
18
9B1
37
0B2
36
1B2
33
2B2
32
3B2
28
4B2
27
5B2
24
6B2
23
7B2
20
8B2
21
9B2
12
SEL
VIA144VIA245VIA346VIA447VIA548VIA1053VIA952VIA851VIA750VIA6
SEL = L , Port B1 active.
SEL = H , Port B2 active.
49
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
NC1
NC2
NC3
NC4
thermal pad
TS3DV520ERUAR
TS3DV520ERUAR
1
4
7
13
22
31
40
2
3
5
6
8
9
10
11
14
15
17
19
41
42
43
+3.3V_RUN
C378
C378
0.1uF
0.1uF
16V,Y5V
16V,Y5V
LCD_B0+ (22)
LCD_B0- (22)
LCD_B1+ (22)
LCD_B1- (22)
LCD_B2+ (22)
LCD_B2- (22)
LCD_B3+ (22)
LCD_B3- (22)
LCD_BCLK+ (22)
LCD_BCLK- (22)
C379
C379
0.1uF
0.1uF
16V,Y5V
16V,Y5V
to Panel
A A
Ever Light
Ever Light
Ever Light
Technology Limited
Technology Limited
Technology Limited
Title
Title
Title
21 -- LVDS MUX fo r PANEL
21 -- LVDS MUX fo r PANEL
21 -- LVDS MUX fo r PANEL
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Thunder 1A
Thunder 1A
Thunder 1A
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet
1
of
21 84Thursday , Ja nuary 27, 2 011
21 84Thursday , Ja nuary 27, 2 011
21 84Thursday , Ja nuary 27, 2 011
5
WWW.MANUALS.CLAN.SU
+PWR_SRC +BL_PWR_SRC
40mil
D D
EN_INVPWR(39)
TOUCH_SCREEN_PD#(3 9)
USBP13-(9)
USBP13+(9 )
DMIC_CLK(6 0)
DMIC_DATA(60)
R418 10K +/-5%R418 10K +/-5%
D58 *SDM10K45-7-F_NCD58 *SDM10K45-7-F_NC
D59 *SDM10K45-7-F_NCD59 *SDM10K45-7-F_NC
D72
D72
SDM10K45-7-F
SDM10K45-7-F
C A
5
BIA_PWM_EC(39)
BIA_PWM_PCH(7)
MXM_LCD_BL_PWM(19)
C C
B B
Touch Screen
DMIC
CCD
A A
R410
R410
330K
330K
+/-5%
+/-5%
G
CA
CA
4
C382
C382
0.1uF
0.1uF
25V,X7R
25V,X7R
R411
R411
330K
330K
+/-5%
+/-5%
D
Q21
Q21
2N7002W-7-F
2N7002W-7-F
S
LCD_PWM_VADJ
R415
R415
*100K_NC
*100K_NC
+/-5%
+/-5%
R421 0 +/-5%R4 21 0 +/-5%
R423 0 +/-5%R4 23 0 +/-5%
L8
L8
1 2
*90 ohm,150mA_NC
*90 ohm,150mA_NC
+3.3V_SUS
R1835
R1835
100K
100K
+/-5%
+/-5%
R414 0R414 0
R416 0R416 0
DMIC_DATA_R DMIC_CLK_R
Q19
Q19
FDC658AP
FDC658AP
40mil
6
5
2
1
3
34
For Nvidia 3D IR: USB13 and +5V_RUN.
For Touc h screen : USB 13,+3. 3V_SUS and T OUCH_SC REEN_P D#
USB_TOUCH_D+
USB_TOUCH_D-
DMIC_CLK_R
DMIC_DATA_R
USB_CAMERA_D+
USB_CAMERA_D-
C388
C388
33pF
33pF
50V,NPO
50V,NPO
C383
C383
0.1uF
0.1uF
25V,X7R
25V,X7R
LCD_PWM_VADJ (20)
USB_TOUCH_D-
USB_TOUCH_D+
1
3
5
7
9
11
13
15
17
19
C389
C389
33pF
33pF
50V,NPO
50V,NPO
C384
C384
0.1uF
0.1uF
25V,X7R
25V,X7R
JDMIC1
JDMIC1
Header_2X10
Header_2X10
4
R407 *0_NC +/-5%R4 07 *0_NC +/-5%
R408 *0_NC +/-5%R4 08 *0_NC +/-5%
L7
USBP12-(9)
USBP12+(9)
1 2
90 ohm,150mAL790 ohm,150mA
N12x has internal PU. Can be removed after SSI.
PANEL_BKEN_EC(40)
PANEL_BKEN_PCH(7)
PANEL_BKEN_DGPU(19)
G1
2
+3.3V_SUS
4
6
+5V_RUN
8
10
12
14
16
CAM_MIC_CBL_DET# (9)
18
+CAM_VCC
20
G2
4
MXM_LCDVCC_EN(19)
ENVDD_PCH(7,40)
LCD_VCC_TEST_EN(40)
3
34
MXM_LCD_DDC_CLK
MXM_LCD_DDC_DATA
MXM_LCD_DDC_CLK(19)
MXM_LCD_DDC_DATA(19)
LDDC_CLK_PCH(7)
LDDC_DATA_PCH(7)
PU at PCH side
R786 10K +/-5%R786 10K +/-5%
D62 SDM10K45-7-FD62 SDM10K45-7-F
CA
D60 SDM10K45-7-FD60 SDM10K45-7-F
CA
Enable to EDP connector.
D6 SDM10K45-7-FD6 SDM10K45-7-F
CA
D7
1
3
EN_LCDVCC
2
BAT54CD7BAT54C
3
USB_CAMERA_D-
USB_CAMERA_D+
1.
R422 *2.2K_NC+/-5%R422 *2.2K_NC+/-5%
R424 *2.2K_NC+/-5%R424 *2.2K_NC+/-5%
MXM_LCD_DDC_CLK
MXM_LCD_DDC_DATA
R417
R417
100K
100K
+/-5%
+/-5%
LCDVCC_ON(20)
R1100
R1100
100K
100K
+/-5%
+/-5%
DISP_ON
+15V_ALW
G
D
S
R434
R434
200K
200K
+/-5%
+/-5%
Q31
Q31
2N7002W-7-F
2N7002W-7-F
+3.3V_RUN_MXM
DISP_ON (20)
+15V_ALW
34
R431
R431
200K
200K
+/-5%
+/-5%
LCDVCC_ON
5
Q30A
Q30A
2N7002DW-7-F
2N7002DW-7-F
U75
U75
9
7
2
4
3
C390
C390
0.1uF
0.1uF
CCD_OFF(40)
NC1
NC2
NO1
NO2
GND
TS5A23157RSER
TS5A23157RSER
+3.3V_ALW
V+
COM1
COM2
IN1
IN2
Q29
Q29
FDC655BN
FDC655BN
6
524
1
3
+15V_ALW
G
+3.3V_RUN
8
10
LDDC_CLK
6
LDDC_DATA
1
5
SEL = L , NC to COM.
SEL = H , NO to COM.
C392
C392
0.1uF
0.1uF
25V,Y5V
25V,Y5V
R433
R433
100
100
+/-5%
+/-5%
61
2
Q30B
Q30B
2N7002DW-7-F
2N7002DW-7-F
Discharge Path
2
R412
R412
*100K_NC
*100K_NC
+/-5%
+/-5%
CCD_OFF#
D
Q22
Q22
*2N7002W-7-F_NC
*2N7002W-7-F_NC
S
C989
C989
0.1uF
0.1uF
16V,X7R
16V,X7R
DGPU_SELECT# (21,24,40 )
2
+LCDVCC
C391
C391
0.1uF
0.1uF
16V,X7R
16V,X7R
+3.3V_RUN
R409 0 +/-5%
R409 0 +/-5%
r0603h6
r0603h6
Q20
Q20
*FDC655BN_NC
*FDC655BN_NC
30V,9.0A,30m@4.5V
6
524
1
3
C387
C387
*0.1uF_NC
*0.1uF_NC
25V,X7R
25V,X7R
+3.3V_RUN
+BL_PWR_SRC
LCD_TST(20,40)
+LCDVCC
+3.3V_RUN
LCD_A0+(21)
LCD_A0-(21)
LCD_A1+(21)
LCD_A1-(21)
LCD_A2+(21)
LCD_A2-(21)
LCD_A3+(21)
LCD_A3-(21)
LCD_ACLK+(21)
LCD_ACLK-(21)
LCD_B0+(21)
LCD_B0-(2 1)
LCD_B1+(21)
LCD_B1-(2 1)
LCD_B2+(21)
LCD_B2-(2 1)
LCD_B3+(21)
LCD_B3-(2 1)
LCD_BCLK+(21)
LCD_BCLK-(21)
1
+CAM_VCC
Current: 220m A(max)
C385
C385
C386
C386
*10uF_NC
*10uF_NC
0.1uF
0.1uF
10V,X5R
10V,X5R
16V,X7R
16V,X7R
R783 2.2K +/-5%R783 2.2 K +/-5%
R784 2.2K +/-5%R784 2.2 K +/-5%
LDDC_CLK
LDDC_DATA
LVDS
0817GC: Need to update CIS.
cable loopback
DISP_ON
LCD_PWM_VADJ
LDDC_CLK
LDDC_DATA
Title
Title
Title
22 -- LCD,Camera,Touch Conn
22 -- LCD,Camera,Touch Conn
22 -- LCD,Camera,Touch Conn
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Thunder 1A
Thunder 1A
Thunder 1A
Date: Sheet of
Date: Sheet of
Date: Sheet
JLVDS1
JLVDS1
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
63
16
GND5
17
62
17
GND4
18
61
18
GND3
19
60
19
GND2
20
59
20
GND1
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
29
29
30
30
31
31
32
32
33
33
34
34
35
35
36
36
37
37
38
38
39
39
40
40
41
41
42
42
43
43
44
44
45
45
46
46
47
47
48
48
49
49
50
50
51
51
52
52
53
53
54
54
55
55
56
56
57
57
58
58
TBD-CONN-WTB
TBD-CONN-WTB
Ever Light
Ever Light
Ever Light
Technology Limited
Technology Limited
Technology Limited
22 84Thursday , Ja nuary 27, 2 011
22 84Thursday , Ja nuary 27, 2 011
22 84Thursday , Ja nuary 27, 2 011
1
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4
3
2
1
DP_CA_DET#
DP_TX1+_R
DP_TX1-_R
DP_TX3+_R
DP_TX3-_R
DP_TX0+_R
DP_TX0-_R
DP_TX2+_R
DP_TX2-_R
DP_AUX+_R
DP_AUX-_R
FOR Dongle
U22
U22
8
VCC
3
1A21B
6
2A52B
1
1OE
7
4
2OE
GND
SN74CBTD3306CPWR
SN74CBTD3306CPWR
+5V_RUN
R477
R477
10K
10K
+/-5%
+/-5%
D
Q33
Q33
2N7002W-7-F
2N7002W-7-F
G
S
+3.3V_RUN
1
2
D48
D48
DA204UT106
DA204UT106
3
MXM_MBDP_HPD
U14
U14
1
IN1
2
IN2
3
GND_1
4
IN3
5
IN4
*RCLAMP0524P.TCT_NC
*RCLAMP0524P.TCT_NC
U15
U15
1
IN1
2
IN2
3
GND_1
4
IN3
5
IN4
*RCLAMP0524P.TCT_NC
*RCLAMP0524P.TCT_NC
U16
U16
1
IN1
2
IN2
3
GND_1
4
IN3
5
IN4
*RCLAMP0524P.TCT_NC
*RCLAMP0524P.TCT_NC
+5V_RUN
DP_CA_DET
GND_2
GND_2
GND_2
C462
C462
0.1uF
0.1uF
50V,X7R
50V,X7R
DP_AUX+
DP_AUX-
0524GC: CIS OK
JDP1
JDP1
C413
C413
4.7uF
4.7uF
6.3V,X5R
6.3V,X5R
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
LANE0+
LANE0_SHIELD
LANE0LANE1+
LANE1_SHIELD
LANE1LANE2+
LANE2_SHIELD
LANE2LANE3+
LANE3_SHIELD
LANE3CA_DET
GND1
AUX_CH+
GND2
AUX_CHHP_DET
RTN
DP_PWR
GND6
GND5
GND4
GND3
CONN-Display Port
CONN-Display Port
24
23
22
21
MXM_MBDP_HPD(1 9,40)
+3.3V_RUN
D8
D8
*RB751V-40 TE-17_NC
*RB751V-40 TE-17_NC
Polyswitch,PTC,6V,1.1A,G,SMD1206
Polyswitch,PTC,6V,1.1A,G,SMD1206
R1088 1M +/-5%R1088 1M +/-5%
F1
F1
*
*
Polyswitch
Polyswitch
CA
DP_TX0+_R
DP_TX0-_R
DP_TX1+_R
DP_TX1-_R
DP_TX2+_R
DP_TX2-_R
DP_TX3+_R
DP_TX3-_R
DP_CA_DET
DP_AUX+_R
DP_AUX-_R
MXM_MBDP_HPD
Put close to connecter.
10
DP_TX1+_R
O1
9
DP_TX1-_R
O2
8
7
DP_TX3+_R
O3
6
DP_TX3-_R
O4
10
DP_TX0+_R
O1
9
DP_TX0-_R
O2
8
7
DP_TX2+_R
O3
6
DP_TX2-_R
O4
10
DP_AUX+_R
O1
9
DP_AUX-_R
O2
8
7
DP_CA_DETDP_CA_DET
O3
6
O4
2
DP_AUX-
R438 100K +/-5%R438 100K +/-5%
DP_AUX+
R437 100K +/-5%R437 100K +/-5%
DP_CA_DET
R443 1M +/-5%R443 1 M +/-5%
MXM_MBDP_HPD
R439 100K +/-5%R439 100K +/-5%
13.
Ever Light
Ever Light
Ever Light
Technology Limited
Technology Limited
Technology Limited
Title
Title
Title
22 -- Display Port & Re-Driver
22 -- Display Port & Re-Driver
22 -- Display Port & Re-Driver
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
+3.3V_RUN
23 84Thursday , Ja nuary 27, 2 011
23 84Thursday , Ja nuary 27, 2 011
23 84Thursday , Ja nuary 27, 2 011
of
of
1
of
D D
MXM_MBDP_AUX
MXM_MBDP_AUX#
DP_CA_DET#
C C
Display Port
R444 0 +/-5%R444 0 +/-5 %
R445 0 +/-5%R445 0 +/-5 %
L9
L9
1
MXM_MBDP_TX0
C410 0.1uF
MXM_MBDP_TX0(19)
B B
A A
5
MXM_MBDP_TX0#(19)
MXM_MBDP_TX1(19)
MXM_MBDP_TX1#(19)
MXM_MBDP_TX2(19)
MXM_MBDP_TX2#(19)
MXM_MBDP_TX3(19)
MXM_MBDP_TX3#(19)
MXM_MBDP_AUX(19)
MXM_MBDP_AUX#(19)
C410 0.1uF
C409 0.1uF
C409 0.1uF
MXM_MBDP_TX1 DP_TX1+_L DP_TX1+_R
C411 0.1uF
C411 0.1uF
C412 0.1uF
C412 0.1uF
MXM_MBDP_TX2 DP_TX2+_L DP_TX2+_R
C414 0.1uF
C414 0.1uF
C415 0.1uF
C415 0.1uF
MXM_MBDP_TX3 DP_TX3+_L DP_TX3+_R
C416 0.1uF
C416 0.1uF
C417 0.1uF
C417 0.1uF
MXM_MBDP_AUX
C430 0.1uF
C430 0.1uF
MXM_MBDP_AUX#
C429 0.1uF
C429 0.1uF
DP_TX0+_L DP_TX0+_R
16V,X7R
16V,X7R
16V,X7R
16V,X7R
16V,X7R
16V,X7R
16V,X7R
16V,X7R
16V,X7R
16V,X7R
16V,X7R
16V,X7R
16V,X7R
16V,X7R
16V,X7R
16V,X7R
DP_AUX+
16V,X7R
16V,X7R
DP_AUX-
16V,X7R
16V,X7R
4
2 3
*90 Ohm,100mA_NC
*90 Ohm,100mA_NC
EXC24CG900U
EXC24CG900U
R446 0 +/-5%R446 0 +/-5 %
R447 0 +/-5%R447 0 +/-5 %
L10
L10
1
2 3
*90 Ohm,100mA_NC
*90 Ohm,100mA_NC
EXC24CG900U
EXC24CG900U
R448 0 +/-5%R448 0 +/-5 %
R449 0 +/-5%R449 0 +/-5 %
L11
L11
1
2 3
*90 Ohm,100mA_NC
*90 Ohm,100mA_NC
EXC24CG900U
EXC24CG900U
R450 0 +/-5%R450 0 +/-5 %
R451 0 +/-5%R451 0 +/-5 %
L12
L12
1
2 3
*90 Ohm,100mA_NC
*90 Ohm,100mA_NC
EXC24CG900U
EXC24CG900U
R452 0 +/-5%R452 0 +/-5 %
R453 0 +/-5%R453 0 +/-5 %
L13
L13
1
2 3
*90 Ohm,100mA_NC
*90 Ohm,100mA_NC
EXC24CG900U
EXC24CG900U
4
DP_TX0-_RDP_TX0-_LMXM_MBDP_TX0#
4
DP_TX1-_RDP_TX1-_LMXM_MBDP_TX1#
4
DP_TX2-_RDP_TX2-_LMXM_MBDP_TX2#
4
DP_TX3-_RDP_TX3-_LMXM_MBDP_TX3#
4
DP_AUX+_R
DP_AUX-_R
3
1A
1A
1A
5
WWW.MANUALS.CLAN.SU
CRT
RED_CRT
D D
BLUE_CRT
R457
R455
R455
150
150
+/ -1%
+/ -1%
R457
R456
R456
150
150
+/ -1%
+/ -1%
150
150
+/ -1%
+/ -1%
FAE suggest
C419
C419
*3.3pF_NC
*3.3pF_NC
50V,NPO
50V,NPO
C420
C420
*3.3pF_NC
*3.3pF_NC
50V,NPO
50V,NPO
4
Layout Note:
Setting R,G,B treac
impedance to 50 ohm.
FB5 0 +/-5 % r0603h6FB5 0 +/-5% r0603h6
FB3 0 +/-5 % r0603h6FB3 0 +/-5% r0603h6
FB6 0 +/-5 % r0603h6FB6 0 +/-5% r0603h6
C421
C421
*3.3pF_NC
*3.3pF_NC
50V,NPO
50V,NPO
C422
C422
4.7pF
4.7pF
50V,NPO
50V,NPO
RED_CRT_L
GREEN_CRT_L GGREEN_CRT
BLUE_CRT_L
C423
C423
4.7pF
4.7pF
50V,NPO
50V,NPO
3
1
2.
FB2 FB 22 Ohm, 400mA
FB2 FB 22 Ohm, 400mA
BK1005LL220-T
BK1005LL220-T
FB4 FB 22 Ohm, 400mA
FB4 FB 22 Ohm, 400mA
BK1005LL220-T
BK1005LL220-T
FB7 FB 22 Ohm, 400mA
FB7 FB 22 Ohm, 400mA
BK1005LL220-T
BK1005LL220-T
C424
C424
4.7pF
4.7pF
50V,NPO
50V,NPO
2
D9
D9
*DA204UT106_NC
*DA204UT106_NC
3
C425
C425
4.7pF
4.7pF
50V,NPO
50V,NPO
1
D10
D10
*DA204UT106_NC
*DA204UT106_NC
3
C426
C426
4.7pF
4.7pF
50V,NPO
50V,NPO
+3.3V_RUN +5V_RUN
2
1
3
DAT_DDC2_CRT
CLK_DDC2_CRT
2
2
CA
+5V_RUN_CRT
D12
D12
D11
D11
SDM10K45-7-F
SDM10K45-7-F
*DA204UT106_NC
*DA204UT106_NC
R
B JVGA_HS
C427
C427
4.7pF
4.7pF
50V,NPO
50V,NPO
+5V_RUN
R461
R461
*1K_NC
*1K_NC
+/-5%
+/-5%
R454 0 +/-5%
R454 0 +/-5%
r1206h7
r1206h7
*
*
F2 *Fuse 5A_NC
F2 *Fuse 5A_NC
R462
R462
*1K_NC
*1K_NC
+/-5%
+/-5%
+CRT_VCC
+CRT_VCC
M_ID2#
C428
C428
0.1uF
0.1uF
16V,Y5V
16V,Y5V
C418
C418
1uF
1uF
6.3V,X5R
6.3V,X5R
JCRT1
JCRT1
6
1 11
7
2
8
3
9
4
10
5
17
12
13
14
15
CONN - D-SUB
CONN - D-SUB
16
1
JVGA_VS
HSYNC_CRT
C C
+3.3V_RUN
C954
C954
1uF
1uF
6.3V,X5R
6.3V,X5R
MXM_VGA_RED(19)
+3.3V_RUN
CRT_SWITCH
CRT_SWITCH
MXM_VGA_GRN(1 9)
MXM_VGA_BLU(19)
MXM_VGA_HSYNC(19)
MXM_VGA_VSYNC(19)
MXM_G_DAT_DDC2(19)
MXM_G_CLK_DDC2(19)
PCH_CRT_RED(7)
PCH_CRT_GRN(7)
PCH_CRT_BLU(7)
PCH_CRT_HSYNC(7)
PCH_CRT_VSYNC(7)
PCH_CRT_DDC_DAT(7)
PCH_CRT_DDC_CLK(7)
R588 100K +/-5%R588 100K +/-5%
B B
Channel A---->MXM
Channel B---->PCH
EDID_SELECT#(40)
CRT_SWITCH(40)
DGPU_SELECT#(21,22, 40)
U79
U79
11
VL
7
REDA
8
GRNA
9
BLUA
3
SHA
4
SVA
6
SDAA
5
SCLA
17
REDB
18
GRNB
19
BLUB
13
SHB
14
SVB
16
SDAB
15
SCLB
2
EN
1
S00
40
S01
39
S10
38
S11
MAXIM
MAXIM
MAX14885EETL+
MAX14885EETL+
VSYNC_CRT
VCC1
VCC2
RED1
GRN1
BLU1
SDA1
SCL1
RED2
GRN2
BLU2
SDA2
SCL2
GND1
GND2
GND3
thermal pad
MAX14885EETL+
MAX14885EETL+
SH1
SV1
SH2
SV2
N.C.
R463 0 +/-5%R463 0 +/-5%
R464 0 +/-5%R464 0 +/-5%
+5V_RUN
21
29
33
RED_CRT
32
GREEN_CRT
31
BLUE_CRT
37
HSYNC_CRT
36
VSYNC_CRT
34
DAT_DDC2_CRT
35
CLK_DDC2_CRT
24
23
22
28
27
25
26
12
10
20
30
41
HSYNC_L2
VSYNC_L2
C767
C767
1uF
1uF
10V,X5R
10V,X5R
RED_DOCK (27)
GREEN_DOCK (27 )
BLUE_DOCK (27)
HSYNC_DOCK (27)
VSYNC_DOCK (27)
DAT_DDC2_DOCK (27)
CLK_DDC2_DOCK (27)
1 2
FB8 FB 120 Ohm, 600mA
FB8 FB 120 Ohm, 600mA
+/-25%
+/-25%
1 2
FB9 FB 120 Ohm, 600mA
FB9 FB 120 Ohm, 600mA
+/-25%
+/-25%
C432
C432
*22pF_NC
*22pF_NC
50V,NPO
50V,NPO
Place near JVGA1 connector <
200 mil
Port 1---->MB CRT
Port 2---->Docking CRT
C433
C433
*22pF_NC
*22pF_NC
50V,NPO
50V,NPO
Truth table
B-->Port 1 A-->Port 2 B-->Port 2
A A
S10 (DGPU_SELECT#)
S00 (EDID_SELECT#)
S01/S11 (CRT_SWITCH)
5
4
A-->Port 1
0
0
0 1 1
1
0 110
3
10
Ever Light
Ever Light
Ever Light
Technology Limited
Technology Limited
Technology Limited
Title
Title
Title
23 -- CRT & MUX
23 -- CRT & MUX
23 -- CRT & MUX
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Thunder 1A
Thunder 1A
Thunder 1A
Date: Sheet of
Date: Sheet of
2
Date: Sheet
1
of
24 84Thursday , Ja nuary 27, 2 011
24 84Thursday , Ja nuary 27, 2 011
24 84Thursday , Ja nuary 27, 2 011
5
WWW.MANUALS.CLAN.SU
4
3
2
1
U85
U85
2
VDD1
8
VDD2
34
VDD3
48
VDD4
54
VDD5
3
ML_IN 0(p)
4
ML_IN 0(n)
6
ML_IN 1(p)
7
ML_IN 1(n)
9
ML_IN 2(p)
10
ML_IN 2(n)
12
ML_IN 3(p)
13
ML_IN 3(n)
19
TMDS_SINK 0(p)
18
TMDS_SINK 0(n)
22
TMDS_SINK 1(p)
21
TMDS_SINK 1(n)
25
TMDS_SINK 2(p)
24
TMDS_SINK 2(n)
16
TMDS_SINK CLK(p)
15
TMDS_SINK CLK(n)
37
HPD
40
DP_HPD_SINK
32
TMDS_HPD_SINK
5
GND1
11
GND2
20
GND3
27
GND4
42
GND5
44
GND6
51
GND7
MXM_DPC_CA_DET
TI 75DP122
AUX_SINK(p)
AUX_SINK(n)
AUX_I2C(SCL)
AUX_I2C(SDA)
VCC#17
SN75DP122ARTQT
SN75DP122ARTQT
DP_SINK 0(p)
DP_SINK 0(n)
DP_SINK 1(p)
DP_SINK 1(n)
DP_SINK 2(p)
DP_SINK 2(n)
DP_SINK 3(p)
DP_SINK 3(n)
AUX_I2C(SCL)
AUX_I2C(SDA)
AUX_SINK(p)
AUX_SINK(n)
I2C_SCL
I2C_SDA
CAD_SINK
THERM_PAD
VIA158VIA259VIA360VIA4
SN75DP122ARTQT
SN75DP122ARTQT
61
R1929 100K +/-5%R1929 10 0K +/-5 %
R1930 100K +/-5%R1930 10 0K +/-5 %
C1023 0.1uF 16 V,X7RC1 023 0.1uF 16 V,X7R
C1024 0.1uF 16 V,X7RC1 024 0.1uF 16 V,X7R
I2C_SCL
I2C_SDA
VDD*1
Priority
DPVadj
VSadj
I2C_EN
VCC
VCC
CAD
LP#
+3.3V_RUN
+5V_RUN
R1918
R1918
*0_NC
*0_NC
+/-5%
+/-5%
38
14
17
23
56
55
53
52
50
49
47
46
36
35
45
43
29
28
39
41
30
33
1
26
31
57
HDMI
(MB)
R1919
R1919
0
0
+/-5%
+/-5%
+3.3V_RUN
C1010
C1010
0.1uF
0.1uF
16V,X7R
16V,X7R
MXM_DPC_AUX_S
MXM_DPC_AUX#_S
MXM_DPC_CA_DET
R1923 10K +/-5%R1923 10K +/-5%
R1924 10K +/-5%R1924 10K +/-5%
R1925 3.83K +/-1%R1925 3 .83K +/- 1%
R1927 5.6K +/-1%R1927 5 .6K +/-1 %
R1928 10K +/-5%R1928 10K +/-5%
U87
U87
9
V+
NC1
7
NC2
COM1
2
NO1
COM2
4
NO2
IN1
3
GND
IN2
TS5A23157RSER
TS5A23157RSER
IN1/2 = L , NC to COM.
IN1/2 = H , NO to COM.
(L=HDMI; H=DP)
C1011
C1011
0.1uF
0.1uF
16V,X7R
16V,X7R
DOCK_DP1_TX0+ (27)
DOCK_DP1_TX0- (27)
DOCK_DP1_TX1+ (27)
DOCK_DP1_TX1- (27)
DOCK_DP1_TX2+ (27)
DOCK_DP1_TX2- (27)
DOCK_DP1_TX3+ (27)
DOCK_DP1_TX3- (27)
DOCK_DP1_AUX+
DOCK_DP1_AUX-
DOCK_DP1_CA_DET
+5V_RUN
8
10
6
1
5
3
Docking
MUX
C1012
C1012
0.1uF
0.1uF
16V,X7R
16V,X7R
To Docking DP1 Port
DOCK_DP1_AUX+ (27)
DOCK_DP1_AUX- (27)
HDMI_DD C_CL K (26)
HDMI_DD C_DAT (26)
DOCK_DP1_CA_DET (27)
+3.3V_RUN
+3.3V_RUN
C1022
C1022
0.1uF
0.1uF
16V,Y5V
16V,Y5V
+5V_RUN
R1931
R1931
10K
10K
+/-5%
+/-5%
D
Q133
Q133
2N7002W-7-F
2N7002W-7-F
G
S
DP
(Dock)
DVI
(Dock)
MXM_DPC_AUX_S
MXM_DPC_AUX#_S
MXM_DPC_CA_DET
MXM_DPC_CA_DET#
+5V_RUN
C1014
C1014
0.1uF
0.1uF
16V,Y5V
U86
+3.3V_RUN
G
MXM_DPC_CA_DET
R1926
R1926
1M
1M
+/-5%
+/-5%
R1920 4.7K +/-5%R1920 4.7K +/-5%
R1921 4.7K +/-5%R1921 4.7K +/-5%
MXM_DPC_CA_DET#
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet
+5V_RUN
R1922
R1922
10K
10K
+/-5%
+/-5%
D
Q132
Q132
2N7002W-7-F
2N7002W-7-F
S
2
U86
1A21B
2A52B
1
1OE
7
2OE
SN74CBTD3306CPWR
SN74CBTD3306CPWR
Ever Light
Ever Light
Ever Light
Technology Limited
Technology Limited
Technology Limited
24 -- MUX for HDMI
24 -- MUX for HDMI
24 -- MUX for HDMI
Thunder 1A
Thunder 1A
Thunder 1A
16V,Y5V
8
VCC
3
MXM_DPC_AUX_S
6
MXM_DPC_AUX#_S
4
GND
of
25 84Thursday , Ja nuary 27, 2 011
25 84Thursday , Ja nuary 27, 2 011
25 84Thursday , Ja nuary 27, 2 011
1
Switched HDMI
DDC pull-up
D D
MXM
AUX-
AUX+
2:1 SW
MXM_DPC_CA_DET
+5V_RUN
C1008
C1008
C1007
C1007
C1009
0.1uF
0.1uF
16V,X7R
16V,X7R
MXM_DPC_TX0+_C
MXM_DPC_TX0-_C
MXM_DPC_TX1+_C
MXM_DPC_TX1-_C
MXM_DPC_TX2+_C
MXM_DPC_TX2-_C
MXM_DPC_TX3+_C
MXM_DPC_TX3-_C
MXM_DPC_HPD
DOCK_DP1_HPD
HDMI_DET
MXM_DPC_AUX#(19)
C1009
0.1uF
0.1uF
16V,X7R
16V,X7R
MXM_DPC_AUX(19)
4
HDMI_DET
MXM_DPC_HPD
0.1uF
0.1uF
16V,X7R
C C
From dGPU
MXM_DPC_TX0(19 )
MXM_DPC_TX0#(19)
MXM_DPC_TX1(19 )
MXM_DPC_TX1#(19)
MXM_DPC_TX2(19 )
MXM_DPC_TX2#(19)
MXM_DPC_TX3(19 )
MXM_DPC_TX3#(19)
TO MB HDMI Conn
B B
A A
5
16V,X7R
C1013 0.1uF 1 6V,X7RC1013 0.1uF 16V,X7R
C1015 0.1uF 1 6V,X7RC1015 0.1uF 16V,X7R
C1016 0.1uF 1 6V,X7RC1016 0.1uF 16V,X7R
C1017 0.1uF 1 6V,X7RC1017 0.1uF 16V,X7R
C1018 0.1uF 1 6V,X7RC1018 0.1uF 16V,X7R
C1019 0.1uF 1 6V,X7RC1019 0.1uF 16V,X7R
C1020 0.1uF 1 6V,X7RC1020 0.1uF 16V,X7R
C1021 0.1uF 1 6V,X7RC1021 0.1uF 16V,X7R
HDMI_TX0+(26)
HDMI_TX0-(26)
HDMI_TX1+(26)
HDMI_TX1-(26)
HDMI_TX2+(26)
HDMI_TX2-(26)
HDMI_CLK+(26)
HDMI_CLK-(26)
MXM_DPC_HPD(19,40)
DOCK_DP1_HPD(2 7)
HDMI_DET(26)
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