Dell KAT00 Schematics

http://mycomp.su/x/

A

B

C

D

E

odel Name:

M

1 1

PCB NO:

BOM P/N:

2 2

KAT00 UMA
LA-5152P
43169631L01

Compal Confidential

Schematic Document

POITIER Montevina

3 3

2008 / 06 / 15

MB PCB

MB PCB

Part Number Description

4 4

Part Number Description

DA80000E510

DA80000E510

A

PCB 080 LA-5152P

PCB 080 LA-5152P
REV1 UMA M/B

REV1 UMA M/B

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

B

C

Rev:1.0

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

Cover Sheet

Cover Sheet

Cover Sheet

LA-5152P

LA-5152P

LA-5152P

1 51Monday, June 15, 2009

1 51Monday, June 15, 2009

1 51Monday, June 15, 2009

E

A00

A00

A00

http://mycomp.su/x/

5

lock Diagram

B
C

ompal confidential

Model : KAT00

D D

CRT CONN

+5VS

LVDS CONN

+LCDVDD
+3.3V_ALW

P.35

P.35

F

AN

5V_ALW

+
+3V_ALW

P

.7

3.3V_ALW

+

DP CONN

+5VS

HDMI CONN

+5VS

C C

To Card-reader subboard

8 IN 1 CONN

+3VS

IEEE1394

B B

Mini Card 3

TV Tunner

+3VS

DC IN

DC/DC Interface

P.37~44 P.44

A A

P.37

HDMI
Level shift

P.36

+5VS

P.36

P.30

CardBus

OZ888GS0

+3VS
+1.8VS

Express Card

P.29

Mini Card 2

WLAN

P.28 P.27 P.27

+3VS
+1.5VS+1.5VS

USB[x]

P.38

BATT IN

ME & LEDPower Sequence

P.34

5

CHARGER

4

T

hermal

MC1402

E

VGA

LVDS

DPB

DPC

PCI Express BUS

PCIE1PCIE2PCIE3

Mini Card 1

WWAN

+3VS
+1.5VS

USB[x]USB[x]

1.5V/0.75V

3V/5V

1.05V/1.8V

4

P.7

P

entium-M

P

+

1.5VS

+1.05V_VCCP

+

VCC_CORE

H

_A#(3..35) H_D#(0..63)

enryn -4MB (Socket P)

u

FCPGA CPU

4

78pin

System Bus

FSB 1066 MHz

INTEL

Cantiga

+1.5VS

+1.05V_VCCP

+3.3VS

1329pin BGA

P.10,11,12,13,14,15,16

DMI

+1.5VS
100MHz

+5V_ALW

+5VS

+RTC_CELL

+3.3VS

+3.3V_ALW_ICH

+1.5VS

+1.05V_VCCP

GPIO5

INTEL

ICH9-M

676pin BGA

P.19,20,21,22,23

LPC BUS

FFS

P.20

+3VS
33MHz

ENE KBC

KB926QFD3

+RTC_CELL

+3.3V_ALW

P.42

Int.KBD &
BL

P.40P.39

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT

P.41

BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

3

P.7,8,9

USB2.0

S-ATA(1)

PCI-E

Azalia I/F

S-ATA(3)

SATA2

E-ODD

+3VS

+5VS

P.30

Touch Pad

P.31P.31

+

+1.5V 1066 MHz

S-HDD-2

+3VS

P.28

SPI

P.28 P.28

+5VS

Flash ROM

16Mx1sector

MMB

To MMB subboard

2

C

PU ITP Port

1.05VS_CK505

M

emory BUS (DDR3)

Right Front Side.

Right behind side.

SATA0SATA1

S-HDD-1

+3VS

+5VS

P.30

P.32

+3.3VS

2

P

.7

+3.3V_ALW

Azalia Codec

92HD73C

+3.3VS
+VDDA

AMP

MAX4411x2

P.25

HeadPhone &
MIC Jack

1

C

lock Generator

C

K505

I

CS9LPRS387AKLFT

+

3VS_CK505

+1.05VS_CK505

DRIII-DIMM X2

D

B

ANK 0, 1, 2, 3, 4 ,5 ,6 ,7 ,8

+1.5V

USB Port X1

+5V_ALW

USB Port1 X1

+5V_ALW

Bluetooth

Touch Screen

Camera

P.6

P.17,18

To Card-reader
subboard

To Single USB
subboard

P.29

P.32

P.30

Charge USB/E-SATA
Ports X1

+5V_ALW

RTL8111DL

P.25

P.24

AMP

MAX9736A

B+

AMP

MAX9736A

B+

P.26

P.26

P.30

RJ45

Speaker

Subwoofer

Dig. MIC

P.29

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

Block Diagram

Block Diagram

Block Diagram

LA-5152P

LA-5152P

LA-5152P

2 51Monday, June 15, 2009

2 51Monday, June 15, 2009

2 51Monday, June 15, 2009

1

P.30

P.30

A00

A00

A00

http://mycomp.su/x/

A

Voltage Rails

O MEANS ON X MEANS OFF

Symbol Note :

power
plane

+B

State

1 1

S0

S1

S3

S5 S4/AC

S5 S4/ Battery only

S5 S4/AC & Battery
don't exist

O

O

O

O

O

X

+5VALW

+3VALW

O

O

O

O

X

X X X

+1.5V

O

X X

X

+5VS

+3VS

+1.8VS

+1.5VS

+1.1VS

+VCCP

+0.75VS

+CPU_CORE

OO

OO

X

X

: means Digital Ground

: means Analog Ground

@ : means just reserve , no build
DEBUG@ : means just reserve for debug.

USB Port

0

1

2

3

4

5

6

7

8

9

10

11

Device

USB&ESATA
Reader/BD

USB board
NC

WLAN
WWAN
WPAN
Express

NC
Touch screen
Bluetooth

Camera

SATA Port

0

1

2

3

Device

JSATA2
JSATA1

JESA1
JODD

PCIE Port

1

2

3

4

5

6

Device

JWWAN1
JWLAN1

JWPAN1

Reader/BD (OZ888)

JEXP1
RTL8111DL

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

Note List

Note List

Note List

LA-5152P

LA-5152P

LA-5152P

3 45Monday, June 15, 2009

3 45Monday, June 15, 2009

3 45Monday, June 15, 2009

1A

1A

1A

http://mycomp.su/x/

5

4

3

2

1

D D

V

R_ON

SL6266ACRZ-T

I
(PU10)

4

4000mA

CPU_CORE

+

I4392DY

S

(Q45)

7700mA

1.5VS

+

ADAPTER

B+

SYSON

BATTERY

SUSP#

CHARGER

C C

SUSP#

TPS51117RGYR
(PU8)

TPS51117RGYR
(PU6)

TPS51427

9794mA

9857mA

+1.5V

+1.05V_VCCPP

SUSP#

0 Ohm

RT9026
(PU11)

+1.05VS_CK505

?mA

+0.75VS

(PU5)

+5VALW

R03 modify

4400mA

SUSP

4800BDY

(Q5)

2000mA 7700mA 669mA160mA 20mA

USB_EN#

TPS2062ADR
(U17)

EN_EOL#

SI3456BDY
(Q3)

+LAN_IO

+5VS

+5V_CHGUSB

EN_EOL#

RTL8111DL

B B

FUSE

0 Ohm

0 Ohm

+CRT_VCC

+AVDD_AUDIO

+5VS_KBL

(U9)

+LAN_VDD

+3VALW

SUSP

FBM-11-160808-601-T
(L29)

+EC_AVCC

R03 modify

SUSP

SI4392DY

(Q50)

+3VS

0 Ohm

0 Ohm

0 Ohm

0 Ohm

+3VS_CK505

+DVDD_AUDIO

+3V_WLAN

+3V_WLAN

SUSP#

RT9025
(PU13)

+1.8VS

VDDEN

SI2310BDS-T1-E3

(Q25)

+LCDVDD

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Power Rail

Power Rail

Power Rail

LA-5152P

LA-5152P

LA-5152P

4 51Monday, June 15, 2009

4 51Monday, June 15, 2009

4 51Monday, June 15, 2009

1

A00

A00

A00

5

4

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

2

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

http://mycomp.su/x/

5

D D

G16

A

13

ICH9-M

4

ICH_SMBCLK

I

CH_SMBDATA

2

.2K

2.2K

10K

3VALW

+

3

2

N7002

2N7002

I

CH_SM_DA

ICH_SM_CLK

2

.2K

2.2K

2

202

200

202

00

+

3.3VS

D

IMMA

DIMMB

2

S

MBUS Address 0xA0

SMBUS Address 0XA4

1

10

9

CLK GEN

SMBUS Address Read D3 (H)
SMBUS Address Write D2 (H)

FFS

4.7K

C C

77

78

EC_SMB_CK1

EC_SMB_DA1

SCL1

SDA1

4.7K

+3VALW

100 ohm

100 ohm

7

6

BATTERY

CONN

4.7K

4.7K

KBC

SCL2

SDA2

KB926QFD3

112

111

EC_SMB_CK2

EC_SMB_DA2

4.7K

4.7K

17

EC_FB_SCLK

18

B B

EC_FB_DATA

+3VS

+3VS

MMB

Need make sure EC will disable this SMB port in S5 /AC mode.

32

30

32

30

32

30

32

30

8

7

WLAN

WPAN

WWAN

EXPRESS
CARD

Thermal
Sensor

SMBUS Address [TBD]

SMBUS Address [TBD]

SMBUS Address [TBD]

SMBUS Address [TBD]

SMBUS Address: 100_1100 b

I2C / SMBUS ADDRESSING

DEVICE

DDR SO-DIMM 0

HEX

A0

DDR SO-DIMM 1

CLOCK GENERATOR (EXT.)

A A

D2

ADDRESS

1 0 1 0 0 0 0 0

1 0 1 0 0 1 0 0A4

1 1 0 1 0 0 1 0

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

SMBUS TOPOLOGY

SMBUS TOPOLOGY

SMBUS TOPOLOGY

LA-5152P

LA-5152P

LA-5152P

5 45Monday, June 15, 2009

5 45Monday, June 15, 2009

5 45Monday, June 15, 2009

1

3.0

3.0

3.0

5

4

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

2

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

http://mycomp.su/x/

5

outing the trace at least 10mil

R

@

@

R

R

2

2

0_0402_5%

0_0402_5%

1 2

14.318MHZ_16PF_7A14300083

14.318MHZ_16PF_7A14300083

22P_0402_50V8J~D

22P_0402_50V8J~D

2

C

D D

C
8

8

1

CPU_STP

CLK_DEBUG_PORT<27>

CLK_PCI_EC<31>

C C

B B

PCI_CLK<20>

CK_PWRGD<21>

CLK_48M_ICH<21>

CLK_14M_ICH<21>

R02 RF reserve part.

FSC FSB REF

CLKSEL1

CLKSEL2

*

LK_XTAL_OUT

C

C

LK_XTAL_IN

Y

Y

1

1

12

22P_0402_50V8J~DC922P_0402_50V8J~D

2

C9

1

10K_0402_5%

10K_0402_5%

H_STP_CPU#<21>

H_STP_PCI#<21>

R941 33_0402_1%R941 33_0402_1%

1 2

R20 33_0402_1%R20 33_0402_1%

1 2

R24 33_0402_1%R24 33_0402_1%

1 2

10P_0402_50V8J~D

10P_0402_50V8J~D

10P_0402_50V8J~D

10P_0402_50V8J~D

C

C
1534

1534

@

@

1

2

C1533

C1533

1

1

2

2

@

@

R38 33_0402_1%R38 33_0402_1%

1 2

(14.318 reference output)

R41 33_0402_1%R41 33_0402_1%

1 2

10P_0402_50V8J~D

10P_0402_50V8J~D

10P_0402_50V8J~D

10P_0402_50V8J~D

@

@

@

@

1

C

C

C

C

1540

1540

1531

1531

2

FSA

CLKSEL0

0

+

3VS_CK505

+

1.05VS_CK505

+3VS_CK505

12

12

R548

@R548

@

R02 RF reserve part.

CPU
MHz

266

@R549

@

10K_0402_5%

10K_0402_5%

SRC
MHz

1000

R549

PCI2_TME

R_CLK_PCI_EC

27_SEL

ITP_EN

CLK_XTAL_IN

CLK_XTAL_OUT

FSB

H_STP_CPU#

H_STP_PCI#

FSA

FSC

T1PAD T1PAD

PCI
MHz

33.30

U

U

1

1

6

DDREF

V

19

DD48

V

72

V

DDCPU

12

V

DDPCI

27

V

DDPLL3

55

DDSRC

V

52

V

DDSRC_IO

38

VDDSRC_IO

62

VDDSRC_IO

31

VDDPLL3_IO

66

VDDCPU_IO

23

VDD96_IO

53

CPU_STOP#

54

PCI_STOP#

13

PCI1

14

PCI2/TME

15

PCI3

16

PCI4/27_SELECT

17

PCI_F5/ITP_EN

1

CK_PWRGD/PD#

5

X1

4

X2

11

NC

20

USB_48MHz/FSLA

2

FSLB/TEST_MODE

7

FSLC/TEST_SEL/REF0

8

REF1

69

GNDCPU

3

GNDREF

18

GNDPCI

22

GND48

30

GND

26

GND

34

GNDSRC

59

GNDSRC

42

GNDSRC

ICS9LPRS387BKLFT_MLF72_10x10

ICS9LPRS387BKLFT_MLF72_10x10

DOT_96

MHz

MHz

14.318 96.0 48.0

0 1000 133 33.31 14.318 96.0 48.0

0 1001 200 33.30 14.318 96.0 48.0

A A

0 1001 166 33.31 14.318 96.0 48.0

1 1000 333 33.30 14.318 96.0 48.0

1 1000 100 33.31 14.318 96.0 48.0

1 1001 400 33.30 14.318 96.0 48.0

1 1 1

5

Reserved

4

S

SRCC0_LPR/DOTC_96_LPR

27MHz_NonSS/SRCT1_LPR/SE1

27MHz_SS/SRCC1_LPR/SE2

CPUT2_ITP_LPR/SRCT8_LPR

CPUC2_ITP_LPR/SRCC8_LPR

B version P/N :
SA000020H10

USB
MHz

4

S

DATA

S

CLK

C

PUT0_LPR_F

C

PUC0_LPR_F

PUT1_LPR_F

C

C

PUC1_LPR_F

RCT0_LPR/DOTT_96_LPR

SRCT2_LPR/SATAT_LPR

SRCC2_LPR/SATAC_LPR

SRCT3_LPR

SRCC3_LPR

SRCT4_LPR

SRCC4_LPR

SRCT6_LPR

SRCC6_LPR

SRCT7_LPR

SRCC7_LPR

SRCT9_LPR

SRCC9_LPR

SRCT10_LPR

SRCC10_LPR

SRCT11_LPR

SRCC11_LPR

CR#3

CR#4

CR#6

CR7#

CR#9

CR10#

CR#11

CR#A

FSA

R48 2.2K_0402_5%R48 2.2K_0402_5%

CPU_BSEL0<8>

FSB

CPU_BSEL1<8>

FSC

CPU_BSEL2<8>

LK_SMBDATA

C

9

C

LK_SMBCLK

10

R

_CPU_BCLK

71

R

_CPU_BCLK#

70

R

_MCH_BCLK

68

R

_MCH_BCLK#

67

R

_MCH_DREFCLK

24

R_MCH_DREFCLK#

25

28

29

R_CLK_SATA

32

R_CLK_SATA#

33

R_CLK_EXPR

35

R_CLK_EXPR#

36

R_CLK_PCIE_WLAN

39

R_CLK_PCIE_WLAN#

40

R_CLK_WAN

57

R_CLK_WAN#

56

R_CLK_CB

61

R_CLK_CB#

60

R_DMI_ICH

64

R_DMI_ICH#

63

R_CLK_PCIE_GLAN

44

R_CLK_PCIE_GLAN#

45

R_CLK_WPAN

50

R_CLK_WPAN#

51

R_MCH_3GPLL

48

R_MCH_3GPLL#

47

37

41

58

65

43

49

46

21

1 2

R54 0_0402_5%R54 0_0402_5%

1 2

R55 10K_0402_5%R55 10K_0402_5%

1 2

3

evel shift on ICH side.

L

4

4

R

R

@

@

R

R

3

3

@

@

5

5

R

R

@

@

R

R

6 0_040 2_5%

6 0_040 2_5%

@

@

R

R

7 0_040 2_5%

7 0_040 2_5%

@

@

R

R

8 0_0402_5%

8 0_0402_5%

@

@

R

10

@R10

@

R12 0_0402_5%@R12 0_0402_5%@

R42 0_0402_5%

R42 0_0402_5%

@

@

R43

R43

@

@

R16

R16

@

@

R17

R17

@

@

R18 0_0402_5%

R18 0_0402_5%

@

@

R19 0_0402_5%

R19 0_0402_5%

@

@

R21 0_0402_5%

R21 0_0402_5%

@

@

R23

R23

@

@

R26

R26

@

@

R28

R28

@

@

R31

@ R31

@

R33

@ R33

@

R35 0_0402_5%

R35 0_0402_5%

@

@

R37 0_0402_5%

R37 0_0402_5%

@

@

R40

R40

@

@

R39

R39

@

@

R14 0_0402_5%

R14 0_0402_5%

@

@

R15 0_0402_5%

R15 0_0402_5%

@

@

R44 0_0402_5%

R44 0_0402_5%

@

@

R49 1K_0402_5%R49 1K_0402_5%

R53 1K_0402_5%R53 1K_0402_5%

R56 1K_0402_5%R56 1K_0402_5%

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

3

0_0402_5%

0_0402_5%

0_0402_5%

0_0402_5%

0_0402_5%

0_0402_5%

12

12

0_0402_5%

0_0402_5%

0_0402_5%

0_0402_5%

0_0402_5%

0_0402_5%

0_0402_5%

0_0402_5%

0_0402_5%

0_0402_5%

0_0402_5%

0_0402_5%

0_0402_5%

0_0402_5%

0_0402_5%

0_0402_5%

0_0402_5%

0_0402_5%

0_0402_5%

0_0402_5%

0_0402_5%

0_0402_5%

CH_SM_DA <17,18,20,21>

I

I

CH_SM_CLK <17,18,20,21>

C

LK_CPU_BCLK <7>

C

LK_CPU_BCLK# <7>

C

LK_MCH_BCLK <10>

C

LK_MCH_BCLK# <10>

C

LK_MCH_DREFCLK <11>

CLK_MCH_DREFCLK# <11>

MCH_SSCDREFCLK <11>

MCH_SSCDREFCLK# <11>

CLK_PCIE_SATA <19>

CLK_PCIE_SATA# <19>

CLK_PCIE_EXPR <28>

CLK_PCIE_EXPR# <28>

CLK_PCIE_WLAN <27>

CLK_PCIE_WLAN# <27>

CLK_PCIE_WAN <27>

CLK_PCIE_WAN# <27>

CLK_PCIE_CB <30>

CLK_PCIE_CB# <30>

CLK_DMI_ICH <22>

CLK_DMI_ICH# <22>

CLK_PCIE_GLAN <24>

CLK_PCIE_GLAN# <24>

CLK_PCIE_WPAN <28>

CLK_PCIE_WPAN# <28>

CLK_MCH_3GPLL <11>

CLK_MCH_3GPLL# <11>

EXP_CLKREQ# <28>

WLAN_CLKREQ# <27>

WWAN_CLK REQ# <27>

CB_CLKREQ# <30>

GLAN_CLKREQ# <24>

WPAN_CLKREQ# <28>

MCH_CLKREQ# <11>

CLKSATAREQ# <21>

MCH_CLKSEL0 <11>

MCH_CLKSEL1 <11>

MCH_CLKSEL2 <11>

C

Cardbus

DMI (ICH)

PU

MCH

VGA (UMA)

SATA

Express Card

WLAN

WWAN

GLAN

WPAN

MCH_3GPLL

2

+

3VS_CK505

1

1

R

R

1 2

3VS

+

0_0805_5%

0_0805_5%

+

1.05V_VCCP

R

R

13

13

1 2

0_0805_5%

0_0805_5%

+

1.05VS_CK505

ITP_EN

27_SEL 0 = PIN 24/25 : DOT96 / DOT96#

PCI2_TME

+3VS_CK505 +3VS_CK505 +3VS_CK505

12

R45
10K_0402_5%

10K_0402_5%

ITP_EN 27_SEL PCI2_TME

12

R50

R50
10K_0402_5%

10K_0402_5%

2

0.1U_0402_10V7K~DC20.1U_0402_10V7K~D

22U_0805_6.3V6M~DC122U_0805_6.3V6M~D

1

1

C1

2

2

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

1

1

C10

C10

2

2

EXP_CLKREQ#

WLAN_CLKREQ#

WWAN_CLK REQ#

CB_CLKREQ#

GLAN_CLKREQ#

WPAN_CLKREQ#

MCH_CLKREQ#

CLKSATAREQ#

Port Device REQ#

SRC0

SRC2

SRC3

SRC4

SRC6

SRC7

SRC8

SRC9

SRC10

SRC11

PCIE_VGA

PCIE_SATA

PCIE_EXPR

PCIE_WLAN

PCIE_WWAN

PCIE_CB

DMI_ICH

PCIE_GLAN

PCIE_WPAN

MCH_3GPLL

0 = SRC8/SRC8#

*

1 = ITP/ITP#

*

PIN 28/29 : LCDCLK / LCDCLK#
1 = PIN 24/25 : SRC_0 / SRC_0#
PIN 28/29 : 27M / 27M_SS

0.1U_0402_10V7K~DC30.1U_0402_10V7K~D

1

C2

C3

2

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

1

C11

C11

C12

C12

2

R34

R34

R32 10K_0402_5%R32 10K_0402_5%

R25 10K_0402_5%R25 10K_0402_5%

R22

R22

R30

R30

R27

R27

R36 10K_0402_5%R36 10K_0402_5%

R29 10K_0402_5%R29 10K_0402_5%

1

2

1

2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

REQ_A#

REQ#3

REQ#4

REQ#6

REQ#7

REQ#9

REQ#10

REQ#11

0.1U_0402_10V7K~DC40.1U_0402_10V7K~D

1

C4

2

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

1

C13

C13

2

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

REQ#_NAME

CLKSATAREQ#

EXP_CLKREQ#

WLAN_CLKREQ#

WAN_CLKREQ#

CB_CLKREQ#

GLAN_CLKREQ#

WPAN_CLKREQ#

MCH_CLKREQ#

0 = Overclocking of CPU and SRC Allowed

1 = Overclocking of CPU and SRC NOT allowed

*

12

R46

@R46

@R45

@

@

10K_0402_5%

10K_0402_5%

12

R51

R51
10K_0402_5%

10K_0402_5%

0103 modify it.

1 2

1 2

R47

R47
10K_0402_5%

10K_0402_5%

R52

@R52

@

10K_0402_5%

10K_0402_5%

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

Clock Generator CK505

Clock Generator CK505

Clock Generator CK505

LA-5152P

LA-5152P

LA-5152P

1

0.1U_0402_10V7K~DC50.1U_0402_10V7K~D

C5

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

C14

C14

+3VS

0103 modify it.

1

1

2

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

1

2

C7

C6

2

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

1

C15

C15

C16

C16

2

A00

A00

6 51Monday, June 15, 2009

6 51Monday, June 15, 2009

6 51Monday, June 15, 2009

A00

0.1U_0402_10V7K~DC70.1U_0402_10V7K~D

0.1U_0402_10V7K~DC60.1U_0402_10V7K~D

1

http://mycomp.su/x/

5

D D

4

3

DP / ITP

X

2

X

DP_TDI

R

R

57 54.9_0402_1 %

57 54.9_0402_1 %

X

DP_TMS

X

DP_TRST#

X

DP_TCK

T

his shall place near CPU

1 2

R

R

58 54.9_0402_1 %

58 54.9_0402_1 %

1 2

R

R

59 54.9_0402_1 %

59 54.9_0402_1 %

1 2

60 54.9_0402_1 %

60 54.9_0402_1 %

R

R

1 2

1.05V_VCCP

+

1

3 1

@

@

8

7

6

5

R237

R237

1 2

0_0402_5%

0_0402_5%

+FAN1_POWER

+5VS

40mil

+FAN1_POWER

+1.05V_VCCP

12

R61

@R61

@

56_0402_5%

56_0402_5%

B

B

2

E

E

C

C

Q1

Q1
MMBT3904_SOT23

MMBT3904_SOT23

EC_SMB_CK2

EC_SMB_DA2

MAINPWON <40,44>

1
2
3
4

OCP# <21>

EC_SMB_CK2 <27,28,31>

EC_SMB_DA2 <27,28,31>

1 2

C21 10U_0805_10V4 Z~DC21 10U_0805_10V4Z~D

U3

U3

VEN
VIN
VO
VSET

RT9027BPS_SO8

RT9027BPS_SO8

1
2

MOLEX_53261-0371~D

MOLEX_53261-0371~D

JFAN1

JFAN1

1
2
33G

CONN@

CONN@

8

GND

7

GND

6

GND

5

GND

4

G

5

CONN@

H_A#[3..16]<10>

H_ADSTB#0<10>

H_REQ#0<10>
H_REQ#1<10>
H_REQ#2<10>
H_REQ#3<10>

C C

B B

A A

H_REQ#4<10>

H_A#[17..35]<10>

H_ADSTB#1<10>

H_A20M#<19>

H_FERR#<19>

H_IGNNE#<19>

H_STPCLK#<19>

H_INTR<19>

H_NMI<19>

H_SMI#<19>

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_ADSTB#0

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35
H_ADSTB#1

H_A20M#
H_FERR#
H_IGNNE#

H_STPCLK#
H_INTR
H_NMI
H_SMI#

CONN@

JCPU1A

JCPU1A

J4

ADDR GROUP 0 ADDR GROUP 1

ADDR GROUP 0 ADDR GROUP 1

A[3]#

L5

A[4]#

L4

A[5]#

K5

A[6]#

M3

A[7]#

N2

A[8]#

J1

A[9]#

N3

A[10]#

P5

A[11]#

P2

A[12]#

L2

A[13]#

P4

A[14]#

P1

A[15]#

R1

A[16]#

M1

ADSTB[0]#

K3

REQ[0]#

H2

REQ[1]#

K2

REQ[2]#

J3

REQ[3]#

L1

REQ[4]#

Y2

A[17]#

U5

A[18]#

R3

A[19]#

W6

A[20]#

U4

A[21]#

Y5

A[22]#

U1

A[23]#

R4

A[24]#

T5

A[25]#

T3

A[26]#

W2

A[27]#

W5

A[28]#

Y4

A[29]#

U2

A[30]#

V4

A[31]#

W3

A[32]#

AA4

A[33]#

AB2

A[34]#

AA3

A[35]#

V1

ADSTB[1]#

A6

A20M#

A5

FERR#

C4

IGNNE#

D5

STPCLK#

C6

LINT0

B4

LINT1

A3

SMI#

M4

RSVD[01]

N5

RSVD[02]

T2

RSVD[03]

V3

RSVD[04]

B2

RSVD[05]

C3

RSVD[06]

D2

RSVD[07]

D22

RSVD[08]

D3

RSVD[09]

F6

RSVD[10]

Penryn

Penryn

DEFER#

DRDY#
DBSY#

IERR#

LOCK#

CONTROL

CONTROL

RESET#

RS[0]#
RS[1]#
RS[2]#

TRDY#

HITM#

BPM[0]#
BPM[1]#
BPM[2]#
BPM[3]#

PRDY#
PREQ#

TRST#

XDP/ITP SIGNALS

XDP/ITP SIGNALS

THERMAL

THERMAL

PROCHOT#

THERMDA

THERMDC

ICH

ICH

THERMTRIP#

H CLK

H CLK

BCLK[0]
BCLK[1]

RESERVED

RESERVED

ADS#
BNR#
BPRI#

BR0#

INIT#

HIT#

TCK

TDO
TMS

DBR#

TDI

H1
E2
G5

H5
F21
E1

F1

D20
B3

H4

C1
F3
F4
G3
G2

G6
E4

AD4
AD3
AD1
AC4
AC2
AC1
AC5
AA6
AB3
AB5
AB6
C20

D21
A24
B25

H_THERMTRIP#

C7

A22
A21

H_ADS#
H_BNR#
H_BPRI#

H_DEFER#
H_DRDY#
H_DBSY#

H_BR0#

H_IERR#
H_INIT#

H_LOCK#

H_RESET#
H_RS#0
H_RS#1
H_RS#2
H_TRDY#

H_HIT#
H_HITM#

XDP_TCK
XDP_TDI
XDP_TDO
XDP_TMS
XDP_TRST#
XDP_DBRESET#

H_PROCHOT#

CLK_CPU_BCLK

12

R932

R932
100_0402_1%

100_0402_1%

CLK_CPU_BCLK#

H_ADS# <10>
H_BNR# <10>
H_BPRI# <10>

H_DEFER# <10>

H_DRDY# <10>
H_DBSY# <10>

H_BR0# < 10>

H_INIT# <19>

H_LOCK# <10>

H_RESET# <10>
H_RS#0 < 10>
H_RS#1 < 10>
H_RS#2 < 10>

H_TRDY# <10>

H_HIT# <10>
H_HITM# <10>

T2T2

XDP_DBRESET# <21>

R63 68_0402_5%R63 68_0402_5%

H_THERMDA
H_THERMDC

H_THERMTRIP# <11,19>

CLK_CPU_BCLK <6>

Qual core request

CLK_CPU_BCLK# <6>

12

H_THERMDA, H_THERMDC
routing together,Trace width /
Spacing = 10 / 10 mil

+1.05V_VCCP

Control

+1.05V_VCCP

Qual core 50 ohm

H_IERR#

+3VS

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

1

C17

C17

2

2200P_0402_50V7K~D

2200P_0402_50V7K~D

C18

C18

1 2

+3VS

CPU_THERM_STP#

R64

R64

1 2

10K_0402_5%

10K_0402_5%

To power

FAN Control circuit

EN_DFAN1<31>

FAN_SPEED1<31>

R62

R62

49.9_0402_1%

49.9_0402_1%

1 2

H_THERMDA

H_THERMDC

CPU_THERM_STP#

CPU_THERM_STP#

VR_ON<31,43>

EN_DFAN1

+3VS

12

2

1

Thermal

H_PROCHOT# OCP#

Thermal Sensor EMC1402-1-ACZL-TR

U2

U2

1

VDD

2

DP

3

DN

4

THERM#

EMC1402-1-ACZL-TR_MSOP8

EMC1402-1-ACZL-TR_MSOP8

Address:100_1100

VR_ON

R65

R65
10K_0402_5%

10K_0402_5%

C22

C22

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

SMCLK

SMDATA

ALERT#

GND

Q29

Q29

2N7002W-7-F_SOT323-3~D

2N7002W-7-F_SOT323-3~D

D

S

D

S

13

G

G

2

C19

C19

10U_0805_10V4Z~D

10U_0805_10V4Z~D

12

C20

C20

12

1000P_0402_50V7K~D

1000P_0402_50V7K~D

5

4

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

2

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

Penryn(1/3)-AGTL+/ITP-XDP

Penryn(1/3)-AGTL+/ITP-XDP

Penryn(1/3)-AGTL+/ITP-XDP

LA-5152P

LA-5152P

LA-5152P

7 51Monday, June 15, 2009

7 51Monday, June 15, 2009

7 51Monday, June 15, 2009

1

A00

A00

A00

http://mycomp.su/x/

5

4

3

2

1

CPU_CORE

+

CONN@

G22

G25

G24

M24

M23

M26

AD26

AF26

E22
F24
E26

F23

E25
E23
K24

H22
F26
K22
H23

H26
H25

N22
K25
P26
R23
L23

L22

P25
P23
P22
T24
R24
L25
T25
N25
L26

N24

C23
D25
C24

AF1
A26

B22
B23
C21

J24
J23

J26

CONN@

J

J

CPU1B

CPU1B

D

[0]#

D

[1]#
[2]#

D

[3]#

D
D

[4]#
[5]#

D
D

[6]#

D

[7]#
D[8]#
D[9]#
D[10]#
D[11]#
D[12]#
D[13]#
D[14]#
D[15]#
DSTBN[0]#
DSTBP[0]#
DINV[0]#

D[16]#
D[17]#
D[18]#
D[19]#
D[20]#
D[21]#
D[22]#
D[23]#
D[24]#
D[25]#
D[26]#
D[27]#
D[28]#
D[29]#
D[30]#
D[31]#
DSTBN[1]#
DSTBP[1]#
DINV[1]#

GTLREF
TEST1
TEST2
TEST3
TEST4
TEST5
TEST6

BSEL[0]
BSEL[1]
BSEL[2]

Penryn

Penryn

DATA GRP 1

DATA GRP 1

MISC

MISC

DATA GRP 0

DATA GRP 0

D

[32]#

D

[33]#
[34]#

D

[35]#

D
D

[36]#
[37]#

D
D

[38]#

D

[39]#
D[40]#
D[41]#
D[42]#
D[43]#
D[44]#
D[45]#

DATA GRP 2DATA GRP 3

DATA GRP 2DATA GRP 3

D[46]#
D[47]#

DSTBN[2]#
DSTBP[2]#

DINV[2]#

D[48]#
D[49]#
D[50]#
D[51]#
D[52]#
D[53]#
D[54]#
D[55]#
D[56]#
D[57]#
D[58]#
D[59]#
D[60]#
D[61]#
D[62]#
D[63]#

DSTBN[3]#
DSTBP[3]#

DINV[3]#

COMP[0]
COMP[1]
COMP[2]
COMP[3]

DPRSTP#

DPSLP#
DPWR#

PWRGOOD

SLP#

PSI#

Y22
AB24
V24
V26
V23
T22
U25
U23
Y25
W22
Y23
W24
W25
AA23
AA24
AB25
Y26
AA26
U22

AE24
AD24
AA21
AB22
AB21
AC26
AD20
AE22
AF23
AC25
AE21
AD21
AC22
AD23
AF22
AC23
AE25
AF24
AC20

R26
U26
AA1
Y1

E5
B5
D24
D6
D7
AE6

H

_D#32
_D#33

H
H

_D#34

H

_D#35

H

_D#36

H

_D#37

H

_D#38

H

_D#39
_D#40

H
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_DSTBN#2
H_DSTBP#2
H_DINV#2

H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_DSTBN#3
H_DSTBP#3
H_DINV#3

COMP0
COMP1
COMP2
COMP3

H_DPRSTP#
H_DPSLP#
H_DPWR#
H_PWRGOOD
H_CPUSLP#
H_PSI#

_D#[32..47] <10>

H

H_DSTBN#2 <10>
H_DSTBP#2 <10>
H_DINV#2 <10>
H_D#[48..63] <10>

H_DSTBN#3 <10>
H_DSTBP#3 <10>
H_DINV#3 <10>

H_DPRSTP# <11,19,43>
H_DPSLP# <19>
H_DPWR# <10>
H_PWRGOOD <19>
H_CPUSLP# <10>
H_PSI# <43>

24.9_0402_1%

24.9_0402_1%

49.9_0402_1%

49.9_0402_1%

24.9_0402_1%

49.9_0402_1%

49.9_0402_1%

12

12

R67

R67

R66

R66

24.9_0402_1%

12

12

R69

R69

R68

R68

_D#[0..15]<10>

H

D D

H_DSTBN#0<10>
H_DSTBP#0<10>

H_DINV#0<10>

H_D#[16..31]<10>

C C

H_DSTBN#1<10>
H_DSTBP#1<10>

H_DINV#1<10>

T3T3
T4T4
T5T5
T6T6
T7T7
T8T8

CPU_BSEL0<6>
CPU_BSEL1<6>
CPU_BSEL2<6>

H

_D#0
_D#1

H
H

_D#2

H

_D#3

H

_D#4

H

_D#5

H

_D#6

H

_D#7
_D#8

H
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_DSTBN#0
H_DSTBP#0
H_DINV#0

H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_DSTBN#1
H_DSTBP#1
H_DINV#1

+V_CPU_GTLREF

TEST1
TEST2
TEST3
TEST4
TEST5
TEST6

CPU_BSEL0
CPU_BSEL1
CPU_BSEL2

layout note: Rout H_DPRSTP# from ICH9 to IMVP6 then to GMCH & CPU

layout note: Route TEST3 & TEST5 traces on ground referenced layer to the TPs

B B

FSB

BCLK BSEL2 BSEL1 BSEL0

533

133

0 0 1

667

166

800

200

110

1 00

Qual core value

1067 266 0 0 0

CONN@

CONN@

J

J

CPU1C

CPU1C

A7

CC[001]
CC[002]
CC[003]
CC[004]
CC[005]
CC[006]
CC[007]
CC[008]
CC[009]
CC[010]
CC[011]
CC[012]
CC[013]

CC[068]

V
V

CC[069]

V

CC[070]

V

CC[071]

V

CC[072]

V

CC[073]

V

CC[074]
CC[075]

V

CC[076]

V
V

CC[077]
CC[078]

V
V

CC[079]

V

CC[080]
VCC[081]
VCC[082]
VCC[083]
VCC[084]
VCC[085]
VCC[086]
VCC[087]
VCC[088]
VCC[089]
VCC[090]
VCC[091]
VCC[092]
VCC[093]
VCC[094]
VCC[095]
VCC[096]
VCC[097]
VCC[098]
VCC[099]
VCC[100]

VCCP[01]
VCCP[02]
VCCP[03]
VCCP[04]
VCCP[05]
VCCP[06]
VCCP[07]
VCCP[08]
VCCP[09]
VCCP[10]
VCCP[11]
VCCP[12]
VCCP[13]
VCCP[14]
VCCP[15]
VCCP[16]

VCCA[01]
VCCA[02]

VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]

VCCSENSE

VSSSENSE

AA10
AA12
AA13
AA15
AA17
AA18
AA20

AC10
AB10
AB12
AB14
AB15
AB17
AB18

V

A9

V

A10

V

A12

V

A13

V

A15

V

A17

V

A18

V

A20

V

B7

V

B9

V

B10

V

B12

V

B14

VCC[014]

B15

VCC[015]

B17

VCC[016]

B18

VCC[017]

B20

VCC[018]

C9

VCC[019]

C10

VCC[020]

C12

VCC[021]

C13

VCC[022]

C15

VCC[023]

C17

VCC[024]

C18

VCC[025]

D9

VCC[026]

D10

VCC[027]

D12

VCC[028]

D14

VCC[029]

D15

VCC[030]

D17

VCC[031]

D18

VCC[032]

E7

VCC[033]

E9

VCC[034]

E10

VCC[035]

E12

VCC[036]

E13

VCC[037]

E15

VCC[038]

E17

VCC[039]

E18

VCC[040]

E20

VCC[041]

F7

VCC[042]

F9

VCC[043]

F10

VCC[044]

F12

VCC[045]

F14

VCC[046]

F15

VCC[047]

F17

VCC[048]

F18

VCC[049]

F20

VCC[050]

AA7

VCC[051]

AA9

VCC[052]
VCC[053]
VCC[054]
VCC[055]
VCC[056]
VCC[057]
VCC[058]
VCC[059]

AB9

VCC[060]
VCC[061]
VCC[062]
VCC[063]
VCC[064]
VCC[065]
VCC[066]
VCC[067]

Penryn

Penryn

For 8 layer condition.
Length match within 25 mils.
The trace width/space/other
is 20/7/25. Zo = 27.4 ohm.

+CPU_CORE

R70 100_0402_1%R70 10 0_0402_1%

1 2

R71 100_0402_1%R71 10 0_0402_1%

1 2

CPU_CORE

+

AB20
AB7
AC7
AC9
AC12
AC13
AC15
AC17
AC18
AD7
AD9
AD10
AD12
AD14
AD15
AD17
AD18
AE9
AE10
AE12
AE13
AE15
AE17
AE18
AE20
AF9
AF10
AF12
AF14
AF15
AF17
AF18
AF20

G21
V6
J6
K6
M6
J21
K21
M21
N21
N6
R21
R6
T21
T6
V21
W21

B26
C26

AD6
AF5
AE5
AF4
AE3
AF3
AE2

VCCSENSE

AF7

VSSSENSE

AE7

.

.

VCCSENSE

VSSSENSE

+1.05V_VCCP

220U_D2_4VY_R15M~D

220U_D2_4VY_R15M~D

1

+

+

2

CPU_VID0 <43>
CPU_VID1 <43>
CPU_VID2 <43>
CPU_VID3 <43>
CPU_VID4 <43>
CPU_VID5 <43>
CPU_VID6 <43>

VCCSENSE <43>

VSSSENSE <43>

C23

C23

0.01U_0402_16V7K~D

0.01U_0402_16V7K~D

1

1

C24

C24

2

2

Near pin B26

+1.5VS

10U_0805_6.3V6M~D

10U_0805_6.3V6M~D

C25

C25

Close to CPU pin

Close to CPU pin AD26
within 500mils. Zo = 55 ohm

+V_CPU_GTLREF

+V_CPU_GTLREF

A A

Cpu Quad Core, R=1.74K_0402_1%

Cpu Dual Core, R=2K_0402_1%

5

+1.05V_VCCP

12

R72

R72
1K_0402_1%

1K_0402_1%

12

R73

R73

1.74K_0402_1%

1.74K_0402_1%

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

4

3

within 500mils.

2

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

Penryn(2/3)-AGTL+/ITP-XDP

Penryn(2/3)-AGTL+/ITP-XDP

Penryn(2/3)-AGTL+/ITP-XDP

LA-5152P

LA-5152P

LA-5152P

8 51Monday, June 15, 2009

8 51Monday, June 15, 2009

8 51Monday, June 15, 2009

1

A00

A00

A00

http://mycomp.su/x/

5

H

igh Frequence Decoupling

1

0uF 0805 X5R -> 85 degree.

D D

C C

B B

CONN@

CONN@

J

J

CPU1D

CPU1D

A4

V

SS[001]

A8

VSS[002]

A11

VSS[003]

A14

VSS[004]

A16

VSS[005]

A19

VSS[006]

A23

VSS[007]

AF2

VSS[008]

B6

VSS[009]

B8

VSS[010]

B11

VSS[011]

B13

VSS[012]

B16

VSS[013]

B19

VSS[014]

B21

VSS[015]

B24

VSS[016]

C5

VSS[017]

C8

VSS[018]

C11

VSS[019]

C14

VSS[020]

C16

VSS[021]

C19

VSS[022]

C2

VSS[023]

C22

VSS[024]

C25

VSS[025]

D1

VSS[026]

D4

VSS[027]

D8

VSS[028]

D11

VSS[029]

D13

VSS[030]

D16

VSS[031]

D19

VSS[032]

D23

VSS[033]

D26

VSS[034]

E3

VSS[035]

E6

VSS[036]

E8

VSS[037]

E11

VSS[038]

E14

VSS[039]

E16

VSS[040]

E19

VSS[041]

E21

VSS[042]

E24

VSS[043]

F5

VSS[044]

F8

VSS[045]

F11

VSS[046]

F13

VSS[047]

F16

VSS[048]

F19

VSS[049]

F2

VSS[050]

F22

VSS[051]

F25

VSS[052]

G4

VSS[053]

G1

VSS[054]

G23

VSS[055]

G26

VSS[056]

H3

VSS[057]

H6

VSS[058]

H21

VSS[059]

H24

VSS[060]

J2

VSS[061]

J5

VSS[062]

J22

VSS[063]

J25

VSS[064]

K1

VSS[065]

K4

VSS[066]

K23

VSS[067]

K26

VSS[068]

L3

VSS[069]

L6

VSS[070]

L21

VSS[071]

L24

VSS[072]

M2

VSS[073]

M5

VSS[074]

M22

VSS[075]

M25

VSS[076]

N1

VSS[077]

N4

VSS[078]

N23

VSS[079]

N26

VSS[080]
VSS[081]P3VSS[162]

Penryn

Penryn

V

SS[082]
VSS[083]
VSS[084]
VSS[085]
VSS[086]
VSS[087]
VSS[088]
VSS[089]
VSS[090]
VSS[091]
VSS[092]
VSS[093]
VSS[094]
VSS[095]
VSS[096]
VSS[097]
VSS[098]
VSS[099]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]

VSS[163]

P6
P21
P24
R2
R5
R22
R25
T1
T4
T23
T26
U3
U6
U21
U24
V2
V5
V22
V25
W1
W4
W23
W26
Y3
Y6
Y21
Y24
AA2
AA5
AA8
AA11
AA14
AA16
AA19
AA22
AA25
AB1
AB4
AB8
AB11
AB13
AB16
AB19
AB23
AB26
AC3
AC6
AC8
AC11
AC14
AC16
AC19
AC21
AC24
AD2
AD5
AD8
AD11
AD13
AD16
AD19
AD22
AD25
AE1
AE4
AE8
AE11
AE14
AE16
AE19
AE23
AE26
A2
AF6
AF8
AF11
AF13
AF16
AF19
AF21
A25
AF25

+1.05V_VCCP

1

C62

C62

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

2

4

+

CPU_CORE

1

2

+CPU_CORE

1

2

+CPU_CORE

1

2

+CPU_CORE

1

2

+CPU_CORE

1

C58

C58

2

1

C63

C63

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

2

C

C

26

26

10U_0805_4VAM~D

10U_0805_4VAM~D

C36

C36
10U_0805_4VAM~D

10U_0805_4VAM~D

C46

C46
10U_0805_4VAM~D

10U_0805_4VAM~D

C52

C52
10U_0805_4VAM~D

10U_0805_4VAM~D

330U_D2E_2.5VM_R9~D

330U_D2E_2.5VM_R9~D

1

C59

C59

+

+

2

1

2

1

C

C
10U_0805_4VAM~D

10U_0805_4VAM~D

2

1

2

1

2

1

2

330U_D2E_2.5VM_R9~D

330U_D2E_2.5VM_R9~D

C60

C60

+

+

C64

C64

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

27

27

C37

C37
10U_0805_4VAM~D

10U_0805_4VAM~D

C47

C47
10U_0805_4VAM~D

10U_0805_4VAM~D

C53

C53
10U_0805_4VAM~D

10U_0805_4VAM~D

330U_D2E_2.5VM_R9~D

330U_D2E_2.5VM_R9~D

1

C61

C61

+

+

2

1

2

1

C

C

28

28

10U_0805_4VAM~D

10U_0805_4VAM~D

2

1

C38

C38
10U_0805_4VAM~D

10U_0805_4VAM~D

2

1

C48

C48
10U_0805_4VAM~D

10U_0805_4VAM~D

2

1

C54

C54
10U_0805_4VAM~D

10U_0805_4VAM~D

2

330U_D2E_2.5VM_R9~D

330U_D2E_2.5VM_R9~D

1

+

+

2

C65

C65

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

1

10U_0805_4VAM~D

10U_0805_4VAM~D

2

1

10U_0805_4VAM~D

10U_0805_4VAM~D

2

1

10U_0805_4VAM~D

10U_0805_4VAM~D

2

1

10U_0805_4VAM~D

10U_0805_4VAM~D

2

1

C66

C66

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

2

3

1

C

C

C

29

29

C39

C39

C49

C49

C55

C55

C

30

30

10U_0805_4VAM~D

10U_0805_4VAM~D

2

1

C40

C40
10U_0805_4VAM~D

10U_0805_4VAM~D

2

1

C50

C50
10U_0805_4VAM~D

10U_0805_4VAM~D

2

1

C56

C56
10U_0805_4VAM~D

10U_0805_4VAM~D

2

1

C

C

31

31

10U_0805_4VAM~D

10U_0805_4VAM~D

2

1

C41

C41
10U_0805_4VAM~D

10U_0805_4VAM~D

2

1

C51

C51
10U_0805_4VAM~D

10U_0805_4VAM~D

2

1

C57

C57
10U_0805_4VAM~D

10U_0805_4VAM~D

2

2

1

C

C

32

32

10U_0805_4VAM~D

10U_0805_4VAM~D

2

1

C42

C42
10U_0805_4VAM~D

10U_0805_4VAM~D

2

1

C

C

33

33

10U_0805_4VAM~D

10U_0805_4VAM~D

2

1

C43

C43
10U_0805_4VAM~D

10U_0805_4VAM~D

2

1

C

C

34

34

10U_0805_4VAM~D

10U_0805_4VAM~D

2

1

C44

C44
10U_0805_4VAM~D

10U_0805_4VAM~D

2

1

C

C

35

35

10U_0805_4VAM~D

10U_0805_4VAM~D

2

1

C45

C45
10U_0805_4VAM~D

10U_0805_4VAM~D

2

1

ESR <= 1.5m ohm

Capacitor > 880 uF

1

C67

C67

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

2

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Penryn(3/3)-AGTL+/ITP-XDP

Penryn(3/3)-AGTL+/ITP-XDP

Penryn(3/3)-AGTL+/ITP-XDP

LA-5152P

LA-5152P

LA-5152P

9 51Monday, June 15, 2009

9 51Monday, June 15, 2009

9 51Monday, June 15, 2009

1

5

4

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

2

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

A00

A00

A00

http://mycomp.su/x/

5

D D

C C

Layout Note :
H_RCOMP / H_VREF / H_SWNG
Trace width and spacing is 10 / 20

+1.05V_V CCP

12

R74

R74
221_040 2_1%

221_040 2_1%

H_SW NG

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

75_0402_1%

Near C5 pin

R76 16.9_0 402_1%R7 6 16 .9_0402_1%

1 2

75_0402_1%

12

1

R75

R75

C68

C68

2

Qual core

H_RCOMP

Qual core

+1.05V_V CCP

12

R77

R77
1K_0402 _1%

1K_0402 _1%

+H_VREF

12

1

@

@

C69

0.1U_040 2_10V7K~D

0.1U_040 2_10V7K~D

B B

C69

R78

R78

2K_0402 _1%

2K_0402 _1%

2

Within 100 mils from NB

H_RCOMP Dual core 24.9 ohm_1% pull down
Qual core 16.9 ohm_1% pull down
H_SWNG Dual core 100 ohm_1% pull down
Qual core 75 ohm_1% pull down

4

_D#[0..63]<8>

H

H_RESET #<7>

H_CPUSL P#<8>

H

_D#0

H

_D#1

H

_D#2
_D#3

H
H

_D#4
_D#5

H
H

_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

H_SW NG
H_RCOMP

H_RESET #
H_CPUSL P#

+H_VREF

3

U

U

4A

4A

F2

H

_D#_0

G8

H

_D#_1

F8

H

_D#_2

E6

_D#_3

H

G2

H

_D#_4

H6

_D#_5

H

H2

H_D#_6

F6

H_D#_7

D4

H_D#_8

H3

H_D#_9

M9

H_D#_10

M11

H_D#_11

J1

H_D#_12

J2

H_D#_13

N12

H_D#_14

J6

H_D#_15

P2

H_D#_16

L2

H_D#_17

R2

H_D#_18

N9

H_D#_19

L6

H_D#_20

M5

H_D#_21

J3

H_D#_22

N2

H_D#_23

R1

H_D#_24

N5

H_D#_25

N6

H_D#_26

P13

H_D#_27

N8

H_D#_28

L7

H_D#_29

N10

H_D#_30

M3

H_D#_31

Y3

H_D#_32

AD14

H_D#_33

Y6

H_D#_34

Y10

H_D#_35

Y12

H_D#_36

Y14

H_D#_37

Y7

H_D#_38

W2

H_D#_39

AA8

H_D#_40

Y9

H_D#_41

AA13

H_D#_42

AA9

H_D#_43

AA11

H_D#_44

AD11

H_D#_45

AD10

H_D#_46

AD13

H_D#_47

AE12

H_D#_48

AE9

H_D#_49

AA2

H_D#_50

AD8

H_D#_51

AA3

H_D#_52

AD3

H_D#_53

AD7

H_D#_54

AE14

H_D#_55

AF3

H_D#_56

AC1

H_D#_57

AE3

H_D#_58

AC3

H_D#_59

AE11

H_D#_60

AE8

H_D#_61

AG2

H_D#_62

AD6

H_D#_63

C5

H_SWING

E3

H_RCOMP

C12

H_CPURST#

E11

H_CPUSLP#

A11

H_AVREF

B11

H_DVREF

CANTIGA ES _FCBGA1329

CANTIGA ES _FCBGA1329

H_ADSTB#_0
H_ADSTB#_1

H_BREQ#

H_DEFER#

HOST

HOST

H_DBSY#

HPLL_CLK

HPLL_CLK#

H_DPWR#

H_DRDY#

H_LOCK#
H_TRDY#

H_DINV#_0
H_DINV#_1
H_DINV#_2
H_DINV#_3

H_DSTBN#_0
H_DSTBN#_1
H_DSTBN#_2
H_DSTBN#_3

H_DSTBP#_0
H_DSTBP#_1
H_DSTBP#_2
H_DSTBP#_3

H_REQ#_0
H_REQ#_1
H_REQ#_2
H_REQ#_3
H_REQ#_4

H

_A#_3

H

_A#_4

H

_A#_5

H

_A#_6
_A#_7

H
H

_A#_8
_A#_9

H
H_A#_10
H_A#_11
H_A#_12
H_A#_13
H_A#_14
H_A#_15
H_A#_16
H_A#_17
H_A#_18
H_A#_19
H_A#_20
H_A#_21
H_A#_22
H_A#_23
H_A#_24
H_A#_25
H_A#_26
H_A#_27
H_A#_28
H_A#_29
H_A#_30
H_A#_31
H_A#_32
H_A#_33
H_A#_34
H_A#_35

H_ADS#

H_BNR#

H_BPRI#

H_HIT#
H_HITM#

H_RS#_0
H_RS#_1
H_RS#_2

A14
C15
F16
H13
C18
M16
J13
P16
R16
N17
M13
E17
P17
F17
G20
B19
J16
E20
H16
J20
L17
A17
B17
L16
C21
J17
H20
B18
K17
B20
F21
K21
L20

H12
B16
G17
A9
F11
G12
E9
B10
AH7
AH6
J11
F9
H9
E12
H11
C9

J8
L3
Y13
Y1

L10
M7
AA5
AE6

L9
M8
AA6
AE5

B15
K13
F13
B13
B14

B6
F12
C8

H

_A#3

H

_A#4

H

_A#5

H

_A#6
_A#7

H
H

_A#8
_A#9

H
H

_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35

H_ADS#
H_ADSTB #0
H_ADSTB #1
H_BNR#
H_BPRI#
H_BR0#
H_DEFER #
H_DBSY#
CLK_MCH _BCLK
CLK_MCH _BCLK#
H_DPW R#
H_DRDY#
H_HIT#
H_HITM#
H_LOCK#
H_TRDY#

H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3

H_DSTBN #0
H_DSTBN #1
H_DSTBN #2
H_DSTBN #3

H_DSTBP #0
H_DSTBP #1
H_DSTBP #2
H_DSTBP #3

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_RS#0
H_RS#1
H_RS#2

2

_A#[3..35] <7>

H

H_ADS# <7>
H_ADSTB #0 <7>
H_ADSTB #1 <7>
H_BNR# <7>

H_BPRI# <7>
H_BR0# <7>
H_DEFER # <7>

H_DBSY# <7>
CLK_MCH _BCLK <6>
CLK_MCH _BCLK# <6>

H_DPW R# <8>

H_DRDY# <7>

H_HIT# <7>
H_HITM# <7>

H_LOCK# <7>

H_TRDY# <7>

H_DINV#0 <8>

H_DINV#1 <8>

H_DINV#2 <8>

H_DINV#3 <8>

H_DSTBN #0 <8>

H_DSTBN #1 <8>

H_DSTBN #2 <8>

H_DSTBN #3 <8>

H_DSTBP #0 <8>

H_DSTBP #1 <8>

H_DSTBP #2 <8>

H_DSTBP #3 <8>

H_REQ#0 <7>
H_REQ#1 <7>
H_REQ#2 <7>
H_REQ#3 <7>
H_REQ#4 <7>

H_RS#0 <7 >
H_RS#1 <7 >
H_RS#2 <7 >

1

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

Title

Title

Title

Size Documen t Number Rev

Size Documen t Number Rev

Size Documen t Number Rev

Date: S heet o f

Date: S heet o f

3

2

Date: S heet o f

Compal Electronics, Inc.

Cantiga(1 of 7)

Cantiga(1 of 7)

Cantiga(1 of 7)

LA-5152P

LA-5152P

LA-5152P

A00

A00

10 51Monday, June 15 , 2009

10 51Monday, June 15 , 2009

10 51Monday, June 15 , 2009

1

A00

http://mycomp.su/x/

5

FG

C

C

79 2.21K_0402_1%@R79 2.21K_0402_1%@

R

D D

R

85 2.21K_0402_1%@R85 2.21K_0402_1%@

R

80 2.21K_0402_1%@R80 2.21K_0402_1%@

R86 2.21K_0402_1%@R86 2.21K_0402_1%@

R81 2.21K_0402_1%@R81 2.21K_0402_1%@

1 2

1 2

1 2

1 2

1 2

FG5

C

FG6

C

FG7

CFG9

CFG16

CFG[5:16] have internal pullup

+3VS

R87 4.02K_0402_1%@ R87 4.02K_0402_1%@

R88 4.02K_0402_1%@ R88 4.02K_0402_1%@

1 2

1 2

CFG19

CFG20

CFG[19:20] have internal pulldown

Strap Pin Table

CFG5

C C

B B

DMI X2 Select

iTPM Host

CFG6

Interface

Management

CFG7

Engine Crypto
Strap

PCI Express

CFG9

Graphic Lane

FSB Dynamic

CFG16

ODT

CFG19

DMI Lane
Reversal

Digital Display

CFG20

Port
Concurrent
Operation

SDVO_CRTL_DATA Low=No SDVO Device Present

DDPC_CTRLDATA

PM

+3VS

+3VS

ICH_PWROK<21,31>

VGATE<21,31,43>

PLT_RST#<20,27,30,31>

A A

Low = DMI x 2

High = DMI x 4 (Default)

Low = iTPM enable

High = iTPM disable(Defult)

Low = TLS cipher suite with no confidentiality

High = TLS cipher suite with
confidentiality(Default)
Low = Reverse Lane

High = Normal Operation(Default)

Low=Dynamic ODT Disable

High=Dynamic ODT Enable(default)

Low=Normal (default)

High=Lane Reversed

Low=Only digital display port (SDVO/DP/iHDMI) or
PCIe is operational (default)
High = Digital display port (SDVO/DP/iHDMI) and
PCIe are operating simultaneously via the PEG
port

(default)
High=SDVO Device Present

Low=DisplayPort disabled (default)

High=DisplayPort device present

R96 10K_0402_5%R96 10K_0402_5%

R97 10K_0402_5%R97 10K_0402_5%

R99 0_0402_5%

R99 0_0402_5%

R100

@R100

@

R102 100_0402_5%R102 100_0402_5%

C957 0.1U_0402_10V7K~D@C957 0.1U_0402_10V7K~D@

@

@

1 2

12

12

12

0_0402_5%

0_0402_5%

12

12

PM_EXTTS#0

PM_EXTTS#1

PM_PWROK_R

PLT_RST#_NB

H_DPRSTP#

Reserve for CPU, reference HPB

5

4

10

T10T
T11T

11

T12T

12

T20T

20

T21T

21

T22T

22

T23T

23

T13T

13

T24T

24

T14T

14

T25T

25

T15T

15

T26T

26
27

T27T

T28T28
T16T16
T17T17

T18T18

T29T29
T19T19
T30T30
T31T31

MCH_CLKSEL0<6>
MCH_CLKSEL1<6>
MCH_CLKSEL2<6>

PM_SYNC#<21>

H_DPRSTP#<8,19,43>
PM_EXTTS#0<17>
PM_EXTTS#1<18>

H_THERMTRIP#<7,19>

DPRSLPVR<21,43>

4

T32T32
T33T33

T34T34

T35T35
T36T36
T37T37
T38T38
T39T39
T40T40

T41T41
T42T42

PM_SYNC#
H_DPRSTP#
PM_EXTTS#0
PM_EXTTS#1
PM_PWROK_R

PLT_RST#_NB

H_THERMTRIP#
DPRSLPVR

CFG5
CFG6
CFG7

CFG9

CFG16

CFG19
CFG20

U

U

4B

4B

M36

SVD1

R

N36

R

SVD2

R33

SVD3

R

T33

R

SVD4

AH9

SVD5

R

AH10

R

SVD6

AH12

R

SVD7

AH13

R

SVD8

K12

R

SVD9

AL34

R

SVD10

AK34

R

SVD11

AN35

SVD12

R

AM35

SVD13

R

T24

R

SVD14

B31

RSVD15

B2

RSVD16

M1

RSVD17

AY21

RSVD20

BG23

RSVD22

BF23

RSVD23

BH18

RSVD24

BF18

RSVD25

T25

CFG_0

R25

CFG_1

P25

CFG_2

P20

CFG_3

P24

CFG_4

C25

CFG_5

N24

CFG_6

M24

CFG_7

E21

CFG_8

C23

CFG_9

C24

CFG_10

N21

CFG_11

P21

CFG_12

T21

CFG_13

R20

CFG_14

M20

CFG_15

L21

CFG_16

H21

CFG_17

P29

CFG_18

R28

CFG_19

T28

CFG_20

R29

PM_SYNC#

B7

PM_DPRSTP#

N33

PM_EXT_TS#_0

P32

PM_EXT_TS#_1

AT40

PWROK

AT11

RSTIN#

T20

THERMTRIP#

R32

DPRSLPVR

BG48

NC_1

BF48

NC_2

BD48

NC_3

BC48

NC_4

BH47

NC_5

BG47

NC_6

BE47

NC_7

BH46

NC_8

BF46

NC_9

BG45

NC_10

BH44

NC_11

BH43

NC_12

BH6

NC_13

BH5

NC_14

BG4

NC_15

BH3

NC_16

BF3

NC_17

BH2

NC_18

BG2

NC_19

BE2

NC_20

BG1

NC_21

BF1

NC_22

BD1

NC_23

BC1

NC_24

F1

NC_25

A47

NC_26

CANTIGA ES_FCBGA1329

CANTIGA ES_FCBGA1329

3

_CLK_DDR0

M

AP24

A_CK_0

S
S

A_CK_1
B_CK_0

S
S

B_CK_1

S

A_CK#_0

S

A_CK#_1

S

B_CK#_0

S

B_CK#_1

S

A_CKE_0
A_CKE_1

S

B_CKE_0

S
S

B_CKE_1

S

A_CS#_0

S

A_CS#_1

SB_CS#_0

RSVD CFG PM NC

RSVD CFG PM NC

DDR CLK/ CONTROL/ COMPENSATIONHDA

DDR CLK/ CONTROL/ COMPENSATIONHDA

CLKDMIGRAPHICS VIDMEMISC

CLKDMIGRAPHICS VIDMEMISC

SB_CS#_1

SA_ODT_0
SA_ODT_1

SB_ODT_O

SB_ODT_1

SM_RCOMP

SM_RCOMP#

SM_RCOMP_VOH

SM_RCOMP_VOL

SM_VREF

SM_PWROK

SM_REXT

SM_DRAMRST#

DPLL_REF_CLK

DPLL_REF_CLK#

DPLL_REF_SSCLK

DPLL_REF_SSCLK#

PEG_CLK

PEG_CLK#

DMI_RXN_0
DMI_RXN_1
DMI_RXN_2
DMI_RXN_3

DMI_RXP_0
DMI_RXP_1
DMI_RXP_2
DMI_RXP_3

DMI_TXN_0
DMI_TXN_1
DMI_TXN_2
DMI_TXN_3

DMI_TXP_0
DMI_TXP_1
DMI_TXP_2
DMI_TXP_3

GFX_VID_0
GFX_VID_1
GFX_VID_2
GFX_VID_3
GFX_VID_4

GFX_VR_EN

CL_CLK

CL_DATA

CL_PWROK

CL_RST#
CL_VREF

DDPC_CTRLCLK

DDPC_CTRLDATA

SDVO_CTRLCLK

SDVO_CTRLDATA

CLKREQ#

ICH_SYNC#

TSATN#

HDA_BCLK

HDA_RST#

HDA_SDI

HDA_SDO

HDA_SYNC

_CLK_DDR1

M

AT21

_CLK_DDR2

M

AV24

M

_CLK_DDR3

AU20

M

_CLK_DDR#0

AR24

M

_CLK_DDR#1

AR21

M

_CLK_DDR#2

AU24

M

_CLK_DDR#3

AV20

DR_CKE0_DIMMA

D

BC28

D

DR_CKE1_DIMMA

AY28

D

DR_CKE2_DIMMB

AY36

D

DR_CKE3_DIMMB

BB36

D

DR_CS0_DIMMA#

BA17

D

DR_CS1_DIMMA#

AY16

DR_CS2_DIMMB#

D

AV16

DDR_CS3_DIMMB#

AR13

M_ODT0_DIMMA

BD17

M_ODT1_DIMMA

AY17

M_ODT2_DIMMB

BF15

M_ODT3_DIMMB

AY13

SMRCOMP

BG22

SMRCOMP#

BH21

SMRCOMP_VOH

BF28

SMRCOMP_VOL

BH28

+V_DDR_MCH_REF

AV42

SM_PWROK

AR36
BF17

DDR3_DRAMRST#

BC36

CLK_MCH_DREFCLK

B38

CLK_MCH_DREFCLK#

A38

MCH_SSCDREFCLK

E41

MCH_SSCDREFCLK#

F41

CLK_MCH_3GPLL

F43

CLK_MCH_3GPLL#

E43

AE41
AE37
AE47
AH39

AE40
AE38
AE48
AH40

AE35
AE43
AE46
AH42

AD35
AE44
AF46
AH43

GFX_VID0

B33

GFX_VID1

B32

GFX_VID2

G33

GFX_VID3

F33

GFX_VID4

E33

GFX_VR_ON

C34

AH37
AH36
AN36
AJ35
AH34

N28
M28
G36
E36
K36

MCH_ICH_SYNC#

H36

B12

MCH_HDA_BITCLK

B28

MCH_HDA_RST#

B30

MCH_HDA_SDIN2_R

B29

MCH_HDA_SDOUT

C29

MCH_HDA_SYNC

A28

DMI_MRX_ITX_N0
DMI_MRX_ITX_N1
DMI_MRX_ITX_N2
DMI_MRX_ITX_N3

DMI_MRX_ITX_P0
DMI_MRX_ITX_P1
DMI_MRX_ITX_P2
DMI_MRX_ITX_P3

DMI_MTX_IRX_N0
DMI_MTX_IRX_N1
DMI_MTX_IRX_N2
DMI_MTX_IRX_N3

DMI_MTX_IRX_P0
DMI_MTX_IRX_P1
DMI_MTX_IRX_P2
DMI_MTX_IRX_P3

CL_CLK0
CL_DATA0

M_PWROK
CL_RST#
+CL_VREF

HDMI_C_CLK
HDMI_C_DATA
HDMI_B_CLK
HDMI_B_DATA
MCH_CLKREQ#

MCH_TSATN#

M
M
M
M

M

_CLK_DDR#0 <17>

M

_CLK_DDR#1 <17>
_CLK_DDR#2 <18>

M
M

_CLK_DDR#3 <18>

D

DR_CKE0_DIMMA <17>
DR_CKE1_DIMMA <17>

D

DR_CKE2_DIMMB <18>

D
D

DR_CKE3_DIMMB <18>

D

DR_CS0_DIMMA# <17>

D

DR_CS1_DIMMA# <17>
DDR_CS2_DIMMB# <18>
DDR_CS3_DIMMB# <18>

M_ODT0_DIMMA <17>
M_ODT1_DIMMA <17>
M_ODT2_DIMMB <18>
M_ODT3_DIMMB <18>

R90 499_0402_1%R90 499_0402_1%

1 2

DDR3_DRAMRST# <17,18>

CLK_MCH_DREFCLK <6>

CLK_MCH_DREFCLK# <6>

MCH_SSCDREFCLK <6>

MCH_SSCDREFCLK# <6>

CLK_MCH_3GPLL <6>

CLK_MCH_3GPLL# <6>

DMI_MRX_ITX_N0 <22>
DMI_MRX_ITX_N1 <22>
DMI_MRX_ITX_N2 <22>
DMI_MRX_ITX_N3 <22>

DMI_MRX_ITX_P0 <22>
DMI_MRX_ITX_P1 <22>
DMI_MRX_ITX_P2 <22>
DMI_MRX_ITX_P3 <22>

DMI_MTX_IRX_N0 <22>
DMI_MTX_IRX_N1 <22>
DMI_MTX_IRX_N2 <22>
DMI_MTX_IRX_N3 <22>

DMI_MTX_IRX_P0 <22>
DMI_MTX_IRX_P1 <22>
DMI_MTX_IRX_P2 <22>
DMI_MTX_IRX_P3 <22>

T43T43
T44T44
T45T45
T46T46
T47T47

T48T48

MCH_CLKREQ# <6>

MCH_ICH_SYNC# < 21>

R101 56_0402_5%R101 56_0402_5%

R103 33_0402_1%R 103 33_0402_1%

R104 33_0402_1%R 104 33_0402_1%

R105 0_0402_5%R105 0_0402_5 %
R106 33_0402_1%R 106 33_0402_1%

R107

R107

2

_CLK_DDR0 <17>
_CLK_DDR1 <17>
_CLK_DDR2 <18>
_CLK_DDR3 <18>

CL_CLK0 <21>

CL_DATA0 <21>

M_PWROK <21>

CL_RST# <21>

R03 modify it.

HDMI_C_CLK <36>
HDMI_C_DATA <36>
HDMI_B_CLK <37>
HDMI_B_DATA <37>

1 2

12
12
12
12

33_0402_1%

33_0402_1%

12

12.30 modify it

+V_DDR_MCH_REF

Reserve for UMA

Use for DDR3 signls,
if support DDR2 need
connect to GND

+1.05V_VCCP

HDA_BITCLK_NB <19>
HDA_RST_NB# <19>

HDA_SDIN1 <19>
HDA_SDOUT_NB <19>
HDA_SYNC_NB <19>

For HDA UMA support 1.5V

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

2

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

1

2

SM_PWROK

1

ompensation

C

S

MRCOMP

S

MRCOMP#

R

R

83 80.6_0402_1%

83 80.6_0402_1%

R

R

84 80.6_0402_1%

84 80.6_0402_1%

DDR3

+

1.5V

12

12

DDR3

+1.5V

1K_0402_1%

1K_0402_1%

12

R82

R82

SMRCOMP_VOH

2.2U_0603_6.3V6K~D

2.2U_0603_6.3V6K~D

0.01U_0402_16V7K~D

0.01U_0402_16V7K~D

1

3.01K_0402_1%

C70

C70

2

0.01U_0402_16V7K~D

0.01U_0402_16V7K~D

1

C74

C74

2

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

R94

R94

0_0402_5%

0_0402_5%

3.01K_0402_1%

12

12

@

@

12

C71

C71

2.2U_0603_6.3V6K~D

2.2U_0603_6.3V6K~D

C73

C73

C75

C75

1 2

5

U5

U5

1

P

IN1

2

IN2

G

3

74AHC1G08GW_SOT353-5~D

74AHC1G08GW_SOT353-5~D

R89

R89

1K_0402_1%

1K_0402_1%

R91

R91

C72

C72

R92

R92

12K_0402_1%

12K_0402_1%

1 2

10K_0402_5%

10K_0402_5%

12

R93

R93

1

2

SMRCOMP_VOL

1

2

+3VALW

4

O

Follow MiniCooper

+1.05V_VCCP

12

R95

R95
1K_0402_1%

1K_0402_1%

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

511_0402_1%

511_0402_1%

R98

R98

1

C76

C76

2

1 2

Thermal Sensor Aux Trip Notification: Output from the
(G)MCH to the EC indicating the Aux2 trip point (SW
programmable) has been crosse d.
(If not used, terminated 56 ohm pull up to VCCP)

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

Cantiga(2 of 7)

Cantiga(2 of 7)

Cantiga(2 of 7)

LA-5152P

LA-5152P

LA-5152P

1

1.5V_PGOOD <42>

SLP_S4# <21,31>

11 51Monday, June 15, 2009

11 51Monday, June 15, 2009

11 51Monday, June 15, 2009

A00

A00

A00

http://mycomp.su/x/

5

D D

c

heck it

For Cantiga:2.4kohm

R02 modify

C C

For UMA use

Layout Note: Place 150 Ω termination
resistors close to GMCH

R113 150_0402_1%R113 150_0402_1%

1 2

R114 150_0402_1%R114 150_0402_1%

B B

1 2

R115 150_0402_1%R115 150_0402_1%

1 2

CRT_HSYNC_R<35>

CRT_VSYNC_R<35>

30_0402_1%

30_0402_1%

30_0402_1%

30_0402_1%

R116

R116

R117

R117

4

VGA_PWM<35>

GMCH_ENBKL<31>

+3VS

LVDS_DDC_CLK<35>

LVDS_DDC_DATA<35>

GM_ENVDD<35>

LVDS_ACLK-< 35>
LVDS_ACLK+<35>
LVDS_BCLK-< 35>
LVDS_BCLK+<35>

LVDS_A0-<35>
LVDS_A1-<35>
LVDS_A2-<35>

LVDS_A0+<35>
LVDS_A1+<35>
LVDS_A2+<35>

LVDS_B0-<35>
LVDS_B1-<35>
LVDS_B2-<35>

LVDS_B0+<35>
LVDS_B1+<35>
LVDS_B2+<35>

R1536 75_0402_1%R1536 75 _0402_1%

1 2

R1537 75_0402_1%R1537 75 _0402_1%

1 2

R1538 75_0402_1%R1538 75 _0402_1%

1 2

12.30 modify it

VGA_CRT_R
VGA_CRT_G
VGA_CRT_B

CRT_DDC_CLK<35>
CRT_DDC_DATA<35>

CRT_VSYNC

GA_PWM

V

GMCH_ENBKL

R551 10K_0402_5%R551 10K_040 2_5%

1 2

R550 10K_0402_5%R550 10K_040 2_5%

1 2

GM_ENVDD

R109 2.4K_0402_1%R109 2.4K_0402_1%

1 2

LVDS_ACLK­LVDS_ACLK+
LVDS_BCLK­LVDS_BCLK+

LVDS_A0­LVDS_A1­LVDS_A2-

LVDS_A0+
LVDS_A1+
LVDS_A2+

LVDS_B0­LVDS_B1­LVDS_B2-

LVDS_B0+
LVDS_B1+
LVDS_B2+

VGA_CRT_B<35>

VGA_CRT_G<35>

VGA_CRT_R<35>

VGA_CRT_B

VGA_CRT_G

VGA_CRT_R

CRT_DDC_CLK
CRT_DDC_DATA
CRT_HSYNC

20mil

TVA_DAC
TVB_DAC
TVC_DAC

CRT_IREF

12

R118

R118
1K_0402_1%

1K_0402_1%

M32
M33

M29

3

ote: All LVDS data

N
signals/and it's compliments
should be routed
Differentially

U

U

4C

4C

L32

L_BKLT_CTRL

G32

L_BKLT_EN
L_CTRL_CLK
L_CTRL_DATA

K33

L_DDC_CLK

J33

L_DDC_DATA
L_VDD_EN

C44

LVDS_IBG

B43

LVDS_VBG

E37

LVDS_VREFH

E38

LVDS_VREFL

C41

LVDSA_CLK#

C40

LVDSA_CLK

B37

LVDSB_CLK#

A37

LVDSB_CLK

H47

LVDSA_DATA#_0

E46

LVDSA_DATA#_1

G40

LVDSA_DATA#_2

A40

LVDSA_DATA#_3

H48

LVDSA_DATA_0

D45

LVDSA_DATA_1

F40

LVDSA_DATA_2

B40

LVDSA_DATA_3

A41

LVDSB_DATA#_0

H38

LVDSB_DATA#_1

G37

LVDSB_DATA#_2

J37

LVDSB_DATA#_3

B42

LVDSB_DATA_0

G38

LVDSB_DATA_1

F37

LVDSB_DATA_2

K37

LVDSB_DATA_3

F25

TVA_DAC

H25

TVB_DAC

K25

TVC_DAC

H24

TV_RTN

C31

TV_DCONSEL_0

E32

TV_DCONSEL_1

E28

CRT_BLUE

G28

CRT_GREEN

J28

CRT_RED

G29

CRT_IRTN

H32

CRT_DDC_CLK

J32

CRT_DDC_DATA

J29

CRT_HSYNC

E29

CRT_TVO_IREF

L29

CRT_VSYNC

PEG_RX#_0
PEG_RX#_1
PEG_RX#_2
PEG_RX#_3
PEG_RX#_4
PEG_RX#_5
PEG_RX#_6
PEG_RX#_7
PEG_RX#_8
PEG_RX#_9

PEG_RX_0
PEG_RX_1
PEG_RX_2
PEG_RX_3
PEG_RX_4
PEG_RX_5
PEG_RX_6
PEG_RX_7
PEG_RX_8

PEG_RX_9
PEG_RX_10
PEG_RX_11
PEG_RX_12
PEG_RX_13
PEG_RX_14
PEG_RX_15

PEG_TX#_0
PEG_TX#_1
PEG_TX#_2
PEG_TX#_3
PEG_TX#_4
PEG_TX#_5
PEG_TX#_6
PEG_TX#_7
PEG_TX#_8
PEG_TX#_9

PEG_TX_0
PEG_TX_1
PEG_TX_2
PEG_TX_3
PEG_TX_4
PEG_TX_5
PEG_TX_6
PEG_TX_7
PEG_TX_8

PEG_TX_9
PEG_TX_10
PEG_TX_11
PEG_TX_12
PEG_TX_13
PEG_TX_14
PEG_TX_15

T37
T36

H44
J46
L44
L40
N41
P48
N44
T43
U43
Y43
Y48
Y36
AA43
AD37
AC47
AD39

H43
J44
L43
L41
N40
P47
N43
T42
U42
Y42
W47
Y37
AA42
AD36
AC48
AD40

J41
M46
M47
M40
M42
R48
N38
T40
U37
U40
Y40
AA46
AA37
AA40
AD43
AC46

J42
L46
M48
M39
M43
R47
N37
T39
U36
U39
Y39
Y46
AA36
AA39
AD42
AD46

DPB_LANE_N0
DPB_LANE_N1
DPB_LANE_N2
DPB_LANE_N3
HDC_DATA_N2
HDC_DATA_N1
HDC_DATA_N0
HDC_CLK_N

PEG_COMPI

PEG_COMPO

LVDS TV VGA

LVDS TV VGA

PEG_RX#_10
PEG_RX#_11
PEG_RX#_12
PEG_RX#_13
PEG_RX#_14
PEG_RX#_15

PCI-EXPRESS GRAPHICS

PCI-EXPRESS GRAPHICS

PEG_TX#_10
PEG_TX#_11
PEG_TX#_12
PEG_TX#_13
PEG_TX#_14
PEG_TX#_15

CANTIGA ES_FCBGA1329

CANTIGA ES_FCBGA1329

PEGCOMP

DPB_AUX#

DPB_AUX
DPB_HPD#

HDC_HPD#

DPB_LANE_P0
DPB_LANE_P1
DPB_LANE_P2
DPB_LANE_P3
HDC_DATA_P2
HDC_DATA_P1
HDC_DATA_P0
HDC_CLK_P

2

+

VCC_PEG

1 2

C78 0.1U_0402_10V 7K~DC78 0.1U_0402_10V 7K~D
C80 0.1U_0402_10V 7K~DC80 0.1U_0402_10V 7K~D
C82 0.1U_0402_10V 7K~DC82 0.1U_0402_10V 7K~D
C84 0.1U_0402_10V 7K~DC84 0.1U_0402_10V 7K~D
C86 0.1U_0402_10V 7K~DC86 0.1U_0402_10V 7K~D
C88 0.1U_0402_10V 7K~DC88 0.1U_0402_10V 7K~D
C90 0.1U_0402_10V 7K~DC90 0.1U_0402_10V 7K~D
C92 0.1U_0402_10V 7K~DC92 0.1U_0402_10V 7K~D

C77

C77
C79

C79
C81 0.1U_0402_10V7K~DC81 0.1U_0402_10V7K~D
C83 0.1U_0402_10V7K~DC83 0.1U_0402_10V7K~D
C85

C85
C87 0.1U_0402_10V7K~DC87 0.1U_0402_10V7K~D
C89

C89
C91 0.1U_0402_10V7K~DC91 0.1U_0402_10V7K~D

lace the resistor within 500mils of the GMCH

P
PEGCOMP trace widht and spacing is 20/25 mils.

R

R

108

108

49.9_0402_1%

49.9_0402_1%

DPB_AUX# <37>

DPB_AUX <37>
DPB_HPD# <37>

HDC_HPD# <36>

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

1 2

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

1 2
1 2
1 2

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

1 2
1 2

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

1 2
1 2

DPB_LANE_N0_C <37>
DPB_LANE_N1_C <37>
DPB_LANE_N2_C <37>
DPB_LANE_N3_C <37>
HDC_DATA_N2_C <36>
HDC_DATA_N1_C <36>
HDC_DATA_N0_C <36>
HDC_CLK_N_C <36>

DPB_LANE_P0_C <37>
DPB_LANE_P1_C <37>
DPB_LANE_P2_C <37>
DPB_LANE_P3_C <37>
HDC_DATA_P2_C <36>
HDC_DATA_P1_C <36>
HDC_DATA_P0_C <36>
HDC_CLK_P_C <36>

1

01.06 modify it

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Cantiga(3 of 7)

Cantiga(3 of 7)

Cantiga(3 of 7)

LA-5152P

LA-5152P

LA-5152P

A00

A00

12 51Monday, June 15, 2009

12 51Monday, June 15, 2009

12 51Monday, June 15, 2009

1

A00

5

4

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

2

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

http://mycomp.su/x/

5

D D

4

3

2

1

DDR_A_D[0..63]<17>

C C

B B

DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8

DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

AJ38
AJ41

AN38

AM38

AJ36

AJ40
AM44
AM42

AN43
AN44
AU40
AT38
AN41
AN39
AU44
AU42
AV39
AY44
BA40
BD43
AV41
AY43
BB41
BC40
AY37
BD38
AV37
AT36
AY38
BB38
AV36

AW36

BD13
AU11
BC11
BA12
AU13
AV13
BD12
BC12

AU10

BA11

BD9
AY8
BA6
AV5
AV7
AT9
AN8
AU5
AU6
AT5

AN10

AM11

AM5

AN12

AM13

AJ11

AJ12

BB9
BA9

AV9

AJ9
AJ8

U4D

U4D

SA_DQ_0
SA_DQ_1
SA_DQ_2
SA_DQ_3
SA_DQ_4
SA_DQ_5
SA_DQ_6
SA_DQ_7
SA_DQ_8
SA_DQ_9
SA_DQ_10
SA_DQ_11
SA_DQ_12
SA_DQ_13
SA_DQ_14
SA_DQ_15
SA_DQ_16
SA_DQ_17
SA_DQ_18
SA_DQ_19
SA_DQ_20
SA_DQ_21
SA_DQ_22
SA_DQ_23
SA_DQ_24
SA_DQ_25
SA_DQ_26
SA_DQ_27
SA_DQ_28
SA_DQ_29
SA_DQ_30
SA_DQ_31
SA_DQ_32
SA_DQ_33
SA_DQ_34
SA_DQ_35
SA_DQ_36
SA_DQ_37
SA_DQ_38
SA_DQ_39
SA_DQ_40
SA_DQ_41
SA_DQ_42
SA_DQ_43
SA_DQ_44
SA_DQ_45
SA_DQ_46
SA_DQ_47
SA_DQ_48
SA_DQ_49
SA_DQ_50
SA_DQ_51
SA_DQ_52
SA_DQ_53
SA_DQ_54
SA_DQ_55
SA_DQ_56
SA_DQ_57
SA_DQ_58
SA_DQ_59
SA_DQ_60
SA_DQ_61
SA_DQ_62
SA_DQ_63

SA_BS_0
SA_BS_1
SA_BS_2

SA_RAS#
SA_CAS#

SA_WE#

SA_DM_0
SA_DM_1
SA_DM_2
SA_DM_3
SA_DM_4
SA_DM_5
SA_DM_6
SA_DM_7

SA_DQS_0
SA_DQS_1
SA_DQS_2
SA_DQS_3
SA_DQS_4
SA_DQS_5
SA_DQS_6
SA_DQS_7

SA_DQS#_0
SA_DQS#_1
SA_DQS#_2
SA_DQS#_3
SA_DQS#_4
SA_DQS#_5
SA_DQS#_6
SA_DQS#_7

SA_MA_0
SA_MA_1
SA_MA_2
SA_MA_3

DDR SYSTEM MEMORY A

DDR SYSTEM MEMORY A

SA_MA_4
SA_MA_5
SA_MA_6
SA_MA_7
SA_MA_8

SA_MA_9
SA_MA_10
SA_MA_11
SA_MA_12
SA_MA_13
SA_MA_14

CANTIGA ES_FCBGA1329

CANTIGA ES_FCBGA1329

BG18
AT25

BB20
BD20
AY20

AM37
AT41
AY41
AU39
BB12
AY6
AT7
AJ5

AJ44
AT44
BA43
BC37
AW12
BC8
AU8
AM7

AJ43
AT43
BA44
BD37
AY12
BD8
AU9
AM8

BA21
BC24
BG24
BH24
BG25
BA24
BD24
BG27
BF25
AW24
BC21
BG26
BH26
BH17
AY25

DDR_A_BS1
DDR_A_BS2

DDR_A_RAS#
DDR_A_CAS#
DDR_A_WE#

DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7

DDR_A_DQS0
DDR_A_DQS1

DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7

DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8

DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14

DDR_A_BS0

BD21

DDR_A_BS0 <17>
DDR_A_BS1 <17>
DDR_A_BS2 <17>

DDR_A_RAS# <17>
DDR_A_CAS# <17>

DDR_A_WE# <17>

DDR_A_DM[0..7] <17>

DDR_A_DQS[0..7] <17>

DDR_A_DQS#[0..7] <17 >

DDR_A_MA[0..14] <17>

DDR_B_D[0..63]<18>

DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8

DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

AK47
AH46
AP47
AP46

AJ46

AJ48
AM48
AP48
AU47
AU46
BA48

AY48

AT47
AR47
BA47
BC47
BC46
BC44
BG43

BF43
BE45
BC41

BF40

BF41
BG38

BF38
BH35
BG35
BH40
BG39
BG34
BH34
BH14
BG12
BH11

BG8

BH12

BF11

BF8
BG7
BC5
BC6
AY3
AY1
BF6
BF5
BA1
BD3
AV2
AU3
AR3
AN2
AY2
AV1
AP3
AR1

AH1
AM2
AM3
AH3

AL1
AL2
AJ1

AJ3

U4E

U4E

SB_DQ_0
SB_DQ_1
SB_DQ_2
SB_DQ_3
SB_DQ_4
SB_DQ_5
SB_DQ_6
SB_DQ_7
SB_DQ_8
SB_DQ_9
SB_DQ_10
SB_DQ_11
SB_DQ_12
SB_DQ_13
SB_DQ_14
SB_DQ_15
SB_DQ_16
SB_DQ_17
SB_DQ_18
SB_DQ_19
SB_DQ_20
SB_DQ_21
SB_DQ_22
SB_DQ_23
SB_DQ_24
SB_DQ_25
SB_DQ_26
SB_DQ_27
SB_DQ_28
SB_DQ_29
SB_DQ_30
SB_DQ_31
SB_DQ_32
SB_DQ_33
SB_DQ_34
SB_DQ_35
SB_DQ_36
SB_DQ_37
SB_DQ_38
SB_DQ_39
SB_DQ_40
SB_DQ_41
SB_DQ_42
SB_DQ_43
SB_DQ_44
SB_DQ_45
SB_DQ_46
SB_DQ_47
SB_DQ_48
SB_DQ_49
SB_DQ_50
SB_DQ_51
SB_DQ_52
SB_DQ_53
SB_DQ_54
SB_DQ_55
SB_DQ_56
SB_DQ_57
SB_DQ_58
SB_DQ_59
SB_DQ_60
SB_DQ_61
SB_DQ_62
SB_DQ_63

SB_BS_0
SB_BS_1
SB_BS_2

SB_RAS#
SB_CAS#

SB_WE#

SB_DM_0
SB_DM_1
SB_DM_2
SB_DM_3
SB_DM_4
SB_DM_5
SB_DM_6
SB_DM_7

SB_DQS_0
SB_DQS_1
SB_DQS_2
SB_DQS_3
SB_DQS_4
SB_DQS_5
SB_DQS_6
SB_DQS_7

SB_DQS#_0
SB_DQS#_1
SB_DQS#_2
SB_DQS#_3
SB_DQS#_4
SB_DQS#_5
SB_DQS#_6
SB_DQS#_7

SB_MA_0
SB_MA_1
SB_MA_2

DDR SYSTEM MEMORY B

DDR SYSTEM MEMORY B

SB_MA_3
SB_MA_4
SB_MA_5
SB_MA_6
SB_MA_7
SB_MA_8

SB_MA_9
SB_MA_10
SB_MA_11
SB_MA_12
SB_MA_13
SB_MA_14

CANTIGA ES_FCBGA1329

CANTIGA ES_FCBGA1329

BB17
BB33

AU17
BG16
BF14

AM47
AY47
BD40
BF35
BG11
BA3
AP1
AK2

AL47
AV48
BG41
BG37
BH9
BB2
AU1
AN6

AL46
AV47
BH41
BH37
BG9
BC2
AT2
AN5

AV17
BA25
BC25
AU25
AW25
BB28
AU28
AW28
AT33
BD33
BB16
AW33
AY33
BH15
AU33

DDR_B_BS1
DDR_B_BS2

DDR_B_RAS#
DDR_B_CAS#

DDR_B_WE#

DDR_B_DM0
DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7

DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7

DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8

DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14

DDR_B_RAS# < 18>
DDR_B_CAS# < 18>

DDR_B_WE# <18>

DDR_B_BS0

BC16

DDR_B_BS0 <18>
DDR_B_BS1 <18>
DDR_B_BS2 <18>

DDR_B_DM[0..7] <18>

DDR_B_DQS[0..7] <18>

DDR_B_DQS#[0..7] <18>

DDR_B_MA[0..14] <18>

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Cantiga(4 of 7)

Cantiga(4 of 7)

Cantiga(4 of 7)

LA-5152P

LA-5152P

LA-5152P

A00

A00

13 51Monday, June 15, 2009

13 51Monday, June 15, 2009

13 51Monday, June 15, 2009

1

A00

5

4

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

2

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

http://mycomp.su/x/

5

1

+

+

2

2

2

1U_0603_10V6K~D

1U_0603_10V6K~D

1

C121

C121

2

1067M 4140mA
800M 3162mA

330U_D2_2.5VY_R9M~D

330U_D2_2.5VY_R9M~D

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

1

C109

C109

C110

C110

2

10U_0805_10V4Z~D

10U_0805_10V4Z~D

1

C123

C123

2

1

2

1

2

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

C114

C114

10U_0805_10V4Z~D

10U_0805_10V4Z~D

C124

C124

0.01U_0402_16V7K~D

0.01U_0402_16V7K~D

2

C115

C115

1

+AXG_CORE

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

1

2

T53PAD T53PAD
T54PAD T54PAD

C125

C125

8700mA

D

DR3

+

1.5V

D D

C C

+1.05V_VCCP +AXG_CORE

B B

A A

J1

J1

112

JUMP_43X118

JUMP_43X118

J2

J2

112

JUMP_43X118

JUMP_43X118

4

4F

4F

U

U

AP33

V

CC_SM_1

AN33

V

CC_SM_2

BH32

V

CC_SM_3

BG32

V

CC_SM_4

BF32

V

CC_SM_5

BD32

CC_SM_6

V

BC32

CC_SM_7

V

BB32

V

CC_SM_8

BA32

CC_SM_9

V

AY32

V

CC_SM_10

AW32

V

CC_SM_11

AV32

VCC_SM_12

AU32

VCC_SM_13

AT32

VCC_SM_14

AR32

VCC_SM_15

AP32

VCC_SM_16

AN32

VCC_SM_17

BH31

VCC_SM_18

BG31

VCC_SM_19

BF31

VCC_SM_20

BG30

VCC_SM_21

BH29

VCC_SM_22

BG29

VCC_SM_23

BF29

VCC_SM_24

BD29

VCC_SM_25

BC29

VCC_SM_26

BB29

VCC_SM_27

BA29

VCC_SM_28

AY29

VCC_SM_29

AW29

VCC_SM_30

AV29

VCC_SM_31

AU29

VCC_SM_32

AT29

VCC_SM_33

AR29

VCC_SM_34

AP29

VCC_SM_35

BA36

VCC_SM_36/NC

BB24

VCC_SM_37/NC

BD16

VCC_SM_38/NC

BB21

VCC_SM_39/NC

AW16

VCC_SM_40/NC

AW13

VCC_SM_41/NC

AT13

VCC_SM_42/NC

Y26

VCC_AXG_1

AE25

VCC_AXG_2

AB25

VCC_AXG_3

AA25

VCC_AXG_4

AE24

VCC_AXG_5

AC24

VCC_AXG_6

AA24

VCC_AXG_7

Y24

VCC_AXG_8

AE23

VCC_AXG_9

AC23

VCC_AXG_10

AB23

VCC_AXG_11

AA23

VCC_AXG_12

AJ21

VCC_AXG_13

AG21

VCC_AXG_14

AE21

VCC_AXG_15

AC21

VCC_AXG_16

AA21

VCC_AXG_17

Y21

VCC_AXG_18

AH20

VCC_AXG_19

AF20

VCC_AXG_20

AE20

VCC_AXG_21

AC20

VCC_AXG_22

AB20

VCC_AXG_23

AA20

VCC_AXG_24

T17

VCC_AXG_25

T16

VCC_AXG_26

AM15

VCC_AXG_27

AL15

VCC_AXG_28

AE15

VCC_AXG_29

AJ15

VCC_AXG_30

AH15

VCC_AXG_31

AG15

VCC_AXG_32

AF15

VCC_AXG_33

AB15

VCC_AXG_34

AA15

VCC_AXG_35

Y15

VCC_AXG_36

V15

VCC_AXG_37

U15

VCC_AXG_38

AN14

VCC_AXG_39

AM14

VCC_AXG_40

U14

VCC_AXG_41

T14

VCC_AXG_42

AJ14

VCC_AXG_SENSE

AH14

VSS_AXG_SENSE

CANTIGA ES_FCBGA1329

CANTIGA ES_FCBGA1329

V

CC_AXG_NTCF_1

V

CC_AXG_NCTF_2

V

CC_AXG_NCTF_3

V

CC_AXG_NCTF_4

V

CC_AXG_NCTF_5

V

CC_AXG_NCTF_6
CC_AXG_NCTF_7

V

CC_AXG_NCTF_8

V

VCC SM

VCC SM

V

CC_AXG_NCTF_9

CC_AXG_NCTF_10

V
V

CC_AXG_NCTF_11

V

CC_AXG_NCTF_12
VCC_AXG_NCTF_13
VCC_AXG_NCTF_14
VCC_AXG_NCTF_15
VCC_AXG_NCTF_16
VCC_AXG_NCTF_17
VCC_AXG_NCTF_18
VCC_AXG_NCTF_19
VCC_AXG_NCTF_20
VCC_AXG_NCTF_21
VCC_AXG_NCTF_22
VCC_AXG_NCTF_23
VCC_AXG_NCTF_24
VCC_AXG_NCTF_25
VCC_AXG_NCTF_26
VCC_AXG_NCTF_27
VCC_AXG_NCTF_28
VCC_AXG_NCTF_29
VCC_AXG_NCTF_30
VCC_AXG_NCTF_31
VCC_AXG_NCTF_32
VCC_AXG_NCTF_33
VCC_AXG_NCTF_34
VCC_AXG_NCTF_35
VCC_AXG_NCTF_36
VCC_AXG_NCTF_37
VCC_AXG_NCTF_38
VCC_AXG_NCTF_39
VCC_AXG_NCTF_40
VCC_AXG_NCTF_41
VCC_AXG_NCTF_42
VCC_AXG_NCTF_43

VCC GFX NCTF

VCC GFX NCTF

VCC_AXG_NCTF_44
VCC_AXG_NCTF_45
VCC_AXG_NCTF_46
VCC_AXG_NCTF_47
VCC_AXG_NCTF_48
VCC_AXG_NCTF_49
VCC_AXG_NCTF_50
VCC_AXG_NCTF_51
VCC_AXG_NCTF_52

POWER

POWER

VCC_AXG_NCTF_53
VCC_AXG_NCTF_54
VCC_AXG_NCTF_55
VCC_AXG_NCTF_56
VCC_AXG_NCTF_57
VCC_AXG_NCTF_58
VCC_AXG_NCTF_59
VCC_AXG_NCTF_60

VCC GFX

VCC GFX

VCC_SM_LF1
VCC_SM_LF2
VCC_SM_LF3
VCC_SM_LF4
VCC_SM_LF5
VCC_SM_LF6
VCC_SM_LF7

VCC SM LF

VCC SM LF

W28
V28
W26
V26
W25
V25
W24
V24
W23
V23
AM21
AL21
AK21
W21
V21
U21
AM20
AK20
W20
U20
AM19
AL19
AK19
AJ19
AH19
AG19
AF19
AE19
AB19
AA19
Y19
W19
V19
U19
AM17
AK17
AH17
AG17
AF17
AE17
AC17
AB17
Y17
W17
V17
AM16
AL16
AK16
AJ16
AH16
AG16
AF16
AE16
AC16
AB16
AA16
Y16
W16
V16
U16

AV44
BA37
AM40
AV21
AY5
AM10
BB13

AXG_CORE

+

VCCSM_LF1
VCCSM_LF2
VCCSM_LF3
VCCSM_LF4
VCCSM_LF5
VCCSM_LF6
VCCSM_LF7

3

22U_0805_6.3V6M~D

0.47U_0402_10V4Z~D

0.47U_0402_10V4Z~D

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

1

1

C1502

C1502

C111

C111

2

2

22U_0805_6.3V6M~D

1U_0603_10V6K~D

1U_0603_10V6K~D

1

1

C1503

C1503

C1506

C1506

2

2

Layout Note: Inside GMC

330U_D2_2.5VY_R15M

330U_D2_2.5VY_R15M

330U_D2_2.5VY_R15M

330U_D2_2.5VY_R15M

@

@

@

@

1

C1500

C1500

+

+

2

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

1

C126

C126

2

1

C1501

C1501

+

+

2

0.22U_0402_10V4Z~D

0.22U_0402_10V4Z~D

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

1

1

C127

C127

2

2

Layout Note:

Place close to GMCH

0.22U_0402_10V4Z~D

0.22U_0402_10V4Z~D

C128

C128

C129

C129

1

1

2

2

2

xtnal Graphic: 3060mA

E

+

1.05V_VCCP

AG34
AC34
AB34
AA34

Y34
V34
U34

AM33
AK33

AJ33
AG33
AF33

220U_D2_4VY_R15M~D

220U_D2_4VY_R15M~D

1

C116

C116

+

+

2

1U_0402_6.3V4Z~D

1U_0402_6.3V4Z~D

1U_0402_6.3V4Z~D

.47U_0402_6.3V6-K~D

.47U_0402_6.3V6-K~D

C130

C130

1U_0402_6.3V4Z~D

1

1

C131

C131

C132

C132

2

2

0.22U_0402_10V4Z~D

0.22U_0402_10V4Z~D

10U_0805_10V4Z~D

10U_0805_10V4Z~D

1

1

C117

C117

C118

C118

2

2

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

0.22U_0402_10V4Z~D

0.22U_0402_10V4Z~D

1

1

C119

C119

2

2

AE33
AC33
AA33

Y33

W33

V33

C120

C120

U33
AH28
AF28
AC28
AA28

AJ26
AG26
AE26
AC26
AH25
AG25
AF25
AG24

AJ23
AH23
AF23

T32

integrated Graphic: 2898mA

4G

4G

U

U

V

CC_1
CC_2

V
V

CC_3

V

CC_4
VCC_5
VCC_6
VCC_7
VCC_8
VCC_9
VCC_10
VCC_11
VCC_12

VCC_13
VCC_14
VCC_15
VCC_16
VCC_17
VCC_18
VCC_19
VCC_20
VCC_21
VCC_22
VCC_23
VCC_24
VCC_25
VCC_26
VCC_27
VCC_28
VCC_29
VCC_30
VCC_31
VCC_32
VCC_33
VCC_34
VCC_35

CANTIGA ES_FCBGA1329

CANTIGA ES_FCBGA1329

VCC CORE

VCC CORE

POWER

POWER

1

VCC_NCTF_1
VCC_NCTF_2
VCC_NCTF_3
VCC_NCTF_4
VCC_NCTF_5
VCC_NCTF_6
VCC_NCTF_7
VCC_NCTF_8

VCC_NCTF_9
VCC_NCTF_10
VCC_NCTF_11
VCC_NCTF_12
VCC_NCTF_13
VCC_NCTF_14
VCC_NCTF_15
VCC_NCTF_16
VCC_NCTF_17
VCC_NCTF_18
VCC_NCTF_19
VCC_NCTF_20
VCC_NCTF_21
VCC_NCTF_22
VCC_NCTF_23
VCC_NCTF_24
VCC_NCTF_25
VCC_NCTF_26
VCC_NCTF_27
VCC_NCTF_28

VCC NCTF

VCC NCTF

VCC_NCTF_29
VCC_NCTF_30
VCC_NCTF_31
VCC_NCTF_32
VCC_NCTF_33
VCC_NCTF_34
VCC_NCTF_35
VCC_NCTF_36
VCC_NCTF_37
VCC_NCTF_38
VCC_NCTF_39
VCC_NCTF_40
VCC_NCTF_41
VCC_NCTF_42
VCC_NCTF_43
VCC_NCTF_44

AM32
AL32
AK32
AJ32
AH32
AG32
AE32
AC32
AA32
Y32
W32
U32
AM30
AL30
AK30
AH30
AG30
AF30
AE30
AC30
AB30
AA30
Y30
W30
V30
U30
AL29
AK29
AJ29
AH29
AG29
AE29
AC29
AA29
Y29
W29
V29
AL28
AK28
AL26
AK26
AK25
AK24
AK23

+1.05V_VCCP

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Cantiga(5 of 7)

Cantiga(5 of 7)

Cantiga(5 of 7)

LA-5152P

LA-5152P

LA-5152P

A00

A00

14 51Monday, June 15, 2009

14 51Monday, June 15, 2009

14 51Monday, June 15, 2009

1

A00

5

4

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

2

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

http://mycomp.su/x/

5

+

3VS

1 2

BLM18PG181SN1_0603~D

BLM18PG181SN1_0603~D

D D

+

3.3V_CRT_DAC

L

L

1

1

0.01U_0402_25V7K~D

0.01U_0402_25V7K~D

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

1

1

C140

C140

C135

C135

2

2

3.3V_CRT_DAC

+

1

2

0.01U_0402_25V7K~D

0.01U_0402_25V7K~D

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

1

C136

C136

C141

C141

2

Place close to U4H.A25Place close to U4H.B27 and A26

Place close to U4H.F47

+1.05V_M_DPLLA

0.1U_0402_10V7K~D

64.8mA Max.

C C

64.8mA Max.

0.1U_0402_10V7K~D

1

2

+1.05V_M_DPLLB

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

1

2

220U_D2_4VY_R15M~D

220U_D2_4VY_R15M~D

10UH_LB2012T100MR_20%_0805~D

10UH_LB2012T100MR_20%_0805~D

1

+

+

C

C
1505

1505

2

220U_D2_4VY_R15M~D

220U_D2_4VY_R15M~D

10UH_LB2012T100MR_20%_0805~D

10UH_LB2012T100MR_20%_0805~D

1

+

+

C

C

C1509

C1509

1510

1510

2

+1.05V_VCCP

L1500

L1500

12

C1504

C1504

+1.05V_VCCP

L1503

L1503

12

Place close to U4H.J48

+1.8VS +VCC_TX_LVDS

L1501

L1501

HK1608R10J-T_0603~D

HK1608R10J-T_0603~D

Place close to U4H.L48

B B

Place close to U4H.M25

+1.5VS +1.5VS_TVDAC

R1539

R1539

12

0_0603_5%

0_0603_5%

0103 modify it.

Place close to U4H.B24 and A24

+3VS

A A

L1502

L1502

BLM18PG181SN1_0603~D

BLM18PG181SN1_0603~D

1 2

0103 modify it.

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

1

2

+3VS_TVDAC

1

2

5

0.01U_0402_25V7K~D

0.01U_0402_25V7K~D

1

C1525

C1525

C1526

C1526

2

0.01U_0402_25V7K~D

0.01U_0402_25V7K~D

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

C1524

C1524

1

C1523

C1523

2

+1.05V_VCCP

4

1.05V_VCCP

+

12

1

2

+1.5VS +1.5VS_QDAC

119

119

R

R
0_0603_5%

0_0603_5%

1 2

+

1.05V_VCCP

1 2

BLM18AG121SN1D_0603~D

BLM18AG121SN1D_0603~D

1000P_0402_50V7K~D

1000P_0402_50V7K~D

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

1

C1508

C1508

C1507

C1507

2

+1.05V_VCCP

100U_D2E_6.3VM_R18M~D

100U_D2E_6.3VM_R18M~D

C150

C150

+1.05V_VCCP

L3

L3

1 2

BLM18PG181SN1_0603~D

BLM18PG181SN1_0603~D

R130 0_0402_5%R13 0 0_0402_5%

+1.05V_VCCP

BLM18PG181SN1_0603~D

BLM18PG181SN1_0603~D

1 2

C171

C171

10U_0805_4VAM~D

10U_0805_4VAM~D

12

4

2

2

L

L

+1.5VS

1

+

+

2

R126 0_0603_5%R126 0_0603_5%

1

2

12

L4

L4

R131

R131

1_0402_5%

1_0402_5%

4.7U_0603_6.3V6M~D

4.7U_0603_6.3V6M~D

C133

C133

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

R123

R123

0_0603_5%

0_0603_5%

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

C160

C160

1

2

1

2

1.05V_M_HPLL

+

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

1

1

C134

C134

2

2

1.05V_M_MPLL

+

0_0603_5%

0_0603_5%

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

R120

R120

1

C137

C137

1 2

2

1

C145

C145

2

R121

R121

12

0_0402_5%

0_0402_5%

+1.05V_A_SM

12

1

2

12

0.01U_0402_25V7K~D

0.01U_0402_25V7K~D

+1.5VS

C161

C161

C166

C166

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

+1.05V_M_PEGPLL

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

1

2

+1.05V_M_DPLLA

+1.05V_M_DPLLB

+VCC_TX_LVDS

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

1

C147

C147

2

4.7U_0603_6.3V6M~D

4.7U_0603_6.3V6M~D

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

C152

C152

1

C151

C151

2

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

1

C156

C156

2

2

C159

C159

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

1

+1.8VS

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

1

C172

C172

C173

C173

2

3

U

U

4H

4H

3.3V_CRT_DAC

+

+

3.3V_CRT_DAC

+VCCA_PEG_BG

+1.05V_M_PEGPLL

1U_0603_10V6K~D

1U_0603_10V6K~D

1

C153

C153

2

+1.05V_A_SM_CK

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

1

C157

C157

2

TVA_DAC 24.15mA
TVB_DAC 39.48mA
TVC_DAC 24.15mA

+3VS_TVDAC

+1.5VS_TVDAC

1U_0603_10V6K~D

1U_0603_10V6K~D

1

2

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

64.8mA

64.8mA

24mA

139.2mA

13.2mA

50mA

747mA

50mA

1mA

157.2mA

50mA

60.31mA

C170

C170

414uA

37.95mA

35mA

AD48

AA48

AR20
AP20
AN20
AR17
AP17
AN17
AT16
AR16
AP16

AP28
AN28
AP25
AN25

AN24
AM28
AM26
AM25

AL25

AM24

AL24

AM23

AL23

AA47

B27

V

CCA_CRT_DAC_1

A26

V

CCA_CRT_DAC_2

A25

CCA_DAC_BG

V

B25

SSA_DAC_BG

V

F47

VCCA_DPLLA

L48

VCCA_DPLLB

AD1

VCCA_HPLL

AE1

VCCA_MPLL

J48

VCCA_LVDS

J47

VSSA_LVDS

VCCA_PEG_BG

VCCA_PEG_PLL

VCCA_SM_1
VCCA_SM_2
VCCA_SM_3
VCCA_SM_4
VCCA_SM_5
VCCA_SM_6
VCCA_SM_7
VCCA_SM_8
VCCA_SM_9

VCCA_SM_CK_1
VCCA_SM_CK_2
VCCA_SM_CK_3
VCCA_SM_CK_4
VCCA_SM_CK_5
VCCA_SM_CK_NCTF_1
VCCA_SM_CK_NCTF_2
VCCA_SM_CK_NCTF_3
VCCA_SM_CK_NCTF_4
VCCA_SM_CK_NCTF_5
VCCA_SM_CK_NCTF_6
VCCA_SM_CK_NCTF_7
VCCA_SM_CK_NCTF_8

B24

VCCA_TV_DAC_1

A24

VCCA_TV_DAC_2

A32

VCC_HDA

M25

VCCD_TVDAC

L28

VCCD_QDAC

AF1

VCCD_HPLL

VCCD_PEG_PLL

M38

VCCD_LVDS_1

L37

VCCD_LVDS_2

CANTIGA ES_FCBGA1329

CANTIGA ES_FCBGA1329

POWER

POWER

A SM

A SM

HDA

HDA

LVDS D TV/CRT

LVDS D TV/CRT

CRTPLLA LVDSA PEG

CRTPLLA LVDSA PEG

TV

TV

VTT

VTT

VCC_AXF_1
VCC_AXF_2
VCC_AXF_3

AXF

AXF

VCC_SM_CK_1
VCC_SM_CK_2
VCC_SM_CK_3
VCC_SM_CK_4

SM CK

SM CK

VCC_TX_LVDS

A CK

A CK

VCC_HV_1
VCC_HV_2
VCC_HV_3

HV

HV

VCC_PEG_1
VCC_PEG_2
VCC_PEG_3
VCC_PEG_4
VCC_PEG_5

VCC_DMI_1
VCC_DMI_2
VCC_DMI_3
VCC_DMI_4

DMI PEG

DMI PEG

VTTLF

VTTLF

V

TT_1

V

TT_2

V

TT_3

V

TT_4

V

TT_5
TT_6

V

TT_7

V
V

TT_8
TT_9

V

V

TT_10

V

TT_11
VTT_12
VTT_13
VTT_14
VTT_15
VTT_16
VTT_17
VTT_18
VTT_19
VTT_20
VTT_21
VTT_22
VTT_23
VTT_24
VTT_25

VTTLF1
VTTLF2
VTTLF3

U13
T13
U12
T12
U11
T11
U10
T10
U9
T9
U8
T8
U7
T7
U6
T6
U5
T5
V3
U3
V2
U2
T2
V1
U1

321.35mA

B22
B21
A21

149mA

BF21
BH20
BG20
BF20

118.8mA

K47

105.3mA

C35
B35
A35

1782mA

V48
U48
V47
U47
U46

456mA

AH48
AF48
AH47
AG47

GMCH_VTTLF1

A8

GMCH_VTTLF2

L1

GMCH_VTTLF3

AB2

2

852mA

+VCC_AXF

+1.5V_SM_CK

+VCC_TX_LVDS

2

+

1.05V_VCCP

4.7U_0603_6.3V6M~D

4.7U_0603_6.3V6M~D

C138

C138

1

2

.47U_0402_6.3V6-K~D

.47U_0402_6.3V6-K~D

1

C142

C142

2

+VCC_AXF

R129 0_0603_5%R129 0_0603_5%

1

C165

C165

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

2

1

2

1U_0603_10V6K~D

1U_0603_10V6K~D

1

2

1 2

.47U_0402_6.3V6-K~D

.47U_0402_6.3V6-K~D

C167

C167

10U_0805_4VAM~D

10U_0805_4VAM~D

1

C148

C148

2

1

2

+3VS

1

2

.47U_0402_6.3V6-K~D

.47U_0402_6.3V6-K~D

C168

C168

1

2

1 2

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

1

2

1

220U_D2_4VY_R15M~D

220U_D2_4VY_R15M~D

1

C139

C139

+

+

2

4.7U_0603_6.3V6M~D

4.7U_0603_6.3V6M~D

2.2U_0603_10V6K~D

@

@

C149

C149

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

C158

C158

R122

R122

C154

C154

2.2U_0603_10V6K~D

1

2

1 2

10_0402_5%

10_0402_5%

.47U_0402_6.3V6-K~D

.47U_0402_6.3V6-K~D

C169

C169

C143

C143

0_0603_5%

0_0603_5%

12

1_0402_5%

1_0402_5%

R125

R125

10U_0805_4VAM~D

10U_0805_4VAM~D

@

@

R127

R127

+VCC_PEG+VCC_DMI

C144

C144

1

2

R124

R124

0_0805_5%

0_0805_5%

C155

C155

1 2

+VCC_PEG

+1.05V_VCCP

12

4.7U_0603_6.3V6M~D

4.7U_0603_6.3V6M~D

1

2

DDR3 connect to 1.5V

+1.5VS

CRB schematic
HPB & Avia no draw.

D1

D1

@

@

21

CH751H-40PT_SOD323-2~D

CH751H-40PT_SOD323-2~D

220U_D2_4VY_R15M~D

220U_D2_4VY_R15M~D

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

C162

C162

C164

C164

1

C163

C163

1

+

+

2

2

+1.05V_VCCP

R02 modify

1 2

JP2@ JP2@

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

Cantiga(6 of 7)

Cantiga(6 of 7)

Cantiga(6 of 7)

LA-5152P

LA-5152P

LA-5152P

15 51Monday, June 15, 2009

15 51Monday, June 15, 2009

15 51Monday, June 15, 2009

1

+1.05V_VCCP

A00

A00

A00

http://mycomp.su/x/

5

D D

C C

B B

A A

4

4I

4I

U

U

AU48

V

SS_1

AR48

SS_2

V

AL48

V

SS_3

BB47

V

SS_4

AW47

V

SS_5

AN47

V

SS_6

AJ47

V

SS_7

AF47

V

SS_8

AD47

SS_9

V

AB47

SS_10

V

Y47

V

SS_11

T47

SS_12

V

N47

V

SS_13

L47

V

SS_14

G47

VSS_15

BD46

VSS_16

BA46

VSS_17

AY46

VSS_18

AV46

VSS_19

AR46

VSS_20

AM46

VSS_21

V46

VSS_22

R46

VSS_23

P46

VSS_24

H46

VSS_25

F46

VSS_26

BF44

VSS_27

AH44

VSS_28

AD44

VSS_29

AA44

VSS_30

Y44

VSS_31

U44

VSS_32

T44

VSS_33

M44

VSS_34

F44

VSS_35

BC43

VSS_36

AV43

VSS_37

AU43

VSS_38

AM43

VSS_39

J43

VSS_40

C43

VSS_41

BG42

VSS_42

AY42

VSS_43

AT42

VSS_44

AN42

VSS_45

AJ42

VSS_46

AE42

VSS_47

N42

VSS_48

L42

VSS_49

BD41

VSS_50

AU41

VSS_51

AM41

VSS_52

AH41

VSS_53

AD41

VSS_54

AA41

VSS_55

Y41

VSS_56

U41

VSS_57

T41

VSS_58

M41

VSS_59

G41

VSS_60

B41

VSS_61

BG40

VSS_62

BB40

VSS_63

AV40

VSS_64

AN40

VSS_65

H40

VSS_66

E40

VSS_67

AT39

VSS_68

AM39

VSS_69

AJ39

VSS_70

AE39

VSS_71

N39

VSS_72

L39

VSS_73

B39

VSS_74

BH38

VSS_75

BC38

VSS_76

BA38

VSS_77

AU38

VSS_78

AH38

VSS_79

AD38

VSS_80

AA38

VSS_81

Y38

VSS_82

U38

VSS_83

T38

VSS_84

J38

VSS_85

F38

VSS_86

C38

VSS_87

BF37

VSS_88

BB37

VSS_89

AW37

VSS_90

AT37

VSS_91

AN37

VSS_92

AJ37

VSS_93

H37

VSS_94

C37

VSS_95

BG36

VSS_96

BD36

VSS_97

AK15

VSS_98

AU36

VSS_99

CANTIGA ES_FCBGA1329

CANTIGA ES_FCBGA1329

VSS

VSS

V

SS_100
SS_101

V
V

SS_102

V

SS_103

V

SS_104

V

SS_105

V

SS_106

V

SS_107
SS_108

V

SS_109

V
V

SS_110
SS_111

V
V

SS_112

V

SS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
VSS_186
VSS_187
VSS_188
VSS_189
VSS_190
VSS_191
VSS_192
VSS_193
VSS_194
VSS_195
VSS_196
VSS_197
VSS_198
VSS_199

AM36
AE36
P36
L36
J36
F36
B36
AH35
AA35
Y35
U35
T35
BF34
AM34
AJ34
AF34
AE34
W34
B34
A34
BG33
BC33
BA33
AV33
AR33
AL33
AH33
AB33
P33
L33
H33
N32
K32
F32
C32
A31
AN29
T29
N29
K29
H29
F29
A29
BG28
BD28
BA28
AV28
AT28
AR28
AJ28
AG28
AE28
AB28
Y28
P28
K28
H28
F28
C28
BF26
AH26
AF26
AB26
AA26
C26
B26
BH25
BD25
BB25
AV25
AR25
AJ25
AC25
Y25
N25
L25
J25
G25
E25
BF24
AD12
AY24
AT24
AJ24
AH24
AF24
AB24
R24
L24
K24
J24
G24
F24
E24
BH23
AG23
Y23
B23
A23
AJ6

3

4J

4J

U

U

BG21

V

SS_199

L12

SS_200

V

AW21

V

SS_201

AU21

V

SS_202

AP21

V

SS_203

AN21

V

SS_204

AH21

V

SS_205

AF21

V

SS_206

AB21

SS_207

V

R21

SS_208

V

M21

V

SS_209

J21

SS_210

V

G21

V

SS_211

BC20

V

SS_212

BA20

VSS_213

AW20

VSS_214

AT20

VSS_215

AJ20

VSS_216

AG20

VSS_217

Y20

VSS_218

N20

VSS_219

K20

VSS_220

F20

VSS_221

C20

VSS_222

A20

VSS_223

BG19

VSS_224

A18

VSS_225

BG17

VSS_226

BC17

VSS_227

AW17

VSS_228

AT17

VSS_229

R17

VSS_230

M17

VSS_231

H17

VSS_232

C17

VSS_233

BA16

VSS_235

AU16

VSS_237

AN16

VSS_238

N16

VSS_239

K16

VSS_240

G16

VSS_241

E16

VSS_242

BG15

VSS_243

AC15

VSS_244

W15

VSS_245

A15

VSS_246

BG14

VSS_247

AA14

VSS_248

C14

VSS_249

BG13

VSS_250

BC13

VSS_251

BA13

VSS_252

AN13

VSS_255

AJ13

VSS_256

AE13

VSS_257

N13

VSS_258

L13

VSS_259

G13

VSS_260

E13

VSS_261

BF12

VSS_262

AV12

VSS_263

AT12

VSS_264

AM12

VSS_265

AA12

VSS_266

J12

VSS_267

A12

VSS_268

BD11

VSS_269

BB11

VSS_270

AY11

VSS_271

AN11

VSS_272

AH11

VSS_273

Y11

VSS_275

N11

VSS_276

G11

VSS_277

C11

VSS_278

BG10

VSS_279

AV10

VSS_280

AT10

VSS_281

AJ10

VSS_282

AE10

VSS_283

AA10

VSS_284

M10

VSS_285

BF9

VSS_286

BC9

VSS_287

AN9

VSS_288

AM9

VSS_289

AD9

VSS_290

G9

VSS_291

B9

VSS_292

BH8

VSS_293

BB8

VSS_294

AV8

VSS_295

AT8

VSS_296

CANTIGA ES_FCBGA1329

CANTIGA ES_FCBGA1329

VSS

VSS

VSS_NCTF_10

VSS NCTF

VSS NCTF

VSS_NCTF_11
VSS_NCTF_12
VSS_NCTF_13
VSS_NCTF_14
VSS_NCTF_15
VSS_NCTF_16

VSS SCB

VSS SCB

NC

NC

2

V

SS_297
SS_298

V
V

SS_299

V

SS_300

V

SS_301

V

SS_302

V

SS_303

V

SS_304
SS_305

V

SS_306

V
V

SS_307
SS_308

V
V

SS_309

V

SS_310
VSS_311
VSS_312
VSS_313
VSS_314
VSS_315
VSS_316
VSS_317
VSS_318
VSS_319
VSS_320
VSS_321
VSS_322
VSS_323
VSS_324
VSS_325

VSS_327
VSS_328
VSS_329
VSS_330
VSS_331
VSS_332
VSS_333
VSS_334
VSS_335
VSS_336
VSS_337
VSS_338
VSS_339
VSS_340
VSS_341
VSS_342
VSS_343
VSS_344
VSS_345
VSS_346
VSS_347
VSS_348
VSS_349
VSS_350

VSS_351
VSS_352
VSS_353
VSS_354

VSS_NCTF_1
VSS_NCTF_2
VSS_NCTF_3
VSS_NCTF_4
VSS_NCTF_5
VSS_NCTF_6
VSS_NCTF_7
VSS_NCTF_8
VSS_NCTF_9

VSS_SCB_1
VSS_SCB_2
VSS_SCB_3
VSS_SCB_4
VSS_SCB_5

NC_26
NC_27
NC_28
NC_29
NC_30
NC_31
NC_32
NC_33
NC_34
NC_35
NC_36
NC_37
NC_38
NC_39
NC_40
NC_41
NC_42

AH8
Y8
L8
E8
B8
AY7
AU7
AN7
AJ7
AE7
AA7
N7
J7
BG6
BD6
AV6
AT6
AM6
M6
C6
BA5
AH5
AD5
Y5
L5
J5
H5
F5
BE4

BC3
AV3
AL3
R3
P3
F3
BA2
AW2
AU2
AR2
AP2
AJ2
AH2
AF2
AE2
AD2
AC2
Y2
M2
K2
AM1
AA1
P1
H1

U24
U28
U25
U29

AF32
AB32
V32
AJ30
AM29
AF29
AB29
U26
U23
AL20
V20
AC19
AL17
AJ17
AA17
U17

BH48
BH1
A48
C1
A3

E1
D2
C3
B4
A5
A6
A43
A44
B45
C46
D47
B47
A46
F48
E48
C48
B48

1

5

4

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

2

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

Cantiga(7 of 7)

Cantiga(7 of 7)

Cantiga(7 of 7)

LA-5152P

LA-5152P

LA-5152P

16 51Monday, June 15, 2009

16 51Monday, June 15, 2009

16 51Monday, June 15, 2009

1

A00

A00

A00