Dell INSPIRON 5437, INSPIRON 3437 Schematics

5

4

3

2

1

D

Hadley15" Schematics Document

Haswell ULT

C

2013-06-28

REV : A00

B

DY : None Installed

B

UMA: UMA only installed OPS: Optimus solution installed. eDP: Support eDP Panel installed. LVDS: Support LVDS Panel installed.

X02

A

5

4

3

2

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

A3

Date: Sheet

Taipei Hsien 221, Taiwan, R.O.C.

Cover Page

Hadley 15"

1

1 101Friday, June 28, 201 3

of

1 101Friday, June 28, 201 3

of

1 101Friday, June 28, 201 3

of

5

4

3

2

1

Project code : 91.47L01.001

Hadly15 Block Diagram

PCB P/N : 12311-1 Revision : A00

eDP/

D

15.6" LCD FHD(1920 x 1080)

52

LVDS Option circuit

52, 53

HDMI CONN

54

USB 2.0

USB 3.0 / Power share

34

C

USB 3.0 CONN

34

Mini-Card

802.11a/b/g/n BT

58

Daughter board

USB 3.0 CONN

USB 3.0

B

USB 3.0 CONN

USB 3.0

mSATA

SATA3

Internal Digital MIC

A

Universal jack

29

2CH SPEAKER

5

eDP

eDP to LVDS

LVDS

Converter

Realtek RTD2136R

USB PowerShare

PERICOM PI5USB1457AZAE

PCI-E

USB 2.0

USB3.0 Redriver

TI SN65LVPE502RGER

USB3.0 Redriver

TI SN65LVPE502RGER

SATA repeater

TI SN75LVCP601

52

29

eDP

53

TMDS

USB 2.0

35

USB 3.0

USB 2.0

USB 3.0

USB 2.0

USB 3.0

USB 2.0

USB 3.0

SATA3

Intel CPU

Haswell ULT

15W/25W

Lynx Point-LP

8 USB 2.0/1.1 ports

2-4 USB 3.0 ports

High Definition Audio

4 SATA ports

8-12 PCIE ports

LPC I/F

ACPI 4.0a

Audio Codec

Realtek ALC3223

HDA

27

www.schematic-x.blogspot.com

4

SMBus

Flash ROM

3

DDR3L Channel A

DDR3L Channel B

PCI-E x4

USB 2.0

SMBUS

INT1

SATA3

PCI-E

LPC

SPI

8MB

25

GPU

25W

N14P-GT

Touch Screen

2M 720P Camera

SATA repeater

TI SN75LVCP601

LAN+Card reader

(10/100/1000M)

Realtek

RTL8411B

LPC debug port

KBC

Nuvoton NPCE985PA0DX

PS2

Touch Pad

62

DDR3L 1600MHz

73~77

52

30

65

24

Backlight Int. KB

Slot A

Slot B

GDDR5 Ch A

GDDR5 Ch B

SATA3

SMBus

62

2

12

13

VRAM(GDDR5)

128M x 16 x4(1GB)

VRAM(GDDR5)

128M x 16 x 4(1GB)

FFS

ST DE351DL

RJ45

67

HDD

31

INT2

56

MMI Card Connector (SD/SDHC/SDXC/ SD-UHS/MS/MS-Pro)

Thermal

Nuvoton NCT7718W

DC Fan Contrroller

ANPEC APL5606AKI

Title

Size Document Number Rev

Custom

Date: Sheet

33

26

DC Fan Module

26

Block Diagram

Hadley 15"

CHARGER

BQ24717

AD+ BT+ DCBATOUT

OUTPUTSINPUTS

SYSTEM DC/DC

TPS51225

INPUTS OUTPUTS

DCBATOUT

INPUTS OUTPUTS

DCBATOUT

5V_AUX_S5 3D3V_AUX_S5 5V_CHARGER 3D3V_PWR

CPU DC/DC TPS51622

VCC_CORE

46~47

SYSTEM DC/DC

TPS51363

DCBATOUT

OUTPUTSINPUTS

1D05V_S0

SYSTEM DC/DC

TPS51216

INPUTS

DCBATOUT

OUTPUTS

1D35V_S3 0D675V_S0

SYSTEM DC/DC

NCP81172

INPUTS

DCBATOUT

5V_S5 3D3V_S5

3D3V_S0 1D05V_S0

1D35V_S3 1D35V_VGA_S0

OUTPUTS

VGA_CORE

Switches

OUTPUTSINPUTS

5V_S0 3D3V_S0

3D3V_VGA_S0 1D05V_VGA_S0

36, 83

LDO

TLV70215DBVR

3D3V_S5

OUTPUTSINPUTS

PCB LAYER

L1 : TOP

L2 : GND

L3 : Signal

L4 : Signal

L5 : VCC

L6 : Signal

L7 : GND

L8 : Bottom

26

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

of

2 101Friday, June 28, 2013

of

2 101Friday, June 28, 2013

of

2 101Friday, June 28, 2013

1

44

D

45

48

49

C

82

51

B

A

X02

5

4

3

2

1

D

C

D

C

(Blanking)

B

X02

A

5

4

3

2

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

A3

Date: Sheet

(Reserved)

Hadley 15"

Taipei Hsien 221, Taiwan, R.O.C.

3 101Friday, June 28, 201 3

of

3 101Friday, June 28, 201 3

of

3 101Friday, June 28, 201 3

1

of

SSID = CPU

5

4

3

2

1

D

1D05S_V CCST

1

R401

62R2J-GP

H_PROCH OT#[24,42,44,4 6]

C

R407 200R2F-L -GP

1

R408 120R2F-G P

1

R409 100R2F-L 1-GP-U

1

Layout Note:

Design Guidelin e: SM_RCOMP keep r outing length less than 500 m ils.

Layout Note:

Impedance contr ol:50 ohm

2

SM_RCOM P_0

SM_RCOM P_1

SM_RCOM P_2

TP401

TP402

H_PECI[24]

2

1

TP403

DDR_PG_ CTRL[12]

R403

56R2J-4-G P

2

SKTOCC#

1

H_CATER R#

1

H_PROCH OT#_R

2

H_CPUPW RGD

1

R405

1

10KR2J-3 -GP

SM_RCOM P_0

SM_RCOM P_1

SM_RCOM P_2

SM_DRAM RST#

DDR_PG_ CTRL

B

D61

K61

N62

K63

C61

AU60

AV60

AU61

AV15

AV61

CPU1B

PROC_DETECT#

CATERR#

PECI

PROCHOT#

PROCPWRGD

SM_RCOMP0

SM_RCOMP1

SM_RCOMP2

SM_DRAMRST#

SM_PG_CNTL1

HASW ELL-6-GP

SM_DRAM RST#

MISC

THERMAL

PWR

DDR3L

HSW_ULT_DDR3L

1D35V_S 3

1

R410

470R2J-2 -GP

2

R404

1

0R0402-P AD-2-GP

JTAG

2

2 OF 19

XDP_PRD Y#

J62

PRDY#

PREQ#

PROC_TCK

PROC_TMS

PROC_TRST#

PROC_TDI

PROC_TDO

BPM#0

BPM#1

BPM#2

BPM#3

BPM#4

BPM#5

BPM#6

BPM#7

Layout Note:

Place close to DIMM

XDP_PRE Q#

K62

XDP_TCL K

E60

XDP_TMS

E61

XDP_TRS T#

E59

XDP_TDI

F63

XDP_TDO

F62

XDP_BPM 0

J60

XDP_BPM 1

H60

XDP_BPM 2

H61

XDP_BPM 3

H62

XDP_BPM 4

K59

XDP_BPM 5

H63

XDP_BPM 6

K60

XDP_BPM 7

J61

DDR3_DR AMRST# [12,13]

XDP_PRD Y# [96]

XDP_PRE Q# [96]

XDP_BPM [7:0]

XDP_BPM [7:0] [96]

XDP_TDO

XDP_TDI

XDP_TMS

R402 51R2J-2-G P

XDP_TRS T#

R406 51R2J-2-G P

XDP_TCL K

RN401

1

2

3

XDP

4

SRN51J-1 -GP

XDP

1

1D05S_V CCST

8

7

6

5

2

D

C

B

X01 change to short pad

A

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU (THERMAL/CLOCK)

Size Document N umber Rev

Date: Sheet

CPU (THERMAL/CLOCK)

A3

Taipei Hsien 221, Taiwan, R.O.C.

Hadley 15"

4 101Friday, June 28, 201 3

of

4 101Friday, June 28, 201 3

of

4 101Friday, June 28, 201 3

of

X02

A

SSID = CPU

M_A_DQ[63:0][12]

D

C

5

M_A_DQ[63:0]

M_A_DQ0

M_A_DQ1

M_A_DQ2

M_A_DQ3

M_A_DQ4

M_A_DQ5

M_A_DQ6

M_A_DQ7

M_A_DQ8

M_A_DQ9

M_A_DQ10

M_A_DQ11

M_A_DQ12

M_A_DQ13

M_A_DQ14

M_A_DQ15

M_A_DQ16

M_A_DQ17

M_A_DQ18

M_A_DQ19

M_A_DQ20

M_A_DQ21

M_A_DQ22

M_A_DQ23

M_A_DQ24

M_A_DQ25

M_A_DQ26

M_A_DQ27

M_A_DQ28

M_A_DQ29

M_A_DQ30

M_A_DQ31

M_A_DQ32

M_A_DQ33

M_A_DQ34

M_A_DQ35

M_A_DQ36

M_A_DQ37

M_A_DQ38

M_A_DQ39

M_A_DQ40

M_A_DQ41

M_A_DQ42

M_A_DQ43

M_A_DQ44

M_A_DQ45

M_A_DQ46

M_A_DQ47

M_A_DQ48

M_A_DQ49

M_A_DQ50

M_A_DQ51

M_A_DQ52

M_A_DQ53

M_A_DQ54

M_A_DQ55

M_A_DQ56

M_A_DQ57

M_A_DQ58

M_A_DQ59

M_A_DQ60

M_A_DQ61

M_A_DQ62

M_A_DQ63

AH63

AH62

AK63

AK62

AH61

AH60

AK61

AK60

AM63

AM62

AP63

AP62

AM61

AM60

AP61

AP60

AP58

AR58

AM57

AK57

AL58

AK58

AR57

AN57

AP55

AR55

AM54

AK54

AL55

AK55

AR54

AN54

AY58

AW58

AY56

AW56

AV58

AU58

AV56

AU56

AY54

AW54

AY52

AW52

AV54

AU54

AV52

AU52

AK40

AK42

AM43

AM45

AK45

AK43

AM40

AM42

AM46

AK46

AM49

AK49

AM48

AK48

AM51

AK51

CPU1C

SA_DQ0

SA_DQ1

SA_DQ2

SA_DQ3

SA_DQ4

SA_DQ5

SA_DQ6

SA_DQ7

SA_DQ8

SA_DQ9

SA_DQ10

SA_DQ11

SA_DQ12

SA_DQ13

SA_DQ14

SA_DQ15

SA_DQ16

SA_DQ17

SA_DQ18

SA_DQ19

SA_DQ20

SA_DQ21

SA_DQ22

SA_DQ23

SA_DQ24

SA_DQ25

SA_DQ26

SA_DQ27

SA_DQ28

SA_DQ29

SA_DQ30

SA_DQ31

SA_DQ32

SA_DQ33

SA_DQ34

SA_DQ35

SA_DQ36

SA_DQ37

SA_DQ38

SA_DQ39

SA_DQ40

SA_DQ41

SA_DQ42

SA_DQ43

SA_DQ44

SA_DQ45

SA_DQ46

SA_DQ47

SA_DQ48

SA_DQ49

SA_DQ50

SA_DQ51

SA_DQ52

SA_DQ53

SA_DQ54

SA_DQ55

SA_DQ56

SA_DQ57

SA_DQ58

SA_DQ59

SA_DQ60

SA_DQ61

SA_DQ62

SA_DQ63

HSW_ULT_DDR3L

DDR CHANNEL A

TP_M_B_DIMB_ODT0

M_B_A0

M_B_A1

M_B_A2

M_B_A3

M_B_A4

M_B_A5

M_B_A6

M_B_A7

M_B_A8

M_B_A9

M_B_A10

M_B_A11

M_B_A12

M_B_A13

M_B_A14

M_B_A15

M_B_DQS#0

M_B_DQS#1

M_B_DQS#2

M_B_DQS#3

M_B_DQS#4

M_B_DQS#5

M_B_DQS#6

M_B_DQS#7

M_B_DQS0

M_B_DQS1

M_B_DQS2

M_B_DQS3

M_B_DQS4

M_B_DQS5

M_B_DQS6

M_B_DQS7

1

M_B_DIMB_CLK_DDR#0 [13]

M_B_DIMB_CLK_DDR0 [13]

M_B_DIMB_CLK_DDR#1 [13]

M_B_DIMB_CLK_DDR1 [13]

M_B_DIMB_CKE0 [13]

M_B_DIMB_CKE1 [13]

M_B_DIMB_CS#0 [13]

M_B_DIMB_CS#1 [13]

M_B_RAS# [13]

M_B_WE# [13]

M_B_CAS# [13]

M_B_BS0 [13]

M_B_BS1 [13]

M_B_BS2 [13]

M_B_A[15:0] [13]

M_B_DQS#[7:0] [13]

M_B_DQS[7:0] [13]

D

TP503

1

C

CPU1D

SB_DQ0

SB_DQ1

SB_DQ2

SB_DQ3

SB_DQ4

SB_DQ5

SB_DQ6

SB_DQ7

SB_DQ8

SB_DQ9

SB_DQ10

SB_DQ11

SB_DQ12

SB_DQ13

SB_DQ14

SB_DQ15

SB_DQ16

SB_DQ17

SB_DQ18

SB_DQ19

SB_DQ20

SB_DQ21

SB_DQ22

SB_DQ23

SB_DQ24

SB_DQ25

SB_DQ26

SB_DQ27

SB_DQ28

SB_DQ29

SB_DQ30

SB_DQ31

SB_DQ32

SB_DQ33

SB_DQ34

SB_DQ35

SB_DQ36

SB_DQ37

SB_DQ38

SB_DQ39

SB_DQ40

SB_DQ41

SB_DQ42

SB_DQ43

SB_DQ44

SB_DQ45

SB_DQ46

SB_DQ47

SB_DQ48

SB_DQ49

SB_DQ50

SB_DQ51

SB_DQ52

SB_DQ53

SB_DQ54

SB_DQ55

SB_DQ56

SB_DQ57

SB_DQ58

SB_DQ59

SB_DQ60

SB_DQ61

SB_DQ62

SB_DQ63

2

HSW_ULT_DDR3L

DDR CHANNEL B

4 OF 19

SB_CK#0

SB_CK0

SB_CK#1

SB_CK1

SB_CKE0

SB_CKE1

SB_CKE2

SB_CKE3

SB_CS#0

SB_CS#1

SB_ODT0

SB_RAS#

SB_WE#

SB_CAS#

SB_BA0

SB_BA1

SB_BA2

SB_MA0

SB_MA1

SB_MA2

SB_MA3

SB_MA4

SB_MA5

SB_MA6

SB_MA7

SB_MA8

SB_MA9

SB_MA10

SB_MA11

SB_MA12

SB_MA13

SB_MA14

SB_MA15

SB_DQSN0

SB_DQSN1

SB_DQSN2

SB_DQSN3

SB_DQSN4

SB_DQSN5

SB_DQSN6

SB_DQSN7

SB_DQSP0

SB_DQSP1

SB_DQSP2

SB_DQSP3

SB_DQSP4

SB_DQSP5

SB_DQSP6

SB_DQSP7

AM38

AN38

AK38

AL38

AY49

AU50

AW49

AV50

AM32

AK32

AL32

AM35

AK35

AM33

AL35

AM36

AU49

AP40

AR40

AP42

AR42

AR45

AP45

AW46

AY46

AY47

AU46

AK36

AV47

AU47

AK33

AR46

AP46

AW30

AV26

AN28

AN25

AW22

AV18

AN21

AN18

AV30

AW26

AM28

AM25

AV22

AW18

AM21

AM18

4

3 OF 19

SA_CLK#0

SA_CLK0

SA_CLK#1

SA_CLK1

SA_CKE0

SA_CKE1

SA_CKE2

SA_CKE3

SA_CS#0

SA_CS#1

SA_ODT0

SA_RAS#

SA_WE#

SA_CAS#

SA_BA0

SA_BA1

SA_BA2

SA_MA0

SA_MA1

SA_MA2

SA_MA3

SA_MA4

SA_MA5

SA_MA6

SA_MA7

SA_MA8

SA_MA9

SA_MA10

SA_MA11

SA_MA12

SA_MA13

SA_MA14

SA_MA15

SA_DQSN0

SA_DQSN1

SA_DQSN2

SA_DQSN3

SA_DQSN4

SA_DQSN5

SA_DQSN6

SA_DQSN7

SA_DQSP0

SA_DQSP1

SA_DQSP2

SA_DQSP3

SA_DQSP4

SA_DQSP5

SA_DQSP6

SA_DQSP7

SM_VREF_CA

SM_VREF_DQ0

SM_VREF_DQ1

AU37

AV37

AW36

AY36

AU43

AW43

AY42

AY43

AP33

AR32

AP32

AY34

AW34

AU34

AU35

AV35

AY41

AU36

AY37

AR38

AP36

AU39

AR36

AV40

AW39

AY39

AU40

AP35

AW41

AU41

AR35

AV42

AU42

AJ61

AN62

AM58

AM55

AV57

AV53

AL43

AL48

AJ62

AN61

AN58

AN55

AW57

AW53

AL42

AL49

AP49

AR51

AP51

+V_SM_VREF_CNT

M_A_A0

M_A_A1

M_A_A2

M_A_A3

M_A_A4

M_A_A5

M_A_A6

M_A_A7

M_A_A8

M_A_A9

M_A_A10

M_A_A11

M_A_A12

M_A_A13

M_A_A14

M_A_A15

M_A_DQS#0

M_A_DQS#1

M_A_DQS#2

M_A_DQS#3

M_A_DQS#4

M_A_DQS#5

M_A_DQS#6

M_A_DQS#7

M_A_DQS0

M_A_DQS1

M_A_DQS2

M_A_DQS3

M_A_DQS4

M_A_DQS5

M_A_DQS6

M_A_DQS7

M_A_DIMA_CLK_DDR#0 [12]

M_A_DIMA_CLK_DDR0 [12]

M_A_DIMA_CLK_DDR#1 [12]

M_A_DIMA_CLK_DDR1 [12]

M_A_DIMA_CKE0 [12]

M_A_DIMA_CKE1 [12]

M_A_DIMA_CS#0 [12]

M_A_DIMA_CS#1 [12]

TP_M_A_DIMA_ODT0

M_A_RAS# [12]

M_A_WE# [12]

M_A_CAS# [12]

M_A_BS0 [12]

M_A_BS1 [12]

M_A_BS2 [12]

3

TP501

1

M_A_A[15:0] [12]

M_A_DQS#[7:0] [12]

M_A_DQS[7:0] [12]

+V_SM_VREF_CNT [ 37]

DDR_WR_VREF01 [12]

DDR_WR_VREF02 [13]

M_B_DQ[63:0][13]

M_B_DQ[63:0]

M_B_DQ0

M_B_DQ1

M_B_DQ2

M_B_DQ3

M_B_DQ4

M_B_DQ5

M_B_DQ6

M_B_DQ7

M_B_DQ8

M_B_DQ9

M_B_DQ10

M_B_DQ11

M_B_DQ12

M_B_DQ13

M_B_DQ14

M_B_DQ15

M_B_DQ16

M_B_DQ17

M_B_DQ18

M_B_DQ19

M_B_DQ20

M_B_DQ21

M_B_DQ22

M_B_DQ23

M_B_DQ24

M_B_DQ25

M_B_DQ26

M_B_DQ27

M_B_DQ28

M_B_DQ29

M_B_DQ30

M_B_DQ31

M_B_DQ32

M_B_DQ33

M_B_DQ34

M_B_DQ35

M_B_DQ36

M_B_DQ37

M_B_DQ38

M_B_DQ39

M_B_DQ40

M_B_DQ41

M_B_DQ42

M_B_DQ43

M_B_DQ44

M_B_DQ45

M_B_DQ46

M_B_DQ47

M_B_DQ48

M_B_DQ49

M_B_DQ50

M_B_DQ51

M_B_DQ52

M_B_DQ53

M_B_DQ54

M_B_DQ55

M_B_DQ56

M_B_DQ57

M_B_DQ58

M_B_DQ59

M_B_DQ60

M_B_DQ61

M_B_DQ62

M_B_DQ63

AY31

AW31

AY29

AW29

AV31

AU31

AV29

AU29

AY27

AW27

AY25

AW25

AV27

AU27

AV25

AU25

AM29

AK29

AL28

AK28

AR29

AN29

AR28

AP28

AN26

AR26

AR25

AP25

AK26

AM26

AK25

AL25

AY23

AW23

AY21

AW21

AV23

AU23

AV21

AU21

AY19

AW19

AY17

AW17

AV19

AU19

AV17

AU17

AR21

AR22

AL21

AM22

AN22

AP21

AK21

AK22

AN20

AR20

AK18

AL18

AK20

AM20

AR18

AP18

X02

B

A

B

HASWELL-6-GP

A

5

4

3

HASWELL-6-GP

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

Taipei Hsien 221, Taiwan, R.O.C.

CPU (DDR)

Hadley 15"

1

of

5 101Friday, June 28, 2013

of

5 101Friday, June 28, 2013

of

5 101Friday, June 28, 2013

SSID = CPU

D

C

3

RSVD_TP#AV63

RSVD_TP#AU63

PROC_OPI_RCOMP

19 OF 19

RSVD_TP#C63

RSVD_TP#C62

RSVD#B43

RSVD_TP#A51

RSVD_TP#B51

RSVD_TP#L60

RSVD#N60

RSVD#W23

RSVD#Y22

RSVD#AV62

RSVD#D58

VSS

RSVD#P20

RSVD#R20

AV63

AU63

C63

C62

EDP_SPA RE

B43

A51

B51

L60

N60

W23

PROC_OP I_COMP3

Y22

PROC_OP I_COMP

AY15

AV62

D58

P22

N21

HVM_CLK #

P20

HVM_CLK

R20

1

TP605

R606 49D9R2F -GP

R602 49D9R2F -GP

1

TP619

1

TP620

2

R601

49D9R2F -GP

2

4

CFG0

CFG1

CFG2

CFG3

CFG4

CFG5

CFG6

CFG7

CFG8

CFG9

CFG10

CFG11

CFG12

CFG13

CFG14

CFG15

CFG16

CFG18

CFG17

CFG19

CFG_RCO MP

TD_IREF

AC60

AC62

AC63

AA63

AA60

Y62

Y61

Y60

V62

V61

V60

U60

T63

T62

T61

T60

AA62

U63

AA61

U62

V63

H18

B12

A5

E1

D1

J20

CPU1S

CFG0

CFG1

CFG2

CFG3

CFG4

CFG5

CFG6

CFG7

CFG8

CFG9

CFG10

CFG11

CFG12

CFG13

CFG14

CFG15

CFG16

CFG18

CFG17

CFG19

CFG_RCOMP

RSVD#A5

RSVD#E1

RSVD#D1

RSVD#J20

RSVD#H18

TD_IREF

HSW_ULT_DDR3L

RESERVED

5

CFG[19:0][96]

CFG[19:0]

1

R603

8K2R2F-1 -GP

2

1

DY

2

1

Layout Note:

1.Referenced "continuous" VSS plane only.

2.Avoid routing next to clock pins or noisy signals.

3.Trace width: 12~15mil

4.Isolation Spacing: 12mil

5.Max length: 500mil

1

D

C

CFG3

CFG4

B

A

5

4

DY

1

2

1

2

R604

1KR2J-1-G P

R605

1KR2J-1-G P

PHYSICAL_DEBUG_ ENABLED (DFX P RIVACY)

0 : ENABLED

CFG[3]

SET DFX ENABLED BIT IN DEBUG INTERFACE MSR

1 : DISABLED

DISPLAY PORT PR ESENCE STRAP

0 : ENABLED

AN EXTERNAL DIS PLAY PORT DEVI CE IS CONNECTED TO THE EMBEDD ED DISPLAY PORT

CFG[4]

1 : DISABLED

NO PHYSICAL DIS PLAY PORT ATTA CHED TO EMBEDDE D DISPLAY PORT

3

B

X02

A

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

A3

Date: Sheet

2

Date: Sheet

Taipei Hsien 221, Taiwan, R.O.C.

CPU (RESERVED)

Hadley 15"

6 101Friday, June 28, 201 3

1

of

5

SSID = CPU

4

3

2

1

D

HSW_ULT_DDR3L

CPU1L

L59

AH26

AJ31

AJ33

AJ37

AN33

AP43

AR48

AY35

AY40

AY44

AY50

F59

N58

AC58

E63

AB23

A59

E20

AD23

AA23

AE59

L62

N63

L63

B59

F60

C59

D63

H59

P62

P60

P61

N59

N61

T59

AD60

AD59

AA59

AE60

AC59

AG58

U59

V59

AC22

AE22

AE23

AB57

AD57

AG57

C24

C28

C32

J58

RSVD#L59

RSVD#J58

VDDQ

VCC

RSVD#N58

RSVD#AC58

VCC_SENSE

RSVD#AB23

VCCIO_OUT

VCCIOA_OUT

RSVD#AD23

RSVD#AA23

RSVD#AE59

VIDALERT#

VIDSCLK

VIDSOUT

VCCST_PWRGD

VR_EN

VR_READY

VSS

PWR_DEBUG#

VSS

RSVD_TP#P60

RSVD_TP#P61

RSVD_TP#N59

RSVD_TP#N61

RSVD#T59

RSVD#AD60

RSVD#AD59

RSVD#AA59

RSVD#AE60

RSVD#AC59

RSVD#AG58

RSVD#U59

RSVD#V59

VCCST

VCC

HASW ELL-6-GP

1D35V_S 3

1D05S_V CCST

R703 75R2F-2-G P

R704 130R2F-1 -GP

C

1D05V_V TT_PWRGD[36,48]

EC701

SCD1U25V2KX-GP

1

DY

2

B

2

1

2

1

VR_SVID_A LERT#

H_CPU_S VIDDAT

SCD1U10 V2KX-5GP

U701

1

NC#1

2

A

DY

3

GND

74LVC1G 07GW-GP

73.01G07.0HG

1

R707

100KR2F -L1-GP

VCC

2

Y

C702

5

4

1

2

3D3V_S5

1

DY

2

R709

51KR2J-1 -GP

1D05S_V CCST

1

R706

10KR2J-3 -GP

DY

2

H_VCCST _PWRGD

Layout Note:

1. Place close to CPU

2. VCC_SENSE/ VSS_SENSE impedance=50 ohm

3. Lwngth match<25mil

VR_SVID_A LERT#[46]

H_CPU_S VIDCLK[46]

H_VR_EN ABLE[46]

H_CPU_S VIDDAT[46]

C705

SCD1U25 V2KX-GP

1D05S_V CCST

100R2F-L 1-GP-U

VCC_SEN SE[46]

IMVP_PW RGD_R

2

1

DY

R705 150R2J-L 1-GP-U

1

VCC_COR E

R702

1

2

1

2

TP701

R701

43R2J-GP

1

DY

VCC_COR E

TP_VCCIO_ OUT

1

+VCCIOA_O UT

H_CPU_S VIDALRT#

2

H_CPU_S VIDCLK

H_CPU_S VIDDAT

H_VCCST _PWRGD

10KR2J-3 -GP

2

R710

PWR_ DEBUG

1D05S_V CCST

VCC_COR E

HSW_ULT_DDR3L

HSW ULT POWER

12 OF 19

VCC

C36

C40

C44

C48

C52

C56

E23

E25

E27

E29

E31

E33

E35

E37

E39

E41

E43

E45

E47

E49

E51

E53

E55

E57

F24

F28

F32

F36

F40

F44

F48

F52

F56

G23

G25

G27

G29

G31

G33

G35

G37

G39

G41

G43

G45

G47

G49

G51

G53

G55

G57

H23

J23

K23

K57

L22

M23

M57

P57

U57

W57

VCC_COR E

D

C

B

A00 0619

H_VR_EN ABLE

1

PR715

PR714

2

1D05V_S 0

0R0805-P AD-2-GP-U

A

5

1D05S_V CCST

2

1

R711

DY

1

2

C703

C701

DY

2

SC1U6D3V2KX-GP

SC22U6D3V5MX-2GP

4

IMVP_PW RGD[24,46]

1

R713

100KR2F -L1-GP

47KR2F-G P

2

R712

IMVP_PW RGD_L

C704

SCD1U25V2KX-GP

1

2

DY

2

3

1

0R2J-2-GP

PD701

A

DY

BAT54LP S-7-GP

K

PR715

DY

10KR2F-2 -GP

2

IMVP_PW RGD_R

1

PC706

DY

SCD047U 10V2KX-2GP

2

X02

A

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

A3

Date: Sheet

2

Date: Sheet

Taipei Hsien 221, Taiwan, R.O.C.

CPU (VCC_CORE)

Hadley 15"

7 101Friday, June 28, 201 3

1

of

SSID = CPU

5

4

3

2

1

D

C

HDMI

D

HSW_ULT_DDR3L

X01 remove

HDMI_DATA 2#[54]

HDMI_DATA 2[54]

HDMI_DATA 1#[54]

HDMI_DATA 1[54]

HDMI_DATA 0#[54]

HDMI_DATA 0[54]

HDMI_CLK#[54]

HDMI_CLK[54]

CPU1A

C54

C55

B58

C58

B55

A55

A57

B57

C51

C50

C53

B54

C49

B50

A53

B53

HASW ELL-6-GP

DDI1_TXN0

DDI1_TXP0

DDI1_TXN1

DDI1_TXP1

DDI1_TXN2

DDI1_TXP2

DDI1_TXN3

DDI1_TXP3

DDI2_TXN0

DDI2_TXP0

DDI2_TXN1

DDI2_TXP1

DDI2_TXN2

DDI2_TXP2

DDI2_TXN3

DDI2_TXP3

HSW_ULT_DDR3L

EDPDDI

1 OF 19

EDP_TXN0

EDP_TXP0

EDP_TXN1

EDP_TXP1

EDP_TXN2

EDP_TXP2

EDP_TXN3

EDP_TXP3

EDP_AUXN

EDP_AUXP

EDP_RCOMP

EDP_DISP_UTIL

C45

B46

A47

B47

C47

C46

A49

B49

A45

B45

D20

A43

EDP_TX0 _DN [53]

EDP_TX0 _DP [53]

EDP_TX1 _DN [53]

EDP_TX1 _DP [53]

EDP_AUX _DN [5 3]

EDP_AUX _DP [53]

EDP_COM P

EDP_BRIGH TNESS

R801

24D9R2F -L-GP

1

TP801

+VCCIOA_O UT

Design Guidelin e:

1

EDP_COMP keep r outing length max 100 mils. Trace Width:20 mils.

2

C

X02

B

A

B

A

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

A3

Date: Sheet

Taipei Hsien 221, Taiwan, R.O.C.

CPU (DDI/EDP)

Hadley 15"

8 101Friday, June 28, 201 3

of

5

SSID = CPU

4

3

2

1

D

HSW_ULT_DDR3L

VSS

HSW_ULT_DDR3L

CPU1P

D33

D34

D35

D37

D38

D39

D41

D42

D43

D45

D46

D47

D49

D5

D50

D51

D53

D54

D55

D57

C

B

D59

D62

D8

E11

E17

F20

F26

F30

F34

F38

F42

F46

F50

F54

F58

F61

G18

G22

G3

G5

G6

G8

H13

HASW ELL-6-GP

16 OF 19

VSS

VSS_SENSE

VSS

H17

H57

J10

J22

J59

J63

K1

K12

L13

L15

L17

L18

L20

L58

L61

L7

M22

N10

N3

P59

P63

R10

R22

R8

T1

T58

U20

U22

U61

U9

V10

V3

V7

W20

W22

Y10

Y59

Y63

V58

AH46

V23

E62

AH16

VSS_SEN SE

VSS_SEN SE [46]

1

R901

2

100R2F-L1-GP-U

Layout Note:

1. Place close to CPU

2. VCC_SENSE/ VSS_SENSE impedance=50 ohm

3. Lwngth match<25mil

D

C

B

X02

A

5

4

3

2

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU (VSS)

Size Document N umber Rev

A3

Date: Sheet

CPU (VSS)

Taipei Hsien 221, Taiwan, R.O.C.

Hadley 15"

9 101Friday, June 28, 201 3

of

9 101Friday, June 28, 201 3

of

9 101Friday, June 28, 201 3

1

of

SSID = CPU

1D35V_S 3

D

5

C1006

C1001

SC10U6D3V3MX-GP

C1001

SC10U6D3V3MX-GP

C1002

SC10U6D3V3MX-GP

C1002

SC10U6D3V3MX-GP

C1003

SC10U6D3V3MX-GP

C1003

SC10U6D3V3MX-GP

C1004

SC10U6D3V3MX-GP

C1004

1

2

SC10U6D3V3MX-GP

1

2

C1006

C1005

SC10U6D3V3MX-GP

C1005

SC10U6D3V3MX-GP

1

DY

2

4

SC10U6D3V3MX-GP

Layout Note:

As close to CPU as possible

3

2

1

D

1

C1017

C1018

DY

2

SC2D2U6D3V2MX-GP

C

B

DY

2

SC2D2U6D3V2MX-GP

1

2

C1020

C1019

DY

2

SC2D2U6D3V2MX-GP

Layout Note:

Direct tie to CPU VccIn/Vss balls

C

B

X02

A

5

4

3

2

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

A3

Date: Sheet

Taipei Hsien 221, Taiwan, R.O.C.

CPU(Power CAP1)

Hadley 15"

10 10 1Friday, June 28, 201 3

1

of

5

SSID = CPU

4

3

2

1

D

MAX: 1.92A

1.838A 41mA 42mA

1D05V_H SIO

2

1

R1101

0R0805-P AD-2-GP-U

CAP need close to pin K9 L10

C

1D05V_S 0

R1102

0R0603-P AD-2-GP-U

2

1

CAP need close to pin AA21

+V1.05DX _MODPHY_PCH

C1102

SC1U6D3V2KX-GP

C1102

SC1U6D3V2KX-GP

1

2

+V1.05S_ APLLOPI

1

2

C1101

SC1U6D3V2KX-GP

C1101

SC1U6D3V2KX-GP

1D05V_H SIO

L1101 IND-2 D2UH-196-GP

1

68.2R21D.10R

2

C1103

1

2

CAP need close to pin B18 CAP need close to pin B11

+V1.05S_ APLLOPI

C1109

SC1U6D3V2KX-GP

C1109

SC1U6D3V2KX-GP

C1110

1

2

C1124

SC10U6D3V3MX-GP

C1124

DY

SC10U6D3V3MX-GP

1

2

SC10U6D3V3MX-GP

1205 Add

3D3V_S5 _PCH

2

1

R1103

0R0603-P AD-2-GP-U

CAP need close to pin AC9

+V1.05S_ AUSB3PLL

C1104

SC10U6D3V3MX-GP

C1104

SC10U6D3V3MX-GP

SC1U6D3V2KX-GP

1

2

+V3.3A_P SUS

+V1.05S_ AUSB3PLL

C1123

SC10U6D3V3MX-GP

C1123

SC10U6D3V3MX-GP

1

DY

2

1205 Add

C1108

SC10U6D3V3MX-GP

C1108

SC10U6D3V3MX-GP

1

2

1D05V_H SIO

L1102 IND-2 D2UH-196-GP

68.2R21D.10R

2

1

2

200mA62mA57mA

1D05V_S 0

L1103 IND-2 D2UH-196-GP

1

68.2R21D.10R

2

C1111

1

2

CAP need close to pin J18

C1105

SC1U6D3V2KX-GP

C1105

SC1U6D3V2KX-GP

1

DY

2

+V1.05S_ ASATA3PLL

1

2

+V1.05S_ AXCK_DCB

C1112

SC10U6D3V3MX-GP

C1112

SC10U6D3V3MX-GP

C1106

SC10U6D3V3MX-GP

C1106

SC10U6D3V3MX-GP

1

DY

2

+V1.05S_ AXCK_DCB

1

DY

2

C1107

C1125

SC10U6D3V3MX-GP

C1125

SC10U6D3V3MX-GP

1205 Add

SC10U6D3V3MX-GP

C

31mA 658mA 1.632A 1mA

1D05V_S 0

IND-2D2UH-1 96-GP

L1104

1

68.2R21D.10R

B

+V1.05S_ AXCK_LCPLL

2

C1114

C1113

SC1U6D3V2KX-GP

C1113

SC1U6D3V2KX-GP

1

DY

2

1D05V_S 0

2

1

R1104

0R0603-P AD-2-GP-U

SC10U6D3V3MX-GP

0R0603-P AD-2-GP-U

C1115

+1.05M_A SW

SC22U6D3V5MX-2GP

C1116

SC1U6D3V2KX-GP

C1116

SC1U6D3V2KX-GP

1

DY

2

1D05V_S 0

C1118

SC1U6D3V2KX-GP

C1118

SC1U6D3V2KX-GP

C1117

SC1U6D3V2KX-GP

C1117

1

2

SC1U6D3V2KX-GP

1

2

C1119

SC10U6D3V3MX-GP

C1119

1

2

SC10U6D3V3MX-GP

1

DY

2

DY

RTC_AUX _S5

C1121

SCD1U10V2KX-5GP

C1121

SCD1U10V2KX-5GP

C1120

SCD1U10V2KX-5GP

C1120

SCD1U10V2KX-5GP

1

2

C1122

SC1U6D3V2KX-GP

C1122

1

2

SC1U6D3V2KX-GP

1

2

B

CAP need close to pin A20 CAP need close to pin AE9

A

5

4

CAP need close to pin AE8 J11

3

CAP need close to pin AG10

Title

Size Document N umber Rev

A3

Date: Sheet

2

Date: Sheet

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

CPU(Power CAP2)

Hadley 15"

11 10 1Friday, June 28, 201 3

1

A

X02

of

X02

SSID = MEMORY

D

M_VREF_CA_DIMMA

1

DY

2

C1201

SCD1U10V2KX-5GP

C

M_VREF_DQ_DIMMA

0D675V_S0

B

A

SCD1U10V2KX-5GP

1

DY

2

C1204

SCD1U10V2KX-5GP

1

C1215

C1214

DY

2

SC1U6D3V2KX-GP

Layout Note:

All VREF traces should have width=20mil; spacing=20 mil

5

C1217

SCD1U10V2KX-5GP

C1217

SCD1U10V2KX-5GP

DY

M_A_A0

M_A_A1

M_A_A2

M_A_A3

M_A_A4

M_A_A5

M_A_A6

M_A_A7

M_A_A8

M_A_A9

M_A_A10

M_A_A11

M_A_A12

M_A_A13

M_A_A14

M_A_A15

M_A_DQ13

M_A_DQ8

M_A_DQ14

M_A_DQ10

M_A_DQ9

M_A_DQ12

M_A_DQ15

M_A_DQ11

M_A_DQ29

M_A_DQ28

M_A_DQ30

M_A_DQ31

M_A_DQ25

M_A_DQ24

M_A_DQ27

M_A_DQ26

M_A_DQ44

M_A_DQ41

M_A_DQ43

M_A_DQ47

M_A_DQ45

M_A_DQ40

M_A_DQ42

M_A_DQ46

M_A_DQ51

M_A_DQ50

M_A_DQ49

M_A_DQ48

M_A_DQ52

M_A_DQ53

M_A_DQ54

M_A_DQ55

M_A_DQ0

M_A_DQ1

M_A_DQ2

M_A_DQ6

M_A_DQ5

M_A_DQ4

M_A_DQ3

M_A_DQ7

M_A_DQ21

M_A_DQ20

M_A_DQ17

M_A_DQ16

M_A_DQ18

M_A_DQ19

M_A_DQ22

M_A_DQ23

M_A_DQ36

M_A_DQ33

M_A_DQ34

M_A_DQ38

M_A_DQ37

M_A_DQ32

M_A_DQ35

M_A_DQ39

M_A_DQ62

M_A_DQ58

M_A_DQ60

M_A_DQ61

M_A_DQ63

M_A_DQ59

M_A_DQ56

M_A_DQ57

M_A_DQS#1

M_A_DQS#3

M_A_DQS#5

M_A_DQS#6

M_A_DQS#0

M_A_DQS#2

M_A_DQS#4

M_A_DQS#7

M_A_DQS1

M_A_DQS3

M_A_DQS5

M_A_DQS6

M_A_DQS0

M_A_DQS2

M_A_DQS4

M_A_DQS7

M_A_DIMA_ODT0

M_A_DIMA_ODT1

0D675V_S0

1

2

M_A_A[15:0][5]

M_A_BS2[5]

M_A_BS0[5]

M_A_BS1[5]

M_A_DQ[63:0][5]

Layout Note:

Place these caps close to VREF_CA

1

DY

2

C1202

C1218

SCD1U10V2KX-5GP

Layout Note:

Place these caps close to VREF_DQ

1

C1205

DY

2

C1206

SC2D2U6D3V2MX-GP

SC1U6D3V2KX-GP

SCD1U10V2KX-5GP

1

C1216

DY

2

SC1U6D3V2KX-GP

M_A_DQS#[7:0][5]

M_A_DQS[7:0][5]

DDR3_DRAMRST#[4,13]

Layout Note:

Place these caps close to VTT1 and VTT2.

M_VREF_CA_DIMMA

M_VREF_DQ_DIMMA

4

DM1

98

A0

97

A1

96

A2

95

A3

92

A4

91

A5

90

A6

86

A7

89

A8

85

A9

107

A10/AP

84

A11

83

A12

119

A13

80

A14

78

A15

79

A16/BA2

109

BA0

108

BA1

5

DQ0

7

DQ1

15

DQ2

17

DQ3

4

DQ4

6

DQ5

16

DQ6

18

DQ7

21

DQ8

23

DQ9

33

DQ10

35

DQ11

22

DQ12

24

DQ13

34

DQ14

36

DQ15

39

DQ16

41

DQ17

51

DQ18

53

DQ19

40

DQ20

42

DQ21

50

DQ22

52

DQ23

57

DQ24

59

DQ25

67

DQ26

69

DQ27

56

DQ28

58

DQ29

68

DQ30

70

DQ31

129

DQ32

131

DQ33

141

DQ34

143

DQ35

130

DQ36

132

DQ37

140

DQ38

142

DQ39

147

DQ40

149

DQ41

157

DQ42

159

DQ43

146

DQ44

148

DQ45

158

DQ46

160

DQ47

163

DQ48

165

DQ49

175

DQ50

177

DQ51

164

DQ52

166

DQ53

174

DQ54

176

DQ55

181

DQ56

183

DQ57

191

DQ58

193

DQ59

180

DQ60

182

DQ61

192

DQ62

194

DQ63

10

DQS0#

27

DQS1#

45

DQS2#

62

DQS3#

135

DQS4#

152

DQS5#

169

DQS6#

186

DQS7#

12

DQS0

29

DQS1

47

DQS2

64

DQS3

137

DQS4

154

DQS5

171

DQS6

188

DQS7

116

ODT0

120

ODT1

126

VREF_CA

1

VREF_DQ

30

RESET#

203

VTT1

204

VTT2

SKT_DDR 204P SMD

DDR3-204P-122-GP-U1

62.10017.Z51

RAS#

WE#

CAS#

CS0#

CS1#

CKE0

CKE1

CK0#

CK1#

DM0

DM1

DM2

DM3

DM4

DM5

DM6

DM7

EVENT#

VDDSPD

NC#1

NC#2

NC#/TEST

VDD1

VDD2

VDD3

VDD4

VDD5

VDD6

VDD7

VDD8

VDD9

VDD10

VDD11

VDD12

VDD13

VDD14

VDD15

VDD16

VDD17

VDD18

NP1

NP2

110

113

115

114

121

73

74

101

CK0

103

102

CK1

104

11

28

46

63

136

153

170

187

200

SDA

202

SCL

198

199

SA0_DIMA

197

SA0

SA1

VSS

SA1_DIMA

201

77

122

125

75

76

81

82

87

88

93

94

99

100

105

106

111

112

117

118

123

124

2

3

8

9

13

14

19

20

25

26

31

32

37

38

43

44

48

49

54

55

60

61

65

66

71

72

127

128

133

134

138

139

144

145

150

151

155

156

161

162

167

168

172

173

178

179

184

185

189

190

195

196

205

206

1D35V_S3

M_A_RAS# [5]

M_A_WE# [5]

M_A_CAS# [5]

M_A_DIMA_CS#0 [5]

M_A_DIMA_CS#1 [5]

M_A_DIMA_CKE0 [5]

M_A_DIMA_CKE1 [5]

M_A_DIMA_CLK_DDR0 [5]

M_A_DIMA_CLK_DDR#0 [5]

M_A_DIMA_CLK_DDR1 [5]

M_A_DIMA_CLK_DDR#1 [5]

PCH_SMBDATA [13,18,58,62,67]

PCH_SMBCLK [13,18,58,62,67]

DDR_PG_CTRL[4]

3

SA0_DIMA

SA1_DIMA

0R0402-PAD-2-GP

3D3V_S0

1

C1203

SCD1U10V2KX-5GP

1D35V_S3

Layout Note:

Place these Caps near SO-DIMMA.

DY

2

C1207

SC10U6D3V3MX-GP

C1207

SC10U6D3V3MX-GP

1

DY

2

1

C1210

C1211

2

SCD1U10V2KX-5GP

X01 change to short pad

0R0402-PAD-2-GP

R1205

DDR_PG_CTRL_R

2

1

Q1201 Need check Vth=1V

R1202

C1208

1

2

1

C1212

2

1

2

C1209

SC10U6D3V3MX-GP

1

2

1

2

SC1U6D3V2KX-GP

1D35V_S3

S

Q1201

DMN5L06K-7-GP

84.05067.031

SC10U6D3V3MX-GP

C1213

SC1U6D3V2KX-GP

G

1

R1201

0R0402-PAD-2-GP

2

1

C1220

2

SCD1U10V2KX-5GP

D

1

C1221

2

5V_S5

DY

close to dimm

5

4

3

2

Note: SA0 DIM0 = 0, SA1_DIM0 = 0 SO-DIMMA SPD Address is 0xA0 SO-DIMMA TS Address is 0x30

Layout Note:

Place Close SO-DIMMA.

DDR_WR_VREF01[5]

1

C1222

2

SCD1U10V2KX-5GP

1

R1208

220KR2J-L2-GP

2

DDR_VTT_PG_CTRL

1

R1204

2MR2-GP

2

1D35V_S3

D

G

1

2

+V_VREF_PATH1

1

2

Q1202

2N7002K-2-GP

84.2N702.J31

2ND = 84.2N702.031

S

M_A_B_DIMM_ODT

DDR_VTT_PG_CTRL [49]

0D675V_VTTREF

0R2J-2-GP

2R2F-GP

R1210

1

C1219

SCD022U16V2JX-GP

R1212

24D9R2F-L-GP

1D35V_S3

1

R1215

2

Title

Size Document Number Rev

Custom

Date: Sheet

1

R1211

1K8R2F-GP

DY

1K8R2F-GP

2

1

R1213

1K8R2F-GP

2

R1206 66D5R2F-GP

1

R1207 66D5R2F-GP

1

R1203 66D5R2F-GP

1

R1209 66D5R2F-GP

1

Friday, June 28, 2013

1

M_VREF_DQ_DIMMA

2

DDR3L-SODIMM1

Hadley 15"

M_A_DIMA_ODT0

M_A_DIMA_ODT1

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

12 101

1

M_B_DIMB_ODT0 [13]

M_B_DIMB_ODT1 [13]

of

X02

D

C

B

A

SSID = MEMORY

D

M_VREF_CA_DIMMB

1

DY

2

C1301

C

M_VREF_DQ_DIMMB

1

C1305

2

SC2D2U6D3V2MX-GP

0D675V_S0

1

C1316

B

A

C1316

DY

2

SC1U6D3V2KX-GP

Layout Note:

All VREF traces should have width=20mil; spacing=20 mil

3

M_B_RAS# [5]

M_B_WE# [5]

M_B_CAS# [5]

M_B_DIMB_CS#0 [5]

M_B_DIMB_CS#1 [5]

M_B_DIMB_CKE0 [5]

M_B_DIMB_CKE1 [5]

M_B_DIMB_CLK_DDR0 [5]

M_B_DIMB_CLK_DDR#0 [5]

M_B_DIMB_CLK_DDR1 [5]

M_B_DIMB_CLK_DDR#1 [5]

PCH_SMBDATA [12,18,58,62,67]

PCH_SMBCLK [12,18,58,62,67]

DY

C1303

SCD1U10V2KX-5GP

1D35V_S3

1

DY

2

1

2

Layout Note:

Place these Caps near SO-DIMMA.

3D3V_S0

1

2

C1311

SC10U6D3V3MX-GP

C1311

SC10U6D3V3MX-GP

C1312

SC10U6D3V3MX-GP

C1312

SC10U6D3V3MX-GP

1

DY

2

1

C1313

C1314

2

SCD1U10V2KX-5GP

Note: SO-DIMMB SPD Address is 0xA4 SO-DIMMB TS Address is 0x34

SA1_DIMB

SA0_DIMB

C1309

SC10U6D3V3MX-GP

C1309

SC10U6D3V3MX-GP

C1310

SC10U6D3V3MX-GP

C1310

SC10U6D3V3MX-GP

1

DY

2

1

C1315

2

DY

SCD1U10V2KX-5GP

C1308

1

2

1

EC1301

2

SCD1U10V2KX-5GP

M_B_A0

M_B_A1

M_B_A2

M_B_A3

M_B_A4

M_B_A5

M_B_A6

M_B_A7

M_B_A8

M_B_A9

M_B_A10

M_B_A11

M_B_A12

M_B_A13

M_B_A14

M_B_A15

M_B_DQ8

M_B_DQ14

M_B_DQ10

M_B_DQ11

M_B_DQ12

M_B_DQ9

M_B_DQ13

M_B_DQ15

M_B_DQ28

M_B_DQ29

M_B_DQ26

M_B_DQ27

M_B_DQ25

M_B_DQ24

M_B_DQ30

M_B_DQ31

M_B_DQ40

M_B_DQ41

M_B_DQ46

M_B_DQ42

M_B_DQ45

M_B_DQ44

M_B_DQ47

M_B_DQ43

M_B_DQ56

M_B_DQ57

M_B_DQ59

M_B_DQ58

M_B_DQ61

M_B_DQ60

M_B_DQ63

M_B_DQ62

M_B_DQ4

M_B_DQ1

M_B_DQ3

M_B_DQ7

M_B_DQ5

M_B_DQ0

M_B_DQ2

M_B_DQ6

M_B_DQ21

M_B_DQ20

M_B_DQ22

M_B_DQ23

M_B_DQ16

M_B_DQ17

M_B_DQ19

M_B_DQ18

M_B_DQ36

M_B_DQ33

M_B_DQ35

M_B_DQ39

M_B_DQ37

M_B_DQ32

M_B_DQ34

M_B_DQ38

M_B_DQ52

M_B_DQ49

M_B_DQ48

M_B_DQ53

M_B_DQ51

M_B_DQ55

M_B_DQ54

M_B_DQ50

M_B_DQS#1

M_B_DQS#3

M_B_DQS#5

M_B_DQS#7

M_B_DQS#0

M_B_DQS#2

M_B_DQS#4

M_B_DQS#6

M_B_DQS1

M_B_DQS3

M_B_DQS5

M_B_DQS7

M_B_DQS0

M_B_DQS2

M_B_DQS4

M_B_DQS6

0D675V_S0

4

DM2

98

A0

97

A1

96

A2

95

A3

92

A4

91

A5

90

A6

86

A7

89

A8

85

A9

107

A10/AP

84

A11

83

A12

119

A13

80

A14

78

A15

79

A16/BA2

109

BA0

108

BA1

5

DQ0

7

DQ1

15

DQ2

17

DQ3

4

DQ4

6

DQ5

16

DQ6

18

DQ7

21

DQ8

23

DQ9

33

DQ10

35

DQ11

22

DQ12

24

DQ13

34

DQ14

36

DQ15

39

DQ16

41

DQ17

51

DQ18

53

DQ19

40

DQ20

42

DQ21

50

DQ22

52

DQ23

57

DQ24

59

DQ25

67

DQ26

69

DQ27

56

DQ28

58

DQ29

68

DQ30

70

DQ31

129

DQ32

131

DQ33

141

DQ34

143

DQ35

130

DQ36

132

DQ37

140

DQ38

142

DQ39

147

DQ40

149

DQ41

157

DQ42

159

DQ43

146

DQ44

148

DQ45

158

DQ46

160

DQ47

163

DQ48

165

DQ49

175

DQ50

177

DQ51

164

DQ52

166

DQ53

174

DQ54

176

DQ55

181

DQ56

183

DQ57

191

DQ58

193

DQ59

180

DQ60

182

DQ61

192

DQ62

194

DQ63

10

DQS0#

27

DQS1#

45

DQS2#

62

DQS3#

135

DQS4#

152

DQS5#

169

DQS6#

186

DQS7#

12

DQS0

29

DQS1

47

DQS2

64

DQS3

137

DQS4

154

DQS5

171

DQS6

188

DQS7

116

ODT0

120

ODT1

126

VREF_CA

1

VREF_DQ

30

RESET#

203

VTT1

204

VTT2

SKT_DDR 204P SMD

DDR3-204P-122-GP-U1

62.10017.Z51

RAS#

WE#

CAS#

CS0#

CS1#

CKE0

CKE1

CK0#

CK1#

DM0

DM1

DM2

DM3

DM4

DM5

DM6

DM7

EVENT#

VDDSPD

NC#1

NC#2

NC#/TEST

VDD1

VDD2

VDD3

VDD4

VDD5

VDD6

VDD7

VDD8

VDD9

VDD10

VDD11

VDD12

VDD13

VDD14

VDD15

VDD16

VDD17

VDD18

NP1

NP2

110

113

115

114

121

73

74

101

CK0

103

102

CK1

104

11

28

46

63

136

153

170

187

200

SDA

202

SCL

198

199

SA0_DIMB

197

SA0

SA1

VSS

SA1_DIMB

201

77

122

125

75

76

81

82

87

88

93

94

99

100

105

106

111

112

117

118

123

124

2

3

8

9

13

14

19

20

25

26

31

32

37

38

43

44

48

49

54

55

60

61

65

66

71

72

127

128

133

134

138

139

144

145

150

151

155

156

161

162

167

168

172

173

178

179

184

185

189

190

195

196

205

206

1D35V_S3

5

M_B_A[15:0] [5]

M_B_BS2[5]

M_B_BS0[5]

M_B_BS1[5]

M_B_DQ[63:0][5]

Layout Note:

Place these caps

1

2

EC1302

SCD1U10V2KX-5GP

1

DY

2

C1304

SCD1U10V2KX-5GP

1

C1317

2

SC1U6D3V2KX-GP

DY

2

1

DY

2

1

C1318

2

close to VREF_CA

C1302

SCD1U10V2KX-5GP

Layout Note:

Place these caps close to VREF_DQ

C1306

SCD1U10V2KX-5GP

Layout Note:

Place these caps close to VTT1 and VTT2.

SC1U6D3V2KX-GP

M_B_DQS#[7:0] [5]

M_B_DQS[7:0] [5]

M_B_DIMB_ODT0[12]

M_B_DIMB_ODT1[12]

M_VREF_CA_DIMMB

M_VREF_DQ_DIMMB

DDR3_DRAMRST#[4,12]

C1319

SCD1U10V2KX-5GP

C1319

SCD1U10V2KX-5GP

1

DY

2

close to dimm

5

4

3

2

3D3V_S0

1

R1301

10KR2J-3-GP

2

1

R1302

0R0402-PAD-2-GP

2

Layout Note:

Place Close SO-DIMMA.

DDR_WR_VREF02[5]

SC10U6D3V3MX-GP

C1307

SC10U6D3V3MX-GP

C1307

SC10U6D3V3MX-GP

1

2

0D675V_VTTREF

R1308

0R2J-2-GP

2R2F-GP

R1304

1

C1320

SCD022U16V2JX-GP

2

+V_VREF_PATH2

1

R1307

24D9R2F-L-GP

2

Title

Size Document Number Rev

Custom

Date: Sheet

1

DY

2

Friday, June 28, 2013

1D35V_S3

1

R1306

1K8R2F-GP

2

1

R1303

1K8R2F-GP

2

DDR3L-SODIMM2

Hadley 15"

M_VREF_DQ_DIMMB

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

13 101

1

D

C

B

A

X02

of

5

4

3

2

1

D

C

D

C

(Blanking)

B

X02

A

5

4

3

2

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

A3

Date: Sheet

Taipei Hsien 221, Taiwan, R.O.C.

M1&M3

Hadley 15"

14 10 1Friday, June 28, 201 3

of

14 10 1Friday, June 28, 201 3

of

14 10 1Friday, June 28, 201 3

1

of

5

SSID = CPU

4

3

2

1

D

3D3V_S0

2

1

RN1501

HSW_ULT_DDR3L

eDP SIDEBAND

PCIE

HSW_ULT_DDR3L

DISPLAY

CPU1I

C

0R0402-P AD-2-GP

R1501

L_BKLT_ CTRL_R

2

L_BKLT_ CTRL[53 ]

RN1504

DGPU_PW R_EN

4

1

2

1

3D3V_S0

B

8

7

6

5

3

OPS

SRN10KJ -5-GP

100KR2J -1-GP

R1509

2

RN1505

SRN10KJ -6-GP

DGPU_HO LD_RST#

DGPU_PW ROK

PIRQD#

1

PIRQC#

2

PIRQB#

3

PIRQA#

4

L_BKLT_ EN[24]

EDP_VDD _EN[52]

A00 change to PIRQB#

HDD_FAL L_INT[67]

DGPU_PW R_EN[82,83]

DGPU_HO LD_RST#[73]

DGPU_PW ROK[24,82,83]

1

0R0402-P AD-2-GP

R1503

1

TP1501

TP1503

TP1502

2

PIRQA#

PIRQB#

PIRQC#

PIRQD#

PCI_PME#

1

MCP_GPIO5 5

1

DGPU_PW R_EN

DGPU_HO LD_RST#

DGPU_PW ROK

PCH_SD_ CD#

1

CPU1I

B8

A9

C6

U6

P4

N4

N2

AD4

U7

L1

L3

R5

L4

HASW ELL-6-GP

EDP_BKLCTL

EDP_BKLEN

EDP_VDDEN

PIRQA#/GPIO77

PIRQB#/GPIO78

PIRQC#/GPIO79

PIRQD#/GPIO80

PME#

GPIO55

GPIO52

GPIO54

GPIO51

GPIO53

9 OF 19

DDPB_CTRLCLK

DDPB_CTRLDATA

DDPC_CTRLCLK

DDPC_CTRLDATA

DDPB_AUXN

DDPC_AUXN

DDPB_AUXP

DDPC_AUXP

DDPB_HPD

DDPC_HPD

EDP_HPD

B9

C9

D9

D11

C5

B6

B5

A6

C8

A8

D6

RN1501

SRN2K2J -1-GP

4

3

HDMI_PCH_ DET [5 4]

EDP_HPD [52,53 ]

PCH_HDM I_CLK [54]

PCH_HDM I_DATA [54]

D

C

B

X02

A

5

4

3

2

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU ( EDP SIDEBAND/GPIO/DDI )

Size Document N umber Rev

A3

Date: Sheet

Taipei Hsien 221, Taiwan, R.O.C.

Hadley 15"

15 10 1Friday, June 28, 201 3

of

15 10 1Friday, June 28, 201 3

of

15 10 1Friday, June 28, 201 3

1

of

SSID = CPU

5

4

3

2

1

D

C

B

PCIE Table

Port

1

2

3

4

5(4lane)

6(4lane)

Device

N/A

WLAN

LAN+ Card reader

GPU

N/A

Share BUS

USB3.0_3

USB3.0_4

SATA0~3

CPU1K

CPU_RXN _C_dGPU_TXN0[73]

CPU_RXP _C_dGPU_TXP0[73]

dGPU_RX N_C_CPU_TXN0[73]

dGPU_RX P_C_CPU_TXP0[73]

CPU_RXN _C_dGPU_TXN1[73]

CPU_RXP _C_dGPU_TXP1[73]

dGPU_RX N_C_CPU_TXN1[73]

dGPU_RX P_C_CPU_TXP1[73]

CPU_RXN _C_dGPU_TXN2[73]

CPU_RXP _C_dGPU_TXP2[73]

dGPU_RX N_C_CPU_TXN2[73]

dGPU_RX P_C_CPU_TXP2[73]

CPU_RXN _C_dGPU_TXN3[73]

CPU_RXP _C_dGPU_TXP3[73]

dGPU_RX N_C_CPU_TXN3[73]

dGPU_RX P_C_CPU_TXP3[73]

PCIE_PRX_ WLANTX_N3[58]

PCIE_PRX_ WLANTX_P3[58]

PCIE_PTX_ WLANRX_N3 _C[58]

PCIE_PTX_ WLANRX_P3 _C[58]

PCIE_PRX_ LANTX_N4[30]

PCIE_PRX_ LANTX_P4[30]

PCIE_PTX_ LANRX_N4_C[30]

PCIE_PTX_ LANRX_P4_C[30]

USB3_PR X_DTX_N2[63]

USB3_PR X_DTX_P2[63]

USB3_PT X_DRX_N2[63]

USB3_PT X_DRX_P2[63]

USB3_PR X_DTX_N3[63]

USB3_PR X_DTX_P3[63]

USB3_PT X_DRX_N3[63]

USB3_PT X_DRX_P3[63]

+V1.05S_ AUSB3PLL

SCD1U10 V2KX-5GP

C1606

1

OPS

1

OPS

C1605

SCD1U10 V2KX-5GP

C1608

1

OPS

1

OPS

C1607

SCD1U10 V2KX-5GP

C1610

1

OPS

1

OPS

C1609

SCD1U10 V2KX-5GP

C1612

1

OPS

1

OPS

C1611

SCD1U10 V2KX-5GP

C1601

1

C1602

SCD1U10 V2KX-5GP

C1603

1

C1604

SCD1U10 V2KX-5GP

R1601

3KR2F-GP

1

Layout Note:

1. PCIE_RCOMP/ PCIE_IREF trac e width=12~15mi l

2. Isolation Sp acing: 12mil

3. Total trace length<500mil

dGPU_RX N_CPU_TXN0

2

dGPU_RX P_CPU_TXP0

2

dGPU_RX N_CPU_TXN1

2

dGPU_RX P_CPU_TXP1

2

dGPU_RX N_CPU_TXN2

2

dGPU_RX P_CPU_TXP2

2

dGPU_RX N_CPU_TXN3

2

dGPU_RX P_CPU_TXP3

2

PCIE_PTX_ WLANRX_N3

2

PCIE_PTX_ WLANRX_P3

2

PCIE_PTX_ LANRX_N4

2

PCIE_PTX_ LANRX_P4

2

PCIE_RCOM P

2

E10

C23

C22

B23

A23

H10

G10

B21

C21

B22

A21

G11

C29

B30

G13

B29

A29

G17

C30

C31

G15

B31

A31

E15

E13

A27

B27

F10

F8

E8

E6

F6

F11

F13

F17

F15

PERN5_L0

PERP5_L0

PETN5_L0

PETP5_L0

PERN5_L1

PERP5_L1

PETN5_L1

PETP5_L1

PERN5_L2

PERP5_L2

PETN5_L2

PETP5_L2

PERN5_L3

PERP5_L3

PETN5_L3

PETP5_L3

PERN3

PERP3

WLAN

PETN3

PETP3

PERN4

PERP4

LAN+Card reader

PETN4

PETP4

PERN1/USB3RN3

PERP1/USB3RP3

PETN1/USB3TN3

PETP1/USB3TP3

PERN2/USB3RN4

PERP2/USB3RP4

PETN2/USB3TN4

PETP2/USB3TP4

RSVD#E15

RSVD#E13

PCIE_RCOMP

PCIE_IREF

HASW ELL-6-GP

HSW_ULT_DDR3L

PCIE USB

11 OF 19

USB2N0

USB2P0

USB2N1

USB2P1

USB2N2

USB2P2

USB2N3

USB2P3

USB2N4

USB2P4

USB2N5

USB2P5

USB2N6

USB2P6

USB2N7

USB2P7

USB3RN1

USB3RP1

USB3TN1

USB3TP1

USB3RN2

USB3RP2

USB3TN2

USB3TP2

USBRBIAS#

USBRBIAS

RSVD#AN10

RSVD#AM10

OC0/GPIO40#

OC1/GPIO41#

OC2/GPIO42#

OC3/GPIO43#

AN8

AM8

AR7

AT7

AR8

AP8

AR10

AT10

AM15

AL15

AM13

AN13

AP11

AN11

AR13

AP13

G20

H20

C33

B34

E18

F18

B33

A33

AJ10

AJ11

AN10

AM10

AL3

AT1

AH2

AV3

USB_PN7

USB_PP7

USB_COM P

USB_OC# 0_1

USB_OC# 2_3

USB_OC# 4_5

USB_OC# 6_7

1

USB_PN0 [34]

USB_PP0 [34]

USB_PN1 [35]

USB_PP1 [35]

USB_PN2 [63]

USB_PP2 [63]

USB_PN3 [63]

USB_PP3 [63]

USB_PN4 [52]

USB_PP4 [52]

USB_PN5 [58]

USB_PP5 [58]

USB_PN6 [52]

USB_PP6 [52]

TP1602

TP1601

1

R1602

22D6R2F -L1-GP

USB3_PR X_CTX_N0 [34]

USB3_PR X_CTX_P0 [34]

USB3_PT X_CRX_N0 [34]

USB3_PT X_CRX_P0 [34]

USB3_PR X_CTX_N1 [34]

USB3_PR X_CTX_P1 [34]

USB3_PT X_CRX_N1 [34]

USB3_PT X_CRX_P1 [34]

2

USB_OC# 0_1 [3 5]

USB_OC# 2_3 [3 5]

USB_OC# 0_1

USB_OC# 2_3

USB_OC# 4_5

USB_OC# 6_7

Pair

Device

USB3.0 Port2

0

USB3.0 port1

1

(with Power Share)

USB3.0 Port3

2

USB3.0 Port4

3

CAMERA

4

WLAN

5

Touch Panel

6

N/A

7

Layout Note:

1. USB_COMP usi ng 50 ohm single-end ed impedance

2. Isolation Sp acing :15mil

3. Total trace length<500mil

3D3V_S5 _PCH

RN1601

1

2

3

4

SRN10KJ -6-GP

8

7

6

5

HSW_ULT_DDR3L

USB 2.0 Table

D

C

B

X02

A

5

4

3

2

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

A3

Date: Sheet

Taipei Hsien 221, Taiwan, R.O.C.

CPU (PCIE/USB)

Hadley 15"

16 10 1Friday, June 28, 201 3

1

of

SSID = CPU

D

R1717 10KR2J -3-GP

3D3V_S0

SRN8K2J -3-GP

C

B

A

1

2

1

RN1704

1

2

5

RN1703

4

3

SRN10KJ -5-GP

2

DY

4

3

SYS_PW ROK[24,96]

PCH_PW ROK[24,26,36]

PM_PW RBTN#[24,96]

AC_PRES ENT[24,76 ]

PCH_SLP _S0#[48]

3D3V_S5

3D3V_S5 _PCH

PM_RSMR ST#

PM_PCH_ PWROK

SYS_PW ROK

XDP_DBR ESET#

PM_CLKR UN#

R1706 0R0402-PAD -2-GP

1

PLT_RST #[24,30,58,6 5,73]

RN1701

4

1

3

2

SRN10KJ -5-GP

2

1

DY

R1724 10KR2J-3 -GP

2

1

R1727 10KR2J-3 -GP

2

R1715

100KR2J -1-GP

BATLOW #

AC_PRES ENT

PM_SUS_ STAT#

PM_SUSW ARN#

R1707

2

1

0R0402-P AD-2-GP

1

TP1705

DY

1

DY

2

0R0402-P AD-2-GP

1

C1701

SC220P5 0V2KX-3GP

2

R1713

4

PM_SUSA CK#_R

XDP_DBR ESET#

SYS_PW ROK

PM_PCH_ PWROK

MPWR OK

PCI_PLTRS T#

PM_RSMR ST#

PM_SUSW ARN#_R

PM_PW RBTN#

AC_PRES ENT

BATLOW #

PCH_SLP _S0#

PCH_SLP _WLAN#

PCI_PLTRS T#

2

PM_SUSA CK#[2 4]

PM_SUSW ARN#[2 4]

CPU1H

AK2

SUSACK#

AC3

SYS_RESET#

AG2

SYS_PWROK

AY7

PCH_PWROK

AB5

APWROK

AG7

PLTRST#

AW6

RSMRST#

AV4

SUSWARN#/SUSPWRDNACK#/GPIO30

AL7

PWRBTN#

AJ8

ACPRESENT/GPIO31

AN4

BATLOW#/GPIO72

AF3

SLP_S0#

AM5

SLP_WLAN#/GPIO29

HASW ELL-6-GP

RN

A00 0618

4

1

3

2

0R4P2R-P AD

RN1702

HSW_ULT_DDR3L

SYSTEM POWER MANAGEMENT

PM_SUSA CK#_R

PM_SUSW ARN#_R

3D3V_AU X_S5

2

R1726

10KR2J-3 -GP

1

3

NON DS3

1

R1708

100KR2J -1-GP

3V_5V_P OK#

DSWVRMEN

DPWROK

CLKRUN#/GPIO32

SUS_STAT#/GPIO61

SUSCLK/GPIO62

SLP_S5#/GPIO63

SLP_S4#

SLP_S3#

SLP_SUS#

SLP_LAN#

2

Q1701

4

3

5

2

6

1

2N7002K DW-GP

8 OF 19

WAKE#

SLP_A#

AW7

AV5

AJ5

V5

AG4

AE6

AP5

AJ6

AT4

AL5

AP4

AJ7

PCH_DPW ROK

PM_RSMR ST#

3V_5V_P OK_C

PCH strap pin:

DSWODVREN

DSWO DVREN

PCH_DPW ROK

PCH_W AKE#

PM_CLKR UN#

PM_SUS_ STAT#

SUS_CLK

PM_SLP_ S5#

PM_SLP_ S4#

PM_SLP_ S3#

PM_SLP_ A#

PM_SLP_ SUS#

PM_SLP_ LAN#

R1703 1KR2J-1-GP

1

A00 0618

R1718

1

0R0402-P AD-2-GP

R1725

100KR2F -L1-GP

1KR2J-1-G P

R1702

2

1

R1728

2

1

0R2J-2-GP

NON DS3

2

1

R1729

0R0402-P AD-2-GP

A00 0618

2

On Die DSW VR Enable

Low = Disable High = Enable (default)

*

NON DS3

0R2J-2-GP

R1704

PM_RSMR ST#

2

1

2

1

0R0402-P AD-2-GP

R1709

2

1

TP1702

R1710

TP1703

TP1704

TP1707

2

DS3

PM_SLP_ SUS#

2

1

0R0402-P AD-2-GP

1

2

RSMRST# _KBC [2 4]

3V_5V_P OK [45]

PM_SLP_ S4# [24,49]

PM_SLP_ S3# [24,36,48,49,5 1]

PM_SLP_ SUS# [24,38]

3D3V_S5

A00 0618

0311 PCH WAKE# pin PH 1K

PM_CLKR UN#_EC [24]

PCH_SUS CLK_KBC [24 ]

KBC_DPW ROK [24 ]

PCH_SUS CLK_KBC

DSWO DVREN

1

R1720

330KR2J -L1-GP

1

DY

R1721

330KR2J -L1-GP

EC1701

SC4D7P5 0V2CN-1GP

RTC_AUX _S5

2

DY

1

D

C

B

A

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

A3

Date: Sheet

5

4

3

2

Date: Sheet

Taipei Hsien 221, Taiwan, R.O.C.

CPU (PM)

Hadley 15"

X02

17 10 1Friday, June 28, 201 3

of

17 10 1Friday, June 28, 201 3

of

17 10 1Friday, June 28, 201 3

1

of

X02

SSID = CPU

3D3V_S0

D

CLK_PCIE_ WLAN_N3[5 8]

CLK_PCIE_ WLAN_P3[58]

CLK_PCIE_ WLAN_REQ3 #[58]

CLK_PCIE_ LAN_N4[30]

CLK_PCIE_ LAN_P4[30 ]

CLK_PCIE_ LAN_REQ4#[30]

C

LPC_AD[3 ..0][24,65]

B

RN1801

1

2

3

4

SRN10KJ -6-GP

CLK_PCIE_ VGA#[73]

CLK_PCIE_ VGA[73 ]

PEG_CLK REQ#[73]

5

CLK_PCIE_ REQ#

8

CLK_PCIE_ WLAN_REQ3 #

7

PEG_CLK REQ#

6

CLK_PCIE_ LAN_REQ4#

5

LPC_AD[3 ..0]

LPC_FRA ME#[24,65]

SPI_CLK_R[24,25]

SPI_CS0#_ R[24,25]

SPI_SI_R[24,25]

SPI_SO_R[24,25]

SPI_WP #[25]

SPI_HOLD#[25]

SRN1KJ-1 1-GP-U

RN1802

LPC_AD0

LPC_AD1

LPC_AD2

LPC_AD3

3D3V_S5

1

4

2

3

X01 0321

RN1806

0R8P4R-P AD-1-GP

8

7

6

5

X01 0321

PCH_SPI_D Q3

PCH_SPI_D Q2

4

3

2

1

A00 0618

C1801

0R0402-P AD-2-GP

R1810

XTAL24_ IN

HSW_ULT_DDR3L

CPU1F

C43

CLKOUT_PCIE_N0

C42

CLK_PCIE_ REQ#

RN

1

2

3

4

1

R18080R 0402-PAD-2-GP

1

R18090R 0402-PAD-2-GP

1

R18110R 0402-PAD-2-GP

1

R18120R 0402-PAD-2-GP

1

R18010R 0402-PAD-2-GP

R18070R 0402-PAD-2-GP

LPC_LAD 0_PCH

LPC_LAD 1_PCH

LPC_LAD 2_PCH

LPC_LAD 3_PCH

LPC_LFR AME#_PCH

2

R180633R2J-2-G P

2

PCH_SPI_S I

2

PCH_SPI_S O

2

PCH_SPI_D Q2

2

PCH_SPI_D Q3

2

PCH_SPI_C LK

PCH_SPI_C S0#

CLKOUT_PCIE_P0

U2

PCIECLKRQ0#/GPIO18

B41

CLKOUT_PCIE_N1

A41

CLKOUT_PCIE_P1

Y5

PCIECLKRQ1#/GPIO19

C41

CLKOUT_PCIE_N2

B42

CLKOUT_PCIE_P2

AD1

PCIECLKRQ2#/GPIO20

B38

CLKOUT_PCIE_N3

C37

CLKOUT_PCIE_P3

N1

PCIECLKRQ3#/GPIO21

A39

CLKOUT_PCIE_N4

B39

CLKOUT_PCIE_P4

U5

PCIECLKRQ4#/GPIO22

B37

CLKOUT_PCIE_N5

A37

CLKOUT_PCIE_P5

T2

PCIECLKRQ5#/GPIO23

HASW ELL-6-GP

CPU1G

AU14

LAD0

AW12

LAD1

AY12

LAD2

AW11

LAD3

AV12

LFRAME#

AA3

SPI_CLK

Y7

SPI_CS0#

Y4

SPI_CS1#

AC2

SPI_CS2#

AA2

SPI_MOSI

AA4

SPI_MISO

Y6

SPI_IO2

AF1

SPI_IO3

HASW ELL-6-GP

HSW_ULT_DDR3L

CLOCK

WLAN

SIGNALS

LAN/ Card reader

GPU

HSW_ULT_DDR3L

LPC

SMBUS

SML1ALERT#/PCHHOT#/GPIO73

C-LINKSPI

CLKOUT_ITPXDP_P

SMBALERT#/GPIO11

SML0ALERT#/GPIO60

6 OF 19

XTAL24_IN

XTAL24_OUT

RSVD#K21

RSVD#M21

DIFFCLK_BIASREF

TESTLOW_C35

TESTLOW_C34

TESTLOW_AK8

TESTLOW_AL8

CLKOUT_LPC_0

CLKOUT_LPC_1

CLKOUT_ITPXDP#

7 OF 19

SMBCLK

SMBDATA

SML0CLK

SML0DATA

SML1CLK/GPIO75

SML1DATA/GPIO74

CL_CLK

CL_DATA

CL_RST#

A25

B25

K21

M21

C26

C35

C34

AK8

AL8

AN15

AP15

B35

A35

AN2

AP2

AH1

AL2

AN1

AK1

AU4

AU3

AH3

AF2

AD2

AF4

XTAL24_ IN

XTAL24_ OUT

XCLK_BIAS REF

MCP_TES TLOW1

MCP_TES TLOW2

MCP_TES TLOW3

MCP_TES TLOW4

CLK_PCI_L PC_R

CLK_PCI_K BC_R

MCP_GPIO1 1

SMB_CLK

SMB_DAT A

CARD_PW R_EN

SML0_CL K

SML0_DA TA

MCP_GPIO7 3

SML1_CL K

SML1_DA TA

TP_CL_C LK

1

TP_CL_D ATA

1

TP_CL_R ST#

1

3KR2F-GP

R1803

1

RN1803

SRN10KJ -5-GP

2

1

RN1808

SRN10KJ -5-GP

1

2

R1804 0R2J-2-GP

1

LPC

R1805

1

0R0402-P AD-2-GP

A00 0618

SML0_CL K [53]

SML0_DA TA [53]

SML1_CL K [24,26,76]

SML1_DA TA [24,26,76]

TP1803

TP1804

TP1805

SMB_DAT A

SMB_CLK

+V1.05S_ AXCK_LCPLL

2

3

4

3

2

EC1801

SC10P50V2JN-4GP

EC1801

SC10P50V2JN-4GP

1

DY

2

3D3V_S0

Q1801

6

5

4

2N7002K DW-GP

XTAL24_ OUT

CLK_PCI_L PC [65]

CLK_PCI_K BC [24]

PCIE_CLK_ XDP_N [96 ]

PCIE_CLK_ XDP_P [96]

EC1802

SC10P50V2JN-4GP

EC1802

SC10P50V2JN-4GP

1

2

3

R1810

1

R1802

1M1R2J-G P

2

SML0_DA TA

SML0_CL K

SML1_CL K

SML1_DA TA

MCP_GPIO7 3

MCP_GPIO1 1

CARD_PW R_EN

SMB_DAT A

SMB_CLK

84.2N702.A3F

2nd = 84.DM601.03F

3rd = 84.2N702.E3F

4th = 84.2N702.F3F

2

1

4

RN1805

2

1

SRN2K2J -1-GP

XTAL24_ IN_R

2

3

RN1807

4

3

2

1

SRN2K2J -4-GP

RN1809

SRN10KJ -6-GP

1

2

3

4

RN1804

2

1

SRN2K2J -1-GP

C1801

2

1

SC15P50 V2JN-2-GP

XTAL-24M HZ-86-GP

X1801

82.30004.891

C1802

2

1

SC15P50 V2JN-2-GP

3D3V_S5 _PCH

5

6

7

8

7

6

5

3

4

3D3V_S5 _PCH

3

3D3V_S0

4

PCH_SMB DATA [12 ,13,58,62,67]

PCH_SMB CLK [12,13,58,62 ,67]

D

C

B

X02

A

5

4

3

2

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU (CLK/SMB/LPC/SPI)

Size Document N umber Rev

A3

Date: Sheet

Taipei Hsien 221, Taiwan, R.O.C.

Hadley 15"

18 10 1Friday, June 28, 201 3

of

18 10 1Friday, June 28, 201 3

of

18 10 1Friday, June 28, 201 3

1

of

5

4

3

2

1

SSID = CPU

D

C

Flash Descriptor Security Overide/ Intel ME Debug Mode

HDA_SDOUT

The internal pull-down is disabled a fter PLTRST# deasserts

B

R1913

1

DY

330KR2J -L1-GP

Integrated SUS 1V VRM Enable

INTVRMEN

RTCRST_ ON[24]

Low = Default High = Enable

2

Low = External VRs High = Internal VRs

*

PCH_INTVR MEN

R1902

10KR2J-3 -GP

*

RTC_X1

2

1

R1915 10M R2J-L-GP

X1901

1

RTC_AUX _S5

1

RTC_AUX _S5

RN1901

SRN20KJ -1-GP

Q1901

G

1

S

2N7002K -2-GP

2

HDA_COD EC_BITCLK[27]

HDA_COD EC_SYNC[27]

HDA_COD EC_RST#[27,29 ]

HDA_COD EC_SDOUT[27]

2N7002K -2-GP

84.2N702.J31

2ND = 84.2N702.031

3rd = 84.07002.I31

ME_UNLO CK[24]

D

1

C1901

SC1U6D3V2KX-GP

2

R1907 33R2J-2-GP

1

R1905 0R0402-PAD -2-GP

1

R1908 0R0402-PAD -2-GP

1

R1910 0R0402-PAD -2-GP

1

R1909 1KR2J-1-GP

1D05S_V CCST

DY

2

R1916 51R2J-2-G P

2

DY

R1917 51R2J-2-G P

2

DY

R1918 51R2J-2-G P

2

DY

R1919 1KR2J-1-G P

2

G1901

GAP-OPEN

1

2

1

330KR2J -L1-GP

2

1

4

3

1

C1902

SC1U6D3 V2KX-GP

2

HDA_BITCL K

PCH_JTA G_TDI

PCH_JTA G_TDO

PCH_JTA G_TMS

XDP_TCK _JTAGX

R1903

HDA_SDIN0[27]

TP1902

TP1901

HDA_SYNC

HDA_RST #

HDA_SDO UT

1

R1901

1M1R2J-G P

2

HDA_BITCL K

HDA_SYNC

HDA_RST #

HDA_SDIN0

HDA_SDO UT

TP_HDA_ DOCK_EN#

1

PCH_JTA G_TRST#

1

PCH_JTA G_TCK

PCH_JTA G_TDI

PCH_JTA G_TDO

PCH_JTA G_TMS

XDP_TCK _JTAGX

RTC_X1

RTC_X2

SM_INTRUD ER#

PCH_INTVR MEN

SRTC_RS T#

RTC_RST #

AW5

AY5

AU6

AV7

AV6

AU7

AW8

AV11

AU8

AY10

AU12

AU11

AW10

AV10

AY8

AU62

AE62

AD61

AE61

AD62

AL11

AC4

AE63

AV2

1

C1903

SC15P50V2JN-2-GP

2

2nd = 82.30001.841

CPU1E

RTCX1

RTCX2

INTRUDER#

INTVRMEN

SRTCRST#

RTCRST#

HDA_BCLK/I2S0_SCLK

HDA_SYNC/I2S0_SFRM

HDA_RST#/I2S_MCLK#

HDA_SDI0/I2S0_RXD

HDA_SDI1/I2S1_RXD

HDA_SDO/I2S0_TXD

HDA_DOCK_EN#/I2S1_TXD#

HDA_DOCK_RST#/I2S1_SFRM#

I2S1_SCLK

PCH_TRST#

PCH_TCK

PCH_TDI

PCH_TDO

PCH_TMS

RSVD#AL11

RSVD#AC4

JTAGX

RSVD#AV2

HASW ELL-6-GP

JTAG

4

3

2

X-32D768 KHZ-65-GP

82.30001.A41

HSW_ULT_DDR3L

RTC

AUDIO SATA

RTC_X2

X02 0502 change C1903 C1904 from 18pF to 15 pF

1

C1904

SC15P50V2JN-2-GP

2

5 OF 19

RSVD#L11

RSVD#K10

SATALED#

J5

H5

B15

A15

J8

H8

A17

B17

J6

H6

B14

C15

F5

E5

C17

D17

EC_SMI#

V1

MCP_GPIO3 5

U1

SATA_OD D_PRSNT#

V6

AC1

SATA_IREF

A12

L11

K10

SATA_RC OMP

C12

SATA_LE D#

U3

SATA_RN0/PERN6_L3

SATA_RP0/PERP6_L3

SATA_TN0/PETN6_L3

SATA_TP0/PETP6_L3

SATA_RN1/PERN6_L2

SATA_RP1/PERP6_L2

SATA_TN1/PETN6_L2

SATA_TP1/PETP6_L2

SATA_RN2/PERN6_L1

SATA_RP2/PERP6_L1

SATA_TN2/PETN6_L1

SATA_TP2/PETP6_L1

SATA_RN3/PERN6_L0

SATA_RP3/PERP6_L0

SATA_TN3/PETN6_L0

SATA_TP3/PETP6_L0

SATA0GP/GPIO34

SATA1GP/GPIO35

SATA2GP/GPIO36

SATA3GP/GPIO37

SATA_IREF

SATA_RCOMP

SATA3_P RX_DTX_N0 [56]

SATA3_P RX_DTX_P0 [56]

SATA3_P TX_DRX_N0 [56]

SATA3_P TX_DRX_P0 [56]

SATA3_P RX_DTX_N1 [63]

SATA3_P RX_DTX_P1 [63]

SATA3_P TX_DRX_N1 [63]

SATA3_P TX_DRX_P1 [63]

EC_SMI# [24]

MSATA_D ET# [63]

SATA_LE D# [61]

Layout Note:

4mil trace at b reak-out and 3 12-15mil trace with <0.2 ohms and length tota l <= 500mils.

RN1902

EC_SMI#

MCP_GPIO3 5

MSATA_D ET#

SATA_OD D_PRSNT#

RN1902

1

2

3

4

SRN10KJ -6-GP

HDD1

mSATA

+V1.05S_ ASATA3PLL

0R0402-P AD-2-GP

R1904

1

R1906

3KR2F-GP

3D3V_S0

8

7

6

5

D

C

2

B

PCH_JTA G_TCK

2

1

DY

R1920 51R2J-2-G P

X02

A

5

4

3

2

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU (RTC/SATA/HDA/JTAG)

Size Document N umber Rev

A3

Date: Sheet

Taipei Hsien 221, Taiwan, R.O.C.

Hadley 15"

19 10 1Friday, June 28, 201 3

of

19 10 1Friday, June 28, 201 3

of

19 10 1Friday, June 28, 201 3

1

of

5

SSID = CPU

3D3V_S5

RN2006

D

1

2

SRN10KJ -5-GP

GPIO[47:44]=[1,1,1,1] for SODIMM configuration

3D3V_S5 _PCH

1

R2013

10KR2J-3 -GP

2

MCP_GPIO_ PH

C

3D3V_S5 _PCH

B

3D3V_S0

RN2012

SRN10KJ -6-GP

1

2

3

4

R2024

1

100KR2J -1-GP

BIOS strap pin:

PX(AMD)

DIS

UMA

Optimus(NV)

A

MCP_GPIO1 2

4

MCP_GPIO2 7

3

A00 0618

R20010R0402 -PAD-2-GP

2

1

R20020R0402 -PAD-2-GP

2

1

R20040R0402 -PAD-2-GP

2

1

R20070R0402 -PAD-2-GP

2

1

R20150R0402 -PAD-2-GP

2

1

R20160R0402 -PAD-2-GP

2

1

R20170R0402 -PAD-2-GP

2

1

R20190R0402 -PAD-2-GP

2

1

R20200R0402 -PAD-2-GP

2

1

R20210R0402 -PAD-2-GP

2

1

R20220R0402 -PAD-2-GP

2

1

R20230R0402 -PAD-2-GP

2

1

EC_SCI#

8

EC_SW I#

7

RTC_DET #

6

WLA N_PLT_RST#

5

HSIOPC

2

BIOS UMA/DIS Strap pin

BOARD_ID1

0 0

0

1

5

MCP_GPIO5 8

DRAM_SE L0

DRAM_SE L2

MCP_GPIO2 6

MCP_GPIO5 6

DRAM_SE L1

MCP_GPIO1 4

MCP_GPIO2 8

MCP_GPIO8

MCP_GPIO1 3

DRAM_SE L3

MCP_GPIO5 7

BOARD_ID2

1

RN2014

SRN10KJ -6-GP

INT_SERIRQ

KB_DET#

H_RCIN#

DBC_EN

I2C0_SDA

I2C1_SCL

I2C1_SDA

I2C0_SCL

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

SRN10KJ -6-GP

1

2

3

4

RN2007

SRN10KJ -6-GP

8

7

6

5

20 10 1Friday, June 28, 201 3

1

8

7

6

5

1

2

3

4

of

3D3V_S0

X02

D

C

B

A

1

KB_DET# [6 2]

KB_LED_ BL_DET [6 2]

DBC_EN [52 ]

1

HDA_SPK R

2

1

R2003

49D9R2F -GP

2

TP2010

TP2011

TP2021

TP2012

TP2013

TP2014

TP2015

TP2016

TP2017

TP2018

TP2019

TP2005

TP2006

TP2007

TP2008

2

COLOR_E NGINE [52]

Title

Size Document N umber Rev

Date: Sheet

1D05S_V CCST

1

R2018

1KR2J-1-G P

2

H_RCIN# [24]

INT_SERIRQ [24]

Layout Note:

1.Referenced "continuous" VSS plane only.

2.Avoid routing next to clock pins or noisy signals.

3. Trace width: 12~15mil

4. Isolation Spacing: 12mil

5. Max length: 500mil

BLUETOO TH_EN [58]

CPU (GPIO)

A3

Hadley 15"

4

HSW_ULT_DDR3L

CPU1J

FFS_INT2[67]

TP2004

RTC_DET #[25]

TP2002

RN2005

SRN10KJ -6-GP

1

DY

1

DY

TP2002

TP2020

TP2009

TP2003

8

7

6

5

HDD_DEV SLP

2

MSATA_D EVSLP

2

HSIOPC[21]

EC_SW I#[24]

EC_SCI#[24]

HDD_DEV SLP[56]

MSATA_D EVSLP[63]

HDA_SPK R[27]

3D3V_S0

1

2

3

4

3D3V_S0

10KR2J-3 -GP

R2009

R2010

10KR2J-3 -GP

1

BOARD_ID2

0

1

FFS_INT2

MCP_GPIO8

MCP_GPIO1 2

MCP_GPIO1 5

MCP_GPIO1 6

1

SATA_OD D_DA#

RTC_DET #

MCP_GPIO2 7

MCP_GPIO2 8

MCP_GPIO2 6

MCP_GPIO5 6

MCP_GPIO5 7

MCP_GPIO5 8

WLA N_PLT_RST#

DRAM_SE L0

DRAM_SE L3

BOARD_ID1

BOARD_ID2

MCP_GPIO5 0

1

MCP_GPIO1 3

MCP_GPIO1 4

CAMERA_ PWR_EN

1

DRAM_SE L1

DRAM_SE L2

EC_SW I#

EC_SCI#

MCP_GPIO7 0

1

MCP_GPIO3 9

1

FFS_INT2

BOARD_ID1

SATA_OD D_DA#

BLUETOO TH_EN

3D3V_S0

1

OPS

2

1

UMA

2

R2005

10KR2J-3 -GP

R2008

10KR2J-3 -GP

P1

BMBUSY#/GPIO76

AU2

GPIO8

AM7

LAN_PHY_PWR_CTRL/GPIO12

AD6

GPIO15

Y1

GPIO16

T3

GPIO17

AD5

GPIO24

AN5

GPIO27

AD7

GPIO28

AN3

GPIO26

AG6

GPIO56

AP1

GPIO57

AL4

GPIO58

AT5

GPIO59

AK4

GPIO44

AB6

GPIO47

U4

GPIO48

Y3

GPIO49

P3

GPIO50

Y2

HSIOPC/GPIO71

AT3

GPIO13

AH4

GPIO14

AM4

GPIO25

AG5

GPIO45

AG3

GPIO46

AM3

GPIO9

AM2

GPIO10

P2

DEVSLP0/GPIO33

C4

SDIO_POWER_EN/GPIO70

L2

DEVSLP1/GPIO38

N5

DEVSLP2/GPIO39

V2

SPKR/GPIO81

HASW ELL-6-GP

PCH strap pin:

HDA_SPKR

The internal pull-down is disabled a fter PLTRST# deasserts

SDIO_D0 / GPIO66

The internal pull-down is disabled a fter PLTRST# deasserts

The internal pull-down is disabled a fter RSMRST# deasserts.

GPIO15

HSW_ULT_DDR3L

GPIO

Top-Block Swap Override mode

*

TLS Confidentiality

Boot BIOS Strap Bit BBS

Boot BIOS Destination

The internal pull-down is disabled a fter PLTRST# deasserts

4

3

THRMTRIP#

CPU/

MISC

SERIAL IO

RCIN#/GPIO82

PCH_OPI_RCOMP

RSVD#AF20

RSVD#AB21

GSPI0_CS#/GPIO83

GSPI0_CLK/GPIO84

GSPI0_MISO/GPIO85

GSPI0_MOSI/GPIO86

GSPI1_CS#/GPIO87

GSPI1_CLK/GPIO88

GSPI1_MISO/GPIO89

GSPI_MOSI/GPIO90

UART0_RXD/GPIO91

UART0_TXD/GPIO92

UART0_RTS#/GPIO93

UART0_CTS#/GPIO94

UART1_RXD/GPIO0

UART1_TXD/GPIO1

UART1_RST#/GPIO2

UART1_CTS#/GPIO3

I2C0_SDA/GPIO4

I2C0_SCL/GPIO5

I2C1_SDA/GPIO6

I2C1_SCL/GPIO7

SDIO_CLK/GPIO64

SDIO_CMD/GPIO65

SDIO_D0/GPIO66

SDIO_D1/GPIO67

SDIO_D2/GPIO68

SDIO_D3/GPIO69

NO REBOOT

Low = Disable (Default)

*

High = Enable

High = Enable "Top-Block swap" mode (Default) Low = Disable "Top-Block swap" mode

Low = Disable Intel ME Crypto TLS

*

High = Enable Intel ME Crypto TLS

Low = SPI

*

High = LPC

3

10 OF 19

SERIRQ

PCH_THE RMTRIP

D60

H_RCIN#

V4

INT_SERIRQ

T4

PCH_OPIRC OMP

AW15

AF20

AB21

MCP_GPIO8 3

R6

MCP_GPIO8 4

L6

SATA_OD D_PWRGT

N6

LPSS_GS PI0_MOSI_BBS0_R

L8

MCP_GPIO8 7

R7

MCP_GPIO8 8

L5

TOUCH_P WR_EN

N7

K2

J1

K3

MCP_GPIO9 3

J2

MCP_GPIO9 4

G1

MCP_GPIO0

K4

MCP_GPIO1

G2

MCP_GPIO2

J3

J4

I2C0_SDA

F2

I2C0_SCL

F3

I2C1_SDA

G4

I2C1_SCL

F1

COLOR_E NGINE

E3

MCP_GPIO6 5

F4

LPSS_SD IO_D0_CMNHDR

D3

MCP_GPIO6 7

E4

MCP_GPIO6 8

C3

MCP_GPIO6 9

E2

3D3V_S0

1KR2J-1-G P

R2006

1

3D3V_S0

1

R2011

DY

1KR2J-1-G P

2

LPSS_SD IO_D0_CMNHDR

3D3V_S5 _PCH

1

R2014

DY

1KR2J-1-G P

2

3D3V_S0

1

R2012

DY

1KR2J-1-G P

2

LPSS_GS PI0_MOSI_BBS0_R

DY

2

MCP_GPIO1 5

SSID = CPU

D

3D3V_S5

C

1D05V_S0

B

1

0R0402-PAD-2-GP

1

0R0402-PAD-2-GP

R2101

R2117

1

R2118

0R0402-PAD-2-GP

1

C2104

SC1U6D3V2KX-GP

2

1

D

C

3D3V_S0

R2103

2

1

B

2

A00 0618

0R0402-PAD-2-GP

1

C2109

SC1U6D3V2KX-GP

2

RTC_AUX_S5

C2110

1

SCD1U10V2KX-5GP

R2110

5D1R2F-GP

1

TP2106

1

2

R2102

2

1

2

PCH_VCCDSW_R

2

3D3V_S0

C2128

1

2

TP2109

TP2105

C2135

SC1U6D3V2KX-GP

C2135

SC1U6D3V2KX-GP

3D3V_S5_PCH

3D3V_S5

C2147

SCD1U10V2KX-5GP

C2114

SC1U6D3V2KX-GP

1

SC1U6D3V2KX-GP

1D05V_S0

2

X02 remove C2103

+V3.3S_1.8S_LPSS_SDIO

GPIO/LPC

LPT LP POWER

1D05V_S0

3

HSW_ULT_DDR3L

HSIO

OPI

USB3

HDA

VRM

R2122

0R5J-5-GP

1

Non-HSIO

RTC

SPI

CORE

THERMAL SENSOR

SERIAL IO

SUS OSCILLATOR

USB2

2

13 OF 19

VCCSUS3_3

VCCRTC

DCPRTC

VCCSPI

VCCASW

VCC1_05

DCPSUSBYP#AG19

DCPSUSBYP#AG20

VCCASW

DCPSUS1#AD10

DCPSUS1#AD8

VCCTS1_5

VCC3_3

VCCSDIO

DCPSUS4

RSVD#AC20

VCC1_05

1D05V_HSIO

+3.3A_DSW_PRTCSUS

AH11

AG10

+VCCRTCEXT

AE7

Y8

AG14

AG13

J11

H11

H15

AE8

AF22

+PCH_VCCDSW

AG19

AG20

AE9

AF9

AG8

+V1.05A_SUS_PCH

AD10

AD8

J15

K14

K16

U8

T9

+V1.05A_AOSCSUS

AB8

TP_V1.05S_APLLOPI

AC20

AG16

AG17

1D05V_S0

+1.05M_ASW

1D5V_S0

+V3.3S_1.8S_LPSS_SDIO

R2104

1

+V3.3A_1.5A_HDA

2

1

0R0402-PAD-2-GP

R2106

4

2

1

DY

2

1

2

+V1.05DX_MODPHY_PCH

C2105

SC1U6D3V2KX-GP

C2105

SC1U6D3V2KX-GP

TP2102

TP2107

C2116

SC1U6D3V2KX-GP

C2116

SC1U6D3V2KX-GP

TP2108

2

TP2103

TP2104

TP2101

+V1.05DX_MODPHY_PCH

+V1.05S_AIDLE

+V1.05S_AUSB3PLL

+V1.05S_ASATA3PLL

TP_VCCAPLLOPI_VAL

1

+V1.05S_APLLOPI

+V1.05A_VCCUSB3SUS

1

+V3.3A_1.5A_HDA

+V1.05A_USB2SUS

1

+V3.3A_PSUS

+V3.3A_DSW_P

1

C2123

SC10U6D3V3MX-GP

2

+V1.05S_AXCK_DCB

+V1.05S_AXCK_LCPLL

+V1.05S_SSCF100

+V1.05S_SSCFF

TP_V1.05S_SSCF100

1

TP_V1.05S_AXCK_DCB

1

TP_V1.05S_SSCFF

1

+V3.3A_PSUS

+V3.3S_PCORE

AA21

AH14

AH13

AH10

AE20

AE21

W21

M20

K9

L10

M9

N8

P9

B18

B11

Y20

J13

AC9

AA9

V8

W9

J18

K19

A20

J17

R21

T21

K18

V21

CPU1M

VCCHSIO

VCC1_05

VCCUSB3PLL

VCCSATA3PLL

RSVD#Y20

VCCAPLL

DCPSUS3

VCCHDA

DCPSUS2

VCCSUS3_3

VCCDSW3_3

VCC3_3

VCCCLK

VCCACLKPLL

VCCCLK

RSVD#K18

RSVD#M20

RSVD#V21

VCCSUS3_3

HASWELL-6-GP

5

1D05V_S0

0R0402-PAD-2-GP

3D3V_S5_PCH

A00 0618

1

R2105

0R0402-PAD-2-GP

+V3.3A_DSW_P

2

C2136

SCD1U10V2KX-5GP

C2136

SCD1U10V2KX-5GP

1

DY

2

+V1.05S_SSCF100

C2137

SC1U6D3V2KX-GP

C2137

SC1U6D3V2KX-GP

1

2

+V1.05S_SSCFF

2

C2138

SC1U6D3V2KX-GP

C2138

SC1U6D3V2KX-GP

1

2

3D3V_S0

R2123

HSIOPC_R

2

5V_S5

HSIO

1

HSIO

0R2J-2-GP

1

C2102

SC4D7U6D3V3KX-GP

2

3

9

U2101

ON

1

VDD

2

D#2

3

HSIO

D#3

4

D#4

SLG59M1470VTR-GP

74.59147.093

GND

1D05V_HSIO

0R5J-5-GP

R2114

8

HSIO_OUT

7

S#7

6

S#6

5

S#5

R2114

2

1

HSIO

C2101

SC10U6D3V3MX-GP

C2101

SC10U6D3V3MX-GP

1

2

A

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

Taipei Hsien 221, Taiwan, R.O.C.

CPU (POWER2)

Hadley 15"

21 101Friday, June 28, 2013

1

X02

of

HSIOPC[20]

1D05V_S0

A

5

4

5

SSID = CPU

4

3

2

1

D

HSW_ULT_DDR3L

CPU1Q

DC_TEST _AY2_AW2

TP2201

TP2204

C

B

DC_TEST _AY3_AW3

TP_DC_T EST_AY60

1

DC_TEST _AY61_AW61

DC_TEST _AY62_AW62

TP_DC_T EST_B2

1

DC_TEST _A3_B3

DC_TEST _A61_B61

DC_TEST _B62_B63

DC_TEST _C1_C2

AY2

DAISY_CHAIN_NCTF_AY2

AY3

DAISY_CHAIN_NCTF_AY3

AY60

DAISY_CHAIN_NCTF_AY60

AY61

DAISY_CHAIN_NCTF_AY61

AY62

DAISY_CHAIN_NCTF_AY62

B2

DAISY_CHAIN_NCTF_B2

B3

DAISY_CHAIN_NCTF_B3

B61

DAISY_CHAIN_NCTF_B61

B62

DAISY_CHAIN_NCTF_B62

B63

DAISY_CHAIN_NCTF_B63

C1

DAISY_CHAIN_NCTF_C1

C2

DAISY_CHAIN_NCTF_C2

HASW ELL-6-GP

CPU1R

AT2

RSVD#AT2

AU44

RSVD#AU44

AV44

RSVD#AV44

D15

RSVD#D15

F22

RSVD#F22

H22

RSVD#H22

J21

RSVD#J21

HASW ELL-6-GP

HSW_ULT_DDR3L

DAISY_CHAIN_NCTF_A3

DAISY_CHAIN_NCTF_A4

DAISY_CHAIN_NCTF_A60

DAISY_CHAIN_NCTF_A61

DAISY_CHAIN_NCTF_A62

DAISY_CHAIN_NCTF_AV1

DAISY_CHAIN_NCTF_AW1

DAISY_CHAIN_NCTF_AW2

DAISY_CHAIN_NCTF_AW3

DAISY_CHAIN_NCTF_AW61

DAISY_CHAIN_NCTF_AW62

DAISY_CHAIN_NCTF_AW63

17 OF 19

18 OF 19

RSVD#N23

RSVD#R23

RSVD#T23

RSVD#U10

RSVD#AL1

RSVD#AM11

RSVD#AP7

RSVD#AU10

RSVD#AU15

RSVD#AW14

RSVD#AY14

DC_TEST _A3_B3

A3

TP_DC_T EST_A4

A4

TP_DC_T EST_A60

A60

DC_TEST _A61_B61

A61

TP_DC_T EST_A62

A62

TP_DC_T EST_AV1

AV1

TP_DC_T EST_AW1

AW1

DC_TEST _AY2_AW2

AW2

DC_TEST _AY3_AW3

AW3

DC_TEST _AY61_AW61

AW61

DC_TEST _AY62_AW62

AW62

TP_DC_T EST_AW63

AW63

N23

R23

T23

U10

AL1

AM11

AP7

AU10

AU15

AW14

AY14

TP2202

1

TP2203

1

TP2205

1

TP2206

1

TP2207

1

TP2208

1

D

C

B

X02

A

5

4

3

2

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

A3

Date: Sheet

Taipei Hsien 221, Taiwan, R.O.C.

RSVD

Hadley 15"

22 10 1Friday, June 28, 201 3

of

22 10 1Friday, June 28, 201 3

of

22 10 1Friday, June 28, 201 3

1

of

SSID = CPU

D

C

B

1

D

C

B

15 OF 19

VSS

2

AV59

AV8

AW16

AW24

AW33

AW35

AW37

AW4

AW40

AW42

AW44

AW47

AW50

AW51

AW59

AW60

AY11

AY16

AY18

AY22

AY24

AY26

AY30

AY33

AY4

AY51

AY53

AY57

AY59

AY6

B20

B24

B26

B28

B32

B36

B4

B40

B44

B48

B52

B56

B60

C11

C14

C18

C20

C25

C27

C38

C39

C57

D12

D14

D18

D2

D21

D23

D25

D26

D27

D29

D30

D31

5

HSW_ULT_DDR3L

VSS

HSW_ULT_DDR3L

AA1

AA58

AB10

AB20

AB22

AB7

AC61

AD21

AD3

AD63

AE10

AE5

AE58

AF11

AF12

AF14

AF15

AF17

AF18

AG1

AG11

AG21

AG23

AG60

AG61

AG62

AG63

AH17

AH19

AH20

AH22

AH24

AH28

AH30

AH32

AH34

AH36

AH38

AH40

AH42

AH44

AH49

AH51

AH53

AH55

AH57

AJ13

AJ14

AJ23

AJ25

AJ27

AJ29

A11

A14

A18

A24

A28

A32

A36

A40

A44

A48

A52

A56

CPU1N

HASW ELL-6-GP

4

14 OF 19

VSS

AJ35

AJ39

AJ41

AJ43

AJ45

AJ47

AJ50

AJ52

AJ54

AJ56

AJ58

AJ60

AJ63

AK23

AK3

AK52

AL10

AL13

AL17

AL20

AL22

AL23

AL26

AL29

AL31

AL33

AL36

AL39

AL40

AL45

AL46

AL51

AL52

AL54

AL57

AL60

AL61

AM1

AM17

AM23

AM31

AM52

AN17

AN23

AN31

AN32

AN35

AN36

AN39

AN40

AN42

AN43

AN45

AN46

AN48

AN49

AN51

AN52

AN60

AN63

AN7

AP10

AP17

AP20

3

HSW_ULT_DDR3L

CPU1O

AP22

VSS

AP23

VSS

AP26

VSS

AP29

VSS

AP3

VSS

AP31

VSS

AP38

VSS

AP39

VSS

AP48

VSS

AP52

VSS

AP54

VSS

AP57

VSS

AR11

VSS

AR15

VSS

AR17

VSS

AR23

VSS

AR31

VSS

AR33

VSS

AR39

VSS

AR43

VSS

AR49

VSS

AR5

VSS

AR52

VSS

AT13

VSS

AT35

VSS

AT37

VSS

AT40

VSS

AT42

VSS

AT43

VSS

AT46

VSS

AT49

VSS

AT61

VSS

AT62

VSS

AT63

VSS

AU1

VSS

AU16

VSS

AU18

VSS

AU20

VSS

AU22

VSS

AU24

VSS

AU26

VSS

AU28

VSS

AU30

VSS

AU33

VSS

AU51

VSS

AU53

VSS

AU55

VSS

AU57

VSS

AU59

VSS

AV14

VSS

AV16

VSS

AV20

VSS

AV24

VSS

AV28

VSS

AV33

VSS

AV34

VSS

AV36

VSS

AV39

VSS

AV41

VSS

AV43

VSS

AV46

VSS

AV49

VSS

AV51

VSS

AV55

VSS

HASW ELL-6-GP

X02

A

5

4

3

2

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

A3

Date: Sheet

Taipei Hsien 221, Taiwan, R.O.C.

CPU (VSS)

Hadley 15"

23 10 1Friday, June 28, 201 3

of

23 10 1Friday, June 28, 201 3

of

23 10 1Friday, June 28, 201 3

1

of

SSID = KBC

1D05V_S0

D

Layout Note:

Need very close to EC

C2412

SCD1U10V2KX- 5GP

C

LCD_TST_EN[52]

LCD_TST[52]

Don't PD

ALL_SYS_PWRGD assert, delay 10ms;

B

PCH_PWROK assert.

ALL_SYS_PWRGD assert, delay 100ms; SYS_PWROK assert.

LVDS backlight Control from PS8625

eDP backlight Control from PCH

LVDS_R2136_BKLT _EN[53]

Backlight Control from LVDS Converter

AOAC Ambient temperature detect

A

NTC-10K-26- GP

69.60037.011

0R0402-PAD-2- GP

3D3V_S0

1

2

L_BKLT_EN[15]

VBAT

R2441

EC_AGND

R2401

2

1

C2413

SC2D2U6D3V2MX-GP

C2413

SC2D2U6D3V2MX-GP

1

DY

2

1

R2417 0R0402-PAD-2-GP

R2444

1

0R2J-2-GP

R2446

1

0R2J-2-GP

1

R2437

10KR2F-2-GP

2

C2419

1

SCD1U10V2KX-5GP

EC_AGND

2

eDP

LVDS

C2420

SC100P50V2JN-3GP

5

EC_VTT

1

2

C2401

SCD1U10V2KX-5GP

C2414 SCD1U10V2KX-5GP

EC_FB_CLAMP_T GL_REQ#[76]

2

1

2

AMB_TEMP

1

2

5

AD_IA[44]

PM_SLP_SUS#[17,38]

BOOST_MON[44]

USBCHARG ER_CB0[35]

IMVP_PWRGD[7,46]

PM_LAN_ENABLE[30]

RTCRST_O N[19]

USBCHG_EN[35]

ALL_SYS_PWRG D[36]

PWR_CH G_AD_OFF[42]

FAN_TACH 1[26]

PM_PWRBT N#[17,96]

EC_FB_CLAMP[75,76,83]

PM_SLP_S3#[17,36,48,49, 51]

EC_BRIGHTN ESS[52]

KB_BL_CTRL[62]

KBC_DPW ROK[17]

CHG_AMBER_L ED#[61]

PCH_PW ROK[17,26,3 6]

USB_PWR _EN#[35]

AC_PRESENT[17,76]

SYS_PWROK[17,96]

AOAC_WLA N_EN[58]

WIFI_RF_EN[58]

PM_SUSWA RN#[17]

DGPU_PW ROK[15,82,83]

PM_CLKRUN #_EC[17]

R2445

100KR2J-1-GP

1

100.0K

10.0K(64.10025.6DL)

13.7K(64.13725.6DL)

17.8K(64.17825.6DL)

22.1K(64.22125.6DL)

27.0K(64.27025.6DL)

32.4K(64.32425.6DL)

37.4K(64.37425.6DL)

43.2K(64.43225.6DL)

57.6K(64.57625.6DL)

64.9K(64.64925.6DL)

73.2K(64.73225.6DL) 1.905V

82.5K(64.82525.6DL) 1.808V

93.1K(64.93125.6DL)

107K(64.10735.6DL)

120K(64.12035.6DL)

137K(64.13735.6DL)

154K(64.15435.6DL)

200K(64.20035.6DL) 1.099V

232K(64.23236.6DL)

X01 0321

R24080R0402- PAD-2-GP

2

1

R24090R0402- PAD-2-GP

2

1

R24100R0402- PAD-2-GP

2

1

R2426 100KR2J-1-GP

2

1

R2411 100KR2J-1-GP

2

1

RN2401

3

4

SRN4K7J-8-G P

R2418 10KR2J-3-GP

1

R2413 100KR2J-1-GP

2

1

DY

R2414 100KR2J-1-GP

2

1

R2424 100KR2J-1-GP

2

1

DY

R2415 10KR2J-3-GP

2

1

R2421 100KR2J-1-GP

1

3D3V_AUX_S5

S

G

D

3D3V_AUX_KBC

D

Wistron Corporation

21F, 88, Sec.1, Hsin T ai Wu Rd., H sichih,

Taipei Hsie n 221, Taiwan, R.O.C.

KBC Nuvoton NPCE985

Hadley 15"

1

3D3V_AUX_KBC

2

1

2

3D3V_AUX_KBC

3D3V_S0

3D3V_S5

2

3D3V_AUX_KBC

24 101

EC_SCI# [ 20]

EC_SMI# [19]

EC_SWI# [20]

1

R2436

10KR2J-3-GP

2

S5_ENABLE

of

3.0V

2.902V

2.801V

2.702V

2.598V

2.492V

2.402V

2.304V

2.201V49.9K(64.49925.6DL)

2.093V

2.001V

1.709V

1.594V

1.499V

1.392V

1.299V

0.994V

D

C

B

A

X02

3.0V

2.75V

2.48V

2.24V

2.0V

1.87V

1.65VReserved

1.204V

0R0402-PAD-2- GP

R2427

1

0R0402-PAD-2- GP

R2430

1

D2401

3

BAT54CPT-2- GP

75.00054.K7D

PSL_OUT#

2

MODEL_ID_DET

3D3V_AUX_S5

2

1

2

1KR2J-1-GP

R2432

1

2

C2403

SCD1U10V2KX- 5GP

2

R2425

330KR2J-L1-GP

1

PSL_IN2#

PSL_IN1#

USB_DET#

KBC_ON#_GAT E_L

2

DY

2

1

EC_AGND

VBAT

1

2

1

R2407

2

3D3V_AUX_S5

R2405

100KR2F-L1-GP

MODEL_ID_DET(GPIO07)

49K9R2F-L-GP

(DOH70)UMA

(DOH50)UMA/eDP

TBD

(DOH70)DIS

TBD

(DOH50)UMA/LVDS

(DOH50)DIS/eDP

TBD TBD TBD TBD TBD TBD TBD TBD

(DOH50)DIS/LVDS

TBD

2

R2431

330KR2J-L1-GP

1

R2433

20KR2J-L2-GP

PULL-LOW RESISTOR PULL-HIGH RESISTOR VOLTAGE

ECSCI#_KBC

ECSMI#_KBC

ECSWI#_KBC

AC_IN_KBC#

USB_DET#

BAT_SCL

BAT_SDA

ECRST#

AC_IN#

BAT_IN#

OVER_CUR RENT_P8#

FAN_TACH 1

LID_CLOSE#

C2417

SCD1U10V2KX- 5GP

2

1

KBC_ON#_GAT E

2

G

Q2402

DMP2130L-7-GP

84.02130.031

2ND = 84.03413.A31

Q2403

G

S

2N7002K-2-GP

84.2N702.J31

2ND = 84.2N702.031

3rd = 84.07002.I31

4th = 84.2N702.W31

Title

Size Document Num ber Rev

A2

Friday, June 28, 2013

Date: Sheet

4

VBAT

R2402

VBAT

3D3V_AUX_KBC _VCC

C2405

SC2D2U6D3V2MX-GP

C2405

SC2D2U6D3V2MX-GP

1

C2404

2

DY

SCD1U10V2KX-5GP

EC_AGND

19

46

76

88

115

102

4

EC_VTT

12

2

1

DY

PSID_EC[42]

FAN1_DAC_1[26 ]

AD_IA_HW[44]

BAT_SCL[43,44,53]

BAT_SDA[43,44,53]

SML1_CLK[18,26,76]

SML1_DATA[18,26,76]

TPCLK[62]

TPDATA[62]

AD_IA_HW2[44]

BLON_OUT[52]

PWRLED #[61]

KBC_BEEP[27]

AC_IN_KBC#[42]

LAN_WAKE#[30]

DIS_DTM[44]

E51_TxD[58]

AMP_MUTE#[27]

PCB_VER_AD

AMB_TEMP

MODEL_ID_DET

PROCHOT _EC

LCD_TST_EN

ECSWI#_KBC

L_BKLT_EN_EC

97

98

99

100

108

96

95

94

101

105

106

107

70

69

67

68

119

120

24

28

26

123

72

71

10

11

25

27

31

117

63

64

32

118

62

65

22

16

81

66

104

110

112

84

83

82

79

124

121

111

9

8

30

EC_GPIO47 High Active

PROCHOT _EC

1

R2442

100KR2J-1-GP

DY

2

R2402

2

0R0603-PAD-2- GP-U

1

C2406

C2407

DY

2

SCD1U10V2KX-5GP

KBC24

VCC

AVCC

VDD

KBSOUT0/GPOB0/SOUT_CR/JENK#

VTT

GPIO90/AD0

GPIO91/AD1

GPIO92/AD2

GPIO93/AD3

GPIO5/AD4

GPIO4/AD5

GPIO3/EXT_PURST#/AD6

GPIO7/AD7/VD_IN2

GPIO94/DA0

GPIO95/DA1

GPIO96/DA2

GPIO97/DA3

GPIO17/SCL1/N2TCK

GPIO22/SDA1/N2TMS

GPIO73/SCL2/N2TCK

GPIO74/SDA2/N2TMS

GPIO23/SCL3/N2TCK

GPIO31/SDA3/N2TMS

GPIO47/SCL4/N2TCK

GPIO53/SDA4/N2TMS

GPIO51/TA3/N2TCK

GPIO67/N2TMS

GPIO37/PSCLK1

GPIO35/PSDAT1

GPIO26/PSCLK2

GPIO27/PSDAT2

GPIO50/PSCLK3/TDO

GPIO52/PSDAT3/RDY#

GPIO56/TA1

GPIO20/TA2/IOX_DIN_DIO

GPIO14/TB1

GPIO1/TB2

GPIO15/A_PWM

GPIO21/B_PWM

GPIO13/C_PWM

GPIO32/D_PWM

GPIO45/E_PWM

GPIO40/F_PWM/1_WIRE

GPIO66/G_PWM

GPO33/H_PWM/VD1_EN#

GPIO80/VD_IN1

GPIO82/IOX_LDSH/VD_OUT1

GPIO84/IOX_SCLK/VD_OUT2

GPIO77/SPI_MISO

GPIO76/SPI_MOSI

GPIO75/SPI_SCK

GPIO2/SPI_CS#

GPIO10/LPCPD#

GPIO85/GA20

GPIO83/SOUT_CR

GPIO65/SMI#

GPIO11/CLKRUN#

GPIO55/CLKOUT/IOX_DIN_DIO

NPCE985PA0DX -1-GP

71.00985.C0G

R2438

0R2J-2-GP

2

1

DY

Q2401

G

D

S

2N7002K-2-GP

84.2N702.J31

2ND = 84.2N702.031

3rd = 84.07002.I31

4th = 84.2N702.W31

1

C2408

2

SCD1U10V2KX-5GP

KBSIN0/GPIOA0/N2TCK

KBSIN1/GPIOA1/N2TMS

KBSOUT1/GPIOB1/TCK

KBSOUT2/GPIOB2/TMS

KBSOUT3/GPIOB3/TDI

KBSOUT4/GPOB4/JEN0#

KBSOUT5/GPIOB5/TDO

KBSOUT6/GPIOB6/RDY#

KBSOUT9/GPOC1/SDP_VIS#

KBSOUT10/P80_CLK/GPIOC2

KBSOUT11/P80_DAT/GPIOC3

KBSOUT12/GPO64/TEST#

KBSOUT13/GPI/O63/TRIST#

KBSOUT14/GPI/O62/XORTR#

KBSOUT15/GPIO61/XOR_OUT

GPIO81/F_WP#/F_SDIO2

GPIO0/EXTCLK/F_SDIO3

PSL_IN2#/GPI6/EXT_PURST#

GPIO46/CIRRXM/TRST#

GPIO87/CIRRXM/SIN_CR

H_PROCHO T#_EC

4

2D2R3-1-U- GP

1

C2409

DY

2

SCD1U10V2KX-5GP

KBSIN2/GPIOA2

KBSIN3/GPIOA3

KBSIN4/GPIOA4

KBSIN5/GPIOA5

KBSIN6/GPIOA6

KBSIN7/GPIOA7

KBSOUT7/GPIOB7

KBSOUT8/GPIOC0

GPIO60/KBSOUT16

GPIO57/KBSOUT17

LAD0/GPIOF1

LAD1/GPIOF2

LAD2/GPIOF3

LAD3/GPIOF4

LCLK/GPIOF5

LFRAME#/GPIOF6

LRESET#/GPIOF7

GPIO30/F_WP#

GPIO41/F_WP#

F_SDIO/F_SDIO0

F_SDI/F_SDIO1

PSL_IN1#/GPI70

PSL_OUT#/GPIO71

ECSCI#/GPIO54

EXT_RST#

KBRST#/GPIO86

SERIRQ/GPIOF0

GPIO36/TB3

GPIO44/TDI

GPIO43/TMS

GPIO42/TCK

GPIO34/CIRRXL

1

0R0402-PAD-2- GP

C2410

F_CS0#

F_SCK

VSBY

VBKUP

VCORF

GPIO24

AGND

R2440

1

2

PECI

GND

3D3V_AUX_KBC

2

R2403

1

2

54

55

56

57

58

59

60

61

53

52

51

50

49

48

47

43

42

41

40

39

38

37

36

35

34

33

126

127

128

1

2

3

7

90

92

109

80

87

86

91

77

73

93

74

29

85

122

75

114

44

13

125

6

15

21

20

17

23

113

14

5

18

45

78

89

116

103

2

1

2

SCD1U10V2KX- 5GP

C2411

SC2D2U6D3V2MX-GP

KROW0

KROW1

KROW2

KROW3

KROW4

KROW5

KROW6

KROW7

KCOL0

KCOL1

KCOL2

KCOL3

KCOL4

KCOL5

KCOL6

KCOL7

KCOL8

KCOL9

KCOL10

KCOL11

KCOL12

KCOL13

KCOL14

KCOL15

KCOL16

USB_DET#

LPC_AD0

LPC_AD1

LPC_AD2

LPC_AD3

PLT_RST#_EC

EC_SPI_CS#_C

EC_SPI_CLK_C

EC_SPI_DI_C

EC_SPI_DO_C

PSL_IN1#

PSL_IN2#

PSL_OUT#

ECSCI#_KBC

ECRST#

EC_VBKUP

KBC_VCORF

PECI

ECSMI#_KBC

ME_UNLOCK [19]

WIFI_WAKE# [58]

S5_ENABLE [36]

EC_AGND

H_PROCHO T# [4,42,44,46]

C2421

SC47P50V2JN-3G P

VBAT

A00 0618

1

R2404

64K9R2F-1-GP

PCB_VER_AD

1

2

1

R2406

2

100KR2F-L1-GP

C2402

X01 0321

R2435

0R0402-PAD-2- GP

100KR2F-L1-GP

DY

2

1

EC_AGND

KROW[0..7] [62]

KCOL[0..16] [62]

LPC_AD[3..0] [18,65]

CLK_PCI_KBC [18]

LPC_FRAME# [18,65]

R2419 0R0 402-PAD-2-GP

2

1

R2412 33R 2J-2-GP

2

1

R2420 0R0 402-PAD-2-GP

2

1

R2422 0R0 402-PAD-2-GP

2

1

Layout Note:

Need very close to EC

H_RCIN# [20]

R2428 0R0 402-PAD-2-GP

2

1

INT_SERIRQ [20]

OVER_CUR RENT_P8# [76]

PM_SLP_S4# [17,49]

RSMRST#_KBC [17]

LID_CLOSE# [61]

D2402

1

2

CH751H-40PT -GP

83.R0304.A8F

Layout Note:

Connect GND and AGND planes via either 0R resistor or connect directly.

3

PCB VERSION A/D(PIN98) PULL-LOW RESISTOR PULL-HIGH RESISTOR VOLTAGE

X00

X01

X02

X03

A00

Reserved

Reserved 100.0K 215.0K 1.048V

SPI_CS0#_R [18,25]

SPI_CLK_R [18,25]

CAP_LED# [62]

BAT_IN# [42,43,44]

SPI_SI_R [18,25 ]

SPI_SO_R [18,25]

PM_SUSACK# [17]

PCH_SUSCL K_KBC [17]

3D3V_AUX_S5

RTC_AUX_S5

1

DY

2

PURE_HW _SHUTDOW N#[26,36,76]

C2416 SC1U6D 3V2KX-GP

1

2

1

R2429

43R2J-GP

C2422

SC100P50V2JN-3 GP

TOUCH_PAN EL_INTR# [5 2]

3

2

100.0K

100.0K 1.358V

100.0K

A00 0618

0R0402-PAD-2- GP

R2416

2

1

SC220P50V2KX-3GP

C2415

DY

2

H_PECI [4]

Layout Note:

Need very close to EC C2422 PDG is 47p

3D3V_AUX_S5

1

R2439

10KR2J-3-GP

1

0R2J-2-GP

2

MMBT3906-4-GP

84.T3906.A11

2nd = 84.03906.F11

R2434

DY

Q2404

B

10.0K

20.0K

33.0K

47.0K

64.9K

76.8

100.0K

143.0K

174.0KReserved

PLT_RST# [17,30,58,65,73]

KBC_PWR BTN#[61]

USBDET_CO N#[34]

2

1

E

DY

2

C

AC_IN#[44]

ECRST#

C2418

SC1U6D3V2KX-GP

5

SSID = Flash.ROM

D

R2501

4K7R2J-2 -GP

3D3V_S5

2

1

4

SPI Flash ROM(8M) for PCH

4

3

RN2501

SRN4K7J -8-GP

DY

2

1

DY

3

3D3V_S5

C2501

SC10U6D3V3MX-GP

C2501

SC10U6D3V3MX-GP

1

C2502

SCD1U10 V2KX-5GP

2

SCD1U10 V2KX-5GP

2

Single SPI shared flash connection (SPI Quad I/O mode)

2

1

D

C

SSID = RBATT

B

SPI_CS0#_ R[18,24]

SPI_SO_R[1 8,24]

SPI_WP #[18]

EC2502

SC4D7P5 0V2CN-1GP

EC2502

DY

SPI25

1

CS#

2

DO/IO1

3

WP#/IO2

4

1

2

AFTP250 2

RTC1

PWR

GND

NP1

NP2

GND

W25 Q64FVSSIQ-GP

72.25Q64.K01

+RTC_VC C

1

2

NP1

NP2

HOLD#/IO3

+RTC_VC C

VCC

CLK

DI/IO0

3D3V_S5

8

7

6

5

1

EC2503

EC2501

SC4D7P5 0V2CN-1GP

Source

DY

EC2503

DY

SC10P50 V2JN-4GP

2

QUAD/DUAL fast read DUAL fast read

72.25Q64.K01

72.25647.00A O O

1KR2J-1-G P

R2502

2

3D3V_AU X_S5

RTC_PW R

1

A00 0619

D2501

2

1

BAS40CW -GP

83.00040.E81

SPI_HOLD# [18]

SPI_CLK_R [18,2 4]

SPI_SI_R [18,24]

O O

RTC_AUX _S5

3

2

C2503

SC1U6D3 V2KX-GP

1

C

Refer to "NCPE985x/ NPCE995x board design reference guide"

B

BAT-AAA-B AT-054-P06-GP-U

62.70001.061

A

5

4

AFTP250 1

1

Q2505

1

R2504

10MR2J-L -GP

2

G

S

2N7002K -2-GP

84.2N702.J31

2ND = 84.2N702.031

3rd = 84.07002.I31

4th = 84.2N702.W31

D

3

RTC_DET # [20]

2

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

A3

Friday, June 28, 201 3

Date: Sheet

Flash/RTC

Hadley 15"

Taipei Hsien 221, Taiwan, R.O.C.

25 10 1

of

25 10 1

of

25 10 1

1

of

X02

A

5

SSID = Thermal

4

3

2

1

D

3D3V_S0

C2601

1

2

84.03904.L06

2ND = 84.03904.P11

C

3

1

Q2603

PMBS390 4-1-GP

2

NCT7718 _DXP

1

C2606

SC470P5 0V3JN-2GP

2

DY

NCT7718 _DXN

2.System Sensor, Put on palm rest

Layout Note:

C2812 close U28 01

Layout Note:

Both DXN and DX P routing 10 m il trace width and 10 mil spa cing.

3D3V_S0

R2603 18K7R2F-GP

B

R2603 18K7R2F-GP

R2604 2KR2F-3-GP

2

1

2

1

Fan controller1

R2605

0R2J-2-GP

3D3V_S0

SC10U6D3V3MX-GP

1

C2602

2

SCD1U10V2KX-5GP

1

C2607

SC2200P 50V2KX-2GP

2

A00 0618

1

R2601

0R0402-P AD-2-GP

2

ALERT#

T_CRIT#

SML1_DA TA[18,24,76]

SML1_CL K[18,2 4,76]

THM26

1

VDD

2

D+

T_CRIT#

3

4

D-

T_CRIT#

NCT7718 W-GP

74.07718.0B9

ALERT#

1204 change to PCH_PWROK

PCH_PW ROK[17,24,36 ]

THERM_S YS_SHDN#

SCL

SDA

GND

6

5

4

Q2601

2N7002K DW-GP

8

7

ALERT#

6

5

G

S

3D3V_S0

1

2

3

Q2602

D

2N7002K -2-GP

84.2N702.J31

2ND = 84.2N702.031

3rd = 84.07002.I31

4th = 84.2N702.W31

2

1

RN2602

SRN2K2J -1-GP

4

3

84.2N702.A3F

2nd = 84.DM601.03F

3rd = 84.2N702.E3F

4th = 84.2N702.F3F

1

DY

C2608

2

SCD1U10V2KX-5GP

1

C2610

DY

SCD1U10 V2KX-5GP

2

THM_SML 1_DATA

THM_SML 1_CLK

THM_SML 1_DATA

C2609

SCD1U10V2KX-5GP

Layout Note:

Signal Routing Guideline: Trace width = 15mil

PURE_HW _SHUTDOW N# [2 4,36,76]

FAN1_DA C_1[24]

Layout Note:

Need 10 mil tra ce width.

0R2J-2-GP

1

DY

5V_S0

FAN_VCC _1

FAN_TAC H1[2 4]

C2604

SC4D7U6 D3V3KX-GP

C2604

FON#

2

1

DY

2

FAN261

1

FSM#

2

VIN

3

VOUT

4

VSET

APL5606 AKI-TRG-GP

74.05606.A71

2nd = 74.02113.0E1

0R0402-P AD-2-GP

R2606

1

2

D2601

DY

1

CH551H-3 0PT-GP

83.R5003.C8F

2ND = 83.R5003.H8H

3rd = 83.5R003.08F

GND

FAN_TAC H1_C

2

FAN_VCC _1

1

C2603

DY

2

SC2200P50V2KX-2GP

8

7

6

5

FAN_TAC H1

FAN_VCC _1

ETY-CON3-8-GP

20.F1841.003

5V_S0

1

2

FAN1

4

1

2

3

5

AFTP260 1

1

AFTP260 2

1

C2611

C2605

2

SCD1U10V2KX-5GP

D

SC4D7U6D3V3KX-GP

C

B

X02

A

5

4

3

2

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

Title

Thermal NCT7718W/Fan

Size Document N umber Rev

A3

Friday, June 28, 201 3

Date: Sheet

Hadley 15"

Taipei Hsien 221, Taiwan, R.O.C.

26 10 1

of

26 10 1

of

26 10 1

1

of

5

SSID = AUDIO

4

3

2

1

AGND

LINE1_VREFO_R[29]

LINE1_VREFO_L[29]

D

C

A00 0618

3D3V_S0

5V_S0

25mA

1

R2701

0R0402-PAD-2-GP

A00 0618

1.5A

0R0805-PAD-2-GP-U

R2702

2

0R0805-PAD-2-GP-U

R2704

2

DGND

3D3V_S0

A00 0618

1D5V_S0

0R0402-PAD-2-GP

1

R2710 0R2J-2-GP

1

R2705

DY

Azalia I/F EMI

EC2701

SCD1U10V2KX-5GP

2

DY

2

DY

EC2702

SC22P50V2JN-4GP

B

SC22P50V2JN-4GP

+3V_AVDD

2

+5V_PVDD

1

C2706

1

2

Layout Note:

Close pin41

AGND

2

PCH_AZ_CODEC_SDOUT1

1

HDA_CODEC_BITCLK_C

1

C2701

SC4D7U6D3V3KX-GP

2

Close pin36

C2707

1

2

SCD1U10V2KX-5GP

SC4D7U6D3V3KX-GP

+3V_1D5V_AVDD

1

C2715

SC4D7U6D3V3KX-GP

2

AUD_AGND

47R2J-2-GP

2

1

ER2702

47R2J-2-GP

C2708

C2709

1

2

SCD1U10V2KX-5GP

SC4D7U6D3V3KX-GP

Layout Note:

Close pin46

Close pin40

ER2701

HDA_CODEC_SDOUT

1

DY

HDA_CODEC_BITCLK

2

DY

AUD_AGND

AMP_MUTE#[24]

C2712 SC10U6D3V3MX-GP

2

1

AUD_SPK_L+[29]

AUD_SPK_L-[29]

AUD_SPK_R-[29]

AUD_SPK_R+[29]

0R0402-PAD-2-GP

R2708

2

1

remove D2702 R2710 R2711 Add R2708_0R(PDB pin)

TP2702

DMIC_CLK[52]

SC22P50V2JN-4GP

Close pin3

0109 Add Close pin2

C2723

DMIC_DATA[52]

2

DY

1

HDA_CODEC_SDOUT[19]

HDA_CODEC_BITCLK[19]

HDA_SDIN0[19]

HDA_CODEC_SYNC[19]

HDA_CODEC_RST#[19,29]

SC22P50V2JN-4GP

C2724

2

1

DY

+3V_1D5V_AVDD

+5V_PVDD

AUD_SPK_L+

AUD_SPK_L-

AUD_SPK_R-

AUD_SPK_R+

+5V_PVDD

1

SC4D7U6D3V3KX-GP

AUD_HP1_JACK_L[29]

AUD_HP1_JACK_R[29]

1

C2703

SC1U6D3V2KX-GP

2

CBP

LDO2_CAP

EAPD#

COMBO-GPI

C2716

A00 0618

0R0402-PAD-2-GP

R2714

1

R2716

1

0R0402-PAD-2-GP

+3V_AVDD

HDA27

37

CBP

38

AVSS2

39

LDO2_CAP

40

AVDD2

41

PVDD1

42

SPK_L+

43

SPK_L-

44

SPK_R-

45

SPK_R+

46

PVDD2

47

PDB

48

SPDIFO/GPIO2

49

GND

ALC3223-CG-GP

+3V_AVDD

1

C2717

2

SCD1U10V2KX-5GP

DMIC_DATA_R

2

DMIC_CLK_R

2

0R0402-PAD-2-GP

R2718

1

HDA_CODEC_SYNC

HDA_CODEC_RST#

SC1U6D3V2KX-GP

C2704

2

1

CBN

36

35

CBN

CPVDD

GPIO0/DMIC_DATA

DVDD

2

1

2

CPVEE

34

33

32

31

CPVEE

HP_OUT_L

HP_OUT_R

SDATA_OUT

DVSS

GPIO1/DMIC_CLK

6

5

4

3

HDA_CODEC_SDIN0

C2705

1

SC2D2U6D3V2MX-GP

2

LDO1_CAP

AUD_VREF

30

29

28

27

VREF

LDO1_CAP

MIC2_VREFO

LINE1_VREFO_L

LINE1_VREFO_R

SYNC

DVDD_IO

SDATA_IN

LDO3_CAP

BIT_CLK

9

8

7

10

LDO3_CAP

C2718SC4D7U6D3V3KX-GP

1

C2719SCD1U10V2KX-5GP

2

MIC2_VREFO [29]

C2702

SC4D7U6D3V3KX-GP

26

25

AVSS1

AVDD1

LINE2_L

LINE2_R

LINE1_L

LINE1_R

CPVREF

MIC_CAP

MIC2_R/SLEEVE

MIC2_L/RING2

MONO_OUT

JDREF

SENSE_B

SENSE_A

PCBEEP

RESET#

12

11

AUD_PC_BEEP

+3V_AVDD

AUD_AGND

+5V_AVDD

AUD_AGND

24

23

22

21

20

19

18

17

16

15

14

13

C2713 SC10U6D3V3MX-GP

MIC_CAP

R2707 20KR2F-L-GP

JDREF

AUD_SENSE_A

Layout Note:

AGND

Place close to Pin 13

DGND

1

C2710

2

SCD1U10V2KX-5GP

LINE1_L [29]

LINE1_R [29]

1

SLEEVE [29]

RING2 [29]

1

R2709

39K2R2F-L-GP

C2711

2

AGND

+5V_AVDD

1

0R0603-PAD-2-GP-U

1

Layout Note:

2

Place close to Pin 26

AUD_AGND

SC4D7U6D3V3KX-GP

2

AUD_SENSE

2

DGND

5V_S0

A00 0618

R2703

2

AUD_AGND

Layout Note:

Width>40mil, to improve Headpohone Crosstalk noise

AUD_AGND

AUD_SENSE [29]

AUD_AGND

DGND

EC2708 SCD1U10V2KX-5GP

EC2707 SCD1U10V2KX-5GP

EC2706 SCD1U10V2KX-5GP

EC2705 SCD1U10V2KX-5GP

EC2704 SCD1U10V2KX-5GP

EC2703 SCD1U10V2KX-5GP

2

1

DY

2

1

2

1

2

1

2

1

DY

2

1

Layout Note:

Tied at point only under Codec or near the Codec

AGND

R2711 0R0603-PAD-2-GP-U

R2706 0R0603-PAD-2-GP-U

DGND

2

1

2

1

Layout Note:

Tied at point only under Codec or near the Codec

D

C

B

RN

HDA_SPKR_R

4

HDA_SPKR[20]

KBC_BEEP[24]

A

5

4

1

2

0R4P2R-PAD

RN2701

3

KBC_BEEP_R

D2701

1

2

BAT54CPT-2-GP

75.00054.K7D

2nd=75.00054.J7D

3

AUD_PC_BEEP_C

3

1

R2717

1KR2J-1-GP

2

AUD_PC_BEEP

2

1

C2720

SCD1U10V2KX-5GP

A

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

Audio Codec ALC3223

Hadley 15"

Taipei Hsien 221, Taiwan, R.O.C.

of

27 101Friday, June 28, 2013

of

27 101Friday, June 28, 2013

of

27 101Friday, June 28, 2013

1

X02

5

4

3

2

1

D

C

D

C

(Blanking)

B

X02

A

5

4

3

2

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

A3

Date: Sheet

Hadley 15"

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

1

28 10 1Friday, June 28, 201 3

of

28 10 1Friday, June 28, 201 3

of

28 10 1Friday, June 28, 201 3

of

5

SSID = AUDIO

4

3

2

1

A00 0618

R29040R0603-P AD-2-GP-U

2

D

C

RN2901

SRN2K2J -1-GP

4

LINE1_L_C

2

LINE1_R_C

2

1

3

2

R2908 10R2F-L -GP

R2921 1KR2J-1 -GP

R2912 2K2R2J -2-GP

R2910 10R2F-L -GP

R2922 1KR2J-1 -GP

R2913 2K2R2J -2-GP

2

1

2

1

2

1

2

1

2

1

2

1

MIC2_VREF O[27]

RING2[27 ]

AUD_HP1 _JACK_L[27]

LINE1_L[27]

LINE1_VRE FO_L[27]

AUD_SEN SE[2 7]

AUD_HP1 _JACK_R[27]

LINE1_R[27]

LINE1_VRE FO_R[27]

SLEEVE[2 7]

B

C2907

1

SC4D7U6 D3V3KX-GP

C2908

1

SC4D7U6 D3V3KX-GP

AUD_SPK _R+[27 ]

AUD_SPK _R-[27]

AUD_SPK _L+[27]

AUD_SPK _L-[27]

AUD_HP1 _JACK_L1

AUD_HP1 _JACK_R1

1

DY

EC2901

SC2K2P50V3KX-GP

1

DY

EC2903

EC2902

2

SC2K2P50V3KX-GP

1

DY

EC2904

2

SC2K2P50V3KX-GP

A00 0618

2

EC2905

SC100P50V2JN-3GP

EC2905

SC100P50V2JN-3GP

EC2906

SC100P50V2JN-3GP

EC2906

EC2908

SC100P50V2JN-3GP

EC2908

SC100P50V2JN-3GP

EC2907

SC100P50V2JN-3GP

EC2907

R2919

10KR2J-3-GP

R2919

10KR2J-3-GP

SC100P50V2JN-3GP

1

2

AUD_AGN D

SC100P50V2JN-3GP

R2920

10KR2J-3-GP

R2920

10KR2J-3-GP

1

2

1

2

AUD_AGN D

DY

1

2

1

2

1

2

1

2

1

R29060R0603-P AD-2-GP-U

1

R29070R0603-P AD-2-GP-U

1

R29090R0603-P AD-2-GP-U

1

R29110R0603-P AD-2-GP-U

1

AUD_SPK _R+_C

R29030R0603-P AD-2-GP-U

AUD_SPK _R-_C

R29020R0603-P AD-2-GP-U

AUD_SPK _L+_C

R29010R0603-P AD-2-GP-U

AUD_SPK _L-_C

AUD_POR TA_L_R_B

AUD_POR TA_R_R_B

SLEEVE_ R

AUD_AGN D

RING2_R

Speaker

1

2

3

4

ACES-CON 4-7-GP-U

20.F0772.004

AUD_SPK _L-_C

AUD_SPK _L+_C

AUD_SPK _R-_C

AUD_SPK _R+_C

Universal jack

AUD_AGN D

AUD_POR TA_L_R_B

AUD_POR TA_R_R_B

AUD_SEN SE

SPK1

5

6

HPMIC1

3

1

5

6

2

4

MS

AUDIO-JK40 4-GP

22.10270.V01

1

AFTP290 6

AFTP290 7

AFTP290 8

AFTP290 9

AFTP290 1

AFTP290 2

AFTP290 3

AFTP290 4

CONN Pin

Pin1

Pin2

Pin3

Pin4

D

Net name

SPK_R+

SPK_R-

SPK_L+

SPK_L_

C

B

R2918

100KR2J -1-GP

D

3

GG

2

S

1

3

+3V_AVD D

POP_G2

1

DY

2

1

C2901

DY

SC1U6D3 V2KX-GP

2

0R0402-P AD-2-GP

R2917

2

1

HDA_COD EC_RST# [19 ,27]

SLEEVE [27]

2

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

Title

Speaker/HPMIC CONN

Size Document N umber Rev

A3

Date: Sheet

Speaker/HPMIC CONN

Hadley 15"

Taipei Hsien 221, Taiwan, R.O.C.

29 10 1Friday, June 28, 201 3

of

29 10 1Friday, June 28, 201 3

of

29 10 1Friday, June 28, 201 3

1

of

X02

A

AUD_POR TA_R_R_B

AUD_POR TA_L_R_B

RING2_R

AUD_SEN SE

SLEEVE_ R

ED2901

AZ2025-01H-R7G-GP

ED2901

AZ2025-01H-R7G-GP

1

A

DY

75.02025.077

2

75.02025.077

ED2902

AZ2025-01H-R7G-GP

ED2902

AZ2025-01H-R7G-GP

1

DY

2

75.02025.077

5

DY

1

2

ED2903

AZ2025-01H-R7G-GP

ED2903

AZ2025-01H-R7G-GP

75.02025.077

DY

1

2

ED2904

AZ2025-01H-R7G-GP

ED2904

AZ2025-01H-R7G-GP

75.02025.077

DY

ED2905

AZ2025-01H-R7G-GP

ED2905

AZ2025-01H-R7G-GP

1

2

4

5V_PW R_2

1

2

AUD_AGN D

R2915

220KR2J -L2-GP

POP_G1

U2901

S

4

5

D

6

2N7002K DW-GP

SSID = LOM

D

PM_LAN_ ENABLE[2 4]

100KR2J -1-GP

3D3V_LA N_S5

C

1

C3007

SCD1U10V2KX-5GP

2

B

REGOUT

DY

A

5

3D3V_S5

1

2

Q3001

G

1

R3023

DY

S

2N7002K -2-GP

2

R3006 0R0603-PAD -2-GP-U

1

C3008

C3012

SCD1U10V2KX-5GP

2

1

A00 0618

R3034 0R0603-PAD -2-GP-U

C3018

1

SCD1U10V2KX-5GP

2

1

L3010

1

IND-4D7UH-2 42-GP

LAN_SW

68.4R71E.10G

2

LAN_SW

X5R

5

C3013

SCD1U10V2KX-5GP

D

LAN_ENABLE_R_C

LAN_SW

C3024

1

SC4D7U6D3V3KX-GP

2

1

R3021

10KR2J-3 -GP

R3022

2

20KR2F-L -GP

1

C3009

SCD1U10V2KX-5GP

2

C3014

1

LAN_SW

SCD1U10V2KX-5GP

2

VDDREG

LAN_SW

1

C3010

SC4D7U6D3V3KX-GP

2

X5R

A00 0618

0R0603-P AD-2-GP-U

1

4

PA102FM G-GP-U

Q3004

S

1

2

PM_LAN_ ENABLE_R

main: 84.00102.031 2nd: 84.03403.031

G

C3003

SC1U6D3 V2KX-GP

0311 modify power railA00 0618

3D3V_LA N_S5

R3007

2

1

C3019

SCD1U10V2KX-5GP

2

4

D

1

R3039

10KR2J-3 -GP

2

LAN_W AKE#

VDD10

C3020

SCD1U10V2KX-5GP

3D3V_LA N_S5

1

C3021

SCD1U10V2KX-5GP

2

EVDD10

1

C3016

SCD1U10V2KX-5GP

2

1

DY

C3005

SCD1U10V2KX-5GP

2

Pin12 Pull VCC33 (3D3V_S0) Supported RTD3

1

C3022

SCD1U10V2KX-5GP

2

1

C3023

SC1U6D3V2KX-GP

2

ENSW REG

CLK_PCIE_ LAN_REQ4#[18]

LANXOUT

LANXIN

LAN_W AKE#[24]

3

4

2

1

C3001

1

SC15P50 V2JN-2-GP

3D3V_LA N_S5

1

LAN_SW

2

1

2

0110 add CAP need close to chip

3D3V_S0

1

2

LAN_TXP _C_PCH_RXP4

LAN_TXN _C_PCH_RXN4

PCIE_PTX_ LANRX_P4_C

PCIE_PTX_ LANRX_N4_C

3

C3011

2

1

SC15P50 V2JN-2-GP

X3001

XTAL-25M HZ-155-GP

2

R3036

0R2J-2-GP

A00 0618

R3037

0R0402-P AD-2-GP

VDD10

EVDD10

3D3V_LA N_S5

C3028

LAN_W AKE#

ISOLATE#

PLT_RST #_LAN

CLK_PCIE_ LAN_P4

CLK_PCIE_ LAN_N4

PCIE_PTX_ LANRX_P4_C

PCIE_PTX_ LANRX_N4_C

LAN_TXP _C_PCH_RXP4

LAN_TXN _C_PCH_RXN4

3D3V_LA N_S5

SCD1U10V2KX-5GP

CARD_3D 3V

VDD33/18

VDDREG

C3025 SCD1U10 V2KX-5GP

1

C3026 SCD1U10 V2KX-5GP

2

CARD_3D 3V_S0

Close To Pin 27

VDD33/18

1

C3017

SCD1U10V2KX-5GP

2

U3001

3

AVDD10

8

AVDD10

46

AVDD10

33

DVDD10

20

EVDD10

11

AVDD33

48

AVDD33

12

DVDD33

32

DVDD33

13

CARD_3V3

27

VDD33/18

35

VDDREG

39

LANWAKE#

31

ISOLATE#

29

CLKREQ#

30

PERST#

23

REFCLK_P

24

REFCLK_N

21

HSIP

22

HSIN

25

HSOP

26

HSON

RTL8411 B-CGT-GP

71.08411.D03

2

SD_D2/MS_CLK

SD_CLK/MS_D0

SD_SMD/MS_D2

SD_WP/MS_BS

PCIE_PRX_ LANTX_P4 [1 6]

PCIE_PRX_ LANTX_N4 [16]

PCIE_PTX_ LANRX_P4_C [16]

PCIE_PTX_ LANRX_N4_C [1 6]

CLK_PCIE_ LAN_P4 [18]

CLK_PCIE_ LAN_N4 [18]

0R0603-P AD-2-GP-U

R3008

1

C3027

SC4D7U6D3V3KX-GP

DY

2

MDIP0

MDIN0

MDIP1

MDIN1

MDIP2

MDIN2

MDIP3

MDIN3

CKXTAL1

CKXTAL2

ENSWREG_H

REGOUT

RSET

LED_CR

LED0

LED1/GPO

LED3

SD_D0/MS_D1

SD_D1

SD_D3/MS_D3

SD_CD#

MS_CD#

GND

2

A00 0618

2

1

2

4

5

6

7

9

10

44

45

34

36

47

40

41

38

37

15

14

19

18

16

17

28

42

43

49

CARD_3D 3V

LANXIN

LANXOUT

ENSW REG

REGOUT

RSET

LED_CR

LED0

LED1

LED3

SP2

SP1

SP6

SP5

SP3

SP4

SP7

Close To Pin 13

1

C3015

SCD1U10V2KX-5GP

DY

2

PLT_RST #[17,24,58,6 5,73]

LAN_MDI0P [31]

LAN_MDI0N [31 ]

LAN_MDI1P [31]

LAN_MDI1N [31 ]

LAN_MDI2P [31]

LAN_MDI2N [31 ]

LAN_MDI3P [31]

LAN_MDI3N [31 ]

R3038

2K49R2F -GP

2

TP3004 T PAD14-OP-GP

1

TP3003 T PAD14-OP-GP

1

TP3002 T PAD14-OP-GP

1

TP3001 T PAD14-OP-GP

1

A00 0618

R3017 0R0402-P AD-2-GP

2

1

R3018 0R0402-P AD-2-GP

2

1

R3019 0R0402-P AD-2-GP

2

1

R3020 0R0402-P AD-2-GP

2

1

R3032 0R0402-P AD-2-GP

2

1

R3033 0R0402-P AD-2-GP

2

1

R3035 0R0402-P AD-2-GP

2

1

Title

Size Document N umber Rev

A3

Date: Sheet

LOM(RTL8411B)

Hadley 15"

1

3D3V_S0

ISOLATE#

2

1

R3014

1KR2J-1-G P

3D3V_LA N_S5

2

1

RN3001

DY

SRN10KJ -5-GP

4

3

Q402_1

1

2

DY

Q3003

PMBS390 4-1-GP

R3016

2

0R0402-P AD-2-GP

1

SP2/SD_D 0/MS_D1 [33]

SP1/SD1 [3 3]

SP6/SD_D 2/MS_CLK [33]

SP5/SD_D 3/MS_D3 [33]

SP3/SD_C LK/MS_D0 [33]

SP4/SD_C MD/MS_D2 [33]

SP7/SD_W P/MS_BS [33]

SD_CD# [33]

MS_CD# [33]

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

1

R3015

15KR2F-G P

3

1

30 10 1Friday, June 28, 201 3

1

DY

2

PLT_RST #_LAN

A00 0618

of

X02

D

C

B

A

Dell INSPIRON 5437, INSPIRON 3437 Schematics

Specifications and Main Features

Frequently Asked Questions

User Manual