Dell Inspiron 1545 Schematic

5

D D

4

3

2

1

DR1 (Roberts) Schematics Document

uFCPGA Mobile Penryn

Intel Cantiga-GM + ICH9M

C C

2008-10-02

REV : A00

B B

DY : Nopop Component

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Custom

Date: Sheet

Taipei Hsien 221, Taiwan, R.O.C.

Cover Page

Roberts

1

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158Thursday, October 02, 2008

A00

5

4

3

2

1

CPU DC/DC

Roberts Block Diagram

ISL6266A

INPUTS

+PWR_SRC

28,29

OUTPUTS

+VCC_CORE

D D

Clock Generator

SLG8SP513VTR

4

Intel Mobile CPU

Penryn

Socket P

5,6,7

Project code : 91.4AQ01.001 PCB P/N : 48.4AQ01.011 Revision : 08212-1

SYSTEM DC/DC

TPS51117

INPUTS

+PWR_SRC

OUTPUTS

+1.05V_VCCP

30

SYSTEM DC/DC

FSB 800/1066MHz

Intel

DDRII 667/800

C C

DDRII 667/800

SD/MMC MS/MS Pro/xD

B B

CAMERA Module

37

Digital Mic Array

MIC IN

Internal Analog MIC

Slot 0

14

Slot 1

15

CardReader

Realtek RTS5158E

Azalia CODEC

IDT 92HD71B7

DDRII 667/800 Channel A

DDR II 667/800 Channel B

USB2.0

21

AZALIA

22

Cantiga-GML

AGTL+ CPU I/F DDR Memory I/F External Graphics

DMIx4

Intel

ICH9-M

USB 2.0/1.1 ports (12) PCI Express ports (6) High Definition Audio

SATA ports (4)

LPC I/F ACPI 1.1

PCI/PCI BRIDGE

8,9,10,11,12,13

C-LINK

16,17,18,19

RGB CRT

LVDS(Dual Channel)

PCIE

USB 2.0

LPC Bus

PCIE x 1

CRT (on I/O board)

LCD

35

PCIE x 1 & USB 2.0 x 1

10/100 NIC

Marvell 88E8040

PCIE x 1

20

USB 2.0 x 2

USB 2.0 x 1

Power SW

G577BR91U

New Card

I/O Board

Connector

41

Mini-Card

802.11a/b/g

CAMERA (Option)

Bluetooth

Right Side: USB x 1

41

37

41

43

RJ45 CONN

Left Side: USB x 2

INPUTS

+PWR_SRC

SYSTEM DC/DC

INPUTS

+PWR_SRC

SYSTEM DC/DC

INPUTS

SYSTEM DC/DC

INPUTS

+5V_ALW +3.3V_ALW

MAXIM CHARGER

INPUTS

+DC_IN +PBATT

PCB LAYER

L1: Top

OUTPUTS

+5V_ALW2 +3.3V_RTC_LDO +5V_ALW +3.3V_ALW

TPS51116

OUTPUTS

+1.8V_SUS +0.9V_DDR_VTT +V_DDR_MCH_REF

APL5912

OUTPUTS

LDO

OUTPUTS

MAX8731A

L2: VCC

MAX17020

HP1

A A

OP AMP

MAX9789A

SATA

23

SATA

2CH SPEAKER

HDD

40

5

4

ODD

36 36

SPI

Flash ROM

2MB

3

WINBOND

WPCE773L

Touch PAD

42 44

44

Int. KB

24

Thermal & Fan

EMC2102

25

Title

Block Diagram

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

Block Diagram

KBC

L3: Signal L4: Signal L5: GND L6: Bottom

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Roberts

1

of

258Thursday, October 02, 2008

+1.5V_RUN+1.8V_SUS

+5V_RUN +3.3V_RUN

OUTPUTS

+PWR_SRC

A00

27

31

32

34

26

A

ICH9M Functional Strap Definitions

Signal

HDA_SDOUT

4 4

HDA_SYNC PCIE config1 bit0,

GNT2#/ GPIO53

GPIO20 Reserved. GNT1#/

GPIO51

GNT3#/ GPIO55

GNT0#: SPI_CS1#/

3 3

GPIO58 SPI_MOSI Integrated TPM Enable,

GPIO49 DMI Termination

SATALED# PCI Express Lane

SPKR

TP3 GPIO33/

HDA_DOCK

2 2

_EN#

Usage/When Sampled

XOR Chain Entrance/ PCIE Port Config1 bit1, Rising Edge of PWROK.

Rising Edge of PWROK.

PCIE config2 bit2, Rising Edge of PWROK.

ESI Strap (Server Only) Rising Edge of PWROK.

Top-Block Swap override. Rising Edge of PWROK.

Boot BIOS Destination Selection 0:1. Rising Edge of PWROK.

Rising Edge of CLPWROK.

Voltage. Rising Edge of CLPWROK.

Reversal. Rising Edge of PWROK.

No Reboot. Rising Edge of PWROK.

XOR Chain Entrance. Rising Edge of PWROK.

Flash Descriptor Security Override Strap. Rising Edge of PWROK.

Allows entrance to XOR Chain testing when TP3 pulled low. When TP3 not pulled low at rising edge of PWROK, sets bit1 of RPC.PC (Cofig Registers: offset 224h). This signal has weak internal pull-down.

This signal has a weak internal pull-down. Sets bit0 of PRC.PC (Config Registers: Offset 224h).

This signal has a weak internal pull-up. Sets bit2 of PRC.PC2 (Config Registers: Offset 224h).

This signal should not be pulled high. ESI compatible mode is for server platforms only.

This signal should not be pulled low for desktop and mobile.

Sampled low: Top-Block Swap mode (inverts A16 for all cycles targeting FWH BIOS space). Note: Software will not be able to clear the Top-Swap bit until the system is rebooted without GNT3# being pulled down.

Controllable via Boot BIOS Destination bit (Config Registers: Offset 3410h:bit 11:10). GNT0# is MSB, 01-SPI, 10-PCI, 11-LPC

Sample low: the Integrated TPM will be disable. Sample high: the MCH TPM enable strap is sampled low and the TPM Disable bit is clear, the Integrated TPM will be enable.

The signal is required to be low for desktop applications and required to be high for mobile applications.

Signal has weak internal pull-up. Sets bit 27 of MPC.LR (Device 28: Function 0:Offset D8).

If sampled high, the system is strapped to the "No Reboot" mode (ICH9 will disable the TCO Timer system reboot feature). The status is readable via the NO REBOOT bit.

This signal should not be pull low unless using XOR Chain testing.

Sampled low: the Flash Descriptor Security will be overridden. If high, the security measures will be in effect. This should only be enabled in manufacturing environments using an external pull-up resister.

ICH9 EDS 642879 Rev.1.5

Comment

B

ICH9 Integrated pull-up and pull-down Resistors

C

Cantiga chipset and ICH9M I/O controller

D

E

Hub strapping configuration

ICH9 EDS 642879 Rev.1.5 Montevina Platform Design guide 22339 Rev.0.5

SIGNAL Resistor Type/Value

CL_CLK[1:0] CL_DATA[1:0] CL_RST0# DPRSLPVR/GPIO16 ENERGY_DETECT HDA_BIT_CLK HDA_DOCK_EN#/GPIO33 HDA_RST# HDA_SDIN[3:0] HDA_SDOUT HDA_SYNC GLAN_DOCK#

GNT[3:0]#/GPIO[55,53,51]

GPIO20 GPIO49 LDA[3:0]#/FHW[3:0]# LAN_RXD[2:0] LDRQ[0] LDRQ[1]/GPIO23 PME# PWRBTN# SATALED#

SPI_CS1#/GPIO58/CLGPIO6

SPI_MOSI SPI_MISO SPKR TACH_[3:0] TP[3] USB[11:0][P,N]

PULL-UP 20K PULL-UP 20K PULL-UP 20K PULL-DOWN 20K PULL-UP 20K PULL-DOWN 20K PULL-UP 20K PULL-DOWN 20K PULL-DOWN 20K PULL-DOWN 20K PULL-DOWN 20K

The pull-up or pull-down active when configured for native GLAN_DOCK# functionality and determined by LAN controller.

PULL-UP 20K PULL-DOWN 20K PULL-UP 20K PULL-UP 20K PULL-UP 20K PULL-UP 20K PULL-UP 20K PULL-UP 20K PULL-UP 20K PULL-UP 15K PULL-UP 20K PULL-DOWN 20K PULL-UP 20K PULL-DOWN 20K PULL-UP 20K PULL-UP 20K PULL-DOWN 15K

Pin Name

CFG[2:0] FSB Frequency Select 000 = FSB1067

CFG[4:3] CFG8 CFG[15:14] CFG[18:17]

CFG5 DMI x2 Select 0 = DMI x2

CFG6 iTPM Host Interface

CFG7 Intel Management

CFG9

CFG10 PCIE Loopback enable 0 = Enable (Note 3)

CFG[13:12] XOR/ALL

CFG16 FSB Dynamic ODT 0 = Dynamic ODT Disabled

CFG19 DMI Lane Reversal

CFG20 Digital Display Port

SDVO _CTRLDATA

L_DDC_DATA Local Flat Panel

NOTE:

1. All strap signals are sampled with respect to the leading edge of the (G)MCH Power OK (PWROK) signal.

2. iTPM can be disabled by a 'Soft-Strap' option in the Flash-decriptor section of the Firmware. This 'Soft-Strap' is activated only after enabling iTPM via CFG6. Only one of the CFG10/CFG12/CFG13 straps can be enabled at any time.

Strap Description Configuration

011 = FSB667 010 = FSB800

Reserved

engine crypto strap

PCIE Graphics Lane 0 = Reserved Lanes, 15->0, 14->1 ect..

(SDVO/DP/iHDMI) Concurrent with PCIe

SDVO Present

(LFP) Present

others = Reserved

1 = DMI x4 (Default)

0 = The iTPM Host Interface is enabled (Note 2)

1 = The iTPM Host Interface is disabled (default)

0 = Transport Layer Security (TLS) cipher

suite with no confidentiality

1 = TLS cipher suite with confidentiality(Default)

1 = Normal operation (Default): Lane Numbered in

Order

1 = Disable (Default)

00 = Reserve 10 = XOR mode Enabled 01 = ALLZ mode Enable (Note 3)

11 = Disabled (Default)

1 = Dynamic ODT Enabled (Default) 0 = Normal operation (Default): Lane Numbered in

Order

1 = Reverse Lanes DMI x4 mode [MCH->ICH]: (3->0, 2->1, 1->2 and 0->3) DMI x2 mode [MCH->ICH]: (3->0, 2->1)

0 = Only Digital Display Port or PCIE is

operational (Default)

1 = Digital display Port and PCIe are operating

simulataneously via the PEG port

0 = No SDVO Card Present (Default)

1 = SDVO Card Present

0 = LFP Disabled (Default)

1 = LFP Card Present; PCIE disabled

USB TablePCIE Routing

0 1 2 3 4 5 6 7 8 9 10 11

USB

USB1 USB2 USB3 RESERVED MINI CARD RESERVED BLUETOOTH NEW CARD RESERVED RESERVED Card Reader CAMERA

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Custom

Date: Sheet

Taipei Hsien 221, Taiwan, R.O.C.

Table of Content

Roberts

358Thursday, October 02, 2008

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A00

Pair Device

LANE2

MiniCard WLAN LANE3 LAN LANE5 New Card

1 1

5

4

3

2

1

SSID = CLOCK

23

VDDPLL3

GND

22

GNDSRC

30

36

3D3V_S0_CK505_IO3D3V_S0_CK505

19

27

33

43

52

VDD96_IO

VDDSRC_IO

VDDPLL3_IO

27MHZ_NONSS/SRCT1/SE1

GND

GNDSRC

GNDCPU

26

49

59

56

61

CPUT0

60

VDDCPU_IO

27MHZ_SS/SRCC1/SE2

GND

65

CPUC0

58

CPUT1_F

57

CPUC1_F

SRCT6 SRCC6

SRCT10 SRCC10

SRCT9 SRCC9

SRCT4 SRCC4

54 53

51 50

48 47

41 42

40 39

37 38

34 35

31 32

28 29

24 25

20 21

CPUT2_ITP/SRCT8

CPUC2_ITP/SRCC8

SRCT7/CR#_F SRCC7/CR#_E

SRCT11/CR#_H

SRCC11/CR#_G

SRCT3/CR#_C

SRCC3/CR#_D

SRCT2/SATAT

SRCC2/SATAC

SRCT0/DOTT_96

SRCC0/DOTC_96

Main source: 71.08513.003 (SLG8SP513VTR) 2nd source: 71.00875.C03 (RTM875N-606-VD-GRT) 3rd source:

Co-layout Ref: 71.09355.B03 (ICS9LPRS355BKLFT)

+3.3V_RUN

R204

D D

C C

B B

1 2

0R0603-PAD

12

C229

SC1U10V3KX-3GP

+3.3V_RUN 3D3V_S0_CK505

R200

1 2

0R0603-PAD

12

C233

SC1U10V3KX-3GP

DY

12

C226

12

C211

12

C210

SCD1U16V2KX-3GP

SC10U6D3V5MX-3GP

12

C218

SCD1U16V2KX-3GP

SC10U6D3V5MX-3GP

C239

SCD1U16V2KX-3GP

C238

SCD1U16V2KX-3GP

CLKSATAREQ#18

CLKREQ#_B9

PCLK_FWH37 PCLK_KBC24

CLK_PCI_ICH16

CLK_14M_ICH18

12

C209

SCD1U16V2KX-3GP

12

C207

SCD1U16V2KX-3GP

3D3V_S0_CK505_IO

12

C215

SCD1U16V2KX-3GP

12

C225

SCD1U16V2KX-3GP

C237

SCD1U16V2KX-3GP

C234

SCD1U16V2KX-3GP

12

C236

DY

C462

SC12P50V2JN-3GP

CLK_48M_CARD21

CLK_48M_ICH18

H_STP_PCI#18 H_STP_CPU#18

ICH_SMBCLK14,15,18

ICH_SMBDATA14,15,18

CK_PWRGD18

A00.08/0922

12

C243

DY

SC4D7P50V2CN-1GP

X3

1 2

X-14D31818M-37GP

12

SC12P50V2JN-3GP

1 2

C245 SC4D7P50V2CN-1GP

R178 475R2F-L1-GPR178 475R2F-L1-GP

1 2

R196 33R2J-2-GP

1 2

R207 33R2J-2-GPR207 33R2J-2-GP

1 2

R212 33R2J-2-GPR212 33R2J-2-GP

1 2

R190 33R2J-2-GPR190 33R2J-2-GP

1 2

C224

SC4D7P50V2CN-1GP

C461

R217 22R2J-2-GPR217 22R2J-2-GP

1 2

DY

CLK_XTAL_IN

CLK_XTAL_OUT

12

R216

1 2

22R2J-2-GP

CLKREQ#_1 PCI2_TME

27_SEL ITP_EN

FSB FSC

FSA

4

46

62

16

VDD48

VDDREF

GNDPCI

GND48

15

18

9

VDDPCI

VDDSRC

GNDREF

1

VDDCPU

U54

3

X1

2

X2

17

USB_48MHZ/FSLA

45

PCI_STOP#

44

CPU_STOP#

ICS9LPRS355BKLFT-GP-U

7

SCLK

6

SDATA

63

CK_PWRGD/PD#

8

PCI0/CR#_A

10

PCI1/CR#_B

11

PCI2/TME

12

PCI3

13

PCI4/27_SELECT

14

PCI_F5/ITP_EN

64

FSLB/TEST_MODE

5

REF0/FSLC/TEST_SEL

55

NC#55

NEWCARD_CLKREQ# MINI1_CLKREQ#

NEWCARD_CLKREQ#

CLK_PCIE_NEW CLK_PCIE_NEW#

R193 10KR2J-3-GPR193 10KR2J-3-GP

1 2

R195 10KR2J-3-GPR195 10KR2J-3-GP

1 2

12

C463

C464

DY

C464

DY

SC4D7P50V2CN-1GP

A00.08/0910

12

EC57

SC22P50V2JN-4GP

NEWCARD_CLKREQ# 41 MINI1_CLKREQ# 37

+3.3V_RUN

CLK_CPU_BCLK 5 CLK_CPU_BCLK# 5

CLK_MCH_BCLK 8 CLK_MCH_BCLK# 8

CLK_CPU_ITP 37 CLK_CPU_ITP# 37

CLK_PCIE_LAN 20 CLK_PCIE_LAN# 20

CLK_PCIE_NEW 41 CLK_PCIE_NEW# 41

CLK_PCIE_MINI1 37 CLK_PCIE_MINI1# 37

CLK_MCH_3GPLL 9 CLK_MCH_3GPLL# 9

CLK_PCIE_ICH 16 CLK_PCIE_ICH# 16

CLK_PCIE_SATA 17 CLK_PCIE_SATA# 17

MCH_SSCDREFCLK 9 MCH_SSCDREFCLK# 9

CLK_MCH_DREFCLK 9 CLK_MCH_DREFCLK# 9

3D3V_S0_CK505

12

R209

R209 10KR2J-3-GP

10KR2J-3-GP

ITP_EN

12

R218

DY

10KR2J-3-GP

A A

ITP_EN Output

0 SRC8 1 CPU_ITP

SEL2 FSC

SEL1 FSB

1 0 01 0 00 0

5

3D3V_S0_CK505

12

R198

R198 10KR2J-3-GP

10KR2J-3-GP

PCI2_TME

12

R202

R202 10KR2J-3-GP

10KR2J-3-GP

DY

SEL0 FSA

01 01

1 01

4

PCI2_TME Output

0

Overclocking of CPU and SRC allowed

1

Overclocking of CPU and SRC not allowed

CPU

100M 133M 166M 200M

FSB

X 533M 667M 800M

1067M266M

12

R206

R206 10KR2J-3-GP

10KR2J-3-GP

27_SEL

CLK_MCH_DREFCLK

12

EC140

DY

SC47P50V2JN-3GP

CLK_MCH_DREFCLK#

12

EC139

DY

SC47P50V2JN-3GP

27_SEL PIN 20 PIN 21

0 DOT96T DOT96C 1 SRCT0 SRCC0

R186 10KR2J-3-GPR186 10KR2J-3-GP

CPU_BSEL26 CPU_BSEL16 CPU_BSEL06

1 2

R412 0R2J-2-GPR412 0R2J-2-GP

1 2

R214 2K2R2J-2-GPR214 2K2R2J-2-GP

1 2

R215 1KR2J-1-GPR215 1KR2J-1-GP

1 2

R411 1KR2J-1-GPR411 1KR2J-1-GP

1 2

R181 1KR2J-1-GPR181 1KR2J-1-GP

1 2

3

FSC FSB FSA

MCH_CLKSEL0 9 MCH_CLKSEL1 9 MCH_CLKSEL2 9

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Clock Generator SLG8SP513VTR

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

Taipei Hsien 221, Taiwan, R.O.C.

Roberts

GM45 PM45

A00

of

458Thursday, October 02, 2008

1

DCCBB

A

SSID = CPU

H_A#[35..3]8

D

5

H_A#[35..3]

4

1 OF 4

U41A

H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15

H_ADSTB#08

H_REQ#[4..0]8

H_ADSTB#18

H_A20M#17

H_FERR#17

H_IGNNE#17

H_STPCLK#17

H_INTR17 H_NMI17 H_SMI#17

TP30TPAD30 TP30TPAD30 TP31TPAD30 TP31TPAD30 TP13TPAD30 TP13TPAD30 TP23TPAD30 TP23TPAD30 TP21TPAD30 TP21TPAD30 TP24TPAD30 TP24TPAD30 TP19TPAD30 TP19TPAD30 TP55TPAD30 TP55TPAD30

TP25TPAD30 TP25TPAD30

TP34TPAD30 TP34TPAD30 TP12TPAD30 TP12TPAD30

H_A#16

H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4

H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35

RSVD_CPU_1 RSVD_CPU_2 RSVD_CPU_3 RSVD_CPU_4 RSVD_CPU_5 RSVD_CPU_6 RSVD_CPU_7 RSVD_CPU_8 RSVD_CPU_9 RSVD_CPU_10

RSVD_CPU_11

U41A

J4

A3#

L5

A4#

L4

A5#

K5

A6#

M3

A7#

N2

A8#

J1

A9#

N3

A10#

P5

A11#

P2

A12#

L2

A13#

P4

A14#

P1

A15#

R1

A16#

M1

ADSTB0#

K3

REQ0#

H2

REQ1#

K2

REQ2#

J3

REQ3#

L1

REQ4#

Y2

A17#

U5

A18#

R3

A19#

W6

A20#

U4

A21#

Y5

A22#

U1

A23#

R4

A24#

T5

A25#

T3

A26#

W2

A27#

W5

A28#

Y4

A29#

U2

A30#

V4

A31#

W3

A32#

AA4

A33#

AB2

A34#

AA3

A35#

V1

ADSTB1#

A6

A20M#

A5

FERR#

C4

IGNNE#

D5

STPCLK#

C6

LINT0

B4

LINT1

A3

SMI#

M4

RSVD#M4

N5

RSVD#N5

T2

RSVD#T2

V3

RSVD#V3

B2

RSVD#B2

C3

RSVD#C3

D2

RSVD#D2

D22

RSVD#D22

D3

RSVD#D3

F6

RSVD#F6

B1

KEY_NC

BGA479-SKT6-GPU7

62.10040.221

ADDR GROUP 0

ADDR GROUP 1

ICH

TEST7

RESERVED

DEFER#

DRDY# DBSY#

LOCK#

RESET#

TRDY#

BPM0# BPM1# BPM2# BPM3# PRDY# PREQ#

TRST#

XDP/ITP SIGNALS CONTROL

XDP/ITP SIGNALS CONTROL THERMAL

THERMAL

PROCHOT#

THRMDA THRMDC

THERMTRIP#

HCLK

BCLK0 BCLK1

ADS# BNR#

BPRI#

BR0#

IERR#

INIT#

RS0# RS1# RS2#

HIT#

HITM#

TCK

TDO TMS

DBR#

H1 E2 G5

H5 F21 E1

F1

CPU_IERR#

D20 B3

H4

H_CPURST#

C1

H_RS#0

F3

H_RS#1

F4

H_RS#2

G3 G2

G6 E4

ITP_BPM#0

AD4

ITP_BPM#1

AD3

ITP_BPM#2

AD1

ITP_BPM#3

AC4

ITP_BPM#4

AC2

ITP_BPM#5

AC1

ITP_TCK

AC5

ITP_TDI

AA6

TDI

ITP_TDO

AB3

ITP_TMS

AB5

ITP_TRST#

AB6

ITP_DBRESET#

C20

R50 0R2J-2-GP

R51 56R2J-4-GPR51 56R2J-4-GP

D21 A24 B25

C7

R76 56R2J-4-GP

A22 A21

R47 56R2J-4-GPR47 56R2J-4-GP

1 2

ITP_BPM#0 37 ITP_BPM#1 37 ITP_BPM#2 37 ITP_BPM#3 37 ITP_BPM#4 37 ITP_BPM#5 37 ITP_TCK 37

ITP_TDO 37 ITP_TMS 37 ITP_TRST# 37

1 2

DY

1 2

DY

ITP_DBRESET# 37

A00.08/0903

H_ADS# 8 H_BNR# 8

H_BPRI# 8

H_DEFER# 8 H_DRDY# 8 H_DBSY# 8

H_BREQ#0 8

H_INIT# 17 H_LOCK# 8

H_CPURST# 8,37

H_RS#[2..0] 8

H_TRDY# 8 H_HIT# 8

H_HITM# 8

ITP_TDI 37

3

+1.05V_VCCP

CPU_PROCHOT# 28

+1.05V_VCCP

H_THERMDA 25 H_THERMDC 25

H_THRMTRIP# 9,17,24,34

+1.05V_VCCP

CLK_CPU_BCLK 4 CLK_CPU_BCLK# 4

2

H_THERMDA, H_THERMDC routing together, Trace width / Spacing = 10 / 10 mil

H_THRMTRIP# should connect to ICH9 and MCH without T-ing.

H_THERMDA

H_THERMDC

12

C49

DY

SC2200P50V2KX-2GP

1

A

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Custom

Date: Sheet

Taipei Hsien 221, Taiwan, R.O.C.

CPU-FSB(1/3)

Roberts

of

558Thursday, October 02, 2008

A00

5

DCCBB

A

SSID = CPU

4

3

2

1

D

Layout notes Z= 55 Ohm 0.5" MAX for CPU_GTLREF0

+1.05V_VCCP

R354

2KR2F-3-GP

H_DINV#[3..0] H_DSTBN#[3..0] H_DSTBP#[3..0] H_D#[63..0]

R357

R357 1KR2F-3-GP

1KR2F-3-GP

1 2 12

DY

CPU_GTLREF0

12

C376

SC1KP50V2KX-1GP

H_DINV#[3..0] 8 H_DSTBN#[3..0] 8 H_DSTBP#[3..0] 8 H_D#[63..0] 8

H_DSTBN#08 H_DSTBP#08 H_DINV#08

H_DSTBN#18 H_DSTBP#18 H_DINV#18

R53 1KR2J-1-GP

1 2

DY

R60 1KR2J-1-GP

1 2

DY

R58 1KR2J-1-GP

1 2

DY

R7 1KR2J-1-GP

1 2

DY

CPU_BSEL04 CPU_BSEL14 CPU_BSEL24

H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15

H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31

TEST1 TEST2 CPU_TEST3

CPU_TEST5

U41B

E22

D0#

F24

D1#

E26

D2#

G22

D3#

F23

D4#

G25

D5#

E25

D6#

E23

D7#

K24

D8#

G24

D9#

J24

D10#

J23

D11#

H22

D12#

F26

D13#

K22

D14#

H23

D15#

J26

DSTBN0#

H26

DSTBP0#

H25

DINV0#

N22

D16#

K25

D17#

P26

D18#

R23

D19#

L23

D20#

M24

D21#

L22

D22#

M23

D23#

P25

D24#

P23

D25#

P22

D26#

T24

D27#

R24

D28#

L25

D29#

T25

D30#

N25

D31#

L26

DSTBN1#

M26

DSTBP1#

N24

DINV1#

AD26

GTLREF

C23

TEST1

D25

TEST2

C24

TEST3

AF26

TEST4

AF1

TEST5

A26

TEST6

B22

BSEL0

B23

BSEL1

C21

BSEL2

BGA479-SKT6-GPU7

62.10040.221

2 OF 4

DATA GRP0 DATA GRP1

DATA GRP2DATA GRP3

DSTBN2# DSTBP2#

DSTBN3# DSTBP3#

MISC

DPRSTP#

PWRGOOD

D32# D33# D34# D35# D36# D37# D38# D39# D40# D41# D42# D43# D44# D45# D46# D47#

DINV2#

D48# D49# D50# D51# D52# D53# D54# D55# D56# D57# D58# D59# D60# D61# D62# D63#

DINV3# COMP0

COMP1 COMP2 COMP3

DPSLP#

DPWR#

SLP#

PSI#

Y22 AB24 V24 V26 V23 T22 U25 U23 Y25 W22 Y23 W24 W25 AA23 AA24 AB25 Y26 AA26 U22

AE24 AD24 AA21 AB22 AB21 AC26 AD20 AE22 AF23 AC25 AE21 AD21 AC22 AD23 AF22 AC23 AE25 AF24 AC20

R26 U26 AA1 Y1

E5 B5 D24 D6 D7 AE6

H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47

H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63

COMP0 COMP1 COMP2 COMP3

H_DSTBN#2 8 H_DSTBP#2 8 H_DINV#2 8

H_DSTBN#3 8 H_DSTBP#3 8 H_DINV#3 8

R350 27D4R2F-L1-GPR350 27D4R2F-L1-GP

1 2

R349 54D9R2F-L1-GPR349 54D9R2F-L1-GP

1 2

R14 27D4R2F-L1-GPR14 27D4R2F-L1-GP

1 2

R13 54D9R2F-L1-GPR13 54D9R2F-L1-GP

1 2

H_DPRSTP# 9,17,28 H_DPSLP# 17 H_DPWR# 8 H_PWRGOOD 17,34 H_CPUSLP# 8

PSI# 28

Layout Note: Comp0, 2 connect with Zo=27.4 ohm, make trace length shorter than 0.5". Comp1, 3 connect with Zo=55 ohm, make trace length shorter than 0.5".

Route the CPU_TEST3 and CPU_TEST5 signals through a ground referenced Zo = 55-ohm trace that ends in a via that is near a GND via and is accessible through an oscilloscope connection.

A

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Custom

Date: Sheet

Taipei Hsien 221, Taiwan, R.O.C.

CPU-FSB(2/3)

Roberts

of

658Thursday, October 02, 2008

A00

5

4

3

2

1

SSID = CPU

D D

+VCC_CORE

3 OF 4

U41C

A7

VCC

A9

VCC

A10

VCC

A12

VCC

A13

VCC

A15

VCC

A17

VCC

A18

VCC

A20

VCC

B7

VCC

B9

VCC

B10

VCC

B12

VCC

B14

VCC

B15

VCC

B17

VCC

B18

VCC

B20

VCC

C9

VCC

C10

VCC

C12

VCC

C13

VCC

C15

VCC

C C

B B

C17

VCC

C18

VCC

D9

VCC

D10

VCC

D12

VCC

D14

VCC

D15

VCC

D17

VCC

D18

VCC

E7

VCC

E9

VCC

E10

VCC

E12

VCC

E13

VCC

E15

VCC

E17

VCC

E18

VCC

E20

VCC

F7

VCC

F9

VCC

F10

VCC

F12

VCC

F14

VCC

F15

VCC

F17

VCC

F18

VCC

F20

VCC

AA7

VCC

AA9

VCC

AA10

VCC

AA12

VCC

AA13

VCC

AA15

VCC

AA17

VCC

AA18

VCC

AA20

VCC

AB9

VCC

AC10

VCC

AB10

VCC

AB12

VCC

AB14

VCC

AB15

VCC

AB17

VCC

AB18

VCC

BGA479-SKT6-GPU7

62.10040.221

VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC

VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP

VCCA VCCA

VID0 VID1 VID2 VID3 VID4 VID5 VID6

VCCSENSE

VSSSENSE

AB20 AB7 AC7 AC9 AC12 AC13 AC15 AC17 AC18 AD7 AD9 AD10 AD12 AD14 AD15 AD17 AD18 AE9 AE10 AE12 AE13 AE15 AE17 AE18 AE20 AF9 AF10 AF12 AF14 AF15 AF17 AF18 AF20

G21 V6 J6 K6 M6 J21 K21 M21 N21 N6 R21 R6 T21 T6 V21 W21

B26 C26

AD6 AF5 AE5 AF4 AE3 AF3 AE2

AF7

AE7

+VCC_CORE

layout note: "+1.5V_VCCA" as short as possible

CPU_VID0 CPU_VID1 CPU_VID2 CPU_VID3 CPU_VID4 CPU_VID5 CPU_VID6

R311 100R2F-L1-GP-UR311 100R2F-L1-GP-U

R302 100R2F-L1-GP-UR302 100R2F-L1-GP-U

CPU_VID[6..0] 28

1 2

+VCC_CORE

12

DY

+VCC_CORE

12

+VCC_CORE

12

+1.05V_VCCP

12

DY

12

C25

C36

DY

SC22U6D3V5MX-2GP

12

C15

C14

DY

SC22U6D3V5MX-2GP

12

C12

C17

SC22U6D3V5MX-2GP

12

C44

TC17

SCD1U10V2KX-4GP

ST220U2D5VBM-LGP

SCD01U16V2KX-3GP

+VCC_CORE

VCC_SENSE 28

VSS_SENSE 28

DY

12

C31

12

C352

12

C32

12

C43

DY

R356

12

C5

12

C338

12

C340

12

C7

12

DY

SC22U6D3V5MX-2GP

12

DY

SC22U6D3V5MX-2GP

12

SC22U6D3V5MX-2GP

12

SCD1U10V2KX-4GP

+1.5V_RUN+1.5V_VCCA

12

C11

C370

DY

SC22U6D3V5MX-2GP

12

DY

SC22U6D3V5MX-2GP

12

SC22U6D3V5MX-2GP

12

SCD1U10V2KX-4GP

C374

C370

DY

SC22U6D3V5MX-2GP

12

C35

C26

DY

SC22U6D3V5MX-2GP

12

C29

C30

SC22U6D3V5MX-2GP

12

C9

C45

SCD1U10V2KX-4GP

1 2

0R0603-PAD

12

C377

C377 SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

VCC_SENSE and VSS_SENSE lines should be of equal length.

12

DY

C365

12

C357

12

C368

12

C366

SC22U6D3V5MX-2GP

12

C363

SC22U6D3V5MX-2GP

12

C336

C336 SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

12

C6

C3

DY

SC22U6D3V5MX-2GP

12

C13

C367

DY

SC22U6D3V5MX-2GP

12

C347

C344

SC22U6D3V5MX-2GP

C8

C8 SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

Layout Note: Place as close as possible to the CPU VCCA pin.

12

C10

C10 SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

12

C24

C24 SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

U41D

A4

VSS

A8

VSS

A11

VSS

A14

VSS

A16

VSS

A19

VSS

A23

VSS

AF2

VSS

B6

VSS

B8

VSS

B11

VSS

B13

VSS

B16

VSS

B19

VSS

B21

VSS

B24

VSS

C5

VSS

C8

VSS

C11

VSS

C14

VSS

C16

VSS

C19

VSS

C2

VSS

C22

VSS

C25

VSS

D1

VSS

D4

VSS

D8

VSS

D11

VSS

D13

VSS

D16

VSS

D19

VSS

D23

VSS

D26

VSS

E3

VSS

E6

VSS

E8

VSS

E11

VSS

E14

VSS

E16

VSS

E19

VSS

E21

VSS

E24

VSS

F5

VSS

F8

VSS

F11

VSS

F13

VSS

F16

VSS

F19

VSS

F2

VSS

F22

VSS

F25

VSS

G4

VSS

G1

VSS

G23

VSS

G26

VSS

H3

VSS

H6

VSS

H21

VSS

H24

VSS

J2

VSS

J5

VSS

J22

VSS

J25

VSS

K1

VSS

K4

VSS

K23

VSS

K26

VSS

L3

VSS

L6

VSS

L21

VSS

L24

VSS

M2

VSS

M5

VSS

M22

VSS

M25

VSS

N1

VSS

N4

VSS

N23

VSS

N26

VSS

P3

VSS

BGA479-SKT6-GPU7

62.10040.221

4 OF 4

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

P6 P21 P24 R2 R5 R22 R25 T1 T4 T23 T26 U3 U6 U21 U24 V2 V5 V22 V25 W1 W4 W23 W26 Y3 Y6 Y21 Y24 AA2 AA5 AA8 AA11 AA14 AA16 AA19 AA22 AA25 AB1 AB4 AB8 AB11 AB13 AB16 AB19 AB23 AB26 AC3 AC6 AC8 AC11 AC14 AC16 AC19 AC21 AC24 AD2 AD5 AD8 AD11 AD13 AD16 AD19 AD22 AD25 AE1 AE4 AE8 AE11 AE14 AE16 AE19 AE23 AE26 A2 AF6 AF8 AF11 AF13 AF16 AF19 AF21 A25 AF25

CPU_GND1

CPU_GND2 CPU_GND3

CPU_GND4

NCTF PIN

TP10TP10

TP224TP224 TP20TP20

TP56TP56

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Custom

Date: Sheet

Taipei Hsien 221, Taiwan, R.O.C.

CPU-Power(3/3)

Roberts

758Thursday, October 02, 2008

1

of

A00

5

DCCBB

A

SSID = MCH

4

3

2

1

1 OF 10

U52A

F2

H_D#_0

G8

H_D#_1

F8

H_D#_2

E6

H_D#_3

G2

H_D#_4

H6

H_D#_5

H2

H_D#_6

F6

H_D#_7

D4

H_D#_8

H3

H_D#_9

M9

H_D#_10

M11

H_D#_11

J1

H_D#_12

J2

H_D#_13

N12

H_D#_14

J6

H_D#_15

P2

H_D#_16

L2

H_D#_17

R2

H_D#_18

N9

H_D#_19

L6

H_D#_20

M5

H_D#_21

J3

H_D#_22

N2

H_D#_23

R1

H_D#_24

N5

H_D#_25

N6

H_D#_26

P13

H_D#_27

N8

H_D#_28

L7

H_D#_29

N10

H_D#_30

M3

H_D#_31

Y3

H_D#_32

AD14

H_D#_33

Y6

H_D#_34

Y10

H_D#_35

Y12

H_D#_36

Y14

H_D#_37

Y7

H_D#_38

W2

H_D#_39

AA8

H_D#_40

Y9

H_D#_41

AA13

H_D#_42

AA9

H_D#_43

AA11

H_D#_44

AD11

H_D#_45

AD10

H_D#_46

AD13

H_D#_47

AE12

H_D#_48

AE9

H_D#_49

AA2

H_D#_50

AD8

H_D#_51

AA3

H_D#_52

AD3

H_D#_53

AD7

H_D#_54

AE14

H_D#_55

AF3

H_D#_56

AC1

H_D#_57

AE3

H_D#_58

AC3

H_D#_59

AE11

H_D#_60

AE8

H_D#_61

AG2

H_D#_62

AD6

H_D#_63

C5

H_SWING

E3

H_RCOMP

C12

H_CPURST#

E11

H_CPUSLP#

A11

H_AVREF

B11

H_DVREF

CANTIGA-GM-GP-U-NF

HOST

H_AVREF

H_D#[63..0]

H_CPURST#5,37 H_CPUSLP#6

12

C403

DY

SCD1U16V2KX-3GP

H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63

H_SWING H_RCOMP

D

H_SWING

H_RCOMP

+1.05V_VCCP

12

R368

R368 221R2F-2-GP

221R2F-2-GP

12

R367

R367 100R2F-L1-GP-U

100R2F-L1-GP-U

H_SWING routing Trace width and Spacing use 10 / 20 mil

H_SWING Resistors and Capacitors close MCH 500 mil ( MAX )

12

C399

C399 SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

H_RCOMP routing Trace width and Spacing use 10 / 20 mil

1 2

24D9R2F-L-GP

R361

H_D#[63..0]6

Place R51 near to the chip ( < 0.5")

+1.05V_VCCP

R369

R369 1KR2F-3-GP

1KR2F-3-GP

1 2

12

R372

R372 2KR2F-3-GP

2KR2F-3-GP

1 OF 10

H_A#_3 H_A#_4 H_A#_5 H_A#_6 H_A#_7 H_A#_8

H_A#_9 H_A#_10 H_A#_11 H_A#_12 H_A#_13 H_A#_14 H_A#_15 H_A#_16 H_A#_17 H_A#_18 H_A#_19 H_A#_20 H_A#_21 H_A#_22 H_A#_23 H_A#_24 H_A#_25 H_A#_26 H_A#_27 H_A#_28 H_A#_29 H_A#_30 H_A#_31 H_A#_32 H_A#_33 H_A#_34 H_A#_35

H_ADS# H_ADSTB#_0 H_ADSTB#_1

H_BNR#

H_BPRI#

H_BREQ#

H_DEFER#

H_DBSY#

HPLL_CLK

HPLL_CLK#

H_DPWR#

H_DRDY#

H_HIT#

H_HITM# H_LOCK# H_TRDY#

H_DINV#_0 H_DINV#_1 H_DINV#_2 H_DINV#_3

H_DSTBN#_0 H_DSTBN#_1 H_DSTBN#_2 H_DSTBN#_3

H_DSTBP#_0 H_DSTBP#_1 H_DSTBP#_2 H_DSTBP#_3

H_REQ#_0 H_REQ#_1 H_REQ#_2 H_REQ#_3 H_REQ#_4

H_RS#_0

H_RS#_1

H_RS#_2

A14 C15 F16 H13 C18 M16 J13 P16 R16 N17 M13 E17 P17 F17 G20 B19 J16 E20 H16 J20 L17 A17 B17 L16 C21 J17 H20 B18 K17 B20 F21 K21 L20

H12 B16 G17 A9 F11 G12 E9 B10 AH7 AH6 J11 F9 H9 E12 H11 C9

J8 L3 Y13 Y1

L10 M7 AA5 AE6

L9 M8 AA6 AE5

B15 K13 F13 B13 B14

B6 F12 C8

H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35

H_DINV#0 H_DINV#1 H_DINV#2 H_DINV#3

H_DSTBN#0 H_DSTBN#1 H_DSTBN#2 H_DSTBN#3

H_DSTBP#0 H_DSTBP#1 H_DSTBP#2 H_DSTBP#3

H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4

H_RS#0 H_RS#1 H_RS#2

H_A#[35..3]

H_ADS# 5 H_ADSTB#0 5 H_ADSTB#1 5 H_BNR# 5

H_BPRI# 5

H_BREQ#0 5

H_DEFER# 5

H_DBSY# 5

CLK_MCH_BCLK 4 CLK_MCH_BCLK# 4

H_DPWR# 6 H_DRDY# 5 H_HIT# 5 H_HITM# 5

H_LOCK# 5

H_TRDY# 5

H_DINV#[3..0]

H_DSTBN#[3..0]

H_DSTBP#[3..0]

H_REQ#[4..0]

H_RS#[2..0]

H_A#[35..3] 5

H_DINV#[3..0] 6

H_DSTBN#[3..0] 6

H_DSTBP#[3..0] 6

H_REQ#[4..0] 5

H_RS#[2..0] 5

A

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Cantiga-HOST(1/6)

Size Document Number Rev

Custom

Date: Sheet

Cantiga-HOST(1/6)

Taipei Hsien 221, Taiwan, R.O.C.

Roberts

858Thursday, October 02, 2008

of

A00

DCCBB

A

SSID = MCH

is current setting

*

CFG Strap HighLow

CFG 5

D

A

CFG 6

CFG 7

CFG 9 PCIE GFX lane reversed

CFG 10 PCIE loopback enable PCIE loopback disable CFG 12 ALLZ mode enable ALLZ mode disable CFG 13 XOR mode enable XOR mode disable

CFG 16

CFG 19 DMI Lane Reserved

CFG 20 SDVO concurrent with PCIE

SDVO_CTRLDATA

L_DDC_DATA LFP disable LFP card present

DDPC_CTRLDATA

+3.3V_RUN

R104 2K21R2F-GP

1 2

DY

R128 2K21R2F-GP

1 2

DY

R117 4K02R2F-GP

1 2

DY

R121 4K02R2F-GP

1 2

DY

RN20

4

SRN10KJ-5-GP

R383 2K21R2F-GP

1 2

DY

R112 2K21R2F-GP

1 2

DY

R111 2K21R2F-GP

1 2

DY

R102 2K21R2F-GP

1 2

DY

R382 4K02R2F-GP

1 2

DY

R375 2K21R2F-GP

1 2

DY

R101 2K21R2F-GP

1 2

DY

R105 2K21R2F-GP

1 2

DY

R103 2K21R2F-GP

1 2

DY

5

DMI X 2

ITPM enable

TLS cipher suite with no confidentiality

FSB dynamic ODT disable

Normal operation Reverse DMI lanes

Only PCIE or SDVO is operational

SDVO interface disable

SDVO/iHDMI/DP interface disabled

CFG11 CFG18 CFG19 CFG20

PM_EXTTS#0

1

PM_EXTTS#1

23

CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG12 CFG13 CFG16

H_THRMTRIP#5,17,24,34

DMI X 4

ITPM disable

TLS cipher suite with confidentiality

PCIE GFX lane numbered in oder

FSB Dynamic ODT enable

*

PCIE and SDVO are operatiing simultaneously

*

via the PEG port

SDVO interface enable

* *

SDVO/iHDMI/DP

*

interface enabled

4

* * *

* *

* * *

M36 N36 R33

AH9 AH10 AH12 AH13

AL34 AK34 AN35

AM35

AY21

BG23

BF23 BH18 BF18

T33

K12

T24 B31

B2

M1

U52B

RESERVED#M36 RESERVED#N36 RESERVED#R33 RESERVED#T33 RESERVED#AH9 RESERVED#AH10 RESERVED#AH12 RESERVED#AH13 RESERVED#K12 RESERVED#AL34 RESERVED#AK34 RESERVED#AN35 RESERVED#AM35 RESERVED#T24

RESERVED#B31 RESERVED#B2 RESERVED#M1

RESERVED#AY21

RESERVED#BG23 RESERVED#BF23 RESERVED#BH18 RESERVED#BF18

RSVD

DDR CLK/ CONTROL/COMPENSATION

DPLL_REF_SSCLK

DPLL_REF_SSCLK#

CLK

FSB setting

MCH_CLKSEL04 MCH_CLKSEL14 MCH_CLKSEL24

TP86TP86 TP88TP88

TP84TP84 TP85TP85

TP87TP87

PM_SYNC#18

H_DPRSTP#6,17,28 PM_EXTTS#014 PM_EXTTS#115

PM_PWROK18,24,25

R94

PLT_RST#16,20,21,24,37,41

DPRSLPVR18,28

1 2

100R2F-L1-GP-U

SC100P50V2JN-3GP

C94

DY

CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15 CFG16 CFG17 CFG18 CFG19 CFG20

RSTIN#

12

T25

CFG_0

R25

CFG_1

P25

CFG_2

P20

CFG_3

P24

CFG_4

C25

CFG_5

N24

CFG_6

M24

CFG_7

E21

CFG_8

C23

CFG_9

C24

CFG_10

N21

CFG_11

P21

CFG_12

T21

CFG_13

R20

CFG_14

M20

CFG_15

L21

CFG_16

H21

CFG_17

P29

CFG_18

R28

CFG_19

T28

CFG_20

R29

PM_SYNC#

B7

PM_DPRSTP#

N33

PM_EXT_TS#_0

P32

PM_EXT_TS#_1

AT40

PWROK

AT11

RSTIN#

T20

THERMTRIP#

R32

DPRSLPVR

BG48

NC#BG48

BF48

NC#BF48

BD48

NC#BD48

BC48

NC#BC48

BH47

NC#BH47

BG47

NC#BG47

BE47

NC#BE47

BH46

NC#BH46

BF46

NC#BF46

BG45

NC#BG45

BH44

NC#BH44

BH43

NC#BH43

BH6

NC#BH6

BH5

NC#BH5

BG4

NC#BG4

BH3

NC#BH3

BF3

NC#BF3

BH2

NC#BH2

BG2

NC#BG2

BE2

NC#BE2

BG1

NC#BG1

BF1

NC#BF1

BD1

NC#BD1

BC1

NC#BC1

F1

NC#F1

A47

NC#A47

CANTIGA-GM-GP-U-NF

DMI

CFG

PM

GRAPHICS VID

MEHDA

NC

MISC

3

2 OF 10

SA_CK_0 SA_CK_1 SB_CK_0 SB_CK_1

SA_CK#_0 SA_CK#_1 SB_CK#_0 SB_CK#_1

SA_CKE_0 SA_CKE_1 SB_CKE_0 SB_CKE_1

SA_CS#_0 SA_CS#_1 SB_CS#_0 SB_CS#_1

SA_ODT_0 SA_ODT_1 SB_ODT_0 SB_ODT_1

SM_RCOMP

SM_RCOMP#

SM_RCOMP_VOH

SM_RCOMP_VOL

SM_VREF

SM_PWROK

SM_REXT

SM_DRAMRST# DPLL_REF_CLK

DPLL_REF_CLK#

PEG_CLK

PEG_CLK#

DMI_RXN_0 DMI_RXN_1 DMI_RXN_2 DMI_RXN_3

DMI_RXP_0 DMI_RXP_1 DMI_RXP_2 DMI_RXP_3

DMI_TXN_0 DMI_TXN_1 DMI_TXN_2 DMI_TXN_3

DMI_TXP_0 DMI_TXP_1 DMI_TXP_2 DMI_TXP_3

GFX_VID_0 GFX_VID_1 GFX_VID_2 GFX_VID_3 GFX_VID_4

GFX_VR_EN

CL_CLK

CL_DATA

CL_PWROK

CL_RST# CL_VREF

DDPC_CTRLCLK

DDPC_CTRLDATA

SDVO_CTRLCLK

SDVO_CTRLDATA

CLKREQ#

ICH_SYNC#

TSATN#

HDA_BCLK HDA_RST#

HDA_SDI

HDA_SDO

HDA_SYNC

AP24 AT21 AV24 AU20

AR24 AR21 AU24 AV20

BC28 AY28 AY36 BB36

BA17 AY16 AV16 AR13

BD17 AY17 BF15 AY13

M_RCOMPP

BG22

M_RCOMPN

BH21

SM_RCOMP_VOH

BF28

SM_RCOMP_VOL

BH28 AV42

AR36

SM_REXT

BF17 BC36

CLK_MCH_DREFCLK

B38

CLK_MCH_DREFCLK#

A38

MCH_SSCDREFCLK

E41

MCH_SSCDREFCLK#

F41

CLK_MCH_3GPLL

F43

CLK_MCH_3GPLL#

E43

DMI_TXN0

AE41

DMI_TXN1

AE37

DMI_TXN2

AE47

DMI_TXN3

AH39

DMI_TXP0

AE40

DMI_TXP1

AE38

DMI_TXP2

AE48

DMI_TXP3

AH40

DMI_RXN0

AE35

DMI_RXN1

AE43

DMI_RXN2

AE46

DMI_RXN3

AH42

DMI_RXP0

AD35

DMI_RXP1

AE44

DMI_RXP2

AF46

DMI_RXP3

AH43

B33 B32 G33 F33 E33

C34

AH37 AH36 AN36 AJ35

MCH_CLVREF

AH34

N28 M28 G36 E36 K36 H36

TSATN#

B12

B28 B30 B29 C29 A28

R374 499R2F-2-GPR374 499R2F-2-GP

1 2

CL_CLK0 18 CL_DATA0 18

M_PWROK 18

CL_RST#0 18

MCH_CLVREF ~= 0.35V

1

TP271TP271

CLKREQ#_B 4 MCH_ICH_SYNC# 18

M_CLK_DDR0 14 M_CLK_DDR1 14 M_CLK_DDR2 15 M_CLK_DDR3 15

M_CLK_DDR#0 14 M_CLK_DDR#1 14 M_CLK_DDR#2 15 M_CLK_DDR#3 15

M_CKE0 14 M_CKE1 14 M_CKE2 15 M_CKE3 15

M_CS0# 14 M_CS1# 14 M_CS2# 15 M_CS3# 15

M_ODT0 14 M_ODT1 14 M_ODT2 15 M_ODT3 15

CLK_MCH_DREFCLK 4 CLK_MCH_DREFCLK# 4 MCH_SSCDREFCLK 4 MCH_SSCDREFCLK# 4

CLK_MCH_3GPLL 4 CLK_MCH_3GPLL# 4

DMI_TXN0 16 DMI_TXN1 16 DMI_TXN2 16 DMI_TXN3 16

DMI_TXP0 16 DMI_TXP1 16 DMI_TXP2 16 DMI_TXP3 16

DMI_RXN0 16 DMI_RXN1 16 DMI_RXN2 16 DMI_RXN3 16

DMI_RXP0 16 DMI_RXP1 16 DMI_RXP2 16 DMI_RXP3 16

2

80D6R2F-L-GP

+V_DDR_MCH_REF

1 2

12

R145

DY

10KR2J-3-GP

+1.05V_VCCP

1 2

12

C175

SCD1U10V2KX-4GP

+1.8V_SUS

R380

R377

+1.8V_SUS

DY

R142

R142 10KR2J-3-GP

10KR2J-3-GP

TSATN#

R126

R126 1KR2F-3-GP

1KR2F-3-GP

R130

R130 499R2F-2-GP

499R2F-2-GP

1

12

SM_RCOMP_VOH

SC2D2U10V3KX-1GP

SM_RCOMP_VOL

SC2D2U10V3KX-1GP

12

R370

R370 56R2J-4-GP

56R2J-4-GP

Title

Size Document Number Rev

Custom

Date: Sheet

12

C159

SCD01U16V2KX-3GP

12

C145

SCD01U16V2KX-3GP

+3.3V_RUN+1.05V_VCCP

12

R371

DY

10KR2J-3-GP

TSATN#_KBC

C

Q19

B

DY

MMBT3904WT1G-GP

E

R131

CLKREQ#_B

R131

1 2

10KR2J-3-GP

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Cantiga-DMI/CFG(2/6)

Roberts

C162

C151

+3.3V_RUN

12

958Thursday, October 02, 2008

+1.8V_SUS

R122

R122 1KR2F-3-GP

1KR2F-3-GP

1 2

12

R116

R116 3K01R2F-3-GP

3K01R2F-3-GP

R119

R119 1KR2F-3-GP

1KR2F-3-GP

1 2

TSATN#_KBC 24

of

A00

5

DCCBB

A

SSID = MCH

4

3

2

1

M_A_DQ[63..0]14

D

M_A_DQ[63..0]

M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63

U52D

AJ38

SA_DQ_0

AJ41

SA_DQ_1

AN38

SA_DQ_2

AM38

SA_DQ_3

AJ36

SA_DQ_4

AJ40

SA_DQ_5

AM44

SA_DQ_6

AM42

SA_DQ_7

AN43

SA_DQ_8

AN44

SA_DQ_9

AU40

SA_DQ_10

AT38

SA_DQ_11

AN41

SA_DQ_12

AN39

SA_DQ_13

AU44

SA_DQ_14

AU42

SA_DQ_15

AV39

SA_DQ_16

AY44

SA_DQ_17

BA40

SA_DQ_18

BD43

SA_DQ_19

AV41

SA_DQ_20

AY43

SA_DQ_21

BB41

SA_DQ_22

BC40

SA_DQ_23

AY37

SA_DQ_24

BD38

SA_DQ_25

AV37

SA_DQ_26

AT36

SA_DQ_27

AY38

SA_DQ_28

BB38

SA_DQ_29

AV36

SA_DQ_30

AW36

SA_DQ_31

BD13

SA_DQ_32

AU11

SA_DQ_33

BC11

SA_DQ_34

BA12

SA_DQ_35

AU13

SA_DQ_36

AV13

SA_DQ_37

BD12

SA_DQ_38

BC12

SA_DQ_39

BB9

SA_DQ_40

BA9

SA_DQ_41

AU10

SA_DQ_42

AV9

SA_DQ_43

BA11

SA_DQ_44

BD9

SA_DQ_45

AY8

SA_DQ_46

BA6

SA_DQ_47

AV5

SA_DQ_48

AV7

SA_DQ_49

AT9

SA_DQ_50

AN8

SA_DQ_51

AU5

SA_DQ_52

AU6

SA_DQ_53

AT5

SA_DQ_54

AN10

SA_DQ_55

AM11

SA_DQ_56

AM5

SA_DQ_57

AJ9

SA_DQ_58

AJ8

SA_DQ_59

AN12

SA_DQ_60

AM13

SA_DQ_61

AJ11

SA_DQ_62

AJ12

SA_DQ_63

CANTIGA-GM-GP-U-NF

4 OF 10

BD21

SA_BS_0

BG18

SA_BS_1

AT25

SA_BS_2

BB20

SA_RAS#

BD20

SA_CAS#

AY20

SA_WE#

M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14

M_A_DM[7..0]

M_A_DQS[7..0]

M_A_DQS#[7..0]

M_A_A[14..0]

SA_DM_0 SA_DM_1 SA_DM_2 SA_DM_3 SA_DM_4 SA_DM_5 SA_DM_6 SA_DM_7

SA_DQS_0 SA_DQS_1 SA_DQS_2 SA_DQS_3 SA_DQS_4 SA_DQS_5 SA_DQS_6

SA_DQS_7 SA_DQS#_0 SA_DQS#_1 SA_DQS#_2 SA_DQS#_3 SA_DQS#_4 SA_DQS#_5 SA_DQS#_6 SA_DQS#_7

SA_MA_0 SA_MA_1 SA_MA_2 SA_MA_3 SA_MA_4 SA_MA_5 SA_MA_6 SA_MA_7 SA_MA_8

SA_MA_9 SA_MA_10 SA_MA_11 SA_MA_12 SA_MA_13 SA_MA_14

DDR SYSTEM MEMORY A

AT41 AY41 AU39 BB12 AY6 AT7 AJ5

AJ44 AT44 BA43 BC37 AW12 BC8 AU8 AM7 AJ43 AT43 BA44 BD37 AY12 BD8 AU9 AM8

BA21 BC24 BG24 BH24 BG25 BA24 BD24 BG27 BF25 AW24 BC21 BG26 BH26 BH17 AY25

M_A_DM1 M_A_DM2 M_A_DM3 M_A_DM4 M_A_DM5 M_A_DM6 M_A_DM7

M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6 M_A_DQS7

M_A_DQS#0

M_A_DQS#1 M_A_DQS#2 M_A_DQS#3 M_A_DQS#4 M_A_DQS#5 M_A_DQS#6 M_A_DQS#7

M_A_DM0

AM37

M_A_BS#0 14 M_A_BS#1 14 M_A_BS#2 14

M_A_RAS# 14 M_A_CAS# 14 M_A_WE# 14

M_A_DM[7..0] 14

M_A_DQS[7..0] 14

M_A_DQS#[7..0] 14

M_A_A[14..0] 14

M_B_DQ[63..0]15

M_B_DQ[63..0]

M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63

U52E

AK47

SB_DQ_0

AH46

SB_DQ_1

AP47

SB_DQ_2

AP46

SB_DQ_3

AJ46

SB_DQ_4

AJ48

SB_DQ_5

AM48

SB_DQ_6

AP48

SB_DQ_7

AU47

SB_DQ_8

AU46

SB_DQ_9

BA48

SB_DQ_10

AY48

SB_DQ_11

AT47

SB_DQ_12

AR47

SB_DQ_13

BA47

SB_DQ_14

BC47

SB_DQ_15

BC46

SB_DQ_16

BC44

SB_DQ_17

BG43

SB_DQ_18

BF43

SB_DQ_19

BE45

SB_DQ_20

BC41

SB_DQ_21

BF40

SB_DQ_22

BF41

SB_DQ_23

BG38

SB_DQ_24

BF38

SB_DQ_25

BH35

SB_DQ_26

BG35

SB_DQ_27

BH40

SB_DQ_28

BG39

SB_DQ_29

BG34

SB_DQ_30

BH34

SB_DQ_31

BH14

SB_DQ_32

BG12

SB_DQ_33

BH11

SB_DQ_34

BG8

SB_DQ_35

BH12

SB_DQ_36

BF11

SB_DQ_37

BF8

SB_DQ_38

BG7

SB_DQ_39

BC5

SB_DQ_40

BC6

SB_DQ_41

AY3

SB_DQ_42

AY1

SB_DQ_43

BF6

SB_DQ_44

BF5

SB_DQ_45

BA1

SB_DQ_46

BD3

SB_DQ_47

AV2

SB_DQ_48

AU3

SB_DQ_49

AR3

SB_DQ_50

AN2

SB_DQ_51

AY2

SB_DQ_52

AV1

SB_DQ_53

AP3

SB_DQ_54

AR1

SB_DQ_55

AL1

SB_DQ_56

AL2

SB_DQ_57

AJ1

SB_DQ_58

AH1

SB_DQ_59

AM2

SB_DQ_60

AM3

SB_DQ_61

AH3

SB_DQ_62

AJ3

SB_DQ_63

CANTIGA-GM-GP-U-NF

5 OF 10

BC16

SB_BS_0

BB17

SB_BS_1

BB33

SB_BS_2

AU17

SB_RAS#

BG16

SB_CAS#

BF14

SB_WE#

SB_DM_0 SB_DM_1 SB_DM_2 SB_DM_3 SB_DM_4 SB_DM_5 SB_DM_6 SB_DM_7

SB_DQS_0 SB_DQS_1 SB_DQS_2 SB_DQS_3 SB_DQS_4 SB_DQS_5 SB_DQS_6

SB_DQS_7 SB_DQS#_0 SB_DQS#_1 SB_DQS#_2 SB_DQS#_3 SB_DQS#_4 SB_DQS#_5 SB_DQS#_6 SB_DQS#_7

SB_MA_0 SB_MA_1 SB_MA_2 SB_MA_3 SB_MA_4 SB_MA_5 SB_MA_6 SB_MA_7 SB_MA_8

SB_MA_9 SB_MA_10 SB_MA_11 SB_MA_12 SB_MA_13 SB_MA_14

DDR SYSTEM MEMORY B

AY47 BD40 BF35 BG11 BA3 AP1 AK2

AL47 AV48 BG41 BG37 BH9 BB2 AU1 AN6 AL46 AV47 BH41 BH37 BG9 BC2 AT2 AN5

AV17 BA25 BC25 AU25 AW25 BB28 AU28 AW28 AT33 BD33 BB16 AW33 AY33 BH15 AU33

M_B_DM1 M_B_DM2 M_B_DM3 M_B_DM4 M_B_DM5 M_B_DM6 M_B_DM7

M_B_DQS0 M_B_DQS1 M_B_DQS2 M_B_DQS3 M_B_DQS4 M_B_DQS5 M_B_DQS6 M_B_DQS7 M_B_DQS#0 M_B_DQS#1 M_B_DQS#2 M_B_DQS#3 M_B_DQS#4 M_B_DQS#5 M_B_DQS#6 M_B_DQS#7

M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14

M_B_DM0

AM47

M_B_DM[7..0]

M_B_DQS[7..0]

M_B_DQS#[7..0]

M_B_A[14..0]

M_B_BS#0 15 M_B_BS#1 15 M_B_BS#2 15

M_B_RAS# 15 M_B_CAS# 15 M_B_WE# 15

M_B_DM[7..0] 15

M_B_DQS[7..0] 15

M_B_DQS#[7..0] 15

M_B_A[14..0] 15

A

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Cantiga-DDR(3/6)

Size Document Number Rev

Custom

Date: Sheet

Cantiga-DDR(3/6)

Taipei Hsien 221, Taiwan, R.O.C.

Roberts

10 58Thursday, October 02, 2008

of

A00

DCCBB

A

SSID = MCH

+1.8V_SUS

D

+1.05V_VCCP

VCC_AXG_SENSE

TP83TP83

A

TP82TP82

VSS_AXG_SENSE

5

U52G

AP33

VCC_SM

AN33

VCC_SM

BH32

VCC_SM

BG32

VCC_SM

BF32

VCC_SM

BD32

VCC_SM

BC32

VCC_SM

BB32

VCC_SM

BA32

VCC_SM

AY32

VCC_SM

AW32

VCC_SM

AV32

VCC_SM

AU32

VCC_SM

AT32

VCC_SM

AR32

VCC_SM

AP32

VCC_SM

AN32

VCC_SM

BH31

VCC_SM

BG31

VCC_SM

BF31

VCC_SM

BG30

VCC_SM

BH29

VCC_SM

BG29

VCC_SM

BF29

VCC_SM

BD29

VCC_SM

BC29

VCC_SM

BB29

VCC_SM

BA29

VCC_SM

AY29

VCC_SM

AW29

VCC_SM

AV29

VCC_SM

AU29

VCC_SM

AT29

VCC_SM

AR29

VCC_SM

AP29

VCC_SM

BA36

VCC_SM/NC

BB24

VCC_SM/NC

BD16

VCC_SM/NC

BB21

VCC_SM/NC

AW16

VCC_SM/NC

AW13

VCC_SM/NC

AT13

VCC_SM/NC

Y26

VCC_AXG

AE25

VCC_AXG

AB25

VCC_AXG

AA25

VCC_AXG

AE24

VCC_AXG

AC24

VCC_AXG

AA24

VCC_AXG

Y24

VCC_AXG

AE23

VCC_AXG

AC23

VCC_AXG

AB23

VCC_AXG

AA23

VCC_AXG

AJ21

VCC_AXG

AG21

VCC_AXG

AE21

VCC_AXG

AC21

VCC_AXG

AA21

VCC_AXG

Y21

VCC_AXG

AH20

VCC_AXG

AF20

VCC_AXG

AE20

VCC_AXG

AC20

VCC_AXG

AB20

VCC_AXG

AA20

VCC_AXG

T17

VCC_AXG

T16

VCC_AXG

AM15

VCC_AXG

AL15

VCC_AXG

AE15

VCC_AXG

AJ15

VCC_AXG

AH15

VCC_AXG

AG15

VCC_AXG

AF15

VCC_AXG

AB15

VCC_AXG

AA15

VCC_AXG

Y15

VCC_AXG

V15

VCC_AXG

U15

VCC_AXG

AN14

VCC_AXG

AM14

VCC_AXG

U14

VCC_AXG

T14

VCC_AXG

AJ14

VCC_AXG_SENSE

AH14

VSS_AXG_SENSE

CANTIGA-GM-GP-U-NF

3000mA

8700mA

POWER

VCC SMVCC GFX

VCC GFX NCTF

7 OF 10

VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF

VCC_SM_LF VCC_SM_LF VCC_SM_LF VCC_SM_LF VCC_SM_LF VCC_SM_LF VCC_SM_LF

VCC SM LF

+1.05V_VCCP

W28 V28 W26 V26 W25 V25 W24 V24 W23 V23 AM21 AL21 AK21 W21 V21 U21 AM20 AK20 W20 U20 AM19 AL19 AK19 AJ19 AH19 AG19 AF19 AE19 AB19 AA19 Y19 W19 V19 U19 AM17 AK17 AH17 AG17 AF17 AE17 AC17 AB17 Y17 W17 V17 AM16 AL16 AK16 AJ16 AH16 AG16 AF16 AE16 AC16 AB16 AA16 Y16 W16 V16 U16

SM_LF1_GMCH

AV44

SM_LF2_GMCH

BA37

SM_LF3_GMCH

AM40

SM_LF4_GMCH

AV21

SM_LF5_GMCH

AY5

SM_LF6_GMCH

AM10

SM_LF7_GMCH

BB13

4

Place on the Edge

12

C108

SCD1U16V2KX-3GP

12

1

TC19

2

ST220U2D5VBM-2GP

Place CAP where LVDS and DDR2 taps

12

C99

SCD1U10V2KX-4GP

12

C110

C173

SCD1U16V2KX-3GP

Coupling CAP

12

C170

C161

SC22U6D3V5MX-2GP

SCD47U6D3V2KX-GP

12

C92

SCD1U10V2KX-4GP

12

C383

SC10U6D3V5MX-3GP

12

C142

SC1U10V3KX-3GP

FOR VCC SM

12

C431

SCD1U10V2KX-4GP

12

C81

C134

SCD22U10V2KX-1GP

12

C164

SCD1U10V2KX-4GP

12

TC21

C426

DY

ST220U2D5VBM-2GP

Place on the Edge

1

C182

2

SCD47U6D3V2KX-GP

3

+1.8V_SUS

12

C435

SC22U6D3V5MX-2GP

12

C178

C186

SC1U10V3KX-3GP

DY

12

C390

SC22U6D3V5MX-2GP

FOR VCC CORE

12

C84

C91

SCD1U16V2KX-3GP

SCD22U10V2KX-1GP

+1.05V_VCCP

Coupling CAP 370 mils from the Edge

12

C111

SC10U6D3V5MX-3GP

12

C113

SCD22U10V2KX-1GP

12

C166

SCD1U10V2KX-4GP

Coupling CAP

R125

1 2

0R2J-2-GP

Supply Signal Group

+1.05V_VCCP

VCC_AXG +1.05V_VCCP +1.05V_VCCP +1.05V_VCCP

VCCA_SM +1.05V_VCCP +1.05V_VCCP

VCCA_SM_CK 26mA

VCCA_HPLL 24mA +1.05V_VCCP +1.05V_VCCP +1.05V_VCCP +1.05V_VCCP 50mA +1.05V_VCCP

VCCD_PEG_PLL

VCC_AXF

VCC_HDA+1.5V_RUN +1.5V_RUN VCCD_TVDAC 35mA +1.8V_SUS 60.31mA

VCCD_LVDS +1.8V_SUS +1.8V_SUS

VCC_SM_CK +3.3V_RUN VCCA_PEG_BG 414uA +3.3V_RUN VCC_HV 105.3mA

2

12

C98

SCD1U10V2KX-4GP

12

C156

SCD1U10V2KX-4GP

Imax

2898.52mAVCC+1.05V_VCCP 8700mA 852mAVTT 1782mAVCC_PEG 456mAVCC_DMI 720mA+1.05V_VCCP

139.2mAVCCA_MPLL

157.2mAVCCD_HPLL 50mAVCCA_PEG_PLL

321.35mA 50mA

3000mAVCC_SM 124mA

12

C80

SCD1U10V2KX-4GP

VCC_GMCH_35

1

6 OF 10

U52F

AG34

VCC

AC34

VCC

AB34

VCC

AA34

VCC

Y34

VCC

V34

VCC

U34

VCC

AM33

VCC

AK33

VCC

AJ33

VCC

AG33

VCC

AF33

VCC

AE33 AC33 AA33

AH28 AF28 AC28 AA28

AJ26 AG26 AE26 AC26 AH25 AG25 AF25 AG24

AJ23 AH23 AF23

2898.52mA

VCC VCC VCC

Y33

VCC

W33

VCC

V33

VCC

U33

VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC

T32

VCC

CANTIGA-GM-GP-U-NF

Title

Size Document Number Rev

Custom

Date: Sheet

VCC CORE

POWER

Cantiga-Power(4/6)

6 OF 10

+1.05V_VCCP

VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF

VCC NCTF

VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Roberts

AM32 AL32 AK32 AJ32 AH32 AG32 AE32 AC32 AA32 Y32 W32 U32 AM30 AL30 AK30 AH30 AG30 AF30 AE30 AC30 AB30 AA30 Y30 W30 V30 U30 AL29 AK29 AJ29 AH29 AG29 AE29 AC29 AA29 Y29 W29 V29 AL28 AK28 AL26 AK26 AK25 AK24 AK23

11 58Thursday, September 11, 2008

A00

of

DCCBB

A

+1.05V_VCCP

R152

1 2

0R0603-PAD

D

+1.05V_VCCP

R351

R351 0R3-0-U-GP

0R3-0-U-GP

1 2

120ohm 100MHz

+1.05V_VCCP

220ohm 100MHz

+1.5V_RUN

R408

1 2

0R0603-PAD

L12

1 2

FCM1608KF-1-GP

L11

1 2

FCM1608KF-1-GP

L16

1 2

BLM18BB221SN1D-GP

R115

1 2

0R0603-PAD

A00.08/0903

L3

1 2

HCB1608K-181T20GP

180ohm 100MHz

C436

SC1U10V3KX-3GP

A

+3.3V_CRT_LDO

C419

SC10U6D3V5MX-3GP

C419

Reserved for TV ripple

12

C189

SCD1U16V2KX-3GP

12

C448

SCD1U16V2KX-3GP

12

5

M_VCCA_DPLLA

12

C188

DY

SCD1U16V2KX-3GP

M_VCCA_DPLLB

12

C444

DY

SCD1U16V2KX-3GP

M_VCCA_HPLL

12

C393

SC4D7U6D3V3KX-GP

M_VCCA_MPLL

12

C391

DY

SC10U6D3V5MX-3GP

1D05V_RUN_PEGPLL

12

C450

SC10U6D3V5MX-3GP

1D5VRUN_TVDAC

12

C153

SCD01U16V2KX-3GP

1D5VRUN_QDAC

12

C154

SCD01U16V2KX-3GP

1 2 3 4 5

C187

SCD1U10V2KX-4GP

C439

SCD1U10V2KX-4GP

C387

SCD1U10V2KX-4GP

C384

SCD1U10V2KX-4GP

C443

SCD1U10V2KX-4GP

C152

SCD1U10V2KX-4GP

C158

SCD1U10V2KX-4GP

U53

EN GND VIN VOUT NC#5

G9091-330T12U-GP

Main source:

74.09091.H3F 2nd source:

74.09198.07F

+3.3V_CRT_LDO

+1.8V_SUS

+1.5V_RUN

+1.05V_VCCP

+1.8V_SUS

R394

1 2

0R0603-PAD

R390

1 2

0R0603-PAD

R403

1 2

0R0402-PAD

R402

1 2

0R0402-PAD

R120

1 2

0R0603-PAD

R378

1 2

0R0402-PAD

R360

1 2

0R0603-PAD

R140

1 2

0R0603-PAD

4

12

C434

12

C427

12

C441

C441 SC1KP50V2KX-1GP

SC1KP50V2KX-1GP

12

C442

C442 SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

12

C127

DY

12

C140

+3.3V_TV_DAC+3.3V_CRT_LDO

12

C385

12

C181

C181 SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

3D3V_CRTDAC_S0

12

C433

SCD1U10V2KX-4GP

SCD01U16V2KX-3GP

M_VCCA_DAC_BG

12

C423

M_VCCA_DPLLA

SCD1U10V2KX-4GP

SCD01U16V2KX-3GP

SC22U6D3V5MX-2GP

DY

SC22U6D3V5MX-2GP

DY

R395

1 2

0R0402-PAD

SCD1U10V2KX-4GP

M_VCCA_DPLLB M_VCCA_HPLL M_VCCA_MPLL

VCCA_PEG_BG

1D05V_RUN_PEGPLL

12

C126

SC22U6D3V5MX-2GP

1D05V_SM_CK

12

C144

SC2D2U10V3KX-1GP

12

C417

DY

SCD1U10V2KX-4GP

VCC_HDA

1D5VRUN_TVDAC 1D5VRUN_QDAC 1D05V_RUN_HPLL 1D05V_RUN_PEGPLL

SCD1U10V2KX-4GP

1D8V_SUS_DLVDS

1D8V_TXLVDS

12

C130

SC4D7U6D3V3KX-GP

C157

SCD1U10V2KX-4GP

C416

SCD01U16V2KX-3GP

12

C438

B27 A26

A25 B25

F47

L48 AD1 AE1

J48

J47

AD48

AA48

AR20 AP20 AN20 AR17 AP17

C129

AN17 AT16 AR16

SC1U10V3KX-3GP

AP16

AP28 AN28 AP25 AN25

AN24 AM28 AM26 AM25

AL25

AM24

AL24

AM23

AL23

B24 A24

A32

M25

L28

AF1

AA47

M38

L37

U52H

VCCA_CRT_DAC VCCA_CRT_DAC

VCCA_DAC_BG VSSA_DAC_BG

VCCA_DPLLA VCCA_DPLLB VCCA_HPLL VCCA_MPLL

VCCA_LVDS VSSA_LVDS

VCCA_PEG_BG

VCCA_PEG_PLL

VCCA_SM VCCA_SM VCCA_SM VCCA_SM VCCA_SM VCCA_SM VCCA_SM VCCA_SM VCCA_SM

VCCA_SM_CK VCCA_SM_CK VCCA_SM_CK VCCA_SM_CK VCCA_SM_CK VCCA_SM_CK_NCTF VCCA_SM_CK_NCTF VCCA_SM_CK_NCTF VCCA_SM_CK_NCTF VCCA_SM_CK_NCTF VCCA_SM_CK_NCTF VCCA_SM_CK_NCTF VCCA_SM_CK_NCTF

VCCA_TV_DAC VCCA_TV_DAC

VCC_HDA

VCCD_TVDAC VCCD_QDAC VCCD_HPLL VCCD_PEG_PLL

VCCD_LVDS VCCD_LVDS

CANTIGA-GM-GP-U-NF

5mA

64.8mA

24mA

139.2mA

13.2mA

414uA

50mA

720mA

26mA

79mA

50mA

35mA

2mA

157.2mA 50mA

60.31mA

73mA

3

TV

HDA

LVDS

CRTPLLA PEGA SM

A LVDS

POWER

A CK

118.8mA

D TV/CRT

AXF

VCC_SM_CK VCC_SM_CK VCC_SM_CK VCC_SM_CK

124mA

SM CK

VCC_TX_LVDS

HV

PEG

DMI

VTTLF

8 OF 10

VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT

852mA

VTT VTT VTT

VTT

VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT

VCC_AXF VCC_AXF VCC_AXF

321.35mA

VCC_HV VCC_HV VCC_HV

105.3mA

VCC_PEG VCC_PEG VCC_PEG VCC_PEG VCC_PEG

1782mA

VCC_DMI

VCC_DMI VCC_DMI VCC_DMI

456mA

VTTLF VTTLF VTTLF

U13 T13 U12 T12 U11 T11 U10 T10 U9 T9 U8 T8 U7 T7 U6 T6 U5 T5 V3 U3 V2 U2 T2 V1 U1

B22 B21 A21

BF21 BH20 BG20 BF20

K47 C35

B35 A35

V48 U48 V47 U47 U46

AH48 AF48 AH47 AG47

A8 L1 AB2

1

C143

2

SCD47U6D3V2KX-GP

1D05V_VCC_AXF

1D8V_TXLVDS_S3

+3.3V_VCC_HV

VTTLF1 VTTLF2 VTTLF3

2

12

C135

SC2D2U10V3KX-1GP

12

C447

SC4D7U6D3V3KX-GP

1

C395

2

SCD47U6D3V2KX-GP

12

C123

SC4D7U6D3V3KX-GP

+1.05V_VCCP

12

C191

SC10U6D3V5MX-3GP

1

C394

2

SCD47U6D3V2KX-GP

12

C128

SC4D7U6D3V3KX-GP

1

3

BAT54-7-F-GP

12

C408

SC1U10V3KX-3GP

12

C133

SCD1U10V2KX-4GP

12

C440

SC1KP50V2KX-1GP

12

C445

SC10U6D3V5MX-3GP

1

C90

2

SCD47U6D3V2KX-GP

1

SSID = MCH

+1.05V_VCCP

12

D22

DY

12

1 2

12

TC3

EC48

DY

SCD1U25V3KX-GP

ST220U2D5VBM-LGP

+3.3V_RUN +3.3V_VCC_HV

R396

2

R373

1 2

0R0603-PAD

C407

C407 SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

R97

1 2

0R0805-PAD

R100

R100 1R3F-GP

1R3F-GP

C137

C137 SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

R405

1 2

0R0603-PAD

C449

C449 SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

C446

C446 SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

C185

C185 SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

Title

Size Document Number Rev

Custom

Date: Sheet

12

10R2J-2-GP

+1.05V_VCCP

+1.8V_SUS

+1.05V_VCCP

+1.05V_VCCP+5V_RUN

Cantiga-Power/Filter(5/6)

R398

1 2

0R0402-PAD

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Roberts

12

C437

C437 SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

12 58Thursday, September 11, 2008

A00

of

DCCBB

A

SSID = MCH

U52I

AU48

VSS

AR48

VSS

AL48

VSS

BB47

VSS

AW47

VSS

AN47

VSS

AJ47

VSS

AF47

D

A

VSS

AD47

VSS

AB47

VSS

Y47

VSS

T47

VSS

N47

VSS

L47

VSS

G47

VSS

BD46

VSS

BA46

VSS

AY46

VSS

AV46

VSS

AR46

VSS

AM46

VSS

V46

VSS

R46

VSS

P46

VSS

H46

VSS

F46

VSS

BF44

VSS

AH44

VSS

AD44

VSS

AA44

VSS

Y44

VSS

U44

VSS

T44

VSS

M44

VSS

F44

VSS

BC43

VSS

AV43

VSS

AU43

VSS

AM43

VSS

J43

VSS

C43

VSS

BG42

VSS

AY42

VSS

AT42

VSS

AN42

VSS

AJ42

VSS

AE42

VSS

N42

VSS

L42

VSS

BD41

VSS

AU41

VSS

AM41

VSS

AH41

VSS

AD41

VSS

AA41

VSS

Y41

VSS

U41

VSS

T41

VSS

M41

VSS

G41

VSS

B41

VSS

BG40

VSS

BB40

VSS

AV40

VSS

AN40

VSS

H40

VSS

E40

VSS

AT39

VSS

AM39

VSS

AJ39

VSS

AE39

VSS

N39

VSS

L39

VSS

B39

VSS

BH38

VSS

BC38

VSS

BA38

VSS

AU38

VSS

AH38

VSS

AD38

VSS

AA38

VSS

Y38

VSS

U38

VSS

T38

VSS

J38

VSS

F38

VSS

C38

VSS

BF37

VSS

BB37

VSS

AW37

VSS

AT37

VSS

AN37

VSS

AJ37

VSS

H37

VSS

C37

VSS

BG36

VSS

BD36

VSS

AK15

VSS

AU36

VSS

CANTIGA-GM-GP-U-NF

5

VSS

9 OF 10

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

AM36 AE36 P36 L36 J36 F36 B36 AH35 AA35 Y35 U35 T35 BF34 AM34 AJ34 AF34 AE34 W34 B34 A34 BG33 BC33 BA33 AV33 AR33 AL33 AH33 AB33 P33 L33 H33 N32 K32 F32 C32 A31 AN29 T29 N29 K29 H29 F29 A29 BG28 BD28 BA28 AV28 AT28 AR28 AJ28 AG28 AE28 AB28 Y28 P28 K28 H28 F28 C28 BF26 AH26 AF26 AB26 AA26 C26 B26 BH25 BD25 BB25 AV25 AR25 AJ25 AC25 Y25 N25 L25 J25 G25 E25 BF24 AD12 AY24 AT24 AJ24 AH24 AF24 AB24 R24 L24 K24 J24 G24 F24 E24 BH23 AG23 Y23 B23 A23 AJ6

U52J

BG21

VSS

L12

VSS

AW21

VSS

AU21

VSS

AP21

VSS

AN21

VSS

AH21

VSS

AF21

VSS

AB21

VSS

R21

VSS

M21

VSS

J21

VSS

G21

VSS

BC20

VSS

BA20

VSS

AW20

VSS

AT20

VSS

AJ20

VSS

AG20

VSS

Y20

VSS

N20

VSS

K20

VSS

F20

VSS

C20

VSS

A20

VSS

BG19

VSS

A18

VSS

BG17

VSS

BC17

VSS

AW17

VSS

AT17

VSS

R17

VSS

M17

VSS

H17

VSS

C17

VSS

BA16

VSS

AU16

VSS

AN16

VSS

N16

VSS

K16

VSS

G16

VSS

E16

VSS

BG15

VSS

AC15

VSS

W15

VSS

A15

VSS

BG14

VSS

AA14

VSS

C14

VSS

BG13

VSS

BC13

VSS

BA13

VSS

AN13

VSS

AJ13

VSS

AE13

VSS

N13

VSS

L13

VSS

G13

VSS

E13

VSS

BF12

VSS

AV12

VSS

AT12

VSS

AM12

VSS

AA12

VSS

J12

VSS

A12

VSS

BD11

VSS

BB11

VSS

AY11

VSS

AN11

VSS

AH11

VSS

Y11

VSS

N11

VSS

G11

VSS

C11

VSS

BG10

VSS

AV10

VSS

AT10

VSS

AJ10

VSS

AE10

VSS

AA10

VSS

M10

VSS

BF9

VSS

BC9

VSS

AN9

VSS

AM9

VSS

AD9

VSS

G9

VSS

B9

VSS

BH8

VSS

BB8

VSS

AV8

VSS

AT8

VSS

CANTIGA-GM-GP-U-NF

4

VSS

VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF

VSS NCTF

VSS_NCTF VSS_NCTF

VSS_SCB VSS_SCB VSS_SCB VSS_SCB VSS_SCB

VSS SCB

NC

10 OF 10

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSS VSS VSS VSS

NC#E1 NC#D2 NC#C3 NC#B4 NC#A5

NC#A6 NC#A43 NC#A44 NC#B45 NC#C46 NC#D47 NC#B47 NC#A46

NC#F48 NC#E48 NC#C48 NC#B48

AH8 Y8 L8 E8 B8 AY7 AU7 AN7 AJ7 AE7 AA7 N7 J7 BG6 BD6 AV6 AT6 AM6 M6 C6 BA5 AH5 AD5 Y5 L5 J5 H5 F5 BE4

BC3 AV3 AL3 R3 P3 F3 BA2 AW2 AU2 AR2 AP2 AJ2 AH2 AF2 AE2 AD2 AC2 Y2 M2 K2 AM1 AA1 P1 H1

U24 U28 U25 U29

AF32 AB32 V32 AJ30 AM29 AF29 AB29 U26 U23 AL20 V20 AC19 AL17 AJ17 AA17 U17

BH48 BH1 A48 C1 A3

E1 D2 C3 B4 A5 A6 A43 A44 B45 C46 D47 B47 A46 F48 E48 C48 B48

GMCH_GND1 GMCH_GND2 GMCH_GND3 GMCH_GND4

TP103TP103 TP80TP80 TP226TP226 TP78TP78

+3.3V_RUN

NCTF PIN

3

RN19

1 2 3

SRN2K2J-1-GP

LDDC_CLK

4

LDDC_DATA

GMCH_HSYNC45

CRT_IREF routing Trace width use 20 mil.

GMCH_VSYNC45

M_BLUE45 M_GREEN45 M_RED45

DDC_CLK_CON45

LBKLT_CTL35 GMCH_BL_ON24

+3.3V_RUN

4

R144 2K37R2F-GPR144 2K37R2F-GP

VGA_TXACLK-35 VGA_TXACLK+35 VGA_TXBCLK-35 VGA_TXBCLK+35

VGA_TXAOUT0-35 VGA_TXAOUT1-35 VGA_TXAOUT2-35

VGA_TXAOUT0+35 VGA_TXAOUT1+35 VGA_TXAOUT2+35

VGA_TXBOUT0-35 VGA_TXBOUT1-35 VGA_TXBOUT2-35

VGA_TXBOUT0+35 VGA_TXBOUT1+35 VGA_TXBOUT2+35

R389 75R2F-2-GPR389 75R2F-2-GP

1 2

R386 75R2F-2-GPR386 75R2F-2-GP

1 2

R385 75R2F-2-GPR385 75R2F-2-GP

1 2

R376 150R2F-1-GPR376 150R2F-1-GP R379 150R2F-1-GPR379 150R2F-1-GP R381 150R2F-1-GPR381 150R2F-1-GP

RN41

SRN10KJ-5-GP

LDDC_CLK35 LDDC_DATA35 LCDVDD_EN35

1 2 1 2 1 2

GMCH_DDCDATA

DDC_CLK_CON

L_CTRL_DATA

1

L_CTRL_CLK

23

12

TP225TP225

1 2

R123 33R2J-2-GPR123 33R2J-2-GP

1 2

R124 1K02R2F-1-GPR124 1K02R2F-1-GP

1 2

R392 33R2J-2-GPR392 33R2J-2-GP

LIBG LVDS_VBG

TV_DACA TV_DACB TV_DACC

M_BLUE M_GREEN M_RED

GMCH_DDCCLK GMCH_DDCDATA GMCH_HS

CRT_IREF

GMCH_VS

+3.3V_RUN

U4

5 6

2N7002SPT

2

U52C

L32

L_BKLT_CTRL

G32

L_BKLT_EN

M32

L_CTRL_CLK

M33

L_CTRL_DATA

K33

L_DDC_CLK

J33

L_DDC_DATA

M29

L_VDD_EN

C44

LVDS_IBG

B43

LVDS_VBG

E37

LVDS_VREFH

E38

LVDS_VREFL

C41

LVDSA_CLK#

C40

LVDSA_CLK

B37

LVDSB_CLK#

A37

LVDSB_CLK

H47

LVDSA_DATA#_0

E46

LVDSA_DATA#_1

G40

LVDSA_DATA#_2

A40

LVDSA_DATA#_3

H48

LVDSA_DATA_0

D45

LVDSA_DATA_1

F40

LVDSA_DATA_2

B40

LVDSA_DATA_3

A41

LVDSB_DATA#_0

H38

LVDSB_DATA#_1

G37

LVDSB_DATA#_2

J37

LVDSB_DATA#_3

B42

LVDSB_DATA_0

G38

LVDSB_DATA_1

F37

LVDSB_DATA_2

K37

LVDSB_DATA_3

F25

TVA_DAC

H25

TVB_DAC

K25

TVC_DAC

H24

TV_RTN

C31

TV_DCONSEL_0

E32

TV_DCONSEL_1

E28

CRT_BLUE

G28

CRT_GREEN

J28

CRT_RED

G29

CRT_IRTN

H32

CRT_DDC_CLK

J32

CRT_DDC_DATA

J29

CRT_HSYNC

E29

CRT_TVO_IREF

L29

CRT_VSYNC

CANTIGA-GM-GP-U-NF

34 2 1

5V @ ext. CRT side

1

3 OF 10

PEG_CMP

PEG_COMPI

PEG_COMPO

PEG_RX#_0 PEG_RX#_1 PEG_RX#_2 PEG_RX#_3 PEG_RX#_4 PEG_RX#_5 PEG_RX#_6 PEG_RX#_7 PEG_RX#_8 PEG_RX#_9

PEG_RX#_10

LVDS

TV VGA

+3.3V_RUN

RN2

23 1

4

SRN2K2J-1-GP

DDC_DATA_CON

GMCH_DDCCLK

Title

Size Document Number Rev

Custom

Date: Sheet

PEG_RX#_11 PEG_RX#_12 PEG_RX#_13 PEG_RX#_14 PEG_RX#_15

PEG_RX_10 PEG_RX_11 PEG_RX_12 PEG_RX_13 PEG_RX_14 PEG_RX_15

PEG_TX#_0 PEG_TX#_1 PEG_TX#_2 PEG_TX#_3 PEG_TX#_4 PEG_TX#_5 PEG_TX#_6 PEG_TX#_7 PEG_TX#_8

PEG_TX#_9 PEG_TX#_10 PEG_TX#_11 PEG_TX#_12

PCI-EXPRESS GRAPHICS

PEG_TX#_13 PEG_TX#_14 PEG_TX#_15

PEG_TX_10

PEG_TX_11

PEG_TX_12

PEG_TX_13

PEG_TX_14

PEG_TX_15

DDC_DATA_CON 45

Cantiga-GND/LVDS/VGA(6/6)

T37 T36

H44 J46 L44 L40 N41 P48 N44 T43 U43 Y43 Y48 Y36 AA43 AD37 AC47 AD39

H43

PEG_RX_0

J44

PEG_RX_1

L43

PEG_RX_2

L41

PEG_RX_3

N40

PEG_RX_4

P47

PEG_RX_5

N43

PEG_RX_6

T42

PEG_RX_7

U42

PEG_RX_8

Y42

PEG_RX_9

W47 Y37 AA42 AD36 AC48 AD40

J41 M46 M47 M40 M42 R48 N38 T40 U37 U40 Y40 AA46 AA37 AA40 AD43 AC46

J42

PEG_TX_0

L46

PEG_TX_1

M48

PEG_TX_2

M39

PEG_TX_3

M43

PEG_TX_4

R47

PEG_TX_5

N37

PEG_TX_6

T39

PEG_TX_7

U36

PEG_TX_8

U39

PEG_TX_9

Y39 Y46 AA36 AA39 AD42 AD46

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Roberts

+1.05V_VCCP

R133

R133 49D9R2F-GP

49D9R2F-GP

1 2

Place R105 close to MCH within 500 mils.

of

13 58Thursday, October 02, 2008

A00

5

SSID = MEMORY

M_A_DQS#[7..0]10

D D

+1.8V_SUS

DY

12

C101

12

C132

SC2D2U10V3KX-1GP

12

C409

DY

SCD1U16V2KX-3GP

C C

+0.9V_DDR_VTT

B B

A A

M_A_DQ[63..0]10 M_A_DM[7..0]10 M_A_DQS[7..0]10 M_A_A[14..0]10

Layout Note: Place near DM1

DY

12

C138

12

C83

12

C116

DY

SC2D2U10V3KX-1GP

12

C432

DY

SCD1U16V2KX-3GP

12

C122

C160

DY

SC2D2U10V3KX-1GP

Layout Note: Place one cap close to every 2 pullup resistors terminated to +0.9V_DDR_VTT.

12

C96

C103

SCD1U16V2KX-3GP

5

12

C93

C109

SCD1U16V2KX-3GP

12

C87

C114

DY

SCD1U16V2KX-3GP

4

12

C100

SCD1U16V2KX-3GP

12

C118

DY

SCD1U16V2KX-3GP

+V_DDR_MCH_REF

C203

4

12

C106

SCD1U16V2KX-3GP

12

C119

SCD1U16V2KX-3GP

12

DY

12

TC8

12

C115

M_A_BS#210 M_A_BS#010

M_A_BS#110

ST220U2D5VBM-LGP

12

C428

SCD1U16V2KX-3GP

M_ODT09 M_ODT19

12

DY

M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14

M_A_BS#2 M_A_BS#0

M_A_BS#1

M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48

C420

C202

C202 SC2D2U10V3KX-1GP

SC2D2U10V3KX-1GP

M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53

SCD1U16V2KX-3GP

M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63

M_A_DQS#0 M_A_DQS#1 M_A_DQS#2 M_A_DQS#3 M_A_DQS#4 M_A_DQS#5 M_A_DQS#6 M_A_DQS#7

M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6 M_A_DQS7

M_ODT0 M_ODT1

3

DM2

102

A0

101

A1

100

A2

99

A3

98

A4

97

A5

94

A6

92

A7

93

A8

91

A9

105

A10/AP

90

A11

89

A12

116

A13

86

A14

84

A15

85

A16/BA2

107

BA0

106

BA1

5

DQ0

7

DQ1

17

DQ2

19

DQ3

4

DQ4

6

DQ5

14

DQ6

16

DQ7

23

DQ8

25

DQ9

35

DQ10

37

DQ11

20

DQ12

22

DQ13

36

DQ14

38

DQ15

43

DQ16

45

DQ17

55

DQ18

57

DQ19

44

DQ20

46

DQ21

56

DQ22

58

DQ23

61

DQ24

63

DQ25

73

DQ26

75

DQ27

62

DQ28

64

DQ29

74

DQ30

76

DQ31

123

DQ32

125

DQ33

135

DQ34

137

DQ35

124

DQ36

126

DQ37

134

DQ38

136

DQ39

141

DQ40

143

DQ41

151

DQ42

153

DQ43

140

DQ44

142

DQ45

152

DQ46

154

DQ47

157

DQ48

159

DQ49

173

DQ50

175

DQ51

158

DQ52

160

DQ53

174

DQ54

176

DQ55

179

DQ56

181

DQ57

189

DQ58

191

DQ59

180

DQ60

182

DQ61

192

DQ62

194

DQ63

11

DQS0#

29

DQS1#

49

DQS2#

68

DQS3#

129

DQS4#

146

DQS5#

167

DQS6#

186

DQS7#

13

DQS0

31

DQS1

51

DQS2

70

DQS3

131

DQS4

148

DQS5

169

DQS6

188

DQS7

114

OTD0

119

OTD1

1

VREF

2

VSS

202

GND

MH1

SKT-SODIMM200-37GP 62.10017.E21

3

VDDSPD

NC#50 NC#69 NC#83

NC#120

NC#163/TEST

RAS#

WE#

CAS#

CS0# CS1#

CKE0 CKE1

CK0

CK0#

CK1

CK1#

DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7

SDA SCL

SA0 SA1

VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSS GND MH2

108 109 113

110 115

79 80

M_CLK_DDR0

30

M_CLK_DDR#0

32

M_CLK_DDR1

164

M_CLK_DDR#1

166

M_A_DM0

10

M_A_DM1

26

M_A_DM2

52

M_A_DM3

67

M_A_DM4

130

M_A_DM5

147

M_A_DM6

170

M_A_DM7

185

ICH_SMBDATA

195

ICH_SMBCLK

197 199

R55 10KR2J-3-GPR55 10KR2J-3-GP

198

1 2

R56 10KR2J-3-GPR56 10KR2J-3-GP

200

1 2

50 69 83 120 163

+1.8V_SUS

81 82 87 88 95 96 103 104 111 112 117 118

3 8 9 12 15 18 21 24 27 28 33 34 39 40 41 42 47 48 53 54 59 60 65 66 71 72 77 78 121 122 127 128 132 133 138 139 144 145 149 150 155 156 161 162 165 168 171 172 177 178 183 184 187 190 193 196

201 MH2

2

+3.3V_RUN

2

M_A_RAS# 10

M_A_WE# 10

M_A_CAS# 10 M_CS0# 9

M_CS1# 9 M_CKE0 9

M_CKE1 9 M_CLK_DDR0 9

M_CLK_DDR#0 9 M_CLK_DDR1 9

M_CLK_DDR#1 9

ICH_SMBDATA 4,15,18 ICH_SMBCLK 4,15,18

PM_EXTTS#0 9

1

put near connector

M_CLK_DDR0 M_CLK_DDR#0 M_CLK_DDR1 M_CLK_DDR#1

12

C74

DUMMY-C2

12

C53

SC2D2U10V3KX-1GP

RN6

SRN56J-4-GP

SRN56J-4-GP RN35

RN35

SRN56J-4-GP

SRN56J-4-GP RN10

RN10

SRN56J-4-GP

SRN56J-4-GP RN33

RN33

SRN56J-4-GP

SRN56J-4-GP RN39

RN39

SRN56J-4-GP

SRN56J-4-GP RN8

RN8

SRN56J-4-GP

SRN56J-4-GP RN17

RN17

SRN56J-4-GP

1

1 23

4

1 23

12

M_A_A13

M_A_A5 M_A_A8

M_A_A6 M_A_A2

M_A_A1 M_A_A3

M_CKE0 M_A_BS#2

M_A_BS#1 M_A_RAS#

M_A_A0 M_A_A4

14 58Thursday, October 02, 2008

C192

DUMMY-C2

of

12

C72

DUMMY-C2

+3.3V_RUN

12

C54

DY

SCD1U16V2KX-3GP

Layout Note: Place these resistors close to DM1, all trace length Max=1.5".

+0.9V_DDR_VTT

RN37

Custom

RN37

1 2 3

4

SRN56J-4-GP

RN31

1

4

23

SRN56J-4-GP

RN4

1

4

23

SRN56J-4-GP

RN12

1

4

23

SRN56J-4-GP

RN29

SRN56J-4-GP

RN28

SRN56J-4-GP

RN11

SRN56J-4-GP

DDRII-SODIMM SLOT1

1

2 3

23

1

4

23

4

1 23

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Roberts

M_A_A9 M_A_A12

M_A_A10 M_A_BS#0

M_ODT0 M_CS0#

M_CKE1 M_A_A14

M_A_WE# M_A_CAS#

M_CS1# M_ODT1

M_A_A11 M_A_A7

Title

Size Document Number Rev

Date: Sheet

12

C195

DUMMY-C2

A00

5

SSID = MEMORY

M_B_DQS#[7..0]10

D D

+1.8V_SUS

C C

+0.9V_DDR_VTT

B B

A A

DY

12

C430

12

C136

SC2D2U10V3KX-1GP

12

C415

SCD1U16V2KX-3GP

M_B_DQ[63..0]10 M_B_DM[7..0]10 M_B_DQS[7..0]10 M_B_A[14..0]10

Layout Note: Place near DM2

12

C97

C107

DY

12

5

C107

SC2D2U10V3KX-1GP

Layout Note: Place one cap close to every 2 pullup resistors terminated to +0.9V_DDR_VTT.

12

C425

C418

DY

SCD1U16V2KX-3GP

12

C112

SC2D2U10V3KX-1GP

12

C414

SCD1U16V2KX-3GP

12

C105

SC2D2U10V3KX-1GP

12

C406

SCD1U16V2KX-3GP

12

C124

SCD1U16V2KX-3GP

12

C405

SCD1U16V2KX-3GP

DY

12

C150

12

C95

4

12

C104

SCD1U16V2KX-3GP

12

C410

DY

SCD1U16V2KX-3GP

4

12

C131

DY

SCD1U16V2KX-3GP

12

C117

SCD1U16V2KX-3GP

+V_DDR_MCH_REF

12

TC4

ST220U2D5VBM-LGP

12

C88

C404

DY

SCD1U16V2KX-3GP

ICH_SMBCLK4,14,18

ICH_SMBDATA4,14,18

C200

C200 SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

M_B_BS#210

M_B_BS#010 M_B_BS#110

12

PM_EXTTS#19

M_CS2#9

M_CS3#9 M_CKE29

M_CKE39 M_B_RAS#10 M_B_CAS#10

M_B_WE#10

M_ODT29

M_ODT39

C102

SCD1U16V2KX-3GP

12

C201

C201 SC2D2U10V3KX-1GP

SC2D2U10V3KX-1GP

M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14

M_B_BS#2

M_B_BS#0 M_B_BS#1

M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63

ICH_SMBCLK ICH_SMBDATA

M_ODT2 M_ODT3

3

DM1

MH1

102

A0

101

A1

100

A2

99

A3

98

A4

97

A5

94

A6

92

A7

93

A8

91

A9

105

A10/AP

90

A11

89

A12

116

A13

86

A14

84

A15

85

A16_BA2

107

BA0

106

BA1

5

DQ0

7

DQ1

17

DQ2

19

DQ3

4

DQ4

6

DQ5

14

DQ6

16

DQ7

23

DQ8

25

DQ9

35

DQ10

37

DQ11

20

DQ12

22

DQ13

36

DQ14

38

DQ15

43

DQ16

45

DQ17

55

DQ18

57

DQ19

44

DQ20

46

DQ21

56

DQ22

58

DQ23

61

DQ24

63

DQ25

73

DQ26

75

DQ27

62

DQ28

64

DQ29

74

DQ30

76

DQ31

123

DQ32

125

DQ33

135

DQ34

137

DQ35

124

DQ36

126

DQ37

134

DQ38

136

DQ39

141

DQ40

143

DQ41

151

DQ42

153

DQ43

140

DQ44

142

DQ45

152

DQ46

154

DQ47

157

DQ48

159

DQ49

173

DQ50

175

DQ51

158

DQ52

160

DQ53

174

DQ54

176

DQ55

179

DQ56

181

DQ57

189

DQ58

191

DQ59

180

DQ60

182

DQ61

192

DQ62

194

DQ63

50

NC#50

69

NC#69

83

NC#83

120

NC#120

163

NC#163/TEST

110

CS0#

115

CS1#

79

CKE0

80

CKE1

108

RAS#

113

CAS#

109

WE#

197

SCL

195

SDA

114

ODT0

119

ODT1

1

VREF

201

GND

SKT-SODIMM200-38GP

62.10017.E31

MH2

DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6

DQS7 DQS0# DQS1# DQS2# DQS3# DQS4# DQS5# DQS6# DQS7#

DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7

CK0

CK0#

CK1

CK1#

SA0 SA1

VDD_SPD

VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

GND

MH2

M_B_DQS0

13

M_B_DQS1

31

M_B_DQS2

51

M_B_DQS3

70

M_B_DQS4

131

M_B_DQS5

148

M_B_DQS6

169

M_B_DQS7

188

M_B_DQS#0

11

M_B_DQS#1

29

M_B_DQS#2

49

M_B_DQS#3

68

M_B_DQS#4

129

M_B_DQS#5

146

M_B_DQS#6

167

M_B_DQS#7

186

M_B_DM0

10

M_B_DM1

26

M_B_DM2

52

M_B_DM3

67

M_B_DM4

130

M_B_DM5

147

M_B_DM6

170

M_B_DM7

185

M_CLK_DDR2

30

M_CLK_DDR#2

32

M_CLK_DDR3

164

M_CLK_DDR#3

166

R57 10KR2J-3-GPR57 10KR2J-3-GP

198

1 2

R54 10KR2J-3-GPR54 10KR2J-3-GP

200

1 2

199

+1.8V_SUS

81 82 87 88 95 96 103 104 111 112 117 118

2 3 8 9 12 15 18 21 24 27 28 33 34 39 40 41 42 47 48 53 54 59 60 65 66 71 72 77 78 121 122 127 128 132 133 138 139 144 145 149 150 155 156 161 162 165 168 171 172 177 178 183 184 187 190 193 196

202

2

M_CLK_DDR2 9 M_CLK_DDR#2 9 M_CLK_DDR3 9 M_CLK_DDR#3 9

+3.3V_RUN

2

1

put near connector

M_CLK_DDR2 M_CLK_DDR#2 M_CLK_DDR3 M_CLK_DDR#3

12

C71

C75

DUMMY-C2

+3.3V_RUN

12

C52

+3.3V_RUN

12

EC12

EC12 SCD1U25V3KX-GP

SCD1U25V3KX-GP

Layout Note: Place these resistors close to DM2, all trace length Max=1.5".

+0.9V_DDR_VTT

RN7

M_B_WE# M_B_CAS#

M_B_BS#2 M_CKE2

M_B_A5 M_B_A8

M_B_A0

M_B_A1 M_B_A3

M_ODT3 M_CS3#

M_CKE3

RN7

1

4

23

SRN56J-4-GP

RN13

1

4

23

SRN56J-4-GP

RN16

1

4

23

SRN56J-4-GP

RN32

1

4

23

SRN56J-4-GP

RN15

1

4

23

SRN56J-4-GP

RN5

1

4

23

SRN56J-4-GP

RN40

1

4

23

SRN56J-4-GP

Title

DDRII-SODIMM SLOT2

Size Document Number Rev

Custom

Date: Sheet

DDRII-SODIMM SLOT2

C52

DY

SCD1U16V2KX-3GP

RN27

4

SRN56J-4-GP

SRN56J-4-GP RN38

RN38

4

SRN56J-4-GP

SRN56J-4-GP RN36

RN36

4

SRN56J-4-GP

SRN56J-4-GP RN34

RN34

4

SRN56J-4-GP

RN9

4

SRN56J-4-GP

SRN56J-4-GP RN30

RN30

4

SRN56J-4-GP

SRN56J-4-GP RN14

RN14

4

SRN56J-4-GP

M_ODT2

1

M_B_A13

23

M_B_A14

1

M_B_A11

23

M_B_A7

1

M_B_A6

23

M_B_A4M_B_BS#1

1

M_B_A2

23

M_B_A10

1

M_B_BS#0

23

M_B_RAS#

1

M_CS2#

23

M_B_A12

1

M_B_A9

23

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Roberts

1

12

C193

DUMMY-C2

C56

SC2D2U10V3KX-1GP

of

15 58Thursday, October 02, 2008

12

C197

DUMMY-C2

A00

5

SSID = ICH

5 OF 6

U25E

AA26

VSS

AA27

VSS

AA3

VSS

AA6

VSS

AB1

VSS

AA23

VSS

AB28

D D

C C

B B

A A

AB29

AB4

AB5 AC17 AC26 AC27

AC3

AD1 AD10 AD12 AD13 AD14 AD17 AD18 AD21 AD28 AD29

AD4

AD5

AD6

AD7

AD9 AE12 AE13 AE14 AE16 AE17

AE2 AE20 AE24

AE3

AE4

AE6

AE9 AF13 AF16 AF18 AF22 AH26 AF26 AF27

AF5

AF7

AF9 AG13 AG16 AG18 AG20 AG23

AG3

AG6

AG9 AH12 AH14 AH17 AH19

AH2 AH22 AH25 AH28

AH5

AH8

AJ12 AJ14 AJ17

C26

C27

G12

G14

G18

G21

G24

G26

G27

H23

H28

H29

AJ8 B11 B14 B17

B2 B20 B23

B5

B8

E11 E14 E18

E2 E21 E24

E5

E8 F16 F28 F29

G8 H2

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

ICH9M-GP-NF

5

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

H5 J23 J26 J27 AC22 K28 K29 L13 L15 L2 L26 L27 L5 L7 M12 M13 M14 M15 M16 M17 M23 M28 M29 N11 N12 N13 N14 N15 N16 N17 N18 N26 N27 P12 P13 P14 P15 P16 P17 P2 P23 P28 P29 P4 P7 R11 R12 R13 R14 R15 R16 R17 R18 R28 T12 T13 T14 T15 T16 T17 T23 B26 U12 U13 U14 U15 U16 U17 AD23 U26 U27 U3 V1 V13 V15 V23 V28 V29 V4 V5 W26 W27 W3 Y1 Y28 Y29 Y4 Y5 AG28 AH6 AF2 B25

A1 A2 A28 A29 AH1 AH29 AJ1 AJ2 AJ28 AJ29 B1 B29

Mini Card

New Card

ICH_GND1

ICH_GND2

ICH_GND3

ICH_GND4

+3.3V_ALW

LAN

TP177TP177

TP178TP178

TP125TP125

TP127TP127

PLT_RST#9,20,21,24,37,41

SPI_WP# SPI_MOSO SPI_CS#0

NCTF PIN

USB_OC#7 USB_OC#11

USB_OC#4

PCIE_RXN237 PCIE_RXP237

PCIE_TXN237 PCIE_TXP237

PCIE_RXN320 PCIE_RXP320

PCIE_TXN320 PCIE_TXP320

PCIE_RXN541 PCIE_RXP541

PCIE_TXN541 PCIE_TXP541

4

+3.3V_RUN

PLT_RST#

R245

1 2

DY

10KR2J-3-GP

U27

4

GND

3

WP#

SCLK

DY

2

SO

HOLD#

1

CS#

VCC

MX25L512MC-12G-GP

RP1

1 2 3 4 5 6

SRN10KJ-L3-GP

C500 SCD1U16V2KX-3GPC500 SCD1U16V2KX-3GP C497 SCD1U16V2KX-3GPC497 SCD1U16V2KX-3GP

C506 SCD1U16V2KX-3GPC506 SCD1U16V2KX-3GP C510 SCD1U16V2KX-3GPC510 SCD1U16V2KX-3GP

C518 SCD1U16V2KX-3GPC518 SCD1U16V2KX-3GP C517 SCD1U16V2KX-3GPC517 SCD1U16V2KX-3GP

SPI_CLK

R233 15R2J-GP

SPI_CS#0

R241 15R2J-GP

SPI_MOSI

R230 15R2J-GP

SPI_MOSO

R237 15R2J-GP

4

U32

5 4

74LVC1G08GW-1-GP

1 2

0R0402-PAD

5

SI

6 7 8

1 2

DY

1 2

DY

1 2

DY

1 2

DY

USB_OC#045 USB_OC#145 USB_OC#243

VCC Y

10 9 8 7

R262

DY

12 12

B A

GND

10KR2J-3-GP

SPI_MOSI SPI_CLK SPI_HOLD#

USB_OC#0 USB_OC#1USB_OC#5 USB_OC#6 USB_OC#2

R208

1 2

22R2F-1-GP

3

1

PCI_PLTRST#

2 3

+3.3V_RUN

12

R240

DY

+3.3V_ALW +3.3V_ALW

PCIE_C_TXN2 PCIE_C_TXP2

PCIE_C_TXN3 PCIE_C_TXP3

PCIE_C_TXN5 PCIE_C_TXP5

SPI_CLK_R SPI_CS#0_R SPI_CS#1

SPI_MOSI_R SPI_MOSO_R

USB_OC#0 USB_OC#1 USB_OC#2 USB_OC#3 USB_OC#4 USB_OC#5 USB_OC#6 USB_OC#7 USB_OC#8 USB_OC#9 USB_OC#10 USB_OC#11

USB_RBIAS_PN

C315

DY

SCD1U16V2KX-3GP

N29 N28 P27 P26

L29

L28 M27 M26

K27

K26

G29

G28

H27

H26

E29

E28

F27

F26

C29

C28

D27

D26

D23

D24

F23

D25

E23

AG2 AG1

U25D

PERN1 PERP1 PETN1 PETP1

PERN2 PERP2 PETN2 PETP2

J29

PERN3

J28

PERP3 PETN3 PETP3

PERN4 PERP4 PETN4 PETP4

PERN5 PERP5 PETN5 PETP5

PERN6/GLAN_RXN PERP6/GLAN_RXP PETN6/GLAN_TXN PETP6/GLAN_TXP

SPI_CLK SPI_CS0# SPI_CS1#/GPIO58/CLGPIO6

SPI_MOSI SPI_MISO

N4

OC0#/GPIO59

N5

OC1#/GPIO40

N6

OC2#/GPIO41

P6

OC3#/GPIO42

M1

OC4#/GPIO43

N2

OC5#/GPIO29

M4

OC6#/GPIO30

M3

OC7#/GPIO31

N3

OC8#/GPIO44

N1

OC9#/GPIO45

P5

OC10#/GPIO46

P3

OC11#/GPIO47 USBRBIAS

USBRBIAS#

ICH9M-GP-NF

3

PCI_PIRQA# PCI_PIRQB# PCI_PIRQC# PCI_PIRQD#

RN55

8 7 6

SRN8K2J-4-GP

4 OF 6

V27

DMI0RXN

V26

DMI0RXP

U29

DMI0TXN

U28

DMI0TXP

Y27

DMI1RXN

Y26

DMI1RXP

W29

DMI1TXN

W28

DMI1TXP

AB27

DMI2RXN

AB26

DMI2RXP

AA29

DMI2TXN

AA28

DMI2TXP

AD27

DMI3RXN

AD26

DMI3RXP

AC29

DMI3TXN

AC28

DMI3TXP

T26

DMI_CLKN

PCI-Express

DMI_ZCOMP

DMI_IRCOMP

SPI

USB

T25

DMI_CLKP

Direct Media Interface

AF29 AF28

AC5

USBP0N

AC4

USBP0P

AD3

USBP1N

AD2

USBP1P

AC1

USBP2N

AC2

USBP2P

AA5

USBP3N

AA4

USBP3P

AB2

USBP4N

AB3

USBP4P

AA1

USBP5N

AA2

USBP5P

W5

USBP6N

W4

USBP6P

Y3

USBP7N

Y2

USBP7P

W1

USBP8N

W2

USBP8P

V2

USBP9N

V3

USBP9P

U5

USBP10N

U4

USBP10P

U1

USBP11N

U2

USBP11P

U25B

D11

AD0

C8

AD1

D9

AD2

E12

AD3

E9

AD4

C9

AD5

E10

AD6

B7

AD7

C7

AD8

C5

AD9

G11

AD10

F8

AD11

F11

AD12

E7

AD13

A3

AD14

D2

AD15

F10

AD16

D5

AD17

D10

AD18

B3

AD19

F7

AD20

C3

AD21

F3

AD22

F4

AD23

C1

AD24

G7

AD25

H7

AD26

D1

AD27

G5

AD28

H6

AD29

G1

AD30

H3

AD31

Interrupt I/F

J5

PIRQA#

E1

PIRQB#

J6

PIRQC#

C4

PIRQD#

ICH9M-GP-NF

USB_OC#9

1

USB_OC#8

2

USB_OC#10

3

USB_OC#3

45

DMI_IRCOMP_R

USB_PN3 USB_PP3

USB_PN5 USB_PP5

USB_PN8 USB_PP8 USB_PN9 USB_PP9 USB_PN10 USB_PP10

2

2 OF 6

PCI

REQ1#/GPIO50 GNT1#/GPIO51 REQ2#/GPIO52 GNT2#/GPIO53 REQ3#/GPIO54 GNT3#/GPIO55

PCIRST#

DEVSEL#

PLOCK#

FRAME#

PLTRST#

PIRQE#/GPIO2 PIRQF#/GPIO3 PIRQG#/GPIO4 PIRQH#/GPIO5

DMI_RXN0 9 DMI_RXP0 9 DMI_TXN0 9 DMI_TXP0 9

DMI_RXN1 9 DMI_RXP1 9 DMI_TXN1 9 DMI_TXP1 9

DMI_RXN2 9 DMI_RXP2 9 DMI_TXN2 9 DMI_TXP2 9

DMI_RXN3 9 DMI_RXP3 9 DMI_TXN3 9 DMI_TXP3 9

CLK_PCIE_ICH# 4 CLK_PCIE_ICH 4

USB_PN0 45 USB_PP0 45 USB_PN1 45 USB_PP1 45 USB_PN2 43

USB_PP2 43

TP246TP246 TP247TP247

USB_PN4 37

USB_PP4 37

TP250TP250 TP251TP251

USB_PN6 41

USB_PP6 41

USB_PN7 41

USB_PP7 41

TP248TP248 TP249TP249 TP252TP252 TP253TP253

USB_PN10 21

USB_PP10 21

USB_PN11 41

USB_PP11 41

2

F1

REQ0#

G4

GNT0#

B6 A7 F13 F12 E6 F6

D8

C/BE0#

B4

C/BE1#

D6

C/BE2#

A5

C/BE3#

D3

IRDY#

E3

PAR

R1 C6 E4

PERR#

C2 J4

SERR#

A4

STOP#

F5

TRDY#

D7 C14

D4

PCICLK

R2

PME#

H4 K6 F2 G2

USB1 USB2 USB3

BlUETOOTH New Card

Card Reader CAMERA

1

PCI_REQ0# PCI_GNT0# PCI_REQ1# PCI_GNT1# PCI_REQ2# PCI_GNT2# PCI_REQ3# PCI_GNT3#

PCI_IRDY# PCIRST1#

PCI_DEVSEL# PCI_PERR# PCI_PLOCK# PCI_SERR# PCI_STOP# PCI_TRDY# PCI_FRAME#

PCI_PLTRST# ICH_PME#

PCI_PIRQE# PCI_PIRQF# PCI_PIRQG# PCI_PIRQH#

TP179TP179 TP261TP261

TP135TP135

CLK_PCI_ICH 4

TP138TP138

PCI_GNT0# SPI_CS#1 PCI_GNT3#

1 2

R442 1KR2J-1-GP

1 2

R443 1KR2J-1-GP

1 2

R441 1KR2J-1-GP

DY

DY DY

DY

PCI_PIRQF# PCI_TRDY# PCI_REQ3# PCI_PIRQD#

PCI_PIRQB# PCI_PIRQG# PCI_REQ0# PCI_PIRQH#

PCI_STOP# PCI_PLOCK# PCI_IRDY# PCI_PERR#

PCI_DEVSEL# PCI_REQ1# PCI_FRAME# PCI_REQ2#

PCI_SERR# PCI_PIRQE# PCI_PIRQA# PCI_PIRQC#

8 7 6

BOOT BIOS Strap

SPI_CS#1 BOOT BIOS LocationPCI_GNT#0

0 1 SPI

01

PCI

11

LPC(Default)

A16 swap override strap

low = A16 swap override enable high = default

USB Pair

0 1 2 3

Device USB1 USB2 USB3 RESERVED

+1.5V_RUN

1 2

PCI_GNT#3

R429

R429 24D9R2F-L-GP

24D9R2F-L-GP

4 MINI CARD 5

RESERVED BLUETOOTH

6 7

NEW CARD RESERVED

8

RESERVED

9 10

Card Reader

11

Title

ICH9-PCI/PCIE/DMI/USB/GND(1/4)

Size Document Number Rev

Custom

Date: Sheet

CAMERA

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Roberts

1

RN57

SRN8K2J-4-GP

SRN8K2J-4-GP RN25

RN25

SRN8K2J-4-GP

SRN8K2J-4-GP RN26

RN26

SRN8K2J-4-GP

SRN8K2J-4-GP RN58

RN58

SRN8K2J-4-GP

RN56

SRN8K2J-4-GP

of

16 58Thursday, October 02, 2008

1 2 3 45

+3.3V_RUN

A00

5

4

3

2

1

SSID = ICH

ICH_RTCX1

R445 10MR2J-L-GPR445 10MR2J-L-GP

1 2

X4

1

4

D D

SC12P50V2JN-3GP

C522

12

23

X-32D768KHZ-38GPU

ICH_RTCX2

12

C520

C520 SC12P50V2JN-3GP

SC12P50V2JN-3GP

1 OF 6

+RTC_CELL

C C

+1.5V_RUN

ICH_AZ_CODEC_BITCLK22

ICH_AZ_CODEC_SYNC22 ICH_AZ_CODEC_RST#22 ICH_SDOUT_CODEC22

12

C227

DY

SC4D7P50V2CN-1GP

DY

HDD

B B

ODD

R456

1 2

20KR2F-L-GP

C307

SC1U10V3KX-3GP

R461

1 2

20KR2F-L-GP

ICH_RTCRST#

21

12

C526

C526 SC1U10V3KX-3GP

SC1U10V3KX-3GP

G49

G49 GAP-OPEN

GAP-OPEN

Place within 500 mil of SB.

R444 24D9R2F-L-GPR444 24D9R2F-L-GP

1 2

R201 33R2J-2-GPR201 33R2J-2-GP

1 2

R197 33R2J-2-GPR197 33R2J-2-GP

1 2

R205 33R2J-2-GPR205 33R2J-2-GP

1 2

R194 33R2J-2-GPR194 33R2J-2-GP

1 2

12

C230

DY

SC4D7P50V2CN-1GP

SATA_RXN0_C36 SATA_RXP0_C36

SATA_TXN036 SATA_TXP036

SATA_RXN1_C36 SATA_RXP1_C36

SATA_TXN136 SATA_TXP136

TP235TP235

ICH_SDIN_CODEC22

C473 SCD01U50V2KX-1GPC473 SCD01U50V2KX-1GP

1 2

C474 SCD01U50V2KX-1GPC474 SCD01U50V2KX-1GP

1 2

C475 SCD01U50V2KX-1GPC475 SCD01U50V2KX-1GP

1 2

C476 SCD01U50V2KX-1GPC476 SCD01U50V2KX-1GP

1 2

R506

1 2

DY

10KR2J-3-GP

ICH_RTCRST# SRTCRST# SM_INTRUDER#

ICH_INTVRMEN LAN100_SLP

GPIO56 GLAN_COMP

ACZ_BIT_CLK ACZ_SYNC_R

ACZ_RST#_R

ACZ_SDATAOUT_R

SATA_LED#

SATA_TXN0_C SATA_TXP0_C

SATA_TXN1_C SATA_TXP1_C

U25A

C23

RTCX1

C24

RTCX2

A25

RTCRST#

F20

SRTCRST#

C22

INTRUDER#

B22

INTVRMEN

A22

LAN100_SLP

E25

GLAN_CLK

C13

LAN_RSTSYNC

F14

LAN_RXD0

G13

LAN_RXD1

D14

LAN_RXD2

D13

LAN_TXD0

D12

LAN_TXD1

E13

LAN_TXD2

B10

GLAN_DOCK#/GPIO56

B28

GLAN_COMPI

B27

GLAN_COMPO

AF6

HDA_BIT_CLK

AH4

HDA_SYNC

AE7

HDA_RST#

AF4

HDA_SDIN0

AG4

HDA_SDIN1

AH3

HDA_SDIN2

AE5

HDA_SDIN3

AG5

HDA_SDOUT

AG7

HDA_DOCK_EN#/GPIO33

AE8

HDA_DOCK_RST#/GPIO34

AG8

SATALED#

AJ16

SATA0RXN

AH16

SATA0RXP

AF17

SATA0TXN

AG17

SATA0TXP

AH13

SATA1RXN

AJ13

SATA1RXP

AG14

SATA1TXN

AF14

SATA1TXP

ICH9M-GP-NF

1 OF 6

FWH0/LAD0 FWH1/LAD1 FWH2/LAD2 FWH3/LAD3

FWH4/LFRAME#

RTCLAN / GLAN

LPCCPU

RTCLAN / GLAN

LPCCPU

LDRQ0#

LDRQ1#/GPIO23

A20GATE

A20M#

DPRSTP#

DPSLP#

FERR#

CPUPWRGD

IGNNE#

INIT#

RCIN#

STPCLK#

THRMTRIP#

SATA4RXN

IHDA

SATA4RXP

SATA4TXN SATA4TXP

SATA5RXN SATA5RXP

SATA5TXN SATA5TXP

SATA_CLKN

SATA_CLKP

SATA

SATARBIAS#

SATARBIAS

INTR

NMI

SMI#

PECI

K5 K4 L6 K2

K3 J3

J1 N7

AJ27 AJ25

AE23 AJ26 AD22 AF25 AE22

AG25 L3

AF23 AF24

AH27 AG26 AG27

AH11 AJ11 AG12 AF12

AH9 AJ9 AE10 AF10

AH18 AJ18

AJ7 AH7

LPC_LAD0 LPC_LAD1 LPC_LAD2 LPC_LAD3

H_DPRSTP#

H_FERR#_R

H_THERMTRIP_R

Placed Within 2" from SB.

SATARBIAS

Place within 500 mils from SB.

LPC_LAD[0..3]

LPC_LFRAME# 24,37

KA20GATE 24 H_A20M# 5

H_DPRSTP# 6,9,28 H_DPSLP# 6

1 2

R166 56R2J-4-GPR166 56R2J-4-GP

R165 54D9R2F-L1-GPR165 54D9R2F-L1-GP

R187 24D9R2F-L-GPR187 24D9R2F-L-GP

1 2

H_PWRGOOD 6,34 H_IGNNE# 5 H_INIT# 5

H_INTR 5

H_NMI 5 H_SMI# 5

H_STPCLK# 5

H_THERMTRIP_1

CLK_PCIE_SATA# 4 CLK_PCIE_SATA 4

LPC_LAD[0..3] 24,37

R438

1 2

DY

10KR2J-3-GP

R163

1 2

56R2J-4-GP

R242

1 2

DY

10KR2J-3-GP

R164

1 2

R167

1 2

A00.08/0903

+3.3V_RUN

+1.05V_VCCP

+3.3V_RUN

+1.05V_VCCP

56R2J-4-GP

0R2J-2-GP

H_FERR# 5

KBRCIN# 24

H_THRMTRIP# 5,9,24,34

+RTC_CELL

R448

330KR2F-L-GP

A A

330KR2F-L-GP

R271

330KR2F-L-GP

R264

1MR2J-1-GP

12

5

ICH_INTVRMEN

LAN100_SLP

SM_INTRUDER#

integrated VccSus1_05,VccSus1_5,VccCL1_5

INTVRMEN

High=Enable Low=Disable

integrated VccLan1_05VccCL1_05

LAN100_SLP

High=Enable Low=Disable

4

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

ICH9-LAN/HDA/SATA/LPC(2/4)

Size Document Number Rev

Custom

Date: Sheet

3

2

Date: Sheet

Taipei Hsien 221, Taiwan, R.O.C.

Roberts

17 58Thursday, October 02, 2008

1

A00

of

5

4

3

2

1

SSID = ICH

U25C

+3.3V_ALW

RN60

1

4

23

SRN2K2J-1-GP

D D

C C

+3.3V_RUN

B B

SRN2K2J-1-GP

R267 10KR2J-3-GPR267 10KR2J-3-GP

1 2

RN59

1

4

23

SRN10KJ-5-GP

R455 10KR2J-3-GPR455 10KR2J-3-GP

1 2

RN61

1

8

2

7

3

6

45

SRN8K2J-4-GP

R451 10KR2J-3-GPR451 10KR2J-3-GP

1 2

RN63

1

4

23

DY

SRN10KJ-5-GP

R235 8K2R2J-3-GPR235 8K2R2J-3-GP

1 2

R244 8K2R2J-3-GPR244 8K2R2J-3-GP

1 2

R247 10KR2J-3-GPR247 10KR2J-3-GP R421 10KR2J-3-GPR421 10KR2J-3-GP R424 10KR2J-3-GPR424 10KR2J-3-GP R180 8K2R2J-3-GP

R180 8K2R2J-3-GP R238 10KR2J-3-GPR238 10KR2J-3-GP

+3.3V_RUN

DY

12

DY

R449

R449 100KR2J-1-GP

100KR2J-1-GP

R446

R446 100KR2J-1-GP

100KR2J-1-GP

12 12 12 12 12

iTPM_EN

SMB_DATA SMB_CLK

ME_EC_DATA1 ME_EC_CLK1

SMB_ALERT# PM_BATLOW#_R ITP_DBRESET#_1 ICH_RI#

ECSMI#

H_STP_CPU# H_STP_PCI#

PM_CLKRUN# INT_SERIRQ GPIO18 ECSCI# ECSWI# GPIO22 CLKSATAREQ#

iTPM Select

iTPM_EN

0 = Disable 1 = Enable

A A

5

SMB_CLK37,41

SMB_DATA37,41

TP257TP257

ITP_DBRESET#_137

PM_SYNC#9

TP186TP186

H_STP_PCI#4 H_STP_CPU#4

PM_CLKRUN#24

PCIE_WAKE#20,41 INT_SERIRQ24

THERM_SCI#25

VGATE_PWRGD24,28

R263 0R2J-2-GP

1 2

DY

ECSCI#24 ECSWI#24

ECSMI#24

TP181TP181

TP168TP168 TP236TP236 TP123TP123 TP184TP184 TP262TP262

CLKSATAREQ#4

TP124TP124

SB_SPKR22

MCH_ICH_SYNC#9

TP263TP263

4

LINKALERT# ME_EC_CLK1 ME_EC_DATA1

ICH_RI# SUS_STAT#

ITP_DBRESET#_1

SMB_ALERT# H_STP_PCI#

H_STP_CPU#

PCIE_WAKE#PCIE_WAKE# INT_SERIRQ

VGATE_PWRGD ICH_TP7 ECSCI# ECSWI#

ECSMI# GPIO12 GPIO13 GPIO17 GPIO18 GPIO20 GPIO22 GPIO27 GPIO28

CLK_SEL0 CLK_SEL1 GPIO48

iTPM_EN

ICH_TP3

+3.3V_RUN

R179

10KR2J-3-GP

R185

10KR2J-3-GP

ICH_SMBDATA4,14,15

DY

U25C

G16

SMBCLK

A13

SMBDATA

E17

LINKALERT#/GPIO60/CLGPIO4

C17

SMLINK0

B18

SMLINK1

F19

RI#

R4

SUS_STAT#/LPCPD#

G19

SYS_RESET#

M6

PMSYNC#/GPIO0

A17

SMBALERT#/GPIO11

A14

STP_PCI#

E19

STP_CPU#

L4

CLKRUN#

E20

WAKE#

M5

SERIRQ

AJ23

THRM#

D21

VRMPWRGD

A20

SST

AG19

TACH1/GPIO1

AH21

TACH2/GPIO6

AG21

TACH3/GPIO7

A21

GPIO8

C12

LAN_PHY_PWR_CTRL/GPIO12

C21

ENERGY_DETECT/GPIO13

AE18

TACH0/GPIO17

K1

GPIO18

AF8

GPIO20

AJ22

SCLOCK/GPIO22

A9

GPIO27

D19

GPIO28

L1

SATACLKREQ#/GPIO35

AE19

SLOAD/GPIO38

AG22

SDATAOUT0/GPIO39

AF21

SDATAOUT1/GPIO48

AH24

GPIO49

A8

GPIO57/CLGPIO5

M7

SPKR

AJ24

MCH_SYNC#

B21

TP3

AH20

PWM0

AJ20

PWM1

AJ21

PWM2

ICH9M-GP-NF

12

R423

R423 10KR2J-3-GP

10KR2J-3-GP

DY

CLK_SEL0 CLK_SEL1

12

R427

R427 10KR2J-3-GP

10KR2J-3-GP

DY

SMB_CLK

3 OF 6

SATA0GP/GPIO21 SATA1GP/GPIO19 SATA4GP/GPIO36 SATA5GP/GPIO37

SATA

GPIO

SATA

GPIO

SMB

Clocks

SYS GPIO

Power MGTController Link

GPIO

GPIO10/SUS_PWR_ACK

GPIO14/AC_PRESENT

MISC

CLK14 CLK48

SUSCLK

SLP_S3# SLP_S4# SLP_S5#

S4_STATE#/GPIO26

PWROK

DPRSLPVR/GPIO16

BATLOW# PWRBTN#

LAN_RST#

RSMRST#

CK_PWRGD

CLPWROK

SLP_M#

CL_CLK0 CL_CLK1

CL_DATA0 CL_DATA1

CL_VREF0 CL_VREF1

CL_RST0# CL_RST1#

GPIO24/MEM_LED

GPIO9/WOL_EN

CLK Gen Select

CLK Gen select

CLK_SEL0

Disable X X

Seligo Realtek ICS

RN62

4

SRN2K2J-1-GP

U56

1 2 3 4

2N7002SPT

3

1 1 0

+3.3V_RUN

1 23

SMB_DATA

6 5

SATA0GP

AH23

SATA1GP

AF19

SATA2GP

AE21

SATA3GP

AD20 H1

AF3

ICH_SUSCLK

P1

SB_SLP_S3#

C16 E16

PM_SLP_S5#

G17

GPIO26

C10

PM_PWROK

G20 M2

PM_BATLOW#_R

B13 R3

LAN_RST#1

D20 D22 R5

M_PWROK

R6

PM_SLP_M#

B16 F24

B19 F22

C19

CL_VREF0_ICH

C25

CL_VREF1_ICH

A19 F21

D18

GPIO24

A16

GPIO10

C18

GPIO14

C11 C20

CLL_SEL1

1 0 1

ICH_SMBCLK 4,14,15

CLK_14M_ICH 4 CLK_48M_ICH 4

ICH_SUSCLK 25

PM_SLP_S4# 24,31,41

TP259TP259 TP182TP182

DPRSLPVR 9,28

PM_PWRBTN# 24

RSMRST#_KBC 24 CK_PWRGD 4 M_PWROK 9

TP183TP183

CL_CLK0 9

CL_DATA0 9

CL_RST#0 9

TP180TP180

2

SB_SLP_S3#

RN49

SATA2GP SATA3GP SATA1GP SATA0GP

PM_PWROKLINKALERT# DPRSLPVR LAN_RST#1 RSMRST#_KBC

GPIO10 GPIO13 GPIO14 GPIO17 GPIO48

M_PWROK

+3.3V_ALW +3.3V_RUN

12

R268

DY

3K24R2F-GP

12

C309

R261

DY

U29

1

B

2

A

3

GND

74LVC1G08GW-1-GP

R261

DY

453R2F-1-GP

SCD1U10V2KX-4GP

+3.3V_ALW

5

VCC

DY

R265

1 2

0R0402-PAD

Title

Size Document Number Rev

Custom

Date: Sheet

PM_SLP_S3#

4

Y

ICH9-GPIO/PM/CL(3/4)

RN49

8 7 6

SRN10KJ-6-GP

R440 10KR2J-3-GPR440 10KR2J-3-GP

1 2

R232 100KR2J-1-GP

1 2

DY

R266 0R0402-PADR266 0R0402-PAD

1 2

R447 10KR2J-3-GPR447 10KR2J-3-GP

1 2

R501 10KR2J-3-GP

1 2

DY

R502 10KR2J-3-GP

1 2

DY

R503 10KR2J-3-GP

1 2

DY

R504 10KR2J-3-GP

1 2

DY

R505 10KR2J-3-GP

1 2

DY

R439

1 2

0R0402-PAD

12

R454

3K24R2F-GP

12

R450

C523

453R2F-1-GP

SCD1U10V2KX-4GP

PM_SLP_S3# 24,25,30,31,32,34,41

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Roberts

1

+3.3V_RUN

1 2 3 45

PM_PWROK 9,24,25

of

18 58Thursday, October 02, 2008

A00