Dell Inspiron 1525 Schematic

5

4

3

2

1

CPU DC/DC

Spears Intel UMA Block Diagram

D D

C C

1394

26

SD/SDIO/MMC MS/MS Pro/xD

RJ11 CONN (Option)

B B

Digital Mic Array

26

31

MIC IN

HP1

HP2

Internal Analog MIC

CLK GEN

ICS9LPRS365

DDRII

Slot 0

533/667

DDRII

Slot 1

533/667

1394

25,26

Ricoh R5C833

CardReader

MDC MODEM (Option)

Azalia CODEC

Sigmatel STAC 9228

4

14

15

31

32

DDRII 667 Channel A

DDR II 667 Channel B

PCI

AZALIA

2CH SPEAKER

A A

OP AMP

MAX9789A

33 37

Merom 4M FSB:667MHz/800MHz

Crestline-GM

AGTL+ CPU I/F INTEGRATED GRAHPICS LVDS, CRT I/F

INTEL

ICH8-M

10 USB 2.0/1.1 ports

(10/100/1000Mb)ETHERNET

High Definition Audio

ATA 66/100

ACPI 1.1 LPC I/F

PCI/PCI BRIDGE

SATA

HDD

24 24

PATA

ODD

5,6,7

Host BUS 533/667MHz

DDR I/F

8,9,10,11,12,13

DMI I/F 100MHz

19,20,21,22

Capacity Button

PCIE x 16

Intel CPU

Project code : 91.4W001.001 PCB P/N : 07211 Revision : -1

RGB CRT

LVDS

SVIDEO

SDVO

AZALIA

PCIE

USB 2.0

LPC Bus

KBC

Winbond WPC8763L

Touch Pad

Int. KB

37

37 36

PCIE x 1

34

S/W CIR

CRT

LCD

S-Vedio (Upsell)

SiI 1392 (Upsell)

PCIE x 1 & USB 2.0 x 1

10/100 NIC

Marvell 88E8040

PCIE x 2 & USB 2.0 x 1

PCIE x 1 & USB 2.0 x 1

SPI

Thermal & Fan

G792

2007/08/29

17

18

16

23

27

USB 2.0 x 1

Flash ROM

1MB

HDMI (Upsell)

RJ45 CONN

Mini-Card X2

802.11a/b/g BT/UWB/Robson

Mini-Card X1

WWAN(Upsell)

CAMERA (Option)

Lift Side: USB x 2 Right Side:

USB x 1 USB x 1(Upsell)

35

Power SW

TI TPS2231

New Card

ISL6262A

INPUTS

DCBATOUT

OUTPUTS

VCC_CORE

SYSTEM DC/DC

TPS5117

INPUTS

DCBATOUT

OUTPUTS

1D05V_S0 1D8V_S3

SYSTEM DC/DC

TPS51120

INPUTS

16

28

SYSTEM DC/DC

OUTPUTS

5V_AUX_S5 5V_S5DCBATOUT 3D3V_S5

TPS51100

INPUTS

28

29 30

30

1D8V_S3

SYSTEM DC/DC

INPUTS

1D8V

OUTPUTS

0D9V_S3

LDO

OUTPUTS

2D5V3D3V 1D5V_S0

SYSTEM DC/DC

24

INPUTS

DCBATOUT

24

LDO

OUTPUTS

3D3V_AUX_S5 1D5V_S0

MAXIM CHARGER

MAX8731A

INPUTS

AD+ BAT+

OUTPUTS

DCBATOUT

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

A3 Date: Sheet

Date: Sheet

5

4

3

2

Date: Sheet

DS2 System Block Diagram

Spears-Intel -1

147Wednesday, September 12, 2007

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TI TPS51120

CPU_CORE ISL6262A

VID0

D D

VID1

VID2

VID3

VID4

VID5

VID Setting

VID0(I / 3.3V)

VID1(I / 3.3V)

VID2(I / 3.3V)

VID3(I / 3.3V)

VID4(I / 3.3V)

VID5(I / 3.3V)

Output Signal

VROK()

Output Power

VCC_CORE_PWR(O)

VRPWRGD

VCC_CORE_S0(Imax=35A)

3V/5V_EN

DCBATOUT

Input Signal

CPUCORE_ON

VCC_SENSE

C C

VSS_SENSE

EN (I / 3.3V)

Voltage Sense

VSEN(I / Vcore)

RGND(I / Vcore)

DCBATOUT

5V_AUX_S5

Input Power

DCBATOUT

5V_S0

3D3V_S0

VCC(I)

AD_OFF

AD_JK

B B

5V_AUX_S5

TI TPS51100

Input Signal

51120_EN2

51120_EN1

VIN

Input Power

VIN

V5FILT(I / 5V)

Input Signal

(I)

Input Power

VCC(I)

0.9V/DDR_VREF_S3

PM_SLP_S4# PM_SLP_S3#

Input Signal

S5 S3

PM_SLP_S4#

EN_PSV(I / 5V)

Output Power

Input Power

DCBATOUT

5V_S5

A A

VCC(I)

5

VCC(O)

0D9V_DDR_VTT

DDR_VREF_S3

4

VCC

DCBATOUT

PM_SLP_S3#

5V_S5 Output Power

DCBATOUT

VIN

EN_PSV(I / 5V)

VCC

VIN

TPS51117_1D8V_S3

Input Signal

Input Power Output Power5V_S5

TPS51117_1D05V

Input Signal

Input Power

3D3V/5V

FOR

3.3V FOR

5.0V

Adapter

Output Signal

3

Output Signal

PGOUT1(OD / 5V)

PGOUT2(OD / 3D3V)

Output Power

(O)

Output Power

VCC(O)

Output Signal

PGOUT(OD / 5V)

1D8V_PWR

Output Signal

PGOUT(OD / 5V)

1D05V_PWR

5V(O)

3D3V(O)

AD_IN

AD+

CPUCORE_ON

1D8V_S3

CPUCORE_ON

1D05V_S0 (15A)

CPUCORE_ON(Pull High 3D3V)

PM_SLP_S3#

5V_AUX_S5

3D3V_S0

3D3V_AUX_S5

5V_S5 (6A)

3D3V_S5 (5A)

1D8V_S3

PM_SLP_S3#

Charger_MAX8731A

CHARGE_OFF

BAT+SENSE

BT_SCL

BT_SDA

AC_IN

AD+

2

CLS (I / 3.3V)

BATT (I / 3.3V)

SCL (IO / 5V)

SDA (IO / 5V)

PB0/MOSI/AIN0

Input Power

DCIN (I)

Title

Size Document Number Rev

Size Document Number Rev A3

A3

A3 Date: Sheet

Date: Sheet

1D5V_S0

5V_S5

1D8V_S3

VCNTL

VIN

EN

APL5915

2D5V_S0

INPUT OUT

G9131

1D25V_S0

5V_S5

VCNTL

VIN

G971

Output SignalInput Signal

LDO (O / 5.4V)

XTAL2/PB4 (O/5V)

XTAL1/PB3 (O/5V)

Output Power

Power Block Diagram

DS2-Intel -1

CPUCORE_ON

POK

1D5V_S0

VOUT(O)

2D5V_S0

CPUCORE_ON

POKEN

1D5V_S0

VOUT(O)

MAX8731_LDO

VCC (O)

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

DCBATOUT

BT+

247Wednesday, September 12, 2007

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INTEL ICH8-M STRAP PIN

Signal Usage/When Sampled

HDA_SDOUT XOR Chain Entrance/

4 4

HDA_SYNC

GNT2#

GPIO20

GNT3#

GNT0# SPI_CS1#

INTVRMEN

3 3

LAN100_SLP

SATALED#

SPKR

TP3

GPIO33/ HDA_DOCK_EN#

PCIE Port Config 1 bit1, Rising Edge of PWROK

PCIE Port Config 1 bit0, Rising Edge of PWROK.

PCIE Port Config 2 bit0, Rising Edge of PWROK.

Reserved

Top-Block Swap Override. Rising Edge of PWROK.

Boot BIOS Destination Selection. Rising Edge of PWROK.

Integrated VccSus1_05 VccSus1_5 and VccCL1_5 VRM Enable/Disable.Always sampled.

Integrated VccLAN1_05 VccCL1_05 VRM enable /Disable. Always sampled.

PCIE LAN REVERSAL.Rising Edge of PWROK.

No Reboot. Rising Edge of PWROK.

XOR Chain Entrance. Rising Edge of PWROK.

Flash Descriptor Security Override Strap Rising Edge of PWROK.

Allows entrance to XOR Chain testing when TP3 pulled low at rising edge of PWROK.When TP3 not pulled low at rising edge of PWROK,sets bit1 of RPC.PC(Config Registers:offset 224h) Sets bit0 of RPC.PC(Config Registers:Offset 224h)

Sets bit2 of RPC.PC(Config Registers:Offset 224h)

Weak Internal PULL-DOWN.NOTE:This signal should not be pull HIGH.

Sampled low:Top-Block Swap mode(inverts A16 for all cycles targeting FWH BIOS space). Note: Software will not be able to clear the Top-Swap bit until the system is rebooted without GNT3# being pulled down.

Controllable via Boot BIOS Destination bit (Config Registers:Offset 3410h:bit 11:10). GNT0# is MSB, 01-SPI, 10-PCI, 11-LPC.

Enables integrated VccSus1_05,VccSus1_5 and VccCL1_5 VRM when sampled high

Enables integrated VccLAN1_05,VccCL1_05 VRM when sampled high

This signal has weak internal pull-up. set bit27 of MPC.LR(Device28:Function0:Offset D8)

If sampled high, the system is strapped to the "No Reboot" mode(ICH8M will disable the TCO Timer system reboot feature). The status is readable via the NO REBOOT bit.(Offset:3410h:bit5)

This signal should not be pull low unless using XOR Chain testing.

Internal Pull-Up.If sampled low,the Flash Descriptor Security will be overidden.if high,the Security measures defined in the Flash Descriptor will be in effect. This should only be used in manufacturing environments

Comment

2 2

INTEL CRESTLINE STRAP PIN

CFG Strap HIGH 1LOW 0

CFG 5 CFG 8

Low Power PCI Express Normal Low Power mode

CFG 9

PCI Express Graphics Lane Reversal

CFG 16

FSB Dynamic ODT Disabled Enabled

CFG 19

DMI Lane Reserved Normal Operation Reserved Lane

CFG 20

Concurrent SDVO/PCIE

SDVO_CTRL_DATA

SDVO Present

1 1

CFG 12 CFG 13

LL(00) LH(01) HL(10) HH(11)

DMI X 2 DMI X 4

★

Lane Reversal Normal Mode(Lanes

Only PCIE or SDVO is operation

NO SDVO Card Present

★

number in order)

★

PCIE and SDVO are operation simultaneous

SDVO Card Present

XOR/ALL-Z

Reserved XOR Mode Enabled All Z Mode Enabled Normal Operation

★

XOR Chain Entrance Strap

ICH_RSVD

A16 swap override strap

PCI_GNT#3

BOOT BIOS Strap

PCI_GNT#0 BOOT BIOS Location

integrated VccSus1_05,VccSus1_5,VccCL1_5

SM_INTVRMEN

integrated VccLan1_05VccCL1_05

LAN100_SLP

AZ_DOUT_ICH

tp3

0 0 10

10 1

0 1

11

low = A16 swap override enable high = default

SPI_CS#1

1

Description

Normal Operation(default) Set PCIE port cofig bit1

SPI10 PCI LPC(Default)

High=Enable Low=Disable

RSVD Enter XOR Chain

DEFAULE HIGH

No Reboot Strap

LOW = DefauleSPKR

High=No Reboot

INTEL ICH8-M INTEGRATED

8.2K PULL HIGH

PULL-UPS and PULL-DOWNS

SIGNAL Resistor Type/Value

HDA_BIT_CLK HDA_RST# HDA_SDIN[3:0] HDA_SDOUT HDA_SYNC GNT[3:0] GPIO[20] LDA[3:0]#/FHW[3:0]# LAN_RXD[2:0] LDRQ[0] LDRQ[1]/GPIO23 PME# PWRBTN# SATALED# SPI_CS1# SPI_CLK SPI_MOSI SPI_MISO TACH_[3:0] SPKR TP[3] USB[9:0][P,N] CL_RST#

PULL-DOWN 20K NONE PULL-DOWN 20K PULL-DOWN 20K PULL-DOWN 20K PULL-UP 20K PULL-DOWN 20K PULL-UP 20K PULL-UP 20K PULL-UP 20K PULL-UP 20K PULL-UP 20K PULL-UP 20K PULL-UP 20K PULL-UP 20K PULL-UP 20K PULL-UP 20K PULL-UP 20K PULL-UP 20K PULL-DOWN 20K PULL-UP 20K PULL-DOWN 15K TBD

Title

Size Document Number Rev

Size Document Number Rev A3

A3

A3 Date: Sheet

Date: Sheet

Date: Sheet of

+RTCVCC20,22

1D05V_S05,6,7,8,10,11,12,20,22,34,43,47

1D25V_S08,11,22,45

1D2V_LAN_S527

1D5V_NEW_S028

1D5V_S06,11,20,21,22,28,29,30,45

1D8V_S38,11,12,14,15,44,45,46,47

2D5V_LAN_S527,28

3D3V_AUX_S520,31,34,35,36,38,39,40,47 3D3V_LAN_S527,28

3D3V_S04,8,10,11,14,15,16,17,18,19,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,40,41,43,45,46,47

3D3V_S519,21,22,27,28,31,35,38,40,46,47

5V_AUX_S518,39,40,47

5V_S016,17,18,22,24,33,35,36,37,41,45,46,47

5V_S522,24,29,30,31,35,38,40,43,44,45,46,47

AD+38,39,47

DCBATOUT18,39,40,41,42,43,44,46,47 DDR_VREF_S014,15,45,47 DDR_VREF_S38,14,15,45

+LCDVDD18 VCC_CORE_S06,7,42

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Table of Content

DS2-Intel -1

+RTCVCC 1D05V_S0 1D25V_S0 1D2V_LAN_S5 1D5V_NEW_S0 1D5V_S0 1D8V_S3 2D5V_LAN_S5

3D3V_AUX_S5 3D3V_LAN_S5 3D3V_S0 3D3V_S5 5V_AUX_S5

5V_S0 5V_S5 AD+ DCBATOUT DDR_VREF_S0 DDR_VREF_S3

+LCDVDD VCC_CORE_S0

347Wednesday, September 12, 2007

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A

3D3V_S0 3D3V_S0_CK505

R127 0R0603-PADR127 0R0603-PAD

12

C222

SC1U10V3KX-3GP

5

12

C219

SC10U6D3V5KX-1GP

12

C527

C549

SCD1U16V2ZY-2GP

12

C523

SCD1U16V2ZY-2GP

C529

SCD1U16V2ZY-2GP

D D

4

12

C537

SCD1U16V2ZY-2GP

X3

1 2

12

C214

C214 SC15P50V2JN-2-GP

SC15P50V2JN-2-GP

CLK_XTAL_OUTCLK_XTAL_IN

X-14D31818M-37GP

3

12

C211

C211 SC15P50V2JN-2-GP

SC15P50V2JN-2-GP

2

3D3V_S0_CK505_IO3D3V_S0_CK505

U24

4

9

46

62

16

23

33

43

52

56

19

27

U24

1

SA:0430

VDDREF

GND48

15

18

VDD48

GNDPCI

1

VDDPCI

VDDSRC

GNDREF

VDDCPU

VDDPLL3

GND

GNDSRC

22

30

36

MCH_CLKSEL0 8 MCH_CLKSEL1 8 MCH_CLKSEL2 8

VDD96_IO

VDDSRC_IO

VDDPLL3_IO

27MHZ_NONSS/SRCT1/SE1

GND

GNDSRC

GNDCPU

26

49

59

FSC FSB FSA

CPUT0

VDDCPU_IO

27MHZ_SS/SRCC1/SE2

GND

65

ICS9LPRS365BKLFT-GP

CPUC0

CPUT1_F CPUC1_F

CPUT2_ITP/SRCT8

CPUC2_ITP/SRCC8

SRCT7/CR#_F

SRCC7/CR#_E

SRCT6 SRCC6

SRCT10 SRCC10

SRCT11/CR#_H

SRCC11/CR#_G

SRCT9 SRCC9

SRCT4 SRCC4

SRCT3/CR#_C

SRCC3/CR#_D

SRCT2/SATAT

SRCC2/SATAC

SRCT0/DOTT_96

SRCC0/DOTC_96

27_SEL

12

R378

R378 10KR2J-3-GP

10KR2J-3-GP

27_SEL PIN 20 PIN 21 PIN 24 PIN 25

0 DOT96T DOT96C SRCT1/LCDT_100 SRCT1/LCDT_100 1 SRCT0 SRCC0 27M_NSS 27M_SS

3D3V_S0

12

R128 0R0603-PADR128 0R0603-PAD

12

C231

SC1U10V3KX-3GP

12

DY

C227

SC10U6D3V5KX-1GP

12

C524

SCD1U16V2ZY-2GP

12

C533

SCD1U16V2ZY-2GP

C525

SCD1U16V2ZY-2GP

C C

CLKSATAREQ#21

CLKREQ#_B8

PCLK_PCM25 PCLK_KBC34 CLK_PCI_ICH19

CLK_14M_ICH21

3D3V_S0_CK505

12

R374

R374 10KR2J-3-GP

10KR2J-3-GP

PCI2_TME

ITP_EN

12

R373

R373 10KR2J-3-GP

10KR2J-3-GP

DY

ITP_EN Output

0 SRC8 1 CPU_ITP

B B

12

R380

R380 10KR2J-3-GP

10KR2J-3-GP

3D3V_S0_CK505_IO

C566 SC4D7P50V2CN-1GPC566 SC4D7P50V2CN-1GP

12

C548

C550

SCD1U16V2ZY-2GP

12

C540

SC4D7P50V2CN-1GP

CLK_48M_ICH21

12

C552

C545

SC4D7P50V2CN-1GP

1 2

H_STP_PCI#21 H_STP_CPU#21

ICH_SMBCLK14,15,21

ICH_SMBDATA14,15,21

CK_PWRGD21

12

C526

SC4D7P50V2CN-1GP

Main source : 71.09365.A03 ICS9LPRS365CKLFT 2nd source:71.00875.A03 RTM875N-606-LF

PCI2_TME Output

0

1

Overclocking of CPU and SRC allowed

Overclocking of CPU and SRC not allowed

CPU_BSEL26 CPU_BSEL16 CPU_BSEL06

CLK_XTAL_IN CLK_XTAL_OUT

1 2

R383 33R2J-2-GPR383 33R2J-2-GP

R370 33R2J-2-GPR370 33R2J-2-GP

1 2

R379 33R2J-2-GPR379 33R2J-2-GP

1 2

R382 33R2J-2-GPR382 33R2J-2-GP

1 2

R355

1 2

33R2J-2-GP

FSA

PCI2_TME PCLK_PCM_R 27_SEL ITP_EN

FSB FSC

Please place R10 near U1 pin5

3

X1

2

X2

17

USB_48MHZ/FSLA

45

PCI_STOP#

44

CPU_STOP#

7

SCLK

6

SDATA

63

CK_PWRGD/PD#

8

PCI0/CR#_A

10

PCI1/CR#_B

11

PCI2/TME

12

PCI3

13

PCI4/27_SELECT

14

PCI_F5/ITP_EN

64

FSLB/TEST_MODE

5

REF0/FSLC/TEST_SEL

55

NC#55

FS_C FS_B FS_A CPU

1 0 1 100M 0 0 1 133M 0 1 0 200M 0 1 1 166M

1 2

R360 2K2R2J-2-GPR360 2K2R2J-2-GP

1 2

R353 0R0402-PADR353 0R0402-PAD

1 2

R386 2K2R2J-2-GPR386 2K2R2J-2-GP R385 0R0402-PADR385 0R0402-PAD

1 2

R352 0R0402-PADR352 0R0402-PAD

1 2

R359 0R0402-PADR359 0R0402-PAD

1 2

Design Note:

1. All of Input pin didn't have internal pull up resistor.

2. Clock Request (CR) function are enable by registers.

3. CY28548 integrated serial resistor of differential clock, so put 0 ohm serial resistor in the schematic.

CLK_CPU_BCLK1

61

CLK_CPU_BCLK1#

60

CLK_MCH_BCLK1

58

CLK_MCH_BCLK1#

57

CLK_PCIE_MINI3_1

54

CLK_PCIE_MINI3_1#

53

CLK_PCIE_LAN1

51

CLK_PCIE_LAN1#

50

CLK_PCIE_MINI1_1

48

CLK_PCIE_MINI1_1#

47

CLK_PCIE_NEW1

41

CLK_PCIE_NEW1#

42 40

39

CLK_PCIE_MINI2_1

37

CLK_PCIE_MINI2_1#

38

CLK_MCH_3GPLL1

34

CLK_MCH_3GPLL1#

35

CLK_PCIE_ICH1

31

CLK_PCIE_ICH1#

32

CLK_PCIE_SATA1CLK_PCIE_SATA1

28

CLK_PCIE_SATA1#CLK_PCIE_SATA1#

29

MCH_SSCDREFCLK1

24

MCH_SSCDREFCLK1#

25

CLK_MCH_DREFCLK1

20

CLK_MCH_DREFCLK1#

21

RN25 SRN0J-6-GPRN25 SRN0J-6-GP

RN26 SRN0J-6-GPRN26 SRN0J-6-GP

RN27 SRN22-3-GPRN27 SRN22-3-GP

RN28 SRN0J-6-GPRN28 SRN0J-6-GP

RN29 SRN22-3-GPRN29 SRN22-3-GP

RN30 SRN0J-6-GPRN30 SRN0J-6-GP

RN31

RN32 SRN0J-6-GPRN32 SRN0J-6-GP

RN36 SRN0J-6-GPRN36 SRN0J-6-GP

RN35 SRN0J-6-GPRN35 SRN0J-6-GP

RN33 SRN0J-6-GPRN33 SRN0J-6-GP

NEWCARD_CLKREQ#

12

EC119

EC119 SC22P50V2JN-4GP

SC22P50V2JN-4GP

1 2 3

2 3 1

RN34 SRN0J-6-GPRN34 SRN0J-6-GP

2 3 1

4

1 2

R371 10KR2J-3-GPR371 10KR2J-3-GP R375

R375

1 2

10KR2J-3-GP

DY

SRN22-3-GP

EC165

DY

SC47P50V2JN-3GP

DY

CLK_MCH_DREFCLK CLK_MCH_DREFCLK#

12

EC166

SC47P50V2JN-3GP

4

SC:08/11 Add EC165,EC166 on

CLK_MCH_DREFCLK -/+ pair .

12

DY

CLK_PCIE_LAN 27 CLK_PCIE_LAN# 27

NEWCARD_CLKREQ# 28

CLK_PCIE_MINI2 30 CLK_PCIE_MINI2# 30

CLK_MCH_3GPLL 8 CLK_MCH_3GPLL# 8

CLK_PCIE_ICH 21 CLK_PCIE_ICH# 21

MCH_SSCDREFCLK 8 MCH_SSCDREFCLK# 8

CLK_MCH_DREFCLK 8 CLK_MCH_DREFCLK# 8

27_SEL strap 0:For 965GM, 1:For 965PM

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Clock generator ICS9LPRS365

Size Document Number Rev

Size Document Number Rev A3

A3

A3 Date: Sheet

Date: Sheet

DS2-Intel -1

447Wednesday, September 12, 2007

CLK_CPU_BCLK 5 CLK_CPU_BCLK# 5

CLK_MCH_BCLK 8 CLK_MCH_BCLK# 8

CLK_PCIE_MINI3 30 CLK_PCIE_MINI3# 30

CLK_PCIE_MINI1 29 CLK_PCIE_MINI1# 29

CLK_PCIE_NEW 28 CLK_PCIE_NEW# 28

3D3V_S0

CLK_PCIE_SATA 20 CLK_PCIE_SATA# 20

965GM 965PM

of

A

5

A

4

3

2

1

H_A#[3..35]8

H_A#3 H_A#4

D D

H_ADSTB#08 H_REQ#08

H_REQ#18 H_REQ#28 H_REQ#38 H_REQ#48

C C

H_ADSTB#18

H_A20M#20 H_FERR#20 H_IGNNE#20

H_STPCLK#20 H_INTR20 H_NMI20 H_SMI#20

TP14TPAD28 TP14TPAD28 TP16TPAD28 TP16TPAD28 TP6TPAD28 TP6TPAD28 TP12TPAD28 TP12TPAD28 TP4TPAD28 TP4TPAD28 TP10TPAD28 TP10TPAD28 TP5TPAD28 TP5TPAD28 TP20TPAD28 TP20TPAD28

B B

TP11TPAD28 TP11TPAD28 TP18TPAD28 TP18TPAD28

H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16

H_ADSTB#0

H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4

H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35

H_ADSTB#1 H_A20M#

H_FERR# H_IGNNE#

CPU_RSVD01 CPU_RSVD02 CPU_RSVD03 CPU_RSVD04 CPU_RSVD05 CPU_RSVD06 CPU_RSVD07 CPU_RSVD08 CPU_RSVD09 CPU_RSVD10

U45A

J4

A3#

L5

A4#

L4

A5#

K5

A6#

M3

A7#

N2

A8#

J1

A9#

N3

A10#

P5

A11#

P2

A12#

L2

A13#

P4

A14#

P1

A15#

R1

A16#

M1

ADSTB0#

K3

REQ0#

H2

REQ1#

K2

REQ2#

J3

REQ3#

L1

REQ4#

Y2

A17#

U5

A18#

R3

A19#

W6

A20#

U4

A21#

Y5

A22#

U1

A23#

R4

A24#

T5

A25#

T3

A26#

W2

A27#

W5

A28#

Y4

A29#

U2

A30#

V4

A31#

W3

A32#

AA4

A33#

AB2

A34#

AA3

A35#

V1

ADSTB1#

A6

A20M#

A5

FERR#

C4

IGNNE#

D5

STPCLK#

C6

LINT0

B4

LINT1

A3

SMI#

M4

RSVD#M4

N5

RSVD#N5

T2

RSVD#T2

V3

RSVD#V3

B2

RSVD#B2

C3

RSVD#C3

D2

RSVD#D2

D22

RSVD#D22

D3

RSVD#D3

F6

RSVD#F6

B1

KEY_NC

SKT-CPU478P-GP

1 OF 4

ADDR GROUP 0

ADDR GROUP 1

XDP/ITP SIGNALS CONTROL

XDP/ITP SIGNALS CONTROL THERMAL

THERMAL

PROCHOT#

ICH

THERMTRIP#

HCLK

RESERVED

ADS# BNR# BPRI#

DEFER#

DRDY# DBSY#

BR0#

IERR#

INIT#

LOCK#

RESET#

RS0# RS1# RS2#

TRDY#

HIT#

HITM#

BPM0# BPM1# BPM2# BPM3# PRDY# PREQ#

TCK

TDO TMS

TRST#

DBR#

THRMDA THRMDC

BCLK0 BCLK1

TDI

H_ADS#

H1

H_BNR#

E2

H_BPRI#

G5

H_DEFER#

H5

H_DRDY#

F21

H_DBSY#

E1

H_BR0#

F1

H_IERR#

D20

H_INIT#

B3

H_LOCK#

H4

H_RESET#

C1

H_RS#0

F3

H_RS#1

F4

H_RS#2

G3

H_TRDY#

G2

H_HIT#

G6

H_HITM#

E4

XDP_BPM#0

AD4

XDP_BPM#1

AD3

XDP_BPM#2

AD1

XDP_BPM#3

AC4

XDP_BPM#4

AC2

XDP_BPM#5

AC1

XDP_TCK

AC5

XDP_TDI

AA6

XDP_TDO

AB3

XDP_TMS

AB5

XDP_TRST#

AB6

XDP_DBRESET#

C20

CPU_PROCHOT

D21

H_THERMDA

A24

H_THERMDC

B25

H_THERMTRIP#

C7

CLK_CPU_BCLK

A22

CLK_CPU_BCLK#

A21

layout note:Zo =55 ohm , 0.5" MAX for GTLREF

H_ADS# 8 H_BNR# 8

H_BPRI# 8 H_DEFER# 8

H_DRDY# 8 H_DBSY# 8

H_BR0# 8

H_INIT# 20

H_LOCK# 8

H_RESET# 8

H_RS#0 8 H_RS#1 8 H_RS#2 8

H_TRDY# 8

H_HIT# 8 H_HITM# 8

TP15TP15 TP13TP13 TP3TP3 TP9TP9 TP7TP7 TP2TP2

TP8TP8

TP19TP19

1 2

R236 56R2J-4-GPR236 56R2J-4-GP

H_THERMTRIP# 8,20,34,46

CLK_CPU_BCLK 4 CLK_CPU_BCLK# 4

1D05V_S0

12

R235

R235 56R2J-4-GP

56R2J-4-GP

1D05V_S0

H_THERMDA 36 H_THERMDC 36

H_THERMDA, H_THERMDC routing together, Trace width / Spacing = 10 / 10 mil

XDP_TDI

R7 150R2F-1-GPR7 150R2F-1-GP

XDP_TMS

R5 39R2F-GPR5 39R2F-GP

1D05V_S0

1 2 1 2

CPU_PROCHOT

DY

12

R237 0R2J-2-GP

XDP_TRST# XDP_TCK

CPU_PROCHOT# 41

1 2

R6 649R2F-GPR6 649R2F-GP

1 2

R4 27D4R2F-L1-GPR4 27D4R2F-L1-GP

Title

Size Document Number Rev

Size Document Number Rev A3

A3

A3 Date: Sheet

Date: Sheet

Meron(1/3)-AGTL+/XDP

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

DS2-Intel

5

A

-1

47Wednesday, September 12, 2007

of

5

A

4

3

2

1

H_D#[0..63]8

H_D#0 H_D#1 H_D#2 H_D#3 H_D#4

TP21TPAD28 TP21TPAD28 TP23TPAD28 TP23TPAD28 TP22TPAD28 TP22TPAD28

TP85TPAD28 TP85TPAD28 TP87TPAD28 TP87TPAD28

H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14

H_D#15 H_DSTBN#0 H_DSTBP#0 H_DINV#0

H_D#16

H_D#17

H_D#18

H_D#19

H_D#20

H_D#21

H_D#22

H_D#23

H_D#24

H_D#25

H_D#26

H_D#27

H_D#28

H_D#29

H_D#30

H_D#31 H_DSTBN#1 H_DSTBP#1 H_DINV#1

TEST1 TEST2 TEST3 TEST4 TEST5 TEST6

CPU_BSEL0 CPU_BSEL1 CPU_BSEL2

D D

H_DSTBN#08 H_DSTBP#08

H_DINV#08

C C

H_DSTBN#18 H_DSTBP#18 H_DINV#18

V_CPU_GTLREF

SCD1U16V2KX-3GP

PLACE C25 close to the TEST4 PIN, make sure TEST3,TEST4,TEST5 trace routing is reference to GND and away other noisy signals

1 2

DY

C395

CPU_BSEL04 CPU_BSEL14 CPU_BSEL24

B B

CPU_BSEL CPU_BSEL2 CPU_BSEL1 CPU_BSEL0

166

200

Place C635 near R238 and R239

0

00

12

C635

SCD1U16V2KX-3GP

1

1D05V_S0

R239

R239 1KR2F-3-GP

1KR2F-3-GP

1 2

V_CPU_GTLREF

12

R238

2KR2F-3-GP

U45B

E22 F24 E26 G22 F23 G25 E25 E23 K24 G24

J24

J23 H22 F26 K22 H23

J26 H26 H25

N22 K25 P26 R23

L23 M24

L22 M23 P25 P23 P22 T24 R24

L25 T25 N25

L26 M26 N24

AD26

C23 D25 C24

AF26

AF1 A26

B22 B23 C21

SKT-CPU478P-GP

D0# D1# D2# D3# D4# D5# D6# D7# D8# D9# D10# D11# D12# D13# D14# D15# DSTBN0# DSTBP0# DINV0#

D16# D17# D18# D19# D20# D21# D22# D23# D24# D25# D26# D27# D28# D29# D30# D31# DSTBN1# DSTBP1# DINV1#

GTLREF TEST1 TEST2 TEST3 TEST4 TEST5 TEST6

BSEL0 BSEL1 BSEL2

11

2 OF 4

DATA GRP0 DATA GRP1

MISC

Close to CPU pin AD26 Z0=55 ohm with in 500mils .

D32# D33# D34# D35# D36# D37# D38# D39# D40# D41# D42#

DATA GRP2DATA GRP3

D43# D44# D45# D46#

D47# DSTBN2# DSTBP2#

DINV2#

D48#

D49#

D50#

D51#

D52#

D53#

D54#

D55#

D56#

D57#

D58#

D59#

D60#

D61#

D62#

D63# DSTBN3# DSTBP3#

DINV3# COMP0

COMP1 COMP2 COMP3

DPRSTP#

DPSLP#

DPWR#

PWRGOOD

SLP#

PSI#

Y22 AB24 V24 V26 V23 T22 U25 U23 Y25 W22 Y23 W24 W25 AA23 AA24 AB25 Y26 AA26 U22

AE24 AD24 AA21 AB22 AB21 AC26 AD20 AE22 AF23 AC25 AE21 AD21 AC22 AD23 AF22 AC23 AE25 AF24 AC20

R26 U26 AA1 Y1

E5 B5 D24 D6 D7 AE6

H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46

H_D#47 H_DSTBN#2 H_DSTBP#2 H_DINV#2

H_D#48

H_D#49

H_D#50

H_D#51

H_D#52

H_D#53

H_D#54

H_D#55

H_D#56

H_D#57

H_D#58

H_D#59

H_D#60

H_D#61

H_D#62

H_D#63 H_DSTBN#3 H_DSTBP#3 H_DINV#3

COMP0 COMP1

R233 27D4R2F-L1-GPR233 27D4R2F-L1-GP

COMP2

R234 54D9R2F-L1-GPR234 54D9R2F-L1-GP

COMP3

R3 27D4R2F-L1-GPR3 27D4R2F-L1-GP

R2 54D9R2F-L1-GPR2 54D9R2F-L1-GP

H_DPRSTP# H_DPSLP# H_DPWR#

H_CPUSLP# PSI#

H_DSTBN#2 8 H_DSTBP#2 8 H_DINV#2 8

H_DSTBN#3 8 H_DSTBP#3 8 H_DINV#3 8

1 2 1 2 1 2 1 2

H_DPRSTP# 8,20,41 H_DPSLP# 20

H_DPWR# 8

H_CPUSLP# 8

PSI# 41

Resistor Placed within 0.5" of CPU pin. Trace should be at least 25 mils away from any other toggling signal . COMP[0,2] trace width is 18 mils. COMP[1,3] trace width is 4 mils .

H_PWRGOOD 20,46

VCC_CORE_S0 VCC_CORE_S0

3 OF 4

U45C

A7

A9 A10 A12 A13 A15 A17 A18 A20

B7

B9 B10 B12 B14 B15 B17 B18 B20

C9 C10 C12 C13 C15 C17 C18

D9 D10 D12 D14 D15 D17 D18

E7

E9 E10 E12 E13 E15 E17 E18 E20

F7

F9 F10 F12 F14 F15 F17 F18 F20 AA7 AA9

AA10 AA12 AA13 AA15 AA17 AA18 AA20

AB9

AC10 AB10 AB12 AB14 AB15 AB17 AB18

SKT-CPU478P-GP

VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC

VCCSENSE

VSSSENSE

VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC

VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP

VCCA VCCA

VID0 VID1 VID2 VID3 VID4 VID5 VID6

AB20 AB7 AC7 AC9 AC12 AC13 AC15 AC17 AC18 AD7 AD9 AD10 AD12 AD14 AD15 AD17 AD18 AE9 AE10 AE12 AE13 AE15 AE17 AE18 AE20 AF9 AF10 AF12 AF14 AF15 AF17 AF18 AF20

G21 V6 J6 K6 M6 J21 K21 M21 N21 N6 R21 R6 T21 T6 V21 W21

B26 C26

AD6 AF5 AE5 AF4 AE3 AF3 AE2

AF7

AE7

CPU_VID0 CPU_VID1 CPU_VID2 CPU_VID3 CPU_VID4 CPU_VID5 CPU_VID6

VCC_SENSE

VSS_SENSE

1D05V_S0

12

C20

C20 SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

1D5V_S0

12

C394

CPU_VID[0..6] 41

VCC_SENSE 41

VSS_SENSE 41

VCC_SENSE

R201 100R2F-L1-GP-UR201 100R2F-L1-GP-U

VSS_SENSE

R199 100R2F-L1-GP-UR199 100R2F-L1-GP-U

Close to CPU pin within 500mils

Title

Size Document Number Rev

Size Document Number Rev A3

A3

A3 Date: Sheet

Date: Sheet

Date: Sheet of

Meron(2/3)-AGTL+/PWR

C394

SCD01U16V2KX-3GP

Length match within 25 mils . The trace width/space/other is 20/7/25 .

1 2

DS2-Intel

layout note: place C3 near PIN B26

12

C397

C397 SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

VCC_CORE_S0

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

of

6

-1

47Wednesday, September 12, 2007

A

5

A

4

3

VCC_CORE_S0

2

1

12

C382

C377

SC10U6D3V5KX-1GP

12

C33

SC10U6D3V5KX-1GP

C634

12

SC10U6D3V5KX-1GP

C39

C39 SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

1 2

4 OF 4

U45D

A4

VSS

D D

C C

B B

A8

VSS

A11

VSS

A14

VSS

A16

VSS

A19

VSS

A23

VSS

AF2

VSS

B6

VSS

B8

VSS

B11

VSS

B13

VSS

B16

VSS

B19

VSS

B21

VSS

B24

VSS

C5

VSS

C8

VSS

C11

VSS

C14

VSS

C16

VSS

C19

VSS

C2

VSS

C22

VSS

C25

VSS

D1

VSS

D4

VSS

D8

VSS

D11

VSS

D13

VSS

D16

VSS

D19

VSS

D23

VSS

D26

VSS

E3

VSS

E6

VSS

E8

VSS

E11

VSS

E14

VSS

E16

VSS

E19

VSS

E21

VSS

E24

VSS

F5

VSS

F8

VSS

F11

VSS

F13

VSS

F16

VSS

F19

VSS

F2

VSS

F22

VSS

F25

VSS

G4

VSS

G1

VSS

G23

VSS

G26

VSS

H3

VSS

H6

VSS

H21

VSS

H24

VSS

J2

VSS

J5

VSS

J22

VSS

J25

VSS

K1

VSS

K4

VSS

K23

VSS

K26

VSS

L3

VSS

L6

VSS

L21

VSS

L24

VSS

M2

VSS

M5

VSS

M22

VSS

M25

VSS

N1

VSS

N4

VSS

N23

VSS

N26

VSS

P3

VSS

SKT-CPU478P-GP

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

P6 P21 P24 R2 R5 R22 R25 T1 T4 T23 T26 U3 U6 U21 U24 V2 V5 V22 V25 W1 W4 W23 W26 Y3 Y6 Y21 Y24 AA2 AA5 AA8 AA11 AA14 AA16 AA19 AA22 AA25 AB1 AB4 AB8 AB11 AB13 AB16 AB19 AB23 AB26 AC3 AC6 AC8 AC11 AC14 AC16 AC19 AC21 AC24 AD2 AD5 AD8 AD11 AD13 AD16 AD19 AD22 AD25 AE1 AE4 AE8 AE11 AE14 AE16 AE19 AE23 AE26 A2 AF6 AF8 AF11 AF13 AF16 AF19 AF21 A25 AF25

Place these capacitors on L1 (North side ,Secondary Layer)

1D05V_S0

C16

C16 SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

1 2

C12

C12 SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

1 2

VCC_CORE_S0

C10

C10 SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

1 2

12

C34

C633

12

C376

C374

SC10U6D3V5KX-1GP

12

C36

SC10U6D3V5KX-1GP

C17

SC10U6D3V5KX-1GP

C45

C45 SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

1 2

12

C371

C361

SC10U6D3V5KX-1GP

12

C35

C24

SC10U6D3V5KX-1GP

C37

C37 SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

1 2

12

C358

C25

C349

SC10U6D3V5KX-1GP

12

C23

SC10U6D3V5KX-1GP

Mid Frequencd Decoupling

Place these inside socket cavity on L1 (North side Secondary)

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

A3 Date: Sheet

Date: Sheet

Date: Sheet of

Meron(3/3)-GND&Bypass

DS2-Intel

7

of

A

-1

47Wednesday, September 12, 2007

A

1 OF 10

U50A

12

E2 G2

G7 M6 H7 H3 G4

F3 N8 H2

M10 N12

N9 H5

P13

K9 M2

W10

Y8

V4 M3

J1 N5 N3 W6 W9 N2

Y7

Y9

P4 W3 N1

AD12

AE3 AD9 AC9

AC7 AC14 AD11 AC11

AB2

AD7

AB1

Y3 AC6 AE2 AC5

AG3

AJ9 AH8

AJ14

AE9

AE11 AH12

AJ5 AH5 AJ6 AE7 AJ7 AJ2 AE5 AJ3 AH2

AH13

B3

C2 W1

W2

B6

E5

B9

A9

CRESTLINE-GP-U-NF

H_RCOMP

R250

R250 24D9R2F-L-GP

24D9R2F-L-GP

U50A

H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63

H_SWING H_RCOMP

H_SCOMP H_SCOMP#

H_CPURST# H_CPUSLP#

H_AVREF H_DVREF

J13

H_A#3

B11

H_A#4

C11

H_A#5

M11

H_A#6

C15

H_A#7

F16

H_A#8

L13

H_A#9

G17

H_A#10

C14

H_A#11

K16

H_A#12

B13

H_A#13

L16

H_A#14

J17

H_A#15

B14

H_A#16

K19

H_A#17

P15

H_A#18

R17

H_A#19

B16

H_A#20

H20

H_A#21

L19

H_A#22

D17

H_A#23

M17

H_A#24

N16

H_A#25

J19

H_A#26

B18

H_A#27

E19

H_A#28

B17

H_A#29

B15

H_A#30

E17

H_A#31

C18

H_A#32

A19

H_A#33

B19

H_A#34

N19

H_A#35

G12

H_ADS#

H17

H_ADSTB#0

G20

H_ADSTB#1

C8

H_BNR#

HOST

100R2F-L1-GP-U

E8

H_BPRI#

F12

H_BREQ#

D6

H_DEFER#

C10

H_DBSY#

HPLL_CLK

HPLL_CLK#

H_DPWR#

H_DRDY#

H_HIT#

H_HITM# H_LOCK# H_TRDY#

H_DINV#0 H_DINV#1 H_DINV#2 H_DINV#3

H_DSTBN#0 H_DSTBN#1 H_DSTBN#2 H_DSTBN#3

H_DSTBP#0 H_DSTBP#1 H_DSTBP#2 H_DSTBP#3

H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4

H_RS#0 H_RS#1 H_RS#2

Spec: H_SWING=0.3125 X VTT +/- 1%

1D05V_S0

12

221R2F-2-GP

12

AM5 AM7 H8 K7 E4 C6 G10 B7

K5 L2 AD13 AE13

M7 K3 AD2 AH11

L7 K2 AC2 AJ10

M14 E13 A11 H13 B12

E12 D7 D8

R255

R254

12

C415

C415 SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

Layout Note : Place C33 near pin B3 of NB

CLK_MCH_BCLK CLK_MCH_BCLK#

H_SWNGH_VREF

H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35

H_ADS# H_ADSTB#0 H_ADSTB#1 H_BNR# H_BPRI# H_BR0# H_DEFER# H_DBSY#

H_DPWR# H_DRDY#

H_HIT#

H_HITM# H_LOCK# H_TRDY#

H_DINV#0 H_DINV#1 H_DINV#2 H_DINV#3

H_DSTBN#0 H_DSTBN#1 H_DSTBN#2 H_DSTBN#3

H_DSTBP#0 H_DSTBP#1 H_DSTBP#2 H_DSTBP#3

H_REQ#0

H_REQ#1

H_REQ#2

H_REQ#3

H_REQ#4

H_RS#0

H_RS#1

H_RS#2

4

H_A#[3..35] 5H_D#[0..63]6

H_ADS# 5 H_ADSTB#0 5 H_ADSTB#1 5 H_BNR# 5

H_BPRI# 5

H_BR0# 5

H_DEFER# 5

H_DBSY# 5 CLK_MCH_BCLK 4 CLK_MCH_BCLK# 4

H_DPWR# 6

H_DRDY# 5

H_HIT# 5

H_HITM# 5 H_LOCK# 5 H_TRDY# 5

H_DINV#0 6 H_DINV#1 6 H_DINV#2 6 H_DINV#3 6

H_DSTBN#0 6 H_DSTBN#1 6 H_DSTBN#2 6 H_DSTBN#3 6

H_DSTBP#0 6 H_DSTBP#1 6 H_DSTBP#2 6 H_DSTBP#3 6

H_REQ#0 5 H_REQ#1 5 H_REQ#2 5 H_REQ#3 5 H_REQ#4 5

H_RS#0 5 H_RS#1 5 H_RS#2 5

PM_PWROK21,36

VGATE_PWRGD21,41

PLT_RST_R#

TV_DCONSEL010 TV_DCONSEL110

1D8V_S3

12

C435

SC2D2U6D3V3KX-GP

SM_RCOMP_VOH

SM_RCOMP_VOL

SC2D2U6D3V3KX-GP

CFG[17:3] have internal pull up CFG[19:18] have internal pull down

C435

12

C444

DY

R86 0R2J-2-GP

1 2 1 2

R87 0R2J-2-GPR87 0R2J-2-GP

R52

1 2

100R2J-2-GP

PM_EXTTS#0 PM_EXTTS#1 TV_DCONSEL0 TV_DCONSEL1

CLKREQ#_B

12

SCD01U25V2KX-3GP

C437

12

C442

1 2

SCD01U25V2KX-3GP

MCH_CLKSEL04 MCH_CLKSEL14 MCH_CLKSEL24

PM_BMBUSY#21 H_DPRSTP#6,20,41 PM_EXTTS#014 PM_EXTTS#115

H_THERMTRIP#5,20,34,46

DPRSLPVR21,41

PLT_RST1# 19,23,24,28,29,30,34

RN18

1 2 3 4 5

SRN10KJ-6-GP

1 2

R69 10KR2J-3-GPR69 10KR2J-3-GP

3

R268

R268 1KR2F-3-GP

1KR2F-3-GP

R272

R272 3K01R2F-3-GP

3K01R2F-3-GP

R273

R273 1KR2F-3-GP

1KR2F-3-GP

PM_POK_R

8 7 6

TP33TP33 TP29TP29 TP32TP32 TP26TP26 TP27TP27 TP31TP31 TP34TP34 TP25TP25 TP35TP35

TP24TP24 TP39TP39

TP36TP36 TP37TP37

3D3V_S0

MCH_CLKSEL0 MCH_CLKSEL1 MCH_CLKSEL2

CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13

CFG16 CFG18

CFG19 CFG20

PM_BMBUSY# H_DPRSTP# PM_EXTTS#0 PM_EXTTS#1 PM_POK_R PLT_RST_R# H_THERMTRIP# DPRSLPVR

2 OF 10

U50B

P36

RSVD#P36

P37

RSVD#P37

R35

RSVD#R35

N35

RSVD#N35

AR12

RSVD#AR12

AR13

RSVD#AR13

AM12

RSVD#AM12

AN13

RSVD#AN13

J12

RSVD#J12

AR37

RSVD#AR37

AM36

RSVD#AM36

AL36

RSVD#AL36

AM37

RSVD#AM37

D20

RSVD#D20

H10

RSVD#H10

B51

RSVD#B51

BJ20

RSVD#BJ20

BK22

RSVD#BK22

BF19

RSVD#BF19

BH20

RSVD#BH20

BK18

RSVD#BK18

BJ18

RSVD#BJ18

BF23

RSVD#BF23

BG23

RSVD#BG23

BC23

RSVD#BC23

BD24

RSVD#BD24

BH39

RSVD#BH39

AW20

RSVD#AW20

BK20

RSVD#BK20

B44

RSVD#B44

C44

RSVD#C44

A35

RSVD#A35

B37

RSVD#B37

B36

RSVD#B36

B34

RSVD#B34

C34

RSVD#C34

P27

CFG0

N27

CFG1

N24

CFG2

C21

CFG3

C23

CFG4

F23

CFG5

N23

CFG6

G23

CFG7

J20

CFG8

C20

CFG9

R24

CFG10

L23

CFG11

J23

CFG12

E23

CFG13

E20

CFG14

K23

CFG15

M20

CFG16

M24

CFG17

L32

CFG18

N33

CFG19

L35

CFG20

G41

PM_BM_BUSY#

L39

PM_DPRSTP#

L36

PM_EXT_TS#0

J36

PM_EXT_TS#1

AW49

PWROK

AV20

RSTIN#

N20

THERMTRIP#

G36

DPRSLPVR

BJ51

NC#BJ51

BK51

NC#BK51

BK50

NC#BK50

BL50

NC#BL50

BL49

NC#BL49

BL3

NC#BL3

BL2

NC#BL2

BK1

NC#BK1

BJ1

NC#BJ1

E1

NC#E1

A5

NC#A5

C51

NC#C51

B50

NC#B50

A50

NC#A50

A49

NC#A49

BK2

NC#BK2

CRESTLINE-GP-U-NF

NB:71.GM965.A0U

RSVD

DDR MUXING

SM_RCOMP_VOH

SM_RCOMP_VOL

SM_VREF#AR49

SM_VREF#AW4

DPLL_REF_CLK

DPLL_REF_CLK#

DPLL_REF_SSCLK

DPLL_REF_SSCLK#

CLK

DMI

CFG PM NC

SDVO_CTRL_CLK

SDVO_CTRL_DATA

MISC ME GRAPHICS VID

2

SM_CK0 SM_CK1 SM_CK3 SM_CK4

SM_CK#0 SM_CK#1 SM_CK#3 SM_CK#4

SM_CKE0 SM_CKE1 SM_CKE3 SM_CKE4

SM_CS#0 SM_CS#1 SM_CS#2 SM_CS#3

SM_ODT0 SM_ODT1 SM_ODT2 SM_ODT3

SM_RCOMP

SM_RCOMP#

PEG_CLK

PEG_CLK#

DMI_RXN0 DMI_RXN1 DMI_RXN2 DMI_RXN3

DMI_RXP0 DMI_RXP1 DMI_RXP2 DMI_RXP3

DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3

DMI_TXP0 DMI_TXP1 DMI_TXP2 DMI_TXP3

GFX_VID0 GFX_VID1 GFX_VID2 GFX_VID3

GFX_VR_EN

CL_CLK

CL_DATA

CL_PWROK

CL_RST#

CL_VREF

CLKREQ#

ICH_SYNC#

TEST1 TEST2

M_CLK_DDR0

AV29

M_CLK_DDR1

BB23

M_CLK_DDR2

BA25

M_CLK_DDR3

AV23

M_CLK_DDR#0

AW30

M_CLK_DDR#1

BA23

M_CLK_DDR#2

AW25

M_CLK_DDR#3

AW23

DDR_CKE0_DIMMA

BE29

DDR_CKE1_DIMMA

AY32

DDR_CKE2_DIMMB

BD39

DDR_CKE3_DIMMB

BG37

DDR_CS0_DIMMA#

BG20

DDR_CS1_DIMMA#

BK16

DDR_CS2_DIMMB#

BG16

DDR_CS3_DIMMB#

BE13

M_ODT0

BH18

M_ODT1

BJ15

M_ODT2

BJ14

M_ODT3

BE16

SM_RCOMP_VOH

BK31

SM_RCOMP_VOL

BL31

SM_RCOMP

BL15

SM_RCOMP#

BK14 AR49

AW4

CLK_MCH_DREFCLK

B42

CLK_MCH_DREFCLK#

C42

MCH_SSCDREFCLK

H48

MCH_SSCDREFCLK#

H47

CLK_MCH_3GPLL

K44

CLK_MCH_3GPLL#

K45

AN47 AJ38 AN42 AN46

AM47 AJ39 AN41 AN45

AJ46 AJ41 AM40 AM44

AJ47 AJ42 AM39 AM43

DFGT_VID0

E35

DFGT_VID1

A39

DFGT_VID2

C38

DFGT_VID3

B39

DFGT_VR_EN

E36

AM49 AK50

PM_POK_R

AT43 AN49

CL_VREF

AM50

H35 K36 G39

MCH_ICH_SYNC#

G40

TEST1_GMCH

A37

TEST2_GMCH

R32

1

FOR Calero: 80.6 ohm Crestline: 20 ohm

M_CLK_DDR0 14 M_CLK_DDR1 14 M_CLK_DDR2 15 M_CLK_DDR3 15

M_CLK_DDR#0 14 M_CLK_DDR#1 14 M_CLK_DDR#2 15 M_CLK_DDR#3 15

DDR_CKE0_DIMMA 14 DDR_CKE1_DIMMA 14 DDR_CKE2_DIMMB 15 DDR_CKE3_DIMMB 15

DDR_CS0_DIMMA# 14 DDR_CS1_DIMMA# 14 DDR_CS2_DIMMB# 15 DDR_CS3_DIMMB# 15

M_ODT0 14 M_ODT1 14 M_ODT2 15 M_ODT3 15

1D8V_S3

1 2

R264 20R2F-GPR264 20R2F-GP

1 2

R261 20R2F-GPR261 20R2F-GP

DDR_VREF_S3

DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3

DMI_TXP0 DMI_TXP1 DMI_TXP2 DMI_TXP3

DMI_RXN0 DMI_RXN1 DMI_RXN2 DMI_RXN3

DMI_RXP0 DMI_RXP1 DMI_RXP2 DMI_RXP3

1 2

R65

20KR2J-L2-GP

Title

Size Document Number Rev

Size Document Number Rev Custom

Custom

Custom Date: Sheet

Date: Sheet

DDR_VREF_S3

CLK_MCH_DREFCLK 4 CLK_MCH_DREFCLK# 4 MCH_SSCDREFCLK 4 MCH_SSCDREFCLK# 4

CLK_MCH_3GPLL 4 CLK_MCH_3GPLL# 4

DMI_TXN0 21 DMI_TXN1 21 DMI_TXN2 21 DMI_TXN3 21

DMI_TXP0 21 DMI_TXP1 21 DMI_TXP2 21 DMI_TXP3 21

DMI_RXN0 21 DMI_RXN1 21 DMI_RXN2 21 DMI_RXN3 21

DMI_RXP0 21 DMI_RXP1 21 DMI_RXP2 21 DMI_RXP3 21

TP38TP38 TP94TP94 TP92TP92 TP93TP93 TP40TP40

CL_CLK0 21 CL_DATA0 21

CL_RST# 21

SDVO_CTRLCLK 23 SDVO_CTRLDATA 23

CLKREQ#_B 4 MCH_ICH_SYNC# 21

R64

1 2

0R0402-PAD

CRESTLINE(1/6)-AGTL+/DMI/DDR2

DS2-Intel

1D25V_S0

R84

R84 1KR2F-3-GP

1KR2F-3-GP

1 2

12

R85

R85 392R2F-GP

SCD1U16V2KX-3GP

392R2F-GP

8

C182

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

-1

of

47Wednesday, September 12, 2007

5

H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14

H_SWNG

54D9R2F-L1-GP

H_RCOMP H_SCOMP

H_SCOMP# H_RESET#

H_CPUSLP#

12

C426

SCD1U16V2ZY-2GP

H_D#15 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63

D D

C C

1D05V_S0

12

R249

R248

54D9R2F-L1-GP

H_RESET#5 H_CPUSLP#6

H_VREF

B B

layout note : Route H_SCOMP and H_SCOMP# with trace width, spacing and impedance (55 ohm) same as FSB data traces

Layout Note : H_RCOMP / H_VREF / H_SWNG trace width and spacing is 10/20

Layout Note : Place C32 within 100 mils of NB

NB:71.GM965.A0U

1D05V_S0

12

R263

R263 1KR2F-3-GP

1KR2F-3-GP

12

R262

R262 2KR2F-3-GP

2KR2F-3-GP

A

5

A

4

3

2

1

DDR_A_D[0..63] 14 DDR_A_BS[0..2] 14

SA_BS0 SA_BS1 SA_BS2

SA_CAS#

SA_DM0 SA_DM1 SA_DM2 SA_DM3 SA_DM4 SA_DM5 SA_DM6 SA_DM7

SA_DQS0 SA_DQS1 SA_DQS2 SA_DQS3 SA_DQS4 SA_DQS5 SA_DQS6

SA_DQS7 SA_DQS#0 SA_DQS#1 SA_DQS#2 SA_DQS#3 SA_DQS#4 SA_DQS#5 SA_DQS#6 SA_DQS#7

SA_MA0 SA_MA1 SA_MA2 SA_MA3 SA_MA4 SA_MA5 SA_MA6 SA_MA7 SA_MA8

SA_MA9 SA_MA10 SA_MA11 SA_MA12 SA_MA13 SA_MA14

SA_RAS#

SA_WE#

DDR_A_DM[0..7] 14 DDR_A_DQS[0..7] 14 DDR_A_DQS#[0..7] 14 DDR_A_MA[0..14] 14

5 OF 10

U50E

DDR_A_BS0

BB19

DDR_A_BS1

BK19

DDR_A_BS2

BF29

DDR_A_CAS#

BL17

DDR_A_DM0

AT45

DDR_A_DM1

BD44

DDR_A_DM2

BD42

DDR_A_DM3

AW38

DDR_A_DM4

AW13

DDR_A_DM5

BG8

DDR_A_DM6

AY5

DDR_A_DM7

AN6

DDR_A_DQS0

AT46

DDR_A_DQS1

BE48

DDR_A_DQS2

BB43

DDR_A_DQS3

BC37

DDR_A_DQS4

BB16

DDR_A_DQS5

BH6

DDR_A_DQS6

BB2

DDR_A_DQS7

AP3

DDR_A_DQS#0

AT47

DDR_A_DQS#1

BD47

DDR_A_DQS#2

BC41

DDR_A_DQS#3

BA37

DDR_A_DQS#4

BA16

DDR_A_DQS#5

BH7

DDR_A_DQS#6

BC1

DDR_A_DQS#7

AP2

DDR_A_MA0

BJ19

DDR_A_MA1

BD20

DDR_A_MA2

BK27

DDR_A_MA3

BH28

DDR_A_MA4

BL24

DDR_A_MA5

BK28

DDR_A_MA6

BJ27

DDR_A_MA7

BJ25

DDR_A_MA8

BL28

DDR_A_MA9

BA28

DDR_A_MA10

BC19

DDR_A_MA11

BE28

DDR_A_MA12

BG30

DDR_A_MA13

BJ16

DDR_A_MA14 DDR_B_MA14

BJ29

DDR_A_RAS#

BE18

SA_RCVEN#

AY20

DDR_A_WE#

BA19

DDR_A_CAS# 14 DDR_B_CAS# 15

DDR_A_RAS# 14

TP30TP30 TP28TP28

DDR_A_WE# 14

DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6

DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15

DDR_B_D16

DDR_B_D17

DDR_B_D18

DDR_B_D19

DDR_B_D20

DDR_B_D21

DDR_B_D22

DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31

DDR_B_D32

DDR_B_D33

DDR_B_D34

DDR_B_D35

DDR_B_D36

DDR_B_D37

DDR_B_D38

DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47

DDR_B_D48

DDR_B_D49

DDR_B_D50

DDR_B_D51

DDR_B_D52

DDR_B_D53

DDR_B_D54

DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63

AP49

AR51 AW50 AW51

AN51

AN50

AV50

AV49

BA50

BB50

BA49

BE50

BA51

AY49

BF50 BF49 BJ50 BJ44 BJ43

BL43 BK47 BK49 BK43 BK42

BJ41

BL41

BJ37

BJ36 BK41

BJ40

BL35 BK37 BK13 BE11 BK11 BC11 BC13 BE12 BC12 BG12

BJ10

BK10

BH5 BG1 BC2

BD3

AR1

AU2

BL9 BK5 BL5 BK9

BJ8 BJ6 BF4

BK3 BE4

BJ2 BA3 BB3

AT3 AY2 AY3

AT2

SB_DQ0 SB_DQ1 SB_DQ2 SB_DQ3 SB_DQ4 SB_DQ5 SB_DQ6 SB_DQ7 SB_DQ8 SB_DQ9 SB_DQ10 SB_DQ11 SB_DQ12 SB_DQ13 SB_DQ14 SB_DQ15 SB_DQ16 SB_DQ17 SB_DQ18 SB_DQ19 SB_DQ20 SB_DQ21 SB_DQ22 SB_DQ23 SB_DQ24 SB_DQ25 SB_DQ26 SB_DQ27 SB_DQ28 SB_DQ29 SB_DQ30 SB_DQ31 SB_DQ32 SB_DQ33 SB_DQ34 SB_DQ35 SB_DQ36 SB_DQ37 SB_DQ38 SB_DQ39 SB_DQ40 SB_DQ41 SB_DQ42 SB_DQ43 SB_DQ44 SB_DQ45 SB_DQ46 SB_DQ47 SB_DQ48 SB_DQ49 SB_DQ50 SB_DQ51 SB_DQ52 SB_DQ53 SB_DQ54 SB_DQ55 SB_DQ56 SB_DQ57 SB_DQ58 SB_DQ59 SB_DQ60 SB_DQ61 SB_DQ62 SB_DQ63

DDR SYSTEM MEMORY B

D D

4 OF 10

U50D

DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8

DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15

DDR_A_D16

DDR_A_D17

C C

B B

DDR_A_D18

DDR_A_D19

DDR_A_D20

DDR_A_D21

DDR_A_D22

DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31

DDR_A_D32

DDR_A_D33

DDR_A_D34

DDR_A_D35

DDR_A_D36

DDR_A_D37

DDR_A_D38

DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47

DDR_A_D48

DDR_A_D49

DDR_A_D50

DDR_A_D51

DDR_A_D52

DDR_A_D53

DDR_A_D54

DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63

AR43

AW44

BA45 AY46 AR41 AR45 AT42

AW47

BB45

BF48

BG47

BJ45 BB47 BG50 BH49 BE45

AW43

BE44 BG42 BE40

BF44 BH45 BG40

BF40 AR40

AW40

AT39

AW36 AW41

AY41 AV38 AT38 AV13 AT13

AW11

AV11 AU15 AT11 BA13 BA11 BE10 BD10

BD8 AY9

BG10

AW9

BD7 BB9 BB5 AY7 AT5 AT7 AY6 BB7 AR5 AR8 AR9 AN3 AM8

AN10

AT9 AN9 AM9

AN11

SA_DQ0 SA_DQ1 SA_DQ2 SA_DQ3 SA_DQ4 SA_DQ5 SA_DQ6 SA_DQ7 SA_DQ8 SA_DQ9 SA_DQ10 SA_DQ11 SA_DQ12 SA_DQ13 SA_DQ14 SA_DQ15 SA_DQ16 SA_DQ17 SA_DQ18 SA_DQ19 SA_DQ20 SA_DQ21 SA_DQ22 SA_DQ23 SA_DQ24 SA_DQ25 SA_DQ26 SA_DQ27 SA_DQ28 SA_DQ29 SA_DQ30 SA_DQ31 SA_DQ32 SA_DQ33 SA_DQ34 SA_DQ35 SA_DQ36 SA_DQ37 SA_DQ38 SA_DQ39 SA_DQ40 SA_DQ41 SA_DQ42 SA_DQ43 SA_DQ44 SA_DQ45 SA_DQ46 SA_DQ47 SA_DQ48 SA_DQ49 SA_DQ50 SA_DQ51 SA_DQ52 SA_DQ53 SA_DQ54 SA_DQ55 SA_DQ56 SA_DQ57 SA_DQ58 SA_DQ59 SA_DQ60 SA_DQ61 SA_DQ62 SA_DQ63

DDR SYSTEM MEMORRY A

SA_RCVEN#

SB_BS0 SB_BS1 SB_BS2

SB_CAS#

SB_DM0 SB_DM1 SB_DM2 SB_DM3 SB_DM4 SB_DM5 SB_DM6 SB_DM7

SB_DQS0 SB_DQS1 SB_DQS2 SB_DQS3 SB_DQS4 SB_DQS5 SB_DQS6

SB_DQS7 SB_DQS#0 SB_DQS#1 SB_DQS#2 SB_DQS#3 SB_DQS#4 SB_DQS#5 SB_DQS#6 SB_DQS#7

SB_MA0 SB_MA1 SB_MA2 SB_MA3 SB_MA4 SB_MA5 SB_MA6 SB_MA7 SB_MA8

SB_MA9 SB_MA10 SB_MA11 SB_MA12 SB_MA13 SB_MA14

SB_RAS#

SB_RCVEN#

SB_WE#

DDR_B_D[0..63] 15 DDR_B_BS[0..2] 15 DDR_B_DM[0..7] 15 DDR_B_DQS[0..7] 15 DDR_B_DQS#[0..7] 15 DDR_B_MA[0..14] 15

DDR_B_BS0

AY17

DDR_B_BS1

BG18

DDR_B_BS2

BG36

DDR_B_CAS#

BE17

DDR_B_DM0

AR50

DDR_B_DM1

BD49

DDR_B_DM2

BK45

DDR_B_DM3

BL39

DDR_B_DM4

BH12

DDR_B_DM5

BJ7

DDR_B_DM6

BF3

DDR_B_DM7

AW2

DDR_B_DQS0

AT50

DDR_B_DQS1

BD50

DDR_B_DQS2

BK46

DDR_B_DQS3

BK39

DDR_B_DQS4

BJ12

DDR_B_DQS5

BL7

DDR_B_DQS6

BE2

DDR_B_DQS7

AV2

DDR_B_DQS#0

AU50

DDR_B_DQS#1

BC50

DDR_B_DQS#2

BL45

DDR_B_DQS#3

BK38

DDR_B_DQS#4

BK12

DDR_B_DQS#5

BK7

DDR_B_DQS#6

BF2

DDR_B_DQS#7

AV3

DDR_B_MA0

BC18

DDR_B_MA1

BG28

DDR_B_MA2

BG25

DDR_B_MA3

AW17

DDR_B_MA4

BF25

DDR_B_MA5

BE25

DDR_B_MA6

BA29

DDR_B_MA7

BC28

DDR_B_MA8

AY28

DDR_B_MA9

BD37

DDR_B_MA10

BG17

DDR_B_MA11

BE37

DDR_B_MA12

BA39

DDR_B_MA13

BG13 BE24

DDR_B_RAS#

AV16

SB_RCVEN#

AY18

DDR_B_WE#

BC17

DDR_B_RAS# 15

DDR_B_WE# 15

CRESTLINE-GP-U-NF

NB:71.GM965.A0U NB:71.GM965.A0U

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

CRESTLINE(2/6)-DDR2 A/B CH

Size Document Number Rev

Size Document Number Rev A3

A3

A3 Date: Sheet

Date: Sheet

DS2-Intel

of

9

A

-1

47Wednesday, September 12, 2007

A

TV_DCONSEL08 TV_DCONSEL18

GMCH_DDCCLK17 GMCH_DDCDATA17 GMCH_VSYNC17 GMCH_HSYNC17

3D3V_S0

5

3D3V_S0

M_COMP M_LUMA M_CRMA

M_BLUE M_GREEN M_RED

4

LBKLT_CTL18

GMCH_BL_ON34

LDDC_CLK18 LDDC_DATA18 LCDVDD_EN18

R68 3K3R2F-2-GPR68 3K3R2F-2-GP

VGA_TXACLK-18 VGA_TXACLK+18 VGA_TXBCLK-18 VGA_TXBCLK+18

VGA_TXAOUT0-18 VGA_TXAOUT1-18 VGA_TXAOUT2-18

VGA_TXAOUT0+18 VGA_TXAOUT1+18 VGA_TXAOUT2+18

VGA_TXBOUT0-18 VGA_TXBOUT1-18 VGA_TXBOUT2-18

VGA_TXBOUT0+18 VGA_TXBOUT1+18 VGA_TXBOUT2+18

12

SRN33J-5-GP-U

RN55

23 1

SRN10KJ-5-GP

RN56

4

SRN10KJ-5-GP

1 2

12

R54

R55

150R2F-1-GP

TV_DCONSEL0 TV_DCONSEL1

12

R57

R56

150R2F-1-GP

RN54

1

4

2 3

1 2

R60 1K3R2F-1-GPR60 1K3R2F-1-GP

FOR Calero: 255 ohm Crestline: 1.3k ohm

LDDC_CLK LDDC_DATA

23 1

DY

LVDS_IBG

TP41TP41

R53

150R2F-1-GP

R61

150R2F-1-GP

CRT_VSYNC CRT_HSYNC

CRTIREF

SA:0428

For Crestline : 2.4 Kohm For Calero : 1.5Kohm

-1:0908 Chang R68 from

D D

64.24015.6DL to 64.33015.6DL

M_COMP35 M_LUMA35 M_CRMA35

C C

M_BLUE17 M_GREEN17 M_RED17

B B

4

3 OF 10

U50C

J40

L_BKLT_CTRL

H39

L_BKLT_EN

E39

L_CTRL_CLK

E40

L_CTRL_DATA

C37

L_DDC_CLK

D35

L_DDC_DATA

K40

L_VDD_EN

L41

LVDS_IBG

L43

LVDS_VBG

N41

LVDS_VREFH

N40

LVDS_VREFL

D46

LVDSA_CLK#

C45

LVDSA_CLK

D44

LVDSB_CLK#

E42

LVDSB_CLK

G51

LVDSA_DATA#0

E51

LVDSA_DATA#1

F49

LVDSA_DATA#2

C48

LVDSA_DATA#3

G50

LVDSA_DATA0

E50

LVDSA_DATA1

F48

LVDSA_DATA2

D47

LVDSA_DATA3

G44

LVDSB_DATA#0

B47

LVDSB_DATA#1

B45

LVDSB_DATA#2

E44

LVDSB_DATA0

A47

LVDSB_DATA1

A45

LVDSB_DATA2

E27

TVA_DAC

G27

TVB_DAC

K27

TVC_DAC

F27

TVA_RTN

J27

TVB_RTN

L27

TVC_RTN

M35

TV_DCONSEL0

P33

TV_DCONSEL1

H32

CRT_BLUE

G32

CRT_BLUE#

K29

CRT_GREEN

J29

CRT_GREEN#

F29

CRT_RED

E29

CRT_RED#

K33

CRT_DDC_CLK

G35

CRT_DDC_DATA

E33

CRT_VSYNC

C32

CRT_TVO_IREF

F33

CRT_HSYNC

CRESTLINE-GP-U-NF

NB:71.GM965.A0U

1D05V_S0

PEG_RX#0 PEG_RX#1 PEG_RX#2 PEG_RX#3 PEG_RX#4 PEG_RX#5 PEG_RX#6 PEG_RX#7 PEG_RX#8 PEG_RX#9

PEG_RX0 PEG_RX1 PEG_RX2 PEG_RX3 PEG_RX4 PEG_RX5 PEG_RX6 PEG_RX7 PEG_RX8

PEG_RX9 PEG_RX10 PEG_RX11 PEG_RX12 PEG_RX13 PEG_RX14 PEG_RX15

PEG_TX#0 PEG_TX#1 PEG_TX#2 PEG_TX#3 PEG_TX#4 PEG_TX#5 PEG_TX#6 PEG_TX#7 PEG_TX#8 PEG_TX#9

PEG_TX0

PEG_TX1

PEG_TX2

PEG_TX3

PEG_TX4

PEG_TX5

PEG_TX6

PEG_TX7

PEG_TX8

PEG_TX9 PEG_TX10 PEG_TX11 PEG_TX12 PEG_TX13 PEG_TX14 PEG_TX15

N43 M43

J51 L51 N47 T45 T50 U40 Y44 Y40 AB51 W49 AD44 AD40 AG46 AH49 AG45 AG41

J50 L50 M47 U44 T49 T41 W45 W41 AB50 Y48 AC45 AC41 AH47 AG49 AH45 AG42

N45 U39 U47 N51 R50 T42 Y43 W46 W38 AD39 AC46 AC49 AC42 AH39 AE49 AH44

M45 T38 T46 N50 R51 U43 W42 Y47 Y39 AC38 AD47 AC50 AD43 AG39 AE50 AH43

PEG_COMPI

PEG_COMPO

LVDS

PEG_RX#10 PEG_RX#11 PEG_RX#12 PEG_RX#13 PEG_RX#14 PEG_RX#15

TV VGA

PEG_TX#10

PCI_EXPRESS GRAPHICS

PEG_TX#11 PEG_TX#12 PEG_TX#13 PEG_TX#14 PEG_TX#15

1 2

R74 24D9R2F-L-GPR74 24D9R2F-L-GP

PEGCOMP

NB_SDVOB_RNB_SDVOB_GNB_SDVOB_BNB_SDVOB_C-

NB_SDVOB_R+ NB_SDVOB_G+ NB_SDVOB_B+ NB_SDVOB_C+

3

PEGCOMP trace width and spacing is 20/25 mils.

SDVOB_INT- 23

SDVOB_INT+ 23

NB_SDVOB_RNB_SDVOB_GNB_SDVOB_BNB_SDVOB_C-

NB_SDVOB_R+ NB_SDVOB_G+ NB_SDVOB_B+

NB_SDVOB_C+

CFG[2:0] FSB Freq select

CFG8 (Low power PCIE)

(PCIE Graphics Lane Reversal)

CFG16 (FSB Dynamic ODT)

CFG19(DMI Lane Reversal)

CFG20(PCIE/SDVO consurrent)

C469 SCD1U10V2KX-4GPC469 SCD1U10V2KX-4GP

12

C464 SCD1U10V2KX-4GPC464 SCD1U10V2KX-4GP

12

C474 SCD1U10V2KX-4GPC474 SCD1U10V2KX-4GP

12

C480 SCD1U10V2KX-4GPC480 SCD1U10V2KX-4GP

12

C470 SCD1U10V2KX-4GPC470 SCD1U10V2KX-4GP

12

C468 SCD1U10V2KX-4GPC468 SCD1U10V2KX-4GP

12

C478 SCD1U10V2KX-4GPC478 SCD1U10V2KX-4GP

12

C484 SCD1U10V2KX-4GPC484 SCD1U10V2KX-4GP

12

2

Strap Pin Table

010 = FSB 800MHz 011 = FSB 667MHz Others = Reserved

CFG5 (DMI select)

CFG6 Reserved

CFG7 (CPU Strap)

CFG9

CFG[11:10] Reserved

CFG[13:12] (XOR/ALLZ)

CFG[15:14] Reserved

CFG[18:17] Reversed

SDVO_CTRLDATA 0 = No SDVO Device Present *

SDVOB_R- 23 SDVOB_G- 23 SDVOB_B- 23 SDVOB_C- 23

SDVOB_R+ 23 SDVOB_G+ 23 SDVOB_B+ 23 SDVOB_C+ 23

0 = DMI x 2 1 = DMI x 4 *

0 = Reserved 1 = Mobile CPU *

0 = Normal mode 1 = Low Power mode *

0 = Reverse Lane 1 = Normal Operation *

00 = Reserved 01 = XOR Mode Enabled 10 = All Z Mode Enabled 11 = Normal Operation (Default)*

0 = Disable 1 = Enable *

1 = SDVO Device Present

0 = Normal Operation * (Lane number in Order) 1 = Reverse lane

0 = Only PCIE or SDVO is operational * 1 = PCIE/SDVO are operating simu.

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

CRESTLINE(3/6)-VGA/LVDS/TV

Size Document Number Rev

Size Document Number Rev A3

A3

Wednesday, September 12, 2007

Date: Sheet

Wednesday, September 12, 2007

Date: Sheet

Wednesday, September 12, 2007

Date: Sheet

DS2-Intel

1

10 47

-1

of

-1

A

5

A

3D3V_S03D3V_S0_DAC_BG

R58

12

0R3-0-U-GP

SCD1U16V2ZY-2GP

12

D D

3D3V_S0_DAC_CRT

SCD1U16V2ZY-2GP

12

0R3-0-U-GP

C121

SB:07/01 Change R58,R59 from 0602 close pad to

63.00000.00L

3D3V_S0

R59

12

0R3-0-U-GP

C127

SCD1U16V2ZY-2GP

3D3V_S0_DAC_CRT

3D3V_S0_DAC_BG

C124

3D3V_S0

12

Place TC21 near R58 and R59

3D3V_S0

12

TC21

DY

SC22U6D3V5MX-2GP

1D25V_S0

SC10U6D3V5KX-1GP

1D25V_S0

SC22U6D3V5MX-2GP

12

C89

C115

SC10U6D3V5KX-1GP

12

C82

C101

C C

B B

SC1U10V3KX-3GP

SC10U6D3V5KX-1GP

3D3V_S0_TVDACC

SCD022U16V2KX-3GP

C446

12

3D3V_S0_TVDACA

SCD022U16V2KX-3GP

12

C434

3D3V_S0_TVDACB

12

C440

SCD1U16V2ZY-2GP

SCD022U16V2KX-3GP

C445

12

C433

12

C439

R271

R271 0R0603-PAD

0R0603-PAD

SCD1U16V2ZY-2GP

R267

0R0603-PAD

R269

0R0603-PAD

SCD1U16V2ZY-2GP

VCCA_TVDAC

12

VCCA_TVDAC

12

VCCA_TVDAC

12

SC10U6D3V5KX-1GP

1D25V_S0_DPLLA 1D25V_S0_DPLLB

1D25V_S0_MPLL

1D8V_S0_TXLVDS

3D3V_S0

12

C171

C171 SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

1D25V_S0_PEGPLL

-1:0909

12

C94

SCD22U10V3KX-2GP

12

C104

SCD1U16V2ZY-2GP

1D25V_S0_PEGPLL

1D25V_S0_HPLL

150mA

12

C157

SC1KP50V2KX-1GP

400uA

SCD1U16V2ZY-2GP

C167

12

C118

SC1U10V3KX-3GP

3D3V_S0_TVDACA 3D3V_S0_TVDACB 3D3V_S0_TVDACC

1D5V_S0

1D25V_S0

1D8V_S0_LVDS

NB:71.GM965.A0U

1D5V_S0

SCD022U16V2KX-3GP

12

C114

1D8V_S0_LVDS

12

C172

SC10U6D3V5KX-1GP

20mil

SCD1U16V2ZY-2GP

4

U50H

J32

VCC_SYNC

A33

VCCA_CRT_DAC

B33

VCCA_CRT_DAC

A30

VCCA_DAC_BG

B32

VSSA_DAC_BG

B49

VCCA_DPLLA

H49

VCCA_DPLLB

AL2

VCCA_HPLL

AM2

VCCA_MPLL

A41

VCCA_LVDS

B41

VSSA_LVDS

K50

VCCA_PEG_BG

K49

VSSA_PEG_BG

U51

VCCA_PEG_PLL

AW18

VCCA_SM

AV19

VCCA_SM

AU19

VCCA_SM

AU18

VCCA_SM

AU17

VCCA_SM

AT22

VCCA_SM

AT21

VCCA_SM

AT19

VCCA_SM

AT18

VCCA_SM

AT17

VCCA_SM

AR17

VCCA_SM_NCTF

AR16

VCCA_SM_NCTF

BC29

VCCA_SM_CK

BB29

VCCA_SM_CK

C25

VCCA_TVA_DAC

B25

VCCA_TVA_DAC

C27

VCCA_TVB_DAC

B27

VCCA_TVB_DAC

B28

VCCA_TVC_DAC

A28

VCCA_TVC_DAC

M32

VCCD_CRT

L29

VCCD_TVDAC

N28

VCCD_QDAC

AN2

VCCD_HPLL

U48

VCCD_PEG_PLL

J41

VCCD_LVDS

H42

VCCD_LVDS

CRESTLINE-GP-U-NF

Place C108,C109

12

C105

near Pin N28

R82

1 2

0R0603-PAD

12

C164

SC1U10V3KX-3GP

8 OF 10

A LVDS PLL CRT

A PEG

LVDS TV/CRT

1D8V_S3

POWER

AXD

VCC_AXD_NCTF

AXF

VCC_SM_CK VCC_SM_CK VCC_SM_CK VCC_SM_CK

SM CK

VCC_TX_LVDS

HV

TV A CK A SM

PEG

VCC_RXR_DMI VCC_RXR_DMI

DMI

VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT

VTT

VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT

VCC_AXD VCC_AXD VCC_AXD VCC_AXD VCC_AXD VCC_AXD

VCC_AXF VCC_AXF VCC_AXF

VCC_DMI

VCC_HV VCC_HV

VCC_PEG VCC_PEG VCC_PEG VCC_PEG VCC_PEG

VTTLF VTTLF VTTLF

VTTLF

1D8V_S0_TXLVDS

40mil

SC10U6D3V5KX-1GP

U13 U12 U11 U9 U8 U7 U5 U3 U2 U1 T13 T11 T10 T9 T7 T6 T5 T3 T2 R3 R2 R1

AT23 AU28 AU24 AT29 AT25 AT30

AR29

B23 B21 A21

AJ50

BK24 BK23 BJ24 BJ23

A43

C40 B40

AD51 W50 W51 V49 V50

AH50 AH51

A7 F2 AH1

1 2

12

C162

1D05V_S0

VTTLF1 VTTLF2 VTTLF3

R79

0R0603-PAD

3

12

C106

SC10U6D3V5KX-1GP

12

C75

SCD47U16V3ZY-3GP

12

C117

SC1U10V3KX-3GP

1D25V_S0

1D8V_S3

SC1KP50V2KX-1GP

1D8V_S0_TXLVDS

12

C153

1D05V_S0

20mil

C406

C404

12

SCD47U16V3ZY-3GP

1D8V_S3

12

C110

C110 SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

12

SCD47U16V3ZY-3GP

C168

C83

C137

C422

SCD1U16V2ZY-2GP

12

SC4D7U6D3V5KX-3GP

C76

SC1U10V3KX-3GP

1D25V_S0

SC4D7U6D3V5KX-3GP

1D25V_S0

SCD1U16V2ZY-2GP

C96

12

3D3V_S0_HV

12

C139

SCD1U16V2ZY-2GP

SCD47U16V3ZY-3GP

3D3V_S0

1 2

BLM18PG181SN-3GP

L85 2nd source

68.00214.101/68.00217.141

2

1D25V_S0

1D25V_S0_DPLLB

1 2

C493

C396

C181

C490

C169

SC10U6D3V5KX-1GP

1

2

BAS16-1-GP

L26 L-10UH-11-GPL26 L-10UH-11-GP

12

C170

SCD1U16V2ZY-2GP

L16

1 2

BLM18AG121SN-1GP

C399

12

SCD1U16V2ZY-2GP

L4

1 2

SCD1U16V2ZY-2GP

C176

12

BLM18PG121SN-1GP

1 2

L25 L-10UH-11-GPL25 L-10UH-11-GP

SCD1U16V2ZY-2GP

12

C492

SC10U6D3V5KX-1GP

12

C180

D12

3

SC10U6D3V5KX-1GP

12

1D25V_S0_HPLL

12

1D25V_S0_PEGPLL 1D5V_S0

SC10U6D3V5KX-1GP

DY

12

1D25V_S0_DPLLA

SC10U6D3V5KX-1GP

12

1D05V_S0

SCD1U16V2ZY-2GP

12

1D05V_S0

VCCA_TVDAC

L19

12

C447

C447 SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

12

C179

1D25V_S0

Place C95,C99,C112 near Pin AD51,W50,W51

3D3V_S0 3D3V_S0_HV1D05V_S0_D

R70

12

10R2J-2-GP

Title

Size Document Number Rev

Size Document Number Rev A3

A3

A3 Date: Sheet

Date: Sheet

Date: Sheet of

SC10U6D3V5KX-1GP

12

C99

1D8V_S3

SC10U6D3V5KX-1GP

12

C126

SCD022U16V2KX-3GP

C119

12

1D25V_S0_MPLL

C407

12

R71

12

0R0402-PAD

CRESTLINE(4/6)-PWR

DS2-Intel

1

Place C69,C70 near Pin B23,B21,A21

12

C107

C107 SC1U16V3ZY-GP

SC1U16V3ZY-GP

Place C75,C76 near Pin

12

C102

SCD1U16V2ZY-2GP

BK24,BK23,BJ24,BJ23

SCD1U16V2ZY-2GP

C125

Place C82,C83

12

near Pin M32,L29

1D25V_S0

SCD1U16V2ZY-2GP

C60

Place C96

12

near Pin AN2

L17

1 2

C411

BLM18AG121SN-1GP

12

SCD1U16V2ZY-2GP

SC10U6D3V5KX-1GP

12

C144

C144 SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

1D25V_S0

of

11

-1

47Wednesday, September 12, 2007

A

5

A

1D05V_S0

AT35 AT34 AH28 AC32 AC31 AK32

D D

1D8V_S3

C133

C132

TC17

12

DY

C133

C142

12

C C

ST220U2VBM-3GP

SC10U6D3V5KX-1GP

B B

C134

C129

12

C129

12

SC10U6D3V5KX-1GP

12

1D05V_S0

C87

SC1U10V3KX-3GP

SCD1U16V2ZY-2GP

12

C111

SCD1U16V2ZY-2GP

AH32 AH31 AH29

AU32 AU33 AU35 AV33

AW33

C131

AW35

AY35 BA32 BA33 BA35 BB33 BC32 BC33 BC35 BD32 BD35 BE32 BE33 BE35

SCD01U16V2KX-3GP

BG32 BG33 BG35 BH32 BH34 BH35

BK32 BK33 BK34 BK35

AU30

AA20 AA23 AA26 AA28 AB21 AB24 AB29 AC20 AC21 AC23 AC24 AC26 AC28 AC29 AD20 AD23 AD24 AD28

AA31 AH20 AH21 AH23 AH24 AH26 AD31

AN14

U50F

VCC VCC VCC VCC VCC VCC

AJ31

VCC

AJ28

VCC VCC VCC VCC

AF32

VCC

R30

VCC

VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM

BF33

VCC_SM

BF34

VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM

BJ32

VCC_SM

BJ33

VCC_SM

BJ34

VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM

BL33

VCC_SM VCC_SM

R20

VCC_AXG

T14

VCC_AXG

W13

VCC_AXG

W14

VCC_AXG

Y12

VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG

AF21

VCC_AXG

AF26

VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG

AJ20

VCC_AXG VCC_AXG

CRESTLINE-GP-U-NF

6 OF 10

VCC CORE

POWER

VCC SM

VCC GFX

4

LIB C

VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF

VCC GFX NCTF

VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF

VCC_SM_LF VCC_SM_LF VCC_SM_LF VCC_SM_LF VCC_SM_LF VCC_SM_LF VCC_SM_LF

VCC SM LF

NB:71.GM965.A0U

T17 T18 T19 T21 T22 T23 T25 U15 U16 U17 U19 U20 U21 U23 U26 V16 V17 V19 V20 V21 V23 V24 Y15 Y16 Y17 Y19 Y20 Y21 Y23 Y24 Y26 Y28 Y29 AA16 AA17 AB16 AB19 AC16 AC17 AC19 AD15 AD16 AD17 AF16 AF19 AH15 AH16 AH17 AH19 AJ16 AJ17 AJ19 AK16 AK19 AL16 AL17 AL19 AL20 AL21 AL23 AM15 AM16 AM19 AM20 AM21 AM23 AP15 AP16 AP17 AP19 AP20 AP21 AP23 AP24 AR20 AR21 AR23 AR24 AR26 V26 V28 V29 Y31

AW45 BC39 BE39 BD17 BD4 AW8 AT6

1D05V_S0

VCCSM_LF1 VCCSM_LF2 VCCSM_LF3 VCCSM_LF4 VCCSM_LF5 VCCSM_LF6 VCCSM_LF7

3

-1:0909

C136

C403

12

TC15

C90

12

SCD1U16V2ZY-2GP

C66SCD1U16V2ZY-2GP C66SCD1U16V2ZY-2GP

12

C120

12

SCD22U10V2KX-1GP

C71SCD1U16V2ZY-2GP C71SCD1U16V2ZY-2GP

12

C79

12

SC4D7U6D3V5KX-3GP

C62SCD22U10V2KX-1GP C62SCD22U10V2KX-1GP

C93SCD22U10V2KX-1GP C93SCD22U10V2KX-1GP

C143SCD47U16V3ZY-3GP C143SCD47U16V3ZY-3GP

12

DY

ST220U2VBM-3GP

C155SC1U10V3KX-3GP C155SC1U10V3KX-3GP

C156SC1U10V3KX-3GP C156SC1U10V3KX-3GP

12

C403

12

SC10U6D3V5KX-1GP

C158 SCD22U10V2KX-1GPC158 SCD22U10V2KX-1GP

C160 SCD22U10V2KX-1GPC160 SCD22U10V2KX-1GP

12

C402

12

SC10U6D3V5KX-1GP

1D05V_S0

12

C92

C92 SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

C116 SCD1U16V2ZY-2GPC116 SCD1U16V2ZY-2GP

12

C128 SCD22U10V2KX-1GPC128 SCD22U10V2KX-1GP12C402

C130 SCD22U10V2KX-1GPC130 SCD22U10V2KX-1GP

12

C140 SCD1U16V2ZY-2GPC140 SCD1U16V2ZY-2GP

12

1D05V_S0

C100 SCD1U16V2ZY-2GPC100 SCD1U16V2ZY-2GP

12

C141 SCD1U16V2ZY-2GPC141 SCD1U16V2ZY-2GP

12

2

U50G

AB33

VCC_NCTF

AB36

VCC_NCTF

AB37

VCC_NCTF

AC33

VCC_NCTF

AC35

VCC_NCTF

AC36

VCC_NCTF

AD35

VCC_NCTF

AD36

VCC_NCTF

AF33

VCC_NCTF

AF36

VCC_NCTF

AH33

VCC_NCTF

AH35

VCC_NCTF

AH36

VCC_NCTF

AH37

VCC_NCTF

AJ33

VCC_NCTF

AJ35

VCC_NCTF

AK33

VCC_NCTF

AK35

VCC_NCTF

AK36

VCC_NCTF

AK37

VCC_NCTF

AD33

VCC_NCTF

AJ36

VCC_NCTF

AM35

VCC_NCTF

AL33

VCC_NCTF

AL35

VCC_NCTF

AA33

VCC_NCTF

AA35

VCC_NCTF

AA36

VCC_NCTF

AP35

VCC_NCTF

AP36

VCC_NCTF

AR35

VCC_NCTF

AR36

VCC_NCTF

Y32

VCC_NCTF

Y33

VCC_NCTF

Y35

VCC_NCTF

Y36

VCC_NCTF

Y37

VCC_NCTF

T30

VCC_NCTF

T34

VCC_NCTF

T35

VCC_NCTF

U29

VCC_NCTF

U31

VCC_NCTF

U32

VCC_NCTF

U33

VCC_NCTF

U35

VCC_NCTF

U36

VCC_NCTF

V32

VCC_NCTF

V33

VCC_NCTF

V36

VCC_NCTF

V37

VCC_NCTF

AL24

VCC_AXM_NCTF

AL26

VCC_AXM_NCTF

AL28

VCC_AXM_NCTF

AM26

VCC_AXM_NCTF

AM28

VCC_AXM_NCTF

AM29

VCC_AXM_NCTF

AM31

VCC_AXM_NCTF

AM32

VCC_AXM_NCTF

AM33

VCC_AXM_NCTF

AP29

VCC_AXM_NCTF

AP31

VCC_AXM_NCTF

AP32

VCC_AXM_NCTF

AP33

VCC_AXM_NCTF

AL29

VCC_AXM_NCTF

AL31

VCC_AXM_NCTF

AL32

VCC_AXM_NCTF

AR31

VCC_AXM_NCTF

AR32

VCC_AXM_NCTF

AR33

VCC_AXM_NCTF

CRESTLINE-GP-U-NF

1

7 OF 10

T27

VSS_NCTF

T37

VSS_NCTF

U24

VSS_NCTF

U28

VSS_NCTF

V31

VSS_NCTF

V35

VSS_NCTF

AA19

VSS_NCTF

AB17

VSS_NCTF

AB35

VSS_NCTF

AD19

VSS_NCTF

AD37

VSS_NCTF

AF17

VSS_NCTF

AF35

VSS_NCTF

AK17

VSS_NCTF

AM17

VSS_NCTF

VSS NCTF

VCC NCTF

POWER

VSS SCBVSS AXM

VSS AXM NCTF

Title

Size Document Number Rev

Size Document Number Rev A3

A3

A3 Date: Sheet

Date: Sheet of

AM24

VSS_NCTF

AP26

VSS_NCTF

AP28

VSS_NCTF

AR15

VSS_NCTF

AR19

VSS_NCTF

AR28

VSS_NCTF

NCTF_U56-1

A3

VSS_SCB

B2

VSS_SCB

C1

VSS_SCB VSS_SCB VSS_SCB VSS_SCB

VCC_AXM VCC_AXM VCC_AXM VCC_AXM VCC_AXM VCC_AXM VCC_AXM

CRESTLINE(5/6)-PWR/GND

BL1 BL51 A51

AT33 AT31 AK29 AK24 AK23 AJ26 AJ23

NCTF_U56-2 NCTF_U56-4 NCTF_U56-3

1D05V_S0

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

DS2-Intel

12

TP89TP89

TP88TP88 TP96TP96 TP95TP95

-1

of

-1

47Wednesday, September 12, 2007

A

5

A

U50I

A13

VSS

A15

VSS

A17

VSS

A24

VSS

D D

C C

B B

AA21

VSS

AA24

VSS

AA29

VSS

AB20

VSS

AB23

VSS

AB26

VSS

AB28

VSS

AB31

VSS

AC10

VSS

AC13

VSS

AC3

VSS

AC39

VSS

AC43

VSS

AC47

VSS

AD1

VSS

AD21

VSS

AD26

VSS

AD29

VSS

AD3

VSS

AD41

VSS

AD45

VSS

AD49

VSS

AD5

VSS

AD50

VSS

AD8

VSS

AE10

VSS

AE14

VSS

AE6

VSS

AF20

VSS

AF23

VSS

AF24

VSS

AF31

VSS

AG2

VSS

AG38

VSS

AG43

VSS

AG47

VSS

AG50

VSS

AH3

VSS

AH40

VSS

AH41

VSS

AH7

VSS

AH9

VSS

AJ11

VSS

AJ13

VSS

AJ21

VSS

AJ24

VSS

AJ29

VSS

AJ32

VSS

AJ43

VSS

AJ45

VSS

AJ49

VSS

AK20

VSS

AK21

VSS

AK26

VSS

AK28

VSS

AK31

VSS

AK51

VSS

AL1

VSS

AM11

VSS

AM13

VSS

AM3

VSS

AM4

VSS

AM41

VSS

AM45

VSS

AN1

VSS

AN38

VSS

AN39

VSS

AN43

VSS

AN5

VSS

AN7

VSS

AP4

VSS

AP48

VSS

AP50

VSS

AR11

VSS

AR2

VSS

AR39

VSS

AR44

VSS

AR47

VSS

AR7

VSS

AT10

VSS

AT14

VSS

AT41

VSS

AT49

VSS

AU1

VSS

AU23

VSS

AU29

VSS

AU3

VSS

AU36

VSS

AU49

VSS

AU51

VSS

AV39

VSS

AV48

VSS

AW1

VSS

AW12

VSS

AW16

VSS

CRESTLINE-GP-U-NF

NB:71.GM965.A0U

9 OF 10

VSS

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

4

AW24 AW29 AW32 AW5 AW7 AY10 AY24 AY37 AY42 AY43 AY45 AY47 AY50 B10 B20 B24 B29 B30 B35 B38 B43 B46 B5 B8 BA1 BA17 BA18 BA2 BA24 BB12 BB25 BB40 BB44 BB49 BB8 BC16 BC24 BC25 BC36 BC40 BC51 BD13 BD2 BD28 BD45 BD48 BD5 BE1 BE19 BE23 BE30 BE42 BE51 BE8 BF12 BF16 BF36 BG19 BG2 BG24 BG29 BG39 BG48 BG5 BG51 BH17 BH30 BH44 BH46 BH8 BJ11 BJ13 BJ38 BJ4 BJ42 BJ46 BK15 BK17 BK25 BK29 BK36 BK40 BK44 BK6 BK8 BL11 BL13 BL19 BL22 BL37 BL47 C12 C16 C19 C28 C29 C33 C36 C41

3

10 OF 10

U50J

C46

VSS

C50

VSS

C7

VSS

D13

VSS

D24

VSS

D3

VSS

D32

VSS

D39

VSS

D45

VSS

D49

VSS

E10

VSS

E16

VSS

E24

VSS

E28

VSS

E32

VSS

E47

VSS

F19

VSS

F36

VSS

F4

VSS

F40

VSS

F50

VSS

G1

VSS

G13

VSS

G16

VSS

G19

VSS

G24

VSS

G28

VSS

G29

VSS

G33

VSS

G42

VSS

G45

VSS

G48

VSS

G8

VSS

H24

VSS

H28

VSS

H4

VSS

H45

VSS

J11

VSS

J16

VSS

J2

VSS

J24

VSS

J28

VSS

J33

VSS

J35

VSS

J39

VSS

K12

VSS

K47

VSS

K8

VSS

L1

VSS

L17

VSS

L20

VSS

L24

VSS

L28

VSS

L3

VSS

L33

VSS

L49

VSS

M28

VSS

M42

VSS

M46

VSS

M49

VSS

M5

VSS

M50

VSS

M9

VSS

N11

VSS

N14

VSS

N17

VSS

N29

VSS

N32

VSS

N36

VSS

N39

VSS

N44

VSS

N49

VSS

N7

VSS

P19

VSS

P2

VSS

P23

VSS

P3

VSS

P50

VSS

R49

VSS

T39

VSS

T43

VSS

T47

VSS

U41

VSS

U45

VSS

U50

VSS

V2

VSS

V3

VSS

CRESTLINE-GP-U-NF

NB:71.GM965.A0U

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSS VSS VSS VSS VSS VSS VSS VSS

W11 W39 W43 W47 W5 W7 Y13 Y2 Y41 Y45 Y49 Y5 Y50 Y11 P29 T29 T31 T33 R28

AA32 AB32 AD32 AF28 AF29 AT27 AV25 H50

2

Title

CRESTLINE(6/6)-PWR/GND

Size Document Number Rev

Size Document Number Rev A3

A3

A3 Date: Sheet of

Date: Sheet

DS2-Intel

1

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

of

47Wednesday, September 12, 2007

13

47Wednesday, September 12, 2007

-1

A

5

DDR_A_DQS#[0..7]9

DDR_A_D[0..63]9 DDR_A_DM[0..7]9 DDR_A_DQS[0..7]9 DDR_A_MA[0..14]9

D D

C C

B B

A A

Layout Note: Place near DM1

1D8V_S3

C123

C91

12

SC2D2U16V5ZY-2GP

Layout Note: Place one cap close to every 2 pullup resistors terminated to +0.9VS

DDR_VREF_S0

C112

12

SCD1U16V2ZY-2GP

DY

C77

C84

12

SC2D2U16V5ZY-2GP

C73

C95

12

SCD1U16V2ZY-2GP

12

SC2D2U16V5ZY-2GP

C423

C63

12

SCD1U16V2ZY-2GP

change to 8P4R

DDR_VREF_S0

RN13

DDR_A_MA9 DDR_A_MA5 DDR_A_MA8 DDR_A_MA3

DDR_A_MA1 DDR_A_MA10 DDR_A_BS0 DDR_A_WE#

DDR_A_CAS# DDR_A_MA13 M_ODT1 DDR_CS1_DIMMA#

RN13

1 2 3 4 5

SRN56J-5-GP

RN11

1 2 3 4 5

SRN56J-5-GP

RN9

1 2 3 4 5

SRN56J-5-GP

5

1

8

2

7

3

6

4 5

1

8

2

7

3

6

4 5

8

1

7

2

6

3 4 5

1 2 3 4 5

C81

SCD1U16V2ZY-2GP

12

SCD1U16V2ZY-2GP

RN15

SRN56J-5-GP

SRN56J-5-GP RN50

RN50

SRN56J-5-GP

SRN56J-5-GP RN48

RN48

SRN56J-5-GP

SRN56J-5-GP RN52

RN52

SRN56J-5-GP

DDR_A_BS[0..2]9

C98

12

SCD1U16V2ZY-2GP

C430

SCD1U16V2ZY-2GP

DDR_A_MA12

8

DDR_A_BS2

7

DDR_CKE0_DIMMA

6

DDR_A_MA0

8

DDR_A_MA2

7

DDR_A_MA4

6

DDR_A_MA6

M_ODT0

8

DDR_CS0_DIMMA#

7

DDR_A_RAS#

6

DDR_A_BS1

DDR_A_MA7

8

DDR_A_MA11

7

DDR_A_MA14

6

DDR_CKE1_DIMMA

C69

12

SCD1U16V2ZY-2GP

C438

12

SCD1U16V2ZY-2GP

4

C122

12

SC10U6D3V5KX-1GP

C421

C427

12

SCD1U16V2ZY-2GP

C421

C85

12

SCD1U16V2ZY-2GP

Layout Note: Place these resistors closely DM1,all trace length Max=1.5"

4

SCD1U16V2ZY-2GP

DDR_CS0_DIMMA#8

DDR_CS1_DIMMA#8 DDR_CKE0_DIMMA8

DDR_CKE1_DIMMA8

ICH_SMBDATA4,15,21

DDR_VREF_S3

SCD1U16V2ZY-2GP

3

DM2

MH1

DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14

DDR_A_BS2

DDR_A_BS0 DDR_A_BS1

DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63

PM_EXTTS#08

DDR_CS0_DIMMA#

DDR_CS1_DIMMA# DDR_CKE0_DIMMA DDR_CKE1_DIMMA

12

3

DDR_A_RAS#

DDR_A_CAS#

DDR_A_WE#

ICH_SMBCLK

ICH_SMBDATA

M_ODT0 M_ODT1

DDR_VREF_S3

12

C185

SC2D2U16V5ZY-2GP

DDR_A_RAS#9 DDR_A_CAS#9

DDR_A_WE#9

ICH_SMBCLK4,15,21

M_ODT08

M_ODT18

C184

MH1

102

A0

101

A1

100

A2

99

A3

98

A4

97

A5

94

A6

92

A7

93

A8

91

A9

105

A10/AP

90

A11

89

A12

116

A13

86

A14

84

A15

85

A16_BA2

107

BA0

106

BA1

5

DQ0

7

DQ1

17

DQ2

19

DQ3

4

DQ4

6

DQ5

14

DQ6

16

DQ7

23

DQ8

25

DQ9

35

DQ10

37

DQ11

20

DQ12

22

DQ13

36

DQ14

38

DQ15

43

DQ16

45

DQ17

55

DQ18

57

DQ19

44

DQ20

46

DQ21

56

DQ22

58

DQ23

61

DQ24

63

DQ25

73

DQ26

75

DQ27

62

DQ28

64

DQ29

74

DQ30

76

DQ31

123

DQ32

125

DQ33

135

DQ34

137

DQ35

124

DQ36

126

DQ37

134

DQ38

136

DQ39

141

DQ40

143

DQ41

151

DQ42

153

DQ43

140

DQ44

142

DQ45

152

DQ46

154

DQ47

157

DQ48

159

DQ49

173

DQ50

175

DQ51

158

DQ52

160

DQ53

174

DQ54

176

DQ55

179

DQ56

181

DQ57

189

DQ58

191

DQ59

180

DQ60

182

DQ61

192

DQ62

194

DQ63

50

NC#50

69

NC#69

83

NC#83

120

NC#120

163

NC#163/TEST

110

CS0#

115

CS1#

79

CKE0

80

CKE1

108

RAS#

113

CAS#

109

WE#

197

SCL

195

SDA

114

ODT0

119

ODT1

1

VREF

201

GND

SKT-SODIMM200-38GP

Main Source:62.10017.E31 2nd Source: 62.10017.A41

MH2

DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6

DQS7 DQS0# DQS1# DQS2# DQS3# DQS4# DQS5# DQS6# DQS7#

DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7

CK0#

CK1#

VDD_SPD

VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD

GND

2

MH2

DDR_A_DQS0

13

DDR_A_DQS1

31

DDR_A_DQS2

51

DDR_A_DQS3

70

DDR_A_DQS4

131

DDR_A_DQS5

148

DDR_A_DQS6

169

DDR_A_DQS7

188

DDR_A_DQS#0

11

DDR_A_DQS#1

29

DDR_A_DQS#2

49

DDR_A_DQS#3

68

DDR_A_DQS#4

129

DDR_A_DQS#5

146

DDR_A_DQS#6

167

DDR_A_DQS#7

186

DDR_A_DM0

10

DDR_A_DM1

26

DDR_A_DM2

52

DDR_A_DM3

67

DDR_A_DM4

130

DDR_A_DM5

147

DDR_A_DM6

170

DDR_A_DM7

185

M_CLK_DDR0

30

CK0 CK1

SA0 SA1

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

32 164 166

198 200

199

81 82 87 88 95 96 103 104 111 112 117 118

2 3 8 9 12 15 18 21 24 27 28 33 34 39 40 41 42 47 48 53 54 59 60 65 66 71 72 77 78 121 122 127 128 132 133 138 139 144 145 149 150 155 156 161 162 165 168 171 172 177 178 183 184 187 190 193 196

202

M_CLK_DDR#0 M_CLK_DDR1 M_CLK_DDR#1

SA0

1 2

SA1

1 2

1D8V_S3

2

SB:0707 For EMI request

R37 0R0402-PADR37 0R0402-PAD R39 0R0402-PADR39 0R0402-PAD

SCD1U16V2ZY-2GP

M_CLK_DDR0 8 M_CLK_DDR#0 8

M_CLK_DDR1 8 M_CLK_DDR#1 8

SA:0428

12

C41

Title

DDRII-SODIMM SLOT1

Size Document Number Rev

Size Document Number Rev Custom

Custom

Custom Date: Sheet

Date: Sheet

M_CLK_DDR0 M_CLK_DDR#0

12

C46

C46 SC2D2U6D3V3KX-GP

SC2D2U6D3V3KX-GP

DY

1

12

C476

put near connector

M_CLK_DDR1

M_CLK_DDR#1

C388

3D3V_S0

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

DS2-Intel -1

C477

SC10P50V2JN-4GP

12

C391

SC10P50V2JN-4GP

14 47Wednesday, September 12, 2007

of

1

of

5

DDR_B_DQS#[0..7]9

DDR_B_D[0..63]9 DDR_B_DM[0..7]9 DDR_B_DQS[0..7]9

12

SC2D2U16V5ZY-2GP

C419

SCD1U16V2ZY-2GP

DDR_VREF_S0

C70

SC2D2U16V5ZY-2GP

C441

12

SCD1U16V2ZY-2GP

1 2 3 4 5

1 2 3

1 2 3 4 5

1 2 3

DDR_B_MA[0..14]9

DDR_B_BS[0..2]9

C103

12

SCD1U16V2ZY-2GP

C443

12

RN14

SRN56J-5-GP

SRN56J-5-GP RN51

RN51

SRN56J-5-GP

SRN56J-5-GP RN10

RN10

SRN56J-4-GP

RN16

SRN56J-5-GP

RN53

SRN56J-4-GP

12

SCD1U16V2ZY-2GP

DDR_B_MA14

8

DDR_B_MA6

7

DDR_B_MA2

6

DDR_B_MA4

DDR_B_MA12

8

DDR_B_MA9

7

DDR_B_MA8

6

DDR_B_MA5

DDR_B_MA13

4

M_ODT2

8

DDR_CKE3_DIMMB

7

DDR_B_MA7

6

DDR_B_MA11

DDR_CKE2_DIMMB

4

DDR_B_BS2

C78

SCD1U16V2ZY-2GP

C97

12

SCD1U16V2ZY-2GP

D D

C C

B B

A A

Layout Note: Place near DM2

1D8V_S3

C88

12

SC2D2U16V5ZY-2GP

Layout Note: Place one cap close to every 2 pullup resistors terminated to +0.9VS

DDR_VREF_S0

C86

12

SCD1U16V2ZY-2GP

DY

DDR_B_BS0 DDR_B_MA10 DDR_B_MA1 DDR_B_MA3

DDR_CS2_DIMMB# DDR_B_BS1 DDR_B_RAS# DDR_B_MA0

M_ODT3 DDR_CS3_DIMMB# DDR_B_CAS# DDR_B_WE#

5

C109

12

C64

SCD1U16V2ZY-2GP

1 2 3 4 5

12

SC2D2U16V5ZY-2GP

C113

12

SCD1U16V2ZY-2GP

RN49

SRN56J-5-GP

SRN56J-5-GP RN12

RN12

SRN56J-5-GP

SRN56J-5-GP RN47

RN47

SRN56J-5-GP

C67

12

8 7 6

12

C425

4

C108

C72

12

SC10U6D3V5KX-1GP

SCD1U16V2ZY-2GP

C74

C429

12

SCD1U16V2ZY-2GP

Layout Note: Place these resistors closely DM2,all trace length Max=1.5"

DDR_VREF_S3

4

M_ODT28

M_ODT38

DDR_VREF_S3

SCD1U16V2ZY-2GP

C499

12

3

DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_MA14

DDR_B_BS2 DDR_B_BS0

DDR_B_BS1

DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63

DDR_B_DQS#0 DDR_B_DQS#1 DDR_B_DQS#2 DDR_B_DQS#3 DDR_B_DQS#4 DDR_B_DQS#5 DDR_B_DQS#6 DDR_B_DQS#7

DDR_B_DQS0 DDR_B_DQS1 DDR_B_DQS2 DDR_B_DQS3 DDR_B_DQS4 DDR_B_DQS5 DDR_B_DQS6 DDR_B_DQS7

M_ODT2 M_ODT3

12

C503

SC2D2U16V5ZY-2GP

3

DM1

102

A0

101

A1

100

A2

99

A3

98

A4

97

A5

94

A6

92

A7

93

A8

91

A9

105

A10/AP

90

A11

89

A12

116

A13

86

A14

84

A15

85

A16/BA2

107

BA0

106

BA1

5

DQ0

7

DQ1

17

DQ2

19

DQ3

4

DQ4

6

DQ5

14

DQ6

16

DQ7

23

DQ8

25

DQ9

35

DQ10

37

DQ11

20

DQ12

22

DQ13

36

DQ14

38

DQ15

43

DQ16

45

DQ17

55

DQ18

57

DQ19

44

DQ20

46

DQ21

56

DQ22

58

DQ23

61

DQ24

63

DQ25

73

DQ26

75

DQ27

62

DQ28

64

DQ29

74

DQ30

76

DQ31

123

DQ32

125

DQ33

135

DQ34

137

DQ35

124

DQ36

126

DQ37

134

DQ38

136

DQ39

141

DQ40

143

DQ41

151

DQ42

153

DQ43

140

DQ44

142

DQ45

152

DQ46

154

DQ47

157

DQ48

159

DQ49

173

DQ50

175

DQ51

158

DQ52

160

DQ53

174

DQ54

176

DQ55

179

DQ56

181

DQ57

189

DQ58

191

DQ59

180

DQ60

182

DQ61

192

DQ62

194

DQ63

11

DQS0#

29

DQS1#

49

DQS2#

68

DQS3#

129

DQS4#

146

DQS5#

167

DQS6#

186

DQS7#

13

DQS0

31

DQS1

51

DQS2

70

DQS3

131

DQS4

148

DQS5

169

DQS6

188

DQS7

114

OTD0

119

OTD1

1

VREF

2

VSS

202

GND

MH1

SKT-SODIMM200-37GP

Main Source:62.10017.E21 2nd Source: 62.10017.A51

NC#163/TEST

RAS#

WE#

CAS# CS0#

CS1# CKE0

CKE1

CK0#

CK1#

DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7

SDA

VDDSPD

NC#50 NC#69 NC#83

NC#120

VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

GND MH2

108 109 113

110 115

79 80

30

CK0

32 164

CK1

166 10

26 52 67 130 147 170 185

195 197

SCL

199

R36 0R0402-PADR36 0R0402-PAD

198

SA0

R38 10KR2J-3-GPR38 10KR2J-3-GP

200

SA1

50 69 83 120 163

81 82 87 88 95 96 103 104 111 112 117 118

3 8 9 12 15 18 21 24 27 28 33 34 39 40 41 42 47 48 53 54 59 60 65 66 71 72 77 78 121 122 127 128 132 133 138 139 144 145 149 150 155 156 161 162 165 168 171 172 177 178 183 184 187 190 193 196

201 MH2

2

DDR_B_RAS# DDR_B_WE# DDR_B_CAS#

DDR_CS2_DIMMB# DDR_CS3_DIMMB#

DDR_CKE2_DIMMB DDR_CKE3_DIMMB

M_CLK_DDR2 M_CLK_DDR#2

M_CLK_DDR3 M_CLK_DDR#3

DDR_B_DM0 DDR_B_DM1 DDR_B_DM2 DDR_B_DM3 DDR_B_DM4 DDR_B_DM5 DDR_B_DM6 DDR_B_DM7

ICH_SMBDATA ICH_SMBCLK

1 2 1 2

1D8V_S3

2

1

M_CLK_DDR2 M_CLK_DDR#2

C175

DDR_B_RAS# 9

DDR_B_WE# 9

DDR_B_CAS# 9 DDR_CS2_DIMMB# 8

DDR_CS3_DIMMB# 8

DDR_CKE2_DIMMB 8

DDR_CKE3_DIMMB 8 M_CLK_DDR2 8

M_CLK_DDR#2 8 M_CLK_DDR3 8

M_CLK_DDR#3 8

ICH_SMBDATA 4,14,21

ICH_SMBCLK 4,14,21

SA:0428

PM_EXTTS#1 8

SB:0707 For EMI request

C44

3D3V_S0

Title

Size Document Number Rev

Size Document Number Rev Custom

Custom

Custom Date: Sheet

Date: Sheet

C44

SCD1U16V2ZY-2GP

DDRII-SODIMM SLOT2

C175

SC10P50V2JN-4GP

put near connector

M_CLK_DDR3 M_CLK_DDR#3

C50

3D3V_S0

12

C38

C38 SC2D2U6D3V3KX-GP

SC2D2U6D3V3KX-GP

DY

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

DS2-Intel -1

1

C174

12

SC10P50V2JN-4GP

12

C51

SC10P50V2JN-4GP

of

15 47Wednesday, September 12, 2007