Dell Inspiron 11 3179 Schematics

5

D D

4

3

2

1

Drax 11.6" Schematic

SKL-Y

C C

2016-03-21 REV : A00

B B

DY : None Installed

Wistron Corporation

A A

Title

Cover Page

Size Document Number Rev

A4

Date: Sheet of

5

4

3

Date: Sheet of

2

Cover Page

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Drax SKL Y

1 109Monday, March 21, 2016

1

A00

5

Project code : 4PD06Q010001 PCB P/N : 15250 Revision : A00

D D

LCD 11.6"

11.6 HD (1366 x 768)

11.6 FHD (Drax)

Touch Panel

HDMI 1.4a

55

57

USB1(USB3.0 )

Card reader

RealTek RTS5227S

35, 36

C C

Micro-SD

HDD

SPI Flash

B B

16MB Qual Read

Drax 11.6" Block Diagram

eDP

USB2.0 x 1

HDMI

USB3.0 x 1

USB2.0 x 1

PCIe x 1

33

SATA(Gen3) x 1

60

SPI

25

4

ETHERNET (10/100/1000Mb)

I2C

Intel CPU

Skylake-Y BGA1515

USB 3.0/2.0 ports (6)

High Definition Audio

SATA ports (2) PCIe ports (5)

LPC I/F

4,5,6,7,8,9,10, 11,15,16,18,19,20,21

ISH

DDR3L Channel A

DDR3L Channel B

PCIe x 1 Port5

USB2.0 x 1 Port9

USB2.0 x 1 Port7

HD Audio

USB2.0 x 1

I2C

3

NGFF WLAN & BT combo module

HD Audio Codec

USB 2.0 HUB1

2.0 ports(4)

AU6259661

37

DDR3L Memory Down

61

Camera(HD)

55

D-MIC

RealTek ALC3246

27

USB2.0 x 1

Drax IO Board

12(2GB 4*16*256M)

13(2GB 4*16*256M)

29

USB2(USB2.0)

USB3(USB2.0)

Sensor Hub

ST

STM32L151CBU6TR-GP

2CH SPEAKER

Combo Jack

2

1

CHARGER

BQ24727RGRR

INPUTS

19V_DCBATOUT

SYSTEM DC/DC

SY8288CRAC SY8286BRAC

INPUTS

19V_DCBATOUT

CPU Core Power

NCP81208MNTXG NCP81381MNTXG *2 SY8288RAC NCP81253MNTBG

INPUTS

19V_DCBATOUT

DDR3L SUS

SY8288RAC APL5338XAI

OUTPUTS

12V_BT+

OUTPUTS

3D3V_AUX_S5

5V_PWR_2

5V_S5

3D3V_S5

OUTPUTS

+VCC_CORE

+VCCGT

1D0V_S5

+VCCSA

INPUTS OUTPUTS

19V_DCBATOUT

1D35V_S3

0D675V_S0

44

45

46-50

51

SYSTEM DC/DC

APL5930KAI

INPUTS OUTPUTS

Drax Sensor Board

53

1D8V_S53D3V_S5

PCB LAYER

Gyro +G Sensor

LSM6DS3USTR

I2C

E-compass

LIS3MDLTR

Free Fall Sensor + G Sensor

ST LNG2DMTR

70

L1:Top L2:Signal L3:GND L4:Signal

L5:Signal L6:GND L7:Signal L8:Bottom

Touch PAD

PS2

65

SPI

LPC BUS

SMBus

KBC

Int. KB

65

A A

5

NUVOTON NPCE285

4

SMBus

24

LPC debug port

Thermal

NUVOTON NCT7718W

Charger

TI BQ24727RGRR

3

68

26

44

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

C

Date: Sheet of

2

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

Block Diagram

Drax SKL Y

1

A00

2 109Tuesday, March 22, 2016

A00

5

D

C

B

A

D

C

4

3

2

1

Blanking

B

Wistron Corporation

A

Title

Reserved

Size Document Number Rev

A4

Date: Sheet of

Reserved

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Drax SKL Y

3 109Thursday, March 17, 2016

A00

D

C

B

A

SSID = CPU

5

+VCCSTG

4

3

2

1

D

C

B

+VCCST_CPU

R429

R429 1KR2J-1-GP

1KR2J-1-GP

1 2

THERMTRIP#_CPU_R

12

EC401

DY

AZ5725-01FDR7G-GP

INT_TP#[24,65]

3D3V_S5_PCH

1 2

100KR2J-1-GP

3D3V_S0

100KR2J-1-GP

1 2

100KR2J-1-GP

NON DS3

0R0402-PAD-1-GP

A00 20160302

DS3

K A

1 2

R427 1KR2J-1-GPR427 1KR2J-1-GP

R404

DY

R406

DS3

R410

1 2

D401

D401 RB751V-40H-GP

RB751V-40H-GP

83.R2004.G8F

H_PROCHOT#

H_PROCHOT#[24,44,46]

BPM_CPU_N0[99] BPM_CPU_N1[99]

H_PECI[24]

[PECI] and [PROCHOT#] Impedance control: 50 ohm

CATERR#_CPU

TP417TP417

TP416TP416

TP415TP415

TP414TP414

TOUCHPAD_INTR#

1

R415499R2F-2-GP R415499R2F-2-GP

1 2

R42160D4R2F-GP R42160D4R2F-GP

1 2

1

1 1

R42249D9R2F-GP R42249D9R2F-GP

1 2

R42849D9R2F-GP R42849D9R2F-GP

1 2

PROCHOT#_CPU THERMTRIP#_CPU SKTOCC#_CPU

BPM_CPU_N0 BPM_CPU_N1 BPM_CPU_N2 BPM_CPU_N3

CPU_POPIRCOMP PCH_POPIRCOMP

Add resistor by NON DS3 function

CPU1D

H49

CATERR#

F49

PECI

J48

PROCHOT#

H47

THERMTRIP#

B62

SKTOCC#

H51

BPM#[0]

J50

BPM#[1]

F51

BPM#[2]

G50

BPM#[3]

E11

GPP_E3/CPU_GP0

M9

GPP_E7/CPU_GP1

BD8

GPP_B3/CPU_GP2

BC11

GPP_B4/CPU_GP3

BN17

PROC_POPIRCOMP

BP16

PCH_OPIRCOMP

SKYLAKE-Y-GP

SKYLAKE_ULX

JTAG

CPU MISC

071.SKYLA.0C0U

PV stage CPU

PCH_JTAG_TMS

PCH_JTAG_TDI

XDP_TCK_JTAGX

PCH_JTAG_TDO

PCH_JTAG_TCK

4 OF 20

PROC_TCK

PROC_TDI PROC_TDO PROC_TMS

PROC_TRST#

PCH_JTAG_TCK

PCH_JTAG_TDI PCH_JTAG_TDO PCH_JTAG_TMS

PCH_TRST#

JTAGX

+VCCSTG +VCCSTG

1 2

R438 51R2J-2-GPR438 51R2J-2-GP

1 2

R439 51R2J-2-GPR439 51R2J-2-GP

1 2

DY

R430 1KR2J-1-GP

1 2

R440 51R2J-2-GPR440 51R2J-2-GP

1 2

DY

R437 51R2J-2-GP

D53 C54 G48 C59 F47

B53 C50 B51 A52 C52 B49

XDP_TMS_CPU

XDP_TDI_CPU

XDP_TDO_CPU

XDP_TCK_CPU

XDP_TRST#_CPU

XDP_TCK_CPU [99] XDP_TDI_CPU [99] XDP_TDO_CPU [99] XDP_TMS_CPU [99] XDP_TRST#_CPU [99]

PCH_JTAG_TCK [99] PCH_JTAG_TDI [99] PCH_JTAG_TDO [99] PCH_JTAG_TMS [99] XDP_TRST#_CPU [99] XDP_TCK_JTAGX [99]

1 2

DY

R433 51R2J-2-GP

1 2

DY

R434 51R2J-2-GP

1 2

DY

R435 51R2J-2-GP

1 2

R431 51R2J-2-GPR431 51R2J-2-GP

1 2

DY

R436 51R2J-2-GP

Wistron Corporation

A

Title

CPU_(JTAG/CPU SIDE BAND)

Size Document Number Rev

Date: Sheet of

CPU_(JTAG/CPU SIDE BAND)

A4

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Drax SKL Y

4 109Thursday, March 17, 2016

A00

5

4

3

2

1

SSID = CPU

3 OF 20

CPU1C

NC#1 A GND3Y

DY

R506

1 2

DY

0R2J-2-GP

CPU1C

BC41

DDR0_DQ[32]/DDR1_DQ[0]

BC39

DDR0_DQ[33]/DDR1_DQ[1]

BG41

DDR0_DQ[34]/DDR1_DQ[2]

BE39

DDR0_DQ[35]/DDR1_DQ[3]

BF42

DDR0_DQ[36]/DDR1_DQ[4]

BD42

DDR0_DQ[37]/DDR1_DQ[5]

BG39

DDR0_DQ[38]/DDR1_DQ[6]

BE41

DDR0_DQ[39]/DDR1_DQ[7]

BC43

DDR0_DQ[40]/DDR1_DQ[8]

BD46

DDR0_DQ[41]/DDR1_DQ[9]

BG43

DDR0_DQ[42]/DDR1_DQ[10]

BG45

DDR0_DQ[43]/DDR1_DQ[11]

BC45

DDR0_DQ[44]/DDR1_DQ[12]

BE43

DDR0_DQ[45]/DDR1_DQ[13]

BE45

DDR0_DQ[46]/DDR1_DQ[14]

BF46

DDR0_DQ[47]/DDR1_DQ[15]

BM28

DDR1_DQ[32]/DDR1_DQ[16]

BN27

DDR1_DQ[33]/DDR1_DQ[17]

BK28

DDR1_DQ[34]/DDR1_DQ[18]

BL25

DDR1_DQ[35]/DDR1_DQ[19]

BN25

DDR1_DQ[36]/DDR1_DQ[20]

BL27

DDR1_DQ[37]/DDR1_DQ[21]

BJ25

DDR1_DQ[38]/DDR1_DQ[22]

BJ27

DDR1_DQ[39]/DDR1_DQ[23]

BM24

DDR1_DQ[40]/DDR1_DQ[24]

BK24

DDR1_DQ[41]/DDR1_DQ[25]

BN21

DDR1_DQ[42]/DDR1_DQ[26]

BJ23

DDR1_DQ[43]/DDR1_DQ[27]

BL23

DDR1_DQ[44]/DDR1_DQ[28]

BN23

DDR1_DQ[45]/DDR1_DQ[29]

BJ21

DDR1_DQ[46]/DDR1_DQ[30]

BL21

DDR1_DQ[47]/DDR1_DQ[31]

BN45

DDR0_DQ[48]/DDR1_DQ[32]

BM46

DDR0_DQ[49]/DDR1_DQ[33]

BL43

DDR0_DQ[50]/DDR1_DQ[34]

BK46

DDR0_DQ[51]/DDR1_DQ[35]

BN43

DDR0_DQ[52]/DDR1_DQ[36]

BL45

DDR0_DQ[53]/DDR1_DQ[37]

BJ45

DDR0_DQ[54]/DDR1_DQ[38]

BJ43

DDR0_DQ[55]/DDR1_DQ[39]

BM42

DDR0_DQ[56]/DDR1_DQ[40]

BN41

DDR0_DQ[57]/DDR1_DQ[41]

BJ41

DDR0_DQ[58]/DDR1_DQ[42]

BN39

DDR0_DQ[59]/DDR1_DQ[43]

BK42

DDR0_DQ[60]/DDR1_DQ[44]

BL41

DDR0_DQ[61]/DDR1_DQ[45]

BL39

DDR0_DQ[62]/DDR1_DQ[46]

BJ39

DDR0_DQ[63]/DDR1_DQ[47]

BF28

DDR1_DQ[48]

BD28

DDR1_DQ[49]

BG25

DDR1_DQ[50]

BC27

DDR1_DQ[51]

BG27

DDR1_DQ[52]

BE27

DDR1_DQ[53]

BE25

DDR1_DQ[54]

BC25

DDR1_DQ[55]

BF24

DDR1_DQ[56]

BD24

DDR1_DQ[57]

BG21

DDR1_DQ[58]

BC23

DDR1_DQ[59]

BE23

DDR1_DQ[60]

BG23

DDR1_DQ[61]

BC21

DDR1_DQ[62]

BE21

DDR1_DQ[63]

SKYLAKE-Y-GP

5

VCC

DDR_VTT_P G_CTRL_R

4

1D0V_S5

R509

1 2

DY

0R2J-2-GP

SKYLAKE_ULX

DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[ 5] DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[ 9] DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[ 6] DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[ 8] DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[ 7]

DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0] DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[ 12] DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[ 11]

DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT # DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1]

DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[ 13]

DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15]

DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14]

DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16]

DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[4]

DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[ 2]

DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1]

DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[ 10]

DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[ 1] DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[ 0]

DDR CH - B

C501

SCD1U10V1KX-GP

12

3D3V_S0

DY

12

DY

DDR0_DQSN[4]/DDR1_DQSN[0]

DDR0_DQSP[4]/DDR1_DQSP[0]

DDR0_DQSN[5]/DDR1_DQSN[1]

DDR0_DQSP[5]/DDR1_DQSP[1]

DDR1_DQSN[4]/DDR1_DQSN[2]

DDR1_DQSP[4]/DDR1_DQSP[2]

DDR1_DQSN[5]/DDR1_DQSN[3]

DDR1_DQSP[5]/DDR1_DQSP[3]

DDR0_DQSN[6]/DDR1_DQSN[4]

DDR0_DQSP[6]/DDR1_DQSP[4]

DDR0_DQSN[7]/DDR1_DQSN[5]

DDR0_DQSP[7]/DDR1_DQSP[5]

R505

R505 220KR2J-L2-GP

220KR2J-L2-GP

2 OF 20

CPU1B

M_A_DQ[63:0][12]

D D

C C

B B

M_A_DQ[63:0]

M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63

CPU1B

AG61

DDR0_DQ[0]

AH60

DDR0_DQ[1]

AK62

DDR0_DQ[2]

AK60

DDR0_DQ[3]

AH62

DDR0_DQ[4]

AG63

DDR0_DQ[5]

AL61

DDR0_DQ[6]

AL63

DDR0_DQ[7]

AM60

DDR0_DQ[8]

AM62

DDR0_DQ[9]

AT60

DDR0_DQ[10]

AR61

DDR0_DQ[11]

AN61

DDR0_DQ[12]

AN63

DDR0_DQ[13]

AR63

DDR0_DQ[14]

AT62

DDR0_DQ[15]

AT56

DDR1_DQ[0]/DDR0_DQ[16]

AR55

DDR1_DQ[1]/DDR0_DQ[17]

AN57

DDR1_DQ[2]/DDR0_DQ[18]

AN55

DDR1_DQ[3]/DDR0_DQ[19]

AR57

DDR1_DQ[4]/DDR0_DQ[20]

AT58

DDR1_DQ[5]/DDR0_DQ[21]

AM58

DDR1_DQ[6]/DDR0_DQ[22]

AM56

DDR1_DQ[7]/DDR0_DQ[23]

AL55

DDR1_DQ[8]/DDR0_DQ[24]

AL57

DDR1_DQ[9]/DDR0_DQ[25]

AH58

DDR1_DQ[10]/DDR0_DQ[26]

AH56

DDR1_DQ[11]/DDR0_DQ[27]

AK58

DDR1_DQ[12]/DDR0_DQ[28]

AK56

DDR1_DQ[13]/DDR0_DQ[29]

AG55

DDR1_DQ[14]/DDR0_DQ[30]

AG57

DDR1_DQ[15]/DDR0_DQ[31]

BE55

DDR0_DQ[16]/DDR0_DQ[32]

BC55

DDR0_DQ[17]/DDR0_DQ[33]

BG53

DDR0_DQ[18]/DDR0_DQ[34]

BE53

DDR0_DQ[19]/DDR0_DQ[35]

BC53

DDR0_DQ[20]/DDR0_DQ[36]

BG55

DDR0_DQ[21]/DDR0_DQ[37]

BD52

DDR0_DQ[22]/DDR0_DQ[38]

BF52

DDR0_DQ[23]/DDR0_DQ[39]

BC51

DDR0_DQ[24]/DDR0_DQ[40]

BE51

DDR0_DQ[25]/DDR0_DQ[41]

BC49

DDR0_DQ[26]/DDR0_DQ[42]

BE49

DDR0_DQ[27]/DDR0_DQ[43]

BG51

DDR0_DQ[28]/DDR0_DQ[44]

BG49

DDR0_DQ[29]/DDR0_DQ[45]

BF48

DDR0_DQ[30]/DDR0_DQ[46]

BD48

DDR0_DQ[31]/DDR0_DQ[47]

BJ55

DDR1_DQ[16]/DDR0_DQ[48]

BL55

DDR1_DQ[17]/DDR0_DQ[49]

BJ53

DDR1_DQ[18]/DDR0_DQ[50]

BL53

DDR1_DQ[19]/DDR0_DQ[51]

BN55

DDR1_DQ[20]/DDR0_DQ[52]

BN53

DDR1_DQ[21]/DDR0_DQ[53]

BM52

DDR1_DQ[22]/DDR0_DQ[54]

BK52

DDR1_DQ[23]/DDR0_DQ[55]

BL51

DDR1_DQ[24]/DDR0_DQ[56]

BJ51

DDR1_DQ[25]/DDR0_DQ[57]

BL49

DDR1_DQ[26]/DDR0_DQ[58]

BJ49

DDR1_DQ[27]/DDR0_DQ[59]

BN49

DDR1_DQ[28]/DDR0_DQ[60]

BN51

DDR1_DQ[29]/DDR0_DQ[61]

BK48

DDR1_DQ[30]/DDR0_DQ[62]

BM48

DDR1_DQ[31]/DDR0_DQ[63]

SKYLAKE-Y-GP

SKYLAKE_ULX

DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[ 5] DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[ 9] DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[ 6] DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[ 8] DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[ 7]

DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0] DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[ 12] DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[ 11]

DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT # DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1]

DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[ 13]

DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15]

DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14]

DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16]

DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0]

DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[ 2]

DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1] DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[ 10]

DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[ 1] DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[ 0]

DDR1_DQSN[0]/DDR0_DQSN[2] DDR1_DQSP[0]/DDR0_DQSP[2] DDR1_DQSN[1]/DDR0_DQSN[3] DDR1_DQSP[1]/DDR0_DQSP[3] DDR0_DQSN[2]/DDR0_DQSN[4] DDR0_DQSP[2]/DDR0_DQSP[4] DDR0_DQSN[3]/DDR0_DQSN[5] DDR0_DQSP[3]/DDR0_DQSP[5] DDR1_DQSN[2]/DDR0_DQSN[6] DDR1_DQSP[2]/DDR0_DQSP[6] DDR1_DQSN[3]/DDR0_DQSN[7] DDR1_DQSP[3]/DDR0_DQSP[7]

DDR CH - A

2 OF 20

DDR0_CKN[0] DDR0_CKP[0] DDR0_CKN[1] DDR0_CKP[1]

DDR0_CKE[0] DDR0_CKE[1] DDR0_CKE[2] DDR0_CKE[3]

DDR0_CS#[0] DDR0_CS#[1] DDR0_ODT[0]

DDR0_MA[3] DDR0_MA[4]

DDR0_DQSN[0] DDR0_DQSP[0] DDR0_DQSN[1] DDR0_DQSP[1]

DDR0_ALERT#

DDR0_PAR

DDR_VREF_CA DDR0_VREF_DQ DDR1_VREF_DQ

DDR_VTT_CNTL

M_A_DQS#0 M_A_DQS#1 M_A_DQS#2 M_A_DQS#3 M_A_DQS#4 M_A_DQS#5 M_A_DQS#6 M_A_DQS#7

M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6 M_A_DQS7

M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8

M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14 M_A_A15

BC62 BC60 BA60 BA62

BB57 BC58 BE57 AW61

AW63 BJ57 BN61

AW59 AW55 BF62 AV56 AW57 AV58 BA56 BD59 BD61 BG61

BK59 BL62 BJ61 AV60 BN62 BB61 BL61 BM59 BN58 AV62

BB63 BL57

AJ61 AJ63 AP62 AP60 AP56 AP58 AJ57 AJ55 BD54 BF54 BF50 BD50 BM54 BK54 BK50 BM50

BG57 BM56

AR53 AN53 AW53

BN47

TP_M_A_DIMA_ODT 0

M_A_A5 M_A_A9 M_A_A6 M_A_A8 M_A_A7

M_A_A12 M_A_A11 M_A_A15 M_A_A14

M_A_A13

M_A_A2

M_A_A10

M_A_A1 M_A_A0

M_A_A3 M_A_A4

M_A_DQS#0 M_A_DQS0 M_A_DQS#1 M_A_DQS1 M_A_DQS#2 M_A_DQS2 M_A_DQS#3 M_A_DQS3 M_A_DQS#4 M_A_DQS4 M_A_DQS#5 M_A_DQS5 M_A_DQS#6 M_A_DQS6 M_A_DQS#7 M_A_DQS7

DDR_VTT_C TRL

M_A_DIMA_CLK_DD R#0 [12] M_A_DIMA_CLK_DD R0 [12]

M_A_DIMA_CKE0 [12] M_A_DIMA_CKE1 [12]

M_A_DIMA_CS#0 [12] M_A_DIMA_CS#1 [12]

M_A_BS2 [12]

M_A_CAS# [12] M_A_WE# [12] M_A_RAS# [12]

M_A_BS0 [12] M_A_BS1 [12]

+V_SM_VREF_C NT [42] DDR_W R_VREF01 [42] DDR_W R_VREF02 [42]

M_A_A[15:0] [12]

M_A_DQS#[7:0] [12]

M_A_DQS[7:0] [12]

M_B_DQ[63:0][13]

1

TP501TP501

DDR_VTT_C TRL

M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63

U501

R507

1 2

DY

1KR2J-1-GP

DDR_VTT_C TRL_R

U501

1 2

74AUP1G07GW -GP

VccST_PWRGD assertion to DDR_VTT_CNTL asserted within 100ns.

3 OF 20

DDR1_CKN[0] DDR1_CKP[0] DDR1_CKN[1] DDR1_CKP[1]

DDR1_CKE[0] DDR1_CKE[1] DDR1_CKE[2] DDR1_CKE[3]

DDR1_CS#[0] DDR1_CS#[1] DDR1_ODT[0]

DDR1_MA[3] DDR1_MA[4]

DDR1_DQSN[6] DDR1_DQSP[6] DDR1_DQSN[7] DDR1_DQSP[7]

DDR1_ALERT#

DDR1_PAR

DRAM_RESET#

DDR_RCOMP[0] DDR_RCOMP[1] DDR_RCOMP[2]

DRAM_RESET #

DDR_VTT_P G_CTRL [51]

BK36 BM36 BD32 BF32

BN33 BK32 BG33 BH30

BM30 BJ33

TP_M_B_DIMB_ODT 0

BC35 BK30

BN31 BM32 BL37 BG31 BN37 BJ37 BJ35 BM34 BN35

BG37 BE37 BC37 BF34 BC33 BF30 BD36 BG35 BC31 BF36

BJ31 BK34

M_B_DQS#0

BD40

M_B_DQS0

BF40

M_B_DQS#1

BD44

M_B_DQS1

BF44

M_B_DQS#2

BK26

M_B_DQS2

BM26

M_B_DQS#3

BM22

M_B_DQS3

BK22

M_B_DQS#4

BK44

M_B_DQS4

BM44

M_B_DQS#5

BM40

M_B_DQS5

BK40

M_B_DQS#6

BD26

M_B_DQS6

BF26

M_B_DQS#7

BF22

M_B_DQS7

BD22 BD34

DDR1_PAR

BD30

DRAM_RESET #

BP20

SM_RCOMP_0

BF64

SM_RCOMP_1

BJ64

SM_RCOMP_2

BC64

W/S= 15/25 mils. Lmax=500 mils.

1D35V_S3

12

R504

R504 470R2F-GP

470R2F-GP

A00 20160302

M_B_A5 M_B_A9 M_B_A6 M_B_A8 M_B_A7

M_B_A12 M_B_A11 M_B_A15 M_B_A14

M_B_A13

M_B_A2

M_B_A10

M_B_A1 M_B_A0

M_B_A3 M_B_A4

1

R501 200R2F-L-GPR501 200R2F-L-GP R502 80D6R2F-L-G PR502 80D6R2F-L- GP R503 100R2F-L1-GP- UR503 100R2F-L1-GP-U

R508

1 2

0R0402-PAD-1- GP

DY

M_B_DIMB_CLK_DD R#0 [13] M_B_DIMB_CLK_DD R0 [13]

M_B_DIMB_CKE0 [13] M_B_DIMB_CKE1 [13]

M_B_DIMB_CS#0 [13] M_B_DIMB_CS#1 [13]

M_B_BS2 [13]

M_B_CAS# [13] M_B_WE# [13] M_B_RAS# [13]

M_B_BS0 [13] M_B_BS1 [13]

TP503 TPAD14-OP-G PTP503 TPAD14-OP-G P

1 2 1 2 1 2

C502

SCD1U10V1KX-GP

12

CLose to CPU

1

TP502TP502

DDR3_DR AMRST# [12,13]

ED501

ED501 AZ5725-01FDR 7G-GP

AZ5725-01FDR 7G-GP

A00 20160303

83.05725.0A0

M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8

M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14 M_B_A15

M_B_DQS#0 M_B_DQS#1 M_B_DQS#2 M_B_DQS#3 M_B_DQS#4 M_B_DQS#5 M_B_DQS#6 M_B_DQS#7

M_B_DQS0 M_B_DQS1 M_B_DQS2 M_B_DQS3 M_B_DQS4 M_B_DQS5 M_B_DQS6 M_B_DQS7

M_B_A[15:0] [13]

M_B_DQS#[7:0] [13]

M_B_DQS[7:0] [13]

A A

Wistron Corporation

21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih,

21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih, Taipei Hsie n 221, Taiwan, R.O.C .

Taipei Hsie n 221, Taiwan, R.O.C .

Title

Size Document Num ber Rev

A2

Date: Sheet of

5

4

3

2

Date: Sheet of

Taipei Hsie n 221, Taiwan, R.O.C .

CPU(DDR)

Drax SKL Y

1

A00

5 109Monday, March 21, 2016

A00

5

4

3

2

1

SSID = CPU

20 OF 20

CPU1T

SKYLAKE_ULX

CFG[19:0][99]

D D

R601

1 2

C C

B B

ITP_PMODE[99]

CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15

CFG16 CFG17

CFG18 CFG19

49D9R2F-GP

CFG_RCOMP

G52

F53

J52 H53 H55 D55 C56

F55 D61 G58 D57

F61

J60

J58 H61 H59

J54 G54

G56

J56

A54 A60

B4 B3

F3 F1

L36 L38

BA19 BB18

BC19 BD18

D49 M21

L20

M19

L26

CFG[0] CFG[1] CFG[2] CFG[3] CFG[4] CFG[5] CFG[6] CFG[7] CFG[8] CFG[9] CFG[10] CFG[11] CFG[12] CFG[13] CFG[14] CFG[15]

CFG[16] CFG[17]

CFG[18] CFG[19]

CFG_RCOMP ITP_PMODE RSVD#B4

RSVD#B3 RSVD#F3

RSVD#F1 RSVD#L36

RSVD#L38 RSVD#BA19

RSVD#BB18 RSVD#BC19

RSVD#BD18 RSVD#D49

RSVD#M21 RSVD#L20 RSVD#M19

RSVD#L26

SKYLAKE_ULX

RESERVED SIGNALS

PCH strap pin:

SKYLAKE-Y-GP

CFG4

R602

R602 1KR2J-1-GP

1KR2J-1-GP

1 2

DISPLAY PORT PRESENCE STRAP

0 : ENABLED

CFG[4]

AN EXTERNAL DISPLAY PORT DEVICE IS CONNECTED TO THE EMBEDDED DISPLAY PORT 1 : DISABLED

NO PHYSICAL DISPLAY PORT ATTACHED TO EMBEDDED DISPLAY PORT

20 OF 20

RSVD_TP#BL64

RSVD_TP#BG47

RSVD_TP#BA17 RSVD_TP#AY18

RSVD#BF18 RSVD#BE19

TP5 TP6

RSVD#R12 RSVD#P13

RSVD#M15

RSVD#L16 RSVD#L18

RSVD#M17 RSVD#AH7

RSVD#K12 RSVD#H12

RSVD#BN3 RSVD#BP3

RSVD#L22

RSVD#M23

TP4

RSVD#AY20 RSVD#BA21

RSVD#BB14

RSVD#M25

RSVD#L24 RSVD#L28

RSVD#M27

TP1 TP2

BL64 BG47

BA17 AY18

BF18 BE19

BA23 AY22

R12 P13 M15 L16

L18 M17

AH7 K12

H12 BN3

BP3 L22

M23 BN1 AY20

BA21 BB14 M25

L24 L28

M27 BJ15

BJ17

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

A A

SKL(#543016): Processor strap CFG[4] should be pulled low to enable embedded DisplayPort*

5

4

3

Title

CPU (CFG/RSVD)

Size Document Number Rev

A4

Date: Sheet of

2

CPU (CFG/RSVD)

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Drax SKL Y

6 109Thursday, March 17, 2016

A00

1

5

SSID = CPU

+VCC_COR E

D D

C C

AE32 AE40 AH41 AN32 AT33 AT41

AA32 AE33 AE41 AK32 AN41 AT35

AA41 AE35 AF32 AK41 AR32 AT36

A64

J64

L48 M33 M43 M53 M64

N40

N59

P60

R57

T41

B64

L40

L50 M35 M45 M56

N32

N42

N61

P62

R59

V32

D64

L42

L52 M37 M47

R63

P56

R32

Y32

CPU1L

VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC

SKYLAKE-Y-GP

SKYLAKE_ULX

CPU POWER 1 OF 4

Icc max 16A

12 OF 20

VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC

VCC_SENSE VSS_SENSE

VIDALERT#

VIDSCK

VIDSOUT

VCCSTG VCCSTG

M58 N34 N54 N63 P64 R61 V41 AC41 AE38 AH32 AL41 AT32 AT40 H63 L46 L63 M41 M51 M62 N38 N57 P58 R41 T32 Y41 AC32 AE36 AF41 AL32 AR41 AT38 F64 L44 L54 M39 M49 M60 N36 N55

L34 L32

B58 A56 A58

AA26 AC26

VCC_SENSE VSS_SENSE

VIDALERT#_CPU

2.09A

1D35V_S3

A00 20160302

12

R724

0R0402-PAD-1-GP

B B

+VDDQC

0.12A

+VCCST_CP U

0.16A

+VCCSTG

0.35A

+VCCPLL_OC

+VCCPLL

AH64 BA27 BA37 BA49 BP32 BP50 AK64 BA29 BA41 BA51 BP34 BP56 AT64 BA31 BA43 BN64 BP40 BP58 AV64 BA33 BA45 BP24 BP42 BP64 BA25 BA35 BA47 BP26 BP48 BA39

AE27 AF27

R26

R27

V26 Y26

T26

T27

CPU1N

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQC

VCCST VCCST

VCCSTG VCCSTG

VCCPLL_OC VCCPLL_OC

VCCPLL VCCPLL

CPU POWER 3 OF 4

SKYLAKE_ULX

VCCIO_DDR VCCIO_DDR VCCIO_DDR VCCIO_DDR VCCIO_DDR VCCIO_DDR VCCIO_DDR VCCIO_DDR VCCIO_DDR VCCIO_DDR VCCIO_DDR VCCIO_DDR VCCIO_DDR VCCIO_DDR VCCIO_DDR VCCIO_DDR VCCIO_DDR VCCIO_DDR VCCIO_DDR VCCIO_DDR VCCIO_DDR VCCIO_DDR VCCIO_DDR VCCIO_DDR VCCIO_DDR VCCIO_DDR

VCCIO_SENSE

VSSIO_SENSE

4

+VCC_COR E

Layout Notes:

1. Place close to CPU within 2"

2. VCC_SENSE/VSS_SENSE impedance=50 ohm

3. Length match<25mil

+VCC_COR E

12

R707

R707 100R2F-L1-GP- U

100R2F-L1-GP- U

VCC_SENSE [46] VSS_SENSE [46]

12

R706

R706 100R2F-L1-GP- U

100R2F-L1-GP- U

R701 220R2J-L2-GPR701 220R2J-L2-GP

1 2

VIDSCK_CPU [46] VIDSOUT_CPU [46]

+VCCSTG

+VCCST_CP U

1 2

56R2F-1-GP

1 2

56R2F-1-GP

1 2

100R2F-L1-GP- U

2.39A

+VCCIO

DY

VIDALERT#_CPU _R

1 1

14 OF 20

VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO

AC23 AF24 AN26 AC24 AF26 AR26 AE23 AH26 AT26 AE24 AK26 AE26 AL26

AV26 AV36 AV46 AW31 AW41 AW51 AV28 AV38 AV48 AW33 AW43 AV30 AV40 AV50 AW35 AW45 AV32 AV42 AW27 AW37 AW47 AV34 AV44 AW29 AW39 AW49

AT24 AR24

R727

R725

R726

VCCIO_SENSE VSSIO_SENSE

VIDALERT#_CPU _R [46]

PH at VR side

VIDSCK_CPU

VIDSOUT_CPU

TP701TP701 TP702TP702

Icc max 2A

CPU1M

AA53

VCCGT

AB62

VCCGT

AC47

VCCGT

AC55

VCCGT

AD54

VCCGT

AD64

VCCGT

AE61

VCCGT

AF47

VCCGT

AJ53

VCCGT

AK49

VCCGT

AN46

VCCGT

AT43

VCCGT

AT50

VCCGT

N50

VCCGT

T46

VCCGT

T54

VCCGT

U61

VCCGT

V60

VCCGT

W57

VCCGT

Y44

VCCGT

Y51

VCCGT

Y62

VCCGT

AB54

VCCGT

AB64

VCCGT

AC49

VCCGT

AC57

VCCGT

AD56

VCCGT

AE53

VCCGT

AE63

VCCGT

AF49

VCCGT

AK43

VCCGT

AK50

VCCGT

AN47

VCCGT

AT44

VCCGT

AT51

VCCGT

R51

VCCGT

T47

VCCGT

U53

VCCGT

U63

VCCGT

V62

VCCGT

W59

VCCGT

Y46

VCCGT

Y54

VCCGT

Y64

VCCGT

AB58

VCCGT

AC44

VCCGT

AC51

VCCGT

AC61

VCCGT

AD60

VCCGT

AE57

VCCGT

AF44

VCCGT

AF51

VCCGT

AK46

VCCGT

AB60

VCCGT

AC46

VCCGT

SKYLAKE-Y-GP

Put cap. underneath the CPU

C702

12

SCD1U6D3V1KX-GP

+VCCSTG +VCCPLL+VCCST_CPU +VCCPLL_OC

C703

12

SCD1U6D3V1KX-GP

+VDDQC

C701

SCD1U6D3V1KX-GP

12

3

CPU POWER 2 OF 4

C704

12

SCD1U6D3V1KX-GP

SKYLAKE_ULX

C705

12

13 OF 20

VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT

VCCGT_SENSE VSSGT_SENSE

SCD1U6D3V1KX-GP

AC53 AC63 AD62 AE59 AF46 AG53 AK47 AN44 AN51 AT49 N48 T44 T51 U59 V58 W55 Y43 Y50 Y60 AB56 AC43 AC50 AC59 AD58 AE55 AF43 AF50 AK44 AK51 AN49 AT46 N44 R53 T49 U55 V54 V64 W61 Y47 Y56 AN50 AT47 N46 T43 T50 U57 V56 W53 W63 Y49 Y58 AN43

N52 P52

2

+VCCGT+VCCGT

+VCCSA

+VCCGT

12

R702

R702 100R2F-L1-GP- U

100R2F-L1-GP- U

VCCGT_SEN SE [46] VSSGT_SENSE [46]

12

R703

R703 100R2F-L1-GP- U

100R2F-L1-GP- U

Icc max 4.1A

CPU1O

AA29

VCCSA

AF30

VCCSA

AN29

VCCSA

L30

VCCSA

T30

VCCSA

AC29

VCCSA

AH29

VCCSA

AN30

VCCSA

M31

VCCSA

V29

VCCSA

AC30

VCCSA

AK29

VCCSA

AR29

VCCSA

N30

VCCSA

Y29

VCCSA

AE29

VCCSA

AK30

VCCSA

R29

VCCSA

Y30

VCCSA

AF29

VCCSA

AL29

VCCSA

T29

VCCSA

AT29

VCCSA_DDR

AT30

M29 N28

VCCSA_DDR VCCSA_SENSE

VSSSA_SENSE

SKYLAKE-Y-GP

CPU POWER 4 OF 4

12

C706

SC22U6D3V5MX-2GP

Layout Notes:

1. Place close to CPU within 2"

2. VCCGT_SENSE/VSSGT_SENSE impedance=50 ohm

3. Length match<25mil

C712

C711

SCD1U6D3V1KX-GP

VCCSA_SENS E VSSSA_SENSE

12

SKYLAKE_ULX

R708

1 2

0R0603-PAD-1- GP-U

15 OF 20

VCCG0 VCCG0 VCCG0 VCCG0 VCCG0 VCCG0 VCCG0 VCCG0 VCCG0 VCCG0 VCCG0 VCCG0

VCCG1 VCCG1 VCCG1 VCCG1 VCCG1 VCCG1 VCCG1 VCCG1 VCCG1 VCCG1 VCCG1 VCCG1

1

+VCCG0+VCCSA

AA35 R38 Y35 AA38 T35 Y38 AC35 T38 AC38 V35 R35 V38

AF35 AK38 AR35 AF38 AL35 AR38 AH35 AL38 AH38 AN35 AK35 AN38

VCCSA_SENS E[46]

VSSSA_SENSE[46]

+VCCPLL_OC1D35V _S3

+VCCSA

+VCCG1

12

R704

R704 100R2F-L1-GP- U

100R2F-L1-GP- U

12

R705

R705 100R2F-L1-GP- U

100R2F-L1-GP- U

A00 20160301

SKYLAKE-Y-GP

A A

5

4

VDDQC width at least 6 mil and reference GND.

3

Wistron Corporation

21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih,

21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih, Taipei Hsie n 221, Taiwan, R.O.C .

Taipei Hsie n 221, Taiwan, R.O.C .

Title

Size Document Num ber Rev

A2

Date: Sheet of

2

Date: Sheet of

Taipei Hsie n 221, Taiwan, R.O.C .

CPU(VCC)

Drax SKL Y

1

A00

7 109Monday, March 21, 2016

A00

5

4

3

2

1

SSID = CPU

D D

1 OF 20

CPU1A

HDMI_DATA2#[57]

HDMI_DATA2[57]

HDMI_DATA1#[57]

CPU_DP1_CTRL_CLK[57]

CPU_DP1_CTRL_DATA[57]

+VCCIO

HDMI_DATA0#[57]

HDMI_DATA1[57] HDMI_DATA0[57]

HDMI_CLK#[57]

HDMI_CLK[57]

R806

1 2

24D9R2F-L-GP

CPU_DP2_CTRL_CLK CPU_DP2_CTRL_DATA

EDP_COMP

HDMI

3D3V_S0

RN801

1 2 3

SRN2K2J-1-GP

C C

3D3V_S0

RN803

2 3 1

DY

SRN2K2J-1-GP

CPU_DP1_CTRL_DATA

4

CPU_DP1_CTRL_CLK

CPU_DP2_CTRL_DATA CPU_DP2_CTRL_CLK

4

A46

DDI1_TXN[0]

C46

DDI1_TXP[0]

C48

DDI1_TXN[1]

A48

DDI1_TXP[1]

B45

DDI1_TXN[2]

D45

DDI1_TXP[2]

B47

DDI1_TXN[3]

D47

DDI1_TXP[3]

A42

DDI2_TXN[0]

C42

DDI2_TXP[0]

A44

DDI2_TXN[1]

C44

DDI2_TXP[1]

B41

DDI2_TXN[2]

D41

DDI2_TXP[2]

B43

DDI2_TXN[3]

D43

DDI2_TXP[3]

L6

GPP_E18/DDPB_CTRLCLK

H6

GPP_E19/DDPB_CTRLDATA

H4

GPP_E20/DDPC_CTRLCLK

F4

GPP_E21/DDPC_CTRLDATA

M5

GPP_E22/DDPD_CTRLCLK

L4

GPP_E23/DDPD_CTRLDATA

A50

EDP_RCOMP

SKYLAKE-Y-GP

SKYLAKE_ULX

DDI

DISPLAY SIDEBANDS

DISPLAY

Strap

eDP

GPP_E13/DDPB_HPD0 GPP_E14/DDPC_HPD1 GPP_E15/DDPD_HPD2 GPP_E16/DDPE_HPD3

(#543016) eDP_RCOMP Guideline

Signal

Trace Width

Isolation Spacing

25 mils20 milseDP_RCOMP

Resistor Value

24.9 Ω ±1%

Length

Max = 100 mils

1 OF 20

EDP_TXN[0]

EDP_TXP[0]

EDP_TXN[1]

EDP_TXP[1]

EDP_TXN[2]

EDP_TXP[2]

EDP_TXN[3]

EDP_TXP[3]

EDP_AUXN EDP_AUXP

EDP_DISP_UTIL

DDI1_AUXN DDI1_AUXP DDI2_AUXN DDI2_AUXP

GPP_E17/EDP_HPD

EDP_BKLEN

EDP_BKLCTL

EDP_VDDEN

H45 F45 J44 G44 J46 G46 H43 F43

J42 G42

A40 H41

F41 J40 G40

C11 L10 M7 F6 A7

D4 B6 D3

SIO_EXT_SMI#_R

DP_DISP_UTIL

eDP_TX_CPU_N0 [55] eDP_TX_CPU_P0 [55] eDP_TX_CPU_N1 [55] eDP_TX_CPU_P1 [55]

eDP_AUX_CPU_N [55] eDP_AUX_CPU_P [55]

1

TP801TP801

CPU_DP1_HPD [57] SIO_EXT_SMI#_R [24] EDP_HPD [55]

L_BKLT_EN [24] L_BKLT_CTRL [55] EDP_VDD_EN [55]

3D3V_S0

R802 10KR2J-3-GPR802 10KR2J-3-GP

1 2

(#543016) DDI Disabling and Termination Guidelines

Enable PortStrapPort

DDPB_CTRLDATA

B B

A A

Port 1

DDPC_CTRLDATA

Port 2

Design Guideline: Skylake processor signal eDP_RCOMP should be connected to the VCCIO rail via a single 24.9 ±1% Ω resistor.

5

PU to 3.3 V with 2.2-k ±5% resistor

Disable Port

NC

4

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet of

3

2

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

CPU (DISPLAY)

Drax SKL Y

8 109Thursday, March 17, 2016

1

A00

5

4

3

2

1

SSID = CPU

18 OF 20

17 OF 20

CPU1Q

SKYLAKE_ULX

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

J9

VSS VSS VSS VSS VSS VSS VSS

SKYLAKE-Y-GP

GND 1 OF 3

SKYLAKE_ULX

A14 AA36 AA47 AA57 AC15

D D

C C

AC27 AE10 AE43 AE50 AF16 AF40 AF62 AH24 AH40 AH49

AK24 AK40

AN18 AN33 AP64

AR47 AU55

AV16

AW17

AY16 AY32 AY42 AY52

BB28 BB38 BB48 BC17 BD56 BE33 BF56

BH28 BH40 BH50

BK56 BM16

BP36 BP54

AH47 AK16

AK36

AL16 AL33 AL46 AL53

BJ29 BL35

AJ59

AK1

AR2 AR4

AR6

BA5 BA9

BG2 BG8

D10

E14

E24

E34

E44

E54

J14

AK9

V24

17 OF 20

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

K23 K33 K43 K53 L61 N20 R10 R24 R40 R49 T13 T33 T60 V27 V43 V50 Y15 Y33 Y9 AA24 AA40 AA49 AA59 AC16 AC33 AE2 AE44 AE51 AF21 AF54 AF64 AH27 AH43 AH50 AK11 AK27 AK5 AL21 AL36 AL47 AL59 AN19 AN36 AR10 AR27 AR40 AR49 AR8 AU57 AV20 AW19 AY24 AY34 AY44 BA53 BB20 BB30 BB40 BB50 BC29 BD63 BE35 BF59 BG29 AL30 AL44 AL51 AN16 AN27 BA7

BH20 BH32 BH42 BH52

BM18 BP38

BP60

AA27 AA43 AA50 AA61 AC18 AC36 AE21 AE46

AF23 AF56 AG59 AH30 AH44 AH51 AK13

AK54

AM54 AN21 AN40 AR12 AR30 AR43 AP54 AR18 AR36 AR46 AR59

BJ47 BL47

AL24 AL40 AL49

BL1

BN6

E16 E26 E36 E46 E56

K15 K25 K35 K45 K55

M3 N22 R30 R43 R50 T18 T36 T62 V30 V44 V51 Y16 Y36

AE8

AK3

BA3

CPU1R

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

J3

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

Y7

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

SKYLAKE-Y-GP

SKYLAKE_ULX

GND 2 OF 3

18 OF 20

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

AR50 AT27 AU59 AV24 AW21 AY26 AY36 AY46 BA1 BA58 BB22 BB32 BB42 BB52 BC47 BE12 BE47 BG12 BG4 BH22 BH34 BH44 BH54 BJ62 BL29 BL8 BM20 BP22 BP44 D6 E18 E28 E38 E48 E59 J5 K17 K27 K37 K47 L14 N14 N24 R33 R44 R55 T21 T40 T64 V33 V46 Y1 Y24 Y40 AA30 AA44 AA51 AA63 AC19 AC40 AE30 AE47 AF13 AU53 AU63 AV54 AW25 AY30 AY50

AF33 AF58 AH16 AH33 AH46 AH54 AK15 AK33

AM64 AN24 AN59 AR15 AR33 AR44 AR51 AT54 AU61 AV52

AW23

AY28 AY38 AY48 BA11 BA64 BB24 BB34 BB44 BB54 BD20 BE29 BF20 BG15

BH24 BH36 BH46 BH56 BK20

BM11 BM38 BP28 BP46

AY40

AH36

AL27 AL43 AL50

BL31

AK7

BG6

C14 D62 E20 E30 E40 E50 F62

K19 K29 K39 K49

N16 N26 R18 R36

V49 Y13

V40

J62

L57

CPU1S

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

SKYLAKE-Y-GP

SKYLAKE_ULX

GND 3 OF 3

19 OF 20

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSS

R46 R6 T23 T56 V13 V36 V47 Y11 Y27 Y5 BB26 BB36 BB46 BB59 BD38 BE31 BF38 BG17 BG63 BH26 BH38 BH48 BH59 BK38 BL33 BM14 BN29 BP30 BP52 C40 D8 E22 E32 E42 E52 G14 J7 K21 K31 K41 K51 L59 N18 P54 R2 R4 R47 R8 T24 T58 Y3 AA33 AA46 AA55 AB13 AC21 AD13 AE4 AE49 AF15 AF36 AF60 AH23 BP1 A5 D1

BP62

NCTF_BP1 NCTF_A5 NCTF_D1

NCTF_BP62

TP902 TPAD14-OP-GPTP902 TPAD14-OP-GP

1

TP904 TPAD14-OP-GPTP904 TPAD14-OP-GP

1

TP903 TPAD14-OP-GPTP903 TPAD14-OP-GP

1 1

TP901

TPAD14-OP-GP

B B

A A

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

C

Date: Sheet of

5

4

3

2

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

CPU (VSS)

Drax SKL Y

1

A00

9 109Monday, March 21, 2016

A00

5

SSID = CPU

+VCC_CORE +VCCGT

0603 update 22 uf cap *30(6DY)20151021 by PWR SKY

4

3

2

1

0603 update 22 uf cap *30(6DY)20151021 by PWR SKY

12

PC1007

SC22U6D3V3MX-1-GP

12

PC1014

12

PC1052

12

PC1012

SC22U6D3V3MX-1-GP

DY

12

PC1018

SC22U6D3V3MX-1-GP

12

PC1057

SC22U6D3V3MX-1-GP

12

PC1037

SC22U6D3V3MX-1-GP

DY

12

PC1045

12

PC1034

PC1004

SC22U6D3V3MX-1-GP

12

PC1033

SC22U6D3V3MX-1-GP

12

PC1027

12

PC1031

12

PC1011

SC22U6D3V3MX-1-GP

12

PC1059

SC22U6D3V3MX-1-GP

D D

C C

12

PC1019

12

PC1056

SC22U6D3V3MX-1-GP

DY

12

PC1043

PC1001

SC22U6D3V3MX-1-GP

12

PC1021

PC1023

SC22U6D3V3MX-1-GP

PC1023

SC22U6D3V3MX-1-GP

0.1U *10

12

PC1044

PC1055

SC22U6D3V3MX-1-GP

DY

12

PC1003

SC22U6D3V3MX-1-GP

DY

12

PC1026

SC22U6D3V3MX-1-GP

12

PC1041

SC22U6D3V3MX-1-GP

12

PC1008

SC22U6D3V3MX-1-GP

12

PC1028

SC22U6D3V3MX-1-GP

12

TC1001

DY

SE330U2VDM-L-GP

79.33719.L01

12

PC1032

12

PC1010

12

PC1053

SC22U6D3V3MX-1-GP

12

PC1036

12

PC1013

12

PC1051

SC22U6D3V3MX-1-GP

12

PC1035

SC22U6D3V3MX-1-GP

12

PC1015

SC22U6D3V3MX-1-GP

12

PC1046

SC22U6D3V3MX-1-GP

DY

12

PC1038

SC22U6D3V3MX-1-GP

12

PC1017

SC22U6D3V3MX-1-GP

12

PC1050

SC22U6D3V3MX-1-GP

DY

12

PC1040

SC22U6D3V3MX-1-GP

12

PC1020

SC22U6D3V3MX-1-GP

12

PC1060

SC22U6D3V3MX-1-GP

DY

12

PC1042

SC22U6D3V3MX-1-GP

12

PC1022

SC22U6D3V3MX-1-GP

12

PC1049

SC22U6D3V3MX-1-GP

DY

12

PC1002

SC22U6D3V3MX-1-GP

12

PC1024

SC22U6D3V3MX-1-GP

12

PC1058

SC22U6D3V3MX-1-GP

DY

12

PC1005

SC22U6D3V3MX-1-GP

12

PC1025

SC22U6D3V3MX-1-GP

12

PC1048

SC22U6D3V3MX-1-GP

DY

12

PC1006

SC22U6D3V3MX-1-GP

12

PC1029

SC22U6D3V3MX-1-GP

12

PC1054

SC22U6D3V3MX-1-GP

DY

12

PC1009

SC22U6D3V3MX-1-GP

12

PC1030

SC22U6D3V3MX-1-GP

12

PC1047

SC22U6D3V3MX-1-GP

0.1U *10

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

CPU (Power CAP1)

Drax SKL Y

10 109Monday, March 21, 2016

1

A00

5

4

3

2

1

SSID = CPU

+VCCG0

C1101

12

SCD1U6D3V1KX-GP

D D

+VCCG1

C C

1D35V_S3

SCD1U6D3V1KX-GP

12

C1102

C1114

SCD1U6D3V1KX-GP

0.1U *12

C1105

12

SCD1U6D3V1KX-GP

0.1U *12

C1115

12

SCD1U6D3V1KX-GP

12

C1116

C1106

SCD1U6D3V1KX-GP

C1108

C1109

12

SCD1U6D3V1KX-GP

C1117

12

C1109

12

SCD1U6D3V1KX-GP

C1119

C1118

12

SCD1U6D3V1KX-GP

+VCCIO

22U *1 / 1u *1 / 0.1U *32

0126

C1152

C1145

C1143

12

C1153

12

SC1U10V2KX-1GP

12

SC22U6D3V3MX-1-GP

SCD1U6D3V1KX-GP

12

DY

12

C1154

C1164

DY

SCD1U6D3V1KX-GP

DY

12

C1155

C1165

12

SCD1U6D3V1KX-GP

12

SCD1U6D3V1KX-GP

12

SCD1U6D3V1KX-GP

DY

C1145

C1144

C1143

C1146

C1156

C1166

C1147

C1148

C1157

C1167

12

SCD1U6D3V1KX-GP

DY

SCD1U6D3V1KX-GP

DY

SCD1U6D3V1KX-GP

C1148

12

SCD1U6D3V1KX-GP

C1158

12

SCD1U6D3V1KX-GP

DY

C1168

12

SCD1U6D3V1KX-GP

DY

12

SCD1U6D3V1KX-GP

DY

12

SCD1U6D3V1KX-GP

DY

C1149

C1173

C1169

C1150

12

SCD1U6D3V1KX-GP

DY

12

DY

12

DY

C1174

C1170

DY

12

SCD1U6D3V1KX-GP

DY

SCD1U6D3V1KX-GP

C1151

C1176

C1152

12

SCD1U6D3V1KX-GP

DY

SCD1U6D3V1KX-GP

VDDQ: 0.1U *18

C1125

C1126

12

C1126

12

SCD1U6D3V1KX-GP

12

SCD1U6D3V1KX-GP

C1127

C1128

12

SCD1U6D3V1KX-GP

12

C1130

C1133

SCD1U6D3V1KX-GP

12

SCD1U6D3V1KX-GP

C1135

12

SCD1U6D3V1KX-GP

B B

+VCCSA

A A

0603 update 22 uf cap *10(2 DY)20151023 by PWR SKY

PC1102

PC1101

12

SC22U6D3V3MX-1-GP

PC1103

PC1104

12

SC22U6D3V3MX-1-GP

5

PC1104

12

SC22U6D3V3MX-1-GP

C1136

C1137

12

SCD1U6D3V1KX-GP

PC1106

PC1105

12

SC22U6D3V3MX-1-GP

C1139

SCD1U6D3V1KX-GP

PC1107

12

SC22U6D3V3MX-1-GP

C1141

12

PC1108

12

SC22U6D3V3MX-1-GP

C1142

12

SCD1U6D3V1KX-GP

PC1111

PC1112

12

SC22U6D3V3MX-1-GP

DY

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet of

4

3

2

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

CPU (Power CAP2)

Drax SKL Y

11 109Monday, March 21, 2016

1

A00

5

SSID = MEMORY

Close RAM1 CA & DQ pin

D D

M_VREF_CA_DIMMA M_VREF_D Q_DIMMA

12

R1201

240R2F-1-GP

M_A_BS0[5] M_A_BS1[5] M_A_BS2[5]

M_A_DIMA_CLK_DDR0[5]

M_A_DIMA_CLK_DDR#0[5]

M_A_WE#[5]

C C

M_A_CAS#[5] M_A_RAS#[5]

VRAM_CH_A_ZQ_1A

M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12

M_VREF_CA_DIMMA

1D35V_S3

RAM1

B2

VDD

D9

VDD

G7

VDD

K2

VDD

K8

VDD

N1

VDD

N9

VDD

R1

VDD

R9

VDD

A1

VDDQ

A8

VDDQ

C1

VDDQ

C9

VDDQ

D2

VDDQ

E9

VDDQ

F1

VDDQ

H2

VDDQ

H9

VDDQ

H1

VREFDQ

M8

VREFCA

L8

ZQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

RAM

R3

A9

L7

A10/AP

R7

A11

N7

A12/BC#

M2

BA0

N8

BA1

M3

BA2

E7

LDM

D3

UDM

J7

CK

K7

CK#

K9

CKE

L3

WE#

K3

CAS#

J3

RAS#

MT41K256M16HA-125 -E-COLAY-1-GP

ZZ.00PAD.GW1

SCD047U25V2KX-GP

C1202

C1201

1 2

E3

DQ0

F7

DQ1

F2

DQ2

F8

DQ3

H3

DQ4

H8

DQ5

G2

DQ6

H7

DQ7

D7

DQ8

C3

DQ9

C8

DQ10

C2

DQ11

A7

DQ12

A2

DQ13

B8

DQ14

A3

DQ15

F3

LDQS

G3

LDQS#

C7

UDQS

B7

UDQS#

M_A_DIM0_ODT0

K1

ODT

L2

CS#

T2

RESET#

M_A_DIM0_ODT1

J1

NC#J1

J9

NC#J9

L1

NC#L1

VRAM_CH_A_ZQ_1B

L9

NC#L9

M_A_A15

M7

NC#M7

M_A_A13

T3

A13

M_A_A14

T7

A14

A9

VSS

B3

VSS

E1

VSS

G8

VSS

J2

VSS

J8

VSS

M1

VSS

M9

VSS

P1

VSS

P9

VSS

T1

VSS

T9

VSS

B1

VSSQ

B9

VSSQ

D1

VSSQ

D8

VSSQ

E2

VSSQ

E8

VSSQ

F9

VSSQ

G1

VSSQ

G9

VSSQ

SCD047U25V2KX-GP

C1203

C1204

1 2

M_A_A[15:0][5]

M_A_DQS#[7:0][5]

M_A_DQ29 [5] M_A_DQ26 [5] M_A_DQ28 [5] M_A_DQ27 [5] M_A_DQ25 [5] M_A_DQ30 [5] M_A_DQ24 [5] M_A_DQ31 [5]

M_A_DQ5 [5] M_A_DQ2 [5] M_A_DQ0 [5] M_A_DQ3 [5] M_A_DQ1 [5] M_A_DQ6 [5] M_A_DQ4 [5] M_A_DQ7 [5]

M_A_DQS3 [5] M_A_DQS#3 [5]

M_A_DQS0 [5] M_A_DQS#0 [5]

M_A_DIMA_CS#0 [5]

DDR3_DRAMRST# [5,13]

M_A_DIMA_CKE1 [5] M_A_DIMA_CS#1 [5]

12

R1205

R1205 240R2F-1-GP

240R2F-1-GP

1D35V_S3

DDR3L MD A DECOUPLING

12

C1215

SC10U6D3V2MX-GP-U

DY

240R2F-1-GP

12

C1216

DY

M_A_DQ[63:0][5]

M_A_DQS[7:0][5]

M_VREF_CA_DIMMA

R1202

M_A_DIMA_CLK_DDR0[5]

M_A_DIMA_CLK_DDR#0[5]

M_A_DIMA_CKE0[5]M_A_DIMA_CKE0[5]

12

C1217

SC10U6D3V2MX-GP-U

DY

12

SC10U6D3V2MX-GP-U

4

M_A_BS0[5] M_A_BS1[5] M_A_BS2[5]

M_A_WE#[5] M_A_CAS#[5] M_A_RAS#[5]

12

C1218

DY

M_VREF_DQ_DIMMA

VRAM_CH_A_ZQ_2A

M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12

Layout Note: Place these Caps near DDR3L MD.

12

C1219

SC10U6D3V2MX-GP-U

DY

1D35V_S3

B2 D9 G7 K2 K8 N1 N9 R1 R9

A1 A8 C1 C9 D2 E9 F1 H2 H9

H1

M8

L8

N3 P7 P3 N2 P8 P2 R8 R2 T8 R3

L7 R7 N7

M2 N8 M3

E7 D3

J7

K7

K9

L3

K3

J3

MT41K256M16HA-125 -E-COLAY-1-GP

12

C1220

TC1201

SC10U6D3V3MX-GP

DY

RAM2

VDD VDD VDD VDD VDD VDD VDD VDD VDD

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

LDQS#

VDDQ

UDQS

VREFDQ

UDQS# VREFCA ZQ

A0

RESET# A1 A2

NC#J1

A3

NC#J9

A4

NC#L1

A5

NC#L9

A6

NC#M7 A7 A8

RAM

A9 A10/AP A11 A12/BC#

BA0 BA1 BA2

LDM UDM

CK CK#

CKE

WE# CAS# RAS#

ZZ.00PAD.GW1

ST330U2VDM-4-GP-U

3

1D35V_S3

RAM3

VRAM_CH_A_ZQ_3A

M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12

0D675V_S0

C1205

SC1U10V2KX-1GP

C1205

SC1U10V2KX-1GP

12

B2

VDD

D9

VDD

G7

VDD

K2

VDD

K8

VDD

N1

VDD

N9

VDD

R1

VDD

R9

VDD

A1

VDDQ

A8

VDDQ

C1

VDDQ

C9

VDDQ

D2

VDDQ

E9

VDDQ

F1

VDDQ

H2

VDDQ

H9

VDDQ

H1

VREFDQ

M8

VREFCA

L8

ZQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12/BC#

M2

BA0

N8

BA1

M3

BA2

E7

LDM

D3

UDM

J7

CK

K7

CK#

K9

CKE

L3

WE#

K3

CAS#

J3

RAS#

MT41K256M16HA-125 -E-COLAY-1-GP

ZZ.00PAD.GW1

C1206

SC1U10V2KX-1GP

C1206

SC1U10V2KX-1GP

C1207

SC1U10V2KX-1GP

C1207

SC1U10V2KX-1GP

12

E3

DQ0

F7

DQ1

F2

DQ2

F8

DQ3

H3

DQ4

H8

DQ5

G2

DQ6

H7

DQ7

D7

DQ8

C3

DQ9

C8

DQ10

C2

DQ11

A7

DQ12

A2

DQ13

B8

DQ14

A3

DQ15

F3

LDQS

G3 C7

B7

M_A_DIM0_ODT0

K1

ODT

L2

CS#

T2

M_A_DIM0_ODT1

J1 J9 L1

VRAM_CH_A_ZQ_2B

L9

M_A_A15

M7

M_A_A13

T3

A13

M_A_A14

T7

A14

A9

VSS

B3

VSS

E1

VSS

G8

VSS

J2

VSS

J8

VSS

M1

VSS

M9

VSS

P1

VSS

P9

VSS

T1

VSS

T9

VSS

B1

VSSQ

B9

VSSQ

D1

VSSQ

D8

VSSQ

E2

VSSQ

E8

VSSQ

F9

VSSQ

G1

VSSQ

G9

VSSQ

M_A_DQ35 [5] M_A_DQ32 [5] M_A_DQ34 [5] M_A_DQ38 [5] M_A_DQ37 [5] M_A_DQ36 [5] M_A_DQ39 [5] M_A_DQ33 [5] M_A_DQ48 [5] M_A_DQ51 [5] M_A_DQ50 [5] M_A_DQ53 [5] M_A_DQ52 [5] M_A_DQ54 [5] M_A_DQ49 [5] M_A_DQ55 [5]

M_A_DQS4 [5] M_A_DQS#4 [5]

M_A_DQS6 [5] M_A_DQS#6 [5]

M_A_DIMA_CS#0 [5]

DDR3_DRAMRST# [5,13]

M_A_DIMA_CKE1 [5] M_A_DIMA_CS#1 [5]

240R2F-1-GP

12

R1206

R1206 240R2F-1-GP

240R2F-1-GP

M_VREF_CA_DIMMA

12

R1203

M_A_DIMA_CLK_DDR0[5]

M_A_DIMA_CLK_DDR#0[5]

M_A_DIMA_CKE0[5]

M_A_WE#[5] M_A_CAS#[5] M_A_RAS#[5]

M_A_BS0[5] M_A_BS1[5] M_A_BS2[5]

M_VREF_DQ_DIMMA

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8

DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15

LDQS

LDQS#

UDQS

UDQS#

ODT

CS#

RESET#

NC#J1 NC#J9 NC#L1 NC#L9

RAM

NC#M7

A13 A14

VSS

VSS VSSQ

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

Place these caps close to VTT1 and VTT2.

C1208

SC1U10V2KX-1GP

C1208

SC1U10V2KX-1GP

12

DY

12

C1209

E3 F7 F2 F8 H3 H8 G2 H7 D7 C3 C8 C2 A7 A2 B8 A3

F3 G3

C7 B7

K1 L2

T2 J1

J9 L1 L9 M7 T3 T7

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

B1 B9 D1 D8 E2 E8 F9 G1 G9

SC1U6D3V2KX-L-1-GP

M_A_DIM0_ODT0

M_A_DIM0_ODT1

VRAM_CH_A_ZQ_3B

M_A_A15 M_A_A13 M_A_A14

12

C1210

SC1U6D3V2KX-L-1-GP

DY

M_A_DQ18 [5] M_A_DQ16 [5] M_A_DQ23 [5] M_A_DQ21 [5] M_A_DQ19 [5] M_A_DQ17 [5] M_A_DQ22 [5] M_A_DQ20 [5] M_A_DQ10 [5] M_A_DQ13 [5] M_A_DQ15 [5] M_A_DQ12 [5] M_A_DQ14 [5]

M_A_DQ8 [5]

M_A_DQ11 [5]

M_A_DQ9 [5]

M_A_DQS2 [5] M_A_DQS#2 [5]

M_A_DQS1 [5] M_A_DQS#1 [5]

M_A_DIMA_CS#0 [5]

DDR3_DRAMRST# [5,13]

M_A_DIMA_CKE1 [5] M_A_DIMA_CS#1 [5]

12

C1211

C1212

SC1U6D3V2KX-L-1-GP

DY

2

1D35V_S3

RAM4

B2

DQ0

VDD

D9

DQ1

VDD

G7

DQ2

VDD

K2

DQ3

VDD

K8

DQ4

VDD

N1

DQ5

VDD

N9

DQ6

VDD

R1

DQ7

VDD

R9

DQ8

VDD

DQ9

A1

DQ10

VDDQ

A8

DQ11

VDDQ

C1

DQ12

VDDQ

C9

DQ13

VDDQ

D2

DQ14

VDDQ

E9

DQ15

VDDQ

F1

VDDQ

H2

LDQS

VDDQ

VRAM_CH_A_ZQ_4A

M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5

M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12

H9

LDQS#

VDDQ

UDQS

H1

VREFDQ

UDQS#

M8

VREFCA

L8

ODT

ZQ

CS#

N3

A0

RESET#

P7

A1

P3

A2

NC#J1

N2

A3

NC#J9

P8

A4

NC#L1

P2

RAM

A5

NC#L9

R8

A6

NC#M7

R2

A7

A13

T8

A8

A14

R3

A9

L7

A10/AP

R7

A11

VSS

N7

A12/BC#

VSS VSS VSS

M2

BA0

VSS

N8

BA1

VSS

M3

BA2

VSS VSS VSS

E7

VSS

LDM

D3

VSS

UDM

VSS

J7

CK

VSSQ

K7

CK#

VSSQ VSSQ

K9

CKE

VSSQ VSSQ VSSQ

L3

WE#

VSSQ

K3

CAS#

VSSQ

J3

RAS#

MT41K256M16HA-125 -E-COLAY-1-GP

VSSQ

ZZ.00PAD.GW1

M_VREF_CA_DIMMA

240R2F-1-GP

12

R1207

R1207 240R2F-1-GP

240R2F-1-GP

12

C1214

C1213

SC10U6D3V3MX-GP

SC1U6D3V2KX-L-1-GP

M_VREF_DQ_DIMMA

12

R1204

M_A_BS0[5] M_A_BS1[5] M_A_BS2[5]

M_A_DIMA_CLK_DDR0[5]

M_A_DIMA_CLK_DDR#0[5]

M_A_DIMA_CKE0[5]

M_A_WE#[5] M_A_CAS#[5] M_A_RAS#[5]

E3 F7 F2 F8 H3 H8 G2 H7 D7 C3 C8 C2 A7 A2 B8 A3

F3 G3

C7 B7

K1 L2

T2 J1

J9 L1

VRAM_CH_A_ZQ_4B

L9 M7 T3 T7

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

B1 B9 D1 D8 E2 E8 F9 G1 G9

M_A_DIM0_ODT0

M_A_DIM0_ODT1

M_A_A15M_A_A6 M_A_A13 M_A_A14

1

M_A_DQ42 [5]

M_A_DQ45 [5] M_A_DQ41 [5] M_A_DQ43 [5] M_A_DQ44 [5] M_A_DQ47 [5] M_A_DQ40 [5] M_A_DQ46 [5] M_A_DQ62 [5] M_A_DQ59 [5]

M_A_DQ63 [5] M_A_DQ56 [5]

M_A_DQ60 [5] M_A_DQ61 [5] M_A_DQ58 [5] M_A_DQ57 [5]

M_A_DQS5 [5] M_A_DQS#5 [5]

M_A_DQS7 [5] M_A_DQS#7 [5]

M_A_DIMA_CS#0 [5]

DDR3_DRAMRST# [5,13]

M_A_DIMA_CKE1 [5] M_A_DIMA_CS#1 [5]

12

R1208

R1208 240R2F-1-GP

240R2F-1-GP

M_VREF_DQ_DIMMA

B B

DIMM VREF FILTER CAPS

PLACE THESE CAPS NEAR TO RESPECTIVE DIMM PINS

SSID = MEMORY

1D35V_S3

R1210

1 2

34D8R2F-GP

1D35V_S3

R1240

1 2

34D8R2F-GP

A A

5

12

C1221

SCD047U25V2KX-GP

M_A_DIM0_ODT0

M_A_DIM0_ODT1

12

C1222

SCD047U25V2KX-GP

0D675V_S0

R1209 34D8R2F-GPR1209 34D8R2F-GP R1217 34D8R2F-GPR1217 34D8R2F-GP

R1241 34D8R2F-GPR1241 34D8R2F -GP

R1242 34D8R2F-GPR1242 34D8R2F -GP R1222 34D8R2F-GPR1222 34D8R2F-GP R1224 34D8R2F-GPR1224 34D8R2F-GP R1226 34D8R2F-GPR1226 34D8R2F-GP R1231 34D8R2F-GPR1231 34D8R2F-GP R1234 34D8R2F-GPR1234 34D8R2F-GP

R1236 34D8R2F-GPR1236 34D8R2F-GP

R1238 26D1R2F-GPR1238 26D1R2F-GP R1239 26D1R2F-GPR1239 26D1R2F-GP

12

1 2 1 2

1 2

1 2 1 2 1 2 1 2 1 2 1 2

1 2

1 2 1 2

12

C1223

C1224

SCD047U25V2KX-GP

M_A_DIMA_CKE0 M_A_DIMA_CS#0 M_A_DIMA_CKE1

M_A_DIMA_CS#1 M_A_RAS# M_A_CAS# M_A_WE# M_A_BS0 M_A_BS1

M_A_BS2

1D35V_S3

SC1U10V2KX-1GP

C1225

12

DY

M_A_DIMA_CLK_DDR0 [5] M_A_DIMA_CLK_DDR#0 [5]

SC1U10V2KX-1GP

C1226

12

DY

0D675V_S0

R1211 34D8R2F-GPR1211 34D8R2F -GP R1212 34D8R2F-GPR1212 34D8R2F -GP R1213 34D8R2F-GPR1213 34D8R2F -GP R1214 34D8R2F-GPR1214 34D8R2F -GP R1215 34D8R2F-GPR1215 34D8R2F -GP R1216 34D8R2F-GPR1216 34D8R2F -GP R1218 34D8R2F-GPR1218 34D8R2F -GP R1219 34D8R2F-GPR1219 34D8R2F -GP R1221 34D8R2F-GPR1221 34D8R2F -GP R1223 34D8R2F-GPR1223 34D8R2F -GP R1225 34D8R2F-GPR1225 34D8R2F -GP R1228 34D8R2F-GPR1228 34D8R2F -GP R1229 34D8R2F-GPR1229 34D8R2F -GP R1230 34D8R2F-GPR1230 34D8R2F -GP R1232 34D8R2F-GPR1232 34D8R2F -GP R1235 34D8R2F-GPR1235 34D8R2F -GP

C1227

12

DY

1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2

SC1U10V2KX-1GP

C1228

12

DY

4

SC1U10V2KX-1GP

C1230

C1231

C1229

12

DY

M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14 M_A_A15

SC1U10V2KX-1GP

C1234

C1232

C1233

12

DY

SC1U10V2KX-1GP

C1236

C1235

12

DY

SC1U10V2KX-1GP

C1237

12

DY

SC1U10V2KX-1GP

C1239

C1238

C1240

12

DY

Title

Size Document Number Rev

Size Document Number Rev Custom

Custom

Monday, March 21, 2016

Date: Sheet of

3

2

Date: Sheet of

Wistron Corporation

21F, 88, Se c.1, Hsin Tai W u Rd., Hsichih,

21F, 88, Se c.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

DDR3L-Memorydown1

Drax SKL Y

1

12 109

A00

M_VREF_DQ_DIMMB

M_B_BS0[5] M_B_BS1[5] M_B_BS2[5]

M_B_WE#[5] M_B_CAS#[5] M_B_RAS#[5]

5

1D35V_S3

VRAM_CH_B_ZQ_1A

M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12

SCD047U25V2KX-GP

C1301

1 2

RAM5

B2

VDD

D9

VDD

G7

VDD

K2

VDD

K8

VDD

N1

VDD

N9

VDD

R1

VDD

R9

VDD

A1

VDDQ

A8

VDDQ

C1

VDDQ

C9

VDDQ

D2

VDDQ

E9

VDDQ

F1

VDDQ

H2

VDDQ

H9

VDDQ

H1

VREFDQ

M8

VREFCA

L8

ZQ

N3

A0

P7

A1

P3

A2

N2

A3

RAM

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12/BC#

M2

BA0

N8

BA1

M3

BA2

E7

LDM

D3

UDM

J7

CK

K7

CK#

K9

CKE

L3

WE#

K3

CAS#

J3

RAS#

MT41K256M16HA-125 -E-COLAY-1-GP

ZZ.00PAD.GW1

SCD047U25V2KX-GP

C1303

C1302

1 2

M_B_DQ[63:0][5]

E3

DQ0

F7

DQ1

F2

DQ2

F8

DQ3

H3

DQ4

H8

DQ5

G2

DQ6

H7

DQ7

D7

DQ8

C3

DQ9

C8

DQ10

C2

DQ11

A7

DQ12

A2

DQ13

B8

DQ14

A3

DQ15

F3

LDQS

G3

LDQS#

C7

UDQS

B7

UDQS#

K1

ODT

L2

CS#

T2

RESET#

J1

NC#J1

J9

NC#J9

L1

NC#L1

VRAM_CH_B_ZQ_1B VRAM_CH_B_ZQ_2B VRAM_CH_B_ZQ_3B VRAM_CH_B_ZQ_4B

L9

NC#L9

M_B_A15

M7

NC#M7

M_B_A13

T3

A13

M_B_A14

T7

A14

A9

VSS

B3

VSS

E1

VSS

G8

VSS

J2

VSS

J8

VSS

M1

VSS

M9

VSS

P1

VSS

P9

VSS

T1

VSS

T9

VSS

B1

VSSQ

B9

VSSQ

D1

VSSQ

D8

VSSQ

E2

VSSQ

E8

VSSQ

F9

VSSQ

G1

VSSQ

G9

VSSQ

SCD047U25V2KX-GP

C1304

1 2

M_B_DQS[7:0][5] M_B_DQS#[7:0][5]

M_B_DQ23 [5] M_B_DQ21 [5] M_B_DQ19 [5] M_B_DQ17 [5] M_B_DQ20 [5] M_B_DQ18 [5] M_B_DQ22 [5] M_B_DQ16 [5] M_B_DQ28 [5] M_B_DQ31 [5] M_B_DQ24 [5] M_B_DQ30 [5] M_B_DQ26 [5] M_B_DQ27 [5] M_B_DQ29 [5] M_B_DQ25 [5]

M_B_DQS2 [5] M_B_DQS#2 [5]

M_B_DQS3 [5] M_B_DQS#3 [5]

M_B_DIMB_CS#0 [5]

DDR3_DRAMRST# [5,12]

M_B_DIMB_CKE1 [5] M_B_DIMB_CKE1 [5] M_B_ DIMB_CKE1 [5] M_B_D IMB_CKE1 [5]

M_B_DIMB_CS#1 [5] M_B_DIMB_CS#1 [5] M_B_DIMB_CS#1 [5] M_B_DIMB_CS# 1 [5]

12

R1305

R1305 240R2F-1-GP

240R2F-1-GP

1D35V_S3

SODIMM A DECOUPLING

12

C1315

C1316

SC10U6D3V2MX-GP-U

DY

SSID = MEMORY

D D

M_VREF_CA_DIMMB M_VREF_CA_DIMMB M_VREF_DQ_DI MMB M_VREF_CA_DIMMB M_VREF_D Q_DIMMB M_VREF_CA_DIMMB M_VREF_DQ_DIMMB

Close RAM1 CA & DQ pin

12

R1301

240R2F-1-GP

M_B_DIMB_CLK_ DDR0[5 ]

M_B_DIMB_CLK_ DDR#0[5]

C C

M_B_DIMB_CKE0[5]

M_VREF_CA_DIMMB

240R2F-1-GP

12

C1317

R1302

M_B_DIMB_CLK_ DDR0[5 ]

M_B_DIMB_CLK_ DDR#0[5]

12

C1318

SC10U6D3V3MX-GP

4

M_B_A[15:0][5]

12

M_B_BS0[5] M_B_BS1[5] M_B_BS2[5]

M_B_DIMB_CKE0[5]

M_B_WE#[5] M_B_CAS#[5] M_B_RAS#[5]

Layout Note: Place these Caps near SO-DIMMA.

12

C1319

SC10U6D3V3MX-GP

1D35V_S3 1D35V_S3 1D35V_S3

RAM6

B2

VDD

D9

VDD

G7

VDD

K2

VDD

K8

VDD

N1

VDD

N9

VDD

R1

VDD

R9

VDD

A1

VDDQ

A8

VDDQ

C1

VDDQ

C9

VDDQ

D2

VDDQ

E9

VDDQ

F1

VDDQ

H2

VDDQ

H9

VDDQ

H1

VREFDQ

M8

VRAM_CH_B_ZQ_2A VRAM_CH_B_ZQ_4A

M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12

12

C1320

SC10U6D3V3MX-GP

VREFCA

L8

ZQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12/BC#

M2

BA0

N8

BA1

M3

BA2

E7

LDM

D3

UDM

J7

CK

K7

CK#

K9

CKE

L3

WE#

K3

CAS#

J3

RAS#

MT41K256M16HA-125 -E-COLAY-1-GP

ZZ.00PAD.GW1

RAM

LDQS#

UDQS#

RESET#

NC#M7

E3

DQ0

F7

DQ1

F2

DQ2

F8

DQ3

H3

DQ4

H8

DQ5

G2

DQ6

H7

DQ7

D7

DQ8

C3

DQ9

C8

DQ10

C2

DQ11

A7

DQ12

A2

DQ13

B8

DQ14

A3

DQ15

F3

LDQS

G3 C7

UDQS

B7

M_B_DIM0_ODT0

K1

ODT

L2

CS#

T2

M_B_DIM0_ODT1 M_B_DIM0_ODT1M_B_DIM0_ODT1

J1

NC#J1

J9

NC#J9

L1

NC#L1

L9

NC#L9

M7 T3

A13

T7

A14

A9

VSS

B3

VSS

E1

VSS

G8

VSS

J2

VSS

J8

VSS

M1

VSS

M9

VSS

P1

VSS

P9

VSS

T1

VSS

T9

VSS

B1

VSSQ

B9

VSSQ

D1

VSSQ

D8

VSSQ

E2

VSSQ

E8

VSSQ

F9

VSSQ

G1

VSSQ

G9

VSSQ

M_B_A15 M_B_A13 M_B_A14

M_B_DQS7 [5] M_B_DQS#7 [5]

M_B_DQS6 [5] M_B_DQS#6 [5]

M_B_DIMB_CS#0 [5]

DDR3_DRAMRST# [5,12]

M_B_DQ60 [5] M_B_DQ58 [5] M_B_DQ61 [5] M_B_DQ62 [5] M_B_DQ56 [5] M_B_DQ59 [5] M_B_DQ57 [5] M_B_DQ63 [5] M_B_DQ51 [5] M_B_DQ52 [5] M_B_DQ55 [5] M_B_DQ48 [5] M_B_DQ54 [5] M_B_DQ49 [5] M_B_DQ50 [5] M_B_DQ53 [5]

3

12

240R2F-1-GP

R1306

R1306 240R2F-1-GP

240R2F-1-GP

2

RAM7

B2

VDD

D9

VDD

G7

VDD

K2

VDD

K8

VDD

N1

VDD

N9

VDD

R1

VDD

R9

VDD

A1

VDDQ

A8

VDDQ

C1

VDDQ

C9

VDDQ

D2

VDDQ

E9

VDDQ

F1

VDDQ

H2

VDDQ

H9

VDDQ

H1

VREFDQ

M8

MT41K256M16HA-125 -E-COLAY-1-GP

C1308

SC1U10V2KX-1GP

C1308

SC1U10V2KX-1GP

12

VREFCA

L8

ZQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12/BC#

M2

BA0

N8

BA1

M3

BA2

E7

LDM

D3

UDM

J7

CK

K7

CK#

K9

CKE

L3

WE#

K3

CAS#

J3

RAS#

ZZ.00PAD.GW1

12

DY

VRAM_CH_B_ZQ_3AM_B_DIM0_ODT0

12

M_B_A0

R1303

M_B_DIMB_CLK_ DDR0[5 ]

M_B_DIMB_CLK_ DDR#0[5]

M_B_DIMB_CKE0[5]

0D675V_S0

C1305

SC1U10V2KX-1GP

C1305

SC1U10V2KX-1GP

M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12

M_B_BS0[5] M_B_BS1[5] M_B_BS2[5]

M_B_WE#[5] M_B_CAS#[5] M_B_RAS#[5]

Place these caps close to VTT1 and VTT2.

C1306

SC1U10V2KX-1GP

C1306

SC1U10V2KX-1GP

C1307

SC1U10V2KX-1GP

C1307

SC1U10V2KX-1GP

12

E3

DQ0

F7

DQ1

F2

DQ2

F8

DQ3

H3

DQ4

H8

DQ5

G2

DQ6

H7

DQ7

D7

DQ8

C3

DQ9

C8

DQ10

C2

DQ11

A7

DQ12

A2

DQ13

B8

DQ14

A3

DQ15

F3

LDQS

G3

LDQS#

C7

UDQS

B7

UDQS#

M_B_DIM0_ODT0

K1

ODT

L2

CS#

T2

RESET#

M_B_DIM0_ODT1

J1

NC#J1

J9

NC#J9

RAM

L1

NC#L1

L9

NC#L9

M_B_A15

M7

NC#M7

M_B_A13

T3

A13

M_B_A14

T7

A14

A9

VSS

B3

VSS

E1

VSS

G8

VSS

J2

VSS

J8

VSS

M1

VSS

M9

VSS

P1

VSS

P9

VSS

T1

VSS

T9

VSS

B1

VSSQ

B9

VSSQ

D1

VSSQ

D8

VSSQ

E2

VSSQ

E8

VSSQ

F9

VSSQ

G1

VSSQ

G9

VSSQ

12

DY

C1311

C1310

C1309

SC1U10V2KX-1GP

C1312

SC1U10V2KX-1GP

12

C1313

SC10U6D3V3MX-GP

M_B_DQ15 [5] M_B_DQ14 [5]

M_B_DQ8 [5]

M_B_DQ11 [5]

M_B_DQ9 [5] M_B_DQ13 [5] M_B_DQ12 [5] M_B_DQ10 [5]

M_B_DQ1 [5]

M_B_DQ5 [5]

M_B_DQ3 [5]

M_B_DQ4 [5]

M_B_DQ6 [5]

M_B_DQ7 [5]

M_B_DQ0 [5]

M_B_DQ2 [5]

M_B_DQS1 [5] M_B_DQS#1 [5]

M_B_DQS0 [5] M_B_DQS#0 [5]

M_B_DIMB_CS#0 [5]

DDR3_DRAMRST# [5,12]

12

C1314

SC10U6D3V3MX-GP

12

R1307

R1307 240R2F-1-GP

240R2F-1-GP

1

RAM8

B2

VDD

D9

VDD

G7

VDD

K2

VDD

K8

VDD

N1

VDD

N9

VDD

R1

VDD

R9

VDD

A1

VDDQ

A8

VDDQ

C1

VDDQ

C9

VDDQ

D2

VDDQ

E9

VDDQ

F1

VDDQ

H2

VDDQ

H9

VDDQ

H1

VREFDQ

M8

VREFCA

L8

12

M_B_A0

R1304

M_B_DIMB_CLK_ DDR0[5 ]

M_B_DIMB_CLK_ DDR#0[5]

M_B_DIMB_CKE0[5]

M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12

M_B_BS0[5] M_B_BS1[5] M_B_BS2[5]

M_B_WE#[5] M_B_CAS#[5] M_B_RAS#[5]

ZQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12/BC#

M2

BA0

N8

BA1

M3

BA2

E7

LDM

D3

UDM

J7

CK

K7

CK#

K9

CKE

L3

WE#

K3

CAS#

J3

RAS#

MT41K256M16HA-125 -E-COLAY-1-GP

ZZ.00PAD.GW1

RAM

LDQS#

UDQS#

RESET#

NC#J1 NC#J9 NC#L1 NC#L9 NC#M7

E3

DQ0

F7

DQ1

F2

DQ2

F8

DQ3

H3

DQ4

H8

DQ5

G2

DQ6

H7

DQ7

D7

DQ8

C3

DQ9

C8

DQ10

C2

DQ11

A7

DQ12

A2

DQ13

B8

DQ14

A3

DQ15

F3

LDQS

G3 C7

UDQS

B7

M_B_DIM0_ODT0

K1

ODT

L2

CS#

T2 J1

J9 L1 L9

M_B_A15

M7

M_B_A13

T3

A13

M_B_A14

T7

A14

A9

VSS

B3

VSS

E1

VSS

G8

VSS

J2

VSS

J8

VSS

M1

VSS

M9

VSS

P1

VSS

P9

VSS

T1

VSS

T9

VSS

B1

VSSQ

B9

VSSQ

D1

VSSQ

D8

VSSQ

E2

VSSQ

E8

VSSQ

F9

VSSQ

G1

VSSQ

G9

VSSQ

M_B_DQ32 [5] M_B_DQ33 [5] M_B_DQ34 [5] M_B_DQ37 [5] M_B_DQ39 [5] M_B_DQ35 [5] M_B_DQ36 [5] M_B_DQ38 [5] M_B_DQ41 [5] M_B_DQ43 [5] M_B_DQ40 [5] M_B_DQ46 [5] M_B_DQ45 [5] M_B_DQ42 [5] M_B_DQ44 [5] M_B_DQ47 [5]

M_B_DQS4 [5] M_B_DQS#4 [5]

M_B_DQS5 [5] M_B_DQS#5 [5]

M_B_DIMB_CS#0 [5]

DDR3_DRAMRST# [5,12]

12

R1308

R1308 240R2F-1-GP

240R2F-1-GP

M_VREF_DQ_DIMMB

B B

DIMM VREF FILTER CAPS

PLACE THESE CAPS NEAR TO RESPECTIVE DIMM PINS

1D35V_S3

R1316

1 2

34D8R2F-GP

1D35V_S3

R1341

1 2

34D8R2F-GP

A A

34D8R2F-GP

12

M_B_DIM0_ODT0

M_B_DIM0_ODT1

5

12

C1321

SCD047U25V2KX-GP

0D675V_S0

12

C1322

C1323

SCD047U25V2KX-GP

R1309 34D8R2F-GPR1309 34D8R2F -GP

1 2

R1317 34D8R2F-GPR1317 34D8R2F -GP

1 2

R1327 34D8R2F-GPR1327 34D8R2F -GP

1 2

R1342 34D8R2F-GPR1342 34D8R2F -GP

1 2

R1322 34D8R2F-GPR1322 34D8R2F -GP

1 2

R1324 34D8R2F-GPR1324 34D8R2F -GP

1 2

R1328 34D8R2F-GPR1328 34D8R2F -GP

1 2

R1332 34D8R2F-GPR1332 34D8R2F -GP

1 2

R1335 34D8R2F-GPR1335 34D8R2F -GP

1 2

R1337 34D8R2F-GPR1337 34D8R2F -GP

1 2

R1339 26D1R2 F-GPR1339 26D1R2 F-GP

1 2

R1340 26D1R2 F-GPR1340 26D1R2 F-GP

1 2

C1324

SCD047U25V2KX-GP

M_B_DIMB_CKE0 M_B_DIMB_CS#0 M_B_DIMB_CKE1 M_B_DIMB_CS#1

M_B_RAS# M_B_CAS# M_B_WE# M_B_BS0 M_B_BS1 M_B_BS2

1D35V_S3

C1325

SC1U10V2KX-1GPDYC1325

SC1U10V2KX-1GP

DY

M_B_DIMB_CLK_ DDR0 [5]

M_B_DIMB_CLK_ DDR#0 [ 5]

12

SC1U10V2KX-1GP

0D675V_S0

C1326

C1328

SC1U10V2KX-1GPDYC1328

SC1U10V2KX-1GP

C1327

SC1U10V2KX-1GPDYC1327

SC1U10V2KX-1GP

12

DY

R1310 34D8R2F-GPR1310 34D8R2F -GP

1 2

R1311 34D8R2F-GPR1311 34D8R2F -GP

1 2

R1312 34D8R2F-GPR1312 34D8R2F -GP

1 2

R1313 34D8R2F-GPR1313 34D8R2F -GP

1 2

R1314 34D8R2F-GPR1314 34D8R2F -GP

1 2

R1315 34D8R2F-GPR1315 34D8R2F -GP

1 2

R1318 34D8R2F-GPR1318 34D8R2F -GP

1 2

R1319 34D8R2F-GPR1319 34D8R2F -GP

1 2

R1321 34D8R2F-GPR1321 34D8R2F -GP

1 2

R1323 34D8R2F-GPR1323 34D8R2F -GP

1 2

R1325 34D8R2F-GPR1325 34D8R2F -GP

1 2

R1329 34D8R2F-GPR1329 34D8R2F -GP

1 2

R1330 34D8R2F-GPR1330 34D8R2F -GP

1 2

R1331 34D8R2F-GPR1331 34D8R2F -GP

1 2

R1334 34D8R2F-GPR1334 34D8R2F -GP

1 2

R1336 34D8R2F-GPR1336 34D8R2F -GP

1 2

C1332

SC1U10V2KX-1GPDYC1332

SC1U10V2KX-1GP

C1331

SC1U10V2KX-1GP

C1331

SC1U10V2KX-1GP

C1330

SC1U10V2KX-1GPDYC1330

SC1U10V2KX-1GP

C1329

SC1U10V2KX-1GPDYC1329

SC1U10V2KX-1GP

DY

4

12

DY

M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14 M_B_A15

DY

SC1U10V2KX-1GPDYC1334

SC1U10V2KX-1GP

C1333

SC1U10V2KX-1GPDYC1333

SC1U10V2KX-1GP

12

DY

C1336

SC1U10V2KX-1GPDYC1336

SC1U10V2KX-1GP

C1335

SC1U10V2KX-1GPDYC1335

SC1U10V2KX-1GP

C1334

12

DY

C1337

SC1U10V2KX-1GPDYC1337

SC1U10V2KX-1GP

SC1U10V2KX-1GPDYC1338

SC1U10V2KX-1GP

12

DY

C1340

SC1U10V2KX-1GPDYC1340

SC1U10V2KX-1GP

C1339

SC1U10V2KX-1GPDYC1339

SC1U10V2KX-1GP

C1338

DY

12

DY

Title

Size Document Number Rev

Size Document Number Rev Custom

Custom

Monday, March 21, 2016

Date: Sheet of

3

2

Date: Sheet of

Wistron Corporation

21F, 88, Se c.1, Hsin Tai W u Rd., Hsichih,

21F, 88, Se c.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

DDR3L-Memorydown2

Drax SKL Y

1

13 109

A00

5

D D

C C

4

3

2

1

(Blanking)

B B

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

A A

Title

Reserved

Size Document Number Rev

A4

Date: Sheet of

5

4

3

2

Reserved

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Drax SKL Y

14 109Monday, March 21, 2016

A00

1

5

4

3

2

1

SSID = CPU

9 OF 20

CPU1I

D D

C C

CPU1I

H29

CSI2_DN0

F29

CSI2_DP0

F33

CSI2_DN1

H33

CSI2_DP1

J30

CSI2_DN2

G30

CSI2_DP2

J32

CSI2_DN3

G32

CSI2_DP3

D29

CSI2_DN4

B29

CSI2_DP4

C32

CSI2_DN5

A32

CSI2_DP5

C30

CSI2_DN6

A30

CSI2_DP6

D33

CSI2_DN7

B33

CSI2_DP7

D35

CSI2_DN8

B35

CSI2_DP8

C36

CSI2_DN9

A36

CSI2_DP9

D37

CSI2_DN10

B37

CSI2_DP10

C38

CSI2_DN11

A38

CSI2_DP11

SKYLAKE-Y-GP

SKYLAKE_ULX

CSI-2

eMMC

GPP_F13/EMMC_DATA0 GPP_F14/EMMC_DATA1 GPP_F15/EMMC_DATA2 GPP_F16/EMMC_DATA3 GPP_F17/EMMC_DATA4 GPP_F18/EMMC_DATA5 GPP_F19/EMMC_DATA6 GPP_F20/EMMC_DATA7

GPP_F21/EMMC_RCLK

GPP_D4/FLASHTRIG

GPP_F22/EMMC_CLK

GPP_F12/EMMC_CMD

9 OF 20

CSI2_CLKN0 CSI2_CLKP0 CSI2_CLKN1 CSI2_CLKP1 CSI2_CLKN2 CSI2_CLKP2 CSI2_CLKN3 CSI2_CLKP3

CSI2_COMP

EMMC_RCOMP

H31 F31 D31 B31 C34 A34 D39 B39 A11 N4

AN12 AP9 AN10 AJ10 AM9 AL12 AJ12 AN8

AL10 AL8 AM11

BC1

DC resistance < 0.5ohm.

R1501 100R2F-L1-GP-UR1501 100R2F-L1-GP-U

CSI2_COMP

EMMC_RCOMP

1 2

R1504

R1504 200R2F-L-GP

200R2F-L-GP

B B

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

A A

Title

CPU (CSI2/EMMC )

Size Document Number Rev

A4

Date: Sheet of

5

4

3

2

CPU (CSI2/EMMC )

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Drax SKL Y

15 109Monday, March 21, 2016

A00

1

5

SSID = PCH

D D

WLAN

Card Reader

C C

B B

HDD

PCIE_RX_CPU_N5[61] PCIE_RX_CPU_P5[61]

PCIE_TX_CON_N5[61] PCIE_TX_CON_P5[61]

PCIE_RX_CPU_N6[33] PCIE_RX_CPU_P6[33]

PCIE_TX_CON_N6[33] PCIE_TX_CON_P6[33]

SATA_RX_CPU_N0[60]

SATA_RX_CPU_P0[60]

SATA_TX_CPU_N0[60]

SATA_TX_CPU_P0[60]

XDP_PRDY#[99] XDP_PREQ#[99]

C1607

C1607 C1608

C1608

C1610

C1610 C1609

C1609

R1604 100R2F-L1-GP-UR1604 100R2F-L1-GP-U

3D3V_S0

R1605 10KR2F-2-GPR1605 10KR2F-2-GP

1 2 1 2

1 2

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

PEG_RCOMPN_CPU PEG_RCOMPP_CPU

PIRQA#

4

PCIE_TX_CPU_N5 PCIE_TX_CPU_P5

PCIE_TX_CPU_N6 PCIE_TX_CPU_P6

CPU1H

C20

PCIE1_RXN/USB3_5_RXN

A20

PCIE1_RXP/USB3_5_RXP

G20

PCIE1_TXN/USB3_5_TXN

J20

PCIE1_TXP/USB3_5_TXP

B19

PCIE2_RXN/USB3_6_RXN

D19

PCIE2_RXP/USB3_6_RXP

F19

PCIE2_TXN/USB3_6_TXN

H19

PCIE2_TXP/USB3_6_TXP

C22

PCIE3_RXN

A22

PCIE3_RXP

G22

PCIE3_TXN

J22

PCIE3_TXP

B21

PCIE4_RXN

D21

PCIE4_RXP

F21

PCIE4_TXN

H21

PCIE4_TXP

C24

PCIE5_RXN

A24

PCIE5_RXP

G24

PCIE5_TXN

J24

PCIE5_TXP

B23

PCIE6_RXN

D23

PCIE6_RXP

F23

PCIE6_TXN

H23

PCIE6_TXP

C26

PCIE7_RXN/SATA0_RXN

A26

PCIE7_RXP/SATA0_RXP

G26

PCIE7_TXN/SATA0_TXN

J26

PCIE7_TXP/SATA0_TXP

B25

PCIE8_RXN/SATA1A_RXN

D25

PCIE8_RXP/SATA1A_RXP

F25

PCIE8_TXN/SATA1A_TXN

H25

PCIE8_TXP/SATA1A_TXP

C28

PCIE9_RXN

A28

PCIE9_RXP

G28

PCIE9_TXN

J28

PCIE9_TXP

B27

PCIE10_RXN

D27

PCIE10_RXP

F27

PCIE10_TXN

H27

PCIE10_TXP

A9

PCIE_RCOMPN

B10

PCIE_RCOMPP

D51

PROC_PRDY#

B55

PROC_PREQ#

BF3

GPP_A7/PIRQA#

SKYLAKE-Y-GP

PCIE/USB3/SATA

SKYLAKE_ULX

3

SSIC / USB3

SIO_EXT_SCI#_R

SATAGP2 SATAGP0 SATAGP1

2

1

USB Table

Pair

1

8 OF 20

USB2N_1 USB2P_1

USB2N_5 USB2P_5

USB2N_7 USB2P_7

USB2N_3 USB2P_3

USB2N_9 USB2P_9

USB2N_2 USB2P_2

USB2_ID

3D3V_S0

C16 A16 G16 J16

B15 D15 F15 H15

C18 A18 G18 J18

B17 D17 F17 H17

AJ6 AJ4

AH5 AH3

AF5 AF3

AL6 AL4

AG6 AG4

AM3 AM5

N2 AF7 AE6

N12 M11 F8 B8

F10 H10 L8

G11 J11 N10

H8

USBCOMP USB2_ID USB2_VBSENSE

USB_OC2# USB_OC3#

SATAGP0 SATAGP1 SATAGP2

SATA_ACT#

USB_OC2# USB_OC3# USB_OC0# USB_OC1#

USB3_1_RXN

USB3_1_RXP USB3_1_TXN USB3_1_TXP

USB3_2_RXN/SSIC_1_RXN USB3_2_RXP/SSIC_1_RXP

USB3_2_TXN/SSIC_1_TXN USB3_2_TXP/SSIC_1_TXP

USB3_3_RXN/SSIC_2_RXN USB3_3_RXP/SSIC_2_RXP

USB3_3_TXN/SSIC_2_TXN USB3_3_TXP/SSIC_2_TXP

USB3_4_RXN

USB3_4_RXP USB3_4_TXN USB3_4_TXP

USB2

USB2_COMP

USB2_VBUSSENSE

GPP_E9/USB2_OC0# GPP_E10/USB2_OC1# GPP_E11/USB2_OC2# GPP_E12/USB2_OC3#

GPP_E4/DEVSLP0 GPP_E5/DEVSLP1 GPP_E6/DEVSLP2

GPP_E0/SATAXPCIE0/SATAGP0 GPP_E1/SATAXPCIE1/SATAGP1 GPP_E2/SATAXPCIE2/SATAGP2

GPP_E8/SATALED#

(#543611) The SATALED# signal is open-collector and requires a weak external pull-up (8.2 kΩ to 10 kΩ ) to Vcc3_3.

DY

DY DY

DY

12

12 12 12

R1608 10KR2J-3-GPR1608 10KR2J-3-GP

R1613 10KR2J-3-GP

R1613 10KR2J-3-GP R1611 10KR2J-3-GP

R1611 10KR2J-3-GP R1612 10KR2J-3-GP

R1612 10KR2J-3-GP

USB30_RX_CPU_N1 [36] USB30_RX_CPU_P1 [36] USB30_TX_CPU_N1 [36] USB30_TX_CPU_P1 [36]

USB_CPU_PN1 [36] USB_CPU_PP1 [36]

USB_CPU_PN5 [55] USB_CPU_PP5 [55]

USB_CPU_PN7 [55] USB_CPU_PP7 [55]

USB_CPU_PN3 [66] USB_CPU_PP3 [66]

USB_CPU_PN9 [61] USB_CPU_PP9 [61]

USB_CPU_PN2 [37] USB_CPU_PP2 [37]

R1603 113R2F-GPR1603 113R2F-GP

1 2

R1601

R1601 R1602

R1602

HDD_DEVSLP [60] SIO_EXT_SCI#_R [24]

1 2 1 2

1KR2J-1-GP

1KR2J-1-GP 1KR2J-1-GP

1KR2J-1-GP

USB_OC0# [66] USB_OC1# [35]

1

RN1601

8 7 6

SRN10KJ-6-GP

TP1601 TPAD14-OP-GPTP1601 TPAD14-OP-GP

2 3 5 7 9

USB3.0 on MB

TOUCH SCREEN

CAMERA

USB2.0 on DB

WLAN

USB2.0 on DB

DC resistance < 0.5ohm.

3D3V_S5_PCH

1 2 3 45

Device

USB3.0 on MB

USB 2.0 on DB

TOUCH SCREEN

CAMERA

WLAN

R1607

SATA_ACT#

R1607

DY

10KR2J-3-GP

3D3V_S0

12

(#543016) When used as DEVSLP, no external pull-up or pull-down termination required from SATA Host DEVSLP.

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

CPU (PCIE/SATA/USB)

Drax SKL Y

16 109Thursday, March 17, 2016

1

A00

5

4

3

2

1

SSID = PCH

PLT_RST#[24,26,33,37,61,68]

3D3V_S5

RN1710

1 2 3

SRN10KJ-5-G P

D D

C C

SRN10KJ-5-G P

GPD11 pull high by Intel PDG1.3 request

EC1707

DY

RN1703

1 2 3

SRN10KJ-5-G P

R1729

DY

R1738

DS3

Follow PDG ver1.5

3D3V_S5_PCH

R1742

1 2

DY

10KR2J-3-GP

R1717

1 2

10KR2J-3-GP

R1711

1 2

20KR2F-L-GP

+VCCDSW _3P3

RN1704

1 2 3

SRN10KJ-5-G P

R1710

1 2

12

R1736

DY

10KR2J-3-GP

#544669 Rev0.52 CRB: No PL resistor on THERMTRIP#.

RTC_AUX_S5

R1703

1 2

1MR2J-L2-GP

4

12

SCD1U16V2KX- 3GP

4

12

10KR2J-3-GP

12

10KR2J-3-GP

ME_SUS_PW R_ACK_R

Follow PDG ver1.5

4

10KR2J-3-GP

H_CPUPW RGD

12

DY

EC1701

AZ5725-01FDR 7G-GP

AC_PRESENT GPD11/LANPHYPC

AC_PRESENT

PM_PCH_PW ROK

PM_RSMRST#

SYS_PWROK PCH_DPW ROK

XDP_DBRESE T#

EXT_PWR _GATE#

PCH_WA KE#

GPD2/LAN_W AKE#

PM_BATLOW #

SM_INTRUDER #

KBC delay 99ms

#543016 Rev0.7

1. VCCST_PWRGD is only 1.0 V tolerant.

2. VCCST_PWRGD must go low during Sx pwr states, regardless of the voltage level of VCCST

1 2

0R0603-PAD-1- GP-U

A00 20160301

XDP_DBRESE T#[99]

H_VCCST_PW RGD[99]

SYS_PWROK[24,99]

PCH_PW ROK[24,26]

PM_RSMRST#

R1701 R1706 R1733 A00 20160302

(PDG#543016) WAKE#: Ensure that WAKE# signal Trise (Maximum) is <100 ns.

ALL_SYS_PWRG D[24,40,50]

+VCCDSW _3P33D3V _S5

R1748

R1716 60D4R2F-GPR1716 60D4R2F -GP

1 2

R1701 0R0402-PAD-1-GPR 1701 0R0402-PAD-1-GP

1 2

R1706 0R0402-PAD-1-GPR 1706 0R0402-PAD-1-GP

1 2

R1733 0R0402-PAD-1-GPR 1733 0R0402-PAD-1-GP

1 2

12

EC1709

DY

AZ5725-01FDR 7G-GP

NON DS3

TPAD14-OP-G P

TP1705

U1702

1

NC#1

2

A GND3Y

74LVC1G07GW -GP

73.01G07.0HG

1 2

DY

R1725

R1725 100KR2F-L1-GP

100KR2F-L1-GP

CPU1K

PCH_PLTRST # PM_RSMRST# SIO_SLP_S5# H_CPUPW RGD

1

H_VCCST_PW RGD_R SYS_PWROK_R SIO_SLP_A#

PM_PCH_PW ROK PCH_DPW ROK

ME_SUS_PW R_ACK_R SUSACK#_R

PCH_WA KE#

GPD2/LAN_W AKE#

GPD11/LANPHYPC

3D3V_S5

SCD1U16V2KX-3GP

C1702

12

DY

5

VCC

4

12

R1726

R1726 47KR2F-GP

47KR2F-GP

DY

+VCCSTG

12

H_VCCST_PW RGD

BB8

GPP_B13/PLTRST#

H2

SYS_RESET#

BJ12

RSMRST#

A62

PROCPWRGD

B61

VCCST_PWRGD

J1

SYS_PWROK

BP14

PCH_PWROK

BN15

DSW_PWROK

BL6

GPP_A13/SUSWARN#/SUSPWRDNACK

BF9

GPP_A15/SUSACK#

BP9

WAKE#

BE15

GPD2/LAN_WAKE#

BC15

GPD11/LANPHYPC

BB16

GPD7/RSVD

SKYLAKE-Y-GP

R1704

R1704 100KR2J-1-GP

100KR2J-1-GP

12

C1701

SCD01U50V2KX-1GP

PLT_RST# PCH_PLTRST#

12

R1723

100KR2J-1-GP

DY

A00 EMC 20160303 It layout near CPU so use.

SYSTEM POWER MANAGEMENT

12

DY

EC1708

AZ5725-01FDR7G-GP

1 2

0R0402-PAD-1- GP

EC1710

AZ5725-01FDR7G-GP

EC1710

AZ5725-01FDR7G-GP

12

SKYLAKE_ULX

R1713

83.05725.0A0

12

EC1706

DY

SC1KP50V2KX-1GP

A00 20160301

GPD1/ACPRESENT

GPP_B11/EXT_PWR_GATE#

GPP_B2/VRALERT#

12

DY

EC1702

EC1703

AZ5725-01FDR7G-GP

3D3V_AUX_S5

[#543016 Rev0.7] EXT_PWR_GATE#: Due to a bug on A0, a temporary pull-up resistor will be required to overcome the internal 20k pull-down that is active during the early portion of the power up sequence

Layout note: 3 PAD SHARING

11 OF 20

SIO_SLP_S0#

GPP_B12/SLP_S0#

GPD4/SLP_S3# GPD5/SLP_S4#

GPD10/SLP_S5#

SLP_SUS# SLP_LAN#

GPD9/SLP_WLAN#

GPD6/SLP_A# GPD3/PWRBTN# GPD0/BATLOW#

GPP_A11/PME#

INTRUDER#

12

DY

EC1704

DY

AZ5725-01FDR7G-GP

R1737

1 2

NON DS3

100KR2J-1-GP

12

PM_RSMRST#_M

BC9 AY14 BF16 BH14

BN10 BP11 BH16 BE17

BF14 BD14 BD16

BF7 BG19

BC7 BD6

EC1705

12

DY

AZ5725-01FDR7G-GP

SIO_SLP_LAN# AUX_EN_W OWL

AC_PRESENT PM_BATLOW #

PME# SM_INTRUDER #

EXT_PWR _GATE# GPP_B2/VRALER T#

XDP_DBRESE T#

SYS_PWROK

PLT_RST#

PCH_PW ROK

3V_5V_POK

SIO_SLP_S0# [24]

1

TP1708TP1708

1

TP1709TP1709

1

TP1711TP1711

1

TP1710TP1710

1

TP1706TP1706

1

TP1707TP1707

4th = 84.DMN66.03F

3rd = 75.00601.07C

2nd = 84.2N702.E3F

84.2N702.A3F

Q1702

Q1702 2N7002KDW -GP

2N7002KDW -GP

NON DS3

6

SIO_SLP_S3# [24,27,40,51]

SIO_SLP_S4# [24,40,51]

SIO_SLP_SUS# [24,41,49,53]

SIO_PWRBTN # [2 4,99] AC_PRESENT [24]

PM_RSMRST#_R

2345 1

R1724

1 2

0R0402-PAD-1- GP

AC_PRESENT PM_RSMRST#

A00 20160301NON DS3

B B

NON DS3

ME_SUS_PW R_ACK_R

PM_SUSACK#[24]

PM_SUSWA RN#[24]

3D3V_AUX_S5

R1727

R1727 10KR2J-3-GP

10KR2J-3-GP

1 2

A A

5

0R0402-PAD-1- GP

R1730

100KR2J-1-GP

1 2

NON DS3

84.2N702.A3F

2nd = 84.2N702.E3F

3rd = 75.00601.07C

4th = 84.DMN66.03F

R1714

1 2

RN1702

2 3

DS3

1

SRN0J-6-GP

Q1701

6

2N7002KDW -GP

SUSACK#_R

A00 20160301

SUSACK#_R ME_SUS_PW R_ACK_R

4

2345 1

PM_RSMRST# 3V_5V_POK_C3V_5V_POK#

DS3 BOM Option

PCH_DPW ROK

1KR2J-1-GP

1KR2J-1-GP R1712

R1712

1 2

R1728

1 2

0R0402-PAD-1- GP

A00 20160301NON DS3

R1722

SIO_SLP_SUS#

1 2

DS3

0R2J-2-GP

R1719 0R2J-2-GP

1 2

DS3

12

DY

EC1711

AZ5725-01FDR7G-GP

12

DY

C1704

SCD47U10V2KX-GP

4

KBC_DPW ROK [24]

3V_5V_POK [40,45,49,5 3]

EC1712

12

DY

SCD1U16V2KX-3GP

RSMRST#_KBC [24,99]

U1701

1

PLT_RST#

3

B

2

A GND3Y

74AHC1G08GW -GP-U

R1732

MPHY / SRAM Supply instantaneous slew rate must between 5~100mV/us Tr between 10~200us

VCC

XDP

1 2

DY

0R2J-2-GP

3D3V_S0

5

4

BUF_PLT_RST # [99]

2

Wistron Corporation

21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih,

21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih, Taipei Hsie n 221, Taiwan, R.O.C .

Taipei Hsie n 221, Taiwan, R.O.C .

Title

Size Document Num ber Rev

A2

Date: Sheet of

Taipei Hsie n 221, Taiwan, R.O.C .

CPU (PM)

Drax SKL Y

1

17 109Monday, March 21, 201 6

A00

5

4

3

2

1

SSID = PCH

PCH strap pin:

Sampled at rising edge of RSMRST#

eSPI or LPC

SML0ALERT# / GPP_C5

This signal has a weak internal pull-down.

D D

3D3V_S5_PCH

C C

B B

A A

5

This signal has a weak internal pull-down. 0 = LPC Is selected for EC. 1 = eSPI Is selected for EC.

R1843

1 2

1KR2J-1-GP

R1837

1 2

1KR2J-1-GP

SPI_CLK_ROM[24,25]

SPI_SO_ROM[24,25]

SPI_SI_ROM[24,25] SPI_WP_ROM[25] SPI_HOLD_ROM[25]

SPI_CS_ROM_N0[24,25] SPI_CS_ROM_N1[25 ]

HDD_FALL_INT[70]

SIO_RCIN#[24]

SERIRQ[24]

3D3V_S0

SRN10KJ-5-G P

RCIN#: Frequency to Avoid: 33 MHz

3D3V_S0

SPI_WP_ROM

SPI_HOLD_ROM

R1831 A00 20160301

RN1801

CLKREQ_PCIE#1

1

4

2 3

SERIRQ PH: PDG: 8.2k CRB: 10k

RN1802

1 2 3

SRN10KJ-5-G P

RN1803

1 2 3

SRN10KJ-5-G P

1 2

R1806 10KR2J -3-GPR1806 10KR2J-3-GP

1 2

R1804 10KR2J -3-GPR1804 10KR2J-3-GP

12

C1804

SC6P50V2CN-1GP

R181610R2F-L-GP R181610R2F-L-GP

1 2

R183410R2F-L-GP R183410R2F-L-GP

1 2

R184010R2F-L-GP R184010R2F-L-GP

1 2

R183610R2F-L-GP R183610R2F-L-GP

1 2

R183510R2F-L-GP R183510R2F-L-GP

1 2

R18310R0402-PAD-1- GP R18310R0402-PAD- 1-GP

1 2

R18320R2J-2-GP

1 2

DY

TP1801TPAD14-OP-G P TP1801TPAD 14-OP-GP TP1807TPAD14-OP-G P TP1807TPAD 14-OP-GP

TP1804TPAD14-OP-G P TP1804TPAD 14-OP-GP TP1805TPAD14-OP-G P TP1805TPAD 14-OP-GP TP1806TPAD14-OP-G P TP1806TPAD 14-OP-GP

SERIRQ

SIO_RCIN#

4

CLKREQ_PCIE#0

CLKREQ_PCIE#3

4

CLKREQ_PCIE#5

CLKREQ_PCIE#4

1 2

R1820 10M R2J-L-GPR1820 10MR 2J-L-GP

X1802

41

2 3

XTAL-32D768KH Z-67-GP

82.30001.G11

GPP_C5/SML0ALER T# SPI_SI_CPU

SPI_CLK_CPU SPI_SO_CPU SPI_SI_CPU SPI_WP_CPU SPI_HOLD_CPU SPI_CS_CPU_N0 SPI_CS_CPU_N1

RTC_X2

RTC_X1

PCH Prim

3D3V_S5_PCH 3D3V_S5_PCH

12

R1842

DY

1KR2J-1-GP

12

R1839

DY

1KR2J-1-GP

XDP_SPI_IO2[99]

CPU1E

AU10

SPI0_CLK

AU12

SPI0_MISO

AT3

SPI0_MOSI

CPU_D1_TP

1

HDD_EN_PC H

1

CPU_D4_TP

1

CPU_D5_TP

1

CPU_D6_TP

1

PCI_CLK_LPC0 PCI_CLK_LPC1

Cardreader

12

C1803

SC6P50V2CN-1GP

4

AV11 AV13

AU4 AU6 AU8

W12

F12 D12 B12

BL10

BN8

WLAN

Strap

SPI0_IO2 SPI0_IO3 SPI0_CS0# SPI0_CS1# SPI0_CS2#

P9

GPP_D1

N8

GPP_D2

P3

GPP_D3 GPP_D21

V7

GPP_D22

N6

GPP_D0 CL_CLK

CL_DATA CL_RST#

GPP_A0/RCIN# GPP_A6/SERIRQ

SKYLAKE-Y-GP

R1845 22R2J-2-GP

1 2

LPC

R1844 22R2J-2-GPR1844 22R2J-2-GP

1 2

PEG_CLK3_CPU #[61] PEG_CLK3_CPU[61] CLKREQ_PCIE#3[61]

PEG_CLK4_CPU #[33] PEG_CLK4_CPU[33] CLKREQ_PCIE#4[33]

C1801

1 2

SC15P50V2JN-L- GP

C1802

1 2

SC15P50V2JN-L- GP

SPI - FLASH SMBUS, SMLINK

SPI - TOUCH

12

DY

82.30004.841

C LINK

EC1801

SC10P50V2JN-4GPDYEC1801

SC10P50V2JN-4GP

12

DY

23

SKYLAKE_ULX

LPC

EC1802

SC10P50V2JN-4GPDYEC1802

SC10P50V2JN-4GP

CLKREQ_PCIE#1

CLKREQ_PCIE#2

CLKREQ_PCIE#5 CLKREQ_PCIE#0

X1801

XTAL-24MHZ- 81-GP

4 1

PCH strap pin:

BOOT HALT

1KR2J-1-GP

0 = ENABLED 1 = DISABLED WEAK INTERNAL PU

LPC_LAD[3..0][24,68]

SPI_WP_CPU

SPI0_MOSI

This signal has a weak internal pull-up.

R1827

1 2

XDP

Strap

GPP_C5/SML0ALERT#

Strap

GPP_B23/SML1ALERT#/PCHHOT#

Strap

CLK_PCI_LPC [68 ] CLK_PCI_LPC_MEC [24]

XTAL24_IN

1 2

XTAL24_OUT

GPP_A1/LAD0/ESPI_IO0 GPP_A2/LAD1/ESPI_IO1 GPP_A3/LAD2/ESPI_IO2 GPP_A4/LAD3/ESPI_IO3

GPP_A5/LFRAME#/ESPI_CS#

GPP_A14/SUS_STAT#/ESPI_RESET#

GPP_A9/CLKOUT_LPC0/ESPI_CLK

GPP_A10/CLKOUT_LPC1

CPU1J

H35

CLKOUT_PCIE_N1

F35

CLKOUT_PCIE_P1

AV9

GPP_B6/SRCCLKREQ1#

J36

CLKOUT_PCIE_N2

G36

CLKOUT_PCIE_P2

BD10

GPP_B7/SRCCLKREQ2#

J38

CLKOUT_PCIE_N3

G38

CLKOUT_PCIE_P3

AV5

GPP_B8/SRCCLKREQ3#

H37

CLKOUT_PCIE_N4

F37

CLKOUT_PCIE_P4

AV7

GPP_B9/SRCCLKREQ4#

H39

CLKOUT_PCIE_N5

F39

CLKOUT_PCIE_P5

BC5

GPP_B10/SRCCLKREQ5#

BB10

GPP_B5/SRCCLKREQ0#

SKYLAKE-Y-GP

R1812

R1812 1MR2J-L2-GP

1MR2J-L2-GP

LPC_LAD[3..0]

5 OF 20

GPP_C0/SMBCLK

GPP_C1/SMBDATA

GPP_C2/SMBALERT#

GPP_C3/SML0CLK

GPP_C4/SML0DATA

GPP_C6/SML1CLK

GPP_C7/SML1DATA

GPP_A8/CLKRUN#

CLOCK SIGNALS

3

SKYLAKE_ULX

LPC_LAD0 LPC_LAD1 LPC_LAD2 LPC_LAD3

AC12 W6

GPP_C2/SMBALER T#

W8

SML0_SMBCLK

W4

SML0_SMBDATA

AC10

GPP_C5/SML0ALER T#

AA6

SML1_SMBCLK

AA4

SML1_SMBDATA

W10

GPP_B23/SML1ALERT #

BB6 BK11

BJ8 BG10 BP5 BP7 BJ6

BJ10 BF5 BH11

RTCRST_O N[24]

PCH Prim

12

R1833

DY

1KR2J-1-GP

12

R1841

DY

1KR2J-1-GP

LPC_LAD0_R LPC_LAD1_R LPC_LAD2_R LPC_LAD3_R LPC_LFRAME#_R SUS_STAT#/LPC PD#

PCI_CLK_LPC0 PCI_CLK_LPC1 CLKRUN#_R

CLKOUT_ITPXDP_N CLKOUT_ITPXDP_P

GPD8/SUSCLK

XCLK_BIASREF

SCD1U16V2KX-3GP

EC1811

DY

RN1806

8 7 6

SRN0J-7-GP -U

10 OF 20

XTAL24_IN

XTAL24_OUT

RTCX1 RTCX2

SRTCRST#

RTCRST#

12

10KR2J-3-GP

12

LPC_LAD0_R

1

LPC_LAD1_R

2

LPC_LAD2_R

3

LPC_LAD3_R

45

PCH_SMBDAT A [99] PCH_SMBCLK [99]

SML1_SMBCLK [24 ,26] SML1_SMBDATA [24,26]

R1808

1 2

0R0402-PAD-1- GP

A00 20160301

R1809

1 2

0R0402-PAD-1- GP

A00 20160301

SC6D8P25V1DN -GP

R1823

EC1810

J34 G34

SUSCLK_R

BA15 M1

L2 P1 BN19

BP18 BH18

BN12

Q1802

G

S

2N7002K-2-GP

84.2N702.J31

2ND = 84.2N702.031

3rd = 84.07002.I31

12

DY

XTAL24_IN XTAL24_OUT

XCLK_BIASREF RTC_X1

RTC_X2CLKREQ_PCIE#2 SRTC_RST #

RTC_RST#

D

(#514849)

Layout: Place at the open door area.

LPC_LFRAME# [24,68]

CLKRUN# [24]

R1811

1 2

0R2J-2-GP

1 2

2K7R1F-GP

21

12

G1802

GAP-OPEN

C1808

SC1U10V2KX-1GP

2

SUS_STAT#/LPC PD#

PCH strap pin:

SMBALERT# / GPP_C2

The internal pull-down is disabled after RSMRST# deasserts.

SML1_SMBDATA SML1_SMBCLK SML0_SMBDATA SML0_SMBCLK

Reserve by Intel MOW

GPP_B23/SML1ALERT #

GPP_C2/SMBALER T#

Intel PDG1.3 check list request

PCH_SMBDAT A PCH_SMBCLK

Intel PDG1.5 check list request

PCIE_CLK_XDP_P [9 9] SUS_CLK [24]

R1819

+VCCCLK5

RTC_AUX_S5

1

23

RN1805

RN1805 SRN20KJ-1-G P

SRN20KJ-1-G P

4

12

C1807

C1807 SC1U10V2KX-1G P

SC1U10V2KX-1G P

3D3V_S5_PCH

R1817

12

DY

10KR2J-3-GP

TLS Confidentiality

Low = Disable Intel ME Crypto TLS (Default)

*

High = Enable Intel ME Crypto TLS

RN1807

8 7 6

SRN2K2J-4-G P

SRN2K2J-1-G P

4

RN1811

R1810

8K2R2F-1-GP

CLKRUN#_R

PCIE_CLK_XDP_N [99]

8K2R2F-1-GP

1 2

SUSCLK_R

SRTC_RST # RTC_RST#

SCD1U16V2KX-3GP

12

EC1806

DY

to KBC, PL 100

1 2 3 45

12

R1847150KR2J-GP R1847150KR2J-G P

12

R18462K2R2J-2-GP R18462K2R2J-2-GP

23 1

SCD1U16V2KX-3GP

EC1808

3D3V_S5_PCH

3D3V_S0

EC1803

DY

1 2

SC4D7P50V2BN-GP

Wistron Corporation

21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih,

21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih, Taipei Hsie n 221, Taiwan, R.O.C .

Taipei Hsie n 221, Taiwan, R.O.C .

Title

CPU (LPC/SPI/SMBS/RTC/CLK)

Size Document Num ber Rev

A2

Date: Sheet of

Taipei Hsie n 221, Taiwan, R.O.C .

Drax SKL Y

1

18 109Monday, March 21, 201 6

A00

5

4

3

2

1

SSID = PCH

7 OF 20

CPU1G

SKYLAKE_ULX

HDA_SYNC HDA_BITCLK

D D

C C

HDA_SDIN0[27]

TP1903TPAD14-OP-GP TP1903TPAD14-OP-GP

SPKR[27]

HDA_SDOUT HDA_SDIN0

HDA_RST#

1

BJ19

HDA_SYNC/I2S0_SFRM

BK18

HDA_BLK/I2S0_SCLK

BK16

HDA_SDO/I2S0_TXD

BL15

HDA_SDI0/I2S0_RXD

BL17

HDA_SDI1/I2S1_RXD

BL19

HDA_RST#/I2S1_SCLK

V5

GPP_D23/I2S_MCLK

BL12

I2S1_SFRM

BK14

I2S1_TXD

AT13

GPP_F1/I2S2_SFRM

AT11

GPP_F0/I2S2_SCLK

AP11

GPP_F2/I2S2_TXD

AT5

GPP_F3/I2S2_RXD

V3

GPP_D19/DMIC_CLK0

V11

GPP_D20/DMIC_DATA0

U12

GPP_D17/DMIC_CLK1

U8

GPP_D18/DMIC_DATA1

AV3

GPP_B14/SPKR

SKYLAKE-Y-GP

Strap

AUDIO

Strap

SKYLAKE_ULX

SDIO/SDXC

GPP_G1/SD_DATA0 GPP_G2/SD_DATA1 GPP_G3/SD_DATA2 GPP_G4/SD_DATA3

GPP_A17/SD_PWR_EN#/ISH_GP7

GPP_A16/SD_1P8_SEL

PCH strap pin:

7 OF 20

GPP_G0/SD_CMD

GPP_G5/SD_CD# GPP_G6/SD_CLK

GPP_G7/SD_WP

SD_RCOMP

GPP_F23

AH9 AH11 AG12 AF9 AF11 AG8 AG10

GPP_G7/SD_WP

AE12 BL4

GPP_A16/SD_1P8_SEL

BN4 BF1

AJ8

SD_RCOMP

R1903 200R2F-L-GPR1903 200R2F-L-GP

1 2

SD_CMD_CPU [33] SD_D0_CPU [33] SD_D1_CPU [33] SD_D2_CPU [33] SD_D3_CPU [33]

SD_CD#_CPU [33] SD_CLK_CPU [33]

SD_PWR_EN#_CPU [33]

1

TP1901 TPAD14-OP-GPTP1901 TPAD14-OP-GP

TP1902 TPAD14-OP-GPTP1902 TPAD14-OP-GP

NO REBOOT

R1906 33R2J-2-GPR1906 33R2J-2-GP

HDA_SPKR

Low = Enable (Default) High = Disable

*

HDA_CODEC_BITCLK[27] HDA_CODEC_SYNC[27]

1 2

R1905 33R2J-2-GPR1905 33R2J-2-GP

1 2

The internal pull-down is disabled after PLTRST# deasserts

B B

PCH strap pin:

Flash Descriptor Security Overide/ Intel ME Debug Mode

HDA_SDOUT

Low = Default High = Enable

The internal pull-down is disabled after PLTRST# deasserts

A A

5

*

HDA_CODEC_SDOUT[27]

ME_UNLOCK[24]

3D3V_S0

R1901 1KR2J-1-GP

1 2

DY

+VCCHDA

R1918 1KR2J-1-GP

1 2

DY

R1919 1KR2J-1-GP

1 2

DY

EC1901

4

1 2

DY

R1902 33R2J-2-GPR1902 33R2J-2-GP

1 2

R1907 1KR2J-1-GPR1907 1KR2J-1-GP

1 2

SPKR

HDA_SDOUT

HDA_CODEC_BITCLK

SC10P50V2JN-4GP

3

HDA_BITCLK HDA_SYNC

HDA_SDOUT HDA_SDOUT

3D3V_CARD

SD_CMD_CPU SD_D0_CPU SD_D1_CPU SD_D2_CPU SD_D3_CPU

SD_CLK_CPU

Title

CPU (AUDIO/SDIO)

Size Document Number Rev

A4

Date: Sheet of

2

R1904 49K9R2F-L-GP

CPU_SD

R1908 49K9R2F-L-GP

CPU_SD

R1909 49K9R2F-L-GP

CPU_SD

R1910 49K9R2F-L-GP

CPU_SD

R1912 49K9R2F-L-GP

CPU_SD

R1913 49K9R2F-L-GP

CPU_SD

Drax SKL Y

12 12 12 12 12

12

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

19 109Thursday, March 17, 2016

1

A00

5

4

3

2

1

SSID = PCH

RN2010

I2C0_SDA I2C0_SCL

6 OF 20

CPU1F

BC3

GPP_B15/GSPI0_CS#

MD_ID0 MD_ID1 MD_ID2 MD_ID3

AW10

GPP_B16/GSPI0_CLK

AW6

GPP_B17/GSPI0_MISO

BB4

GPP_B18/GSPI0_MOSI

BB2

GPP_B19/GSPI1_CS#

AW12

GPP_B20/GSPI1_CLK

AW4

GPP_B21/GSPI1_MISO

AW8

GPP_B22/GSPI1_MOSI

AC8

GPP_C8/UART0_RXD

AA8

GPP_C9/UART0_TXD

AA10

GPP_C10/UART0_RTS#

AA12

GPP_C11/UART0_CTS#

AD5

GPP_C20/UART2_RXD

AD7

GPP_C21/UART2_TXD

AD3

GPP_C22/UART2_RTS#

AD9

GPP_C23/UART2_CTS#

AD11

GPP_C16/I2C0_SDA

AB3

GPP_C17/I2C0_SCL

AB9

GPP_C18/I2C1_SDA

AB11

GPP_C19/I2C1_SCL

AP3

GPP_F4/I2C2_SDA

AP7

GPP_F5/I2C2_SCL

AP5

GPP_F6/I2C3_SDA

AT7

GPP_F7/I2C3_SCL

AN4

GPP_F8/I2C4_SDA

AN6

GPP_F9/I2C4_SCL

SKYLAKE-Y-GP

Memory Down Strap

Micron_CC_2G4G&Samsung_BD_2G4G

DRAM_4G

DY

R2064

DY

R2064 1KR2J-1-GP

1KR2J-1-GP

1 2

R2065

1 2

1KR2J-1-GP

R2061

1 2

1KR2J-1-GP

Micron2G4G&Hynix2G4G

DRAM_2G

R2062

1 2

1KR2J-1-GP

Strap

3.3V

1.8V

3D3V_S5

1 2

DY

R2037 10KR2J-3-GP

1 2

DY

R2034 10KR2J-3-GP

TP2005TP2005

TP2006TP2006

1 2

DY

1 2

I2C0_SDA_TCH_PAD[65]

I2C0_SCL_TCH_PAD[65] FFS_INT2 [70]

BT_RADIO_DIS#

R204210KR2J-3-GP

DBC_PANEL_EN

R204710KR2J-3-GP R204710KR2J-3-GP R204410KR2J-3-GP R204410KR2J-3-GP

RTC_DET#

R203910KR2J-3-GP R203910KR2J-3-GP

1 1

BT_RADIO_DIS#[61]

GPP_B18/GSPI0_MOSI

CPU_B20_TP CPU_B21_TP GPP_B22/GSPI1_MOSI

3D3V_S0

3D3V_S5_PCH

DBC_PANEL_EN[55]

3D3V_S0

1 2 1 2 1 2

1 2

DY

R2036 10KR2J-3-GP

R2036 10KR2J-3-GP R2035 10KR2J-3-GPR2035 10KR2J-3-GP

D D

3D3V_S5_PCH

C C

PCH strap pin:

Boot BIOS Strap Bit BBS

Boot BIOS Destination

Low = SPI (Default)

*

High = LPC

The internal pull-down is disabled after PLTRST# deasserts

Need double confirm, GPIO table set to GPI if that's needed PH or PL

*

R2058

R2058 1KR2J-1-GP

1KR2J-1-GP

1 2

R2059

R2059 1KR2J-1-GP

1KR2J-1-GP

1 2

SKYLAKE_ULX

ISHLPSS

GPP_F10/I2C5_SDA/ISH_I2C2_SDA GPP_F11/I2C5_SCL/ISH_I2C2_SCL

GPP_D13/ISH_UART0_RXD/SML0BDATA

GPP_D14/ISH_UART0_TXD/SML0BCLK

GPP_D15/ISH_UART0_RTS#

GPP_D16/ISH_UART0_CTS#/SML0BALERT#

GPP_C12/UART1_RXD/ISH_UART1_RXD

GPP_C13/UART1_TXD/ISH_UART1_TXD GPP_C14/UART1_RTS#/ISH_UART1_RTS# GPP_C15/UART1_CTS#/ISH_UART1_CTS#

SX_EXIT_HOLDOFF#/GPP_A12/BM_BUSY#/ISH_GP6

Hynix2G4G & Samsung_BD_2G4G

R2056

R2056 1KR2J-1-GP

1KR2J-1-GP

1 2

MD_ID3 MD_ID2 MD_ID1 MD_ID0

Micron2G4G

R2063

1 2

1KR2J-1-GP

6 OF 20

P11

GPP_D9

T7

GPP_D10

T5

GPP_D11 GPP_D12

GPP_D5/ISH_I2C0_SDA GPP_D6/ISH_I2C0_SCL

GPP_D7/ISH_I2C1_SDA GPP_D8/ISH_I2C1_SCL

GPP_A18/ISH_GP0 GPP_A19/ISH_GP1 GPP_A20/ISH_GP2 GPP_A21/ISH_GP3 GPP_A22/ISH_GP4 GPP_A23/ISH_GP5

T11 P7

P5 T9

T3 AM7

AT9

LANLINK_STATUS

U10

ISH_UART0_T

U4

ISH_UART0_RT

U6

ISH_UART0_C

V9

ISH_UART1_R

AC6 AC4

ISH_UART1_RT

AB7

ISH_UART1_C

AB5 BF11

BD2 BJ1 BL3 BJ3 BD4 BJ4

I2C0_SDA I2C0_SCL

I2C1_SDA I2C1_SCL

GYRO_INTFFS_INT2

RTC_DET#

RTC_DET# [25]

R2001 0R0402-PAD-1-GPR2001 0R0402-PAD-1-GP

1 2

R2004 0R0402-PAD-1-GPR2004 0R0402-PAD-1-GP

1 2

A00 20160301 ISH

1

TP2003TP2003

1

TP2004TP2004

1

TP2007TP2007

1

TP2008TP2008

1

TP2009TP2009

1

TP2010TP2010

1

TP2011TP2011

KB_DISABLE [24,66] GSEN_INT1 [66] GSEN_INT2 [66] GSEN2_INT1_C [66,70] GSEN2_INT2_C [66,70]

1

TP6603TP6603

GYRO_DRDY [66]

KB_DISABLE

RAM ID bit order is DRAM_ID2,DRAM_ID1,DRAM_ID0

Vender RAM_ID Wistron PN

Micron

Hynix

Micron NX80R$CC MT41K256M16T

X000

X001

X010

X011

I2C1_SDA I2C1_SCL

12

DY

NX80R$CB

NX80R$AB H5TC4G63CFR-PBA 2G

NX80R$BD K4B4G1646E-BYK0Samsung 2G 1600MHz

RN2010

4

ISH

SRN1KJ-7-GP

R2002 1KR2J-1-GP

DY

R2003 1KR2J-1-GP

DY

SENSOR_I2C_SDA [66,70] SENSOR_I2C_SCL [66,70]

R203810KR2J-3-GPDYR203810KR2J-3-GP

MT41K256M16LY-107:N

3D3V_S0

23 1

3D3V_S0

12 12

To G Sensor on MB

Mfr. PN

Capacity

2G2G1600MHz

Freq

1600MHz

B B

A A

5

4

A00 20160302

Hynix

Micron NX80R$CC MT41K256M16T

Samsung NX80R$BD K4B4G1646E-BYK0 4G 1600MHz

3

X101

X110

X111

NX80R$CBMicron

MT41K256M16LY-107:NX100

1600MHz

1600MHzNX80R$AB H5TC4G63CFR-PBA 4G

4G4G1600MHz

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU (LPSS/ISH/I2C/UART/GPIO)

Size Document Number Rev

C

Date: Sheet of

2

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

Drax SKL Y

1

A00

20 109Thursday, March 17, 2016

A00

5

4

3

2

1

SSID = PCH

16 OF 20

CPU1P

1D0V_S5

D D

+VCCDSW _1P0

1D0V_S5

+VCCAMPHYPLL_1P0

1D0V_S5

C C

+VCCPDSW_3P3

+VCCPAZIO (3.3)

+VCCDSW _3P3

+VCCHDA

3D3V_S5_PCH

1D0V_S5

3D3V_S5_PCH

1D0V_S5

AH18 AH19 AK18

AL18

AE18 AE19

AF18 AF19

AR16

AT16

AM1

AA18 AA19

AH13 AH15

AL15

AM13

AT23

AV22

AT15

AV15 AA21

AA23 AK23

AL23 AN23 AR23

AH21 AK21

AR21

AT21

AL2

T15 T16

V15 V16

R15 R16

V1

W2

T1

U2

SKYLAKE-Y-GP

VCCPRIM_1P0 VCCPRIM_1P0 VCCPRIM_1P0 VCCPRIM_1P0

VCCPRIM_CORE VCCPRIM_CORE VCCPRIM_CORE VCCPRIM_CORE VCCPRIM_CORE VCCPRIM_CORE

DCPDSW_1P0 DCPDSW_1P0

VCCMPHYAON_1P0 VCCMPHYAON_1P0

VCCMPHYGT_1P0 VCCMPHYGT_1P0 VCCMPHYGT_1P0 VCCMPHYGT_1P0

VCCAMPHYPLL_1P0 VCCAMPHYPLL_1P0

VCCAPLL_1P0 VCCAPLL_1P0

VCCPRIM_1P0 VCCPRIM_1P0

VCCDSW_3P3 VCCDSW_3P3

VCCHDA VCCHDA

VCCSPI VCCSPI

VCCSRAM_1P0 VCCSRAM_1P0 VCCSRAM_1P0 VCCSRAM_1P0 VCCSRAM_1P0 VCCSRAM_1P0

VCCPRIM_3P3 VCCPRIM_3P3

VCCPRIM_1P0 VCCPRIM_1P0

VCCAPLLEBB VCCAPLLEBB

Internal VR

1.29A

2.1A

SKYLAKE_ULX

PCH POWER

Internal VR

16 OF 20

VCCPGPPA VCCPGPPA VCCPGPPB VCCPGPPB VCCPGPPC VCCPGPPC VCCPGPPD VCCPGPPD VCCPGPPE VCCPGPPE VCCPGPPF VCCPGPPF VCCPGPPG VCCPGPPG

VCCPRIM_3P3 VCCPRIM_3P3

VCCPRIM_1P0 VCCPRIM_1P0

VCCATS VCCATS

VCCRTCPRIM_3P3 VCCRTCPRIM_3P3

VCCRTC VCCRTC

DCPRTC DCPRTC

VCCCLK1 VCCCLK1

VCCCLK2 VCCCLK2

VCCCLK3 VCCCLK3

VCCCLK4 VCCCLK4

VCCCLK5 VCCCLK5

VCCCLK6 VCCCLK6

GPP_B0/CORE_VID0 GPP_B1/CORE_VID1

AT1 AU2 AV1 AW2 AH1 AJ2 AF1 AG2 AA2 AB1 AN2 AP1 AN15 AP13

AC2 AD1

AA15 AA16

AE15 AE16

AK19 AL19

AR19 AT19

AT18 AV18

V18 Y18

V19 Y19

V23 Y23

V21 Y21

R21 R23

R19 T19

BA13 BB12

VCCRTCEXT

V0.85A_VID0 V0.85A_VID1

1D0V_S5

+VCCCLK2

1D0V_S5

+VCCCLK4

+VCCCLK5

1D0V_S5

3D3V_S5_PCH

1D8V_S5 3D3V_S5_PCH

3D3V_S5_PCH

1D0V_S5

1D8V_S5

3D3V_S5_PCH

+VCCRTC

C2107

1 2

SCD1U16V2KX-3GP

TP2101TP2101

1

TP2102TP2102

1

+VCCCLK2 +VCCCLK4

SC22U6D3V3MX-1-GP

12

C2139

SC22U6D3V3MX-1-GP

12

C2141

12

C2138

SC22U6D3V3MX-1-GP

12

C2140

SC22U6D3V3MX-1-GP

B B

A A

3D3V_S5

R2139

1 2

0R0402-PAD-1-GP

1D8V_S5

1D0V_S5

0R0402-PAD-1-GP

A00 20160301

DY

R2132 0R2J-2-GP

1 2

R2128

1 2

0R0402-PAD-1-GP

A00 20160301

R2106 0R0603-PAD-1-GP-UR2106 0R0603-PAD-1-GP-U

1 2

R2103 0R0603-PAD-1-GP-UR2103 0R0603-PAD-1-GP-U

1 2

R2104 0R0603-PAD-1-GP-UR2104 0R0603-PAD-1-GP-U

1 2

R2118 0R0603-PAD-1-GP-UR2118 0R0603-PAD-1-GP-U

1 2

+VCCHDA

+VCCRTCRTC_AUX_S5

+VCCCLK2

+VCCCLK5

+VCCCLK4

+VCCAMPHYPLL_1P0

A00 20160303

5

Layout Note:

D1uF: C2102 near V1 C2103 near T1, T15 C2108 near AH13, AH15 C2110 near R15, R16 C2116 near R21 1uF: C2104 near T1, T15 22uF: C2105 near T1, T15

Layout Note:

D1uF: C2128 near AK19 C2120 near AT15 C2130 near AL15 C2131 near AR19 1uF: C2134 near AK19 C2129 near AR19 C2132 near AE15 C2133 near AL2

4

1D0V_S51D0V_S5 1D0V_S5 1D0V_S5

12

C2102

SCD1U16V2KX-3GP

C2128

SCD1U16V2KX-3GP

12

C2103

C2134

SC1U10V2KX-1GP

SCD1U6D3V1KX-GP

3D3V_S5_PCH

12

C2104

C2120

12

SC1U10V2KX-1GP

+VCCDSW _1P0

SCD1U6D3V1KX-GP

C2105

SC22U6D3V3MX-1-GP

+VCCCLK5

12

C2133

3

SC1U10V2KX-1GP

C2108

+VCCDSW _3P3 1D8V_S53D3V_S5_PCH

12

C2110

C2116

SCD1U6D3V1KX-GP

12

C2130

C2116

SCD1U6D3V1KX-GP

+VCCRTC

12

C2132

12

SC1U10V2KX-1GP

C2131

SCD1U16V2KX-3GP

C2129

SC1U10V2KX-1GP

2

SCD1U6D3V1KX-GP

12

+VCCCLK5 +VCCAMPHYPLL_1P0

SC22U6D3V3MX-1-GP

12

C2143

Title

Size Document Number Rev

A3

Date: Sheet of

SC22U6D3V3MX-1-GP

12

C2142

PCH ( POWER1)

SC22U6D3V3MX-1-GP

12

C2144

Drax SKL Y

SC22U6D3V3MX-1-GP

12

C2145

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

21 109Thursday, March 17, 2016

1

A00

5

D D

C C

4

3

2

1

Blanking

B B

Wistron Confidential document, Anyone can not Duplicate, Modify, Forward or any other purpose application without get Wistron permission

Wistron Corporation

A A

Title

(Reserved)

Size Document Number Rev

Size Document Number Rev A4

A4

Thursday, March 17, 2016

Date: Sheet of

5

4

3

Date: Sheet of

2

(Reserved)

Drax SKL Y

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

A00

22 109

1

A00

5

D D

C C

4

3

2

1

Blanking

B B

Wistron Corporation

A A

Title

Size Document Number Rev

Size Document Number Rev A4

A4

Thursday, March 17, 2016

Date: Sheet of

5

4

3

Date: Sheet of

2

(Reserved)

Drax SKL Y

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

A00

23 109

1

A00

5

4

3

2

1

SSID = KBC

R2402

2D2R3-1-U-GP

12

C2410SCD1U16V2K X-3GP C2410SCD1U16V2KX-3GP

C2409SCD1U16V2K X-3GP C2409SCD1U16V2KX-3GP

KBSIN0/GPIOA0/N2TCK

KBSIN2/GPIOA2 KBSIN3/GPIOA3 KBSIN4/GPIOA4 KBSIN5/GPIOA5 KBSIN6/GPIOA6 KBSIN7/GPIOA7

KBSOUT1/GPIOB1/TCK KBSOUT2/GPIOB2/TMS

KBSOUT3/GPIOB3/TDI

KBSOUT4/GPOB4

KBSOUT5/GPIOB5/TDO

KBSOUT7/GPIOB7 KBSOUT8/GPIOC0

LAD0/GPIOF1 LAD1/GPIOF2 LAD2/GPIOF3 LAD3/GPIOF4 LCLK/GPIOF5

LFRAME#/GPIOF6

LRESET#/GPIOF7

GPIOC6/F_CS0#

GPIOC7/F_SCK

GPIO30/F_WP#/RTS1#

PSL_IN1#/GPI70

PSL_OUT#/GPIO71

ECSCI#/GPIO54

EXT_RST#

KBRST#/GPIO86

VSBY VBKUP VCORF

SERIRQ/GPIOF0

GPIO24

GPIO36/TB3/CTS1#

GPIO44/SCL4B PSL_IN4#/GPI43 PSL_IN3#/GPI42

GPIO34/SIN1/CIRRXL

AGND

R2428

1 2

0R0402-PAD-1-GP

3D3V_AUX_KBC

R2403

12

54 55 56 57 58 59 60 61

53 52 51 50 49 48 47 43 42 41 40 39 38 37 36 35 34 33

126 127 128 1 2 3 7

90 92 109 80 87 86 91 77

73 93 74

29 85 122

75 114 44 13

PECI

125 6 15

21 20 17 23

113 14

5

GND

18

GND

45

GND

78

GND

89

GND

116

GND

103

12

DY

1 2

12

C2411SC2D2U10V3KX-1GP C2411SC2D2U10V3KX-1GP

KROW0 KROW1 KROW2 KROW3 KROW4 KROW5 KROW6 KROW7

KCOL0 KCOL1 KCOL2 KCOL3 KCOL4 KCOL5 KCOL6 KCOL7 KCOL8 KCOL9 KCOL10 KCOL11 KCOL12 KCOL13 KCOL14 KCOL15 KCOL16

LPC_LAD0 LPC_LAD1 LPC_LAD2 LPC_LAD3

PLT_RST#_EC

EC_SPI_CS#_C EC_SPI_CLK_C

BAT_IN# EC_SPI_DI_C EC_SPI_DO_C

SUSCLK_KBC

PSL_IN1# PSL_IN2# PSL_OUT#

ECSCI#_KBC ECRST#

EC_VBKUP KBC_VCORF PECI

ECSMI#_KBC

LID_CLOSE#

EC_AGND

C2421

C2421 SC47P50V2JN-3GP

SC47P50V2JN-3GP

VBAT

12

R2404

PCB_VER

PCB_VER_AD

C2402

12

EC_AGND

H_PROCHOT# [4,44,46]

R2404 64K9R2F-1-GP

64K9R2F-1-GP

12

R2406

R2406 100KR2F-L1-GP

100KR2F-L1-GP

DY

1 2

EC_AGND

SCD1U16V2KX-3GP

KROW[0..7] [65]

KCOL[0..16] [65]

LPC_LAD[3..0] [18 ,68]

CLK_PCI_LPC_MEC [18] LPC_LFRAME# [18,68]

R2419 0R0402-PAD-1-GPR2419 0R0402-PAD-1-GP

1 2

R2420 10R2F-L-GPR2420 10R2F-L-GP

1 2

R2422 10R2F-L-GPR2422 10R2F-L-GP

1 2

R2423 10R2F-L-GPR2423 10R2F-L-GP

1 2

R2440

1 2

0R0402-PAD-1-GP

Layout Note:

Need very close to EC

A00 20160302

SIO_RCIN# [18]

R2458

1 2

0R0402-PAD-1-GP

SERIRQ [18] RSMRST#_KBC [17,99] SIO_SLP_S4# [17,40,51]

LID_CLOSE# [70] ME_UNLOCK [19]

PWR_CHG_AD_OFF [43] S5_ENABLE [40]

A00 20160302

R2437

R2437 0R0402-PAD-1-GP

0R0402-PAD-1-GP

Layout Note:

Connect GND and AGND planes via either 0R resistor or connect directly.

C2403

VBAT

12

MODEL

12

1 2

EC_AGND

SCD1U16V2KX-3GP

PCB VERSION A/D(PIN98) PULL-LOW RESISTOR PULL-HIGH RESISTOR VOLTAGE

X01 X02 X03 2.304V

A00

Reserved

Reserved 100.0K 215.0K 1.048V

100.0KX00

100.0K

100.0K 1.358V

10.0K

20.0K

33.0K

47.0K

64.9K

76.8

100.0K

143.0K

174.0KReserved 100.0K

3.0V

2.75V

2.48V

2.24V

2.0V

1.87V

1.65VReserved

1.204V

MODEL_ID_DET

R2405

R2405 10KR2F-2-GP

10KR2F-2-GP

R2407

R2407 100KR2F-L1-GP

100KR2F-L1-GP

MODEL_ID_DET(GPIO07)

SKL Y TBD TBD TBD 2.702V TBD TBD TBD TBD KBL Y TBD100.0K TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD

ECSCI#_KBC ECSMI#_KBC

PULL-LOW RESISTOR PULL-HIGH RESISTOR VOLTAGE

100.0K 3.0V

100.0K

1 2 1 2

10.0K(64.10025 .6DL)

13.7K(64.13725 .6DL)

17.8K(64.17825 .6DL)

22.1K(64.22125 .6DL)

27.0K(64.27025 .6DL)

32.4K(64.32425 .6DL)

37.4K(64.37425 .6DL)

43.2K(64.43225 .6DL)

57.6K(64.57625 .6DL)

64.9K(64.64925 .6DL)

73.2K(64.73225 .6DL) 1.905V

82.5K(64.82525 .6DL) 1.808V

93.1K(64.93125 .6DL) 107K(64.10735.6DL) 120K(64.12035.6DL) 137K(64.13735.6DL) 154K(64.15435.6DL) 200K(64.20035.6DL) 1.099V 232K(64.23236.6DL)

R24080R0402-PAD-1-GP R24080R040 2-PAD-1-GP

SIO_EXT_SCI#_R [16]

R24090R0402-PAD-1-GP R24090R040 2-PAD-1-GP

SIO_EXT_SMI#_R [8]

A00 20160301

3D3V_AUX_KBC

4

RN2404

4

3D3V_AUX_KBC

DY

RN2403

3D3V_S0

4

3D3V_S5

1 2

DY

RN2402

1

8

2

7

3

6

4 5

SRN100KJ-5-GP

S

R2434

DY

0R2J-2-GP

1 2

3D3V_AUX_KBC

D

KBC Nuvoton NPCE285PA0DX

Drax SKL Y

Monday, March 21, 2016

1

R2419 R2440 A00 20160302

SPI_CS_ROM_N0 [18,25] SPI_CLK_ROM [18,25] CAP_LED# [65] BAT_IN# [43,44] SPI_SI_ROM [18,25] SPI_SO_ROM [18,25] PM_SUSACK# [17] SUS_CLK [18]

3D3V_AUX_S5 RTC_AUX_S5

1 2

R2429

C2422

SC100P50V2JN-3GPDYC2422

SC100P50V2JN-3GP

43R2J-GP

12

DY

RN2401

BAT_SCL BAT_SDA

ECRST# BAT_IN#

R2433

R2433 20KR2F-L-GP

20KR2F-L-GP

AC_IN#

VOL_DOWN# FAN_TACH1

TOUCH_PANEL_INTR#

VOL_UP#

WIFI_RF_EN

USB_PWR_EN#

TP_ON# TP_LOCK#_C LID_CLOSE#

KBC_ON#_GATE

R2416

1 2

0R0402-PAD-1-GP

C2415

DY

SC220P50V2KX-3GP

1 2

C2416

SC1U10V2KX-1GP

1 2

H_PECI [4]

Layout Note:

Need very close to EC

3D3V_AUX_S5

R2439

10KR2J-3-GP

PURE_HW_SHUTDOWN#[26,40]

3

PLT_RST# [17,26,33,37,61,68]

A00 20160302

Power Switch Logic(PSL)

KBC_PWRBTN#[66,99]

AC_IN#[44]KBC_DPWROK[17]

R2424

0R2J-2-GP

12

1 2

DY

E

DY

B

Q2404

LMBT3906LT1G-1-GP

84.T3906.E11

C

12

C2418

C2418 SC1U10V2KX-1GP

SC1U10V2KX-1GP

R2427

1 2

0R0402-PAD-1-GP

A00 20160302

R2430

1 2

0R0402-PAD-1-GP

A00 20160302

PSL_OUT#

ECRST#

3D3V_AUX_S5

1 2

R2432

1 2

1KR2J-1-GP

2

R2425

R2425 330KR2J-L1-GP

330KR2J-L1-GP

PSL_IN2#

PSL_IN1#

3D3V_AUX_S5 3D3V_AUX_S5

R2431

R2431 330KR2J-L1-GP

330KR2J-L1-GP

KBC_ON#_GATE_L

1 2

RN2401

1 2 3

SRN4K7J-8-GP

1

2 3

SRN10KJ-5-GP

R2413 100KR2J-1-GP

1 2

1 2 3

SRN10KJ-5-GP

R2443 10KR2J-3-GPR2443 10KR2J-3-GP

1 2

R2446 10KR2J-3-GPR2446 10KR2J-3-GP

1 2

R2451 10KR2J-3-GPR2451 10KR2J-3-GP

1 2

R2412 100KR2J-1-GP

C2417 SCD1U16V2KX-3GPC2417 SCD1U16V2KX-3GP

1 2

G

D

Q2402

Q2402 DMP2130L-7-GP

DMP2130L-7-GP

D

84.02130.031

2ND = 84.03413.A31

Q2403

G

S

2N7002K-2-GP

84.2N702.J31

2ND = 84.2N702.031

Title

Size Document Number Rev

Size Document Number Rev Custom

Custom

Custom Date: Sheet of

Date: Sheet of

2.902V

2.801V

2.598V

2.492V

2.402V

2.201V49 .9K(64.49925.6DL)

2.093V

2.001V

1.709V

1.594V

1.499V

1.392V

1.299V

0.994V

3D3V_AUX_KBC

12

R2436

R2436 10KR2J-3-GP

10KR2J-3-GP

S5_ENABLE

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd ., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd ., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

24 109

A00

VBAT

3D3V_AUX_KBC_VCC

D D

C C

B B

A A

+V1.00U_CPU

1D0V_S5

Layout Note:

Need very close to EC

C2412

ALL_SYS_PWRGD assert, delay 10ms; PCH_PWROK assert.

3D3V_S0

12

SCD1U16V2KX-3GP

R2401

1 2

0R2J-2-GP

R2444

1 2

DY

0R2J-2-GP

12

C2413

DY

SC2D2U10V3KX-1GP

EC_AGND

A00 20160302

R2410

LCD_TST[55]

TP_LOCK#[65]

1 2

0R0402-PAD-1-GP

R2417

1 2

0R0402-PAD-1-GP

A00 20160301

R2414

LCD_TST_EN[55]

ALL_SYS_PWRGD de-assert, delay 100ms; SYS_PWROK assert.

1 2

0R0402-PAD-1-GP

A00 20160302

LVDS backlight Control from PS8625

INT_TP#[4,65]

R2426 R2441 A00 20160302

R2450

1 2

R2411

L_BKLT_EN[8]

eDP backlight Control connect from PCH to eDP side directly

1 2

DY

5

EC_VTT

12

C2401

SCD1U16V2KX-3GP

AD_IA[44]

C2414

SCD1U16V2KX-3GP

1 2

PCH_PWROK[1 7,26]

SIO_SLP_SUS#[17,41,4 9,53]

SIO_SLP_S0#[17]

USB_PWR_EN#[35,66] AD_IA_HW[44]

SML1_SMBCLK[18,26]

SML1_SMBDATA[18,26]

TP_ON#[65] RTCRST_ON[18]

VOL_DOWN#[66]

ALL_SYS_PWRGD[17,40,50]

KB_DISABLE[20,66 ]

AD_IA_HW2[44]

SIO_PWRBTN#[17,99]

SIO_SLP_S3#[17,27,40,51]

HDMI_EC_DET#[57]

VD_IN1[26]

VD_OUT1#[26] AC_PRESENT[17]

SYS_PWROK[17,99]

KB_CLOSE#_2[66]

WIFI_RF_EN[61]

PM_SUSWARN#[17]

TOUCH_PANEL_INTR#[55]

R2426 0R0402-PAD-1-GPR2426 0R0402-PAD-1-GP

1 2

EC_MUTE#[27]

BLON_OUT [ 55]

0R2J-2-GP

12

R2447

100KR2J-1-GP

PSID_EC[43]

BAT_SCL[43,44] BAT_SDA[43,44]

TPCLK[65]

TPDATA[65]

VOL_UP#[66]

TP2404TP2404

BEEP[27]

E51_TxD[61]

CLKRUN#[18]

C2404

SCD1U16V2KX-3GP

R2415

1 2

0R0402-PAD-1-GP

R2435 0R2J-2-GP

TP2402TP2402

1

TP2403TP2403 TP2406TP2406

1 2

R2449

R2441

1 2

0R0402-PAD-1-GP

L_BKLT_EN_EC

PROCHOT_EC

R2442

100KR2J-1-GP

12

C2405

DY

SC2D2U10V3KX-1GP

EC_AGND

PCB_VER_AD

SIO_SLP_S0#_R MODEL_ID_DET

BAT_SCL BAT_SDA

PROCHOT_EC LCD_TST_R

TP_LOCK#_C

1 2

DY

1

BATT_WHITE_LED#

1

CHG_AMBER_LED#

1

PURE_KBCT8

1KR2J-1-GP

TP_WAKE_KBC#

L_BKLT_EN_EC

12

DY

C2406SCD1U16V2K X-3GP C2406SCD1U16V2KX-3GP

KBC24

19

VCC

46

VCC

76

VCC

88

VCC

115

VCC

102

AVCC

4

VDD

EC_VTT

12

VTT

97

GPIO90/AD0

98

GPIO91/AD1

99

GPIO92/AD2

100

GPIO93/AD3

108

GPIO05/AD4

96

GPIO04/AD5

95

GPIO03/EXT_PURST#/AD6

94

GPIO07/AD7/VD_IN2

101

GPIO94/DA0

105

GPIO95/DA1

106

GPIO96/DA2

107

GPIO97/DA3

70

GPIO17/SCL1/N2TCK

69

GPIO22/SDA1/N2TMS

67

GPIO73/SCL2/N2TCK

68

GPIO74/SDA2/N2TMS

119

GPIO23/SCL3/N2TCK

120

GPIO31/SDA3/N2TMS

24

GPIO47/SCL4A/N2TCK

28

GPIO53/SDA4A/N2TMS

26

GPIO51/TA3/N2TCK

123

GPIO67/SOUT1/N2TMS

72

GPIO37/PSCLK1

71

GPIO35/PSDAT1

10

GPIO26/PSCLK2

11

GPIO27/PSDAT2

25

GPIO50/PSCLK3

BLON_OUT_RBLON_OUT

27

FAN_TACH1

FAN_PWM1 LCD_TST_EN_R

WIFI_RF_EN_R

GPIO52/PSDAT3

31

GPIO56/TA1

117

GPIO20/TA2/IOX_DIN_DIO

63

GPIO14/TB1

64

GPIO01/TB2

32

GPIO15/A_PWM

118

GPIO21/B_PWM

62

GPIO13/C_PWM

65

GPIO32/D_PWM

22

GPIO45/E_PWM/DTR1#_BOUT1

16

GPIO40/F_PWM/1_WIRE/RI1#

81

GPIO66/G_PWM/PSL_GPIO66

VD1_EN#

66

GPO33/H_PWM/VD1_EN#

104

GPIO80/VD_IN1

110

GPIO82/IOX_LDSH/VD_OUT1

112

GPIO84/IOX_SCLK/VD_OUT2

84

GPIO77/SPI_MISO

83

GPIO76/SPI_MOSI

82

GPIO75/SPI_SCK

79

GPIO02/SPI_CS#

124

GPIO10/LPCPD#

121

GPIO85/GA20

111

GPIO83/SOUT_CR

9

GPIO65/SMI#

8

GPIO11/CLKRUN#

30

GPIO55/CLKOUT/IOX_DIN_DIO

NPCE285PA0DX-GP

071.00285.000G

EC_GPIO47 High Active

R2438

R2438 0R2J-2-GP

0R2J-2-GP

1 2

DY

Q2401

G

S

2N7002K-2-GP

84.2N702.J31

2ND = 84.2N702.031

12

DY

C2407SCD1U16V2K X-3GPDYC2407SCD1U16V2K X-3GP

D

A00 20160301

1 2

0R0603-PAD-1-GP-U

12

DY

C2408SCD1U16V2K X-3GPDYC2408SCD1U16V2K X-3GP

KBSIN1/GPIOA1/N2TMS

KBSOUT0/GPOB0/SOUT_CR/JENK#

KBSOUT6/GPIOB6/RDY#

KBSOUT9/GPOC1/SDP_VIS# KBSOUT10/P80_CLK/GPIOC2 KBSOUT11/P80_DAT/GPIOC3

KBSOUT12/GPO64/TEST#

KBSOUT13/GP(I)O63/TRIST# KBSOUT14/GP(I)O62/XORTR# KBSOUT15/GPIO61/XOR_OUT

GPIO60/KBSOUT16/DSR1# GPIO57/KBSOUT17/DCD1#

GPIO41/F_WP#/PSL_GPIO41

GPIOC5/F_SDIO/F_SDIO0

GPIOC4/F_SDI/F_SDIO1

GPIO81/F_WP#/F_SDIO2

GPIO00/32KCLKIN/F_SDIO3

PSL_IN2#/GPI06/EXT_PURST#

GPIO46/SDA4B/CIRRXM

GPIO87/CIRRXM/SIN_CR

H_PROCHOT#_EC

A00 20160302

4

5

4

3

2

1

Main Func = SPI Flash

3D3V_S5_PCH

12

R2515

R2515 0R0402-PAD-1-GP

0R0402-PAD-1-GP

12

C2502

C2502 SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

DY

A00 20160302

R2501

4K7R2J-2-GP

3D3V_S5_PCH

1 2

C2501

C2501 SC10U10V5KX-2GP

SC10U10V5KX-2GP

SPI Flash ROM(16M) for PCH

D D

3D3V_SPIVCC1

12

DY

SPI251

SPI_CS_ROM_N0[18,24]

SPI_SO_ROM[18,24] SPI_WP_ROM[18]

C C

B B

R2507 10R2F-L-GPR2507 10R2F-L-GP

1 2

R2508 10R2F-L-GPR2508 10R2F-L-GP

1 2

SPI_CS_ROM_N1[18]

SPI_SO_ROM[18,24]

SPI_WP_ROM[18]

SPI_WP_ROM_R

12

EC2502

DY

DY DY

DY

SC4D7P50V2BN-GP

DY

SC4D7P50V2BN-GP

R2513 10R2F-L-GP

1 2

R2514 10R2F-L-GP

1 2

EC2504

R2502

4K7R2J-2-GP

SPI1_SO_ROM_R

SPI1_WP_ROM_R

12

DY

1 2 3

3D3V_S5_PCH

DY

1 2

CS# SO/SIO1 SIO2 GND4SI/SIO0

MX25L12873FM2I-10G-GP

72.12873.001

1 2 3 4

3D3V_SPIVCC1

8

VCC

SIO3

SCLK

SPI252

CS# SO/SIO1 SIO2 GND

MX25L3273EM2I-10G-GP

72.25327.A01

7 6 5

DY

SPI_HOLD_ROM_RSPI_SO_ROM_R SPI_CLK_ROM_R SPI_SI_ROM_R

EC2501

VCC

SIO3

SCLK

SI/SIO0

12

DY

SC4D7P50V2BN-GP

8

SPI1_HOLD_ROM_R

7

SPI1_CLK_ROM_R

6

SPI1_SI_ROM_R

5

R2503 10R2F-L-GPR2503 10R2F-L-GP

1 2

R2505 10R2F-L-GPR2505 10R2F-L-GP

1 2

R2506 10R2F-L-GPR2506 10R2F-L-GP

1 2

12

EC2503

DY

SC10P50V2JN-4GP

3D3V_SPIVCC2

12

DY

EC2506

SC4D7P50V2BN-GP

SPI_HOLD_ROM [18] SPI_CLK_ROM [18,24] SPI_SI_ROM [18,24]

3D3V_SPIVCC2

12

C2505

SC10U10V5KX-2GP

R2509 10R2F-L-GP

R2509 10R2F-L-GP R2511 10R2F-L-GP

R2511 10R2F-L-GP R2512 10R2F-L-GP

R2512 10R2F-L-GP

EC2505

EC2505 SC10P50V2JN-4GP

SC10P50V2JN-4GP

C2505

1 2

DY

1 2

DY

1 2

DY

3D3V_S5_PCH

12

R2516

R2516 0R2J-2-GP

0R2J-2-GP

DY

12

C2504

DY

SCD1U16V2KX-3GP

SPI_HOLD_ROM [18] SPI_CLK_ROM [18,24] SPI_SI_ROM [18,24]

Main Func = RTC

RTC_AUX_S5+RTC_VCC 3D3V_AUX_S5

D2501

RTC1

3 1

2

ACES-CON2-20-GP-U

A A

4

20.F1639.002

5

RTC_VCC_R

R2520

1 2

1KR2J-1-GP

12

R2504

R2504 10MR2J-L-GP

10MR2J-L-GP

4

1

3

2

BAS40C-2-GP

75.00040.07D

2nd = 75.00040.C7D

2nd = 75.00040.C7D 3rd = 75.00040.A7D

3rd = 75.00040.A7D

Q2505

G

D

S

2N7002K-2-GP

84.2N702.J31

2ND = 84.2N702.031

12

C2503

DY

SCD47U25V3KX-1GP

RTC_DET# [20]

3

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Monday, March 21, 2016

Date: Sheet of

2

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

Flash/RTC

Drax SKL Y

25 109

1

A00

5

4

3

2

1

SSID = Thermal Sensor

3D3V_S0 3D3V_S0

3D3V_S0

1

23

RN2602

RN2602 SRN2K2J-1-GP

12

C2601

C2602

DY

7718

DY

12

C2606

B

C2606 SC470P50V3JN-2GP

SC470P50V3JN-2GP

DY

D D

84.03904.P11

2nd = 84.03904.T11

C

Q2603

CH3904PT-GP

E

2.System Sensor, Put on palm rest

C C

Layout Note:

Both DXN and DXP routing 10 mil trace width and 10 mil spacing.

3D3V_S0

R2603 18K7R2F-GP

R2603 18K7R2F-GP R2604 2KR2F-3-GP

R2604 2KR2F-3-GP

7718

7718 7718

7718

12 12

C2602

7718

SCD1U16V2KX-3GP

SC10U6D3V3MX-GP

NCT7718_DXP

12

7718

NCT7718_DXN

Layout Note:

C2607 close THM2601

ALERT#

T_CRIT#

C2607

C2607 SC2200P50V2KX-2GP

SC2200P50V2KX-2GP

T_CRIT#

12

R2601

R2601 0R0402-PAD-1-GP

0R0402-PAD-1-GP

THM261

1

VDD

2

D+

3

DT_CRIT#4GND

NCT7718W-GP

74.07718.0B9

A00 20160302

THERM_SYS_SHDN#

7718

SCL SDA

ALERT#

2N7002KDW-GP

1

SML1_SMBDATA[18,24]

DY

C2608

SCD1U16V2KX-3GP

THM_SML1_CLK THM_SML1_DATA

12

C2609

SCD1U16V2KX-3GP

1 2

0R2J-2-GP

R2606

Q2602

G

S

2N7002K-2-GP

84.2N702.J31

2ND = 84.2N702.031

3rd = 84.07002.I31

4th = 84.2N702.W31

SML1_SMBCLK[18,24]

D

DY

8 7

ALERT#

6 5

12

DY

PCH_PW ROK[17,24]

KBC T8

R2602 0R2J-2-GP

84.2N702.A3F

2nd = 84.2N702.E3F

3rd = 75.00601.07C

4th = 84.DMN66.03F

1 2

R2611 10KR2J-3-GP

12

C2603

DY

SCD22U10V2KX-1GP

12

C2610

SCD1U16V2KX-3GP

3D3V_S5

R2607 10KR2J-3-GP

1 2

DY

1 2

DY

6

7718

2

5

34

Q2601

DY

1 2

PURE_KBCT8

R2615 0R2J-2-GP

VD_OUT1#

PLT_RST# [17,24,33,37,61,68]

VD_OUT1# [24]

SRN2K2J-1-GP

7718

4

PURE_HW _SHUTDOWN# [24,40]

THM_SML1_DATA

THM_SML1_CLK

VD_IN1 for system thermal sensorClose to Thermal sensor

B B

12

DY

PURE_KBCT8

A A

5

4

3

R2609

24K9R2F-L-GP

R2610

NTC-100K-8-GP

3D3V_AUX_KBC3D3V_AUX_S5

12

R2608

24K9R2F-L-GP

PURE_KBCT8

12

C2612

12

SCD1U16V2KX-3GP

PURE_KBCT8

VD_IN1_C

2

12

C2613

PURE_KBCT8

SC100P50V2JN-3GP

PURE_KBCT8

Title

Size Document Number Rev

Size Document Number Rev A3

A3

A3 Date: Sheet of

Date: Sheet of

VD_IN1 [24]

0R2J-2-GP

R2605

THERMAL NCT7718W/Fan

Monday, March 21, 2016

0R2J-2-GP

1 2

Drax SKL Y

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

1

26 109

A00

SSID = Audio

5

4

3

2

1

3D3V_S0

25mA

R2731

1 2

0R0805-PAD-1- GP-U

1D8V_S0

0R0805-PAD-1- GP-U

A00 20160301

R2726

1 2

0R0402-PAD-1- GP

D D

A00 20160302

1.5A

5V_S0 +5V_PVDD

R2702

1 2

0R0805-PAD-1- GP-U

R2704

1 2

0R0805-PAD-1- GP-U

A00 20160301

Layout Note:

moat

C C

1D8V_S0

3D3V_S0

R2713 0R0402-PAD-1-G PR2713 0R0402-PAD-1 -GP R2710 0R2J-2-GP

R2710 0R2J-2-GP

A00 20160302

1 2 1 2

DY

AVDD2: +1.8VD@3246 +1.5VD@3234

Close pin41

+3V_1D5V_AVDD

12

C2715

AUD_AGND

+3V_AVDD

CPVDD

C2714

12

C2701

SC4D7U6D3V 3KX-GP

Close pin36

SCD1U16V2KX-3GP

C2706

12

SC10U6D3V3MX-GP

C2707

12

SCD1U16V2KX-3GP

C2709

C2708

12

SCD1U16V2KX-3GP

SC10U6D3V3MX-GP

Layout Note:

Close pin46

Speaker trace width >40mil @ 2W4ohm speaker power

SC4D7U6D3V3KX-GP

12

C2721

Close pin40

SCD1U16V2KX-3GP

EC_MUTE#[24]

+3V_AVDD

AUD_AGND AUD_AGND

Layout Note:

R2724

1 2

DY

0R2J-2-GP

C2712 SC10U6D3V3MX- GPC2712 SC10U6D3V3MX- GP

1 2

AUD_SPK_L+[29]

AUD_SPK_L-[29] AUD_SPK_R-[29] AUD_SPK_R+[29 ]

R2708

1 2

0R0402-PAD-1- GP

A00 20160302

+3V_1D5V_AVDD

TP2701

TPAD14-OP-G P

Azalia I/F EMI

HDA_CODE C_SDOUT HDA_CODE C_BITCLK

DMIC_DATA_R

EC2709

EC2708

12

SC22P50V2JN-4GP

B B

EC2701

12

SC22P50V2JN-4GP

SC10P50V2JN-4GP

DY

DMIC_CLK[55]

SC22P50V2JN-4G P

Close pin3

C2723

DY

1 2

DMIC_DATA[55]

HDA_CODE C_SDOUT[19]

HDA_CODE C_BITCLK[19]

HDA_SDIN0[19]

HDA_CODE C_SYNC[19]

Audio Codec Chip ALC3246

LINE1_VREFO_R[29] LINE1_VREFO_L[29]

AUD_HP1_JAC K_L[29] AUD_HP1_JAC K_R[29]

C2704

1 2

SC1U10V2KX-1G P

12

CPVDD

C2703

C2703 SC1U10V2KX-1G P

+5V_PVDD

AUD_SPK_L+ AUD_SPK_LAUD_SPK_RAUD_SPK_R+

+5V_PVDD

COMBO-GPI

1

SC4D7U6D3V 3KX-GP

SC1U10V2KX-1G P

CBP

LDO2_CAP

PD#

C2716

R271422R 2J-2-GP R271422R2J-2-GP

1 2

R271622R 2J-2-GP R271622R2J-2-GP

1 2

R2719 A00 20160302

HDA27

37

CBP

38

AVSS2

39

LDO2-CAP

40

AVDD2

41

PVDD1

42

SPK-OUT-L+

43

SPK-OUT-L-

44

SPK-OUT-R-

45

SPK-OUT-R+

46

PVDD2

47

PDB

48

SPDIF-OUT/GPIO2/DMIC-DATA34/DMIC -CLK-IN

49

GND

ALC3246-CG-G P-U

+3V_AVDD

12

DMIC_DATA_R DMIC_CLK_R

R27190R0402-PAD-1-GP R27190R0402-PAD-1-GP

1 2

R272022R2J-2-GP R272022R2J-2-GP

1 2

R271822R2J-2-GP R271822R2J-2-GP

1 2

HDA_CODE C_SYNC

CPVEE

CBN

30

31

32

33

34

35

36

CBN

CPVEE

CPVDD

LINE1-VREFO-L

LINE1-VREFO-R

HPOUT-L_PORT-I-L

HPOUT-R_PORT-I-R

071.03246.0003

SPDIFO/FRONT-JD_JD3/GPIO3

DVDD1GPIO0/DMIC-DATA122GPIO1/DMIC-CLK3DC_DET4SDATA-OUT5BCLK6LDO3-CAP7SDATA-IN8DVDD-IO9SYNC10I2C-DATA11I2C-CLK

DVSS

12

C2717

12

SCD1U16V2KX-3GP

CODEC_SD OUT_R CODEC_BITC LK_R HDA_CODE C_SDIN0

0R2J-2-GP

LDO3_CAP

DY

C2718SC4D7U6D3V3KX-GP C2718SC4D7U6D3V3KX-GP

12

R2732

12

C2705

12

C2702

SC2D2U10V3KX-1GP

SC4D7U6D3V3KX-GP

AUD_VREF

LDO1_CAP

25

26

27

28

29

VREF

AVSS1

AVDD1

LDO1-CAP

LINE2-L_PORT-E-L

MIC2-VREFO

LINE2-R_PORT-E-R

LINE1-L_PORT-C-L

LINE1-R_PORT-C-R

VD33STB

MIC2-CAP

MIC2-R_PORT-F-R/SLEEVE

MIC2-L_PORT-F-L/RING2

PCBEEP

MIC2/LINE2-JD_JD2

HP/LINE1-JD_JD1

12

+3V_AVDD

C2719SCD1U16V2KX-3GP C2719SCD1U16V2KX-3GP

12

MIC2_VREFO [29]

R2711

R2711 100KR2J-1-GP

100KR2J-1-GP

+5V_AVDD AUD_AGND

AUD_AGND

24 23 22 21 20 19 18 17 16 15 14 13

V3D3_STB MIC_CAP

AUD_PC_BEEP _3246 JDREF

AUD_SENSE_A

moat

R2703

1 2

0R0603-PAD-1- GP-U

12

C2710

C2711

Layout Note:

Place close to Pin 26

SCD1U16V2KX-3GP

AUD_AGND

SC4D7U6D3V3KX-GP

moat

LINE1_L [29] LINE1_R [29]

R2712 0R0402-PAD-1-G PR2712 0R0402-PAD-1-GP

1 2

SLEEVE [29] RING2 [29]

DY

R2709

Layout Note:

Place close to Pin 13

1 2

AUD_SENSE

C2713 SC10U6D3V3MX- GPC2713 SC10U6D3V3MX- GP

R2707 20KR2F-L-GP

1 2

200KR2F-L-GP

moat

SPKR[19]

BEEP[24]

Follow Iris SKL

A00 20160301

R2723

1 2

0R0402-PAD-1- GP

RN2701

2 3 1

SRN1KJ-7-G P

5V_S0+5V_AVDD

3D3V_S5

A00 20160302

AUD_AGND

Layout Note:

AUD_PC_BEEP _R

A00 20160302

AUD_AGND

AUD_SENSE [29]

4

moat

EC2707 SC1KP50V2KX-1GP

1 2

DY

EC2706 SC1KP50V2KX-1GP

1 2

DY

EC2705 SCD1U25V2KX-GP

1 2

DY

EC2704 SC1KP50V2KX-1GP

1 2

DY

EC2703 SCD1U25V2KX-GP

1 2

DY

AUD_AGND

R2706 0R0603-PAD-1-G P-UR 2706 0R0603-PAD-1-G P-U

1 2

R2727 0R0603-PAD-1-G P-UR 2727 0R0603-PAD-1-G P-U

1 2

R2730 0R0603-PAD-1-G P-UR 2730 0R0603-PAD-1-G P-U

1 2

Layout Note:

AUD_AGND

Tied at point only under Codec or near the Codec

Width>40mil, to improve Headpohone Crosstalk noise Change it to sharp will be better. Add 2 vias (>0.5A) when trace layer change.

A00 20160301

moat

R2722

HDA_SPKR_R

KBC_BEEP_R

75.00054.E7D

75.00054.E7D 2nd = 83.R2003.W81

2nd = 83.R2003.W81 3rd = 75.00054.A7D

3rd = 75.00054.A7D 4th = 83.R2003.V81

4th = 83.R2003.V81

D2701

2

1

BAT54C-7-F- 3-GP

AUD_SENSE_A

+3.3VD@3234 follow Pin1 Power setting@3246

AUD_PC_BEEP _C

3

12

Follow Iris SKL

C2720

1 2

R2717

R2717 2K2R2J-2-GP

2K2R2J-2-GP

R2722

100KR2J-1-GP

AUD_PC_BEEP _R

SCD1U16V2KX- 3GP

+3V_AVDD

12

1D8V_S01D8V_S5

Q2701

DMP2130L-7-GP

150mA

12

Q2702

G

S

2N7002K-2-GP

12

C2724

SCD1U16V2KX-3GP

1D8V_EN#

D

3

3D3V_S0

SIO_SLP_S3#[17,24, 40,51]

A A

5

4

R2728

1 2

0R0402-PAD-1- GP

A00 20160303

DY

0R2J-2-GP

Q4009_G

R2729

1 2

R2715

R2715 10KR2J-3-GP

10KR2J-3-GP

R2733

1 2

4K7R2J-2-GP

1

2

1D8V_EN_R#

S

C2722

SCD22U25V3KX- GP

84.02130.031

84.02130.031 2nd = 84.00102.031

2nd = 84.00102.031 3rd = 84.03413.B31

3rd = 84.03413.B31

DMP2130L-7-GP

D

G

12

C2725

SCD1U16V2KX-3GP

DY

Wistron Corporation

21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih,

21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih, Taipei Hsie n 221, Taiwan, R.O.C .

Taipei Hsie n 221, Taiwan, R.O.C .

Drax SKL Y

1

Taipei Hsie n 221, Taiwan, R.O.C .

27 109Tuesday, Mar ch 22, 2016

A00

Title

Audio Codec ALC3246

Size Document Numb er Rev

A2

Date: Sheet of

2

Date: Sheet of

5

D D

C C

4

3

2

1

Blanking

B B

Wistron Corporation

A A

Title

Size Document Number Rev

A4

Date: Sheet of

5

4

3

Date: Sheet of

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

(Reserved)

Drax SKL Y

28 109Thursday, March 17, 2016

1

A00

5

SSID = Audio

4

3

2

1

Layout Note:

Speaker trace width >40mil @ 2W4ohm speaker power

AUD_SPK_R+_C

D D

AUD_SPK_R+[27] AUD_SPK_R-[27]

AUD_SPK_L+[27] AUD_SPK_L-[27]

1 2 1 2

R29040R0603-PAD-1-GP-U R29040R0603-PAD-1-GP-U R29030R0603-PAD-1-GP-U R29030R0603-PAD-1-GP-U

R29020R0603-PAD-1-GP-U R29020R0603-PAD-1-GP-U R29010R0603-PAD-1-GP-U R29010R0603-PAD-1-GP-U

AUD_SPK_R-_C AUD_SPK_L+_C AUD_SPK_L-_C

A00 20160301

12

EC2902

SC1KP50V2KX-1GP

EC2902

SC1KP50V2KX-1GP

EC2903

SC1KP50V2KX-1GP

EC2903

EC2901

SC1KP50V2KX-1GP

EC2901

SC1KP50V2KX-1GP

C C

RN2901

1

MIC2_VREFO[27]

SRN2K2J-1-GP

RING2[27]

AUD_HP1_JACK_L[27]

LINE1_L[27]

LINE1_VREFO_L[27]

AUD_HP1_JACK_R[27]

LINE1_R[27]

LINE1_VREFO_R[27]

SLEEVE[27]

C2903

1 2

SC10U6D3V3MX-GP

C2904

1 2

SC10U6D3V3MX-GP

SRN2K2J-1-GP

LINE1-L_C

LINE1-L_R

4

2 3

R2908 10R2F-L-GPR2908 10R2F-L-GP

1 2

R2922 1KR2J-1-GPR2922 1KR2J-1-GP

1 2

R2912 4K7R2J-2-GPR2912 4K7R2J-2-GP

1 2

R2910 10R2F-L-GPR2910 10R2F-L-GP

1 2

R2921 1KR2J-1-GPR2921 1KR2J-1-GP

1 2

R2913 4K7R2J-2-GPR2913 4K7R2J-2-GP

1 2

SC1KP50V2KX-1GP

12

EC2904

SC1KP50V2KX-1GP

EC2904

SC1KP50V2KX-1GP

AUD_HP1_JACK_L1

AUD_HP1_JACK_R1

EC2908

SC100P50V2JN-3GPDYEC2908

SC100P50V2JN-3GP

12

R2920

10KR2J-3-GPDYR2920

10KR2J-3-GP

DY

EC2907

SC100P50V2JN-3GPDYEC2907

SC100P50V2JN-3GP

12

DY

12

R2919

DY

SC100P50V2JN-3GPDYEC2906

SC100P50V2JN-3GP

10KR2J-3-GP

DY

SC100P50V2JN-3GP

EC2906

A00 20160301

12

DY

EC2905

SC100P50V2JN-3GPDYEC2905

Speaker

SPK1

5

1 2

3 4

ACES-CON4-29-GP

20.F1639.004

6

CONN Pin Pin1 Pin2 Pin3 Pin4

AUD_SPK_L-_C AUD_SPK_L+_C AUD_SPK_R-_C

AUD_SPK_R+_C

AFTP2901AFTP2901

1

AFTP2902AFTP2902

1

AFTP2903AFTP2903

1

AFTP2904AFTP2904

1

Universal Jack (Moved to I/O Board)

R2906 0R0603-PAD-1-GP-UR2906 0R0603-PAD-1-GP-U

1 2

R2907 0R0603-PAD-1-GP-UR2907 0R0603-PAD-1-GP-U

1 2

R2909

1 2

R2911 0R0603-PAD-1-GP-UR2911 0R0603-PAD-1-GP-U

1 2

0R0603-PAD-1-GP-U

RING2_R AUD_PORTA_L_R_B

JACK_PLUG AUD_PORTA_R_R_B

SLEEVE_R

Delay circuit

Net name SPK_R+ SPK_RSPK_L+ SPK_L-

RING2_R [66] AUD_PORTA_L_R_B [66]

JACK_PLUG [66] AUD_PORTA_R_R_B [66]

SLEEVE_R [66]

(JACK_PLUG_DET: on IO Board)

10 mils

B B

AUD_AGND AUD_AGND

JACK_PLUG

R2905

100KR2J-1-GP

AUD_AGND

DY

12

C2902

SC10U6D3V3MX-GP

DY

1 2

AUD_AGND

R2923

1 2

0R0603-PAD-1-GP-U

G

S

Q2901

Q2901 2N7002K-2-GP

2N7002K-2-GP

84.2N702.J31

DY

2nd = 84.2N702.W31

3rd = 84.07002.I31

D

10 mils

AUD_AGND

AUD_SENSE [27]

A00 20160302

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

A3 Date: Sheet of

Date: Sheet of

Audio IO

Drax SKL Y

Monday, March 21, 2016

Taipei Hsien 221, Taiwan, R.O.C.

29 109

1

A00

5

D D

C C

4

3

2

1

Blanking

B B

Wistron Corporation

A A

Title

(Reserved)

Size Document Number Rev

A4

Date: Sheet of

5

4

3

Date: Sheet of

2

(Reserved)

Drax SKL Y

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

30 109Monday, March 21, 2016

1

A00

Dell Inspiron 11 3179 Schematics

Specifications and Main Features

Frequently Asked Questions

User Manual