Dell Enrico Caruso 14 MLK DIS Schematics

5

4

3

2

1

Enrico Caruso 14

D D

Muxless Schematics Document

Ivy Bridge & Sandy Bridge

Intel PCH

2012-01-03

C C

REV : X02

DY : None Installed PSL: 10mW internal schematic UMA: UMA ONLY installed

B B

OPS: Optimus solution installed. Surge: For GO Rural config stuff. GIGA: For GIGA LAN config stuff. LPC : Reserve for LPC debug card POP : Reserve for solve "POP" sound iuuse

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Enrico Caruso 14 MLK DIS

Tuesday, January 03, 2012

Date: Sheet of

Cover Page

Taipei Hsien 221, Taiwan, R.O.C.

1 104

1

X02

5

##OnMainBoard

Hynix:72.52G63.A0U (HT31P$AA) Samsung:72.42164.D0U (JP0F2$AA)

D D

VRAM

1GB (128Mx16x4)

gDDR3 900MHz

88,89,90,91

gDDR3 900MHz

N13M-GS

Xtal=27MHz

C C

CRT

LCD

HDMI

B B

50

49

51

SD/MMC/MS/ MS Pro

CardReader

74

Audio board

Internal Analog MIC

HP1

58

82

Cirrus CS4213D

MIC IN

2CH SPEAKER

A A

5

58

83.84,85,86,87

CRT

LVDS

HDMI

Realtek RTS5138

Azalia CODEC

4

3

Block Diagram (Discrete)

4

Intel CPU

Ivy Bridge & Sandy Bridge

PCIe x 8

(Discrete only)

4,5,6,7,8,9,10

8MB

DMIx4

SPI

60

3

FDIx4x2

Intel

PCH Panther Point

BGA989

HM75

USB2.0

32

AZALIA 24MHz

29

4

12 USB 2.0/1.1 ports High Definition Audio

6 SATA ports 8 PCIE ports

ACPI 4.0a

17,18,19,20,21,22,23,24,25

SATA

ODDHDD

LPC I/F

3Gbps

Flash ROM

5656

Project code: Inspiron:91.4TY01.001 Vostro :91.4UA01.001 PCB P/N :48.4TY02.0SC Revision:11282-SC

DDRIII 1333/1600 Channel A

DDRIII 1333/1600 Channel B

PCIE x 1

PCIE

100MHz

2.5Gbps

USB 2.0

480Mbps

LPC Bus

33MHz

NUVOTON

NPCE885P

PS/2 PS/2

Touch PAD

DDRIII 1333/1600

10/100 /1000 LOM

Realtek RTL8111F (Giga LAN) Realtek RTL8105E-VD (10M/100M)

Xtal=25MHz

KBC

27

Int. KB

6969

2

Slot 0

15

Slot 1

14

USB 2.0 x 1

USB 2.0 x 2

D/A

Fan Control

G991P

2

1

SYSTEM DC/DC

APL5916

INPUTS

DCBATOUT

31

Mini-Card WLAN+BT3.0

CAMERA

M/B USB x1 (Left)

I/O board USB x2 (Right)

RJ45 CONN

802.11a/b/g

OUTPUTS

0D85V_S0

48

59

64

49

61

82

CPU DC/DC

VT1318+1323

INPUTS

DCBATOUT

OUTPUTS

VCC_CORE

SYSTEM DC/DC

TPS51219

INPUTS

DCBATOUT

OUTPUTS

1D05V_VTT

SYSTEM DC/DC

TPS51125

INPUTS

DCBATOUT 5V_S5

OUTPUTS

5V_AUX_S5 3D3V_AUX_S5

3D3V_S5 15V_S5

SYSTEM DC/DC

TPS51216R

INPUTS

DCBATOUT

OUTPUTS

1D5V_S3 0D75V_S0 DDR_VREF_S3

GFX DC/DC

VT1318+1323

INPUTS

DCBATOUT

OUTPUTS

VCC_GFXCORE

VGA

DCBATOUT

ADP3211

OUTPUTS

VGA_CORE

INPUTS

TI CHARGER

BQ24707

INPUTS

+DC_IN_S5

SYSTEM DC/DC

INPUTS

3D3V_S5

Switches

OUTPUTS

RT8068A

OUTPUTS

42~44

45

41

46

44

92

40

DCBATOUT+PBATT

47

1D8V_S0

93

INPUTS OUTPUTS

1D5V_S0 5V_S0 3D3V_S03D3V_S5

Thermal

NCT7718W

1D5V_S3 5V_S5

28

Thermal

G709

28

Title

Size Document Number Rev

A3

Date: Sheet of

28

Block Diagram

Enrico Caruso 14 MLK DIS

PCB LAYER

L1:Top L2:GND L3:Signal

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

1

2 104Friday, December 30, 2011

L4:Signal L5:VCC L6:Bottom

X02

A

PCH Strapping

Name Schematics Notes

The signal has a weak internal pull-down.

SPKR

INIT3_3V#

4 4

INTVRMEN

GNT3#/GPIO55 GNT2#/GPIO53 GNT1#/GPIO51

DF_TVS

SATA1GP/ GPIO19

3 3

SATA2GP/ GPIO36

SATA3GP/ GPIO37

HDA_DOCK_EN# /GPIO33

HDA_SDO

HDA_SYNC

2 2

GPIO15

L_DDC_DATA

SDVO_CTRLDATA

DDPC_CTRLDATA

DDPD_CTRLDATA

1 1

GPIO28

GPIO29/ SLP_LAN#

Note: the internal pull-down is disabled after PLTRST# deasserts. If the signal is sampled high, this indicates that the system is strapped to the ¨No Reboot〃 mode (Panther Point will disable the TCO Timer system reboot feature).

This signal has a weak internal pull-up. Note: The internal pull-up is disabled after PLTRST# deasserts. NOTE: This signal should not be pulled low. Leave as "No Connect".

Integrated 1.05 V VRM Enable / Disable. Integrated 1.05 V VRMs is enabled when high NOTE: This signal should always be pulled high External 1.05 V VRM Enable / Disable. Integrated 1.05 V VRMs is enabled when Low. NOTE: This signal should be pulled down to GND through 330 kOhms resistor

GNT[3:0]# functionality is not available on Mobile. Used as GPIO only. Pull-up resistors are not required on these signals. If pull-ups are used, they should be tied to the Vcc3_3 power rail.

This signal is a strap for selecting DMI and FDI termination voltage. For Ivy Bridge processor only implementation: DF_TVS needs to be pulled up to VccDFTERM power rail through 2.2 kOhms ∮5% resistor. For future processor compatibility: It needs to be connected to PROC_SELECT through a

1.0 kOhms ∮5% series resistor. The PROC_SELECT signal would need a 2.2 kOhms ∮5% pull-up resistor to PCH VccDFTERM.

Bit11 Bit 10 Boot BIOS Destination 0 1 Reserved 1 0 PCI 1 1 SPI 0 0 LPC NOTE: If option 00 LPC is selected BIOS may still be placed on LPC, but all platforms with Panther Point require SPI flash connected directly to the Panther Point's SPI bus with a valid descriptor in order to boot. NOTE: Booting to PCI is intended for debut/testing only. Boot BIOS Destination Select to LPC/PCI by functional strap or via Boot BIOS Destination Bit will not affect SPI accesses initiated by Management Engine or Integrated GbE LAN. NOTE: PCI Boot BIOS destination is not supported on mobile.

Reserved. This signal has a weak internal pull-down. NOTE: The internal pull-down is disabled after PLTRST# deasserts. NOTE: This signal should not be pulled high when strap is sampled.

Reserved This signal has a weak internal pull-down. NOTE: The internal pull-down is disabled after PLTRST# deasserts. NOTE: This signal should not be pulled high when strap is sampled.

High Definition Audio Dock Enable: This signal controls the external Intel HD Audio docking isolation logic. This is an active-low-signal. When deasserted the external docking switch is in isolate mode. When asserted the external docking switch electrically connects the IntelR HD Audio dock signals to the corresponding Panther Point signals. This signal can instead be used as GPIO33.

Signal has a weak internal pull-down. If strap is sampled low, the security measures defined in the Flash Descriptor will be in effect (default).If sampled high, the Flash Descriptor Security will be overridden. This strap should only be asserted high via external pull-up in manufacturing/debug environments ONLY. Note: The weak internal pull-down is disabled after PLTRST# deasserts. Asserting the HDA_SDO high on the rising edge of PWROK will also halt Intel Management Engine after chipset bring up and disable runtime Intel Management Engine features. This is a debug mode and must not be asserted after manufacturing/ debug.This signal has a 20k internal pull down resistor. This signal has a weak internal pull-down. On Die PLL VR is supplied by 1.5 V from VCCVRM when sampled high, 1.8 V from VCCVRM when sampled low. Needs to be pulled High for Chief River platform. Note: HDA_SYNC signal also serves as a strap for selecting VRM voltage to the PCH. The strap is sampled on the rising edge of RSMRST# signal. Due to potential leakage on the codec (path to GND), the strap may not be able to achieve the Vihmin at PCH input.Therefore, platform may need to isolate this signal from the codec during the strap phase. Refer to the example circuits provided in the latest Chief River platform design guide. TLS Confidentiality Low (0) Intel ME Crypto Transport Layer Security (TLS) cipher suite with no



confidentiality High (1) - Intel ME Crypto Transport Layer Security (TLS) cipher suite with confidentiality This signal has a weak internal pull-down. NOTE:The weak internal pull-down is disabled after RSMRST# deasserts. NOTE: A strong pull-up may be needed for GPIO functionality

LVDS Detected. When '1'- LVDS is detected; When '0'- LVDS is not detected. This signal has a weak internal pull-down. NOTE:The internal pull-down is disabled after PLTRST# deasserts.

Port B Detected When '1'- Port B is detected; When '0'- Port B is not detected This signal has a weak internal pull-down. NOTE:The internal pull-down is disabled after PLTRST# deasserts.

Port C Detected. When '1'- Port C is detected; When '0'- Port C is not detected This signal has a weak internal pull-down. NOTE:The internal pull-down is disabled after PLTRST# deasserts.

Port D Detected. When '1'- Port D is detected; When '0'- Port D is not detected This signal has a weak internal pull-down. NOTE:The internal pull-down is disabled after PLTRST# deasserts.

The On-Die PLL voltage regulator is enabled when sampled high. When sampled low the On-Die PLL Voltage Regulator is disabled.If not used, 8.2-k to 10-k pull-up to +V3.3A power-rail. GPIO28 signal also needs to be pulled up to 3.3V_SUS with 4.7K resistor to ensure proper strap setting when use as the chipset test interface.Refer to the latest platform debug design guide and platform design guide for more details. NOTE:This signal has a weak internal pull-up. The internal pull-up is disabled after RSMRST# deasserts.

GPIO29 is multiplexed with SLP_LAN#. If Intel LAN is implemented on the platform, SLP_LAN# must be used to control the power to the PHY LAN (no other implementation is supported). If integrated Intel LAN is not supported on the platform, GPIO29 can be used as a normal GPIO. A soft strap determines the functionality of GPIO29, either as SLP_LAN# or GPIO. By default, the soft strap enables SLP_LAN# functionality on the pin. If the soft trap is changed to enable GPIO functionality, then SLP_LAN# functionality is no longer available, and the signal can be used as a normal GPIO (default to GPI).

Chief River Schematic Checklist Revision 1.5

 

A

B

Processor Strapping

Pin Name Strap Description

CFG[0] Connect a series 1 kOhms resistor on the critical CFG[0]

CFG[2] PCIe Static x16 Lane

Numbering Reversal.

CFG[4]

Display Port Presence strap

PCIE Port Bifurcation

CFG[6:5]

Straps

Reserved configuration

CFG[17:7]

lands. A test point may be placed on the board for these lands.

Sandy Bridge + Ivy Bridge Compatibility Requirements

Pin Name Configuration Schematic Notes

DDR3 VREF

PROC_SELECT# & DF_TVS

VCCIO VR Implementation

VCCSA_SEL connection to VCCSA_VID[1:0] lines

Layout Requirement on PCI Express Gen3

GT Core VR Implementation

Processor PCI Express Graphics Guidelines

Sandy Bridge + Ivy Bridge

Ivy Bridge

Sandy Bridge + Ivy Bridge

Ivy Bridge No change.

Sandy Bridge + Ivy Bridge

Ivy Bridge No change.

Sandy Bridge + Ivy Bridge

Ivy Bridge No change.

Sandy Bridge + Ivy Bridge

Ivy Bridge No change.

Sandy Bridge + Ivy Bridge

Ivy Bridge No change.

Sandy Bridge + Ivy Bridge (PCIe Gen3):

B

C

Chief River Schematic Checklist Revision 1.5

Configuration (Default value for each bit is 1 unless specified otherwise)

trace in a manner which does not introduce any stubs to CFG[0] trace. Route as needed from the opposite side of this series isolation resistor to the debug port. ITP will drive the net to GND.

1: Normal Operation; Lane # definition matches socket pin map definition 0:Lane Reversed

1:Disabled - No Physical Display Port attached to Embedded DisplayPort No connect for disable 0:Enabled - An external Display Port device is connected to the Embedded Display Port Pull-down to GND through a 1K ∮ 5% resistor to enable port

00 = 1 x 8, 2 x 4 PCI Express 01 = reserved 10 = 2 x 8 PCI Express 11 = 1 x 16 PCI Express

Chief River Schematic Checklist Revision 1.5

DDR3 VREF M1 and M3 Guidelines are required. Note: The M3 traces are routed to the Sandy Bridge Processor reserved pins.

No change.

Connect DF_TVS signal of the PCH to PROC_SELECT# of the processor through a 1K∮5% series resistor. PROC_SELECT# also needs a 2.2K∮5% pull up resistor to PCH VccDFTERM rail.

The POR for Ivy Bridge mobile parts is now 1.05 V. There is no longer a requirement for a separate VCCIO VR for Sandy Bridge + Ivy Bridge compatibility.

VCCSA_SELECT[0:1] which should be connected to VID[1:0] of the System Agent (SA) VR controller.

The total motherboard length for a pair of consecutive PCI Express Tx lanes be length matched within 100 mils (2.54 mm)

Depending on the PDDG specifications, some IVB GT2 SKUs may require a new VR controller and 2 phase VCC GT core VR.

To support Gen 3 PCI Express Graphic, the value of the AC coupling capacitor should be 180 - 265 nF.

No change.Ivy Bridge

C

Default Value

1

D

Power Plane

VOLTAGE DESCRIPTION

POWER PLANE

5V_S0

5V

3D3V_S0

3.3V

1D8V_S0

1.8V

1D5V_S0

1.5V

1D05V_VTT

1.05V

0D85V_S0

0.95 - 0.85V

0D75V_S0

0.75V

VCC_CORE

0.35V to 1.5V

VCC_GFXCORE

0.4 to 1.25V

1D8V_VGA_S0

1.8V

3D3V_VGA_S0

3.3V

1V_VGA_S0

1V

5V

5V_USBX_S3

1.5V

1D5V_S3

0.75V

DDR_VREF_S3

BT+

6V-14.1V

DCBATOUT

6V-14.1V

5V_S5

5V

5V_AUX_S5

5V

3D3V_S5

3.3V

3D3V_AUX_S5

3.3V

3.3V3D3V_LAN_S5

3D3V_AUX_KBC

3.3V

3D3V_AUX_S5

PCIE Routing

LANE1 X

X

LANE2 LANE3xMini Card1(WLAN) LANE4 LANE5

X

Onboard LAN

LANE6 LANE7

X

LANE8 X

SATA Table

Pair

0 1 2 3 4 5

E

Voltage Rails

ACTIVE IN

S0

S3

All S states

WOL_EN

DSW, Sx ON for supporting Deep Sleep states

G3, Sx

CPU Core Rail Graphics Core Rail

AC Brick Mode only

Legacy WOL

Powered by Li Coin Cell in G3 and +V3ALW in Sx

USB Table

Pair

X

0

USB Ext. port 1

1

X

2

X

3

X

4

CARD READER

5

X

6

X

7

USB Ext. port 2

8

USB Ext. port 3

9

X

10 11

Mini Card1 (WLAN) CAMERA

12

X

13

SATA Device

HDD1 X X X ODD1 X

Title

Size Document Num ber Rev

Size Document Num ber Rev A2

A2

A2 Date: Sheet of

Date: Sheet of

Table of Content

Enrico Caruso 14 MLK DIS

Friday, Decem ber 30, 2011

E

Device

Wistron Corporation

21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih,

21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih, Taipei Hsie n 221, Taiwan, R.O. C.

Taipei Hsie n 221, Taiwan, R.O. C.

3 104

X02

5

4

3

2

1

SSID = CPU

Layout Note:

Signal Routing Guideline: PEG_ICOMPO keep W/S=12/15 mils and routing length less than 500 mils.

D D

1 OF 9

CPU1A

DMI_TXN[3:0]19

DMI_TXP[3:0]19

DMI_RXN[3:0]19

DMI_RXP[3:0]19

C C

B B

Layout Note:

Signal Routing Guideline: EDP_ICOMPO keep W/S=12/15 mils and routing length less than 500 mils. EDP_COMPIO keep W/S=4/15 mils and routing length less than 500 mils.

1D05V_VTT

FDI_TXN[7:0]19

FDI_TXP[7:0]19

FDI_FSYNC019 FDI_FSYNC119

FDI_INT19 FDI_LSYNC019

FDI_LSYNC119

R402 24D9R2F-L-GPR402 24D9R2F-L-GP

1 2

R403 10KR2J-3-GP

1 2

DY

DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3

DMI_TXP0 DMI_TXP1 DMI_TXP2 DMI_TXP3

DMI_RXN0 DMI_RXN1 DMI_RXN2 DMI_RXN3

DMI_RXP0 DMI_RXP1 DMI_RXP2 DMI_RXP3

FDI_TXN0 FDI_TXN1 FDI_TXN2 FDI_TXN3 FDI_TXN4 FDI_TXN5 FDI_TXN6 FDI_TXN7

FDI_TXP0 FDI_TXP1 FDI_TXP2 FDI_TXP3 FDI_TXP4 FDI_TXP5 FDI_TXP6 FDI_TXP7

FDI_FSYNC0 FDI_FSYNC1

FDI_INT FDI_LSYNC0

FDI_LSYNC1

DP_COMP eDP_HPD

B27 B25 A25 B24

B28 B26 A24 B23

G21 E22 F21 D21

G22 D22 F20 C21

A21 H19 E19 F18 B21 C20 D18 E17

A22 G19 E20 G18 B20 C19 D19 F17

H20

H17

A18 A17 B16

C15 D15

C17 F16 C16 G15

C18 E16 D16 F15

J18 J17

J19

DMI_RX#0 DMI_RX#1 DMI_RX#2 DMI_RX#3

DMI_RX0 DMI_RX1 DMI_RX2 DMI_RX3

DMI_TX#0 DMI_TX#1 DMI_TX#2 DMI_TX#3

DMI_TX0 DMI_TX1 DMI_TX2 DMI_TX3

FDI0_TX#0 FDI0_TX#1 FDI0_TX#2 FDI0_TX#3 FDI1_TX#0 FDI1_TX#1 FDI1_TX#2 FDI1_TX#3

FDI0_TX0 FDI0_TX1 FDI0_TX2 FDI0_TX3 FDI1_TX0 FDI1_TX1 FDI1_TX2 FDI1_TX3

FDI0_FSYNC FDI1_FSYNC

FDI_INT FDI0_LSYNC

FDI1_LSYNC

EDP_COMPIO EDP_ICOMPO EDP_HPD

EDP_AUX EDP_AUX#

EDP_TX0 EDP_TX1 EDP_TX2 EDP_TX3

EDP_TX#0 EDP_TX#1 EDP_TX#2 EDP_TX#3

IVY-BRIDGE

DMI

Intel(R) FDI

eDP

PEG_ICOMPI

PEG_ICOMPO

PEG_RCOMPO

PEG_RX#0 PEG_RX#1 PEG_RX#2 PEG_RX#3 PEG_RX#4 PEG_RX#5 PEG_RX#6 PEG_RX#7 PEG_RX#8

PEG_RX#9 PEG_RX#10 PEG_RX#11 PEG_RX#12 PEG_RX#13 PEG_RX#14 PEG_RX#15

PEG_RX0 PEG_RX1 PEG_RX2 PEG_RX3 PEG_RX4 PEG_RX5 PEG_RX6 PEG_RX7 PEG_RX8

PEG_RX9 PEG_RX10 PEG_RX11 PEG_RX12 PEG_RX13 PEG_RX14 PEG_RX15

PEG_TX#0 PEG_TX#1 PEG_TX#2 PEG_TX#3 PEG_TX#4 PEG_TX#5 PEG_TX#6 PEG_TX#7 PEG_TX#8 PEG_TX#9

PEG_TX#10 PEG_TX#11

PCI EXPRESS* - GRAPHICS

PEG_TX#12 PEG_TX#13 PEG_TX#14 PEG_TX#15

PEG_TX0

PEG_TX1

PEG_TX2

PEG_TX3

PEG_TX4

PEG_TX5

PEG_TX6

PEG_TX7

PEG_TX8

PEG_TX9 PEG_TX10 PEG_TX11 PEG_TX12 PEG_TX13 PEG_TX14 PEG_TX15

1 OF 9

J22 J21 H22

K33 M35 L34 J35 J32 H34 H31 G33 G30 F35 E34 E32 D33 D31 B33 C32

J33 L35 K34 H35 H32 G34 G31 F33 F30 E35 E33 F32 D34 E31 C33 B32

M29 M32 M31 L32 L29 K31 K28 J30 J28 H29 G27 E29 F27 D28 F26 E25

M28 M33 M30 L31 L28 K30 K27 J29 J27 H28 G28 E28 F28 D27 E26 D25

PEG_IRCOMP_R

PEG_RXN7 PEG_RXN6 PEG_RXN5 PEG_RXN4 PEG_RXN3 PEG_RXN2 PEG_RXN1 PEG_RXN0

PEG_RXP7 PEG_RXP6 PEG_RXP5 PEG_RXP4 PEG_RXP3 PEG_RXP2 PEG_RXP1 PEG_RXP0

PEG_C_TXN7 PEG_C_TXN6 PEG_C_TXN5 PEG_C_TXN4 PEG_C_TXN3 PEG_C_TXN2 PEG_C_TXN1 PEG_C_TXN0

PEG_C_TXP7 PEG_C_TXP6 PEG_C_TXP5 PEG_C_TXP4 PEG_C_TXP3 PEG_C_TXP2 PEG_C_TXP1 PEG_C_TXP0

R401 24D9R2F-L-GPR401 24D9R2F-L-GP

PEG_ICOMPI & PEG_RCOMPO keep W/S=4/15 mils and routing length less than 500 mils.

1D05V_VTT

1 2

PEG_RXN[0..7]83

PEG_RXP[0..7]83

NOTE. If PEG is not implemented, the RX&TX pairs can be left as No Connect

PEG Static Lane Reversal

C409 SCD22U10V2KX-1GP

1 2

OPS

C410 SCD22U10V2KX-1GP

1 2

OPS

C411 SCD22U10V2KX-1GP

1 2

OPS

C412 SCD22U10V2KX-1GP

1 2

OPS

C413 SCD22U10V2KX-1GP

1 2

OPS

C414 SCD22U10V2KX-1GP

1 2

OPS

C415 SCD22U10V2KX-1GP

1 2

OPS

C416 SCD22U10V2KX-1GP

1 2

OPS

C425 SCD22U10V2KX-1GP

1 2

OPS

C426 SCD22U10V2KX-1GP

1 2

OPS

C427 SCD22U10V2KX-1GP

1 2

OPS

C428 SCD22U10V2KX-1GP

1 2

OPS

C429 SCD22U10V2KX-1GP

1 2

OPS

C430 SCD22U10V2KX-1GP

1 2

OPS

C431 SCD22U10V2KX-1GP

1 2

OPS

C432 SCD22U10V2KX-1GP

1 2

OPS

PEG_TXN7 PEG_TXN6 PEG_TXN5 PEG_TXN4 PEG_TXN3 PEG_TXN2 PEG_TXN1 PEG_TXN0

PEG_TXP7 PEG_TXP6 PEG_TXP5 PEG_TXP4 PEG_TXP3 PEG_TXP2 PEG_TXP1 PEG_TXP0

PEG_TXP7 83 PEG_TXP6 83 PEG_TXP5 83 PEG_TXP4 83 PEG_TXP3 83 PEG_TXP2 83 PEG_TXP1 83 PEG_TXP0 83

PEG_TXN[0..7] 83

PEG_TXP[0..7] 83

62.10055.551

2nd = 22.10252.171

3rd = 62.10040.821

A A

3rd = 62.10040.821

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Enrico Caruso 14 MLK DIS

Tuesday, January 03, 2012

Date: Sheet of

CPU (PCIE/DMI/FDI)

Taipei Hsien 221, Taiwan, R.O.C.

4 104

X02

5

4

3

2

1

SSID = CPU

D D

2 OF 9

CPU1B

C26

PROC_SELECT#

AN34

SKTOCC#

AL33

CATERR#

AN33

PECI

AL32

PROCHOT#

AN32

THERMTRIP#

AM34

C504SCD1U10V2KX-5GP C504SCD1U10V2KX-5GP

PM_SYNC

AP33

UNCOREPWRGOOD

V8

SM_DRAMPWROK

AR33

RESET#

H_THERMTRIP#22,36

H_CPUPW RGD22,36

VDDPWRGOOD37

1 2

R510

1K5R2F-2-GP

H_SNB_IVB#22

R513

R504

DY

SKTOCC#_R

H_CATERR#

H_PECI

H_PROCHOT#_R

H_THERMTRIP#

H_PM_SYNC

1 2

H_CPUPW RGD_R

0R0402-PAD

VDDPWRGOOD

BUF_CPU_RST#

12

C501

C501 SC220P50V2KX-3GP

SC220P50V2KX-3GP

1

TP501TPAD14-OP-GP TP501TPAD14-OP-GP

1

TP502TPAD14-OP-GP TP502TPAD14-OP-GP

H_PECI22,27

X02

1 2

R503

R509

R509 698R2F-GP

698R2F-GP

1 2

56R2J-4-GP

1 2

10KR2J-3-GP

H_PROCHOT#27,40

H_PM_SYNC19

12

1D05V_VTT

R501

1 2

62R2J-GP

H_PROCHOT#_L86

C C

Layout Note:

R501, R513 place near to CPU C502 need place at the separate point.

DY

1 2

H_PROCHOT#

R505

R505 0R2J-2-GP

0R2J-2-GP

PLT_RST#18,27,31,65,71,83

B B

IVY-BRIDGE

MISCTHERMALPWR MANAGEMENT

CLOCKS

DDR3

MISC

DDR3

MISC

JTAG & BPM

2 OF 9

BCLK

BCLK#

DPLL_REF_CLK

DPLL_REF_CLK#

SM_DRAMRST#

SM_RCOMP0 SM_RCOMP1 SM_RCOMP2

PRDY# PREQ#

TCK

TMS

TRST#

TDO

DBR#

BPM#0 BPM#1 BPM#2 BPM#3 BPM#4 BPM#5 BPM#6 BPM#7

CLK_EXP_P

A28

CLK_EXP_NH_SNB_IVB#

A27

RN502

CLK_DP_P_R

A16

CLK_DP_N_R

A15

SM_DRAMRST#

R8

SM_RCOMP_0

AK1

SM_RCOMP_1

A5

SM_RCOMP_2

A4

XDP_PRDY#

AP29

XDP_PREQ#

AP27

XDP_TCLK

AR26

XDP_TMS

AR27

XDP_TRST#

AP30

XDP_TDI

AR28

TDI

AP26

AL35

AT28 AR29 AR30 AT30 AP32 AR31 AT31 AR32

XDP_TDO

XDP_DBRESET#

XDP_BPM0 XDP_BPM1 XDP_BPM2 XDP_BPM3 XDP_BPM4 XDP_BPM5 XDP_BPM6 XDP_BPM7

RN502

1 2 3

1 2

4

SRN1KJ-7-GP

R502

R502 4K99R2F-L-GP

4K99R2F-L-GP

R506 140R2F-GPR506 140R2F-GP

1 2

R507 25D5R2F-GPR507 25D5R2F-GP

1 2

R508 200R2F-L-GPR508 200R2F-L-GP

1 2

1

TP511 TPAD14-OP-GPTP511 TPAD14-OP-GP

1

TP512 TPAD14-OP-GPTP512 TPAD14-OP-GP

XDP_DBRESET# 19

1 1 1 1 1 1 1 1

CLK_EXP_P 20 CLK_EXP_N 20

1D05V_VTT

SM_DRAMRST# 37

TP503 TPAD14-OP-GPTP503 TPAD14-OP-GP TP504 TPAD14-OP-GPTP504 TPAD14-OP-GP TP505 TPAD14-OP-GPTP505 TPAD14-OP-GP TP506 TPAD14-OP-GPTP506 TPAD14-OP-GP TP507 TPAD14-OP-GPTP507 TPAD14-OP-GP TP508 TPAD14-OP-GPTP508 TPAD14-OP-GP TP509 TPAD14-OP-GPTP509 TPAD14-OP-GP TP510 TPAD14-OP-GPTP510 TPAD14-OP-GP

Layout Note:

Signal Routing Guideline: SM_RCOMP keep routing length less than 500 mils. Trace width = 15mil

RN501

XDP_TDI XDP_TMS XDP_TDO XDP_TCLK

XDP_TRST#

RN501

1 2 3 4 5

SRN51J-1-GP

R511 51R2J-2-GPR511 51R2J-2-GP

1 2

8 7 6

1D05V_VTT

A A

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

A3 Date: Sheet of

Date: Sheet of

CPU (THERMAL/CLOCK/PM )

Enrico Caruso 14 MLK DIS

Tuesday, January 03, 2012

Taipei Hsien 221, Taiwan, R.O.C.

5 104

X02

5

4

3

2

1

SSID = CPU

3 OF 9

CPU1C

D D

M_A_DQ[63:0]15 M_B_DQ[63:0]14

C C

B B

M_A_DQ[63:0]

M_A_BS015 M_A_BS115 M_A_BS215

M_A_CAS#15 M_A_RAS#15 M_A_WE#15

M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63

G10

N10

M10

AG6 AG5

AK6 AK5 AH5 AH6

AK8 AK9

AH8 AH9 AL9

AL8 AP11 AN11

AL12 AM12 AM11

AL11 AP12 AN12

AJ14 AH14

AL15 AK15

AL14 AK14

AJ15 AH15

AE10

AF10

AE8 AD9 AF9

C5

SA_DQ0

D5

SA_DQ1

D3

SA_DQ2

D2

SA_DQ3

D6

SA_DQ4

C6

SA_DQ5

C2

SA_DQ6

C3

SA_DQ7

F10

SA_DQ8

F8

SA_DQ9 SA_DQ10

G9

SA_DQ11

F9

SA_DQ12

F7

SA_DQ13

G8

SA_DQ14

G7

SA_DQ15

K4

SA_DQ16

K5

SA_DQ17

K1

SA_DQ18

J1

SA_DQ19

J5

SA_DQ20

J4

SA_DQ21

J2

SA_DQ22

K2

SA_DQ23

M8

SA_DQ24 SA_DQ25

N8

SA_DQ26

N7

SA_DQ27 SA_DQ28

M9

SA_DQ29

N9

SA_DQ30

M7

SA_DQ31 SA_DQ32 SA_DQ33 SA_DQ34 SA_DQ35 SA_DQ36 SA_DQ37

AJ5

SA_DQ38

AJ6

SA_DQ39

AJ8

SA_DQ40 SA_DQ41

AJ9

SA_DQ42 SA_DQ43 SA_DQ44 SA_DQ45 SA_DQ46 SA_DQ47 SA_DQ48 SA_DQ49 SA_DQ50 SA_DQ51 SA_DQ52 SA_DQ53 SA_DQ54 SA_DQ55 SA_DQ56 SA_DQ57 SA_DQ58 SA_DQ59 SA_DQ60 SA_DQ61 SA_DQ62 SA_DQ63

SA_BS0 SA_BS1

V6

SA_BS2

SA_CAS# SA_RAS# SA_WE#

IVY-BRIDGE

DDR SYSTEM MEMORY A

3 OF 9

SA_CK0

SA_CLK#0

SA_CKE0

SA_CK1

SA_CLK#1

SA_CKE1

SA_CK2

SA_CLK#2

SA_CKE2

SA_CK3

SA_CLK#3

SA_CKE3

SA_CS#0 SA_CS#1 SA_CS#2 SA_CS#3

SA_ODT0 SA_ODT1 SA_ODT2 SA_ODT3

SA_DQS#0 SA_DQS#1 SA_DQS#2 SA_DQS#3 SA_DQS#4 SA_DQS#5 SA_DQS#6 SA_DQS#7

SA_DQS0 SA_DQS1 SA_DQS2 SA_DQS3 SA_DQS4 SA_DQS5 SA_DQS6 SA_DQS7

SA_MA0 SA_MA1 SA_MA2 SA_MA3 SA_MA4 SA_MA5 SA_MA6 SA_MA7 SA_MA8

SA_MA9 SA_MA10 SA_MA11 SA_MA12 SA_MA13 SA_MA14 SA_MA15

AB6 AA6 V9

AA5 AB5 V10

AB4 AA4 W9

AB3 AA3 W10

AK3 AL3 AG1 AH1

AH3 AG3 AG2 AH2

C4 G6 J3 M6 AL6 AM8 AR12 AM15

D4 F6 K3 N6 AL5 AM9 AR11 AM14

AD10 W1 W2 W7 V3 V2 W3 W6 V1 W5 AD8 V4 W4 AF8 V5 V7

M_A_DQS#0 M_A_DQS#1 M_A_DQS#2 M_A_DQS#3 M_A_DQS#4 M_A_DQS#5 M_A_DQS#6 M_A_DQS#7

M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6 M_A_DQS7

M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14 M_A_A15

M_A_DIMA_CLK_DDR0 15 M_A_DIMA_CLK_DDR#0 15 M_A_DIMA_CKE0 15

M_A_DIMA_CLK_DDR1 15 M_A_DIMA_CLK_DDR#1 15 M_A_DIMA_CKE1 15

M_A_DIMA_CS#0 15 M_A_DIMA_CS#1 15

M_A_DIMA_ODT0 15 M_A_DIMA_ODT1 15

M_A_DQS#[7:0] 15

M_A_DQS[7:0] 15

M_A_A[15:0] 15

M_B_DQ[63:0]

M_B_BS014 M_B_BS114 M_B_BS214

M_B_CAS#14 M_B_RAS#14 M_B_WE#14

M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63

D10

K10

AM5 AM6 AR3

AP3 AN3 AN2 AN1

AP2

AP5 AN9

AT5

AT6

AP6 AN8 AR6 AR5 AR9

AJ11

AT8

AT9

AH11

AR8

AJ12

AH12

AT11 AN14 AR14

AT14

AT12 AN15 AR15

AT15

AA9 AA7

AA10

AB8 AB9

CPU1D

IVY-BRIDGE

C9

SB_DQ0

A7

SB_DQ1 SB_DQ2

C8

SB_DQ3

A9

SB_DQ4

A8

SB_DQ5

D9

SB_DQ6

D8

SB_DQ7

G4

SB_DQ8

F4

SB_DQ9

F1

SB_DQ10

G1

SB_DQ11

G5

SB_DQ12

F5

SB_DQ13

F2

SB_DQ14

G2

SB_DQ15

J7

SB_DQ16

J8

SB_DQ17 SB_DQ18

K9

SB_DQ19

J9

SB_DQ20

J10

SB_DQ21

K8

SB_DQ22

K7

SB_DQ23

M5

SB_DQ24

N4

SB_DQ25

N2

SB_DQ26

N1

SB_DQ27

M4

SB_DQ28

N5

SB_DQ29

M2

SB_DQ30

M1

SB_DQ31 SB_DQ32 SB_DQ33 SB_DQ34 SB_DQ35 SB_DQ36 SB_DQ37 SB_DQ38 SB_DQ39 SB_DQ40 SB_DQ41 SB_DQ42 SB_DQ43 SB_DQ44 SB_DQ45 SB_DQ46 SB_DQ47 SB_DQ48 SB_DQ49 SB_DQ50 SB_DQ51 SB_DQ52 SB_DQ53 SB_DQ54

R6

SB_DQ55 SB_DQ56 SB_DQ57 SB_DQ58 SB_DQ59 SB_DQ60 SB_DQ61 SB_DQ62 SB_DQ63

SB_BS0 SB_BS1 SB_BS2

SB_CAS# SB_RAS# SB_WE#

DDR SYSTEM MEMORY B

4 OF 9

SB_CK0

SB_CLK#0

SB_CKE0

SB_CK1

SB_CLK#1

SB_CKE1

SB_CK2

SB_CLK#2

SB_CKE2

SB_CK3

SB_CLK#3

SB_CKE3

SB_CS#0 SB_CS#1 SB_CS#2 SB_CS#3

SB_ODT0 SB_ODT1 SB_ODT2 SB_ODT3

SB_DQS#0 SB_DQS#1 SB_DQS#2 SB_DQS#3 SB_DQS#4 SB_DQS#5 SB_DQS#6 SB_DQS#7

SB_DQS0 SB_DQS1 SB_DQS2 SB_DQS3 SB_DQS4 SB_DQS5 SB_DQS6 SB_DQS7

SB_MA0 SB_MA1 SB_MA2 SB_MA3 SB_MA4 SB_MA5 SB_MA6 SB_MA7 SB_MA8

SB_MA9 SB_MA10 SB_MA11 SB_MA12 SB_MA13 SB_MA14 SB_MA15

AE2 AD2 R9

AE1 AD1 R10

AB2 AA2 T9

AA1 AB1 T10

AD3 AE3 AD6 AE6

AE4 AD4 AD5 AE5

D7 F3 K6 N3 AN5 AP9 AK12 AP15

C7 G3 J6 M3 AN6 AP8 AK11 AP14

AA8 T7 R7 T6 T2 T4 T3 R2 T5 R3 AB7 R1 T1 AB10 R5 R4

M_B_DQS#0 M_B_DQS#1 M_B_DQS#2 M_B_DQS#3 M_B_DQS#4 M_B_DQS#5 M_B_DQS#6 M_B_DQS#7

M_B_DQS0 M_B_DQS1 M_B_DQS2 M_B_DQS3 M_B_DQS4 M_B_DQS5 M_B_DQS6 M_B_DQS7

M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14 M_B_A15

M_B_DIMB_CLK_DDR0 14 M_B_DIMB_CLK_DDR#0 14 M_B_DIMB_CKE0 14

M_B_DIMB_CLK_DDR1 14 M_B_DIMB_CLK_DDR#1 14 M_B_DIMB_CKE1 14

M_B_DIMB_CS#0 14 M_B_DIMB_CS#1 14

M_B_DIMB_ODT0 14 M_B_DIMB_ODT1 14

M_B_DQS#[7:0] 14

M_B_DQS[7:0] 14

M_B_A[15:0] 14

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Enrico Caruso 14 MLK DIS

Tuesday, January 03, 2012

Date: Sheet of

CPU (DDR)

Taipei Hsien 221, Taiwan, R.O.C.

6 104

1

X02

5

4

3

2

1

SSID = CPU

D D

5 OF 9

CPU1E

CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15 CFG16 CFG17

AK28

CFG0

AK29

CFG1

AL26

CFG2

AL27

CFG3

AK26

CFG4

AL29

CFG5

AL30

CFG6

AM31

CFG7

AM32

CFG8

AM30

CFG9

AM28

CFG10

AM26

CFG11

AN28

CFG12

AN31

CFG13

AN26

CFG14

AM27

CFG15

AK31

CFG16

AN29

CFG17

AJ31

VAXG_VAL_SENSE

AH31

VSSAXG_VAL_SENSE

AJ33

VCC_VAL_SENSE

AH33

VSS_VAL_SENSE

AJ26

RSVD#AJ26

F25

RSVD#F25

F24

RSVD#F24

F23

RSVD#F23

D24

RSVD#D24

G25

RSVD#G25

G24

RSVD#G24

E23

RSVD#E23

D23

RSVD#D23

C30

RSVD#C30

A31

RSVD#A31

B30

RSVD#B30

B29

RSVD#B29

D30

RSVD#D30

B31

RSVD#B31

A30

RSVD#A30

C29

RSVD#C29

J20

RSVD#J20

B18

RSVD#B18

1

TP703TPAD14-OP-GP TP703TPAD14-OP-GP

1

TP701TPAD14-OP-GP TP701TPAD14-OP-GP

1

TP702TPAD14-OP-GP TP702TPAD14-OP-GP

1

TP723TPAD14-OP-GP TP723TPAD14-OP-GP

1

TP704TPAD14-OP-GP TP704TPAD14-OP-GP

1

TP705TPAD14-OP-GP TP705TPAD14-OP-GP

1

TP706TPAD14-OP-GP TP706TPAD14-OP-GP

1

TP707TPAD14-OP-GP TP707TPAD14-OP-GP

1

TP708TPAD14-OP-GP TP708TPAD14-OP-GP

1

TP709TPAD14-OP-GP TP709TPAD14-OP-GP

1

TP710TPAD14-OP-GP TP710TPAD14-OP-GP

1

C C

B B

TP711TPAD14-OP-GP TP711TPAD14-OP-GP

1

TP712TPAD14-OP-GP TP712TPAD14-OP-GP

1

TP713TPAD14-OP-GP TP713TPAD14-OP-GP

VAXG_VAL_SENSE

1

TP719TPAD14-OP-GP TP719TPAD14-OP-GP TP720TPAD14-OP-GP TP720TPAD14-OP-GP TP721TPAD14-OP-GP TP721TPAD14-OP-GP TP722TPAD14-OP-GP TP722TPAD14-OP-GP

VSSAXG_VAL_SENSE

1

VCC_VAL_SENSE

1

VSS_VAL_SENSE

1

IVY-BRIDGE

CFG

RESERVED

5 OF 9

VCC_DIE_SENSE VSS_DIE_SENSE

RSVD#L7

RSVD#AG7

RSVD#AE7 RSVD#AK2

RSVD#W8

RSVD#AT26

RSVD#AM33

RSVD#AJ27

RSVD#T8

RSVD#J16 RSVD#H16 RSVD#G16

RSVD_NCTF#AR35 RSVD_NCTF#AT34 RSVD_NCTF#AT33 RSVD_NCTF#AP35 RSVD_NCTF#AR34

RSVD_NCTF#B34 RSVD_NCTF#A33 RSVD_NCTF#A34 RSVD_NCTF#B35

RSVD_NCTF#C35

RSVD#AJ32

RSVD#AK32

BCLK_ITP

BCLK_ITP#

AH27 AH26

L7 AG7 AE7 AK2

W8

AT26 AM33 AJ27

T8 J16 H16 G16

AR35 AT34 AT33 AP35 AR34

B34 A33 A34 B35 C35

AJ32 AK32

AN35 AM35

VCC_DIE_SENSE VSS_DIE_SENSE

CPU_NCTF_AR34

CPU_NCTF_B34

BCLK_ITP BCLK_ITP#

1

TP714 TPAD14-OP-GPTP714 TPAD14-OP-GP

1

TP715 TPAD14-OP-GPTP715 TPAD14-OP-GP

1

BCLK_ITP 20 BCLK_ITP# 20

TP716 TPAD14-OP-GPTP716 TPAD14-OP-GP

TP717 TPAD14-OP-GPTP717 TPAD14-OP-GP

CFG6

CFG2

CFG4

CFG5

DY

12

R701

R701 1KR2J-1-GP

1KR2J-1-GP

CFG7

DY

DIS

12

DY

12

R702

R702 1KR2J-1-GP

1KR2J-1-GP

12

R703

1KR2J-1-GP

12

R704

1KR2J-1-GP

R705

R705 1KR2J-1-GP

1KR2J-1-GP

PEG Static Lane Reversal

CFG[2]

1: Normal Operation; Lane # definition matches socket pin map definition

0:Lane Reversed

Display Port Presence Strap

CFG[4]

1: Disabled; No Physical Display Port attached to Embedded Display Port

0: Enabled; An external Display Port device is connected to the Embedded Display Port

PCIE Port Bifurcation Straps

CFG[6:5]

11: x16 - Device 1 functions 1 and 2 disabled

10: x8, x8 - Device 1 function 1 enabled ; function 2 disabled 01: Reserved - (Device 1 function 1 disabled ; function 2 enabled) 00: x8,x4,x4 - Device 1 functions 1 and 2 enabled

J15

RSVD#J15

A A

5

RSVD_NCTF#AT2 RSVD_NCTF#AT1

RSVD_NCTF#AR1

4

AT2 AT1 AR1

CPU_NCTF_AT1

1

TP718 TPAD14-OP-GPTP718 TPAD14-OP-GP

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Tuesday, January 03, 2012

Date: Sheet of

3

2

Date: Sheet of

CPU (RESERVED)

Enrico Caruso 14 MLK DIS

Taipei Hsien 221, Taiwan, R.O.C.

7 104

1

X02

SSID = CPU

5

4

3

2

1

D D

C C

B B

A A

Voltage Rail

VCC_CORE(DC) VAXG(DC) VCCIO VDDQ 1.5 VCCSA VCCPLL

Refer to PDDG rev 0.8

PROCESSOR CORE POWER

VCC_CORE

53A

Decap

12

C801

SC22U6D3V5MX-2GP

12

C820

DY

SC4D7U6D3V3KX-GP

12

C816

SC22U6D3V5MX-2GP

12

X00

C837

SC22U6D3V5MX-2GP

X00 2011-10-06

Decap

12

C802

C803

SC22U6D3V5MX-2GP

Decap

12

C819

DY

SC4D7U6D3V3KX-GP

Decap

12

C821

SC22U6D3V5MX-2GP

12

C836

SC22U6D3V5MX-2GP

Voltage(V)

0.3~1.35 0~1.3

1

0.9

1.8

12

C804

SC22U6D3V5MX-2GP

12

C818

DY

SC22U6D3V5MX-2GP

12

C822

SC10U6D3V5KX-1GP

12

C835

SC22U6D3V5MX-2GP

12

C806

12

C817

C823

SC22U6D3V5MX-2GP

12

C834

Iccmax(A)

53 33

8.5 10 6

1.5

12

C807

SC22U6D3V5MX-2GP

12

C812

SC22U6D3V5MX-2GP

12

C824

12

SC22U6D3V5MX-2GP

VCC_CORE

SC22U6D3V5MX-2GP

12

C811

SC22U6D3V5MX-2GP

12

C825

SC22U6D3V5MX-2GP

12

C833

SC10U6D3V5KX-1GP

12

X00

SC22U6D3V5MX-2GP

C832

C827

C826

SC22U6D3V5MX-2GP

12

C831

C828

SC22U6D3V5MX-2GP

AG35 AG34 AG33 AG32 AG31 AG30 AG29 AG28 AG27 AG26 AF35 AF34 AF33 AF32 AF31 AF30 AF29 AF28 AF27 AF26 AD35 AD34 AD33 AD32 AD31 AD30 AD29 AD28 AD27 AD26 AC35 AC34 AC33 AC32 AC31 AC30 AC29 AC28 AC27 AC26 AA35 AA34 AA33 AA32 AA31 AA30 AA29 AA28 AA27 AA26

Y35 Y34 Y33 Y32 Y31 Y30 Y29 Y28 Y27 Y26 V35 V34 V33 V32 V31 V30 V29 V28 V27 V26 U35 U34 U33 U32 U31 U30 U29 U28 U27 U26 R35 R34 R33 R32 R31 R30 R29 R28 R27 R26 P35 P34 P33 P32 P31 P30 P29 P28 P27 P26

CPU1F

VCC1 VCC2 VCC3 VCC4 VCC5 VCC6 VCC7 VCC8 VCC9 VCC10 VCC11 VCC12 VCC13 VCC14 VCC15 VCC16 VCC17 VCC18 VCC19 VCC20 VCC21 VCC22 VCC23 VCC24 VCC25 VCC26 VCC27 VCC28 VCC29 VCC30 VCC31 VCC32 VCC33 VCC34 VCC35 VCC36 VCC37 VCC38 VCC39 VCC40 VCC41 VCC42 VCC43 VCC44 VCC45 VCC46 VCC47 VCC48 VCC49 VCC50 VCC51 VCC52 VCC53 VCC54 VCC55 VCC56 VCC57 VCC58 VCC59 VCC60 VCC61 VCC62 VCC63 VCC64 VCC65 VCC66 VCC67 VCC68 VCC69 VCC70 VCC71 VCC72 VCC73 VCC74 VCC75 VCC76 VCC77 VCC78 VCC79 VCC80 VCC81 VCC82 VCC83 VCC84 VCC85 VCC86 VCC87 VCC88 VCC89 VCC90 VCC91 VCC92 VCC93 VCC94 VCC95 VCC96 VCC97 VCC98 VCC99 VCC100

POWER

IVY-BRIDGE

CORE SUPPLY

PEG AND DDR

VCC_SENSE VSS_SENSE

VCCIO_SENSE

VSS_SENSE_VCCIO

SENSE LINES SVID

6 OF 9

VCCIO1 VCCIO2 VCCIO3 VCCIO4 VCCIO5 VCCIO6 VCCIO7 VCCIO8

VCCIO9 VCCIO10 VCCIO11 VCCIO12 VCCIO13 VCCIO14 VCCIO15 VCCIO16 VCCIO17 VCCIO18 VCCIO19 VCCIO20 VCCIO21 VCCIO22 VCCIO23 VCCIO24

VCCIO25 VCCIO26 VCCIO27 VCCIO28 VCCIO29 VCCIO30 VCCIO31 VCCIO32 VCCIO33 VCCIO34 VCCIO35 VCCIO36 VCCIO37 VCCIO38 VCCIO39

VCCIO40

VIDALERT#

VIDSCLK VIDSOUT

AH13 AH10 AG10 AC10 Y10 U10 P10 L10 J14 J13 J12 J11 H14 H12 H11 G14 G13 G12 F14 F13 F12 F11 E14 E12

E11 D14 D13 D12 D11 C14 C13 C12 C11 B14 B12 A14 A13 A12 A11

J23

AJ29 AJ30 AJ28

AJ35 AJ34

B10 A10

H_CPU_SVIDALR T# H_CPU_SVIDC LK H_CPU_SVIDD AT

12

C805

1D05V_VTT

Decap

12

C809

C808

DY

SC10U6D3V3MX-GP

SC4D7U6D3V3KX-GP

12

R803

R803 43R2J-GP

43R2J-GP

1 2

R807

R807 10R2F-L-GP

10R2F-L-GP

R806

R806 10R2F-L-GP

10R2F-L-GP

SC10U6D3V3MX-GP

12

C829

C830

SC10U6D3V5KX-1GP

1D05V_VTT

12

R804

R805

75R2F-2-GP

Layout Note:

1. PH/PL resisors place close CPU

2. SENSE signal recommend differential routing

VCC_CORE

12

R801

R801 100R2F-L1-GP- U

100R2F-L1-GP- U

12

R802

R802 100R2F-L1-GP- U

100R2F-L1-GP- U

VCCIO_SENSE 45 VSSIO_SENSE 45

130R2F-1-GP

8.5A

12

C838

DY

SC22U6D3V5MX-2GP

SC10U6D3V5KX-1GP

12

C842

C843

SC10U6D3V5KX-1GP

1D05V_VTT

12

C839

C840

SC10U6D3V5KX-1GP

1D05V_VTT

Decap

12

C845

C844

SC10U6D3V5KX-1GP

Layout Note:

VR_SVID_ALERT# 42

H_CPU_SVIDC LK 42

H_CPU_SVIDD AT 42

Layout Note:

1. PH/PL resisors place close CPU

2. SENSE signal recommend differential routing

VCCSENSE 42 VSSSENSE 42

Is it need reserved 0 ohm? asked power team PIC: Willis

Decap

12

C841

SC22U6D3V5MX-2GP

SC10U6D3V5KX-1GP

R803, R804, R805 need close to CPU Alert# signal must be routed between the Clock and Data lines to reduce the cross talk between them

Wistron Corporation

21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih,

21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih, Taipei Hsie n 221, Taiwan, R.O. C.

Taipei Hsie n 221, Taiwan, R.O. C.

Title

Size Document Num ber Rev

Size Document Num ber Rev A2

A2

Enrico Caruso 14 MLK DIS

Tuesday, January 03, 2012

Date: Sheet of

5

4

3

2

Date: Sheet of

Taipei Hsie n 221, Taiwan, R.O. C.

CPU (VCC_CORE)

8 104

1

8 104

X02

5

4

3

2

1

SSID = CPU

POWER

CPU1G

AT24 AT23 AT21 AT20 AT18

AT17 AR24 AR23 AR21 AR20 AR18 AR17 AP24 AP23 AP21 AP20 AP18 AP17 AN24 AN23 AN21 AN20 AN18 AN17 AM24 AM23 AM21 AM20 AM18 AM17

AL24

AL23

AL21

AL20

AL18

AL17 AK24 AK23 AK21 AK20 AK18 AK17

AJ24

AJ23

AJ21

AJ20

AJ18

AJ17 AH24 AH23 AH21 AH20 AH18 AH17

B6 A6 A2

CPU1G

VAXG1 VAXG2 VAXG3 VAXG4 VAXG5 VAXG6 VAXG7 VAXG8 VAXG9 VAXG10 VAXG11 VAXG12 VAXG13 VAXG14 VAXG15 VAXG16 VAXG17 VAXG18 VAXG19 VAXG20 VAXG21 VAXG22 VAXG23 VAXG24 VAXG25 VAXG26 VAXG27 VAXG28 VAXG29 VAXG30 VAXG31 VAXG32 VAXG33 VAXG34 VAXG35 VAXG36 VAXG37 VAXG38 VAXG39 VAXG40 VAXG41 VAXG42 VAXG43 VAXG44 VAXG45 VAXG46 VAXG47 VAXG48 VAXG49 VAXG50 VAXG51 VAXG52 VAXG53 VAXG54

VCCPLL1 VCCPLL2 VCCPLL3

VCC_GFXCORE

DY

33A

SC22U6D3V5MX-2GP

12

C901

SC22U6D3V5MX-2GP

12

C900

12

C906

C902

SC22U6D3V5MX-2GP

12

C928

C927

D D

Decap

C C

VAXG Output Decoupling Recommendation: 2 x 470 uF at Bottom Socket Edge 2 x 22 uF at Top Socket Cavity 4 x 22 uF at Top Socket Edge 2 x 22 uF at Bottom Socket Cavity 4 x 22 uF at Bottom Socket Edge

De-Cap 22uF x 1 X00-05/30

SC22U6D3V5MX-2GP

12

C908

DY

SC22U6D3V5MX-2GP

12

C929

SC22U6D3V5MX-2GP

C920

SC22U6D3V5MX-2GP

C921

VCC_GFXCORE

SC22U6D3V5MX-2GP

12

C924

SC22U6D3V5MX-2GP

12

C926

Do not have 2 x 470 uF

B B

A A

1D8V_S0

1.5A

SC1U10V2KX-1GP

SC10U6D3V5KX-1GP

C923

C938

12

VCCPLL Output Decoupling Recommendation: 1 x 330 uF, 6m 2 x 1 uF (0402) Bottom socket Cavity 1 x 10 uF (0805) Bottom socket edge



SC1U10V2KX-1GP

X00X00

C937

12

NEC, 330uF, 2.5V, B2 ESR=9m Iripple=3.073A



POWER

IVY-BRIDGE

GRAPHICS

1.8V RAIL

SENSE

VREFMISC

DDR3 -1.5V RAILS

SA RAIL

Do not have 1 x 330 uF

5

4

7 OF 9

VAXG_SENSE

VSSAXG_SENSE

LINES

SM_VREF

SA_DIMM_VREFDQ SB_DIMM_VREFDQ

VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8

VDDQ9 VDDQ10 VDDQ11 VDDQ12 VDDQ13 VDDQ14 VDDQ15

VCCSA1 VCCSA2 VCCSA3 VCCSA4 VCCSA5 VCCSA6 VCCSA7 VCCSA8

VCCSA_SENSE

VCCSA_VID0 VCCSA_VID1

VCCIO_SEL

VCCIO_SEL: SNB: Floating IVY: GND

DDR_WR_VREFA DDR_WR_VREFB

AK35 AK34

Layout Note:

+V_SM_VREF_CNT should have 10 mil trace width

AL1

DDR_WR_VREFA

B4

DDR_WR_VREFB

D1

AF7 AF4 AF1 AC7 AC4 AC1 Y7 Y4 Y1 U7 U4 U1 P7 P4 P1

M27 M26 L26 J26 J25 J24 H26 H25

H23

C22 C24

H_SNB_IVB#_PWRCTRL

A19

4

RN902

RN902 SRN1KJ-7-GP

SRN1KJ-7-GP

DY

1

2 3

3

C909

12

DY

C934

12

VCCSA_SENSE

SC10U6D3V5KX-1GP

DY

SC10U6D3V5KX-1GP

VCC_AXG_SENSE 42 VSS_AXG_SENSE 42

SC10U6D3V5KX-1GP

C910

12

6A

SC10U6D3V5KX-1GP

C936

12

R910

1 2

VCCSA_SEL0

1

+V_SM_VREF_CNT 37

SC10U6D3V5KX-1GP

C911

12

0D85V_S0

SC10U6D3V5KX-1GP

C935

12

10R2J-2-GP

VCCSA_SEL1 48

TP901 TPAD14-OP-GPTP901 TPAD14-OP-GP

SC10U6D3V5KX-1GP

C912

Decap

12

0D85V_S0

VCC_AXG_SENSE VSS_AXG_SENSE

10A

SC22U6D3V5MX-2GP

C913

VCC_GFXCORE

12

R906

R906 100R2F-L1-GP-U

100R2F-L1-GP-U

Voltage Rail

VCC_CORE(DC) VAXG(DC) VCCIO

12

R907

R907 100R2F-L1-GP-U

100R2F-L1-GP-U

VDDQ 1.5 VCCSA VCCPLL

Refer to PDDG rev 0.8

Layout Note:

1. PH/PL resisors place close CPU

2. SENSE signal recommend differential routing

1D5V_S0

SC10U6D3V5KX-1GP

C914

12

TC915

DY

ST330U2VDM-4-GP

79.33719.20L

2nd = 77.C3371.13L

VDDQ Output Decoupling Recommendation: 1 x 330 uF 6 x 10 uF

VCCSA Output Decoupling Recommendation: 1 x 330 uF, 6m 2 x 10 uF at Bottom Socket Cavity 1 x 10 uF at Bottom Socket Edge

Do not have 1 x 330 uF



Do not have 1 x 330 uF

R910 close to pin H23.

VCCSA_SEL0 VCCSA_SEL1

1

23

RN901

RN901 SRN1KJ-7-GP

SRN1KJ-7-GP

DY

4

CRB: 10K DG: 1K

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Enrico Caruso 14 MLK DIS

Tuesday, January 03, 2012

Date: Sheet of

2

Date: Sheet of

Voltage(V)

0.3~1.35 0~1.3

1

Iccmax(A)

53 33

8.5 10

0.9

1.8

6

1.5

VCCSA Power Select

Voltage(V)

0.9

LV & ULV

0.85

Others

0.8

VID[0] VID[1]

0

0 1

0.725

0.675

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

CPU (VCC_GFXCORE)

9 104

1

0

01

11

X02

5

4

3

2

1

SSID = CPU

9 OF 9

8 OF 9

CPU1H

AT35

VSS1

AT32

VSS2

D D

C C

B B

AT29 AT27 AT25 AT22 AT19 AT16 AT13 AT10

AT7 AT4

AT3 AR25 AR22 AR19 AR16 AR13 AR10

AR7

AR4

AR2 AP34 AP31 AP28 AP25 AP22 AP19 AP16 AP13 AP10

AP7

AP4

AP1 AN30 AN27 AN25 AN22 AN19 AN16 AN13 AN10

AN7

AN4 AM29 AM25 AM22 AM19 AM16 AM13 AM10

AM7 AM4 AM3 AM2

AM1 AL34 AL31 AL28 AL25 AL22 AL19 AL16 AL13 AL10

AL7 AL4

AL2 AK33 AK30 AK27 AK25 AK22 AK19 AK16 AK13 AK10

AK7

AK4

AJ25

VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65 VSS66 VSS67 VSS68 VSS69 VSS70 VSS71 VSS72 VSS73 VSS74 VSS75 VSS76 VSS77 VSS78 VSS79 VSS80

IVY-BRIDGE

VSS

8 OF 9

VSS81 VSS82 VSS83 VSS84 VSS85 VSS86 VSS87 VSS88 VSS89 VSS90 VSS91 VSS92 VSS93 VSS94 VSS95 VSS96 VSS98

VSS99 VSS100 VSS101 VSS102 VSS103 VSS104 VSS105 VSS106 VSS107 VSS108 VSS109 VSS110 VSS111 VSS112 VSS113 VSS114 VSS115 VSS116 VSS117 VSS118 VSS119 VSS120 VSS121 VSS122 VSS123 VSS124 VSS125 VSS126 VSS127 VSS128 VSS129 VSS130 VSS131 VSS132 VSS133 VSS134 VSS135 VSS136 VSS137 VSS138 VSS139 VSS140 VSS141 VSS142 VSS143 VSS144 VSS145 VSS146 VSS147 VSS148 VSS149 VSS150 VSS151 VSS152 VSS153 VSS154 VSS155 VSS156 VSS157 VSS158 VSS159 VSS160

AJ22 AJ19 AJ16 AJ13 AJ10 AJ7 AJ4 AJ3 AJ2 AJ1 AH35 AH34 AH32 AH30 AH29 AH28 AH25 AH22 AH19 AH16 AH7 AH4 AG9 AG8 AG4 AF6 AF5 AF3 AF2 AE35 AE34 AE33 AE32 AE31 AE30 AE29 AE28 AE27 AE26 AE9 AD7 AC9 AC8 AC6 AC5 AC3 AC2 AB35 AB34 AB33 AB32 AB31 AB30 AB29 AB28 AB27 AB26 Y9 Y8 Y6 Y5 Y3 Y2 W35 W34 W33 W32 W31 W30 W29 W28 W27 W26 U9 U8 U6 U5 U3 U2

T35 T34 T33 T32 T31 T30 T29 T28 T27 T26

N35 N34 N33 N32 N31 N30 N29 N28 N27 N26 M34

L33 L30 L27

K35 K32 K29 K26

J34

J31 H33 H30 H27 H24 H21 H18 H15 H13 H10

G35 G32 G29 G26 G23 G20 G17 G11 F34 F31 F29

CPU1I

IVY-BRIDGE

VSS161 VSS162 VSS163 VSS164 VSS165 VSS166 VSS167 VSS168 VSS169 VSS170

P9

VSS171

P8

VSS172

P6

VSS173

P5

VSS174

P3

VSS175

P2

VSS176 VSS177 VSS178 VSS179 VSS180 VSS181 VSS182 VSS183 VSS184 VSS185 VSS186 VSS187 VSS188 VSS189 VSS190

L9

VSS191

L8

VSS192

L6

VSS193

L5

VSS194

L4

VSS195

L3

VSS196

L2

VSS197

L1

VSS198 VSS199 VSS200 VSS201 VSS202 VSS203 VSS204 VSS205 VSS206 VSS207 VSS208 VSS209 VSS210 VSS211 VSS212 VSS213

H9

VSS214

H8

VSS215

H7

VSS216

H6

VSS217

H5

VSS218

H4

VSS219

H3

VSS220

H2

VSS221

H1

VSS222 VSS223 VSS224 VSS225 VSS226 VSS227 VSS228 VSS229 VSS230 VSS231 VSS232 VSS233

IVY-BRIDGE

VSS

9 OF 9

VSS234 VSS235 VSS236 VSS237 VSS238 VSS239 VSS240 VSS241 VSS242 VSS243 VSS244 VSS245 VSS246 VSS247 VSS248 VSS249 VSS250 VSS251 VSS252 VSS253 VSS254 VSS255 VSS256 VSS257 VSS258 VSS259 VSS260 VSS261 VSS262 VSS263 VSS264 VSS265 VSS266 VSS267 VSS268 VSS269 VSS270 VSS271 VSS272 VSS273 VSS274 VSS275 VSS276 VSS277 VSS278 VSS279 VSS280 VSS281 VSS282 VSS283 VSS284 VSS285

F22 F19 E30 E27 E24 E21 E18 E15 E13 E10 E9 E8 E7 E6 E5 E4 E3 E2 E1 D35 D32 D29 D26 D20 D17 C34 C31 C28 C27 C25 C23 C10 C1 B22 B19 B17 B15 B13 B11 B9 B8 B7 B5 B3 B2 A35 A32 A29 A26 A23 A20 A3

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Friday, December 30, 2011

Date: Sheet of

CPU (VSS)

Enrico Caruso 14 MLK DIS

Taipei Hsien 221, Taiwan, R.O.C.

10 104

1

X02

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Enrico Caruso 14 MLK DIS

Friday, December 30, 2011

Date: Sheet of

XDP

Taipei Hsien 221, Taiwan, R.O.C.

11 104

1

X02

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet of

Enrico Caruso 14 MLK DIS

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

1

12 104Friday, December 30, 2011

X02

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet of

Enrico Caruso 14 MLK DIS

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

1

13 104Friday, December 30, 2011

X02

5

SSID = MEMORY

M_B_BS26 M_B_BS06

M_B_BS16

M_B_DQ[63:0]6

12

C1422

DY

SC1U6D3V2KX-GP

M_B_DIMB_ODT06 M_B_DIMB_ODT16

M_VREF_CA_D IMM1 M_VREF_DQ_D IMM1

DDR3_DR AMRST#15,37

M_B_A[15:0] 6

C1418

SC10U6D3V5KX-1GP

M_B_DQS#[7:0] 6 M_B_DQS[7:0] 6

0D75V_S0

DDR_VREF _S3

R1405

X02

0R0402-PAD

M_VREF_CA_D IMM1

1 2

12

X02

12

DDR_VREF _S3

1 2

12

0D75V_S0

C1423

R1404

R1404 0R0402-PAD

0R0402-PAD

C1411

12

D D

C C

B B

DY

SCD1U10V2KX-5GP

M_VREF_DQ_D IMM1

12

DY

SCD1U10V2KX-5GP

Place these caps close to VTT1 and VTT2.

12

C1419

DY

SC1U6D3V2KX-GP

12

C1425

C1424

SCD1U10V2KX-5GP

SC2D2U10V3KX-1GP

12

C1412

C1413

SCD1U10V2KX-5GP

SC2D2U10V3KX-1GP

12

C1420

C1421

DY

SC1U6D3V2KX-GP

M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14 M_B_A15

M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63

M_B_DQS#0 M_B_DQS#1 M_B_DQS#2 M_B_DQS#3 M_B_DQS#4 M_B_DQS#5 M_B_DQS#6 M_B_DQS#7

M_B_DQS0 M_B_DQS1 M_B_DQS2 M_B_DQS3 M_B_DQS4 M_B_DQS5 M_B_DQS6 M_B_DQS7

DM2

98

A0

97

A1

96

A2

95

A3

92

A4

91

A5

90

A6

86

A7

89

A8

85

A9

107

A10/AP

84

A11

83

A12

119

A13

80

A14

78

A15

79

A16/BA2

109

BA0

108

BA1

5

DQ0

7

DQ1

15

DQ2

17

DQ3

4

DQ4

6

DQ5

16

DQ6

18

DQ7

21

DQ8

23

DQ9

33

DQ10

35

DQ11

22

DQ12

24

DQ13

34

DQ14

36

DQ15

39

DQ16

41

DQ17

51

DQ18

53

DQ19

40

DQ20

42

DQ21

50

DQ22

52

DQ23

57

DQ24

59

DQ25

67

DQ26

69

DQ27

56

DQ28

58

DQ29

68

DQ30

70

DQ31

129

DQ32

131

DQ33

141

DQ34

143

DQ35

130

DQ36

132

DQ37

140

DQ38

142

DQ39

147

DQ40

149

DQ41

157

DQ42

159

DQ43

146

DQ44

148

DQ45

158

DQ46

160

DQ47

163

DQ48

165

DQ49

175

DQ50

177

DQ51

164

DQ52

166

DQ53

174

DQ54

176

DQ55

181

DQ56

183

DQ57

191

DQ58

193

DQ59

180

DQ60

182

DQ61

192

DQ62

194

DQ63

10

DQS0#

27

DQS1#

45

DQS2#

62

DQS3#

135

DQS4#

152

DQS5#

169

DQS6#

186

DQS7#

12

DQS0

29

DQS1

47

DQS2

64

DQS3

137

DQS4

154

DQS5

171

DQS6

188

DQS7

116

ODT0

120

ODT1

126

VREF_CA

1

VREF_DQ

30

RESET#

203

VTT1

204

VTT2

DDR3-204P- 48-GP

62.10017.P41

2nd = 62.10017.P61

3rd = 62.10017.N41

RAS# CAS# CS0#

CS1# CKE0

CKE1

CK0#

CK1#

EVENT#

VDDSPD

NC#1 NC#2

NC#/TEST

VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8

VDD9 VDD10 VDD11 VDD12 VDD13 VDD14 VDD15 VDD16 VDD17 VDD18

4

NP1

NP2

110 113

WE#

115 114

121 73

74 101

CK0

103 102

CK1

104 11

DM0

28

DM1

46

DM2

63

DM3

136

DM4

153

DM5

170

DM6

187

DM7

200

SDA

202

SCL

198 199

SA0_DIM1

197

SA0

SA1_DIM1

201

SA1

77 122 125

75 76 81 82 87 88 93 94 99 100 105 106 111 112 117 118 123 124

2

VSS

3

VSS

8

VSS

9

VSS

13

VSS

14

VSS

19

VSS

20

VSS

25

VSS

26

VSS

31

VSS

32

VSS

37

VSS

38

VSS

43

VSS

44

VSS

48

VSS

49

VSS

54

VSS

55

VSS

60

VSS

61

VSS

65

VSS

66

VSS

71

VSS

72

VSS

127

VSS

128

VSS

133

VSS

134

VSS

138

VSS

139

VSS

144

VSS

145

VSS

150

VSS

151

VSS

155

VSS

156

VSS

161

VSS

162

VSS

167

VSS

168

VSS

172

VSS

173

VSS

178

VSS

179

VSS

184

VSS

185

VSS

189

VSS

190

VSS

195

VSS

196

VSS

205

VSS

206

VSS

1D5V_S3

M_B_RAS# 6 M_B_WE# 6 M_B_CAS# 6

M_B_DIMB_CS#0 6 M_B_DIMB_CS#1 6

M_B_DIMB_CKE0 6 M_B_DIMB_CKE1 6

M_B_DIMB_CLK_DD R0 6 M_B_DIMB_CLK_DD R#0 6

M_B_DIMB_CLK_DD R1 6 M_B_DIMB_CLK_DD R#1 6

PCH_SMBDAT A 15,20,65 PCH_SMBCLK 15,20,65

TS#_DIMM0_1 15

SCD1U10V2KX- 5GP

12

C1401

DY

79.33719.20L

2nd = 77.C3371.13L

Layout Note: Place these Caps near SO-DIMMA.

X00

Layout Note: For S3 reduction circuit's 1D5V return pass.

3

3D3V_S0

C1402

C1402 SC2D2U10V3KX- 1GP

SC2D2U10V3KX- 1GP

1D5V_S3

12

TC1401

DY

ST330U2VDM-4-GP

Decap

12

C1426 SCD1U10V2KX-5GP

1 2

DY

C1427 SCD1U10V2KX-5GP

1 2

DY

C1428 SCD1U10V2KX-5GP

1 2

DY

C1429 SCD1U10V2KX-5GP

1 2

DY

SODIMM A DECOUPLING

12

C1403

SC10U6D3V5KX-1GP

Decap

12

C1415

C1414

SC1U6D3V2KX-GP

SA1_DIM1 SA0_DIM1

12

C1404

Decap

C1416

SC1U6D3V2KX-GP

1D5V_S31D5V_S0

3D3V_S0

DY

SC10U6D3V5KX-1GP

12

R1402

R1402 10KR2J-3-GP

10KR2J-3-GP

R1401

R1401 10KR2J-3-GP

10KR2J-3-GP

C1405

SC10U10V5ZY-1GP

C1417

SC1U6D3V2KX-GP

2

Note: If SA0 DIM0 = 0, SA1_DIM0 = 0 SO-DIMMA SPD Address is 0xA0 SO-DIMMA TS Address is 0x30

If SA0 DIM0 = 0, SA1_DIM0 = 1 SO-DIMMA SPD Address is 0xA2 SO-DIMMA TS Address is 0x32

Thermal EVENT

TS#_DIMM0_1

1 2

R1403

12

C1406

DY

SC10U6D3V5KX-1GP

12

C1407

DY

SC10U6D3V5KX-1GP

12

C1409

C1410

C1408

SC10U10V5ZY-1GP

C1410

DY

SC10U6D3V5KX-1GP

3D3V_S0

10KR2J-3-GP

SC10U6D3V5KX-1GP

1

A A

Wistron Corporation

21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih,

21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih, Taipei Hsie n 221, Taiwan, R.O. C.

Taipei Hsie n 221, Taiwan, R.O. C.

Title

Size Document Num ber Rev

Size Document Num ber Rev A2

A2

Enrico Caruso 14 MLK DIS

Tuesday, January 03, 2012

Date: Sheet of

5

4

3

2

Date: Sheet of

Taipei Hsie n 221, Taiwan, R.O. C.

DDR3-SODIMM2

1

14 104

X02

5

SSID = MEMORY

M_A_A[15:0] 6

D D

DDR_VREF _S3

R1504

R1504 0R0402-PAD

0R0402-PAD

X02

DDR_VREF _S3

X02

C C

B B

1 2

12

1 2

12

C1523

SCD1U10V2KX-5GP

R1503

R1503 0R0402-PAD

0R0402-PAD

C1515

SCD1U10V2KX-5GP

0D75V_S0

M_VREF_CA_D IMM0

12

DY

C1524

M_VREF_DQ_D IMM0

12

DY

C1516

12

C1518

DY

12

C1522

SC2D2U10V3KX-1GP

12

C1517

SC2D2U10V3KX-1GP

Place these caps close to VTT1 and VTT2.

12

C1519

SC1U6D3V2KX-GP

SCD1U10V2KX-5GP

12

C1520

DY

SC1U6D3V2KX-GP

12

C1521

SC1U6D3V2KX-GP

M_A_DIMA_ODT06 M_A_DIMA_ODT16

DDR3_DR AMRST#14,37

M_A_BS26 M_A_BS06

M_A_BS16

M_A_DQ[63:0]6

M_A_DQS#[7:0] 6 M_A_DQS[7:0] 6

M_VREF_CA_D IMM0 M_VREF_DQ_D IMM0

0D75V_S0

M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14 M_A_A15

M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63

M_A_DQS#0 M_A_DQS#1 M_A_DQS#2 M_A_DQS#3 M_A_DQS#4 M_A_DQS#5 M_A_DQS#6 M_A_DQS#7

M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6 M_A_DQS7

98 97 96 95 92 91 90 86 89 85

107

84 83

119

80 78 79

109 108

5

7 15 17

4

6 16 18 21 23 33 35 22 24 34 36 39 41 51 53 40 42 50 52 57 59 67 69 56 58 68 70

129 131 141 143 130 132 140 142 147 149 157 159 146 148 158 160 163 165 175 177 164 166 174 176 181 183 191 193 180 182 192 194

10 27 45 62

135 152 169 186

12 29 47 64

137 154 171 188

116 120

126

1 30

203 204

4

DM1

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15 A16/BA2

BA0 BA1

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63

DQS0# DQS1# DQS2# DQS3# DQS4# DQS5# DQS6# DQS7#

DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7

ODT0 ODT1

VREF_CA VREF_DQ

RESET#

VTT1 VTT2

DDR3-204P- 42-GP

62.10017.N61

2nd = 62.10017.Q41

3rd = 62.10017.N11

RAS# CAS# CS0#

CS1# CKE0

CKE1

CK0#

CK1#

EVENT#

VDDSPD

NC#1 NC#2

NC#/TEST

VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8

VDD9 VDD10 VDD11 VDD12 VDD13 VDD14 VDD15 VDD16 VDD17 VDD18

NP1 NP2

WE#

CK0

CK1

DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7

SDA SCL

SA0 SA1

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

3

NP1 NP2

110 113 115

114 121

73 74

101 103

102 104

11 28 46 63 136 153 170 187

200 202

198 199

SA0_DIM0

197

SA1_DIM0

201 77

122 125

75 76 81 82 87 88 93 94 99 100 105 106 111 112 117 118 123 124

2 3 8 9 13 14 19 20 25 26 31 32 37 38 43 44 48 49 54 55 60 61 65 66 71 72 127 128 133 134 138 139 144 145 150 151 155 156 161 162 167 168 172 173 178 179 184 185 189 190 195 196 205 206

1D5V_S3

M_A_RAS# 6 M_A_WE# 6 M_A_CAS# 6

M_A_DIMA_CS#0 6 M_A_DIMA_CS#1 6

M_A_DIMA_CKE0 6 M_A_DIMA_CKE1 6

M_A_DIMA_CLK_DD R0 6 M_A_DIMA_CLK_DD R#0 6

M_A_DIMA_CLK_DD R1 6 M_A_DIMA_CLK_DD R#1 6

PCH_SMBDAT A 14,20,65 PCH_SMBCLK 14,20,65

TS#_DIMM0_1 14

C1501

SCD1U10V2KX- 5GP

1D5V_S3

Layout Note: Place these Caps near SO-DIMMB.

12

C1502

DY

SC2D2U10V3KX- 1GP

SODIMM B DECOUPLING

12

C1503

DY

SC10U10V5ZY-1GP

Decap

12

C1511

SC1U6D3V2KX-GP

SA1_DIM0 SA0_DIM0

12

DY

12

C1504

C1512

3D3V_S0

DY

SC10U10V5ZY-1GP

Decap

SC1U6D3V2KX-GP

12

C1505

C1513

R1502

R1502 10KR2J-3-GP

10KR2J-3-GP

12

SC10U6D3V5KX-1GP

Decap

12

SC1U6D3V2KX-GP

Note: SO-DIMMB SPD Address is 0xA4 SO-DIMMB TS Address is 0x34

SO-DIMMB is placed farther from

R1501

R1501 10KR2J-3-GP

10KR2J-3-GP

1 2

12

C1507

C1506

DY

SC10U6D3V5KX-1GP

C1514

SC1U6D3V2KX-GP

the Processor than SO-DIMMA

12

C1509

C1508

DY

SC10U10V5ZY-1GP

SC10U6D3V5KX-1GP

C1510

SC10U6D3V5KX-1GP

2

1

A A

Wistron Corporation

21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih,

21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih, Taipei Hsie n 221, Taiwan, R.O. C.

Taipei Hsie n 221, Taiwan, R.O. C.

Title

Size Document Num ber Rev

Size Document Num ber Rev A2

A2

Enrico Caruso 14 MLK DIS

Tuesday, January 03, 2012

Date: Sheet of

5

4

3

2

Date: Sheet of

Taipei Hsie n 221, Taiwan, R.O. C.

DDR3-SODIMM1

1

15 104

X02

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet of

Enrico Caruso 14 MLK DIS

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

1

16 104Friday, December 30, 2011

X02

5

4

3

2

1

SSID = PCH

D D

3D3V_S0

RN1701

1 2 3

SRN2K2J-1-GP

RN1702

2 3 1

SRN100KJ-6-GP

C C

B B

4

L_CTRL_DATA L_CTRL_CLK

L_BKLT_EN LVDS_VDD_EN

Layout Note:

Place near PCH; trace spacing=20mil

Layout Note:

Place near PCH

PCH_CRT_BLUE

678

123

4 5

PCH_CRT_GREEN

PCH_CRT_RED

RN1705

RN1705 SRN150F-1-GP

SRN150F-1-GP

CRT_HSYNC50 CRT_VSYNC50

L_BKLT_EN27 LVDS_VDD_EN49

L_BKLT_CTRL49 LVDS_DDC_CLK_R49

LVDS_DDC_DATA_R49

12

R1701

R1701 2K37R2F-GP

2K37R2F-GP

LVDSA_CLK#49 LVDSA_CLK49

LVDSA_DATA0#49 LVDSA_DATA1#49 LVDSA_DATA2#49

LVDSA_DATA049 LVDSA_DATA149 LVDSA_DATA249

PCH_CRT_BLUE50 PCH_CRT_GREEN50 PCH_CRT_RED50

PCH_CRT_DDCCLK50 PCH_CRT_DDCDATA50

X01 1109

Layout Note:

Place near PCH; trace spacing=30mil

TP1701TPAD14-OP-GP TP1701TPAD14-OP-GP

RN1703

1 2 3

SRN22-3-GP

R1702

1KR2D-1-GP

L_CTRL_CLK L_CTRL_DATA

LVDS_IBG LVDS_VBG

1

PCH_CRT_HSYNC

4

PCH_CRT_VSYNC

DAC_IREF_R

12

PCH1D

J47

L_BKLTEN

M45

L_VDD_EN

P45

L_BKLTCTL

T40

L_DDC_CLK

K47

L_DDC_DATA

T45

L_CTRL_CLK

P39

L_CTRL_DATA

AF37

LVD_IBG

AF36

LVD_VBG

AE48

LVD_VREFH

AE47

LVD_VREFL

AK39

LVDSA_CLK#

AK40

LVDSA_CLK

AN48

LVDSA_DATA#0

AM47

LVDSA_DATA#1

AK47

LVDSA_DATA#2

AJ48

LVDSA_DATA#3

AN47

LVDSA_DATA0

AM49

LVDSA_DATA1

AK49

LVDSA_DATA2

AJ47

LVDSA_DATA3

AF40

LVDSB_CLK#

AF39

LVDSB_CLK

AH45

LVDSB_DATA#0

AH47

LVDSB_DATA#1

AF49

LVDSB_DATA#2

AF45

LVDSB_DATA#3

AH43

LVDSB_DATA0

AH49

LVDSB_DATA1

AF47

LVDSB_DATA2

AF43

LVDSB_DATA3

N48

CRT_BLUE

P49

CRT_GREEN

T49

CRT_RED

T39

CRT_DDC_CLK

M40

CRT_DDC_DATA

M47

CRT_HSYNC

M49

CRT_VSYNC

T43

DAC_IREF

T42

CRT_IRTN

PANTHER-GP-NF

71.PANTH.00U

LVDS

Digital Display Interface

CRT

4 OF 10

SDVO_TVCLKINN SDVO_TVCLKINP

SDVO_STALLN SDVO_STALLP

SDVO_INTN SDVO_INTP

SDVO_CTRLCLK

SDVO_CTRLDATA

DDPB_AUXN DDPB_AUXP

DDPB_HPD

DDPB_0N DDPB_0P DDPB_1N DDPB_1P DDPB_2N DDPB_2P DDPB_3N DDPB_3P

DDPC_CTRLCLK

DDPC_CTRLDATA

DDPC_AUXN DDPC_AUXP

DDPC_HPD

DDPC_0N DDPC_0P DDPC_1N DDPC_1P DDPC_2N DDPC_2P DDPC_3N DDPC_3P

DDPD_CTRLCLK

DDPD_CTRLDATA

DDPD_AUXN DDPD_AUXP

DDPD_HPD

DDPD_0N DDPD_0P DDPD_1N DDPD_1P DDPD_2N DDPD_2P DDPD_3N DDPD_3P

AP43 AP45

AM42 AM40

AP39 AP40

P38 M39

AT49 AT47 AT40

AV42 AV40 AV45 AV46 AU48 AU47 AV47 AV49

P46 P42

AP47 AP49 AT38

AY47 AY49 AY43 AY45 BA47 BA48 BB47 BB49

M43 M36

AT45 AT43 BH41

BB43 BB45 BF44 BE44 BF42 BE42 BJ42 BG42

SRN2K2J-1-GP

RN1706

3D3V_S0

4

1

2 3

PCH_HDMI_CLK 51 PCH_HDMI_DATA 51

HDMI_PCH_DET 51 HDMI_DATA2_R# 51

HDMI_DATA2_R 51 HDMI_DATA1_R# 51 HDMI_DATA1_R 51 HDMI_DATA0_R# 51 HDMI_DATA0_R 51 HDMI_CLK_R# 51 HDMI_CLK_R 51

PCH_CRT_BLUE

C1722

12

SC10P50V2JN-4GP

DY

DY DY

A A

DY

5

PCH_CRT_GREEN

C1723

12

SC10P50V2JN-4GP

PCH_CRT_RED

C1724

12

SC10P50V2JN-4GP

4

Notes: 1K 0.5%

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Tuesday, January 03, 2012

Date: Sheet of

3

2

Date: Sheet of

PCH ( LVDS/CRT/DDI )

Enrico Caruso 14 MLK DIS

Taipei Hsien 221, Taiwan, R.O.C.

17 104

1

X02

5

4

3

2

1

SSID = PCH

5 OF 10

RN1801

SRN8K2J-2-GP-U

PCH_GPIO52 INT_PIRQB# INT_PIRQH#

D D

3D3V_S0

PCH_GPIO50 PCH_GPIO54

C C

TP1808TPAD14-OP-GP TP1808TPAD14-OP-GP

1

TP1809TPAD14-OP-GP TP1809TPAD14-OP-GP

B B

1

Boot Bios Strap

GNT1#/GPIO51

0 0

0

1

12

DY

A A

DY

R1801

R1801 4K7R2J-2-GP

4K7R2J-2-GP

SRN8K2J-2-GP-U

1 2 3 4 5 6

RN1803

1 2 3

SRN10KJ-5-GP

BBS_BIT1 BBS_BIT0

1

0

1

PCI_GNT3#

4

10

INT_PIRQD#

9

INT_PIRQE#

8

INT_PIRQC#INT_PIRQA#

7

INT_PIRQG#

3D3V_S0

USB3.0/2.0 Mapping Table

USB 3.0 Port USB 2.0 port Port 1 Port 2 Port 3 Port 4

BBS_BIT0 21

Boot BIOS LocationSATA1GP/GPIO19

LPC

Reserved

SPI(Default)

Port 0 Port 1 Port 2 Port 3

CLK_PCI_LPC71 CLK_PCI_FB20 CLK_PCI_KBC27

EC1802

INT_PIRQA# INT_PIRQB# INT_PIRQC# INT_PIRQD#

PCH_GPIO50 PCH_GPIO52 PCH_GPIO54

BBS_BIT1

1

PCH_GPIO53 PCI_GNT3#

INT_PIRQE#

PCI_PME# PCI_PLTRST#

CLK_PCI_LPC_R CLK_PCI_FB_R CLK_PCI_KBC_R

TP1806TPAD14-OP-GP TP1806TPAD14-OP-GP

SATA_ODD_DA#56

1 2

DY

SC4D7P50V2CN-1GP

INT_PIRQG#

INT_PIRQH#

TP1802TPAD14-OP-GP TP1802TPAD14-OP-GP

R1804 22R2J-2-GP

1 2

LPC

R1805 22R2J-2-GPR1805 22R2J-2-GP

1 2

R1806 22R2J-2-GPR1806 22R2J-2-GP

1 2

EC1801

1 2

EC1801

EC1803

1 2

DY

SC4D7P50V2CN-1GP

BG26

BJ26

BH25

BJ16 BG16 AH38 AH37 AK43 AK45

C18 N30

AH12

AM4 AM5

Y13 K24

L24 AB46 AB45

B21

M20 AY16 BG46

BE28 BC30 BE32

BJ32 BC28 BE30

BF32 BG32 AV26 BB26 AU28 AY30 AU26 AY26 AV28

AW30

K40 K38 H38

G38

C46 C44 E40

D47 E42 F46

G42 G40

C42 D44

K10

H49 H43

K42 H40

H3

C6

J48

PCH1E

TP1 TP2 TP3 TP4 TP5 TP6 TP7 TP8 TP9 TP10 TP11 TP12 TP13 TP14 TP15 TP16 TP17 TP18 TP19 TP20

TP21 TP22 TP23 TP24

USB3RN1 USB3RN2 USB3RN3 USB3RN4 USB3RP1 USB3RP2 USB3RP3 USB3RP4 USB3TN1 USB3TN2 USB3TN3 USB3TN4 USB3TP1 USB3TP2 USB3TP3 USB3TP4

PIRQA# PIRQB# PIRQC# PIRQD#

REQ1#/GPIO50 REQ2#/GPIO52 REQ3#/GPIO54

GNT1#/GPIO51 GNT2#/GPIO53 GNT3#/GPIO55

PIRQE#/GPIO2 PIRQF#/GPIO3 PIRQG#/GPIO4 PIRQH#/GPIO5

PME# PLTRST#

CLKOUT_PCI0 CLKOUT_PCI1 CLKOUT_PCI2 CLKOUT_PCI3 CLKOUT_PCI4

PANTHER-GP-NF

X00

3D3V_S5

RSVD

PCI

USB_OC#14_15 USB_OC#6_7

USB_OC#4_5

USB

X02

A16 Swap Override jumper

PCI_GNT#3 Low = A16 swap override/Top-Block

Swap Override enabled High = Default

5

4

PLT_RST#5,27,31,65,71,83

R1816

100KR2J-1-GP

DY

1 2

12

DY

PCI_PLTRST#

R1807

0R0402-PAD

C1801

C1801 SC220P50V2KX-3GP

SC220P50V2KX-3GP

3

5 OF 10

RSVD1 RSVD2 RSVD3 RSVD4

RSVD5 RSVD6

RSVD7 RSVD8

RSVD9 RSVD10 RSVD11 RSVD12 RSVD13 RSVD14 RSVD15 RSVD16 RSVD17 RSVD18 RSVD19 RSVD20 RSVD21 RSVD22

RSVD23 RSVD24

RSVD25 RSVD26

RSVD27 RSVD28

RSVD29

USBP0N

USBP0P

USBP1N

USBP1P

USBP2N

USBP2P

USBP3N

USBP3P

USBP4N

USBP4P

USBP5N

USBP5P

USBP6N

USBP6P

USBP7N

USBP7P

USBP8N

USBP8P

USBP9N

USBP9P

USBP10N

USBP10P

USBP11N

USBP11P

USBP12N

USBP12P

USBP13N

USBP13P

USBRBIAS#

USBRBIAS

OC0#/GPIO59 OC1#/GPIO40 OC2#/GPIO41 OC3#/GPIO42 OC4#/GPIO43

OC5#/GPIO9 OC6#/GPIO10 OC7#/GPIO14

RN1802

RN1802 SRN8K2J-2-GP-U

SRN8K2J-2-GP-U

1 2 3 4 5 6

AY7 AV7 AU3 BG4

AT10 BC8

AU2 AT4 AT3 AT1 AY3 AT5 AV3 AV1 BB1 BA3 BB5 BB3 BB7 BE8 BD4 BF6

AV5 AV10

AT8 AY5

BA2 AT12

BF3

USB2.0 Signal Group

C24 A24 C25 B25 C26 A26 K28 H28 E28 D28 C28 A28 C29 B29 N28 M28 L30 K30 G30 E30 C30 A30 L32 K32 G32 E32 C32 A32

USB_RBIAS

C33

B33

A14 K20 B17 C16 L16 A16 D14 C14

10 9 8 7

USB_OC#0_1 USB_OC#2_3 USB_OC#4_5 USB_OC#6_7 USB_OC#8_9 USB_OC#10_11 USB_OC#12_13 USB_OC#14_15

USB_OC#0_1 USB_OC#12_13USB_OC#10_11 USB_OC#8_9 USB_OC#2_3

2

1 2

R1811

R1811 22D6R2F-L1-GP

22D6R2F-L1-GP

X00

3D3V_S5

USB_PN1 61 USB_PP1 61

USB_PN5 32 USB_PP5 32

USB_PN8 82 USB_PP8 82 USB_PN9 82 USB_PP9 82

USB_PN11 65 USB_PP11 65 USB_PN12 49 USB_PP12 49

USB Table

Pair

NC

0

USB2.0 port1

1

NC

2

NC

3

NC

4

Card reader

5

NC

6

NC

7

USB2.0 port2

8

USB2.0 port3

9

NC

10

Mini Card1

11

CAMERA

12

NC

13

Layout Note:

1. USBRBIAS/# use 50ohm single-ended impedance spacing to other signal=15mil

2. Length < 500mil

USB_OC#0_1 61

USB_OC#8_9 61

Title

Size Document Number Rev

A3

Tuesday, January 03, 2012

Date: Sheet of

PCH ( PCI/USB/NVRAM )

Enrico Caruso 14 MLK DIS

Device

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

18 104

1

X02

5

4

3

2

1

SSID = PCH

3 OF 10

PCH1C

DMI_RXN[3:0]4

D D

Layout Note:

DMI_ZCOMP keep W=4 mils and routing length less than 500 mils. DMI_IRCOMP keep W=4 mils and routing length less than 500 mils.

C C

PM_DRAM_PWRGD37

B B

Sequence: S0_PWR_GOOD after PM_SLP_S3# delay 200 ms

A A

3D3V_S0

XDP_DBRESET#5

SYS_PWROK36

S0_PWR_GOOD27,36

RUNPWROK45,46,47,93

RSMRST#_KBC27

PM_PWRBTN#27

AC_PRESENT27

BATLOW #27

3D3V_S5

R1924 0R0402-PADR1924 0R0402-PAD

8 7 6

R1909 100KR2J-1-GPR1909 100KR2J-1-GP

1 2

R1922 10KR2J-3-GP

R1922 10KR2J-3-GP R1920 10KR2J-3-GP

R1920 10KR2J-3-GP

R1908 10KR2J-3-GPR1908 10KR2J-3-GP

R1926 100KR2J-1-GP

1 2

R1904 100KR2J-1-GPR1904 100KR2J-1-GP

1 2

5

DMI_RXP[3:0]4

DMI_TXN[3:0]4

DMI_TXP[3:0]4

1D05V_VTT

R1901 49D9R2F-GPR1901 49D9R2F-GP

1 2

R1902 750R2F-GPR1902 750R2F-GP

1 2

R1905 1KR2J-1-GPR1905 1KR2J-1-GP

X02

1 2

R1907 0R2J-2-GP

X02

R1912

1 2

RN1901

1 2 3 45

SRN10KJ-6-GP

12

DY

12

DY

12

DY

TP1907TPAD14-OP-GP TP1907TPAD14-OP-GP

1 2

R1906

DY

X02

1 2

0R0402-PAD

BATLOW # PCH_WAKE# PM_RI# SUS_PW R_ACK

AC_PRESENT

PM_PWRBTN# PM_SLP_LAN#

PM_RSMRST#

SYS_PWROK PWROK

1

DMI_RXN0 DMI_RXN1 DMI_RXN2 DMI_RXN3

DMI_RXP0 DMI_RXP1 DMI_RXP2 DMI_RXP3

DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3

DMI_TXP0 DMI_TXP1 DMI_TXP2 DMI_TXP3

DMI_COMP_R RBIAS_CPY

SUSACK#

PWROK

0R0402-PAD

MEPWROK

PM_RSMRST#

SUS_PW R_ACK

PM_PWRBTN#

AC_PRESENT

BATLOW #

PM_RI#

PCIE_WAKE#: CRB: 1K CEKLT: 10K

PCH1C

BC24

DMI0RXN

BE20

DMI1RXN

BG18

DMI2RXN

BG20

DMI3RXN

BE24

DMI0RXP

BC20

DMI1RXP

BJ18

DMI2RXP

BJ20

DMI3RXP

AW24

DMI0TXN

AW20

DMI1TXN

BB18

DMI2TXN

AV18

DMI3TXN

AY24

DMI0TXP

AY20

DMI1TXP

AY18

DMI2TXP

AU18

DMI3TXP

BJ24

DMI_ZCOMP

BG25

DMI_IRCOMP

BH21

DMI2RBIAS

C12

SUSACK#

K3

SYS_RESET#

P12

SYS_PWROK

L22

PWROK

L10

APWROK

B13

DRAMPWROK

C21

RSMRST#

K16

SUSWARN#/SUSPWRDNACK/GPIO30

E20

PWRBTN#

H20

ACPRESENT/GPIO31

E10

BATLOW#/GPIO72

A10

RI#

PANTHER-GP-NF

71.PANTH.00U

4

DMI

SUS_STAT#/GPIO61

System Power Management

3 OF 10

FDI_RXN0 FDI_RXN1 FDI_RXN2 FDI_RXN3 FDI_RXN4 FDI_RXN5 FDI_RXN6 FDI_RXN7

FDI_RXP0 FDI_RXP1 FDI_RXP2 FDI_RXP3 FDI_RXP4 FDI_RXP5 FDI_RXP6

FDI

FDI_RXP7

FDI_INT FDI_FSYNC0 FDI_FSYNC1 FDI_LSYNC0 FDI_LSYNC1

DSWVRMEN

DPWROK

WAKE#

CLKRUN#/GPIO32

SUSCLK/GPIO62

SLP_S5#/GPIO63

SLP_S4#

SLP_S3#

SLP_A#

SLP_SUS#

PMSYNCH

SLP_LAN#/GPIO29

BJ14 AY14 BE14 BH13 BC12 BJ12 BG10 BG9

BG14 BB14 BF14 BG13 BE12 BG12 BJ10 BH9

AW16 AV12 BC10 AV14 BB10

A18

E22

B9

N3

G8

N14

D10

H4

F4

G10

G16

AP14

K14

FDI_TXN0 FDI_TXN1 FDI_TXN2 FDI_TXN3 FDI_TXN4 FDI_TXN5 FDI_TXN6 FDI_TXN7

FDI_TXP0 FDI_TXP1 FDI_TXP2 FDI_TXP3 FDI_TXP4 FDI_TXP5 FDI_TXP6 FDI_TXP7

FDI_INT FDI_FSYNC0 FDI_FSYNC1 FDI_LSYNC0 FDI_LSYNC1

DSWODVREN

PCH_DPW ROK

PCH_WAKE#

PM_CLKRUN#

PM_SUS_STAT#

SUS_CLK

PM_SLP_S5#

PM_SLP_S4#

PM_SLP_S3#

PM_SLP_A#

PM_SLP_SUS#

H_PM_SYNC

PM_SLP_LAN#

3

FDI_TXN[7:0] 4

FDI_TXP[7:0] 4

FDI_INT 4 FDI_FSYNC0 4 FDI_FSYNC1 4 FDI_LSYNC0 4 FDI_LSYNC1 4

R1911 10KR2J-3-GP

1 2

DY

R1910 0R0402-PADR1910 0R0402-PAD

1 2

X02

R1929 0R0402-PADR1929 0R0402-PAD

1 2

X02

TP1901 TPAD14-OP-GPTP1901 TPAD14-OP-GP

1

R1913 0R0402-PADR1913 0R0402-PAD

1 2

X02

TP1902 TPAD14-OP-GPTP1902 TPAD14-OP-GP

1

TP1903 TPAD14-OP-GPTP1903 TPAD14-OP-GP

1

TP1904 TPAD14-OP-GPTP1904 TPAD14-OP-GP

1

TP1905 TPAD14-OP-GPTP1905 TPAD14-OP-GP

1

RTC_AUX_S5

PM_RSMRST#

PCH_SUSCLK_KBC

PM_CLKRUN#_EC 27

PCH_SUSCLK_KBC 27

PM_SLP_S4# 27,46

PM_SLP_S3# 27,36,37,47

H_PM_SYNC 5

EC1901

EC1901 SC4D7P50V2CN-1GP

SC4D7P50V2CN-1GP

1 2

DY

2

DSWODVREN - On Die DSW VR Enable

HIGH Enabled (DEFAULT)

LOW Disabled

RTC_AUX_S5

DSWODVREN

PM_CLKRUN#

Title

Size Document Number Rev

A3

Enrico Caruso 14 MLK DIS

Tuesday, January 03, 2012

Date: Sheet of

R1917 330KR2J-L1-GPR1917 330KR2J-L1-GP

1 2

R1919 8K2R2J-3-GPR1919 8K2R2J-3-GP

1 2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

PCH ( DMI/FDI/PM )

19 104

1

3D3V_S0

X02

5

SSID = PCH

S5 power rail CLKREQ#:

X00

PCIE_CLK_RQ0# PCIE_CLK_RQ4# PCIE_CLK_RQ3#

PCIE_CLK_REQ0# PCIE_CLK_REQ4#

D D

PCIE_CLK_REQ3#

3D3V_S5

PCIE_RXN465

PCIE_RXP465 PCIE_TXN465 PCIE_TXP465

PCIE_RXN231

PCIE_RXP231 PCIE_TXN231 PCIE_TXP231

C C

S0 power rail CLKREQ#: PCIECLKRQ[2:1]#

CLKOUT termination place close to PCH <500mil

X00

3D3V_S0

RN2018

1 2 3

SRN10KJ-5-GP

RN2001

1 2 3 4 5 6

SRN10KJ-L3-GP

C2005 SCD1U10V2KX-5GPC2005 SCD1U10V2KX-5GP C2006 SCD1U10V2KX-5GPC2006 SCD1U10V2KX-5GP

C2001 SCD1U10V2KX-5GPC2001 SCD1U10V2KX-5GP C2002 SCD1U10V2KX-5GPC2002 SCD1U10V2KX-5GP

CLK_PCIE_WLAN_REQ#

4

CLK_PCIE_WWAN_REQ#

1 2 1 2

PCIE_CLK_RQ2# PCIE_CLK_RQ1#

Layout Note:

CLK_PCIE_WLAN#65 CLK_PCIE_WLAN65

CLK_PCIE_WLAN_REQ#65

B B

CLK_PCIE_LAN#31 CLK_PCIE_LAN31

PCIE_CLK_LAN_REQ#31

A A

BCLK_ITP#7 BCLK_ITP7

5

PCIECLKRQ[0]# PCIECLKRQ[7:3]#

10 9

PCIE_CLK_LAN_REQ#

8

CLK_PCIE_NEW_REQ#

7

PEG_B_CLKRQ#

1 2 3

RN2012

0R4P2R-PAD

1 2 3

RN2014

0R4P2R-PAD

RN2023

1

DY

2 3

SRN0J-6-GP

3D3V_S5

EC_SWI#

PCIE_CLK_RQ5# PCIE_CLK_RQ7# PCIE_CLK_RQ6#

PCIE_TXN4_C PCIE_TXP4_C

PCIE_TXN2_C PCIE_TXP2_C

PCIE_CLK_REQ0#

CLK_PCIE_WWAN_REQ#

RN

CLK_PCH_SRC2_N

4

CLK_PCH_SRC2_P

X02 1229

PCIE_CLK_REQ3#

PCIE_CLK_REQ4#

RN

CLK_PCH_SRC5_N

4

CLK_PCH_SRC5_P

X02 1229

PEG_B_CLKRQ#

PCIE_CLK_REQ6#

CLK_PCIE_NEW_REQ# PCIE_CLK_XDP_N_R

4

PCIE_CLK_XDP_P_R

4

PCH1B

BG34

PERN1

BJ34

PERP1

AV32

PETN1

AU32

PETP1

BE34

PERN2

BF34

PERP2

BB32

PETN2

AY32

PETP2

BG36

PERN3

BJ36

PERP3

AV34

PETN3

AU34

PETP3

BF36

PERN4

BE36

PERP4

AY34

PETN4

BB34

PETP4

BG37

PERN5

BH37

PERP5

AY36

PETN5

BB36

PETP5

BJ38

PERN6

BG38

PERP6

AU36

PETN6

AV36

PETP6

BG40

PERN7

BJ40

PERP7

AY40

PETN7

BB40

PETP7

BE38

PERN8

BC38

PERP8

AW38

PETN8

AY38

PETP8

Y40

CLKOUT_PCIE0N

Y39

CLKOUT_PCIE0P

J2

PCIECLKRQ0#/GPIO73

AB49

CLKOUT_PCIE1N

AB47

CLKOUT_PCIE1P

M1

PCIECLKRQ1#/GPIO18

AA48

CLKOUT_PCIE2N

AA47

CLKOUT_PCIE2P

V10

PCIECLKRQ2#/GPIO20

Y37

CLKOUT_PCIE3N

Y36

CLKOUT_PCIE3P

A8

PCIECLKRQ3#/GPIO25

Y43

CLKOUT_PCIE4N

Y45

CLKOUT_PCIE4P

L12

PCIECLKRQ4#/GPIO26

V45

CLKOUT_PCIE5N

V46

CLKOUT_PCIE5P

L14

PCIECLKRQ5#/GPIO44

AB42

CLKOUT_PEG_B_N

AB40

CLKOUT_PEG_B_P

E6

PEG_B_CLKRQ#/GPIO56

V40

CLKOUT_PCIE6N

V42

CLKOUT_PCIE6P

T13

PCIECLKRQ6#/GPIO45

V38

CLKOUT_PCIE7N

V37

CLKOUT_PCIE7P

K12

PCIECLKRQ7#/GPIO46

AK14

CLKOUT_ITPXDP_N

AK13

CLKOUT_ITPXDP_P

PANTHER-GP-NF

71.PANTH.00U

4

NC

WLAN

NC

LAN

NC

NEW CARD

N/A

WLAN CLK

N/A

LAN CLK

N/A

New Card CLK

3

X02 1223

2 OF 10

EC_SWI#

SMBCLK

SMBDATA

SML0CLK

CL_CLK1

CL_DATA1

CL_RST1#

XTAL25_IN

E12 H14 C9

A12 C8 G12

C13 E14 M16

M7

T11

P10

M10

AB37 AB38

AV22 AU22

AM12 AM13

BF18 BE18

BJ30 BG30

G24 E24

AK7 AK5

K45

H45

V47 V49

Y47

K43 F47 H47 K49

3

SMB_CLK SMB_DATA

DRAMRST_CNTRL_PCH

SML0_CLK SML0_DATA

PCH_GPIO74 SML1_CLK SML1_DATA

CL_CLK

1

CL_DATA

1

CL_RST#

1

PEG_CLKREQ#

CLKOUT_PEG_A_N CLKOUT_PEG_A_P

CLKOUT_DMI_N CLKOUT_DMI_P

CLK_BUF_EXP_N CLK_BUF_EXP_P

CLK_BUF_CPYCLK_N CLK_BUF_CPYCLK_P

CLK_BUF_DOT96_N CLK_BUF_DOT96_P

CLK_BUF_CKSSCD_N CLK_BUF_CKSSCD_P

CLK_BUF_REF14

CLK_PCI_FB

XTAL25_IN XTAL25_OUT

XCLK_RCOMP

JTAG_TCK CLK_PCH_48M_L CLK_27M_VGA_R BOARD_ID1

SMBALERT#/GPIO11

SML0ALERT#/GPIO60

SMBUSController

SML1ALERT#/PCHHOT#/GPIO74

PCI-E*

Link

CLOCKS

FLEX CLOCKS

SML0DATA

SML1CLK/GPIO58

SML1DATA/GPIO75

PEG_A_CLKRQ#/GPIO47

CLKOUT_PEG_A_N CLKOUT_PEG_A_P

CLKOUT_DMI_N CLKOUT_DMI_P

CLKOUT_DP_N

CLKOUT_DP_P

CLKIN_DMI_N CLKIN_DMI_P

CLKIN_GND1_N CLKIN_GND1_P

CLKIN_DOT_96N CLKIN_DOT_96P

CLKIN_SATA_N CLKIN_SATA_P

REFCLK14IN

CLKIN_PCILOOPBACK

XTAL25_OUT

XCLK_RCOMP

CLKOUTFLEX0/GPIO64 CLKOUTFLEX1/GPIO65 CLKOUTFLEX2/GPIO66 CLKOUTFLEX3/GPIO67

EC_SWI# 27

DRAMRST_CNTRL_PCH 37

SML1_CLK 27

SML1_DATA 27

TP2001 TPAD14-OP-GPTP2001 TPAD14-OP-GP

TP2002 TPAD14-OP-GPTP2002 TPAD14-OP-GP

TP2003 TPAD14-OP-GPTP2003 TPAD14-OP-GP

RN

1

4

RN

2 3

RN2016

RN2016 0R4P2R-PAD

0R4P2R-PAD

1

4

2 3

RN2010

0R4P2R-PAD

RN2019

SRN10KJ-5-GP

RN2008

SRN10KJ-5-GP

RN2020

SRN10KJ-5-GP

RN2021

SRN10KJ-5-GP

R2008

10KR2J-3-GP

CLK_PCI_FB 18

R2007

1 2

90D9R2F-1-GP

DY

1 2

X00

1 2

TP2006 TPAD14-OP-GPTP2006 TPAD14-OP-GP

1

DY

R2001 22R2J-2-GP

R2001 22R2J-2-GP R2002 22R2J-2-GPR2002 22R2J-2-GP

PEG_CLKREQ#

Layout Note:

CLKOUT termination place close to PCH <500mil

X02 1229

2 3 1

1 2

BOARD_ID222

+VCCDIFFCLKN

2

3D3V_S5

DY

SML1_CLK

PEG_CLKREQ# 83

CLK_PCIE_VGA# 83 CLK_PCIE_VGA 83

CLK_EXP_N 5 CLK_EXP_P 5

4

10KR2J-3-GP

BOARD_ID2 BOARD_ID1

10KR2J-3-GP

JTAG_TCK_VGA 86 CLK_PCH_48M 32

2

12

R2005

R2005 10KR2J-3-GP

10KR2J-3-GP

12

R2004

R2004 10KR2J-3-GP

10KR2J-3-GP

SML1_DATA

X00

R2013

R2011

1

SMB_CLK SMB_DATA

SML0_DATA SML0_CLK

SML1_CLK SML1_DATA

PCIE_CLK_REQ6# PCH_GPIO74

3D3V_S0

SMB_DATA

SMB_CLK

3D3V_S03D3V_S0

12

DY

Title

Size Document Number Rev

A3

Date: Sheet of

DRAMRST_CNTRL_PCH

RN2009

1 2 3

3rd = 84.DMN66.03F

2nd = 84.2N702.A3F

3D3V_S0

10KR2J-3-GP

4

SRN4K7J-8-GP

84.2N702.F3F

S2

1

6

G1 G2

5

2

D1D2S1

34

Q2002

ME2N7002DKW-G-GP

RN2007

2 3 1

SRN2K2J-1-GP

3rd = 84.DMN66.03F

2nd = 84.2N702.A3F

84.2N702.F3F

6

G1 G2

5

Q2001

ME2N7002DKW-G-GP

XTAL25_IN

R2006

1M1R2J-GP

XTAL25_OUT

R2012

R2010

10KR2J-3-GP

Optimus(NV)

PCH ( PCI-E/SMBUS/CLOCK/CL)

Enrico Caruso 14 MLK DIS

Tuesday, January 03, 2012

4

2 3 1

1 2 3

R2009

1 2

1KR2J-1-GP

CRB : 1K CHKLT: 10K

THM_SML1_DATA 28,86

THM_SML1_CLK 28,86

4

S2

1 2

D1D2S1

34

X2001

2 3

1 2

PX(AMD)

DIS

UMA

XTAL-25MHZ-155-GP

82.30020.D41

2nd = 82.30020.G71

3rd = 82.30020.G61

BIOS UMA/Discrete Strap pin

BOARD_ID1

0

1

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

1

3D3V_S5

RN2003

1

SRN2K2J-1-GP

23

RN2004

1

SRN2K2J-1-GP

23

RN2005

RN2005 SRN2K2J-1-GP

SRN2K2J-1-GP

4

RN2006

4

SRN10KJ-5-GP

PCH_SMBDATA 14,15,65

PCH_SMBCLK 14,15,65

1 2

C2008

SC15P50V2JN-2-GP

41

C2007

SC15P50V2JN-2-GP

1 2

BOARD_ID2

20 104

0

1

0

1

X02

5

4

3

2

1

SSID = PCH

D D

HDA_CODEC_SDOUT29

C C

HDA_CODEC_RST#29 HDA_CODEC_BITCLK29

+3VS_+1.5VS_HDA_IO

3D3V_S0

B B

HDA_SPKR

+3VS_+1.5VS_HDA_IO

R2103 1KR2J-1-GPR2103 1KR2J-1-GP

RTCRST_ON27

R2125

10KR2J-3-GP

Flash Descriptor Security Overide/ Intel ME Debug Mode

HDA_SDOUT

DY

R2102

1 2

1KR2J-1-GP

R2106 1KR2J-1-GP

1 2

DY

No Reboot Strap

Low = Default High = No Reboot

1 2

12

RN2102

1 2 3

SRN33J-5-GP-U

Low = Default High = Enable

HDA_SDOUT

HDA_SPKR

*

HDA_SYNC

2nd = 84.2N702.W31

3rd = 84.2N702.J31

Layout Note:

Q2102

2N7002BK-GP

84.07002.I31

R212333R2J-2-GP R212333R2J-2-GP

12

HDA_RST#

4

HDA_BITCLK

*

RTC_AUX_S5

1 2 3

G

DS

Place close together.

HDA_SDOUT

RN2106

4

SRN20KJ-1-GP

C2103

SC1U6D3V2KX-GP

12

C2104

SC1U6D3V2KX-GP

12

Layout Note:

HDA_SDO and HDA_BCLK must be length matched to within 500 mils

ME_UNLOCK27

X00

1D05V_VTT

RUN_ENABLE

PLL ODVR VOLTAGE

Q2101

1 2

4

Q2101

2N7002BK-GP

HDA_SYNC

A A

HDA_SYNC: This strap is sampled on rising edge of RSMRST# and is used to sample 1.5V VccVRM supply mode. 1K external pull-up resistor is required on this signal on the board. Signal may have leakage paths via powered off devices (Audio Codec) and hence contend with the external pull-up. A blocking FET is recommended in such a case to isolate HDA_SYNC from the Audio Codec device until after the Strap sampling is complete.

Low = 1.8V High = 1.5V

*

HDA_CODEC_SYNC29

5

HDA_CODEC_SYNC_R HDA_SYNC

R2124

12

33R2J-2-GP

R2117

100KR2J-1-GP

Layout Note:

Place it at the open door location.

21

G2101

G2101 GAP-OPEN

GAP-OPEN

RTC_AUX_S5

Integrated SUS 1V VRM Enable

R2104

1M1R2J-GP

1 2

R2105

R2105 330KR2F-L-GP

330KR2F-L-GP

HDA_SDOUT

TP2105TPAD14-OP-GP TP2105TPAD14-OP-GP TP2106TPAD14-OP-GP TP2106TPAD14-OP-GP

Low = External VRs High = Internal VRs

12

INTVRMEN

HDA_SPKR29

HDA_SDIN029

R2107

1KR2J-1-GP

1 2

RTC_X1 RTC_X2 RTC_RST# SRTC_RST# SM_INTRUDER# PCH_INTVRMEN

HDA_BITCLK HDA_SYNC

HDA_RST#

follow DPDG 1.3

EC2103

SC4D7P50V2CN-1GP

PCH_JTAG_TCK_BUF PCH_JTAG_TMS PCH_JTAG_TDI PCH_JTAG_TDO

PCH_SPI_CLK PCH_SPI_CS0#

PCH_SPI_SI

R2111 51R2J-2-GP

1 2

DY

R2118 51R2J-2-GP

1 2

DY

R2119 51R2J-2-GP

1 2

DY

R2120 51R2J-2-GP

1 2

DY

SPI_CLK_R27,60 SPI_CS0#_R27,60

SPI_SI_R27,60 SPI_SO_R60

G

DS

84.07002.I31

2nd = 84.2N702.W31

3rd = 84.2N702.J31

HDA_CODEC_BITCLK

EC2102

DY

1 2

EC2102

SC4D7P50V2CN-1GP

DY

1 2

R2108 33R2J-2-GPR2108 33R2J-2-GP

1 2

R2109 33R2J-2-GPR2109 33R2J-2-GP

1 2

R2110 33R2J-2-GPR2110 33R2J-2-GP

HDA_CODEC_SDOUT

1 2

PCH_GPIO33

1

PCH_GPIO13

1

*

A20 C20 D20 G22 K22 C17

N34

L34 T10

K34

E34 G34 C34 A34

A36

C36 N32

J3 H7 K5 H1

T3

Y14

T1

V4 U3

PCH1A

RTCX1 RTCX2 RTCRST# SRTCRST# INTRUDER# INTVRMEN

HDA_BCLK HDA_SYNC SPKR HDA_RST#

HDA_SDIN0 HDA_SDIN1 HDA_SDIN2 HDA_SDIN3

HDA_SDO

HDA_DOCK_EN#/GPIO33 HDA_DOCK_RST#/GPIO13

JTAG_TCK JTAG_TMS JTAG_TDI JTAG_TDO

SPI_CLK SPI_CS0# SPI_CS1#

SPI_MOSI SPI_MISO

PANTHER-GP-NF

71.PANTH.00U

Layout Note:

JTAG

RTCIHDA

SPI

1 OF 10

FWH0/LAD0 FWH1/LAD1 FWH2/LAD2 FWH3/LAD3

LPC

FWH4/LFRAME#

LDRQ0#

LDRQ1#/GPIO23

SERIRQ

SATA0RXN

SATA0RXP SATA0TXN SATA0TXP

SATA1RXN

SATA1RXP

SATA 6G

SATA1TXN SATA1TXP

SATA2RXN

SATA2RXP SATA2TXN SATA2TXP

SATA3RXN

SATA3RXP SATA3TXN SATA3TXP

SATA4RXN

SATA4RXP SATA4TXN

SATA

SATA4TXP

SATA5RXN

SATA5RXP SATA5TXN SATA5TXP

SATAICOMPO

SATAICOMPI

SATA3RCOMPO

SATA3COMPI

SATA3RBIAS

SATALED# SATA0GP/GPIO21 SATA1GP/GPIO19

C38 A38 B37 C37

D36 E36

K36 V5

AM3 AM1 AP7 AP5

AM10 AM8 AP11 AP10

AD7 AD5 AH5 AH4

AB8 AB10 AF3 AF1

Y7 Y5 AD3 AD1

Y3 Y1 AB3 AB1

Y11 Y10

AB12 AB13

AH1

P3 V14 P1

LPC_AD0_R LPC_AD1_R LPC_AD2_R

LPC_FRAME#_L

SATA_COMP

SATA3_COMP

RBIAS_SATA3

SATA_LED# SATA_DET#0 BBS_BIT0

RN2104 SRN33J-5-GP-URN2104 SRN33J-5-GP-U

2 3 1

RN2105 SRN33J-5-GP-URN2105 SRN33J-5-GP-U

1 2 3

KB_DET# 69 INT_SERIRQ 27

SATA_RXN0 56 SATA_RXP0 56 SATA_TXN0 56 SATA_TXP0 56

SATA_RXN4 56 SATA_RXP4 56 SATA_TXN4 56 SATA_TXP4 56

R2112 37D4R2F-GPR2112 37D4R2F-GP

R2113 49D9R2F-GPR2113 49D9R2F-GP

R2114 750R2F-GPR2114 750R2F-GP

R2127

12

33R2J-2-GP

1 2

SATA_LED# 68

BBS_BIT0 18

LPC_AD0 LPC_AD1

4

LPC_AD2

4

LPC_AD3LPC_AD3_R

HDD1

ODD

INT_SERIRQ SATA_DET#0

LPC_AD[3..0]

LPC_FRAME# 27,71

ESATA

1D05V_VTT

Layout Note:

Place close PCH(<500mil)

RN2103

1 2 3

SRN10KJ-5-GP

LPC_AD[3..0] 27,71

3D3V_S0

4

close to branch point

RTC_X1

1 2

R2101 10MR2J-L-GPR2101 10MR2J-L-GP

X2101

1

4

12

X-32D768KHZ-40GPU

C2101

SC15P50V2JN-2-GP

3

2 3

82.30001.841

2nd = 82.30001.A41

RTC_X2

12

C2102

C2102 SC15P50V2JN-2-GP

SC15P50V2JN-2-GP

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

PCH ( SPI/RTC/LPC/SATA/HDA)

Size Document Number Rev

A3

Enrico Caruso 14 MLK DIS

Tuesday, January 03, 2012

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

21 104

1

X02

5

4

3

2

1

SSID = PCH

6 OF 10

PCH1F

3D3V_S0

RN2206

D D

X02 1223

C C

8 7 6

SRN10KJ-6-GP

RN2207

8 7 6

SRN10KJ-6-GP

RN2201

8 7 6

SRN10KJ-6-GP

DY

1 2

R2202 10KR2J-3-GP

R2205 10KR2J-3-GPR2205 10KR2J-3-GP

1 2

R2206 10KR2J-3-GPR2206 10KR2J-3-GP

1 2

1 2 3 45

PCH_GPIO34

1

3G_EN

2 3

SATA_ODD_PRSNT#

45

EC_SMI#

1

EC_SCI#

2

PCH_GPIO6

3

PCH_GPIO22

45

DGPU_HOLD_RST#

PCH_GPIO49 H_A20GATE PCH_GPIO0 H_RCIN#

DGPU_HOLD_RST# DGPU_PW R_EN#

X02 1223

3D3V_S5

RN2204

RN2204 SRN10KJ-5-GP

SRN10KJ-5-GP

1 2 3

DY

R2221 10KR2J-3-GP

DY

R2224 10KR2J-3-GP

B B

R2224 10KR2J-3-GP

DY

R2201 1KR2J-1-GP

RN2205

RN2205 SRN10KJ-5-GP

SRN10KJ-5-GP

1 2 3

DY

R2212 1KR2J-1-GP

12

12 12

12

4

RTC_DET# PCH_GPIO57

PCH_GPIO24

PCH_GPIO8 PCH_GPIO15

PCH_GPIO36 PCH_GPIO37

PLL_ODVR_EN

EC_SMI#27

EC_SCI#27

FOLLOW CKL

RTC_DET#60

SATA_ODD_PRSNT#56

DGPU_PW ROK27,92,93

FOLLOW CKL

TP2203TPAD14-OP-GP TP2203TPAD14-OP-GP

FOLLOW CKL

TP2213TPAD14-OP-GP TP2213TPAD14-OP-GP

DGPU_HOLD_RST#83 DGPU_PW R_EN#93

TP2206TPAD14-OP-GP TP2206TPAD14-OP-GP

TP2207TPAD14-OP-GP TP2207TPAD14-OP-GP TP2208TPAD14-OP-GP TP2208TPAD14-OP-GP

TP2209TPAD14-OP-GP TP2209TPAD14-OP-GP

PCH_GPIO0 EC_SMI# PCH_GPIO6 EC_SCI# PCH_GPIO8 RTC_DET# PCH_GPIO15

DGPU_PW ROK PCH_GPIO22 PCH_GPIO24 PCH_GPIO27

1

PLL_ODVR_EN

PCH_GPIO34

PCH_GPIO35

1

PCH_GPIO36 PCH_GPIO37 3G_EN

PCH_GPIO49 PCH_GPIO57

PCH_NCTF_1

1

PCH_NCTF_2

1

PCH_NCTF_3

1

PCH_NCTF_4

1

T7

BMBUSY#/GPIO0

A42

TACH1/GPIO1

H36

TACH2/GPIO6

E38

TACH3/GPIO7

C10

GPIO8

C4

LAN_PHY_PWR_CTRL/GPIO12

G2

GPIO15

U2

SATA4GP/GPIO16

D40

TACH0/GPIO17

T5

SCLOCK/GPIO22

E8

GPIO24

E16

GPIO27

P8

GPIO28

K1

STP_PCI#/GPIO34

K4

GPIO35

V8

SATA2GP/GPIO36

M5

SATA3GP/GPIO37

N2

SLOAD/GPIO38

M3

SDATAOUT0/GPIO39

V13

SDATAOUT1/GPIO48

V3

SATA5GP/GPIO49/TEMP_ALERT#

D6

GPIO57

A4

VSS_NCTF_1#A4

A44

VSS_NCTF_2#A44

A45

VSS_NCTF_3#A45

A46

VSS_NCTF_4#A46

A5

VSS_NCTF_5#A5

A6

VSS_NCTF_6#A6

B3

VSS_NCTF_7#B3

B47

VSS_NCTF_8#B47

BD1

VSS_NCTF_9#BD1

BD49

VSS_NCTF_10#BD49

BE1

VSS_NCTF_11#BE1

BE49

VSS_NCTF_12#BE49

BF1

VSS_NCTF_13#BF1

BF49

VSS_NCTF_14#BF49

PANTHER-GP-NF

71.PANTH.00U

GPIO

NCTF

NCTF TEST PIN:

A4,A44,A45,A46,A5,A6,B3,B47,

BD1,BD49,BE1,BE49,BF1,BF49,

BG2,BG48,BH3,BH47,BJ4,BJ44,

BJ45,BJ46,BJ5,BJ6,C2,C48,D1,

D49,E1,E49,F1,F49

NCTF TEST PIN:

A4,A44,A45,A46,A5,A6,B3,B47,

BD1,BD49,BE1,BE49,BF1,BF49,

BG2,BG48,BH3,BH47,BJ4,BJ44,

BJ45,BJ46,BJ5,BJ6,C2,C48,D1,

D49,E1,E49,F1,F49

6 OF 10

TACH4/GPIO68 TACH5/GPIO69 TACH6/GPIO70 TACH7/GPIO71

A20GATE

PECI

RCIN#

PROCPWRGD

THRMTRIP#

INIT3_3V#

DF_TVS

CPU/MISC

TS_VSS1 TS_VSS2 TS_VSS3 TS_VSS4

NC_1

VSS_NCTF_15#BG2

VSS_NCTF_16#BG48

VSS_NCTF_17#BH3

VSS_NCTF_18#BH47

VSS_NCTF_19#BJ4 VSS_NCTF_20#BJ44 VSS_NCTF_21#BJ45 VSS_NCTF_22#BJ46

VSS_NCTF_23#BJ5

VSS_NCTF_24#BJ6

VSS_NCTF_25#C2

VSS_NCTF_26#C48

VSS_NCTF_27#D1

VSS_NCTF_28#D49

VSS_NCTF_29#E1

VSS_NCTF_30#E49

VSS_NCTF_31#F1

VSS_NCTF_32#F49

C40 B41 C41 A40

P4 AU16 P5 AY11 AY10 T14 AY1

AH8 AK11 AH10 AK10

P37

BG2 BG48 BH3 BH47 BJ4 BJ44 BJ45 BJ46 BJ5 BJ6 C2 C48 D1 D49 E1 E49 F1 F49

SATA_ODD_PWRGT BOARD_ID2 PCH_GPIO70 PCH_GPIO71

H_A20GATE H_PECI_R H_RCIN# H_CPUPW RGD PCH_THERMTRIP_R INIT3_3V# DF_TVS

Layout Note:

These four balls must connect to GND shared 1 Via

TP2204 TPAD14-OP-GPTP2204 TPAD14-OP-GP

1

TP2205 TPAD14-OP-GPTP2205 TPAD14-OP-GP

1

R2203 0R2J-2-GP

R2204 390R2J-1-GPR2204 390R2J-1-GP TP2201 TPAD14-OP-GPTP2201 TPAD14-OP-GP

1

SATA_ODD_PWRGT 56 BOARD_ID2 20

H_A20GATE 27

1 2

DY

H_RCIN# 27 H_CPUPW RGD 5,36

1 2

H_PECI 5,27

H_THERMTRIP# 5,36

R2209

DF_TVS

1 2

1KR2J-1-GP

1D8V_S0

12

R2207

R2207 2K2R2J-2-GP

2K2R2J-2-GP

H_SNB_IVB# 5

PLL ON DIE VR ENABLE

A A

GPIO28 (PLL_ODVR_EN)

Weakly internal pull up 20k. High - Enable LOW - Disable

5

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Tuesday, January 03, 2012

Date: Sheet of

4

3

2

Date: Sheet of

PCH ( GPIO/CPU )

Enrico Caruso 14 MLK DIS

Taipei Hsien 221, Taiwan, R.O.C.

22 104

1

X02

5

4

3

2

1

SSID = PCH

Voltage Rail

V_PROC_IO

X02

3D3V_DAC_S0

R2304

1 2

0R0603-PAD

R2301

1 2

0R0805-PAD

R2307

0R0402-PAD

1 2

R2306

0R0402-PAD

1 2

R2308

0R0402-PAD

1 2

X02

3D3V_S0

1D8V_S0

3D3V_S0

1D5V_S0

1D05V_VTT

1D8V_S0

3D3V_S5

V5REF V5REF_Sus Vcc3_3 VccADAC VccADPLLA VccADPLLB VccCore VccDMI VccIO VccASW VccSPI VccDSW3_3 VccDFTERM VccRTC VccSus3_3 VccSusHDA VccVRM VccClkDMI VccSSC VccDIFFCLKN VccALVDS VccTX_LVDS

Refer to PCH EDS V1.5 (General DC Characteristicschipset)

7 OF 10

POWER

PCH1G

1D05V_VTT

D D

C C

1D05V_VTT

B B

3D3V_S0

12

1.73A

3.799A

C2305

SC10U6D3V5KX-1GP

0.228A

C2310

SCD1U10V2KX-5GP

Decap

12

C2303

12

C2308

TP2303TPAD14-OP-GP TP2303TPAD14-OP-GP

Decap

12

C2304

SC1U6D3V2KX-GP

1D05V_VTT

VCCAPLLEXP

12

C2309

SCD1U10V2KX-5GP

VCCVRM

VCCFDIPLL

1

1D05V_VTT

1D05VS_VCC_DMI

SCD1U10V2KX-5GP

SC1U6D3V2KX-GP

12

C2302

C2301

C2306

C2302

SC1U6D3V2KX-GP

SC10U6D3V5KX-1GP

SC1U6D3V2KX-GP

TP2301TPAD14-OP-GP TP2301TPAD14-OP-GP

1

12

C2307

SCD1U10V2KX-5GP

PCH1G

AA23

VCCCORE1

AC23

VCCCORE2

AD21

VCCCORE3

AD23

VCCCORE4

AF21

VCCCORE5

AF23

VCCCORE6

AG21

VCCCORE7

AG23

VCCCORE8

AG24

VCCCORE9

AG26

VCCCORE10

AG27

VCCCORE11

AG29

VCCCORE12

AJ23

VCCCORE13

AJ26

VCCCORE14

AJ27

VCCCORE15

AJ29

VCCCORE16

AJ31

VCCCORE17

AN19

VCCIO28

BJ22

VCCAPLLEXP

AN16

VCCIO15

AN17

VCCIO16

AN21

VCCIO17

AN26

VCCIO18

AN27

VCCIO19

AP21

VCCIO20

AP23

VCCIO21

AP24

VCCIO22

AP26

VCCIO23

AT24

VCCIO24

AN33

VCCIO25

AN34

VCCIO26

BH29

VCC3_3_3

AP16

VCCVRM2

BG6

VCCAFDIPLL

AP17

VCCIO27

AU20

VCCDMI2

PANTHER-GP-NF

71.PANTH.00U

POWER

VCC CORE

VCCIO

FDI

CRTLVDS

DMI

DFT / SPI HVCMOS

7 OF 10

VCCADAC

VSSADAC

VCCALVDS

VSSALVDS

VCCTX_LVDS1 VCCTX_LVDS2 VCCTX_LVDS3 VCCTX_LVDS4

VCC3_3_6

VCC3_3_7

VCCVRM3

VCCDMI1

VCCCLKDMI

VCCDFTERM1

VCCDFTERM2

VCCDFTERM3

VCCDFTERM4

VCCSPI

U48

U47

AK36 AK37

AM37 AM38 AP36 AP37

V33

V34

AT16

AT20

AB36

AG16

AG17

AJ16

AJ17

V1

12

C2313

+3VS_VCCA_LVDS

+1.8VS_VCCTX_LVDS

12

C2319

C2319 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

VCCVRM

1D05VS_VCC_DMI

12

C2320

C2320 SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

+1.05VS_VCC_DMI_CCI

12

C2321

C2321 SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

12

C2322

C2322 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

12

C2323

C2323 SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

0.063A

12

C2314

SCD01U16V2KX-3GP

12

C2315

SCD1U10V2KX-5GP

0.001A

SC10U6D3V5KX-1GP

0.04A

12

C2316

C2317

SCD01U16V2KX-3GP

C2318

SCD01U16V2KX-3GP

SC22U6D3V5MX-2GP

0.178A

0.147A

0.047A

0.075A

0.002A

0.01A

Voltage(V)

1.05 5 5

3.3

1.05

1.1

1.05

3.3

1.8

3.3

1.5

1.05

3.3

1.8

Iccmax(A)

0.002

0.001

0.178

0.063

0.075

1.73

0.047

3.799

0.803

0.01

0.001

0.002 6uA

0.065

0.01

0.147

0.075

0.095

0.05

0.001

0.04

X00

5V_S0 3D3V_DAC_S0

3D3V_S0

A A

5

4

C2311

3

12

SC1U10V2KX-1GP

U2301

OUT

NC#4

5 4

1

IN

2

GND

3

EN

TLV70233DBVR-GP

74.70233.03F

2nd = 74.08818.B3F

X02 1230 removed 3rd source 74.09091.J3F for it is going to EOL

12

C2312

SC1U6D3V2KX-GP

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Friday, December 30, 2011

Date: Sheet of

PCH ( POWER1)

Enrico Caruso 14 MLK DIS

Taipei Hsien 221, Taiwan, R.O.C.

23 104

1

X02

5

4

3

2

1

SSID = PCH

VCCACLK

1

DCPSUSBYP

1

+V3.3S_VCC_CLKF33

+VCCAPLL_CPY_PCH

1

+VCCSUS1

1

C2405

SC1U6D3V2KX-GP

C2405

SC1U6D3V2KX-GP

12

+VCCRTCEXT

VCCVRM

+1.05VS_VCCA_A_DPL +1.05VS_VCCA_B_DPL

+VCCDIFFCLK

+V1.05S_SSCVCC

+VCCSST

DCPSUS

1

12

C2418

SCD1U10V2KX-5GP

12

C2421

SCD1U10V2KX-5GP

C2419

12

0.167A

C2420

12

SC1U6D3V2KX-GP

SCD1U10V2KX-5GP

C2422

SCD1U10V2KX-5GP

12

1D05V_VTT

12

C2417

C2436

TP2401TPAD14-OP-GP TP2401TPAD14-OP-GP

TP2405

TPAD14-OP-GP

TP2404TPAD14-OP-GP TP2404TPAD14-OP-GP

TP2402TPAD14-OP-GP TP2402TPAD14-OP-GP

C2406

SC1U6D3V2KX-GP

C2406

SC1U6D3V2KX-GP

TP2406

TPAD14-OP-GP

12

4

3D3V_S5

0.001A

3D3V_S0

D D

C C

1D05V_VTT

B B

1D05V_VTT

A A

X02

1D05V_VTT

X02

L2401

1 2

IND-10UH-218-GP

68.10050.10Y

2nd = 68.1001F.10N

3rd = 68.1001E.10N

4th = 68.10090.10B

L2402

1 2

IND-10UH-218-GP

68.10050.10Y

2nd = 68.1001F.10N

3rd = 68.1001E.10N

4th = 68.10090.10B

L2403

1 2

IND-10UH-218-GP

68.10050.10Y

2nd = 68.1001F.10N

3rd = 68.1001E.10N

4th = 68.10090.10B

R2403

1 2

0R0402-PAD

R2404

1 2

0R0402-PAD

5

+V3.3S_VCC_CLKF33

12

C2401

SC10U6D3V5KX-1GP

0.075A

+1.05VS_VCCA_A_DPL

12

DY

C2408

0.075A

SC10U6D3V5KX-1GP

+1.05VS_VCCA_B_DPL

12

DY

C2409

SC10U6D3V5KX-1GP

+VCCDIFFCLK

12

C2412

SC1U6D3V2KX-GP

0.095A

+V1.05S_SSCVCC

12

C2413

SC1U6D3V2KX-GP

12

C2402

C2402 SC1U10V2KX-1GP

SC1U10V2KX-1GP

1D05V_VTT

12

C2407

C2407 SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

12

C2410

C2410 SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

1D05V_VTT

SCD1U10V2KX-5GP

0.803A

Decap

12

0.05A

1 2

R2412 0R0603-PADR2412 0R0603-PAD

1D05V_VTT

RTC_AUX_S5

Decap

C2403

SC10U6D3V5KX-1GP

C2403

SC10U6D3V5KX-1GP

12

SCD1U10V2KX-5GP

X02

SC1U6D3V2KX-GP

SCD1U10V2KX-5GP

SC4D7U6D3V3KX-GP

SC1U6D3V2KX-GP

C2416

C2404

SC10U6D3V5KX-1GP

C2404

SC10U6D3V5KX-1GP

C2411

+VCCDIFFCLKN

C2414

C2415

0.002A

6uA

PCH1J

AD49

VCCACLK

T16

VCCDSW3_3

V12

DCPSUSBYP

T38

VCC3_3_5

BH23

VCCAPLLDMI2

AL29

VCCIO14

AL24

DCPSUS3

AA19

VCCASW1

AA21

VCCASW2

AA24

VCCASW3

AA26

VCCASW4

AA27

VCCASW5

AA29

VCCASW6

AA31

VCCASW7

AC26

VCCASW8

AC27

VCCASW9

AC29

VCCASW10

AC31

VCCASW11

AD29

VCCASW12

AD31

VCCASW13

W21

VCCASW14

W23

VCCASW15

W24

VCCASW16

W26

VCCASW17

W29

VCCASW18

W31

VCCASW19

W33

VCCASW20

N16

DCPRTC

Y49

VCCVRM4

BD47

VCCADPLLA

BF47

VCCADPLLB

AF17

VCCIO7

AF33

VCCDIFFCLKN1

AF34

VCCDIFFCLKN2

AG34

VCCDIFFCLKN3

AG33

VCCSSC

V16

DCPSST

T17

DCPSUS1

V19

DCPSUS2

BJ8

V_PROC_IO

A22

VCCRTC

PANTHER-GP-NF

71.PANTH.00U

POWER

Clock and Miscellaneous

CPURTC

3

PCI/GPIO/LPCMISC

SATA USB

HDA

10 OF 10

N26

VCCIO29

P26

VCCIO30

P28

VCCIO31

T27

VCCIO32

T29

VCCIO33

VCCSUS3_3_7 VCCSUS3_3_8 VCCSUS3_3_9

VCCSUS3_3_10

VCCSUS3_3_6

V5REF_SUS

VCCSUS3_3_1

VCCSUS3_3_2 VCCSUS3_3_3 VCCSUS3_3_4 VCCSUS3_3_5

VCCAPLLSATA

VCCSUSHDA

T23 T24 V23 V24 P24

T26

VCCIO34

M26

AN23

DCPSUS4

AN24

P34

V5REF

N20 N22 P20 P22

AA16

VCC3_3_1

W16

VCC3_3_8

T34

VCC3_3_4

AJ2

VCC3_3_2

AF13

VCCIO5

AH13

VCCIO12

AH14

VCCIO13

AF14

VCCIO6

AK1

AF11

VCCVRM1

AC16

VCCIO2

AC17

VCCIO3

AD17

VCCIO4

1D05V_VTT

T21

VCCASW22

V21

VCCASW23

T19

VCCASW21

P32

C2433

SCD1U10V2KX-5GP

VCCSUSHDA need to be at either 3.3V or 1.5V. All the CODEC I/O Voltages need to be at the same level either 3.3 V or 1.5 V.

C2433

12

C2438

C2438 SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

12

C2424

C2424 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

1D05V_VTT

+5VA_PCH_VCC5REFSUS

+VCCA_USBSUS

3D3V_S5

+5VS_PCH_VCC5REF

C2428

SC1U6D3V2KX-GP

3D3V_S0

12

C2431

C2431 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

C2429

SCD1U10V2KX-5GP

C2429

X00

C2432

SC1U6D3V2KX-GP

+V1.05S_VCCAPLL_SATA3

VCCVRM

C2435

SC1U6D3V2KX-GP

+3VS_+1.5VS_HDA_IO

0.01A

12

0R0402-PAD

R2402

12

DY

12

1

12

2

C2425

C2425 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

C2437

C2437 SC1U10V2KX-1GP

SC1U10V2KX-1GP

1 2

1D05V_VTT

3D3V_S5

0.065A

3D3V_S5

(0.1uFx1)

0.001A

3D3V_S5

3D3V_S0

12

C2430

C2430 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

3D3V_S0

1D05V_VTT

TP2403 TPAD14-OP-GPTP2403 TPAD14-OP-GP

1D05V_VTT

3D3V_S5

X02

3D3V_S5

21

D2401

D2401 CH751H-40PT-GP

12

3D3V_S0

21

12

CH751H-40PT-GP

D2402

D2402 CH751H-40PT-GP

CH751H-40PT-GP

R2408

1 2

10R2J-2-GP

C2426

C2426 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

1 2

10R2J-2-GP

C2427

C2427 SC1U10V2KX-1GP

SC1U10V2KX-1GP

83.R0304.A8F

2nd = 83.R3004.A8F

3rd = 83.R2004.B8F

83.R0304.A8F

2nd = 83.R3004.A8F

3rd = 83.R2004.B8F

Voltage Rail

V_PROC_IO V5REF V5REF_Sus Vcc3_3 VccADAC VccADPLLA VccADPLLB VccCore VccDMI VccIO VccASW VccSPI VccDSW3_3 VccDFTERM VccRTC VccSus3_3 VccSusHDA VccVRM VccClkDMI VccSSC VccDIFFCLKN VccALVDS VccTX_LVDS

Refer to PCH EDS V1.5

Title

Size Document Number Rev

A3

Friday, December 30, 2011

Date: Sheet of

(General DC Characteristicschipset)

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

PCH ( POWER2 )

Enrico Caruso 14 MLK DIS

R2407

Voltage(V)

1.05 5 5

3.3

1.05

1.1

1.05

3.3

1.8

3.3

1.5

1.05

3.3

1.8

1

5V_S5

5V_S0

Iccmax(A)

0.002

0.001

0.178

0.063

0.075

1.73

0.047

3.799

0.803

0.01

0.001

0.002 6uA

0.065

0.01

0.147

0.075

0.095

0.05

0.001

0.04

24 104

X02

5

4

3

2

1

SSID = PCH

D D

C C

B B

A A

5

PCH1H

H5

VSS0

AA17

VSS1

AA2

VSS2

AA3

VSS3

AA33

VSS4

AA34

VSS5

AB11

VSS6

AB14

VSS7

AB39

VSS8

AB4

VSS9

AB43

VSS10

AB5

VSS11

AB7

VSS12

AC19

VSS13

AC2

VSS14

AC21

VSS15

AC24

VSS16

AC33

VSS17

AC34

VSS18

AC48

VSS19

AD10

VSS20

AD11

VSS21

AD12

VSS22

AD13

VSS23

AD19

VSS24

AD24

VSS25

AD26

VSS26

AD27

VSS27

AD33

VSS28

AD34

VSS29

AD36

VSS30

AD37

VSS31

AD38

VSS32

AD39

VSS33

AD4

VSS34

AD40

VSS35

AD42

VSS36

AD43

VSS37

AD45

VSS38

AD46

VSS39

AD8

VSS40

AE2

VSS41

AE3

VSS42

AF10

VSS43

AF12

VSS44

AD14

VSS45

AD16

VSS46

AF16

VSS47

AF19

VSS48

AF24

VSS49

AF26

VSS50

AF27

VSS51

AF29

VSS52

AF31

VSS53

AF38

VSS54

AF4

VSS55

AF42

VSS56

AF46

VSS57

AF5

VSS58

AF7

VSS59

AF8

VSS60

AG19

VSS61

AG2

VSS62

AG31

VSS63

AG48

VSS64

AH11

VSS65

AH3

VSS66

AH36

VSS67

AH39

VSS68

AH40

VSS69

AH42

VSS70

AH46

VSS71

AH7

VSS72

AJ19

VSS73

AJ21

VSS74

AJ24

VSS75

AJ33

VSS76

AJ34

VSS77

AK12

VSS78

AK3

VSS79

PANTHER-GP-NF

71.PANTH.00U

8 OF 10

VSS80 VSS81 VSS82 VSS83 VSS84 VSS85 VSS86 VSS87 VSS88 VSS89 VSS90 VSS91 VSS92 VSS93 VSS94 VSS95 VSS96 VSS97 VSS98

VSS99 VSS100 VSS101 VSS102 VSS103 VSS104 VSS105 VSS106 VSS107 VSS108 VSS109 VSS110 VSS111 VSS112 VSS113 VSS114 VSS115 VSS116 VSS117 VSS118 VSS119 VSS120 VSS121 VSS122 VSS123 VSS124 VSS125 VSS126 VSS127 VSS128 VSS129 VSS130 VSS131 VSS132 VSS133 VSS134 VSS135 VSS136 VSS137 VSS138 VSS139 VSS140 VSS141 VSS142 VSS143 VSS144 VSS145 VSS146 VSS147 VSS148 VSS149 VSS150 VSS151 VSS152 VSS153 VSS154 VSS155 VSS156 VSS157 VSS158

AK38 AK4 AK42 AK46 AK8 AL16 AL17 AL19 AL2 AL21 AL23 AL26 AL27 AL31 AL33 AL34 AL48 AM11 AM14 AM36 AM39 AM43 AM45 AM46 AM7 AN2 AN29 AN3 AN31 AP12 AP19 AP28 AP30 AP32 AP38 AP4 AP42 AP46 AP8 AR2 AR48 AT11 AT13 AT18 AT22 AT26 AT28 AT30 AT32 AT34 AT39 AT42 AT46 AT7 AU24 AU30 AV16 AV20 AV24 AV30 AV38 AV4 AV43 AV8 AW14 AW18 AW2 AW22 AW26 AW28 AW32 AW34 AW36 AW40 AW48 AV11 AY12 AY22 AY28

4

PCH1I

AY4

VSS159

AY42

VSS160

AY46

VSS161

AY8

VSS162

B11

VSS163

B15

VSS164

B19

VSS165

B23

VSS166

B27

VSS167

B31

VSS168

B35

VSS169

B39

VSS170

B7

VSS171

F45

VSS172

BB12

VSS173

BB16

VSS174

BB20

VSS175

BB22

VSS176

BB24

VSS177

BB28

VSS178

BB30

VSS179

BB38

VSS180

BB4

VSS181

BB46

VSS182

BC14

VSS183

BC18

VSS184

BC2

VSS185

BC22

VSS186

BC26

VSS187

BC32

VSS188

BC34

VSS189

BC36

VSS190

BC40

VSS191

BC42

VSS192

BC48

VSS193

BD46

VSS194

BD5

VSS195

BE22

VSS196

BE26

VSS197

BE40

VSS198

BF10

VSS199

BF12

VSS200

BF16

VSS201

BF20

VSS202

BF22

VSS203

BF24

VSS204

BF26

VSS205

BF28

VSS206

BD3

VSS207

BF30

VSS208

BF38

VSS209

BF40

VSS210

BF8

VSS211

BG17

VSS212

BG21

VSS213

BG33

VSS214

BG44

VSS215

BG8

VSS216

BH11

VSS217

BH15

VSS218

BH17

VSS219

BH19

VSS220

H10

VSS221

BH27

VSS222

BH31

VSS223

BH33

VSS224

BH35

VSS225

BH39

VSS226

BH43

VSS227

BH7

VSS228

D3

VSS229

D12

VSS230

D16

VSS231

D18

VSS232

D22

VSS233

D24

VSS234

D26

VSS235

D30

VSS236

D32

VSS237

D34

VSS238

D38

VSS239

D42

VSS240

D8

VSS241

E18

VSS242

E26

VSS243

G18

VSS244

G20

VSS245

G26

VSS246

G28

VSS247

G36

VSS248

G48

VSS249

H12

VSS250

H18

VSS251

H22

VSS252

H24

VSS253

H26

VSS254

H30

VSS255

H32

VSS256

H34

VSS257

F3

VSS258

PANTHER-GP-NF

71.PANTH.00U

3

9 OF 10

VSS259 VSS260 VSS261 VSS262 VSS263 VSS264 VSS265 VSS266 VSS267 VSS268 VSS269 VSS270 VSS271 VSS272 VSS273 VSS274 VSS275 VSS276 VSS277 VSS278 VSS279 VSS280 VSS281 VSS282 VSS283 VSS284 VSS285 VSS286 VSS287 VSS288 VSS289 VSS290 VSS291 VSS292 VSS293 VSS294 VSS295 VSS296 VSS297 VSS298 VSS299 VSS300 VSS301 VSS302 VSS303 VSS304 VSS305 VSS306 VSS307 VSS308 VSS309 VSS310 VSS311 VSS312 VSS313 VSS314 VSS315 VSS316 VSS317 VSS318 VSS319 VSS320 VSS321 VSS322 VSS323 VSS324 VSS325 VSS328 VSS329 VSS330 VSS331 VSS333 VSS334 VSS335 VSS337 VSS338 VSS340 VSS342 VSS343 VSS344 VSS345 VSS346 VSS347 VSS348 VSS349 VSS350 VSS351 VSS352

H46 K18 K26 K39 K46 K7 L18 L2 L20 L26 L28 L36 L48 M12 P16 M18 M22 M24 M30 M32 M34 M38 M4 M42 M46 M8 N18 P30 N47 P11 P18 T33 P40 P43 P47 P7 R2 R48 T12 T31 T37 T4 W34 T46 T47 T8 V11 V17 V26 V27 V29 V31 V36 V39 V43 V7 W17 W19 W2 W27 W48 Y12 Y38 Y4 Y42 Y46 Y8 BG29 N24 AJ3 AD47 B43 BE10 BG41 G14 H16 T36 BG22 BG24 C22 AP13 M14 AP3 AP1 BE16 BC16 BG28 BJ28

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Friday, December 30, 2011

Date: Sheet of

2

Date: Sheet of

PCH ( VSS )

Enrico Caruso 14 MLK DIS

Taipei Hsien 221, Taiwan, R.O.C.

25 104

1

X02

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Friday, December 30, 2011

Date: Sheet of

Reserved

Enrico Caruso 14 MLK DIS

Taipei Hsien 221, Taiwan, R.O.C.

26 104

1

X02

C2705

SCD1U10V2KX-5GP

EC_AGND

CARD_W PAN_OUT#65

5

0127 A00 Modify: un-stuff C2707,C2709 on ST2 batch run stage.

12

C2706

DY

SCD1U10V2KX-5GP

X00

BATT_WH ITE_LED#68

RSMRST#_KBC19

X00

BLUETOOTH _EN65 S0_PWR_GO OD19,36

SPI_CS0#_R21,60

SPI_CLK_R21,60

EC_SPI_DI_C60

SPI_SI_R21,60

R2767

R2767 0R0402-PAD

0R0402-PAD

1 2

R2768

R2768 0R0402-PAD

0R0402-PAD

1 2

DS

Q2706

Q2706 2N7002BK-GP

2N7002BK-GP

G

12

C2708

C2707

DY

C2709

SC2D2U10V3KX-1GP

SCD1U10V2KX-5GP

EC_AGND

C2714 SCD1U10V2KX-5G PC2714 SCD1U10V2KX-5G P

1 2

AD_IA40

PSID_EC38

VGA_THRM28

1

TP2711TPAD14-OP -GP TP271 1TPAD14-OP-GP

FAN1_DAC28

AD_IA_HW40

IMVP_PWRGD36,42

CAP_LED#69

S5_ENABLE36

BAT_IN#39

LID_CLOSE#82

PM_SLP_S4#19,46 DGPU_PW ROK22,92,93

WIFI_RF_EN65

33R2J-2-GP R273633R2J-2-GP R2736

1 2

33R2J-2-GP R271933R2J-2-GP R2719

1 2

R272233R2J- 2-GP R272233R2J- 2-GP

1 2

PM_PWRBT N#19

AC_PRESENT19

USB_PWR _EN#61

3D3V_AUX_S5

R2704

R2704 330KR2J-L1-GP

330KR2J-L1-GP

1 2

PSL_IN2#

X02

PSL_IN1#

X02

R2709

S5_ENABLE

10KR2J-3-GP

RSMRST#_KBC

S0_PWR_GO OD

R2709

1 2

4

RN2706

SRN100KJ-6-G P

SCD1U10V2KX-5GP

C2710

PCB_VER_AD

CPU_THR M SYS_THRM

VGA_THRM USBCHARG ER_CB0

MODEL_ID_DET

SERIES_ID

BATLOW#_E C

ECSMI#_KBC

ECSWI#_KBC

BLUETOOTH _EN

EC_SPI_CS#_C EC_SPI_CLK_C

EC_SPI_DI_C

EC_SPI_DO_C

3D3V_AUX_S5

PSL_OUT#

3D3V_AUX_KBC

1

DY

23

PROCHOT _EC

R2734

R2734 330KR2J-L1-GP

330KR2J-L1-GP

1 2

R2735

104

100 108

101 105 106 107

109

123

117 112 110

20100712 V1.5

3D3V_AUX_KBC _VCC

97 98 99

96 95 94

79

6

14 15 80 17 20 21 26

82 83 84

90 92 86 87 91

100KR2J-1-GP

X02 1230

VBAT

115

U2701A

VCC119VCC246VCC376VCC488VCC5

VREF GPIO90/AD0

GPIO91/AD1 GPIO92/AD2 GPIO93/AD3 GPIO5/AD4 GPIO4/AD5 GPIO3/AD6 GPIO7/AD7

GPIO94/DA0 GPIO95/DA1 GPIO96/DA2 GPIO97/DA3

GPIO02 GPIO24 GPIO30/F_WP# GPIO34/CIRRXL GPIO36 GPIO41/F_WP# GPIO42/TCK GPIO43/TMS GPIO44/TDI GPIO51/N2TCK GPIO67N2TMS GPIO75 GPIO76 GPIO77

F_CS0# F_SCK F_SDI&F_SDIO1 F_SDIO&F_SDIO0 GPIO81/F_WP#

GPIO20/TA2/IOX_DIN_DIO GP/I/O84/IOX_SCLK/XORTR# GPO82/IOX_LDSH/TEST#

R2732

KBC_ON#_GAT E

20KR2J-L2-GP

GND118GND245GND378GND489GND5

2N7002BK-GP

NPCE885PA0DX -GP

12

Q2702

SSID = KBC

3D3V_AUX_KBC

R2771

R2771 2D2R3-1-U- GP

2D2R3-1-U- GP

1 2 12

C2701

D D

Need very close to EC

R2702

1 2

0R3J-0-U-G P

12

C2704

DY

SCD1U10V2KX-5GP

SC2D2U10V3KX-1GP

Layout Note:

C C

3D3V_AUX_KBC

12

R2737

R2737 100KR2J-1-GP

100KR2J-1-GP

Ins

SERIES_ID

Vostro

12

R2738

R2738 100KR2J-1-GP

100KR2J-1-GP

B B

Power Switch Logic(PSL)

KBC_PWR BTN#68

AC_IN#40

A A

KBC_ON#_GAT E

84.07002.I31

2nd = 84.2N702.W31

3rd = 84.2N702.J31

SPI Shared Flash ROM

5

4

SCD1U10V2KX- 5GP

102

4

75

114

VDD

VSBY

AVCC

GPIO52/PSDAT3/RDY#

GPIO50/PSCLK3/TDO

GPIO17/SCL1/N2TCK

GPIO22/SDA1/N2TMS

PSL_OUT_GPIO71#

GND6

5

116

R2765

0R0402-PAD

1 2

X02

EC_AGND

G

DS

84.07002.I31

2nd = 84.2N702.W31

3rd = 84.2N702.J31

3D3V_AUX_S5

C2722

1 2

SCD1U10V2KX- 5GP

S

G

D

84.02130.031

D

84.02130.031

2nd = 84.00102.031

3rd = 84.03413.A31

D

4th = 84.02301.G31

4

3D3V_S0

12

C2702

3D3V_AUX_S5

EC_VBKUP

0R0402-PAD

VBKUP

LRESET#/GPIOF7

LCLK/GPIOF5

LFRAME#/GPIOF6

LAD3/GPIOF4 LAD2/GPIOF3 LAD1/GPIOF2 LAD0/GPIOF1

SERIRQ/GPIOF0

GPIO11/CLKRUN#

GPIO65/SMI# ECSCI#/GPIO54 GPIO10/LPCPD#

GPIO85/GA20 KBRST#/GPIO86

GPIO27/PSDAT2 GPIO26/PSCLK2 GPIO35/PSDAT1 GPIO37/PSCLK1

GPIO73/SCL2

GPIO74/SDA2

GPIO23/SCL3

GPIO31/SDA3

GPIO47/SCL4

GPIO53/SDA4

PSL_IN2_GPI06# PSL_IN1_GPI70#

VCORF

AGND

103

EC_AGND

H_PROCHO T#_EC

Q2703

Q2703 DMP2130L-7-GP

DMP2130L-7-GP

3D3V_AUX_KBC

R2778

X02

CLK_PCI_KBC 18

BOOST_MODE# 40

BLON_OUT 49 PWR_CH G_AD_OFF 38

CARD_W LAN_OUT# 65

BAT_SCL 39,40 SML1_CLK 20

X02

12

H_PROCHO T# 5,40

X02 1228

LPC_FRAME# 2 1,71

INT_SERIRQ 21 PM_CLKRUN #_EC 1 9

H_A20GATE 22 H_RCIN# 22

AD_IA_HW2 40

TPDATA 69 TPCLK 69

BAT_SDA 39,40 SML1_DATA 20

RTCRST_O N 21

PM_LAN_ENABLE 31 LCD_TST_EN 49 LCD_TST 49

C2712

C2712 SC1U10V3KX-4G P-U

SC1U10V3KX-4G P-U

12

C2703

DY

SC2D2U10V3KX- 1GP

X02

1 2

RTC_AUX_S5

R2794

1 0F 2

C2711

DY

1 2

SC220P50V2KX-3GP

0R0402-PAD

PLT_RST#_EC

7

1 2 2 3

LPC_AD3

1

LPC_AD2

128

LPC_AD1

127

LPC_AD0

126 125 8

PANEL_BLEN

9

ECSCI#_KBC

29 124 121 122

27

AD_IA_HW2

25 11 10 71 72

70 69 67 68

PROCHOT _EC

119 120 24 28

R2792

1 2

0R0402-PAD

PSL_OUT#

74

PSL_IN2#

93

PSL_IN1#

73

KBC_VCORF

44

Layout Note:

Need very close to EC

Layout Note:

Connect GND and AGND planes via either 0R resistor or connect directly.

R2733

R2733 0R0402-PAD

0R0402-PAD

X02

1 2

X00

12

C2720

C2720 SC47P50V2JN-3G P

SC47P50V2JN-3G P

C502 : check list 1.5

R2791

DY

0R2J-2-GP

1 2

3

VBAT VBAT

12

PCB_VER_AD

C2717

DY

1 2

EC_AGND

SCD1U10V2KX-5GP

PLT_RST# 5,18,31,65,71,83

12

R2726

R2726 100KR2F-L1-GP

100KR2F-L1-GP

X00

<------ TP <------ BATTERY / CHARGER

<------PCH / eDP

KBC CLK EMI

PCB VER AD(GPIO91) PULL-LOW RESISTOR PULL-HIGH RESISTOR VOLTAGE

X01

R2724

R2724 33KR2F-GP

33KR2F-GP

LPC_AD[3..0] 21,71

PURE_HW _SHUTDO WN#28,36,86

CLK_PCI_KBC

X02

A00 Reserved Reserved

Reserved Reserved 100.0K Reserved 100.0K 215.0K 1.048V

3D3V_AUX_S5

12

R2740

22R2J-2-GP

DY

CLK_PCI_KBC_EMI

12

C2723

DY

SC4D7P50V2CN -1GP

12

R2705

R2705 10KR2J-3-GP

10KR2J-3-GP

100.0KX00

100.0K

X02 1230

1D05V_VTT

B

Q2701

MMBT3906-4-GP

2nd = 84.03906.F11

OVER_CUR RENT_P8#86

Layout Note:

Need very close to EC

ECRST#

12

C2715

E

DY

C

84.T3906.A11

E51_TxD65

TP2714TPA D14-OP-GP TP271 4TPAD14- OP-GP TP2715TPA D14-OP-GP TP271 5TPAD14- OP-GP

TP2716TPA D14-OP-GP TP271 6TPAD14- OP-GP

X00

R2721

43R2J-GP

1 2 1 2

R2720

X02

0R0402-PAD

EC_SWI#2 0

EC_SCI#22

EC_SMI#22

CPU_THR M

SYS_THRM

VGA_THRM

BLUETOOTH _EN

3.0V

2.75V

2.48V

2.24V

2.0V

1.87V

1.65VReserved

1.358V

1.204V

10.0K

20.0K

33.0K

47.0K

64.9K

76.8

100.0K

143.0K

174.0K

FAN_TACH 128 PCIE_WAKE#31 PM_SLP_S3#19,36,37,47

CHG_AMBER_L ED#68

KBC_BEEP29

WLAN_LED #68

PWRLED #68

ME_UNLOCK21

E51_RxD65

PCH_SUSCL K_KBC19

AMP_MUTE#29

H_PECI5,22

SC1U6D3V2KX-GP

3

2

MODEL_ID_DET

C2718

U2701B

31

GPIO56/TA1

63

GPIO14/TB1

64

GPIO1/TB2

32

GPIO15/A_PWM

118

GPIO21/B_PWM

62

KBC_GPIO32

1

KBC_GPIO66

1

KBC_GPIO33

1

ECRST#

GPIO13/C_PWM

65

GPIO32/D_PWM

22

GPIO45/E_PWM

81

GPIO66/G_PWM

66

GPIO33/H_PWM

16

GPIO40/F_PWM

23

GPIO46/CIRRXM/TRIST#

113

GPIO87/CIRRXM/SIN_CR

111

GP/I/O83/SOUT_CR/TRIST#

77

GPIO0/EXTCLK

30

GPIO55/CLKOUT/IOX_DIN_DIO

85

VCC_POR#

PECI

13

PECI

EC_VTT

12

VTT

12

NPCE885PA0DX -GP

C2716

SCD1U16V2KX-3GP

D2702

1

DY

2

BAS16-6-GP

D2703

1

DY

2

BAS16-6-GP

D2704

1

DY

2

BAS16-6-GP

C2719 SCD1U10V2KX-5GP

12

DY

C2721 SCD1U10V2KX-5GP

12

DY

R2708 10KR2J-3-GP

1 2

DY

X00

R2714 10KR2J-3-GP

1 2

DY

2

12

X00

R2710

R2710 20KR2F-L-GP

20KR2F-L-GP

12

R2739

R2739 100KR2F-L1-GP

100KR2F-L1-GP

DY

1 2

EC_AGND

SCD1U10V2KX-5GP

ECSWI#_KBC

3

83.00016.K11

2nd = 83.00016.F11

ECSCI#_KBC

3

83.00016.K11

2nd = 83.00016.F11

ECSMI#_KBC

3

83.00016.K11

2nd = 83.00016.F11

EC_AGND

MODEL_ID_DET(GPIO07)

DV14_UMA

DV14_DIS

DV15_UMA with HDMI DV15_UMA without HDMI

TBD TBD TBD TBD TBD TBD

2 0F 2

KBSOUT0/GPOB0/JENK#

KBSOUT9/GPOC1/SDP_VIS# KBSOUT10&P80_CLK/GPIOC2 KBSOUT11&P80_DAT/GPIOC3

KBSOUT15/GPIO61/XOR_OUT

2 0F 2

KBSOUT1/GPIOB1/TCK KBSOUT2/GPIOB2/TMS

KBSOUT3/GPIOB3/TDI

KBSOUT4/GPOB4/JEN0#

KBSOUT5/GPIOB5/TDO

KBSOUT6/GPIOB6/RDY#

KBSOUT7/GPIOB7 KBSOUT8/GPIOC0

KBSOUT12/GPIO64 KBSOUT13/GPIO63 KBSOUT14/GPIO62

GPIO60/KBSOUT16 GPIO57/KBSOUT17

KBSIN0/GPIOA0/N2TCK KBSIN1/GPIOA1/N2TMS

KBSIN2/GPIOA2 KBSIN3/GPIOA3 KBSIN4/GPIOA4 KBSIN5/GPIOA5 KBSIN6/GPIOA6 KBSIN7/GPIOA7

L_BKLT_EN17

EC GPIO standard PH/PL

BAT_SCL BAT_SDA

BAT_IN#

PCIE_WAKE#

ECRST#

BOOST_MODE#

OVER_CUR RENT_P8#

FAN_TACH 1

E51_RxD

LID_CLOSE#

1

PULL-LOW RESISTOR PULL-HIGH RESISTOR VOLTAGE

100.0K 3.0V

100.0K

KCOL0

53

KCOL1

52

KCOL2

51

KCOL3

50

KCOL4

49

KCOL5

48

KCOL6

47

KCOL7

43

KCOL8

42

KCOL9

41

KCOL10

40

KCOL11

39

KCOL12

38

KCOL13

37

KCOL14

36

KCOL15

35

KCOL16

34

KBC_GPIO57

33

KROW0

54

KROW1

55

KROW2

56

KROW3

57

KROW4

58

KROW5

59

KROW6

60

KROW7

61

X00

EC_SWI#20

EC_SCI#22

EC_SMI#22

BATLOW#19

1 2

0R2J-2-GP

1 2

R2706 100KR2J-1-GPR2706 100KR2J-1-GP

R2776 100KR2J-1-GPR2776 100KR2J-1-GP R2707 10KR2J-3-GPR2707 10KR2J-3-GP

X00

R2711 10KR2J-3-GP

X02 1230

R2713 100KR2J-1-GP

R2712 10KR2J-3-GPR2712 10KR2J-3-GP

X00

R2715 10KR2J-3-GP

R2774 100KR2J-1-GPR2774 100KR2J-1-GP

Title

Size Document Num ber Rev

Size Document Num ber Rev A2

A2

Enrico Caruso 14 MLK DIS

Tuesday, January 03, 2012

Date: Sheet of

10.0K(64.10025.6DL)

20.0K(64.20025.6DL)

33.0K(64.33025.6DL)

47.0K(64.47025.6DL)

64.9K(64.64925.6DL)

76.8K(64.76825.6DL)

100.0K(64.10035.6DL)

143.0K(64.14335.6DL)

174.0K(64.17435.6DL)

215.0K(64.21535.6DL)

KCOL[16..0] 69

1

TP2717 TPAD14-OP-GPTP271 7 TPAD14-OP-GP

KROW[7..0] 69

R2766

X02

0R0402-PAD

ECSWI#_KBC

R2764

X02

0R0402-PAD

ECSCI#_KBC

R2723

X02

0R0402-PAD

ECSMI#_KBC

R2793

BATLOW#_E C

DY

R2761

X02

0R0402-PAD

PANEL_BLEN

RN2701

4

SRN4K7J-8-G P

1 2

3D3V_AUX_KBC

23 1

DY

DY DY

DY

3D3V_S0

DY

3D3V_S5

Wistron Corporation

21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih,

21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih, Taipei Hsie n 221, Taiwan, R.O. C.

Taipei Hsie n 221, Taiwan, R.O. C.

KBC Nuvoton NPCE795

27 104

1

2.75V

2.48V

2.24V

2.0V

1.87V

1.65V

1.358V

1.204V

1.048V

X02

5

4

3

2

1

SSID = Thermal

C2803

5V_S0

12

C2804

C2804 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

Fan controller G991

U2802

R2802

Thermal sensor NCT7718W

SC10U6D3V5KX-1GP

D D

3D3V_S0

SC10U6D3V5KX-1GP

C2805

12

C2802

C2802 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

FAN1_DAC27

For linear FAN

R2802

1 2

DY

0R2J-2-GP

5V_S0

FAN_VCC

*Layout* 10 mil

U2802

FON#

1

FON#

2

VIN

3

VOUT VSET4GND

NCT3940S-A-GP

74.03940.A71

2nd = 74.02793.A31

3rd = 74.00991.031

GND GND GND

8 7 6 5

SC4D7U6D3V3KX-GP

Layout notice : Both DXN and DXP routing 10 mil trace width and 10 mil spacing. and route has to be away from the high noise area. Put the C2807 2200pF to close the NCT7718W

12

2ND = 84.03904.P11

3

84.03904.L06

R2808

DY

NTC-100K-8-GP

C C

DY

84.03904.L06

1

Q2801

PMBS3904-1-GP

2

2.System Sensor, Put on palm rest

THERM_SYS_SHDN#

NCT7718_DXP

12

C2806

DY

SC470P50V2KX-3GP

NCT7718_DXN

1 2

R2813 0R0402-PADR2813 0R0402-PAD

X02

12

C2807

C2807 SC2200P50V2KX-2GP

SC2200P50V2KX-2GP

T_CRIT#

U2801

1

VDD

2

D+

3

DT_CRIT#4GND

NCT7718W-GP

74.07718.0B9

ALERT# T_CRIT#

R2815 18K7R2F-GPR2815 18K7R2F-GP R2814 2KR2F-3-GPR2814 2KR2F-3-GP

SCL SDA

ALERT#

8 7 6 5

R5

1 2 1 2

ALERT#

3D3V_S0

DY

THM_SML1_CLK 20,86 THM_SML1_DATA 20,86

12

DY

C2808

SCD1U10V2KX-5GP

Reserved for signal quality

C2812

improvement.

SCD1U10V2KX-5GP

FAN_TACH127

AFTP2802AFTP2802

AFTP2801AFTP2801

X02 1227

R2807

1 2

0R0402-PAD

FAN_TACH1_C

1

FAN_VCC

1

X02

C2809

SC4D7U6D3V3KX-GP

C2809

FAN_TACH1_C

*Layout* 15 mil

21

12

D2802

DY

CH551H-30PT-GP

83.R5003.C8F

2nd = 83.R5003.G8H

3rd = 83.R5003.H8H

4th = 83.5R003.08F

AFTP2803AFTP2803

FAN_VCC

12

DY

1

12

EC2801

C2810

DY

SC2200P50V2KX-2GP

2nd = 20.D0246.103

3 2

1

20.F1716.003

SCD1U16V2KX-3GP

FAN1

5

4

HR-CON3-GP

R7

VGA Thermal sensor P2800

P2800_VGA_DXP86

Layout notice : Both DXN and DXP routing 10 mil trace width and 10 mil spacing.

P2800_VGA_DXN86

B B

3D3V_S0

THERM_SYS_SHDN#

A A

P2800_VGA_DXP

12

DY

P2800_VGA_DXN

1 2

R2817 0R0402-PADR2817 0R0402-PAD

12

R2820

DY

470KR2F-GP

1 2

DY

R2812 0R2J-2-GP

R(K )= 0.0012*T^2- 0.9308T+



3D3V_S0_thermal VGA_THRM_TDR

C2813

C2813 SC2200P50V2KX-2GP

SC2200P50V2KX-2GP

3D3V_S0_thermal

12

C2814

DY

SCD1U10V2KX-5GP

86.9 

1 2

24K3R2F-1-GP

R2801

DY





T8_G709

U2805

5

VCC

6

DXP

7

DY

DXN

8

OTZ

P2800EB0-GP

74.02800.B71

G709_SET

TDR

TDL

GND

ADJ

X02-0311 Add R2816& R2817 to option VGA_THRM and DY the circuit

U2804

1

SET

2

GND OUT#3HYST

G709T1UF-GP

74.00709.A7F

96.147

5

4

VGA_THRM_TDL

3 2 1

DY

VCC

5 4

DY

R2818 0R2J-2-GP

1 2

R2819 0R2J-2-GP

1 2

DY

U2804_5

DY

U2804_4

R2811 0R2J-2-GP

DY

12

R2805 150R2F-1-GP

C2816

C2816 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

DY

R2810 0R2J-2-GP

12

DY

VGA_THRM 27

12

R2816

R2816 100KR2J-1-GP

100KR2J-1-GP

DY

3D3V_S0

12

Q2802

Q2802 2N7002BK-GP

2N7002BK-GP

12

DY

D S

84.07002.I31

G

2nd = 84.2N702.W31

3rd = 84.2N702.J31

3D3V_S0

2

PURE_HW _SHUTDOWN#27,36,86

C2811

SCD1U10V2KX-5GP

3D3V_S03D3V_S0

12

3D3V_S0

12

3

C2811

X00

THERM_SYS_SHDN#

Title

Size Document Number Rev

Size Document Number Rev A3

A3

A3 Date: Sheet of

Date: Sheet of

R2809

DY

100KR2J-1-GP

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Thermal P2800/Fan Controllor P2793

Enrico Caruso 14 MLK DIS

Tuesday, January 03, 2012

28 104

1

X02

5

SSID = AUDIO

3D3V_S0

12

R2941

R2941 10KR2F-2-GP

10KR2F-2-GP

D D

C C

AUD_SENSE_A

12

C2919

DY

SC1000P50V3JN-GP-U

X02 1216

INT_MIC_L_R

INT_MIC_L_R82

3D3V_S0

B B

AMP_MUTE#27

1 2

DY

R2918 10KR2J-3-GP

R2945

2K2R2J-2-GP

12

R2942

1 2

11KR2F-L-GP

R2923

1 2

18KR2F-GP

VREFOUT_C

X00

1

AUD_HP1_JD# 82

AUD_5V

12

DY

C2940

SC10U6D3V5MX-3GP

C2952

C2952 SC1U10V2KX-1GP

SC1U10V2KX-1GP

1 2

3

D2901

D2901 BAS16-6-GP

BAS16-6-GP

POP

2

83.00016.K11

2nd = 83.00016.F11

AUD_PD#_C

EXT_MIC_JD# 82

C2938

SC1U10V2KX-1GP

SC10U6D3V5MX-3GP

12

X00

C2946

SC2D2U6D3V3KX-GP

HDA_CODEC_SDOUT21 HDA_CODEC_BITCLK21

HDA_CODEC_SYNC21 HDA_CODEC_RST#21

R2925

POP

1KR2J-1-GP

4

12

C2945

HDA_SDIN021

AUD_PD#_C1

12

AUD_5V

12

C2939

SC10U6D3V5MX-3GP

X00

12

C2944

SC2D2U6D3V3KX-GP

POP

2nd = 84.03906.F11

C2936

SCD1U10V2KX-5GP

C2937

SC1U10V2KX-1GP

3D3V_S0

AUD_3D3V_1D5V

INT_MIC_L_R82

C2924 SC22P50V2JN-4GP

12

DY

R2906

12

R2926

R2926 100KR2J-1-GP

100KR2J-1-GP

MMBT3906-4-GP

84.T3906.A11

Q2901

E

B

POP

C

1D8V_S0

AUD_PC_BEEP Trace width>15 mils

12

C2935

C2935 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

1 2

R2915 33R2F-3-GPR2915 33R2F-3-GP

1 2

3D3V_S0

HP_MUTE

HDA_CODEC_BITCLK_R

0R0402-PAD

X02

AUD_PC_BEEP

3

AUD_PC_BEEP

12

C2941SCD1U10V2KX-5GP C2941SCD1U10V2KX-5GP

12

C2942SCD1U10V2KX-5GP C2942SCD1U10V2KX-5GP

12

C2943SC1U10V2KX-1GP C2943SC1U10V2KX-1GP

POP

R2927

R2927 1KR2J-1-GP

1KR2J-1-GP

X01 1111

R2913

100KR2J-1-GP

X02 1230

VCOM

VHP_FILTVHP_FILT

INT_MIC_L_R_C

AUD_SENSE_A

ACZ_SDATAIN0_R

12

POP

12

U2901

18

VA

12

VA_HP

36

VP_L

7

VP_R

19

VCOM

11

VHP_FILT-

17

VREF_FILT

28

VL_IF

30

VL_HD

23

MICIN

25

SENSE_A

27

DMIC_SDA/GPIO0

26

DMIC_SCL/GPIO1

33

SDI

31

SDO

32

BITCLK

34

SYNC

35

RESET#

29

PCBEEP

CS4213D-CNZR-GP

71.04213.003

12

C2949

C2949 SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

3

R2928 1KR2J-1-GP

POP

R2929 1KR2J-1-GP

POP

D2902

D2902 BAT54C-U-GP

BAT54C-U-GP

83.00054.Q81

2nd = 83.R2003.E81

1 2

3rd = 83.00054.X81

4th = 83.BAT54.081

LINEIN_L

LINEIN_R

SPKR_L+

SPKR_L-

SPKR_R+

SPKR_R-

FLYP FLYN

VREFOUT_B

VREFOUT_C

HPOUT_L

HPOUT_R

HPREF

AGND

GND GND

PGND_L

PGND_R

12

2ND = 84.03904.P11

2

R2909

SB_SPKR_R

KBC_BEEP_R

MIC_IN_L_C

20

MIC_IN_R_C

21 1

2 6

5 8

9 22

24

AUD_HP1_JACK_L

13

AUD_HP1_JACK_R

15 14

16 10

37 3

4

R2909

1 2

0R2J-2-GP

R2910

1 2

0R2J-2-GP

AUD_SPK_L+ AUD_SPK_L-

AUD_SPK_R+ AUD_SPK_R-

PUMP_FLYP

C2948 SC2D2U10V3KX-1GPC2948 SC2D2U10V3KX-1GP

PUMP_FLYN

VREFOUT_B VREFOUT_C

Depop sound

AUD_HP1_JACK_R2 AUD_HP1_JACK_L2

3

Q2902

HP_MUTE_RC2HP_MUTE_R

HP_MUTE_RC1

84.03904.L06

1

POP

Q2902 PMBS3904-1-GP

PMBS3904-1-GP

2

From PCH

HDA_SPKR 21

KBC_BEEP 27

From EC

X00

C2947 SC1U10V2KX-1GPC2947 SC1U10V2KX-1GP

1 2

C2950 SC1U10V2KX-1GPC2950 SC1U10V2KX-1GP

1 2

AUD_SPK_L+ 58 AUD_SPK_L- 58

AUD_SPK_R+ 58 AUD_SPK_R- 58

1 2

R2916 49D9R2F-GPR2916 49D9R2F-GP

1 2

R2917 49D9R2F-GPR2917 49D9R2F-GP

1 2

3

1

POP

Q2903

Q2903 PMBS3904-1-GP

PMBS3904-1-GP

2

84.03904.L06

2ND = 84.03904.P11

1

5V_S0 AUD_5V

MIC_IN_L MIC_IN_R

VREFOUT_B

AUD_HP1_JACK_L2 82 AUD_HP1_JACK_R2 82

X02

R2911 0R0805-PADR2911 0R0805-PAD

1 2

X02

R2912

R2944

4D3KR2F-GP

1 2

R2905

1 2

0R0402-PAD

12

0R0805-PAD

AUD_3D3V_1D5V3D3V_S0

X02

12

R2943

R2943 4D3KR2F-GP

4D3KR2F-GP

X00

C2951

SC1U10V2KX-1GP

MIC_IN_L 82 MIC_IN_R 82

1 2

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet of

Audio Codec CS4213D

Enrico Caruso 14 MLK DIS

Taipei Hsien 221, Taiwan, R.O.C.

29 104Tuesday, January 03, 2012

1

X02

5

D D

4

3

2

1

(Blanking)

C C

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet of

Enrico Caruso 14 MLK DIS

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

1

30 104Friday, December 30, 2011

X02

Dell Enrico Caruso 14 MLK DIS Schematics

Specifications and Main Features

Frequently Asked Questions

User Manual