Dell 7559 Schematics
1
2
3
4
5
6
7
8
Block Diagram
A A
HDMI Conn.
PAGE 30
Re-Driver
PS8407A
PAGE 30
INT HDMI
CPU
PEG x 8
Skylake-H
Channel A
DDR3 SO-DIMM
PAGE 15
DDR3L 1600MT/s 1.35V
Channel B
DDR3 SO-DIMM
B B
M.2(NGFF) SSD
Flash ROM
4 MB for ME
Flash ROM
8 MB for BIOS+EC
16 MB (Reserve)
C C
Touch Pad
K/B
PAGE 16
PAGE 28
PAGE 28
PAGE 27
PAGE 27
PAGE 31
PAGE 31
PCIE Gen III x4 / SATA III 2,3
SPI
SPI
I2C
PS2
DDR3L 1600MT/s 1.35V
SATA3 6GB /S
EC
ITE
IT8528E
Package : LQPF128
I2C
LPC
Processor : Quad Core
Power : 45W (35W w/dGPU)
Package : BGA1440
Size : 42x28 (mm)
SYSTEM MEMORY
PAGE 2~8
5GT/s
DMI X 4
Mobile Intel
Sunrise point - H
Platform Controller Hub
Power : 2.8 Watt
Package : FCBGA837
eDP 4 Lanes
Giga LAN
PCIE
PCIE Port 5
RTL8111GUHDD
PCIE
USB2.0
Port 1
USB 3.0
Power Share
USB3.0
PAGE 34
Port 1
GPU
Nvidia
N16P-GX
29 x 29 mm
Package : BGA908
PAGE 37
PCIE Port 6
Port 2 Port 3
50W
PAGE 17~21
TRANSFORMER RJ45
Port 5
Port 2 Port 3
GDDR5 x 8
(256 Mb x 16)
15.6" eDP Panel
UHD 3840 x 2160
PAGE 37 PAGE 37
NGFF
WLAN + BT
USB 3.0USB 3.0
Type AType A
PAGE 22~25
PAGE 29
Camera
PAGE 29PAGE 36
Port 4
Sub Woofer
AMP
ANPEC
ALC1003-CGT
Size : 23 x 23 (mm)
FAN
PAGE 33
PAGE 26
HDA
Audio Codec
Universal Jack
Realtek
Card Reader
SD slot Realtek
PAGE 35
RTS5227S
9 x 9mm
PAGE 35
PCIE
PCIe Port7
PAGE 9~14
ALC3246
IO Board
IO Board
IO BoardIO Board
SPEAKER
D D
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Monday, May 25, 2015
Date: Sheet of
Monday, May 25, 2015
Date: Sheet of
1
2
3
4
5
6
Monday, May 25, 2015
7
PROJECT :
BLOCK DIAGRAM
BLOCK DIAGRAM
BLOCK DIAGRAM
AM9A
AM9A
AM9A
1 57
1 57
1 57
8
A0
A0
A0
5
4
3
2
1
Skylake Processor (DDR3-CH-A)
SKL with DDR3L is IL memory design.
M_A_DQ[63:0]15 M_B_DQ[63:0]16
D D
C C
B B
M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63
For ECC
U10A
Interleve
BR6
DDR0_DQ[0]
BT6
DDR0_DQ[1]
BP3
DDR0_DQ[2]
BR3
DDR0_DQ[3]
BN5
DDR0_DQ[4]
BP6
DDR0_DQ[5]
BP2
DDR0_DQ[6]
BN3
DDR0_DQ[7]
BL4
DDR0_DQ[8]
BL5
DDR0_DQ[9]
BL2
DDR0_DQ[10]
BM1
DDR0_DQ[11]
BK4
DDR0_DQ[12]
BK5
DDR0_DQ[13]
BK1
DDR0_DQ[14]
BK2
DDR0_DQ[15]
BG4
DDR0_DQ[16]/DDR0_DQ[32]
BG5
DDR0_DQ[17]/DDR0_DQ[33]
BF4
DDR0_DQ[18]/DDR0_DQ[34]
BF5
DDR0_DQ[19]/DDR0_DQ[35]
BG2
DDR0_DQ[20]/DDR0_DQ[36]
BG1
DDR0_DQ[21]/DDR0_DQ[37]
BF1
DDR0_DQ[22]/DDR0_DQ[38]
BF2
DDR0_DQ[23]/DDR0_DQ[39]
BD2
DDR0_DQ[24]/DDR0_DQ[40]
BD1
DDR0_DQ[25]/DDR0_DQ[41]
BC4
DDR0_DQ[26]/DDR0_DQ[42]
BC5
DDR0_DQ[27]/DDR0_DQ[43]
BD5
DDR0_DQ[28]/DDR0_DQ[44]
BD4
DDR0_DQ[29]/DDR0_DQ[45]
BC1
DDR0_DQ[30]/DDR0_DQ[46]
BC2
DDR0_DQ[31]/DDR0_DQ[47]
AB1
DDR0_DQ[32]/DDR1_DQ[0]
AB2
DDR0_DQ[33]/DDR1_DQ[1]
AA4
DDR0_DQ[34]/DDR1_DQ[2]
AA5
DDR0_DQ[35]/DDR1_DQ[3]
AB5
DDR0_DQ[36]/DDR1_DQ[4]
AB4
DDR0_DQ[37]/DDR1_DQ[5]
AA2
DDR0_DQ[38]/DDR1_DQ[6]
AA1
DDR0_DQ[39]/DDR1_DQ[7]
V5
DDR0_DQ[40]/DDR1_DQ[8]
V2
DDR0_DQ[41]/DDR1_DQ[9]
U1
DDR0_DQ[42]/DDR1_DQ[10]
U2
DDR0_DQ[43]/DDR1_DQ[11]
V1
DDR0_DQ[44]/DDR1_DQ[12]
V4
DDR0_DQ[45]/DDR1_DQ[13]
U5
DDR0_DQ[46]/DDR1_DQ[14]
U4
DDR0_DQ[47]/DDR1_DQ[15]
R2
DDR0_DQ[48]/DDR1_DQ[32]
P5
DDR0_DQ[49]/DDR1_DQ[33]
R4
DDR0_DQ[50]/DDR1_DQ[34]
P4
DDR0_DQ[51]/DDR1_DQ[35]
R5
DDR0_DQ[52]/DDR1_DQ[36]
P2
DDR0_DQ[53]/DDR1_DQ[37]
R1
DDR0_DQ[54]/DDR1_DQ[38]
P1
DDR0_DQ[55]/DDR1_DQ[39]
M4
DDR0_DQ[56]/DDR1_DQ[40]
M1
DDR0_DQ[57]/DDR1_DQ[41]
L4
DDR0_DQ[58]/DDR1_DQ[42]
L2
DDR0_DQ[59]/DDR1_DQ[43]
M5
DDR0_DQ[60]/DDR1_DQ[44]
M2
DDR0_DQ[61]/DDR1_DQ[45]
L5
DDR0_DQ[62]/DDR1_DQ[46]
L1
DDR0_DQ[63]/DDR1_DQ[47]
BA2
DDR0_ECC[0]
BA1
DDR0_ECC[1]
AY4
DDR0_ECC[2]
AY5
DDR0_ECC[3]
BA5
DDR0_ECC[4]
BA4
DDR0_ECC[5]
AY1
DDR0_ECC[6]
AY2
DDR0_ECC[7]
DDR CHANNEL A
SKL_H_BGA_BGA/BGA
SKYLAKE_HALO
Non-Interleve
BGA1440
DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0]
DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1]
DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0]
DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16]
DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14]
DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15]
DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0]
DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1]
DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2]
DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5]
DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6]
DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7]
DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8]
DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9]
DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10]
DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11]
DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12]
DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13]
DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1]
DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT#
Interleve
DDR0_DQSN[2]/DDR0_DQSN[4]
DDR0_DQSN[3]/DDR0_DQSN[5]
DDR0_DQSP[4]/DDR1_DQSP[0]
DDR0_DQSP[5]/DDR1_DQSP[1]
DDR0_DQSP[6]/DDR1_DQSP[4]
DDR0_DQSP[7]/DDR1_DQSP[5]
Interleve
DDR0_DQSP[2]/DDR0_DQSP[4]
DDR0_DQSP[3]/DDR0_DQSP[5]
DDR0_DQSN[4]/DDR1_DQSN[0]
DDR0_DQSN[5]/DDR1_DQSN[1]
DDR0_DQSN[6]/DDR1_DQSN[4]
DDR0_DQSN[7]/DDR1_DQSN[5]
1 OF 14
DDR0_CKP[0]
DDR0_CKN[0]
DDR0_CKN[1]
DDR0_CKP[1]
DDR0_CLKP[2]
DDR0_CLKN[2]
DDR0_CLKP[3]
DDR0_CLKN[3]
DDR0_CKE[0]
DDR0_CKE[1]
DDR0_CKE[2]
DDR0_CKE[3]
DDR0_CS#[0]
DDR0_CS#[1]
DDR0_CS#[2]
DDR0_CS#[3]
DDR0_ODT[0]
DDR0_ODT[1]
DDR0_ODT[2]
DDR0_ODT[3]
DDR0_MA[3]
DDR0_MA[4]
DDR0_PAR
DDR0_ALERT#
Non-Interleve
DDR0_DQSN[0]
DDR0_DQSN[1]
Non-Interleve
DDR0_DQSP[0]
DDR0_DQSP[1]
DDR0_DQSP[8]
DDR0_DQSN[8]
REV = 1
AG1
AG2
AK1
AK2
AL3
AK3
AL2
AL1
AT1
AT2
AT3
AT5
AD5
AE2
AD2
AE5
AD3
AE4
AE1
AD4
AH5
AH1
AU1
AH4
AG4
AD1
AH3
AP4
AN4
AP5
AP2
AP1
AP3
AN1
AN3
AT4
AH2
AN2
AU4
AE3
AU2
AU3
AG3
AU5
BR5
BL3
BG3
BD3
AB3
V3
R3
M3
BP5
BK3
BF3
BC3
AA3
U3
P3
L3
AY3
BA3
M_A_CLKP0
M_A_CLKN0
M_A_CLKN1
M_A_CLKP1
M_A_CKE0
M_A_CKE1
M_A_CS#0
M_A_CS#1
M_A_ODT0
M_A_ODT1
M_A_BS#0
M_A_BS#1
M_A_BS#2
M_A_RAS#
M_A_WE#
M_A_CAS#
M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15
M_A_CLKP0 15
M_A_CLKN0 15
M_A_CLKN1 15
M_A_CLKP1 15
M_A_CKE0 15
M_A_CKE1 15
M_A_CS#0 15
M_A_CS#1 15
M_A_ODT0 15
M_A_ODT1 15
M_A_BS#[2:0] 15
M_A_RAS# 15
M_A_WE# 15
M_A_CAS# 15
M_A_A[15:0] 15
3/11 add GND 3/11 add GND
M_A_DQSN0
M_A_DQSN1
M_A_DQSN2
M_A_DQSN3
M_A_DQSP4
M_A_DQSP5
M_A_DQSP6
M_A_DQSP7
M_A_DQSP0
M_A_DQSP1
M_A_DQSP2
M_A_DQSP3
M_A_DQSN4
M_A_DQSN5
M_A_DQSN6
M_A_DQSN7
M_A_DQSN[3:0] 15
M_A_DQSP[7:4] 15
M_A_DQSP[3:0] 15
M_A_DQSN[7:4] 15
M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63
For ECC
For ECC
Place close to CPU
R301 121/F_4
R299 75/F_4
R298 100/F_4
Follow SKL-H WP(V0.91)
support DDR3L SO-DIMM
#549401 page 26
DDR_RCOMP_0
DDR_RCOMP_1
DDR_RCOMP_2 +VREFDQ_SB
2/10 add net name
Skylake Processor (DDR3-CH-B)
SKL with DDR3L is IL memory design.
U10B
InterleveNon-Interleve
BT11
DDR1_DQ[0]/DDR0_DQ[16]
BR11
DDR1_DQ[1]/DDR0_DQ[17]
BT8
DDR1_DQ[2]/DDR0_DQ[18]
BR8
DDR1_DQ[3]/DDR0_DQ[19]
BP11
DDR1_DQ[4]/DDR0_DQ[20]
BN11
DDR1_DQ[5]/DDR0_DQ[21]
BP8
DDR1_DQ[6]/DDR0_DQ[22]
BN8
DDR1_DQ[7]/DDR0_DQ[23]
BL12
DDR1_DQ[8]/DDR0_DQ[24]
BL11
DDR1_DQ[9]/DDR0_DQ[25]
BL8
DDR1_DQ[10]/DDR0_DQ[26]
BJ8
DDR1_DQ[11]/DDR0_DQ[27]
BJ11
DDR1_DQ[12]/DDR0_DQ[28]
BJ10
DDR1_DQ[13]/DDR0_DQ[29]
BL7
DDR1_DQ[14]/DDR0_DQ[30]
BJ7
DDR1_DQ[15]/DDR0_DQ[31]
BG11
DDR1_DQ[16]/DDR0_DQ[48]
BG10
DDR1_DQ[17]/DDR0_DQ[49]
BG8
DDR1_DQ[18]/DDR0_DQ[50]
BF8
DDR1_DQ[19]/DDR0_DQ[51]
BF11
DDR1_DQ[20]/DDR0_DQ[52]
BF10
DDR1_DQ[21]/DDR0_DQ[53]
BG7
DDR1_DQ[22]/DDR0_DQ[54]
BF7
DDR1_DQ[23]/DDR0_DQ[55]
BB11
DDR1_DQ[24]/DDR0_DQ[56]
BC11
DDR1_DQ[25]/DDR0_DQ[57]
BB8
DDR1_DQ[26]/DDR0_DQ[58]
BC8
DDR1_DQ[27]/DDR0_DQ[59]
BC10
DDR1_DQ[28]/DDR0_DQ[60]
BB10
DDR1_DQ[29]/DDR0_DQ[61]
BC7
DDR1_DQ[30]/DDR0_DQ[62]
BB7
DDR1_DQ[31]/DDR0_DQ[63]
AA11
DDR1_DQ[32]/DDR1_DQ[16]
AA10
DDR1_DQ[33]/DDR1_DQ[17]
AC11
DDR1_DQ[34]/DDR1_DQ[18]
AC10
DDR1_DQ[35]/DDR1_DQ[19]
AA7
DDR1_DQ[36]/DDR1_DQ[20]
AA8
DDR1_DQ[37]/DDR1_DQ[21]
AC8
DDR1_DQ[38]/DDR1_DQ[22]
AC7
DDR1_DQ[39]/DDR1_DQ[23]
W8
DDR1_DQ[40]/DDR1_DQ[24]
W7
DDR1_DQ[41]/DDR1_DQ[25]
V10
DDR1_DQ[42]/DDR1_DQ[26]
V11
DDR1_DQ[43]/DDR1_DQ[27]
W11
DDR1_DQ[44]/DDR1_DQ[28]
W10
DDR1_DQ[45]/DDR1_DQ[29]
V7
DDR1_DQ[46]/DDR1_DQ[30]
V8
DDR1_DQ[47]/DDR1_DQ[31]
R11
DDR1_DQ[48]
P11
DDR1_DQ[49]
P7
DDR1_DQ[50]
R8
DDR1_DQ[51]
R10
DDR1_DQ[52]
P10
DDR1_DQ[53]
R7
DDR1_DQ[54]
P8
DDR1_DQ[55]
L11
DDR1_DQ[56]
M11
DDR1_DQ[57]
L7
DDR1_DQ[58]
M8
DDR1_DQ[59]
L10
DDR1_DQ[60]
M10
DDR1_DQ[61]
M7
DDR1_DQ[62]
L8
DDR1_DQ[63]
AW11
DDR1_ECC[0]
AY11
DDR1_ECC[1]
AY8
DDR1_ECC[2]
AW8
DDR1_ECC[3]
AY10
DDR1_ECC[4]
AW10
DDR1_ECC[5]
AY7
DDR1_ECC[6]
AW7
DDR1_ECC[7]
G1
DDR_RCOMP[0]
H1
DDR_RCOMP[1]
J2
DDR_RCOMP[2]
SKL_H_BGA_BGA/BGA
DDR CHANNEL B
SKYLAKE_HALO
BGA1440
DDR3L LPDDR3 DDR4DDR3L LPDDR3 DDR4
DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16]
DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14]
DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15]
DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0]
DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1]
DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0]
DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0]
DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1]
DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2]
DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5]
DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6]
DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7]
DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8]
DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9]
DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10]
DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11]
DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12]
DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13]
DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1]
DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT#
InterleveNon-Interleve
DDR1_DQSN[0]/DDR0_DQSN[2]
DDR1_DQSN[1]/DDR0_DQSN[3]
DDR1_DQSN[2]/DDR0_DQSN[6]
DDR1_DQSN[3]/DDR0_DQSN[7]
DDR1_DQSN[4]/DDR1_DQSN[2]
DDR1_DQSN[5]/DDR1_DQSN[3]
InterleveNon-Interleve
DDR1_DQSP[0]/DDR0_DQSP[2]
DDR1_DQSP[1]/DDR0_DQSP[3]
DDR1_DQSP[2]/DDR0_DQSP[6]
DDR1_DQSP[3]/DDR0_DQSP[7]
DDR1_DQSP[4]/DDR1_DQSP[2]
DDR1_DQSP[5]/DDR1_DQSP[3]
2 OF 14
M_B_CLKP0
AM9
DDR1_CKP[0]
DDR1_CKN[0]
DDR1_CKN[1]
DDR1_CKP[1]
DDR1_CLKP[2]
DDR1_CLKN[2]
DDR1_CLKP[3]
DDR1_CLKN[3]
DDR1_CKE[0]
DDR1_CKE[1]
DDR1_CKE[2]
DDR1_CKE[3]
DDR1_CS#[0]
DDR1_CS#[1]
DDR1_CS#[2]
DDR1_CS#[3]
DDR1_ODT[0]
DDR1_ODT[1]
DDR1_ODT[2]
DDR1_ODT[3]
DDR1_MA[3]
DDR1_MA[4]
DDR1_PAR
DDR1_ALERT#
DDR1_DQSN[6]
DDR1_DQSN[7]
DDR1_DQSP[6]
DDR1_DQSP[7]
DDR1_DQSP[8]
DDR1_DQSN[8]
DDR_VREF_CA
DDR0_VREF_DQ
DDR1_VREF_DQ
REV = 1
Follow SKL-H WP(V0.91) support DDR3L SO-DIMM
#549401 page 41
AN9
AM8
AM7
AM11
AM10
AJ10
AJ11
AT8
AT10
AT7
AT11
AF11
AE7
AF10
AE10
AF7
AE8
AE9
AE11
AH10
AH11
AF8
AH8
AH9
AR9
AJ9
AK6
AK5
AL5
AL6
AM6
AN7
AN10
AN8
AR11
AH7
AN11
AR10
AF9
AR7
AT9
AJ7
AR8
BP9
BL9
BG9
BC9
AC9
W9
R9
M9
BR9
BJ9
BF9
BB9
AA9
V9
P9
L9
AW9
AY9
BN13
BP13
BR13
M_B_CLKN0
M_B_CLKN1
M_B_CLKP1
M_B_CKE0
M_B_CKE1
M_B_CS#0
M_B_CS#1
M_B_ODT0
M_B_ODT1
M_B_RAS#
M_B_WE#
M_B_CAS#
M_B_BS#0
M_B_BS#1
M_B_BS#2
M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_A14
M_B_A15
M_B_DQSN0
M_B_DQSN1
M_B_DQSN2
M_B_DQSN3
M_B_DQSN4
M_B_DQSN5
M_B_DQSN6
M_B_DQSN7
M_B_DQSP0
M_B_DQSP1
M_B_DQSP2
M_B_DQSP3
M_B_DQSP4
M_B_DQSP5
M_B_DQSP6
M_B_DQSP7
For ECC
+DDR_VREF_CA
+VREFDQ_SA
M_B_CLKP0 16
M_B_CLKN0 16
M_B_CLKN1 16
M_B_CLKP1 16
M_B_CKE0 16
M_B_CKE1 16
M_B_CS#0 16
M_B_CS#1 16
M_B_ODT0 16
M_B_ODT1 16
M_B_RAS# 16
M_B_WE# 16
M_B_CAS# 16
M_B_BS#[2:0] 16
M_B_A[15:0] 16
M_B_DQSN[7:0] 16
M_B_DQSP[7:0] 16
+DDR_VREF_CA
+VREFDQ_SA
+VREFDQ_SB
A A
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Monday, May 25, 2015
Date: Sheet of
Monday, May 25, 2015
Date: Sheet of
5
4
3
2
Monday, May 25, 2015
PROJECT :
CPU
CPU
CPU
AM9A
AM9A
AM9A
2 57
2 57
1
2 57
A0
A0
A0
5
4
3
2
1
Skylake Processor (PEG, DMI)
Skylake Processor (DDI, eDP)
SKYLAKE_HALO
D D
PEG_RXP717
PEG_RXN717
PEG_RXP617
PEG_RXN617
PEG_RXP517
PEG_RXN517
PEG_RXP417
PEG_RXN417
PEG_RXP317
PEG_RXN317
PEG_RXP217
PEG_RXN217
PEG_RXP117
C C
B B
PEG_RXN117
PEG_RXP017
PEG_RXN017
546884 V1.0 P188
+VCCIO
DMI_RXP09
DMI_RXN09
DMI_RXP19
DMI_RXN19
DMI_RXP29
DMI_RXN29
DMI_RXP39
DMI_RXN39
A A
2/3 Port
PEG_RXP7
PEG_RXN7
PEG_RXP6
PEG_RXN6
PEG_RXP5
PEG_RXN5
PEG_RXP4
PEG_RXN4
PEG_RXP3
PEG_RXN3
PEG_RXP2
PEG_RXN2
PEG_RXP1
PEG_RXN1
PEG_RXP0
PEG_RXN0
R300
PEG_RCOMP
24.9/F_4
Place inside CPU cavity
DMI_RXP0
DMI_RXN0
DMI_RXP1
DMI_RXN1
DMI_RXP2
DMI_RXN2
DMI_RXP3
DMI_RXN3
U10C
E25
PEG_RXP[0]
D25
PEG_RXN[0]
E24
PEG_RXP[1]
F24
PEG_RXN[1]
E23
PEG_RXP[2]
D23
PEG_RXN[2]
E22
PEG_RXP[3]
F22
PEG_RXN[3]
E21
PEG_RXP[4]
D21
PEG_RXN[4]
E20
PEG_RXP[5]
F20
PEG_RXN[5]
E19
PEG_RXP[6]
D19
PEG_RXN[6]
E18
PEG_RXP[7]
F18
PEG_RXN[7]
D17
PEG_RXP[8]
E17
PEG_RXN[8]
F16
PEG_RXP[9]
E16
PEG_RXN[9]
D15
PEG_RXP[10]
E15
PEG_RXN[10]
F14
PEG_RXP[11]
E14
PEG_RXN[11]
D13
PEG_RXP[12]
E13
PEG_RXN[12]
F12
PEG_RXP[13]
E12
PEG_RXN[13]
D11
PEG_RXP[14]
E11
PEG_RXN[14]
F10
PEG_RXP[15]
E10
PEG_RXN[15]
G2
PEG_RCOMP
D8
DMI_RXP[0]
E8
DMI_RXN[0]
E6
DMI_RXP[1]
F6
DMI_RXN[1]
D5
DMI_RXP[2]
E5
DMI_RXN[2]
J8
DMI_RXP[3]
J9
DMI_RXN[3]
SKL_H_BGA_BGA/BGA
BGA1440
3 OF 14
PEG_TXP[0]
PEG_TXN[0]
PEG_TXP[1]
PEG_TXN[1]
PEG_TXP[2]
PEG_TXN[2]
PEG_TXP[3]
PEG_TXN[3]
PEG_TXP[4]
PEG_TXN[4]
PEG_TXP[5]
PEG_TXN[5]
PEG_TXP[6]
PEG_TXN[6]
PEG_TXP[7]
PEG_TXN[7]
PEG_TXP[8]
PEG_TXN[8]
PEG_TXP[9]
PEG_TXN[9]
PEG_TXP[10]
PEG_TXN[10]
PEG_TXP[11]
PEG_TXN[11]
PEG_TXP[12]
PEG_TXN[12]
PEG_TXP[13]
PEG_TXN[13]
PEG_TXP[14]
PEG_TXN[14]
PEG_TXP[15]
PEG_TXN[15]
DMI_TXP[0]
DMI_TXN[0]
DMI_TXP[1]
DMI_TXN[1]
DMI_TXP[2]
DMI_TXN[2]
DMI_TXP[3]
DMI_TXN[3]
REV = 1
PEG_TXP7
B25
PEG_TXN7
A25
PEG_TXP6
B24
PEG_TXN6
C24
PEG_TXP5
B23
PEG_TXN5
A23
PEG_TXP4
B22
PEG_TXN4
C22
PEG_TXP3
B21
PEG_TXN3
A21
PEG_TXP2
B20
PEG_TXN2
C20
PEG_TXP1
B19
PEG_TXN1
A19
PEG_TXP0
B18
PEG_TXN0
C18
A17
B17
C16
B16
A15
B15
C14
B14
A13
B13
C12
B12
A11
B11
C10
B10
DMI_TXP0
B8
DMI_TXN0
A8
DMI_TXP1
C6
DMI_TXN1
B6
DMI_TXP2
B5
DMI_TXN2
A5
DMI_TXP3
D4
DMI_TXN3
B4
C589 0.22U/16V_4
C591 0.22U/16V_4
C595 0.22U/16V_4
C592 0.22U/16V_4
C596 0.22U/16V_4
C598 0.22U/16V_4
C601 0.22U/16V_4
C600 0.22U/16V_4
C602 0.22U/16V_4
C603 0.22U/16V_4
C605 0.22U/16V_4
C604 0.22U/16V_4
C606 0.22U/16V_4
C610 0.22U/16V_4
C614 0.22U/16V_4
C611 0.22U/16V_4
2/3 Port
DMI_TXP0 9
DMI_TXN0 9
DMI_TXP1 9
DMI_TXN1 9
DMI_TXP2 9
DMI_TXN2 9
DMI_TXP3 9
DMI_TXN3 9
PEG_TXP7_C 17
PEG_TXN7_C 17
PEG_TXP6_C 17
PEG_TXN6_C 17
PEG_TXP5_C 17
PEG_TXN5_C 17
PEG_TXP4_C 17
PEG_TXN4_C 17
PEG_TXP3_C 17
PEG_TXN3_C 17
PEG_TXP2_C 17
PEG_TXN2_C 17
PEG_TXP1_C 17
PEG_TXN1_C 17
PEG_TXP0_C 17
PEG_TXN0_C 17
#546884 PDG 1.0 page 163 #546884 PDG 1.0 page 155
INT_HDMI_TXP230
INT_HDMI_TXN230
INT_HDMI_TXP130
HDMI eDP
INT_HDMI_TXN130
INT_HDMI_TXP030
INT_HDMI_TXN030
INT_HDMI_TXCP30
INT_HDMI_TXCN30
INT_HDMI_TXP2
INT_HDMI_TXN2
INT_HDMI_TXP1
INT_HDMI_TXN1
INT_HDMI_TXP0
INT_HDMI_TXN0
INT_HDMI_TXCP
INT_HDMI_TXCN
U10D
K36
DDI1_TXP[0]
K37
DDI1_TXN[0]
J35
DDI1_TXP[1]
J34
DDI1_TXN[1]
H37
DDI1_TXP[2]
H36
DDI1_TXN[2]
J37
DDI1_TXP[3]
J38
DDI1_TXN[3]
D27
DDI1_AUXP
E27
DDI1_AUXN
H34
DDI2_TXP[0]
H33
DDI2_TXN[0]
F37
DDI2_TXP[1]
G38
DDI2_TXN[1]
F34
DDI2_TXP[2]
F35
DDI2_TXN[2]
E37
DDI2_TXP[3]
E36
DDI2_TXN[3]
F26
DDI2_AUXP
E26
DDI2_AUXN
C34
DDI3_TXP[0]
D34
DDI3_TXN[0]
B36
DDI3_TXP[1]
B34
DDI3_TXN[1]
F33
DDI3_TXP[2]
E33
DDI3_TXN[2]
C33
DDI3_TXP[3]
B33
DDI3_TXN[3]
A27
DDI3_AUXP
B27
DDI3_AUXN
SKL_H_BGA_BGA/BGA
SKYLAKE_HALO
BGA1440
4 OF 14
EDP_TXP[0]
EDP_TXN[0]
EDP_TXP[1]
EDP_TXN[1]
EDP_TXN[2]
EDP_TXP[2]
EDP_TXN[3]
EDP_TXP[3]
EDP_AUXP
EDP_AUXN
EDP_DISP_UTIL
EDP_RCOMP
PROC_AUDIO_CLK
PROC_AUDIO_SDI
PROC_AUDIO_SDO
REV = 1
EDP_TXP0
D29
EDP_TXN0
E29
EDP_TXP1
F28
EDP_TXN1
E28
EDP_TXN2
B29
EDP_TXP2
A29
EDP_TXN3
B28
EDP_TXP3
C28
EDP_AUXP
C26
EDP_AUXN
B26
EDP_DISP_UTIL
A33
EDP_RCOMP
D37
AUD_AZACPU_SCLK
G27
AUD_AZACPU_SDO
G25
AUD_AZACPU_SDI_R
G29
EDP_TXP0 29
EDP_TXN0 29
EDP_TXP1 29
EDP_TXN1 29
EDP_TXN2 29
EDP_TXP2 29
EDP_TXN3 29
EDP_TXP3 29
EDP_AUXP 29
EDP_AUXN 29
TP1
R29 24.9/F_4
Place inside CPU cavity
R18 20_4
Place near CPU
PDG V1.0 P351
EMI
AUD_AZACPU_SCLK
+VCCIO
AUD_AZACPU_SCLK 10
AUD_AZACPU_SDO 10
AUD_AZACPU_SDI 10
EC10 *10P/50V_4_NC
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Monday, May 25, 2015
Date: Sheet of
Monday, May 25, 2015
Date: Sheet of
5
4
3
2
Monday, May 25, 2015
PROJECT :
CPU
CPU
CPU
AM9A
AM9A
AM9A
A0
A0
3 57
3 57
1
3 57
A0
5
4
3
2
1
SVID
Skylake Processor (CLK, SVID, CFG)
U10E
D D
C C
B B
HWPG26,33
PCH_THERMTRIP#10
Connector Less Debug Hooks Routing Guidelines
#546884 PDG (V1.0) page 505
PROC_TDO
PROC_TDI
PROC_TMS
PROC_TCK
PROC_TRST#
PROC_PREQ#
PROC_PRDY#
CLK_CPU_BCLKP12
CLK_CPU_BCLKN12
PCI_CLK_CPU_BCLKP12
PCI_CLK_CPU_BCLKN12
CPU_24MHZ_CLKP12
CPU_24MHZ_CLKN12
DDR_VTT_CTRL46
VCCST_PWRGD
D13 SDM10K45-7-F
21
H_PWRGOOD10
CPU_PLTRST#10
H_PM_SYNC10
H_PM_DOWN10
H_PECI10,26
PROC_TDO 10
PROC_TDI 10
PROC_TMS 10
PROC_TCK 10
PROC_TRST# 14
PROC_PREQ# 14
PROC_PRDY# 14
2/3 remove 0 ohm
TP55
TP77
TP58
CLK_CPU_BCLKP
CLK_CPU_BCLKN
PCI_CLK_CPU_BCLKP
PCI_CLK_CPU_BCLKN
CPU_24MHZ_CLKP
CPU_24MHZ_CLKN
CPU_VIDALERT#
VR_SVID_CLK
VR_SVID_DATA
H_PROCHOT#_R
DDR_VTT_CTRL
VTT EN
2/9 add net name
R314 60.4/F_4
R265 20_4
H_PECI
2/3 remove 0 ohm
VCCST_PWRGD_R
H_PM_SYNC
H_PM_DOWN_R
H_SKTOCC#
H_PROC_SELECT#
H_CATERR#
B31
BCLKP
A32
BCLKN
D35
PCI_BCLKP
C36
PCI_BCLKN
E31
CLK24P
D31
CLK24N
BH31
VIDALERT#
BH32
VIDSCK
BH29
VIDSOUT
BR30
PROCHOT#
BT13
DDR_VTT_CNTL
H13
VCCST_PWRGD
BT31
PROCPWRGD
BP35
RESET#
BM34
PM_SYNC
BP31
PM_DOWN
BT34
PECI
J31
THERMTRIP#
BR33
SKTOCC#
BN1
PROC_SELECT#
BM30
CATERR#
SKL_H_BGA_BGA/BGA
SKYLAKE_HALO
BGA1440
100 MHz
100 MHz for PCIe
24 MHz
(1V)
5 OF 14
CFG[0]
CFG[1]
CFG[2]
CFG[3]
CFG[4]
CFG[5]
CFG[6]
CFG[7]
CFG[8]
CFG[9]
CFG[10]
CFG[11]
CFG[12]
CFG[13]
CFG[14]
CFG[15]
CFG[17]
CFG[16]
CFG[19]
CFG[18]
BPM#[0]
BPM#[1]
BPM#[2]
BPM#[3]
PROC_TDO
PROC_TDI
PROC_TMS
PROC_TCK
PROC_TRST#
PROC_PREQ#
PROC_PRDY#
CFG_RCOMP
REV = 1
CFG [0..19] Internal
PU 3K to VCCIO
BN25
CFG0
BN27
CFG1
BN26
CFG2
BN28
CFG3
BR20
CFG4
BM20
CFG5
BT20
CFG6
BP20
CFG7
BR23
CFG8
BR22
CFG9
BT23
CFG10
BT22
CFG11
BM19
CFG12
BR19
CFG13
BP19
CFG14
BT19
CFG15
BN23
CFG17
BP23
CFG16
BP22
CFG19
BN22
CFG18
BR27
BT27
BM31
BT30
PROC_TDO
BT28
PROC_TDI
BL32
PROC_TMS
BP28
PROC_TCK
BR28
PROC_TRST#
BP30
PROC_PREQ#
BL30
PROC_PRDY#
BP27
CFG_RCOMP
BT25
TP63
TP5
TP62
TP6
TP69
TP76
TP70
TP74
TP64
TP68
TP65
TP67
TP10
TP71
TP73
TP72
TP8
TP7
TP66
TP9
PROC_TDI & PROC_TMS & BPM[3:0]
& PREQ# & CFG[19:0] had internal PU
TP59
TP2
TP61
TP60
TP57
TP3
TP4
R280 49.9/F_4
CFG_RCOMP PD resistor refer to
#550607 SKL-H schematic page 16
Place near CPU
SIVD CLK
SVID DATA
SVID ALERT
Procssor HOT
CPU PU/PD
Thermtrip
CPU STRAP PIN
Pin Name Usage
CFG[0]
CFG[2]
CFG[4]
CFG[6:5]
A A
CFG[7]
CFG[1] CFG[3]
Stall reset sequence after PCU
PLL lock until de-asserted
PCI Express* Static x16 Lane
Numbering Reversal.
eDP enable 1 = Disabled(Default)
PCI Express* Bifurcation 00 = 1 x8, 2 x4 PCI Express*
PEG Training 1 = PEG Train immediately following
Reserved configuration lanes.
1 = (Default) Normal Operation; No stall.
0 = Stall.
1 = Normal operation (Default)
0 = Lane numbers reversed.
0 = Enabled
01 = reserved
10 = 2 x8 PCI Express*
11 = 1 x16 PCI Express*(default)
RESET# de-assertion.(default)
0 = PEG Wait for BIOS for training.
Configuration Circuitry
CFG0
CFG2
2/4 pop R21 Lane numbers reversed
CFG4
CFG5
CFG6
CFG7
R281 *1K_4_NC
R279 1K_4
R283 1K_4
R288 1K_4
R285 *1K_4_NC
R287 *1K_4_NC
JTAG PU/PD
CFG[19:8]
5
4
3
2
VR_SVID_CLK
VR_SVID_DATA
CPU_VIDALERT#
Place near CPU
H_PROCHOT#_R
PDG V1.0 P210
+VCC_1.00
R274 220_4
R269 499/F_4
2/11 change to +VCC_1.00
Place near CPU
R271
100_4
+VCC_1.00
Place near CPU
+VCC_1.00
R270
1K_4
+VCC_1.00
R273
56.2/F_4
VR_SVID_CLK 41
VR_SVID_DATA 41
VR_SVID_ALERT# 41
H_PROCHOT# 26,40,41
Place near CPU
VCCST_PWRGD
H_CATERR#
R318 1K_4
R272 *10K_4_NC
Place near CPU
Thermtrip PU 1K ohms
PDG #546884 P213
PROC_TCK
PROC_TRST#
2/4 move R841 to PCH JTAG page
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Placed to within 200ps(1") of CPU pin
R276 *51_4_NC
R268 *51_4_NC
#546884 PDG 1.0 page 504
CPU
CPU
Monday, May 25, 2015
Monday, May 25, 2015
Monday, May 25, 2015
CPU
2/3 remove R186 1K_4
double PU
#546884 PDG page 616-> PD 51 ohm
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
PROJECT :
1
AM9A
AM9A
AM9A
4 57
4 57
4 57
A0
A0
A0
5
PDG V1.0 #546844 page 573 VCC decoupling
47uFx4, 22uFx8, 10uFx28, 1uFx63
leverage other BU to optimums capacitor design
2/11 remove 47u*4,
22u*4
D D
C C
B B
A A
+VCCIN +VCCIN
AA13
AA31
AA32
AA33
AA34
AA35
AA36
AA37
AA38
AB29
12
C17222U/6.3V/X6S_6
AB30
12
C19522U/6.3V/X6S_6
AB31
12
C18222U/6.3V/X6S_6
AB32
12
C20522U/6.3V/X6S_6
C14110U/6.3V/X6S_4
C23510U/6.3V/X6S_4
C28810U/6.3V/X6S_4
C9210U/6.3V/X6S_4
C6310U/6.3V/X6S_4
C8310U/6.3V/X6S_4
C10710U/6.3V/X6S_4
C16010U/6.3V/X6S_4
C26210U/6.3V/X6S_4
C12310U/6.3V/X6S_4
C12010U/6.3V/X6S_4
C15510U/6.3V/X6S_4
C10110U/6.3V/X6S_4
C26410U/6.3V/X6S_4
C12210U/6.3V/X6S_4
C14910U/6.3V/X6S_4
C6410U/6.3V/X6S_4
C23410U/6.3V/X6S_4
C22010U/6.3V/X6S_4
C6610U/6.3V/X6S_4
C15110U/6.3V/X6S_4
C6510U/6.3V/X6S_4
C6210U/6.3V/X6S_4
C23310U/6.3V/X6S_4
C10610U/6.3V/X6S_4 C129 1U/10V/X6S_4
C23210U/6.3V/X6S_4
C25310U/6.3V/X6S_4
C25210U/6.3V/X6S_4
AB35
AB36
AB37
AB38
AC13
AC14
AC29
AC30
AC31
AC32
AC33
AC34
AC35
AC36
AD13
AD14
AD31
AD32
AD33
AD34
AD35
AD36
AD37
AD38
AE13
AE14
AE30
AE31
AE32
AE35
AE36
AE37
AE38
AF35
AF36
AF37
AF38
K13
K14
L13
N13
N14
N30
N31
N32
N35
N36
N37
N38
P13
5
SKYLAKE_HALO
U10G
BGA1440
VCC
S0
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
SKL_H_BGA_BGA/BGA
7 OF 14
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC_SENSE
VSS_SENSE
REV = 1
4
VCC = 60A (QC:35W+GT2)
VCC = 68A (QC:45W+GT2)
V32
V33
C148 10U/6.3V/X6S_4
V34
V35
C124 1U/10V/X6S_4
V36
C121 1U/10V/X6S_4
V37
V38
W13
W14
W29
W30
C126 1U/10V/X6S_4
W31
C270 1U/10V/X6S_4
W32
C161 10U/6.3V/X6S_4
W35
C158 10U/6.3V/X6S_4
W36
W37
W38
Y29
C246 1U/10V/X6S_4
Y30
C84 1U/10V/X6S_4
Y31
Y32
C266 1U/10V/X6S_4
Y33
C138 1U/10V/X6S_4
Y34
C127 1U/10V/X6S_4
Y35
Y36
C81 1U/10V/X6S_4
L14
P29
C251 1U/10V/X6S_4
P30
P31
C137 1U/10V/X6S_4
P32
P33
C82 1U/10V/X6S_4
P34
C45 1U/10V/X6S_4
P35
P36
C279 1U/10V/X6S_4
R13
R31
R32
C269 1U/10V/X6S_4
R33
R34
R35
C79 1U/10V/X6S_4
R36
C80 1U/10V/X6S_4
R37
R38
T29
T30
T31
T32
T35
C277 1U/10V/X6S_4
T36
C105 1U/10V/X6S_4
T37
C159 10U/6.3V/X6S_4
T38
U29
U30
C157 10U/6.3V/X6S_4
U31
C100 1U/10V/X6S_4
U32
U33
U34
C44 1U/10V/X6S_4
U35
C114 1U/10V/X6S_4
U36
V13
V14
V31
C104 1U/10V/X6S_4
P14
R26 100/F_4
AG37
AG38
R23 100/F_4
Please near CPU
4
Skylake Processor (POWER)
+VCCIN
VCCCORE_SENSE 41
VSSCORE_SENSE 41
3
VCCOPC, VCCOPC_1p8, VCCEOPIO is OPC (On Package Cache)
realted power rail and used for 4+4e processor
Pandora support 4+2 Processor (w/o OPC)
Rail is unconnected for those pins w/o OPC
#544924 EDS (V0.92) page129 Note3
Unconnected for Processors without OPC.
#544924 EDS (V0.91) page121
3
U10J
BJ17
BJ19
BJ20
BK17
BK19
BK20
BL16
BL17
BL18
BL19
BL20
BL21
BM17
BN17
BJ23
BJ26
BJ27
BK23
BK26
BK27
BL23
BL24
BL25
BL26
BL27
BL28
BM24
BL15
BM16
BL22
BM22
BP15
BR15
BT15
BP16
BR16
BT16
BN15
BM15
BP17
BN16
BM14
BL14
BJ35
BJ36
AT13
AW13
AU13
AY13
BT29
BR25
BP25
SKL_H_BGA_BGA/BGA
2
SKYLAKE_HALO
BGA1440
VCCOPC
VCCOPC
VCCOPC
VCCOPC
VCCOPC
VCCOPC
VCCOPC
VCCOPC
VCCOPC
VCCOPC
VCCOPC
VCCOPC
VCCOPC
VCCOPC
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
VCCOPC_SENSE
VSSOPC_SENSE
RSVD
RSVD
VCCEOPIO
VCCEOPIO
VCCEOPIO
RSVD
RSVD
RSVD
VCCEOPIO_SENSE
VSSEOPIO_SENSE
RSVD
RSVD
VCC_OPC_1P8
VCC_OPC_1P8
RSVD
RSVD
ZVM#
MSM#
ZVM2#
MSM2#
OPC_RCOMP
OPCE_RCOMP
OPCE_RCOMP2
2
10 OF 14
1
REV = 1
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Monday, May 25, 2015
Date: Sheet of
Monday, May 25, 2015
Date: Sheet of
Monday, May 25, 2015
PROJECT :
CPU
CPU
CPU
1
AM9A
AM9A
AM9A
5 57
5 57
5 57
A0
A0
A0
5
PDG V1.0 #546844 page 573 & 574 decoupling capacitor
VCCSA: 220uFx1, 47uFx1, 10uFx10, 1uFx3
VCCIO: 47uFx2, 10uFx3, VDDQ: 22uFx4, 10uFx10
VDDQC: 10uFx1, VCCST:1uFx1, VCCSTG: 1uFx1
VCCPLL: 1uFx1, VCCPLL_OC: 1uFx2,
2/11 47u*1 change
to 22u*2
D D
C C
B B
leverage other BU to optimums capacitor design
+VCCSA
12
C16422U/6.3V/X6S_6
12
C17422U/6.3V/X6S_6
C13010U/6.3V/X6S_4
C13110U/6.3V/X6S_4
C11610U/6.3V/X6S_4
C14310U/6.3V/X6S_4
C14210U/6.3V/X6S_4
2/9 remove 3*10u
22uFx4 Please
near VR
2/11 47u*2 change
to 22u*4, 2pcs NC
C4110U/6.3V/X6S_4
C371U/10V/X6S_4
C951U/10V/X6S_4
C741U/10V/X6S_4
12
C20322U/6.3V/X6S_6
12
12
C618*22U/6.3V/X6S_6_NC
12
C613*22U/6.3V/X6S_6_NC
C19110U/6.3V/X6S_4
C21810U/6.3V/X6S_4
C21710U/6.3V/X6S_4
+VCCIO
U10I
J30
K29
K30
K31
K32
K33
K34
K35
L31
L32
L35
L36
L37
L38
M29
M30
M31
M32
M33
M34
M35
M36
AG12
G15
G17
G19
G21
H15
H16
H17
H19
H20
H21
H26
H27
J15
J16
J17
J19
J20
J21
J26
J27
SKL_H_BGA_BGA/BGA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
SKYLAKE_HALO
BGA1440
S0
S0
9 OF 14
(PLL)
(PLL)
VCCSA_SENSE
VSSSA_SENSE
VCCIO_SENSE
VSSIO_SENSE
S3
VDDQC
VCCPLL_OC
VCCPLL_OC
S3
VCCST
VCCSTG
S0
VCCSTG
S0
VCCPLL
VCCPLL
REV = 1
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
4
EDS V0.92 #544924 page 135~140 power rail
VDDQ: 1.35V/2.8A (DDR3L), 1.2V/2.8A (DDR4/LPDDR3)
VCCSA: 0.55-1.15V/11.1A, VCCIO: 0.95V/5.5A
VCCST: 1.0V/120mA, VCCPLL: 1.0V/145mA
+V_VDDQ
AA6
2/11 22u*2 change to NC
AE12
AF5
AF6
AG5
AG9
AJ12
AL11
AP6
AP7
AR12
AR6
AT12
AW6
AY6
J5
J6
K12
K6
L12
L6
R6
T6
W6
Y12
BH13
G11
H30
H29
G30
H28
J28
M38
M37
H14
J14
1 2
C284 *22U/6.3V/X6S_6_NC
1 2
C383 *22U/6.3V/X6S_6_NC
1 2
C388 22U/6.3V/X6S_6
1 2
C385 22U/6.3V/X6S_6
C320 10U/6.3V/X6S_4
C281 10U/6.3V/X6S_4
C283 10U/6.3V/X6S_4
C280 10U/6.3V/X6S_4
C328 10U/6.3V/X6S_4
C335 10U/6.3V/X6S_4
C380 10U/6.3V/X6S_4
C282 10U/6.3V/X6S_4
C292 10U/6.3V/X6S_4
C381 10U/6.3V/X6S_4
4/31 change to 1u
C290 1U/10V/X6S_4C22722U/6.3V/X6S_6
C340 1U/10V/X6S_4
C300 1U/10V/X6S_4
C168 1U/10V/X6S_4
VCCSTG_R
R22 100/F_4
R30 100/F_4
R46 100/F_4
R47 100/F_4
1 2
R16 *0_6_NC
1 2
R15 0_6
C111 1U/10V/X6S_4
C156 1U/10V/X6S_4
+VCCSA
VCCSA_SENSE 41
VSSSA_SENSE 41
+VCCIO
VCCIO_SENSE 47
VSSIO_SENSE 47
VCCPLL_OC source from VDDQ
EDS V0.92 #544924 P129 note 4 & 5
+VDDQ_CPU_CLK
+V_VDDQ
+VCC_1.00_PP
+VCC_1.00
3
Skylake Processor (POWER)
PROC_TRIGIN14
+VCC_1.00
2/11 change to +VCC_1.00
VCCSTG source from VCCST
EDS V0.92 #544924 P129 note 4 & 5
+VCC_1.00
2/11 change to +VCC_1.00
Debug pin
PROC_TRIGIN
PROC_TRIGOUT_R
2
U10K
D1
RSVD_TP
E1
RSVD_TP
E3
RSVD_TP
E2
RSVD_TP
BR1
RSVD_TP
BT2
RSVD_TP
BN35
RSVD
J24
RSVD
H24
RSVD
BN33
RSVD
BL34
RSVD
N29
RSVD
R14
RSVD
AE29
RSVD
AA14
RSVD
A36
RSVD
A37
RSVD
H23
PROC_TRIGIN
J23
PROC_TRIGOUT
F30
RSVD
E30
RSVD
B30
RSVD
C30
RSVD
G3
RSVD
J3
RSVD
BR35
RSVD
BR31
RSVD
BH30
RSVD
SKL_H_BGA_BGA/BGA
SKYLAKE_HALO
BGA1440
11 OF 14
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
RSVD
RSVD
VSS
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
RSVD
RSVD
RSVD
RSVD
VSS
RSVD_TP
RSVD_TP
RSVD
RSVD
RSVD
NCTF
NCTF
NCTF
NCTF
NCTF
NCTF
REV = 1
1
BM33
BL33
BJ14
BJ13
BK28
BJ28
BJ18
BJ16
BK16
BK24
BJ24
BK21
BJ21
BT17
BR17
BK18
BJ34
BJ33
G13
AJ8
BL31
B2
B38
BP1
BR2
C1
C38
Place near CPU
PROC_TRIGOUT_R PROC_TRIGOUT
R36 30_4
PROC_TRIGOUT 14
VDDQC for SKL - U/Y series, H series left NC.
#550607 reference schematic P18
+VDDQ_CPU_CLK
R49 0_4_
+V_VDDQ
0430 add bom
A A
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Monday, May 25, 2015
Date: Sheet of
Monday, May 25, 2015
Date: Sheet of
5
4
3
2
Monday, May 25, 2015
PROJECT :
CPU
CPU
CPU
1
AM9A
AM9A
AM9A
6 57
6 57
6 57
A0
A0
A0
5
4
PDG V1.0 #546884 P573-574 decupling
47uFx6, 22uFx8, 10uFx35, 1uFx68.
3
2
1
leverage other BU to optimums capacitor design
VCCGT = 55A (QC+GT2)
D D
C274
10U/6.3V/X6S_4
C256
10U/6.3V/X6S_4
C278
1U/10V/X6S_4
C C
C152
1U/10V/X6S_4
C98
1U/10V/X6S_4
B B
A A
C176
10U/6.3V/X6S_4
C55
10U/6.3V/X6S_4
C71
1U/10V/X6S_4
C136
1U/10V/X6S_4
C170
10U/6.3V/X6S_4
10U/6.3V/X6S_4
C76
1U/10V/X6S_4
C134
1U/10V/X6S_4
C73
1U/10V/X6S_4
5
C162
10U/6.3V/X6S_4
C255
10U/6.3V/X6S_4
C133
1U/10V/X6S_4
C132
1U/10V/X6S_4
C145
1U/10V/X6S_4
C102
1U/10V/X6S_4
2/11 change to NC
C273
10U/6.3V/X6S_4
C163
10U/6.3V/X6S_4
C112
1U/10V/X6S_4
C150
1U/10V/X6S_4
C128
1U/10V/X6S_4
C78
1U/10V/X6S_4
+VCCGT
12
C242*22U/6.3V_6_NC
12
C238*22U/6.3V_6_NC
12
C237*22U/6.3V_6_NC
12
C239*22U/6.3V_6_NC
12
C24122U/6.3V_6
12
C18122U/6.3V_6
12
C16922U/6.3V_6
12
C21222U/6.3V_6
C8610U/10V_4
C6110U/10V_4C119
C15410U/10V_4
C25810U/10V_4
C13910U/10V_4
C26710U/10V_4
C6710U/10V_4
C26110U/10V_4
C15310U/10V_4
C5810U/10V_4
C26010U/10V_4
C11310U/10V_4
C9710U/10V_4
C11710U/10V_4
C9610U/10V_4
C9110U/10V_4
C5910U/10V_4
C9910U/10V_4
C11510U/10V_4
C11010U/10V_4
C26810U/10V_4
C5710U/10V_4
C5610U/10V_4
C25910U/10V_4
C11810U/10V_4
C601U/6.3V_4
C2911U/6.3V_4
C721U/6.3V_4
C751U/6.3V_4
C2891U/6.3V_4
C1031U/6.3V_4
C2931U/6.3V_4
C771U/6.3V_4
C941U/6.3V_4
C1351U/6.3V_4
C1441U/6.3V_4
C1091U/6.3V_4
C931U/6.3V_4
C2751U/6.3V_4
C701U/6.3V_4
C871U/6.3V_4
C891U/6.3V_4
C1471U/6.3V_4
C1461U/6.3V_4
C1401U/6.3V_4
C17747U/4V/X6S_8
C16747U/4V/X6S_8
C17947U/4V/X6S_8
C18047U/4V/X6S_8
C16547U/4V/X6S_8
C16647U/4V/X6S_8
4
U10N
AJ29
AJ30
AJ31
AJ32
AJ33
AJ34
AJ35
AJ36
AK31
AK32
AK33
AK34
AK35
AK36
AK37
AK38
AL13
AL29
AL30
AL31
AL32
AL35
AL36
AL37
AL38
AM13
AM14
AM29
AM30
AM31
AM32
AM33
AM34
AM35
AM36
AN13
AN14
AN31
AN32
AN33
AN34
AN35
AN36
AN37
AN38
AP13
AP14
AP29
AP30
AP31
AP32
AP35
AP36
AP37
AP38
AR29
AR30
AR31
AR32
AR33
AR34
AR35
AR36
AT14
AT31
AT32
AT33
AT34
AT35
AT36
AT37
AT38
AU14
AU29
AU30
AU31
AU32
AU35
AU36
AU37
AU38
SKL_H_BGA_BGA/BGA
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
SKYLAKE_HALO
S0
BGA1440
14 OF 14
S0 S0
VCCGT_SENSE
VSSGTX_SENSE
VSSGT_SENSE
VCCGTX_SENSE
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
REV = 1
3
AF29
AF30
AF31
AF32
AF33
AF34
AG13
AG14
AG31
AG32
AG33
AG34
AG35
AG36
AH13
AH14
AH29
AH30
AH31
AH32
AJ13
AJ14
AH38
AH35
AH37
AH36
Skylake Processor (POWER)
VCCGTX is processor w/ GT3/4 power rail.
Pandora support 4+2 Processor.
Rail is unconnected for those pins w/o OPC
#544924 EDS page127 Note2
R21 100/F_4
R24 100/F_4
+VCCGT
VCCGT_SENSE 41
VSSGT_SENSE 41
2
SKYLAKE_HALO
+VCCGT
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
U10H
BG34
VCCGT
BG35
VCCGT
BG36
VCCGT
BH33
VCCGT
BH34
VCCGT
BH35
VCCGT
BH36
VCCGT
BH37
VCCGT
BH38
VCCGT
BJ37
VCCGT
BJ38
VCCGT
BL36
VCCGT
BL37
VCCGT
BM36
VCCGT
BM37
VCCGT
BN36
VCCGT
BN37
VCCGT
BN38
VCCGT
BP37
VCCGT
BP38
VCCGT
BR37
VCCGT
BT37
VCCGT
BE38
VCCGT
BF13
VCCGT
BF14
VCCGT
BF29
VCCGT
BF30
VCCGT
BF31
VCCGT
BF32
VCCGT
BF35
VCCGT
BF36
VCCGT
BF37
VCCGT
BF38
VCCGT
BG29
VCCGT
BG30
VCCGT
BG31
VCCGT
BG32
VCCGT
BG33
VCCGT
BC36
VCCGT
BC37
VCCGT
BC38
VCCGT
BD13
VCCGT
BD14
VCCGT
BD29
VCCGT
BD30
VCCGT
BD31
VCCGT
BD32
VCCGT
BD33
VCCGT
BD34
VCCGT
BD35
VCCGT
BD36
VCCGT
BE31
VCCGT
BE32
VCCGT
BE37
VCCGT
SKL_H_BGA_BGA/BGA
Monday, May 25, 2015
Monday, May 25, 2015
Monday, May 25, 2015
BGA1440
8 OF 14
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
PROJECT :
CPU
CPU
CPU
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
REV = 1
1
+VCCGT
AV29
AV30
AV31
AV32
AV33
AV34
AV35
AV36
AW14
AW31
AW32
AW33
AW34
AW35
AW36
AW37
AW38
AY29
AY30
AY31
AY32
AY35
AY36
AY37
AY38
BA13
BA14
BA29
BA30
BA31
BA32
BA33
BA34
BA35
BA36
BB13
BB14
BB31
BB32
BB33
BB34
BB35
BB36
BB37
BB38
BC29
BC30
BC31
BC32
BC35
BE33
BE34
BE35
BE36
AM9A
AM9A
AM9A
7 57
7 57
7 57
A0
A0
A0
5
4
3
2
1
Skylake Processor (GROUND)
SKYLAKE_HALO
U10F
D D
C C
B B
A A
Y38
Y37
Y14
Y13
Y11
Y10
W34
W33
W12
V30
V29
V12
U38
U37
T34
T33
T14
T13
T12
T11
T10
R30
R29
R12
P38
P37
P12
N34
N33
N12
N11
N10
M14
M13
M12
K38
K11
K10
W5
W4
W3
W2
W1
L34
L33
L30
L29
Y9
Y8
Y7
V6
U6
T9
T8
T7
T5
T4
T3
T2
T1
P6
N9
N8
N7
N6
N5
N4
N3
N2
N1
M6
K9
K8
K7
K5
K4
K3
K2
BGA1440
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
SKL_H_BGA_BGA/BGA
5
6 OF 14
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NCTFVSS
REV = 1
K1
J36
J33
J32
J25
J22
J18
J10
J7
J4
H35
H32
H25
H22
H18
H12
H11
G28
G26
G24
G23
G22
G20
G18
G16
G14
G12
G10
G9
G8
G6
G5
G4
F36
F31
F29
F27
F25
F23
F21
F19
F17
F15
F13
F11
F9
F8
F5
F4
F3
F2
E38
E35
E34
E9
E4
D33
D30
D28
D26
D24
D22
D20
D18
D16
D14
D12
D10
D9
D6
D3
C37
C31
C29
C27
D38
C17
C13
BT32
BT26
BT24
BT21
BT18
BT14
BT12
BT9
BT5
BR36
BR34
BR29
BR26
BR24
BR21
BR18
BR14
BR12
BR7
BP34
BP33
BP29
BP26
BP24
BP21
BP18
BP14
BP12
BP7
BN34
BN31
BN30
BN29
BN24
BN21
BN20
BN19
BN18
BN14
BN12
BN9
BN7
BN4
BN2
BM38
BM35
BM28
BM27
BM26
BM23
BM21
BM13
BM12
BM9
BM6
BM2
BL29
BK29
BK15
BK14
BJ32
BJ31
BJ25
BJ22
BH14
BH12
BH9
BH8
BH5
BH4
BH1
BG38
BG13
BG12
BF33
BF12
BE29
BE6
BD9
BC34
BC12
BB12
4
SKYLAKE_HALO
U10L
VSS
VSS
C9
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
SKL_H_BGA_BGA/BGA
BGA1440
12 OF 14
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NCTFVSS
NCTFVSS
NCTFVSS
NCTFVSS
NCTFVSS
NCTFVSS
REV = 1
C25
C23
C21
C19
C15
C11
C8
C5
BM29
BM25
BM18
BM11
BM8
BM7
BM5
BM3
BL38
BL35
BL13
BL6
BK25
BK22
BK13
BK6
BJ30
BJ29
BJ15
BJ12
BH11
BH10
BH7
BH6
BH3
BH2
BG37
BG14
BG6
BF34
BF6
BE30
BE5
BE4
BE3
BE2
BE1
BD38
BD37
BD12
BD11
BD10
BD8
BD7
BD6
BC33
BC14
BC13
BC6
BB30
BB29
BB6
BB5
C2
BT36
BT35
BT4
BT3
BR38
SKYLAKE_HALO
U10M
BB4
BB3
BB2
BB1
BA38
BA37
BA12
BA11
BA10
BA9
BA8
BA7
BA6
B9
AY34
AY33
AY14
AY12
AW30
AW29
AW12
AW5
AW4
AW3
AW2
AW1
AV38
AV37
AU34
AU33
AU12
AU11
AU10
AU9
AU8
AU7
AU6
AT30
AT29
AT6
AR38
AR37
AR14
AR13
AR5
AR4
AR3
AR2
AR1
AP34
AP33
AP12
AP11
AP10
AP9
AP8
AN30
AN29
AN12
AN6
AN5
AM38
AM37
AM12
AM5
AM4
AM3
AM2
AM1
AL34
AL33
AL14
AL12
AL10
AL9
AL8
AL7
AL4
3
BGA1440
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
SKL_H_BGA_BGA/BGA
13 OF 14
AK30
VSS
AK29
VSS
AK4
VSS
AJ38
VSS
AJ37
VSS
AJ6
VSS
AJ5
VSS
AJ4
VSS
AJ3
VSS
AJ2
VSS
AJ1
VSS
AH34
VSS
AH33
NCTFVSS
NCTFVSS
NCTFVSS
NCTFVSS
NCTFVSS
2
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
REV = 1
AH12
AH6
AG30
AG29
AG11
AG10
AG8
AG7
AG6
AF14
AF13
AF12
AF4
AF3
AF2
AF1
AE34
AE33
AE6
AD30
AD29
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AC38
AC37
AC12
AC6
AC5
AC4
AC3
AC2
AC1
AB34
AB33
AB6
AA30
AA29
AA12
A30
A28
A26
A24
A22
A20
A18
A16
A14
A12
A10
A9
A6
B37
B3
A34
A4
A3
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Monday, May 25, 2015
Date: Sheet of
Monday, May 25, 2015
Date: Sheet of
Monday, May 25, 2015
PROJECT :
CPU
CPU
CPU
1
AM9A
AM9A
AM9A
8 57
8 57
8 57
A0
A0
A0
?
5
4
3
2
1
SPT-H PCH (SPI) SPT-H PCH (DMI/PCIE/USB3/USB2)
SPI_CS0# for 1st SPI device, SPI_CS1# for
D D
second SPI device, SPI_CS3# for TPM.
#546884 PDG (V1.0) page 620
?
U14A
BD17
GPP_A11/PME#
AG15
TP23
TP19
TP28
PCH_SPI_SI
PCH_SPI_SO
PCH_SPI_CS0#
PCH_SPI_CLK
PCH_SPI_CS1#
PCH_SPI_IO2
PCH_SPI_IO3
CAP_LED
+3.3V_SUS
TP27
TP29
TP25
Connector Less Debug Hooks
Routing Guidelines
#546884 PDG (V1.0) page 505
PCH_SPI_SI27
PCH_SPI_SO27
PCH_SPI_CS0#27
PCH_SPI_CLK27
C C
B B
PCH_SPI_CS1#26,27
PCH_SPI_IO227
PCH_SPI_IO327
TP38
THSCR_EN29
CAP_LED31
3/11 KB_DET# move to P10
PCH_TP_INTR#
3/1 add PU 10K
PCH_SPI_IO3
3/2 add PD 100
R148 10K_4
1 2
R174 *100_4_NC
AG14
AF17
AE17
AR19
AN17
BB29
BE30
BD31
BC31
AW31
BC29
BD30
AT31
AN36
AL39
AN41
AN38
AH43
AG44
RSVD
RSVD
RSVD
RSVD
TP2
TP1
SPI0_MOSI
SPI0_MISO
SPI0_CS0#
SPI0_CLK
SPI0_CS1#
SPI0_IO2
SPI0_IO3
SPI0_CS2#
GPP_D1
GPP_D0
GPP_D3
GPP_D2
GPP_D22
GPP_D21
SPT_PCH_H/SKT
SPT-H_PCH
(Primary) (Primary)
1 OF 12
GPP_B13/PLTRST#
GPP_G16/GSXCLK
GPP_G12/GSXDOUT
GPP_G13/GSXSLOAD
GPP_G14/GSXDIN
GPP_G15/GSXSRESET#
GPP_E3/CPU_GP0
GPP_E7/CPU_GP1
GPP_B3/CPU_GP2
GPP_B4/CPU_GP3
GPP_H18/SML4ALERT#
GPP_H17/SML4DATA
GPP_H16/SML4CLK
GPP_H15/SML3ALERT#
GPP_H14/SML3DATA
GPP_H13/SML3CLK
GPP_H12/SML2ALERT#
GPP_H11/SML2DATA
GPP_H10/SML2CLK
INTRUDER#
REV = 1.3
LAN
WLAN
Card Reader
BB27
P43
R39
R36
R42
R41
AF41
AE44
BC23
BD24
BC36
BE34
BD39
BB36
BA35
BC35
BD35
AW35
BD34
BE11
?
PCI_PLTRST#
3/17 change name
R149 0_4
SML4ALERT#
SML4DATA
SML4CLK
SML3ALERT#
SML3DATA
SML3CLK
SML2ALERT#
SML2DATA
SML2CLK
SM_INTRUDER#
R210 *10K_4_NC
R419 *10K_4_NC
R217 *10K_4_NC R413 100/F_4
R205 *10K_4_NC
R199 *10K_4_NC
R196 *10K_4_NC
R423 *10K_4_NC
R192 *10K_4_NC
R188 *10K_4_NC
R406 1M_4
PDG P623->PU 1M ohm
CRB P102->PU 330K ohm
PCIE_RXN537
PCIE_RXP537
PCIE_TXN537
PCIE_TXP537
PCIE_RXN636
PCIE_RXP636
PCIE_TXN636
PCIE_TXP636
PCIE_RXN735
PCIE_RXP735
PCIE_TXN735
PCIE_TXP735
DMI_TXN03
DMI_TXP03
DMI_RXN03
DMI_RXP03
DMI_TXN13
DMI_TXP13
DMI_RXN13
DMI_RXP13
DMI_TXN23
DMI_TXP23
DMI_RXN23
DMI_RXP23
DMI_TXN33
DMI_TXP33
+3V_RTC
DMI_RXN33
DMI_RXP33
PCH_TP_INTR# 31
+3.3V_SUS
SMLINK[4:2] is for Server.
External pull-up resistor is
required???
PCH EDS V1.0 P247&248
#546884 PDG (V1.2) page 224 Device Down
move to device page
#546884 PDG (V1.2) page 226 Mini-Card
move to device page
move to device page
PCIERCOMP_N
PCIERCOMP_P
PCIE_RXN5
PCIE_RXP5
PCIE_TXN5
PCIE_TXP5
PCIE_RXN6
PCIE_RXP6
PCIE_RXN7
PCIE_RXP7
PCIE_TXN7
PCIE_TXP7
DMI_TXN0
DMI_TXP0
DMI_RXN0
DMI_RXP0
DMI_TXN1
DMI_TXP1
DMI_RXN1
DMI_RXP1
DMI_TXN2
DMI_TXP2
DMI_RXN2
DMI_RXP2
DMI_TXN3
DMI_TXP3
DMI_RXN3
DMI_RXP3
PLTRST# Buffer
U14B
L27
DMI_RXN0
N27
DMI_RXP0
C27
DMI_TXN0
B27
DMI_TXP0
E24
DMI_RXN1
G24
DMI_RXP1
B28
DMI_TXN1
A28
DMI_TXP1
G27
DMI_RXN2
E26
DMI_RXP2
B29
DMI_TXN2
C29
DMI_TXP2
L29
DMI_RXN3
K29
DMI_RXP3
B30
DMI_TXN3
A30
DMI_TXP3
B18
PCIE_RCOMPN
C17
PCIE_RCOMPP
H15
PCIE1_RXN/USB3_7_RXN
G15
PCIE1_RXP/USB3_7_RXP
A16
PCIE1_TXN/USB3_7_TXN
B16
PCIE1_TXP/USB3_7_TXP
B19
PCIE2_TXN/USB3_8_TXN
C19
PCIE2_TXP/USB3_8_TXP
E17
PCIE2_RXN/USB3_8_RXN
G17
PCIE2_RXP/USB3_8_RXP
L17
PCIE3_RXN/USB3_9_RXN
K17
PCIE3_RXP/USB3_9_RXP
B20
PCIE3_TXN/USB3_9_TXN
C20
PCIE3_TXP/USB3_9_TXP
E20
PCIE4_RXN/USB3_10_RXN
G19
PCIE4_RXP/USB3_10_RXP
B21
PCIE4_TXN/USB3_10_TXN
A21
PCIE4_TXP/USB3_10_TXP
K19
PCIE5_RXN
L19
PCIE5_RXP
D22
PCIE5_TXN
C22
PCIE5_TXP
G22
PCIE6_RXN
E22
PCIE6_RXP
B22
PCIE6_TXN
A23
PCIE6_TXP
L22
PCIE7_RXN
K22
PCIE7_RXP
C23
PCIE7_TXN
B23
PCIE7_TXP
K24
PCIE8_RXN
L24
PCIE8_RXP
C24
PCIE8_TXN
B24
PCIE8_TXP
SPT_PCH_H/SKT
SPT-H_PCH
DMI
PCIe/USB 3
2 OF 12
USB 2.0
GPP_E9/USB2_OC0#
GPP_E10/USB2_OC1#
GPP_E11/USB2_OC2#
GPP_E12/USB2_OC3#
GPP_F15/USB2_OC4#
GPP_F16/USB2_OC5#
GPP_F17/USB2_OC6#
GPP_F18/USB2_OC7#
USB2_VBUSSENSE
USB2N_1
USB2P_1
USB2N_2
USB2P_2
USB2N_3
USB2P_3
USB2N_4
USB2P_4
USB2N_5
USB2P_5
USB2N_6
USB2P_6
USB2N_7
USB2P_7
USB2N_8
USB2P_8
USB2N_9
USB2P_9
USB2N_10
USB2P_10
USB2N_11
USB2P_11
USB2N_12
USB2P_12
USB2N_13
USB2P_13
USB2N_14
USB2P_14
USB2_COMP
RSVD_AB13
USB2_ID
GPD7/RSVD
?
REV = 1.3
AF5
AG7
AD5
AD7
AG8
AG10
AE1
AE2
AC2
AC3
AF2
AF3
AB3
AB2
AL8
AL7
AA1
AA2
AJ8
AJ7
W2
W3
AD3
AD2
V2
V1
AJ11
AJ13
AD43
AD42
AD39
AC44
Y43
Y41
W44
W43
AG3
AD10
AB13
AG2
BD14
USB2_N1
USB2_P1
USB2_N2
USB2_P2
USB2_N3
USB2_P3
USB2_N4
USB2_P4
USB2_N5
USB2_P5
USB2_N6
USB2_P6
USB_OC0#
USB_OC1#
USB_OC2#
USB_OC3#
USB_OC4#
USB_OC5#
USB_OC6#
USB_OC7#
USBCOMP
TP22
USB2_N1 34
USB2_P1 34
USB2_N2 38
USB2_P2 38
USB2_N3 38
USB2_P3 38
USB2_N4 29
USB2_P4 29
USB2_N5 36
USB2_P5 36
USB2_N6 29
USB2_P6 29
USB_OC0#
USB_OC1#
USB_OC2#
USB_OC3#
USB_OC4#
USB_OC5#
USB_OC6#
USB_OC7#
USB_OC0# 34
USB_OC1# 38
Place near Pin
R382 113/F_4
R120 1K_4
R361 0_4
If this signal is not in use, then it
should have a 1k PD to ground.
#546717 EDS (V1.2) page 288
2/3 add R896,R897
USB3.0 Conn/MB(PS)
USB3.0 Conn / DB
USB3.0 Conn / DB
Camera
BT
Touch Screen
2
RP13 10KX2
RP12 10KX2
RP11 10KX2
RP10 10KX2
1
4
3
2
1
4
3
2
1
4
3
2
1
4
3
+3.3V_SUS
PCI_PLTRST#
A A
5
1 2
R165 *SHORT_4_NC
PLTRST#
R166
100K_4
PLTRST# 17,26,28,35,36,37
4
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Monday, May 25, 2015
Date: Sheet of
Monday, May 25, 2015
Date: Sheet of
3
2
Monday, May 25, 2015
PROJECT :
PCH
PCH
PCH
AM9A
AM9A
AM9A
A0
A0
9 57
9 57
1
9 57
A0
5
+3.3V_RUN
DCR_EN
2/25 modify
KB_DET#
D D
SSD
R428 10K_4
+3.3V_SUS
R429 10K_4
KB_LED_DET31
KB_DET#31
DCR_EN29
BT_RADIO_DIS#36
WLAN_O N/OFF#36
#546884 PDG (V1.2) page 396 NGFF
2/3 Remove to conn page
PCIE_TXP1128
PCIE_TXN1128
PCIE_RXP1128
PCIE_RXN1 128
iAMT used.
WLAN_O N/OFF#
KB_DET#
DCR_EN
3/10 change PCIE port
SATA_TXN02 8
HDD
C C
SSD
SATA_TXP028
SATA_RXN028
SATA_RXP028
PCIE_TXP1228
PCIE_TXN1228
PCIE_RXP1228
PCIE_RXN1 228
SATA_TXN0
SATA_TXP0
SATA_RXN0
SATA_RXP0
PCIE_RXP12
PCIE_RXN1 2
2/3 Remove to conn page
SPT-H PCH (PCIE/SATA/FAN/CLINK) SPT-H PCH (AUDIO/SMBus/JTAG)
?
U14C
AV2
CL_CLK
AV3
CL_DATA
AW2
CL_RST#
R44
GPP_G8/FAN_PWM_0
R43
GPP_G9/FAN_PWM_1
U39
GPP_G10/FAN_PWM_2
N42
GPP_G11/FAN_PWM_3
U43
GPP_G0/FAN_TACH_0
U42
GPP_G1/FAN_TACH_1
U41
GPP_G2/FAN_TACH_2
M44
GPP_G3/FAN_TACH_3
U36
GPP_G4/FAN_TACH_4
P44
GPP_G5/FAN_TACH_5
T45
GPP_G6/FAN_TACH_6
T44
GPP_G7/FAN_TACH_7
B33
PCIE11_TXP
C33
PCIE11_TXN
K31
PCIE11_RXP
L31
PCIE11_RXN
AB33
GPP_F10/SCLOCK
AB35
GPP_F11/SLOAD
AA44
GPP_F13/SDATAOUT0
AA45
GPP_F12/SDATAOUT1
B38
PCIE14_TXN/SATA1B_TXN
C38
PCIE14_TXP/SATA1B_TXP
D39
PCIE14_RXN/SATA1B_RXN
E37
PCIE14_RXP/SATA1B_RXP
C36
PCIE13_TXN/SATA0B_TXN
B36
PCIE13_TXP/SATA0B_TXP
G35
PCIE13_RXN/SATA0B_RXN
E35
PCIE13_RXP/SATA0B_RXP
A35
PCIE12_TXP
B35
PCIE12_TXN
H33
PCIE12_RXP
G33
PCIE12_RXN
J45
PCIE20_TXP/SATA7_TXP
K44
PCIE20_TXN/SATA7_TXN
N38
PCIE20_RXP/SATA7_RXP
N39
PCIE20_RXN/SATA7_RXN
H44
PCIE19_TXP/SATA6_TXP
H43
PCIE19_TXN/SATA6_TXN
L39
PCIE19_RXP/SATA6_RXP
L37
PCIE19_RXN/SATA6_RXN
SPT_PCH_H/S KT
(Primary)
SPT-H_PCH
CLINK
FAN
3 OF 12
Leakage Isolation
+3.3V_SUS
+3.3V_RUN+3.3V_SUS +3 .3V_SUS
2
2
B B
SMB_ME1_ DAT
PCH STRAPING
A A
Pin Name Usage
SPKR / GPP_B14
SMBALERT# / GPP_C2
SML0ALERT# / GPP_C5
HDA_SDO
RP15
2.2KX2
4
1
3
4 3
1
<546717 Rev0.91>
Q28
2N7002KDW
5
2
6
Sampled
Top Swap Override
PCH_PWROK
TLS Confidentiality RSMRST#
eSPI or LPC RSMRST#
Flash Descriptor
Security Override
PCH_PWROK
5
SMBCLK1 26
SMB_PCH_CLKSMB_ME1_ CLK
SMB_PCH_DAT
Configuration
0 = Disable (Default)
1 = Enable
0 = Disable(Default)
1 = Enable (support IAMT and iSBA with iTLS)
0 = LPC Is selected for EC(Default)
1 = eSPI Is selected for EC.
0 = Enable(Default)
1 = Disable (override)
RP16
2.2KX2
4
1
3
4
PCIE9_RXN/SATA0A_RXN
PCIE9_RXP/SATA0A_RXP
PCIE9_TXN/SATA0A_TXN
PCIE9_TXP/SATA0A_TXP
PCIE10_RXN/SATA1A_RXN
PCIE10_RXP/SATA1A_RXP
PCIE10_TXN/SATA1A_TXN
PCIE10_TXP/SATA1A_TXP
PCIE15_RXN/SATA2_RXN
PCIE15_RXP/SATA2_RXP
PCIE15_TXN/SATA2_TXN
PCIE15_TXP/SATA2_TXP
PCIe/SATA
PCIE16_RXN/SATA3_RXN
PCIE16_RXP/SATA3_RXP
PCIE16_TXN/SATA3_TXN
PCIE16_TXP/SATA3_TXP
PCIE17_RXN/SATA4_RXN
PCIE17_RXP/SATA4_RXP
PCIE17_TXN/SATA4_TXN
PCIE17_TXP/SATA4_TXP
PCIE18_RXN/SATA5_RXN
PCIE18_RXP/SATA5_RXP
PCIE18_TXN/SATA5_TXN
PCIE18_TXP/SATA5_TXP
GPP_E0/SATAXPCIE0/SATAGP0
GPP_E1/SATAXPCIE1/SATAGP1
GPP_E2/SATAXPCIE2/SATAGP2
GPP_F0/SATAXPCIE3/SATAGP3
GPP_F1/SATAXPCIE4/SATAGP4
GPP_F2/SATAXPCIE5/SATAGP5
GPP_F3/SATAXPCIE6/SATAGP6
GPP_F4/SATAXPCIE7/SATAGP7
GPP_F21/EDP_BKLTCTL
GPP_F20/EDP_BKLTEN
GPP_F19/EDP_VDDEN
HOST
(Primary)
(Primary)
For DIMMsFor EC
Q27
2N7002KDW
5
43
2
6
1
ACZ_SPKR
SMBALERT#
SML0ALERT#
PCH_MELOCK26
4
GPP_E8/SATALED#
THERMTRIP#
(Primary)
(Primary)
PLTRST_PROC#
PM_DOWN
?
REV = 1.3
+3.3V_RUN
2
4
RP17
2.2KX2
1
3
G31
H31
C31
B31
G29
E29
C32
B32
F41
E41
B39
A39
D43
E42
A41
A40
H42
H40
E45
F45
K37
G37
G45
G44
AD44
AG36
AG35
AG39
AD35
AD31
AD38
AC43
AB44
W36
W35
W42
AJ3
AL3
PECI
AJ4
PM_SYNC
AK2
AH2
SMB_RUN_CL K 15,16
SMB_RUN_DA T 15,16SMBDAT1 26
Circuitry
R175 *1 K_4_NC
R219 *1 K_4_NC
R218 *1 K_4_NC
R140 1K_4
2/3 Remove to conn page
PCIE_RXN9
PCIE_RXP9
PCIE_RXN1 0
PCIE_RXP10
2/3 Remove to conn page
SATALED# 38 IMVP_PW RGD26,41
SATAGP0
SATAGP1
SATAGP2
SATAGP3
M.2_DET 28
M.2 DET
H = PCIE
L = SATA
PCH_THERMTRIP# _R
PCH_PECI
H_PM_SYNC_R
CPU_PLTRST#
H_PM_DOW N
R383 620_4
R364 13/F_4
R363 30_4
PECI: RPCH=13 ohm (PDG P215)CRB 12.1 ohms (P48)
TP85
RTC Circuitry
+3V_RTC
R401 30K/F_4
R403 30K/F_4
PDG #546884 p623 (P369)
The recommended values for resistor and capacitor
are 20 K and 1.0 µF.
CRB p102 PU 30.1K_1%
+3.3V_RUN
+3.3V_SUS
+3.3V_SUS
HDA_SDO_R
3
2/10 add HDA RS
3/16 NC
Mobile HDA codec didn't need
reset signal control from host
PCIE_RXN9 28
PCIE_RXP9 28
PCIE_TXN9 28
PCIE_TXP9 28
PCIE_RXN1 0 28
PCIE_RXP10 28
PCIE_TXN10 28
PCIE_TXP10 28
DSW_PWROK tied together with RSMRST#
for platform no support deep Sx
#546717 EDS V1.0 P196
TP83
Connector Less Debug Hooks
Routing Guidelines
#546884 PDG (V1.0) page 505
EDP_BKLTCTL 29
EDP_BKLTEN 26,29
EDP_VDDEN 29
PCH_THERMTRIP# 4
H_PECI 4,26
H_PM_SYNC 4
CPU_PLTRST# 4
H_PM_DOW N 4
EDS #546717 P220
Layout note:
30mils
RTCRST: It is imperative that this signal not
be pulled low in the S0 to S5 states.
RTC_RST#
C686
1U/10V/X5R_4
SRTC_RST#
EDS #546717 P220
SRTCRST: The only time this signal gets asserted (driven low in
C687
combination with RTCRST#) should be when the coin cell battery is
1U/10V/X5R_4
removed or not installed and the platform is in the G3 state. It
is imperative that this signal not be pulled low in the S0 to S5
states.
3/10 add
5/21 change to 47 ohm
HDA_BITCLK38
HDA_RST#38
HDA_SDIN038
SSD
HDA_SDOUT38
HDA_SYNC38
AUD_AZACP U_SDO3
AUD_AZACP U_SDI3
AUD_AZACP U_SCLK3
GC6_FB_E N20
GPU_EVENT#20
2/25 Add schottky diode
RSMRST#26
TP21
PCH_SYS_RE SET#
PCH_THERMTRIP#
#546884 PDG page214
31
3/1 add
LAN_WA KE#
R402 10K_4
SATAGP0
R212 *10K_4_NC
SATAGP1
R215 *10K_4_NC
SATAGP2
R213 *10K_4_NC
SATAGP3
R216 *10K_4_NC
R119 47_4
R126 *3 3_4_NC
R145 33_4
R124 33_4
Place near PCH
PDG V1.0 P351
AUD_AZACP U_SDO_R
R360 30_4
AUD_AZACP U_SDI
AUD_AZACP U_SCLK_R
R386 30_4
2 1
D8 SDM10K45 -7-F
R144 0_4
R130 0_4
R129 0_4
For PHY
For EC
Q24
*2N7002W _NC
2
+3.3V_SUS
EMI
AUD_AZACP U_SCLK
HDA_BITCLK
5/21 change to 47P
3
EC21 *10 P/50V_4_NC
EC22 47P/50V_4
U14D
HDA_BCLK_R
BA9
HDA_RST#_R
HDA_SDO_R
HDA_SYNC_R
RTC_RST#
SRTC_RST#
PCH_PWROK
PCH_RSMRST#
PCH_DPW ROK
SMBALERT#
SMB_PCH_CLK
SMB_PCH_DAT
SML0ALERT#
SMB_ME0_ CLK
SMB_ME0_ DAT
SML1ALERT#
SMB_ME1_ CLK
SMB_ME1_ DAT
EC_RTC_RST 26
HDA_BCLK
BD8
HDA_RST#
BE7
HDA_SDI0
BC8
HDA_SDI1
BB7
HDA_SDO
BD9
HDA_SYNC
BD1
RSVD_BD1
BE2
RSVD_BE2
AM1
DISPA_SDO
AN2
DISPA_SDI
AM2
DISPA_BCLK
AL42
GPP_D8/I2S0_SCLK
AN42
GPP_D7/I2S0_RXD
AM43
GPP_D6/I2S0_TXD
AJ33
GPP_D5/I2S0_SFRM
AH44
GPP_D20/DMIC_DATA0
AJ35
GPP_D19/DMIC_CLK0
AJ38
GPP_D18/DMIC_DATA1
AJ42
GPP_D17/DMIC_CLK1
BC10
RTCRST#
BB10
SRTCRST#
AW11
PCH_PWROK
BA11
RSMRST#
AV11
DSW_PWROK
BB41
GPP_C2/SMBALERT#
AW44
GPP_C0/SMBCLK
BB43
GPP_C1/SMBDATA
BA40
GPP_C5/SML0ALERT#
AY44
GPP_C3/SML0CLK
BB39
GPP_C4/SML0DATA
AT27
GPP_B23/SML1ALERT#/PCHHOT#
AW42
GPP_C6/SML1CLK
AW45
GPP_C7/SML1DATA
SPT_PCH_H/S KT
SMBUS Alert had internal PD
Default is GPO and driven low after RSMRST#
PCH_THERMTRIP#
#546884 PDG page213
CRB PCH_PECI PD(NC)
#550607 CRB page48
PM_DOWN PD(NC) to GND
#546884 PDG page216 (V1.0)
2/9 PCH_PWROK add PD
#546884 PDG page216 (V1.0)
EC_PWRBTN# internally pulled-up
in PCH to VCCDSW_3p3 through a
weak pull-up resistor (15 kΩ to 40 kΩ).
WAKE# PU 10K to VCCDSW3.3
#546884 PDG P.627 (V1.0)
BATLOW 8.2K-10K# PU to DSW well
#546884 PDG P.627 (V1.0)
(RTC)
(Primary)
(Primary)
(RTC)
(RTC)
2
?
SPT-H_PCH
GPP_A12/BMBUSY#/ISH_GP6/SX_EXIT_HOLDOFF#
(Primary)
AUDIO
(Primary)
(Primary)
(Primary)
SMBUS
(Primary)
4 OF 12
PCH PU/PD setting
2/9 change to +VCC_1.00
PCH_THERMTRIP#
PCH_PECI
H_PM_DOW N
PCH_RSMRST#
PCH_PWROK
PCH_DPW ROK
3/3 DSW_PWROK add PD
#546884 PDG page375 (V1.0)
SMB_ME0_ CLK
SMB_ME0_ DAT
EC_PWRBTN#
PCH_WAKE#
PCH_BATLOW #
AC_PRESE NT
3/5 change net name
2
S0 Sleep Control: When PCH is idle and processor is
in C10 state, this pin will assert to indicate VR
controller can go into a light load mode.
This signal can also be connected to EC for other
power management related optimizations.
GPP_A8/CLKRUN#
(DSW)
GPD11/LANPHYPC
(DSW)
GPD9/SLP_WLAN#
(DSW)
DRAM_RESET#
GPP_B2/VRALERT#
GPP_G17/ADR_COMPLETE
GPP_B11
(Primary)
SYS_PWROK
(DSW)
(DSW)
GPD6/SLP_A#
(DSW)
(DSW)
(DSW)
(DSW)
(DSW)
(DSW)
(DSW)
(DSW)
(DSW)
(Primary)
(Primary)
(Primary)
+3.3V_SUS
3
1
GPP_B12/SLP_S0#
GPD4/SLP_S3#
GPD5/SLP_S4#
GPD10/SLP_S5#
GPD8/SUSCLK
GPD0/BATLOW#
GPP_A15/SUSACK#
GPD2/LAN_WAKE#
GPD1/ACPRESENT
(DSW)
GPD3/PWRBTN#
SYS_RESET#
GPP_B14/SPKR
PROCPWRGD
+VCC_1.00
SLP_LAN#
SLP_SUS#
ITP_PMODE
JTAG_TMS
JTAG_TDO
JTAG_TDI
JTAG_TCK
REV = 1.3
0430 change to 100K
(Primary)
(Primary)
GPP_A13/SUSWARN#/SUSPWRDNACK
JTAG
R362 1K_4
R385 *1 0K_4_NC
R384 *0 _4_NC
R127 *1 0K_4_NC
R137 100K_4
R131 100K_4
RP9 2. 2KX2
4
2
2/9 change to NC
R134 *1 0K_4_NC
R405 10K_4
R407 10K_4
R408 10K_4
R409 *1 00K_4_NC
1
BB17
AW22
CLKRUN#
AR15
SLP_W LAN#
AV13
PCH_DRAMRST#
BC14
GPP_B2
BD23
AL27
GPP_B1
AR27
GPP_B0
N44
AN24
SYS_PWROK
AY1
PCH_WAKE#
BC13
WAKE#
SLP_A#
BC15
SLP_LAN#
AV15
BC26
AW15
BD15
BA13
PCH_SUSCL K
AN15
PCH_BATLOW #
BD13
SUSACK left NC if no support DEEP Sx PDG V1.0 #546884 P364
BB19
SUS_PW R_ACK
BD19
LAN_WA KE#
BD11
AC_PRESE NT
BB15
SLP_SUS left NC if no support DEEP Sx PDG V1.0 #546884 P197
BB13
EC_PWRBTN#
AT13
PCH_SYS_RE SET#
AW1
BD26
AM3
ITP_PMODE
AT2
PROC_TCK
AR3
JTAGX
PROC_TMS
AR2
PROC_TDO
AP1
PROC_TDI
AP2
PCH_JTAG_TCK
AN3
?
Connector Less Debug Hooks Routing Guidelines
#546884 PDG (V1.0) page 505
PROC_TDO
PROC_TDI
PROC_TMS
PROC_TCK
3/1 change to +3.3V_RUN
3/16 change to +3.3V_RUN
5/18 change to non-pop
PROC_TDO
CLKRUN# 26
TP20
PCH_DRAMRST# 16
R367 0_4
2/9 remove off page conn
TP92
TP24
TP26
SUS_PW R_ACK 26
TP89
TP87
TP84
TP88
TP82
PROC_TDO 4
PROC_TDI 4
PROC_TMS 4
PROC_TCK 4
CLKRUN#
GPP_B2
3/16 add PU 10K
PCH_SYS_RE SET#
SML1ALERT#
R412 8.2K_4
R411 10K_4
R366 8.2K_4
R160 *10K_4_NC
2/9 Remove R189 double PU
R365 *51_4_NC
Near the PCH JTAG_TDO pin
EC_PWROK 26,33
SIO_SLP_S0#
to EC or VR?
SLP_S0# 47
SIO_SLP_S3# 26,46
SIO_SLP_S4# 26
SIO_SLP_S5# 26,46
AC_PRESE NT 26
EC_PWRBTN# 26
ACZ_SPKR 38
H_PWRGOOD 4
TP56
2/11 add TP
+3.3V_RUN
+3.3V_SUS
+VCC_1.00
2/4 move R841 to PCH JTAG page
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Num ber Rev
Size Document Num ber Rev
Size Document Num ber Rev
Date: Sheet of
Monday, May 25, 2 015
Date: Sheet of
Monday, May 25, 2 015
Date: Sheet of
Monday, May 25, 2 015
PROJECT :
PCH
PCH
PCH
1
AM9A
AM9A
AM9A
10 57
10 57
10 57
A0
A0
A0
5
4
3
2
1
U14E
HPD: 3.3V Tolerant
INT_HDMI_HPD30
D D
EDP_HPD29
PCH STRAPING
C C
DDPB_CTRLDATA/GPP_I6
DDPC_CTRLDATA/GPP_I8
DDPD_CTRLDATA/GPP_I10
INT_HDMI_HPD
EDP_HPD
<546717 Rev0.91>
Display Port B Detected PCH_PWROK
Display Port C Detected PCH_PWROK
Display Port D Detected PCH_PWROK
AW4
GPP_I0/DDPB_HPD0
AY2
GPP_I1/DDPC_HPD1
AV4
GPP_I2/DDPD_HPD2
BA4
GPP_I3/DDPE_HPD3
BD7
GPP_I4/EDP_HPD
SPT_PCH_H/SKT
(Primary)
Sampled Configuration CircuitryPin Name Usage
SPT-H PCH (USB3/LPC/eSPI)
USB3_TXN134
USB3.0 CONN/MB(PS)
B B
USB3.0 CONN / DB
USB3_TXP134
USB3_RXN134
USB3_RXP134
USB3_TXN238
USB3_TXP238
USB3_RXN238
USB3_RXP238
3/16 net name exchange
USB3.0 CONN / DB
A A
5
USB3_TXN338
USB3_RXP338
USB3_RXN338
USB3_TXN1
USB3_TXP1
USB3_RXN1
USB3_RXP1
USB3_TXN2
USB3_TXP2
USB3_RXN2
USB3_RXP2
USB3_TXP3
USB3_TXN3
USB3_RXP3
USB3_RXN3
U14F
C11
USB3_1_TXN
B11
USB3_1_TXP
B7
USB3_1_RXN
A7
USB3_1_RXP
B12
USB3_2_TXN
A12
USB3_2_TXP
C8
USB3_2_RXN
B8
USB3_2_RXP
B15
USB3_6_TXN
C15
USB3_6_TXP
K15
USB3_6_RXN
K13
USB3_6_RXP
B14
USB3_5_TXN
C14
USB3_5_TXP
G13
USB3_5_RXN
H13
USB3_5_RXP
D13
USB3_3_TXP
C13
USB3_3_TXN
A9
USB3_3_RXP
B10
USB3_3_RXN
B13
USB3_4_TXP
A14
USB3_4_TXN
G11
USB3_4_RXP
E11
USB3_4_RXN
SPT_PCH_H/SKT
4
USB
?
SPT-H_PCH
GPP_I7/DDPC_CTRLCLK
(Primary)
0 = Port B is not detected. (Default)
1 = Port B is detected.
0 = Port C is not detected. (Default)
1 = Port C is detected.
0 = Port D is not detected. (Default)
1 = Port D is detected.
?
SPT-H_PCH
LPC/eSPI
(Primary)
GPP_I8/DDPC_CTRLDATA
GPP_I5/DDPB_CTRLCLK
GPP_I6/DDPB_CTRLDATA
GPP_I9/DDPD_CTRLCLK
GPP_I10/DDPD_CTRLDATA
5 OF 12
GPP_A1/LAD0/ESPI_IO0
GPP_A2/LAD1/ESPI_IO1
GPP_A3/LAD2/ESPI_IO2
GPP_A4/LAD3/ESPI_IO3
GPP_A5/LFRAME#/ESPI_CS0#
GPP_A6/SERIRQ/ESPI_CS1#
GPP_A7/PIRQA#/ESPI_ALERT0#
GPP_A0/RCIN#/ESPI_ALERT1#
GPP_A14/SUS_STAT#/ESPI_RESET#
GPP_A9/CLKOUT_LPC0/ESPI_CLK
GPP_A10/CLKOUT_LPC1
SATA
6 OF 12
GPP_F14
GPP_F23
GPP_F22
GPP_G23
GPP_G22
GPP_G21
GPP_G20
GPP_H23
?
REV = 1.3
GPP_G19/SMI#
GPP_G18/NMI#
GPP_E6/DEVSLP2
GPP_E5/DEVSLP1
GPP_E4/DEVSLP0
GPP_F9/DEVSLP7
GPP_F8/DEVSLP6
GPP_F7/DEVSLP5
GPP_F6/DEVSLP4
GPP_F5/DEVSLP3
REV = 1.3
3
?
2/9 change net
BB3
DDPC_CTRL_DATA
BD6
HDMI_SCL
BA5
HDMI_SDA
BC4
BE5
DDPD_CTRL_DATA
BE6
Y44
V44
W39
L43
L44
U35
R35
BD36
HDMI_SCL
HDMI_SDA
DDPC_CTRL_DATA
DDPD_CTRL_DATA
AT22
AV22
AT19
BD16
BE16
BA17
AW17
AT17
BC18
BC17
AV19
M45
N43
AE45
AG43
AG42
AB39
AB36
AB43
AB42
AB41
4
2
RP8 2.2KX2
R387 *1K_4_NC
R395 *1K_4_NC
IRQ_SERIRQ
PCI_PIRQA#
EC_RCIN#
SUS_STAT#
CLKOUT_LPC0
CLKOUT_LPC1
3/10 change for BIOS
R229 *0_4_NC
3/3 NC
HDMI_SCL 30
HDMI_SDA 30
#546884 PDG page170 (V1.0)
3
1
R410 22_4
F1 22_4
+3.3V_RUN
+3.3V_RUN
+3.3V_RUN
2/3 MP Remove
For HDMI
LPC_LAD0 26,36
LPC_LAD1 26,36
LPC_LAD2 26,36
LPC_LAD3 26,36
LPC_LFRAME# 26,36
IRQ_SERIRQ 26
EC_RCIN# 26
TP30
CLK_24M_EC 26
CLK_24M_DEBUG 36
SIO_EXT_SCI# 26USB3_TXP338
SMC_EXTSMI# 26
DEVSLP0 28
2
RP14
10KX2
+3.3V_RUN
+3.3V_RUN
1
3
#546884 PDG page629 (V1.0)
IRQ_SERIRQ
PCI_PIRQA#
EC_RCIN#
R156 10K_4
R152 10K_4
R147 10K_4
2/9 add PU 10K
SMC_EXTSMI#
SIO_EXT_SCI#
2
4
EMI
CLK_24M_EC
CLK_24M_DEBUG
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Monday, May 25, 2015
Date: Sheet of
Monday, May 25, 2015
Date: Sheet of
Monday, May 25, 2015
PCH
PCH
PCH
EC83 *10P/50V_4_NC
EC23 *10P/50V_4_NC
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
PROJECT :
1
AM9A
AM9A
AM9A
11 57
11 57
11 57
A0
A0
A0
5
Skylake PCH (CLOCK)
D D
CPU_24MHZ_CLKP4
CPU_24MHZ_CLKN4
CLK_CPU_BCLKP4
CLK_CPU_BCLKN4
+VCCPRIM_1P0
CLK_PEGA_REQ#17
PCIE_CLKREQ_LAN#37
PCIE_CLKREQ_WLAN#36
C C
B B
PCIE_CLKREQ_CR#35
PCIE_CLKREQ_SSD#28
R390 *SHORT_4_NC
R389 *SHORT_4_NC
R375 *SHORT_4_NC
R370 *SHORT_4_NC
R380 2.71K/F_4
SLKREQ# can floating if no used
PDG(#546884) V1.0 p619
CPU_24MHZ_CLKP_R
CPU_24MHZ_CLKN_R
CLK_CPU_BCLKP_R
CLK_CPU_BCLKN_R
XTAL24_OUT
XTAL24_IN
XCLK_BIASREF
RTC_X1
RTC_X2
CLK_PEGA_REQ#
5/18 change to short pad
U14G
AR17
GPP_A16/CLKOUT_48
G1
CLKOUT_CPUNSSC_P
F1
CLKOUT_CPUNSSC
G2
CLKOUT_CPUBCLK_P
H2
CLKOUT_CPUBCLK
A5
XTAL24_OUT
A6
XTAL24_IN
E1
XCLK_BIASREF
BC9
RTCX1
BD10
RTCX2
BC24
GPP_B5/SRCCLKREQ0#
AW24
GPP_B6/SRCCLKREQ1#
AT24
GPP_B7/SRCCLKREQ2#
BD25
GPP_B8/SRCCLKREQ3#
BB24
GPP_B9/SRCCLKREQ4#
BE25
GPP_B10/SRCCLKREQ5#
AT33
GPP_H0/SRCCLKREQ6#
AR31
GPP_H1/SRCCLKREQ7#
BD32
GPP_H2/SRCCLKREQ8#
BC32
GPP_H3/SRCCLKREQ9#
BB31
GPP_H4/SRCCLKREQ10#
BC33
GPP_H5/SRCCLKREQ11#
BA33
GPP_H6/SRCCLKREQ12#
AW33
GPP_H7/SRCCLKREQ13#
BB33
GPP_H8/SRCCLKREQ14#
BD33
GPP_H9/SRCCLKREQ15#
R13
CLKOUT_PCIE_N15
R11
CLKOUT_PCIE_P15
P1
CLKOUT_PCIE_N14
R2
CLKOUT_PCIE_P14
W7
CLKOUT_PCIE_N13
Y5
CLKOUT_PCIE_P13
U2
CLKOUT_PCIE_N12
U3
CLKOUT_PCIE_P12
SPT_PCH_H/SKT
24 MHz crystal
100 MHz CPU
32.768MHz
?
SPT-H_PCH
100 MHz PCIe
(Primary)
7 OF 12
4
CLKOUT_ITPXDP
CLKOUT_ITPXDP_P
CLKOUT_CPUPCIBCLK
CLKOUT_CPUPCIBCLK_P
CLKOUT_PCIE_N0
CLKOUT_PCIE_P0
CLKOUT_PCIE_N1
CLKOUT_PCIE_P1
CLKOUT_PCIE_N2
CLKOUT_PCIE_P2
CLKOUT_PCIE_N3
CLKOUT_PCIE_P3
CLKOUT_PCIE_N4
CLKOUT_PCIE_P4
CLKOUT_PCIE_N5
CLKOUT_PCIE_P5
CLKOUT_PCIE_N6
CLKOUT_PCIE_P6
CLKOUT_PCIE_N7
CLKOUT_PCIE_P7
CLKOUT_PCIE_N8
CLKOUT_PCIE_P8
CLKOUT_PCIE_N9
CLKOUT_PCIE_P9
CLKOUT_PCIE_N10
CLKOUT_PCIE_P10
CLKOUT_PCIE_N11
CLKOUT_PCIE_P11
?
REV = 1.3
L1
L2
PCI_CLK_CPU_BCLKN_R
J1
PCI_CLK_CPU_BCLKP_R
J2
N7
N8
L7
L5
D3
F2
E5
G4
D5
E6
D8
D7
R8
R7
U5
U7
W10
W11
N3
N2
P3
P2
R3
R4
R391 *SHORT_4_NC
R388 *SHORT_4_NC
CLK_PCIE_VGAN 17
CLK_PCIE_VGAP 17
CLK_PCIE_LANN 37
CLK_PCIE_LANP 37
CLK_PCIE_WLANN 36
CLK_PCIE_WLANP 36
CLK_PCIE_CRN 35
CLK_PCIE_CRP 35
CLK_PCIE_SSD0N 28
CLK_PCIE_SSD0P 28
3
PCI_CLK_CPU_BCLKN 4
PCI_CLK_CPU_BCLKP 4
DGPU
LAN
WLAN
Card Reader
M.2 SSD
3/4 del TP
3/4 add TP
TP96
TP97
TP41
TP95
PCH_I2C_CLK_TP31
PCH_I2C_DAT_TP31
3/11 move to GPP_G2
2
LPSS_GSPI1_MOSI
LPSS_GSPI0_MOSI
UART2_CTS#
UART2_RTS#
UART2_TX
UART2_RX
CLK_PEGA_REQ#
2/25 modify, 3/2 change to +3.3V_RUN
PCH_I2C_CLK_TP
PCH_I2C_DAT_TP
U14K
AT29
GPP_B22/GSPI1_MOSI
AR29
GPP_B21/GSPI1_MISO
AV29
GPP_B20/GSPI1_CLK
BC27
GPP_B19/GSPI1_CS#
BD28
GPP_B18/GSPI0_MOSI
BD27
GPP_B17/GSPI0_MISO
AW27
GPP_B16/GSPI0_CLK
AR24
GPP_B15/GSPI0_CS#
AV44
GPP_C9/UART0_TXD
BA41
GPP_C8/UART0_RXD
AU44
GPP_C11/UART0_CTS#
AV43
GPP_C10/UART0_RTS#
AU41
GPP_C15/UART1_CTS#/ISH_UART1_CTS#
AT44
GPP_C14/UART1_RTS#/ISH_UART1_RTS#
AT43
GPP_C13/UART1_TXD/ISH_UART1_TXD
AU43
GPP_C12/UART1_RXD/ISH_UART1_RXD
AN43
GPP_C23/UART2_CTS#
AN44
GPP_C22/UART2_RTS#
AR39
GPP_C21/UART2_TXD
AR45
GPP_C20/UART2_RXD
AR41
GPP_C19/I2C1_SCL
AR44
GPP_C18/I2C1_SDA
AR38
GPP_C17/I2C0_SCL
AT42
GPP_C16/I2C0_SDA
AM44
GPP_D4/ISH_I2C2_SDA/I2C3_SDA
AJ44
GPP_D23/ISH_I2C2_SCL/I2C3_SCL
SPT_PCH_H/SKT
+3.3V_RUN
R115 10K_4
+3.3V_SUS
R220 1K_4
R221 1K_4
2/9 add PU, 2/11 change to 1K
UART2_CTS#
UART2_RTS#
UART2_TX
UART2_RX
R431 49.9K/F
R430 49.9K/F
R222 49.9K/F
R432 49.9K/F
?
SPT-H_PCH
(Primary)
GPP_D16/ISH_UART0_CTS#
(Primary)
(Primary)
11 OF 12
GPP_D15/ISH_UART0_RTS#
GPP_H20/ISH_I2C0_SCL
GPP_H19/ISH_I2C0_SDA
GPP_H22/ISH_I2C1_SCL
GPP_H21/ISH_I2C1_SDA
GPP_A23/ISH_GP5
GPP_A22/ISH_GP4
GPP_A21/ISH_GP3
GPP_A20/ISH_GP2
GPP_A19/ISH_GP1
GPP_A18/ISH_GP0
GPP_A17/ISH_GP7
GPP_D14/ISH_UART0_TXD/SML0BCLK/I2C2_SCL
GPP_D13/ISH_UART0_RXD/SML0BDATA/I2C2_SDA
(Primary)
2/25 reference AM9
DGPU_HOLD_RST#
DGPU_PWR_EN
DGPU_PWROK
3/16 add PU 10K
GPP_D9
GPP_D10
GPP_D11
GPP_D12
?
REV = 1.3
R167 *10K_4_NC
R169 10K_4
R427 10K_4
R197 *10K_4_NC
R164 10K_4
AL44
AL36
AL35
AJ39
AJ43
AL43
AK44
AK45
BC38
BB38
BD38
BE39
BC22
BD18
BE21
BD22
BD21
BB22
BC19
1
+3.3V_RUN
DGPU_PWR_EN 50
DGPU_PWROK 17,51
DGPU_HOLD_RST# 17
3/10 reserve for UART2
PCH STRAPING
RTC Clock 32.768KHz24MHz
C679 12P/50V/_4
4
A A
XTAL24_IN
XTAL24_OUT
3
R392
1M_4
5
Y3
24MHz
1
2
C680 12P/50V/_4
C683 15P/50V/_4
C685 15P/50V/_4
12
4
Y4
32.768KHZ
RTC_X1
R400
10M_4
RTC_X2
3
GSPI0_MOSI/GPP_B18 No Reboot PCH_PWROK
GSPI1_MOSI/GPP_B22 Boot BIOS Strap Bit BBS PCH_PWROK
<546717 Rev0.91>
Sampled Configuration CircuitryPin Name Usage
0 = Disable(Default)
1 = Enable
Bit6 Boot BIOS Destination
0 SPI(Default)
1 LPC
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
LPSS_GSPI0_MOSI
LPSS_GSPI1_MOSI
Monday, May 25, 2015
Monday, May 25, 2015
Monday, May 25, 2015
R414 *1K_4_NC
R168 *1K_4_NC
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
PROJECT :
PCH
PCH
PCH
1
AM9A
AM9A
AM9A
12 57
12 57
12 57
+3.3V_SUS
+3.3V_SUS
A0
A0
A0
5
4
3
2
1
Skylake PCH (POWER)
+VCCPRIM_1P0
C510
D D
VCCCLK1 = 21mA
VCCCLK2 = 137mA
VCCCLK3 = 50mA
VCCCLK4 = 20mA
VCCCLK5 = 6mA
VCCMPHY_1p0 = 2.072A
DMI = 700mA
USB3x3 = 396mA
PCIE3 x 4(SSD) = 616mA
SATA = 54mA
PCIE2 x 3 (WiFi/LAN/CR) = 306mA
C C
VCCAMPHYPLL_1p0 = 80mA
VCCMIPIPLL_1p0 = 30mA
1U/6.3V_4
VCCAPLLEBB_1p0 = 30mA
VCCUSB2PLL_1p0 = 12mA
VCCHDAPLL_1p0 = 33mA
VCCDSW_3p3 = 204mA
VCCDSW_3P3 tie to VCCPRIM_3p3 if
Deep Sx is not supported on the
platform, PDG V1.0(#546884) P448
C500
22U/6.3V_6
1 2
+VCCPRIM_1P0
Place close
pin K2, K3
+VCCMPHY_1P0
Place close pin
U21,U23,U25,U26,V26
+VCCMPHY_1P0
+VCCPRIM_1P0
+VCCPRIM_1P0
+VCCPRIM_1P0
+VCCPRIM_1P0
+VCCHDA
+3.3V_SUS
VCCPRIM_1P0 = 2.899A
+VCCPRIM_1P0+VCC_1.00
R184 0_1206
R185 0_1206
DCPDSW_1P0l is generated by on die DSW
voltage regulator to supply DSW GPIOs,
DSW core logic and DSW USB 2.0 logic.
PCH EDS V1.0(#546717) P51
Place close pin W15
C511 1U/6.3V_4
R143 0_4
R153 0_4
R154 0_4
R142 0_4
R381 0_6
C678 1U/6.3V_4
C677 *22U/6.3V_6_NC
C501 1U/6.3V_4
C505 22U/6.3V_6
R208 0_6
Place close pin A43,B43
C519 1U/6.3V_4
C516 *47U/6.3V_8_NC
R187 0_6 C494
R155 0_6
R121 0_6
R158 0_6
C493 *22U/6.3V_6_NC
12
R455 0_6
1U/6.3V_4
C491
DCPDSW_1P0
VCCCLK1
VCCCLK3
VCCCLK4
VCCCLK2
VCCCLK5
12
12
+VCCAMPHYPLL_1P0
+VCCAPLLEBB_1P0
+VCCDUSB_1P0
+VCCAUSB_1P0_L
+VCCAAZPLL_1P0_L
12
0.1U/25V_4
DSW 3.3V
12
C749
1.0V
S3
2.899A
(DSW)
238mA
1.0V
(PLL)
(HDA)
(DSW)
(PLL)
(PLL)
(PLL)
SPT-H_PCH
CORE
CLK
MPHY
(PLL)
USB
8 OF 12
U14H
AA23
VCCPRIM_1P0
AA26
VCCPRIM_1P0
AA28
VCCPRIM_1P0
AC23
VCCPRIM_1P0
AC26
VCCPRIM_1P0
AC28
VCCPRIM_1P0
AE23
VCCPRIM_1P0
AE26
VCCPRIM_1P0
Y23
VCCPRIM_1P0
Y25
VCCPRIM_1P0
BA29
DCPDSW_1P0
N17
VCCCLK1
R19
VCCCLK3
U20
VCCCLK4
V17
VCCCLK2
R17
VCCCLK2
K2
VCCCLK5
K3
VCCCLK5
U21
VCCMPHY_1P0
U23
VCCMPHY_1P0
U25
VCCMPHY_1P0
U26
VCCMPHY_1P0
V26
VCCMPHY_1P0
A43
VCCAMPHYPLL_1P0_A43
B43
VCCAMPHYPLL_1P0_B43
C44
VCCMIPIPLL_1P0_C44
C45
VCCMIPIPLL_1P0_C45
V28
VCCAPLLEBB_1P0
AC17
VCCPRIM_1P0
AJ5
VCCUSB2PLL_1P0
AL5
VCCUSB2PLL_1P0
AN19
VCCHDAPLL_1P0
BA15
VCCHDA
W15
VCCDSW_3P3
C492
SPT_PCH_H/SKT
0.1U/25V_4
1.0V
(HDA)
3/10 add o.1u close BA15
?
Fuse
(DSW)
VCCGPIO
GPIO
3.3V/1.8V
Thermal Sensor
3.3V
RTC
1.0V
Core
SPI
GPIO
3.3V/1.8V
Fuse
3.3V
VCCPRIM_1P0
VCCDSW_3P3
VCCPGPPA
VCCPGPPBCH
VCCPGPPBCH
VCCPGPPEF
VCCPGPPEF
VCCPGPPG
VCCPRIM_3P3
VCCPRIM_1P0
3.3V
VCCATS
VCCRTCPRIM_3P3
VCCRTC
DCPRTC
VCCPRIM_1P0
VCCPRIM_1P0
VCCPRIM_1P0
VCCPRIM_1P0
3.3V
VCCSPI
VCCSPI
VCCSPI
VCCPGPPD
VCCPGPPD
VCCPGPPD
VCCPGPPD
VCCPRIM_3P3
VCCPRIM_3P3
VCCPRIM_3P3
?
REV = 1.3
5/14 add C749(0.1u) and (R455)0 ohm for EMI
5/18 R158 and R455 to 0402 size
B B
5/25 R158 and R455 to 0603 size, footprint is 0603
Power Rating refernce EDS V1.0 #546717 P59-60
Power decoupling capacitor reference PDG V1.0 #546884 P578-579
+VCCFHV_2P8
AL22
BA24
BA31
+VCCPGPPA
BC42
+VCCPGPPBCH
BD40
AJ41
+VCCPGPPEF
AL41
AD41
+VCCPGPPG
+VCCPHVC_3P3
AN5
+VCCDTS_1P0
AD15
+V3.3S_VCCATS
AD13
+VCCPRTCPRIM_3P3
BA20
BA22
VCC_RTCEXT_CAP
BA26
+VCCPRIM_1P0
AJ20
AJ21
AJ23
AJ25
BE41
+VCCPSPI
BE43
BE42
BC44
+VCCPGPPD
BA45
BC45
BB45
+VCCPFUSE_3P3
BD3
BE3
BE4
R157 0_6
+3.3V_SUS
+VCCPGPPA
+VCCPGPPBCH
+VCCPGPPEF
+VCCPGPPG
+VCCPHVC_3P3
R146 0_4
+V3.3S_VCCATS
+VCCPRTCPRIM_3P3
+3V_RTC
C506 0.1U/10V_4
+VCCPRIM_1P0
R425 0_4
+VCCPGPPD
R396 0_4
+VCCPRIM_1P0
VCCDSW_3p3 = 204mA
VCCPGPPA(3.3V) = 82mA
VCCPGPPBCH(3.3V) = 229mA
VCCPGPPEF(3.3V) = 114mA
VCCPGPPG(3.3V) = 65mA
VCCPRIM_3p3 = 117mA
+VCC_1.00
Place close pin BA26
+3.3V_SUS
VCCATS = 7mA
VCCRTCPRIM_3p3 = 1mA
VCCRTC = 117mA
VCCSPI = 29mA
VCCPGPPD = 78mA
+3.3V_SUS
VCCSPI = 29mA
+V3.3S_VCCATS
R136 0_4
3/16 change to 3.3V_RUN
Place close pin AD13
+V3.3S_VCCATS
+VCCPRTCPRIM_3P3
+3.3V_SUS
R141 0_4
1U/6.3V_4
Place close pin AD41
+VCCPHVC_3P3
+3.3V_SUS +VCCPHVC_3P3+3.3V_RUN
C488
1U/6.3V_4
+VCCPRTC_3P3
+3V_RTC
C499
1U/6.3V_4
Place close pin BA22
+VCCPRTCPRIM_3P3
C495
0.1U/10V_4
R123 0_4
0.1U/10V_4
Place close pin AN5
C480
C498
0.1U/10V_4
+VCCPGPPD
+VCCMPHY_1P0
+VCCMPHY_1P0 +VCC_1.00
R207 0_8
R198 0_8
12
A A
5
4
C508
0.1U/25V_4
+VCCHDA
+VCCHDA +3.3V_SUS
R139 0_4
3
+VCCPGPPD+3.3V_SUS
+VCCPGPPA
R182 0_4
+VCCPGPPBCH
R424 0_4
Place close pin BC42,BD40
+VCCPGPPA+3.3V_SUS
+VCCPGPPBCH+3.3V_SUS
C695
0.1U/10V_4
+VCCPGPPEF +VCCPGPPG
+VCCPGPPEF+3.3V_SUS +3.3V_SUS +VCCPGPPG
R214 0_4
C515
0.1U/10V_4
Place close pin AJ41, AL41 Place close pin AD41
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Monday, May 25, 2015
Date: Sheet of
Monday, May 25, 2015
Date: Sheet of
2
Monday, May 25, 2015
PROJECT :
PCH
PCH
PCH
1
R211 0_4R426 0_4
AM9A
AM9A
AM9A
C514
0.1U/10V_4
13 57
13 57
13 57
A0
A0
A0
5
4
3
2
1
?
SPT-H_PCH
U14L
AC18
C42
5
VSS
D10
VSS
D12
VSS
D15
VSS
D16
VSS
D17
VSS
D19
VSS
D21
VSS
D24
VSS
D25
VSS
D27
VSS
D29
VSS
D30
VSS
D31
VSS
D33
VSS
D35
VSS
D36
VSS
E13
VSS
E15
VSS
E31
VSS
E33
VSS
F44
VSS
F8
VSS
G42
VSS
G9
VSS
H17
VSS
H19
VSS
H22
VSS
H24
VSS
H27
VSS
H29
VSS
H3
VSS
H35
VSS
J10
VSS
J11
VSS
J3
VSS
J39
VSS
J5
VSS
T42
VSS
U10
VSS
U11
VSS
U14
VSS
U17
VSS
U18
VSS
U28
VSS
U29
VSS
U31
VSS
U32
VSS
U33
VSS
U38
VSS
U4
VSS
U8
VSS
V18
VSS
V20
VSS
V21
VSS
V23
VSS
V25
VSS
V29
VSS
V3
VSS
V45
VSS
W14
VSS
W31
VSS
W32
VSS
W33
VSS
W38
VSS
W4
VSS
W8
VSS
Y17
VSS
SPT_PCH_H/SKT
12 OF 12
D D
C C
B B
A A
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
?
REV = 1.3
AB11
AB7
AB14
AB31
AB32
AB38
AB4
AB5
AC1
AC20
AC21
AC25
AC29
AC45
AB8
AD11
AD14
AB15
AD32
AD33
AD36
AD4
AD8
AE18
AE20
AE21
AE25
AE28
AL10
AL11
AL13
AL17
AL19
AL24
AL29
AL32
AL33
AL38
AM15
AM17
AM19
AM22
AM24
AM27
AM29
AM45
AN11
AN22
AN27
AN31
AN39
AN7
AN8
AP11
AP4
AR33
AR34
AR42
AR9
AT10
AT15
AT36
AT9
AU1
AU35
AU36
AU39
AU45
C4
4
AN4
AN10
BE14
BE18
BE23
BE28
BE32
BE37
BE40
BE9
C10
C28
C37
K10
K27
K33
K36
K42
K43
L12
L13
L15
L41
M35
M42
N10
N15
N19
N22
N24
N35
N36
N41
P17
P19
P22
P45
R10
R14
R22
R29
R33
R38
Y18
Y20
Y21
Y26
Y28
Y29
A18
A25
A32
A37
AA17
AA18
AA20
AA21
AA25
AA29
AA4
AA42
AB10
C2
J7
K4
L4
L8
N4
N5
R5
T1
T2
T4
?
U14I
SPT-H_PCH
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
9 OF 12
SPT_PCH_H/SKT
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
?
REV = 1.3
AR5
AR7
U15
AL4
AE29
AE4
AE42
AF18
AF20
AF21
AF23
AF25
AF26
AF28
AF29
AG11
AG13
AG31
AG32
AG33
AG38
AG4
AH1
AH17
AH18
AH20
AH21
AH23
AH25
AH26
AH28
AH29
AH45
AJ10
AJ14
AJ15
AJ17
AJ18
AJ26
AJ28
AJ29
AJ31
AJ32
AJ36
AK4
AK42
AU7
AV17
AV24
AV27
AV31
AV33
AV6
AW13
AW19
AW29
AW37
AW9
AY38
AY45
B25
B3
B37
B40
B6
BA1
BB11
BB16
BB21
BB25
BB30
BB34
BC2
BD43
?
U14J
BD2
BD45
BD44
BE44
D45
A42
B45
B44
A4
A3
B2
A2
B1
BB1
BC1
A44
C1
D1
SPT_PCH_H/SKT
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
RSVD
RSVD
SPT-H_PCH
10 OF 12
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
PREQ#
PRDY#
CPU_TRST#
PCH_TRIGOUT
PCH_TRIGIN
?
REV = 1.3
PROC_TRIGIN_R
AR22
W13
U13
P31
N31
P27
R27
N29
P29
AN29
R24
P24
PROC_PREQ#
AT3
PROC_PRDY#
AT4
PROC_TRST#
AY5
PROC_TRIGIN_R
AL2
PROC_TRIGOUT
AK1
Connector Less Debug Hooks Routing Guidelines
#546884 PDG (V1.0) page 505
2/4 Remove TP,
double TP
PROC_PREQ#
PROC_PRDY#
PROC_TRST#
R354 30_4
2/4 add TP
TP86
PROC_TRIGOUT 6
PROC_PREQ# 4
PROC_PRDY# 4
PROC_TRST# 4
PROC_TRIGIN 6
3/17 add 30 ohm
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Monday, May 25, 2015
Date: Sheet of
Monday, May 25, 2015
Date: Sheet of
3
2
Monday, May 25, 2015
PROJECT :
PCH
PCH
PCH
1
AM9A
AM9A
AM9A
14 57
14 57
14 57
A0
A0
A0
5
4
3
2
1
Place these Caps near So-Dimm2.
M_A_A[15:0]2
D D
M_A_BS#[2:0]2
M_A_CS#02
M_A_CS#12
M_A_CLKP02
M_A_CLKN02
M_A_CLKP12
M_A_CLKN12
M_A_CKE02
M_A_CKE12
M_A_CAS#2
SO-DIMMA SPD ADDRESS IS 0XA0
C C
B B
2
RP2 10KX2
4
M_A_RAS#2
1
3
M_A_WE#2
SMB_RUN_CLK10,16
SMB_RUN_DAT10,16
M_A_ODT02
M_A_ODT12
M_A_DQSP[3:0]2
M_A_DQSP[7:4]2
M_A_DQSN[3:0]2
M_A_DQSN[7:4]2
M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15
M_A_BS#0
M_A_BS#1
M_A_BS#2
DIMM0_SA0
DIMM0_SA1
M_A_ODT0
M_A_ODT1
M_A_DQSP0
M_A_DQSP1
M_A_DQSP2
M_A_DQSP3
M_A_DQSP4
M_A_DQSP5
M_A_DQSP6
M_A_DQSP7
M_A_DQSN0
M_A_DQSN1
M_A_DQSN2
M_A_DQSN3
M_A_DQSN4
M_A_DQSN5
M_A_DQSN6
M_A_DQSN7
JDIM2A
98
A0
97
A1
96
A2
95
A3
92
A4
91
A5
90
A6
86
A7
89
A8
85
A9
107
A10/AP
84
A11
83
A12/BC#
119
A13
80
A14
78
A15
109
BA0
108
BA1
79
BA2
114
S0#
121
S1#
101
CK0
103
CK0#
102
CK1
104
CK1#
73
CKE0
74
CKE1
115
CAS#
110
RAS#
113
WE#
197
SA0
201
SA1
202
SCL
200
SDA
116
ODT0
120
ODT1
11
DM0
28
DM1
46
DM2
63
DM3
136
DM4
153
DM5
170
DM6
187
DM7
12
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS#0
DQS#1
DQS#2
DQS#3
DQS#4
DQS#5
DQS#6
DQS#7
PC2100 DDR3 SDRAM SO-DIMM
29
47
64
137
154
171
188
10
27
45
62
135
152
169
186
DS2SK-20401-TP4B
ddr-ddrsk-20401-tp4b-204p-smt
DGMK4000428
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
(204P)
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
M_A_DQ5
7
M_A_DQ7
15
M_A_DQ3
17
M_A_DQ1
4
M_A_DQ0
6
M_A_DQ2
16
M_A_DQ6
18
M_A_DQ9
21
M_A_DQ12
23
M_A_DQ15
33
M_A_DQ11
35
M_A_DQ13
22
M_A_DQ8
24
M_A_DQ14
34
M_A_DQ10
36
M_A_DQ16
39
M_A_DQ21
41
M_A_DQ19
51
M_A_DQ18
53
M_A_DQ17
40
M_A_DQ20
42
M_A_DQ23
50
M_A_DQ22
52
M_A_DQ25
57
M_A_DQ24
59
M_A_DQ31
67
M_A_DQ30
69
M_A_DQ28
56
M_A_DQ29
58
M_A_DQ27
68
M_A_DQ26
70
M_A_DQ36
129
M_A_DQ37
131
M_A_DQ34
141
M_A_DQ38
143
M_A_DQ33
130
M_A_DQ32
132
M_A_DQ35
140
M_A_DQ39
142
M_A_DQ41
147
M_A_DQ45
149
M_A_DQ47
157
M_A_DQ43
159
M_A_DQ40
146
M_A_DQ44
148
M_A_DQ42
158
M_A_DQ46
160
M_A_DQ49
163
M_A_DQ48
165
M_A_DQ54
175
M_A_DQ55
177
M_A_DQ53
164
M_A_DQ52
166
M_A_DQ50
174
M_A_DQ51
176
M_A_DQ60
181
M_A_DQ57
183
M_A_DQ63
191
M_A_DQ62
193
M_A_DQ56
180
M_A_DQ61
182
M_A_DQ58
192
M_A_DQ59
194
M_A_DQ4
5
H =4.0mm
+V_VDDQ
C453 1U/6.3V_4 C447
C449 1U/6.3V_4
C471 1U/6.3V_4
C451 1U/6.3V_4
C469 10U/6.3V_6
C473 10U/6.3V_6
C450 10U/6.3V_6
C472 10U/6.3V_6
A A
C470 10U/6.3V_6
12
C382 *22U/6.3V_8_NC
12
C386 *22U/6.3V_8_NC
C452 10U/6.3V_6
C454 10U/6.3V_6
5
Pleace on the BOT side
Near to JDIM2
T_DDR26
T_DDR
4
+3.3V_ALW
12
12
RT1
10K/NTC_4
R397
1.5K/F_4
M_A_DQ[63:0] 2
+SMDDR_VREF_CA
C476 0.1U/16V/X7R_4
C475 *0.1U/16V/X7R_4_NC
C477 *2.2U/6.3V_6_NC
+SMDDR_VREF_DQA
C455 0.1U/16V/X7R_4
C456 *0.1U/16V/X7R_4_NC
C448 2.2U/6.3V_6
2/24 net name exchange
+SMDDR_VREF_DQA
+SMDDR_VREF_CA
+DDR_VTT
C467 1U/6.3V_4
C443 1U/6.3V_4
C465 1U/6.3V_4
C466 1U/6.3V_4
C440 10U/6.3V_6
C439 *22U/6.3V_8_NC
+3.3V_RUN
C446 0.1U/16V/X7R_4
C444 2.2U/6.3V_6
3
+3.3V_RUN
DRAMRST#16
C474
0.01U/25V_4
+V_VDDQ
2.48A
+3.3V_RUN
R125 *10K/F_4_NC
C457
0.01U/25V_4
DRAMRST#
JDIM2B
75
VDD1
76
VDD2
81
VDD3
82
VDD4
87
VDD5
88
VDD6
93
VDD7
94
VDD8
99
VDD9
100
VDD10
105
VDD11
106
VDD12
111
VDD13
112
VDD14
117
VDD15
118
VDD16
123
VDD17
124
VDD18
199
VDDSPD
77
NC1
122
NC2
125
NCTEST
198
EVENT#
30
RESET#
1
VREF_DQ
126
VREF_CA
2
VSS1
3
VSS2
8
VSS3
9
VSS4
13
VSS5
14
VSS6
19
VSS7
20
VSS8
25
VSS9
26
VSS10
31
VSS11
32
VSS12
37
VSS13
38
VSS14
43
VSS15
DS2SK-20401-TP4B
ddr-ddrsk-20401-tp4b-204p-smt
DGMK4000428
PC2100 DDR3 SDRAM SO-DIMM
(204P)
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VTT1
VTT2
PAD1
PAD2
HOLE1
HOLE2
44
48
49
54
55
60
61
65
66
71
72
127
128
133
134
138
139
144
145
150
151
155
156
161
162
167
168
172
173
178
179
184
185
189
190
195
196
203
204
+DDR_VTT
205
206
207
208
H = 4.0mm
12
+V_VDDQ
R108
1K/F_4
R106 2/F_6
R107
1K/F_4
0.022uF -> WP
V0.91 P.41
Follow SKL-H WP(V0.91) support DDR3L SO-DIMM
#549401 page 41
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Monday, May 25, 2015 15 57
Date: Sheet of
Monday, May 25, 2015 15 57
Date: Sheet of
2
Monday, May 25, 2015 15 57
DDR3 DIMM1-STD (4.0H)
DDR3 DIMM1-STD (4.0H)
DDR3 DIMM1-STD (4.0H)
+VREFDQ_SA+SMDDR_VREF_DQA
C445
0.022U/16V_4
R105
24.9/F_4
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
PROJECT :
1
*0.1U/10V_4_NC
AM9A
AM9A
AM9A
A0
A0
A0
A
B
C
D
E
M_B_A[15:0]2
1 1
M_B_BS#[2:0]2
M_B_CS#02
M_B_CS#12
M_B_CLKP02
M_B_CLKN02
M_B_CLKP12
M_B_CLKN12
M_B_CKE02
M_B_CKE12
SO-DIMMA SPD ADDRESS IS 0XA4
R81 10K/F_4
+3.3V_RUN
2 2
3 3
R91 10K/F_4
M_B_CAS#2
M_B_RAS#2
M_B_WE#2
SMB_RUN_CLK10,15
SMB_RUN_DAT10,15
M_B_ODT02
M_B_ODT12
M_B_DQSP[7:0]2
M_B_DQSN[7:0]2
M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_A14
M_B_A15
M_B_BS#0
M_B_BS#1
M_B_BS#2
DIMM1_SA0
DIMM1_SA1
M_B_ODT0
M_B_ODT1
M_B_DQSP0
M_B_DQSP1
M_B_DQSP2
M_B_DQSP3
M_B_DQSP4
M_B_DQSP5
M_B_DQSP6
M_B_DQSP7
M_B_DQSN0
M_B_DQSN1
M_B_DQSN2
M_B_DQSN3
M_B_DQSN4
M_B_DQSN5
M_B_DQSN6
M_B_DQSN7
Place these Caps near So-Dimm1.
+V_VDDQ
C438 1U/6.3V_4
C402 1U/6.3V_4
C436 1U/6.3V_4
C403 1U/6.3V_4
C430 10U/6.3V_6
C429 10U/6.3V_6
C428 10U/6.3V_6
C395 10U/6.3V_6
C401 10U/6.3V_6
12
4 4
C400 *22U/6.3V_8_NC
12
C394 *22U/6.3V_8_NC
C427 10U/6.3V_6
C426 10U/6.3V_6
+
C384
*220U/2.5V/E15_3528_NC
A
PCH_DRAMRST#10 DRAMRST# 15
Follow SKL-H WP(V0.91)
support DDR3L SO-DIMM
#549401 page 24&25
JDIM1A
98
A0
97
A1
96
A2
95
A3
92
A4
91
A5
90
A6
86
A7
89
A8
85
A9
107
A10/AP
84
A11
83
A12/BC#
119
A13
80
A14
78
A15
109
BA0
108
BA1
79
BA2
114
S0#
121
S1#
101
CK0
103
CK0#
102
CK1
104
CK1#
73
CKE0
74
CKE1
115
CAS#
110
RAS#
113
WE#
197
SA0
201
SA1
202
SCL
200
SDA
116
ODT0
120
ODT1
11
DM0
28
DM1
46
DM2
63
DM3
136
DM4
153
DM5
170
DM6
187
DM7
12
DQS0
29
DQS1
47
DQS2
64
DQS3
137
DQS4
154
DQS5
171
DQS6
188
DQS7
10
DQS#0
27
DQS#1
45
DQS#2
62
DQS#3
135
DQS#4
152
DQS#5
169
DQS#6
186
DQS#7
DS2SK-20401-TP8D
ddr-ds2sk-20401-tp8d-std-204p
DGMK4000431
H = 8.0mm
+V_VDDQ
12
R103
470_4
R102 0_4
B
(204P)
PC2100 DDR3 SDRAM SO-DIMM
DRAMRST#
C435
0.1U/16V/X7R_4
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
M_B_DQ5
5
M_B_DQ1
7
M_B_DQ3
15
M_B_DQ2
17
M_B_DQ0
4
M_B_DQ4
6
M_B_DQ6
16
M_B_DQ7
18
M_B_DQ9
21
M_B_DQ8
23
M_B_DQ10
33
M_B_DQ11
35
M_B_DQ13
22
M_B_DQ12
24
M_B_DQ14
34
M_B_DQ15
36
M_B_DQ16
39
M_B_DQ17
41
M_B_DQ19
51
M_B_DQ23
53
M_B_DQ20
40
M_B_DQ21
42
M_B_DQ18
50
M_B_DQ22
52
M_B_DQ24
57
M_B_DQ29
59
M_B_DQ30
67
M_B_DQ26
69
M_B_DQ28
56
M_B_DQ25
58
M_B_DQ31
68
M_B_DQ27
70
M_B_DQ39
129
M_B_DQ37
131
M_B_DQ32
141
M_B_DQ34
143
M_B_DQ38
130
M_B_DQ36
132
M_B_DQ35
140
M_B_DQ33
142
M_B_DQ40
147
M_B_DQ41
149
M_B_DQ47
157
M_B_DQ42
159
M_B_DQ45
146
M_B_DQ44
148
M_B_DQ46
158
M_B_DQ43
160
M_B_DQ51
163
M_B_DQ54
165
M_B_DQ53
175
M_B_DQ48
177
M_B_DQ50
164
M_B_DQ55
166
M_B_DQ49
174
M_B_DQ52
176
M_B_DQ63
181
M_B_DQ62
183
M_B_DQ56
191
M_B_DQ57
193
M_B_DQ58
180
M_B_DQ59
182
M_B_DQ61
192
M_B_DQ60
194
M_B_DQ[63:0] 2
+DDR_VTT
C416 1U/6.3V_4
C417 1U/6.3V_4
C410 1U/6.3V_4
C392 1U/6.3V_4
C412 *1U/6.3V_4_NC
C409 *1U/6.3V_4_NC
C411 10U/6.3V_6
C390 10U/6.3V_6
2/24 net name exchange
+3.3V_RUN
C408 0.1U/16V/X7R_4
C407 2.2U/6.3V_6
+SMDDR_VREF_CA
C431 0.1U/16V/X7R_4
C433 0.1U/16V/X7R_4
C434 2.2U/6.3V_6
+SMDDR_VREF_DQB
C398 0.1U/16V/X7R_4
C396 *0.1U/16V/X7R_4_NC
C399 2.2U/6.3V_6
+V_VDDQ
C404 0.1U/16V/X7R_4
C405 0.1U/16V/X7R_4
C437 0.1U/16V/X7R_4
C406 0.1U/16V/X7R_4
+SMDDR_VREF_CA
Follow SKL-H WP(V0.91)
support DDR3L SO-DIMM
#549401 page 41
C
+V_VDDQ
R101
1K/F_4
R99 2/F_6
R100
1K/F_4
+SMDDR_VREF_DQB
+SMDDR_VREF_CA
0.01U/25V_4
+DDR_VREF_CA
C441
0.022U/16V_4
0.022uF -> WP V0.91 P.41
R104
24.9/F_4
2.48A
+3.3V_RUN
+3.3V_RUN
DRAMRST#
C432
+SMDDR_VREF_DQB
Follow SKL-H WP(V0.91) support DDR3L SO-DIMM
#549401 page 41
C442
*0.1U/10V_4_NC
D
+V_VDDQ
R87 *10K/F_4_NC
C397
0.01U/25V_4
JDIM1B
75
VDD1
76
VDD2
81
VDD3
82
VDD4
87
VDD5
88
VDD6
93
VDD7
94
VDD8
99
VDD9
100
VDD10
105
VDD11
106
VDD12
111
VDD13
112
VDD14
117
VDD15
118
VDD16
123
VDD17
124
VDD18
199
VDDSPD
77
NC1
122
NC2
125
NCTEST
198
EVENT#
30
RESET#
1
VREF_DQ
126
VREF_CA
2
VSS1
3
VSS2
8
VSS3
9
VSS4
13
VSS5
14
VSS6
19
VSS7
20
VSS8
25
VSS9
26
VSS10
31
VSS11
32
VSS12
37
VSS13
38
VSS14
43
VSS15
DS2SK-20401-TP8D
ddr-ds2sk-20401-tp8d-std-204p
DGMK4000431
PC2100 DDR3 SDRAM SO-DIMM
(204P)
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VTT1
VTT2
PAD1
PAD2
HOLE1
HOLE2
44
48
49
54
55
60
61
65
66
71
72
127
128
133
134
138
139
144
145
150
151
155
156
161
162
167
168
172
173
178
179
184
185
189
190
195
196
203
204
205
206
207
208
H = 8.0mm
+V_VDDQ +VREFDQ_SB
R90
1K/F_4
R88 2/F_6
R89
1K/F_4
0.022uF -> WP
V0.91 P.41
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
DDR3 DIMM2-STD (8.0H)
DDR3 DIMM2-STD (8.0H)
DDR3 DIMM2-STD (8.0H)
Monday, May 25, 2015
Monday, May 25, 2015
Monday, May 25, 2015
C389
0.022U/16V_4
R82
24.9/F_4
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
PROJECT :
E
C387
*0.1U/10V_4_NC
AM9A
AM9A
AM9A
16 57
16 57
16 57
+DDR_VTT
A0
A0
A0
1
2
3
4
5
6
7
8
DG-07158-001 V05 PG51
PEX_IOVDD/Q : 3300mA
+1.05V_GFX
Midway bewteen GPU and Power Supply
C586 22U/6.3V_6
C185 22U/6.3V_6
C196 22U/6.3V_6
A A
B B
C294 22U/6.3V_6
C88 10U/6.3V_6
C69 10U/6.3V_6
C584 10U/6.3V_6
C301 10U/6.3V_6
PLACE UNDER BGA
C583 1U/6.3V_4
C211 1U/6.3V_4
C250 1U/6.3V_4
C221 1U/6.3V_4
PLACE NEAR BALLS
C257 4.7U/6.3V_4
C272 4.7U/6.3V_4
DG-07158-001 V05 PG56
PLACE NEAR GPU
C354 4.7U/6.3V_4
C C
D D
C326 1U/6.3V_4
C327 0.1U/10V_4
C353 *0.1U/10V_4_NC
C636 *0.1U/10V_4_NC
PLACE UNDER GPU
+3V_AON
+3V_GFX
PLACE NEAR GPU
C322 4.7U/6.3V_4
C325 1U/6.3V_4
C355 0.1U/10V_4
C324 0.1U/10V_4
C331 *0.1U/10V_4_NC
PLACE UNDER GPU
1
VDD33 : 85mA
2
AG19
AG21
AG22
AG24
AH21
AH25
AG13
AG15
AG16
AG18
AG25
AH15
AH18
AH26
AH27
AJ27
AK27
AL27
AM28
AN28
AC6
AJ28
AJ4
AJ5
AL11
C15
D19
D20
D23
D26
H31
V32
AA1
AA2
AA3
AA4
AA5
AA6
AA7
AA8
T8
Y1
Y2
Y3
J8
K8
L8
M8
U11A
N16P-GX
PEX_IOVDD_1
PEX_IOVDD_2
PEX_IOVDD_3
PEX_IOVDD_4
PEX_IOVDD_5
PEX_IOVDD_6
PEX_IOVDDQ_1
PEX_IOVDDQ_2
PEX_IOVDDQ_3
PEX_IOVDDQ_4
PEX_IOVDDQ_5
PEX_IOVDDQ_6
PEX_IOVDDQ_7
PEX_IOVDDQ_8
PEX_IOVDDQ_9
PEX_IOVDDQ_10
PEX_IOVDDQ_11
PEX_IOVDDQ_12
PEX_IOVDDQ_13
PEX_IOVDDQ_14
NC_1
NC_2
NC_3
NC_4
NC_5
NC_6
NC_7
NC_8
NC_9
NC_10
NC_11
NC_12
NC_13
NC_14
NC_15
NC_16
NC_17
NC_18
NC_19
NC_20
NC_21
NC_22
NC_23
NC_24
3V3_AON_1
3V3_AON_2
3V3_MAIN_1
3V3_MAIN_2
[PEG Interface]
3
PEX_RX0
PEX_RX0_N
PEX_RX1
PEX_RX1_N
PEX_RX2
PEX_RX2_N
PEX_RX3
PEX_RX3_N
PEX_RX4
PEX_RX4_N
PEX_RX5
PEX_RX5_N
PEX_RX6
PEX_RX6_N
PEX_RX7
PEX_RX7_N
PEX_RX8
PEX_RX8_N
PEX_RX9
PEX_RX9_N
PEX_RX10
PEX_RX10_N
PEX_RX11
PEX_RX11_N
PEX_RX12
PEX_RX12_N
PEX_RX13
PEX_RX13_N
PEX_RX14
PEX_RX14_N
PEX_RX15
PEX_RX15_N
PEX_TX0
PEX_TX0_N
PEX_TX1
PEX_TX1_N
PEX_TX2
PEX_TX2_N
PEX_TX3
PEX_TX3_N
PEX_TX4
PEX_TX4_N
PEX_TX5
PEX_TX5_N
PEX_TX6
PEX_TX6_N
PEX_TX7
PEX_TX7_N
PEX_TX8
PEX_TX8_N
PEX_TX9
PEX_TX9_N
PEX_TX10
PEX_TX10_N
PEX_TX11
PEX_TX11_N
PEX_TX12
PEX_TX12_N
PEX_TX13
PEX_TX13_N
PEX_TX14
PEX_TX14_N
PEX_TX15
PEX_TX15_N
PEX_REFCLK
PEX_REFCLK_N
PEX_TSTCLK_OUT
PEX_TSTCLK_OUT_N
PEX_RST_N
PEX_CLKREQ_N
PEX_TERMP
TESTMODE
PEX_PLLVDD
PEX_PLL_HVDD
PEX_SVDD_3V3
3.3V_AUX_NC
VDD_SENSE
GND_SENSE
AN12
AM12
AN14
AM14
AP14
AP15
AN15
AM15
AN17
AM17
AP17
AP18
AN18
AM18
AN20
AM20
AP20
AP21
AN21
AM21
AN23
AM23
AP23
AP24
AN24
AM24
AN26
AM26
AP26
AP27
AN27
AM27
PEG_RXP0_C
AK14
PEG_RXN0_C
AJ14
PEG_RXP1_C
AH14
PEG_RXN1_C
AG14
PEG_RXP2_C
AK15
PEG_RXN2_C
AJ15
PEG_RXP3_C
AL16
PEG_RXN3_C
AK16
PEG_RXP4_C
AK17
PEG_RXN4_C
AJ17
PEG_RXP5_C
AH17
PEG_RXN5_C
AG17
PEG_RXP6_C
AK18
PEG_RXN6_C
AJ18
PEG_RXP7_C
AL19
PEG_RXN7_C
AK19
AK20
AJ20
AH20
AG20
AK21
AJ21
AL22
AK22
AK23
AJ23
AH23
AG23
AK24
AJ24
AL25
AK25
AL13
AK13
PEX_TSTCLK
AJ26
PEX_TSTCLK#
AK26
AJ11
NC
AJ12
PEX_CLKREQ#
AK12
PEX_TERMP
AP29
AK11
TESTMODE
+1.05V_GFX
AG26
AH12
AG12
3.3V_AUX
P8
L4
L5
3.3V_AUX
CLK_PCIE_VGAP 12
CLK_PCIE_VGAN 12
PEX_PLLVDD : 150mA
PEX_SVDD_3V3 : 210mA
VGPU_CORE_SENSE 50
VSS_GPU_SENSE 50
TP11
4
12
C265 0.22U/16V_4
12
C286 0.22U/16V_4
12
C263 0.22U/16V_4
12
C245 0.22U/16V_4
12
C226 0.22U/16V_4
12
C244 0.22U/16V_4
12
C223 0.22U/16V_4
12
C213 0.22U/16V_4
12
C200 0.22U/16V_4
12
C206 0.22U/16V_4
12
C197 0.22U/16V_4
12
C189 0.22U/16V_4
12
C178 0.22U/16V_4
12
C184 0.22U/16V_4
12
C175 0.22U/16V_4
12
C171 0.22U/16V_4
R34 *200_4_NC
R304 10K_4
R278 2.49K/F_4
R293 10K_4
C3180.1U/10V_4
C3174.7U/6.3V_4
C3444.7U/6.3V_4
PLACE NEAR BGA
DG-06803-001_V04 : R305 is unstuffed
E2703.DSN : R305 is stuffed
PEGX_RST#
+3V_AON
+3V_AON
PEG_TXP0_C 3
PEG_TXN0_C 3
PEG_TXP1_C 3
PEG_TXN1_C 3
PEG_TXP2_C 3
PEG_TXN2_C 3
PEG_TXP3_C 3
PEG_TXN3_C 3
PEG_TXP4_C 3
PEG_TXN4_C 3
PEG_TXP5_C 3
PEG_TXN5_C 3
PEG_TXP6_C 3
PEG_TXN6_C 3
PEG_TXP7_C 3
PEG_TXN7_C 3
PEG_RXP0 3
PEG_RXN0 3
PEG_RXP1 3
PEG_RXN1 3
PEG_RXP2 3
PEG_RXN2 3
PEG_RXP3 3
PEG_RXN3 3
PEG_RXP4 3
PEG_RXN4 3
PEG_RXP5 3
PEG_RXN5 3
PEG_RXP6 3
PEG_RXN6 3
PEG_RXP7 3
PEG_RXN7 3
+1.05V_GFX
DG-07158-001 V05 PG52
C202 4.7U/6.3V_4
C219 1U/6.3V_4
C236 0.1U/10V_4
5
DGPU_PW ROK12,51
GPU_PEX_RST_HOLD#20
PLACE NEAR GPU
PLACE NEAR GPU
PLACE UNDER GPU BALLS
6
+3V_GFX
3/16 change to NC
R306 *10K_4_NC
R315 0_4
2
PEX_CLKREQ#
SYS_PEX_RST_MON#20
RST_MON#
R64 0_4
PLTRST#9,26,28,35,36,37
DGPU_HOLD_RST#12
时序，领跑全行业！
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Monday, May 25, 2015
Date: Sheet of
Monday, May 25, 2015
Date: Sheet of
Monday, May 25, 2015
31
Q18
2N7002W
+3V_AON
C346
0.1U/10V_4
U1
2
1
74AHC1G09GW
N16P-GX - 1/5 (PCIE)
N16P-GX - 1/5 (PCIE)
N16P-GX - 1/5 (PCIE)
7
4
MC74VHC1G08DFT2G
3 5
+3V_AON
2
1
3 5
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
PROJECT :
CLK_PEGA_REQ# 12
+3V_AON
PEGX_RST#
C349
4
0.1U/10V_4
RST_MON#
U3
R61
*10K_4_NC
R59
100K_4
AM9A
AM9A
AM9A
17 57
17 57
17 57
8
A0
A0
A0
1
FBA_CMD0
FBA_CMD[31:0]22,23
A A
FBA_DBI[7:0]22,23
B B
FBA_EDC[7:0]22,23
GDDR5 NO USE
DG-07158-001 V05 PG48
PLACE CLOSE UNDER GPU
C C
PLACE CLOSE TO NEAE GPU
C4 22U/6.3V_6
C537 22U/6.3V_6
D D
+1.35V_GFX
C187 1U/10V/X5R_4
C316 1U/10V/X5R_4
C68 1U/10V/X5R_4
1 2
C216 0.1U/16V/X7R_4
1 2
C193 0.1U/16V/X7R_4
1 2
C194 0.1U/16V/X7R_4
1 2
C188 0.1U/16V/X7R_4
C271 4.7U/6.3V_4
C548 4.7U/6.3V_4
C13 4.7U/6.3V_4
C307 4.7U/6.3V_4
C276 10U/6.3V_6
C612 10U/6.3V_6
1
U30
FBA_CMD1
T31
FBA_CMD2
U29
FBA_CMD3
R34
FBA_CMD4
R33
FBA_CMD5
U32
FBA_CMD6
U33
FBA_CMD7
U28
FBA_CMD8
V28
FBA_CMD9
V29
FBA_CMD10
V30
FBA_CMD11
U34
FBA_CMD12
U31
FBA_CMD13
V34
FBA_CMD14
V33
FBA_CMD15
Y32
FBA_CMD16
AA31
FBA_CMD17
AA29
FBA_CMD18
AA28
FBA_CMD19
AC34
FBA_CMD20
AC33
FBA_CMD21
AA32
FBA_CMD22
AA33
FBA_CMD23
Y28
FBA_CMD24
Y29
FBA_CMD25
W31
FBA_CMD26
Y30
FBA_CMD27
AA34
FBA_CMD28
Y31
FBA_CMD29
Y34
FBA_CMD30
Y33
FBA_CMD31 VMA_DQ31
V31
FBA_DBI0
P30
FBA_DBI1
F31
FBA_DBI2
F34
FBA_DBI3
M32
FBA_DBI4
AD31
FBA_DBI5
AL29
FBA_DBI6
AM32
FBA_DBI7
AF34
FBA_EDC0
M31
FBA_EDC1
G31
FBA_EDC2
E33
FBA_EDC3
M33
FBA_EDC4
AE31
FBA_EDC5
AK30
FBA_EDC6
AN33
FBA_EDC7
AF33
M30
H30
E34
M34
AF30
AK31
AM34
AF32
AA27
AA30
AB27
AB33
AC27
AD27
AE27
AF27
AG27
B13
B19
E13
E19
H10
H11
H12
H13
H14
H18
H19
H20
H21
H22
H23
H24
M27
N27
P27
R27
T27
T30
T33
Y27
B16
E16
H15
H16
V27
W27
W30
W33
2
U11B
N16P-GX
FBA_CMD0 (FBA_CMD25)
FBA_CMD1 (FBA_CMD23)
FBA_CMD2
FBA_CMD3 (FBA_CMD0)
FBA_CMD4 (FBA_CMD10)
FBA_CMD5 (FBA_CMD26)
FBA_CMD6 (FBA_CMD14)
FBA_CMD7
FBA_CMD8 (FBA_CMD1)
FBA_CMD9 (FBA_CMD22)
FBA_CMD10 (FBA_CMD20)
FBA_CMD11 (FBA_CMD24)
FBA_CMD12 (FBA_CMD18)
FBA_CMD13 (FBA_CMD9)
FBA_CMD14 (FBA_CMD29)
FBA_CMD15 (FBA_CMD8)
FBA_CMD16 (FBA_CMD27)
FBA_CMD17 (FBA_CMD15)
FBA_CMD18 (FBA_CMD11)
FBA_CMD19 (FBA_CMD16)
FBA_CMD20 (FBA_CMD28)
FBA_CMD21 (FBA_CMD3)
FBA_CMD22 (FBA_CMD17)
FBA_CMD23 (FBA_CMD5)
FBA_CMD24 (FBA_CMD4)
FBA_CMD25 (FBA_CMD21)
FBA_CMD26 (FBA_CMD6)
FBA_CMD27 (FBA_CMD13)
FBA_CMD28 (FBA_CMD19)
FBA_CMD29 (FBA_CMD12)
FBA_CMD30
FBA_CMD31 (NC)
FBA_DQM0
FBA_DQM1
FBA_DQM2
FBA_DQM3
FBA_DQM4
FBA_DQM5
FBA_DQM6
FBA_DQM7
FBA_DQS_WP0
FBA_DQS_WP1
FBA_DQS_WP2
FBA_DQS_WP3
FBA_DQS_WP4
FBA_DQS_WP5
FBA_DQS_WP6
FBA_DQS_WP7
FBA_DQS_RN0
FBA_DQS_RN1
FBA_DQS_RN2
FBA_DQS_RN3
FBA_DQS_RN4
FBA_DQS_RN5
FBA_DQS_RN6
FBA_DQS_RN7
FBVDDQ_1
FBVDDQ_2
FBVDDQ_3
FBVDDQ_4
FBVDDQ_5
FBVDDQ_6
FBVDDQ_7
FBVDDQ_8
FBVDDQ_9
FBVDDQ_10
FBVDDQ_12
FBVDDQ_13
FBVDDQ_15
FBVDDQ_16
FBVDDQ_17
FBVDDQ_18
FBVDDQ_19
FBVDDQ_20
FBVDDQ_23
FBVDDQ_24
FBVDDQ_25
FBVDDQ_26
FBVDDQ_27
FBVDDQ_28
FBVDDQ_29
H8
FBVDDQ_30
H9
FBVDDQ_31
L27
FBVDDQ_32
FBVDDQ_33
FBVDDQ_34
FBVDDQ_35
FBVDDQ_36
FBVDDQ_37
FBVDDQ_38
FBVDDQ_39
FBVDDQ_44
FBVDDQ_AON_1
FBVDDQ_AON_2
FBVDDQ_AON_3
FBVDDQ_AON_4
FBVDDQ_AON_5
FBVDDQ_AON_6
FBVDDQ_AON_7
FBVDDQ_AON_8
2
[MEMORY I/F A]
FBB_DEBUG0
FBB_DEBUG1
FBB_WCKBxx
are reserved
NC ON : GM108/GM107
USED ON : GK107
FBA_CLK0
FBA_CLK0_N
FBA_CLK1
FBA_CLK1_N
FBA_CMD32
FBA_CMD33
FBA_CMD34
NC
FBA_CMD35
NC
FB_VREF
FBA_WCK01
FBA_WCK01_N
FBA_WCK23
FBA_WCK23_N
FBA_WCK45
FBA_WCK45_N
FBA_WCK67
FBA_WCK67_N
FBA_WCKB01
FBA_WCKB01_N
FBA_WCKB23
FBA_WCKB23_N
FBA_WCKB45
FBA_WCKB45_N
FBA_WCKB67
FBA_WCKB67_N
FB_CLAMP
FB_DLL_AVDD
FBA_PLL_AVDD
FB_VDDQ_SENSE
FB_GND_SENSE
FB_CAL_PD_VDDQ
FB_CAL_PU_GND
FB_CALTERM_GND
FBA_D00
FBA_D01
FBA_D02
FBA_D03
FBA_D04
FBA_D05
FBA_D06
FBA_D07
FBA_D08
FBA_D09
FBA_D10
FBA_D11
FBA_D12
FBA_D13
FBA_D14
FBA_D15
FBA_D16
FBA_D17
FBA_D18
FBA_D19
FBA_D20
FBA_D21
FBA_D22
FBA_D23
FBA_D24
FBA_D25
FBA_D26
FBA_D27
FBA_D28
FBA_D29
FBA_D30
FBA_D31
FBA_D32
FBA_D33
FBA_D34
FBA_D35
FBA_D36
FBA_D37
FBA_D38
FBA_D39
FBA_D40
FBA_D41
FBA_D42
FBA_D43
FBA_D44
FBA_D45
FBA_D46
FBA_D47
FBA_D48
FBA_D49
FBA_D50
FBA_D51
FBA_D52
FBA_D53
FBA_D54
FBA_D55
FBA_D56
FBA_D57
FBA_D58
FBA_D59
FBA_D60
FBA_D61
FBA_D62
FBA_D63
GM107GK107
3
L28
M29
L29
M28
N31
P29
R29
P28
J28
H29
J29
H28
G29
E31
E32
F30
C34
D32
B33
C33
F33
F32
H33
H32
P34
P32
P31
P33
L31
L34
L32
L33
AG28
AF29
AG29
AF28
AD30
AD29
AC29
AD28
AJ29
AK29
AJ30
AK28
AM29
AM31
AN29
AM30
AN31
AN32
AP30
AP32
AM33
AL31
AK33
AK32
AD34
AD32
AC30
AD33
AF31
AG34
AG32
AG33
R30
R31
AB31
AC31
FBA_DEBUG0_K
R28
FBA_DEBUG1_K
AC28
FBA_DEBUG0
R32
FBA_DEBUG1
AC32
H26
K31
L30
H34
J34
AG30
AG31
AJ34
AK34
J30
J31
J32
J33
AH31
AJ31
AJ32
AJ33
PS_FB_CLAMP
E1
K27
U27
FBVDDQ_SENSE
F1
FB_GND_SENSE
F2
FB_CAL_PD_VDDQ
J27
FB_CAL_PU_GND
H27
FB_CAL_TERM_GND
H25
3
VMA_DQ0
VMA_DQ1
VMA_DQ2
VMA_DQ3
VMA_DQ4
VMA_DQ5
VMA_DQ6
VMA_DQ7
VMA_DQ8
VMA_DQ9
VMA_DQ10
VMA_DQ11
VMA_DQ12
VMA_DQ13
VMA_DQ14
VMA_DQ15
VMA_DQ16
VMA_DQ17
VMA_DQ18
VMA_DQ19
VMA_DQ20
VMA_DQ21
VMA_DQ22
VMA_DQ23
VMA_DQ24
VMA_DQ25
VMA_DQ26
VMA_DQ27
VMA_DQ28
VMA_DQ29
VMA_DQ30
VMA_DQ32
VMA_DQ33
VMA_DQ34
VMA_DQ35
VMA_DQ36
VMA_DQ37
VMA_DQ38
VMA_DQ39
VMA_DQ40
VMA_DQ41
VMA_DQ42
VMA_DQ43
VMA_DQ44
VMA_DQ45
VMA_DQ46
VMA_DQ47
VMA_DQ48
VMA_DQ49
VMA_DQ50
VMA_DQ51
VMA_DQ52
VMA_DQ53
VMA_DQ54
VMA_DQ55
VMA_DQ56
VMA_DQ57
VMA_DQ58
VMA_DQ59
VMA_DQ60
VMA_DQ61
VMA_DQ62
VMA_DQ63
VMA_DQ[63:0]
VMC_DQ[63:0]
VMA_CLK0 22
VMA_CLK0# 22
VMA_CLK1 23
VMA_CLK1# 23
VMA_WCK01 22
VMA_WCK01# 22
VMA_WCK23 22
VMA_WCK23# 22
VMA_WCK45 23
VMA_WCK45# 23
VMA_WCK67 23
VMA_WCK67# 23
R317 10K_4
FB_PLLAVDD
+FB_PLLAVDD : 62mA
+1.35V_GFX
R322 *0_4_NC
R326 *0_4_NC
R38 40.2/F_4
R37 40.2/F_4
R40 60.4/F_4
PLACE CLOSE TO GPU BALLS
4
FBC_CMD[31:0]24,25
VMA_DQ[63:0] 22,23
VMC_DQ[63:0] 24,25
FBC_DBI[7:0]24,25
FBC_EDC[7:0]24,25
5
FBC_CMD0
FBC_CMD1
FBC_CMD2
FBC_CMD3
FBC_CMD4
FBC_CMD5
FBC_CMD6
FBC_CMD7
FBC_CMD8
FBC_CMD9
FBC_CMD10
FBC_CMD11
FBC_CMD12
FBC_CMD13
FBC_CMD14
FBC_CMD15
FBC_CMD16
FBC_CMD17
FBC_CMD18
FBC_CMD19
FBC_CMD20
FBC_CMD21
FBC_CMD22
FBC_CMD23
FBC_CMD24
FBC_CMD25
FBC_CMD26
FBC_CMD27
FBC_CMD28
FBC_CMD29
FBC_CMD30
FBC_CMD31
FBC_DBI0
FBC_DBI1
FBC_DBI2
FBC_DBI3
FBC_DBI4
FBC_DBI5
FBC_DBI6
FBC_DBI7
FBC_EDC0
FBC_EDC1
FBC_EDC2
FBC_EDC3
FBC_EDC4
FBC_EDC5
FBC_EDC6
FBC_EDC7
GDDR5 NO USE
R39*60.4/F_4_NCC231 1U/10V/X5R_4
+1.35V_GFX
R35*60.4/F_4_NC
R27*60.4/F_4_NC
R28*60.4/F_4_NC
5/20 change to HCB1608KF-300T30
DG-07158-001 V05 PG50
change to CX300T30000
1 2
C192 0.1U/16V/X7R_4
1 2
C186 0.1U/16V/X7R_4
1 2
C285 *0.1U/16V/X7R_4_NC
C299 22U/6.3V_6
+1.35V_GFX
+1.05V_GFX
L1HCB1608KF-300T30
near to GPU
under GPU
Close to GPU BALL
near to GPU
1201
4
5
U11C
N16P-GX
D13
FBB_CMD0 (FBC_CMD25)
E14
FBB_CMD1 (FBC_CMD23)
F14
FBC_CMD2
A12
FBB_CMD3 (FBC_CMD0)
B12
FBB_CMD4 (FBC_CMD10)
C14
FBB_CMD5 (FBC_CMD26)
B14
FBB_CMD6 (FBC_CMD14)
G15
FBC_CMD7
F15
FBB_CMD8 (FBC_CMD1)
E15
FBB_CMD9 (FBC_CMD22)
D15
FBB_CMD10 (FBC_CMD20)
A14
FBB_CMD11 (FBC_CMD24)
D14
FBB_CMD12 (FBC_CMD18)
A15
FBB_CMD13 (FBC_CMD9)
B15
FBB_CMD14 (FBC_CMD29)
C17
FBB_CMD15 (FBC_CMD8)
D18
FBB_CMD16 (FBC_CMD27)
E18
FBB_CMD17 (FBC_CMD15)
F18
FBB_CMD18 (FBC_CMD11)
A20
FBB_CMD19 (FBC_CMD16)
B20
FBB_CMD20 (FBC_CMD28)
C18
FBB_CMD21 (FBC_CMD3)
B18
FBB_CMD22 (FBC_CMD17)
G18
FBB_CMD23 (FBC_CMD5)
G17
FBB_CMD24(FBC_CMD4)
F17
FBB_CMD25 (FBC_CMD21)
D16
FBB_CMD26 (FBC_CMD6)
A18
FBB_CMD27 (FBC_CMD13)
D17
FBB_CMD28 (FBC_CMD19)
A17
FBB_CMD29 (FBC_CMD12)
B17
FBC_CMD30
E17
FBC_CMD31 (NC)
E11
FBC_DQM0
E3
FBC_DQM1
A3
FBC_DQM2
C9
FBC_DQM3
F23
FBC_DQM4
F27
FBC_DQM5
C30
FBC_DQM6
A24
FBC_DQM7
D10
FBC_DQS_WP0
D5
FBC_DQS_WP1
C3
FBC_DQS_WP2
B9
FBC_DQS_WP3
E23
FBC_DQS_WP4
E28
FBC_DQS_WP5
B30
FBC_DQS_WP6
A23
FBC_DQS_WP7
D9
FBC_DQS_RN0
E4
FBC_DQS_RN1
B2
FBC_DQS_RN2
A9
FBC_DQS_RN3
D22
FBC_DQS_RN4
D28
FBC_DQS_RN5
A30
FBC_DQS_RN6
B23
FBC_DQS_RN7
6
MEMORY I/F C
GK107
FBA_DEBUG0
FBA_DEBUG1
FBB_WCKBxx are reserved
NC ON : GM108/GM107
USED ON : GK107
6
NC
NC
FBB_WCK01_N
FBB_WCK23_N
FBB_WCK45_N
FBB_WCK67_N
FBB_WCKB01_N
FBB_WCKB23_N
FBB_WCKB45_N
FBB_WCKB67_N
FBB_PLL_AVDD
FBC_D00
FBC_D01
FBC_D02
FBC_D03
FBC_D04
FBC_D05
FBC_D06
FBC_D07
FBC_D08
FBC_D09
FBC_D10
FBC_D11
FBC_D12
FBC_D13
FBC_D14
FBC_D15
FBC_D16
FBC_D17
FBC_D18
FBC_D19
FBC_D20
FBC_D21
FBC_D22
FBC_D23
FBC_D24
FBC_D25
FBC_D26
FBC_D27
FBC_D28
FBC_D29
FBC_D30
FBC_D31
FBC_D32
FBC_D33
FBC_D34
FBC_D35
FBC_D36
FBC_D37
FBC_D38
FBC_D39
FBC_D40
FBC_D41
FBC_D42
FBC_D43
FBC_D44
FBC_D45
FBC_D46
FBC_D47
FBC_D48
FBC_D49
FBC_D50
FBC_D51
FBC_D52
FBC_D53
FBC_D54
FBC_D55
FBC_D56
FBC_D57
FBC_D58
FBC_D59
FBC_D60
FBC_D61
FBC_D62
FBC_D63
FBC_CLK0
FBC_CLK0_N
FBC_CLK1
FBC_CLK1_N
GM107
FBB_CMD32
FBB_CMD33
FBB_CMD34
FBB_CMD35
FBB_WCK01
FBB_WCK23
FBB_WCK45
FBB_WCK67
FBB_WCKB01
FBB_WCKB23
FBB_WCKB45
FBB_WCKB67
7
VMC_DQ0
G9
VMC_DQ1
E9
VMC_DQ2
G8
VMC_DQ3
F9
VMC_DQ4
F11
VMC_DQ5
G11
VMC_DQ6
F12
VMC_DQ7
G12
VMC_DQ8
G6
VMC_DQ9
F5
VMC_DQ10
E6
VMC_DQ11
F6
VMC_DQ12
F4
VMC_DQ13
G4
VMC_DQ14
E2
VMC_DQ15
F3
VMC_DQ16
C2
VMC_DQ17
D4
VMC_DQ18
D3
VMC_DQ19
C1
VMC_DQ20
B3
VMC_DQ21
C4
VMC_DQ22
B5
VMC_DQ23
C5
VMC_DQ24
A11
VMC_DQ25
C11
VMC_DQ26
D11
VMC_DQ27
B11
VMC_DQ28
D8
VMC_DQ29
A8
VMC_DQ30
C8
VMC_DQ31
B8
VMC_DQ32
F24
VMC_DQ33
G23
VMC_DQ34
E24
VMC_DQ35
G24
VMC_DQ36
D21
VMC_DQ37
E21
VMC_DQ38
G21
VMC_DQ39
F21
VMC_DQ40
G27
VMC_DQ41
D27
VMC_DQ42
G26
VMC_DQ43
E27
VMC_DQ44
E29
VMC_DQ45
F29
VMC_DQ46
E30
VMC_DQ47
D30
VMC_DQ48
A32
VMC_DQ49
C31
VMC_DQ50
C32
VMC_DQ51
B32
VMC_DQ52
D29
VMC_DQ53
A29
VMC_DQ54
C29
VMC_DQ55
B29
VMC_DQ56
B21
VMC_DQ57
C23
VMC_DQ58
A21
VMC_DQ59
C21
VMC_DQ60
B24
VMC_DQ61
C24
VMC_DQ62
B26
VMC_DQ63
C26
D12
E12
E20
F20
FBB_DEBUG0_K
G14
FBB_DEBUG1_K
G20
FBB_DEBUG0
C12
FBB_DEBUG1
C20
F8
E8
A5
A6
D24
D25
B27
C27
D6
D7
C6
B6
F26
E26
A26
A27
FB_PLLAVDD
H17
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Monday, May 25, 2015
Monday, May 25, 2015
Monday, May 25, 2015
Date: Sheet of
Date: Sheet of
Date: Sheet of
7
VMC_CLK0 24
VMC_CLK0# 24
VMC_CLK1 25
VMC_CLK1# 25
VMC_WCK01 24
VMC_WCK01# 24
VMC_WCK23 24
VMC_WCK23# 24
VMC_WCK45 25
VMC_WCK45# 25
VMC_WCK67 25
VMC_WCK67# 25
C276 close to H17 (under GPU)
12
0.1U/16V/X7R_4
C295
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
PROJECT :
N16P-GX - 2/5 (Memory)
N16P-GX - 2/5 (Memory)
N16P-GX - 2/5 (Memory)
8
R52*60.4/F_4_NC
R48*60.4/F_4_NC
R51*60.4/F_4_NC
R44*60.4/F_4_NC
AM9A
AM9A
AM9A
18 57
18 57
18 57
8
+1.35V_GFX
A0
A0
A0
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