Dell 7447 Schematic
1
2
3
4
5
6
7
8
01
Project : AM7
(14.0")
MB Schematic
PCB Rev: C0
Build: DVT2
Block Diagram
A A
HDMI Conn.
Channel A
DDR3L SO-DIMM
Channel B
DDR3L SO-DIMM
B B
HDD
PAGE 35
PAGE 18
PAGE 19
PAGE 31
INT HDMI
DDR3L 1600 MT/s 1.35V
DDR3L 1600 MT/s 1.35V
SATA3 6GB /S
SYSTEM MEMORY
Port4
CPU
Haswell
Processor : Quad Core
Power : 47 (Watt)
Package : BGA1364
Size : 37.5 x 32 (mm)
PAGE 07~11
5GT/s
DMI X 4
PEG x 8
eDP
PCIE
PCIE Port 3
Giga LAN
Intel
RTL8111GU
Mobile Intel
ODD (Tray)
SATA3 6GB /S
PAGE 31
Port5
Lynx Point
(HM87)
Flash ROM
8 MB
C C
Flash ROM
8 MB
Touch Pad
Universal Jack
D D
SPEAKER
Sub Woofer
1
PAGE 30
PAGE 30
PAGE 36
K/B
PAGE 36
FAN
PAGE 38 PAGE 29
PAGE 32
SPI
SMbus
PS/2
Package : LQPF128
Audio Codec
ALS-3234
PAGE 32
PAGE 33
2
SPI (CS0)
HSPI
EC
ITE
IT8528E
Realtek
PAGE 32
Platform Controller Hub
Power : 3 Watt
Package : FCBGA695
Size : 20 x 20 (mm)
LPC
PAGE 12~17
HDA
AMP
ANPEC
ALC1003-CGT
PAGE 33
3
4
USB2.0
PCIE
Card Reader
Realtek
RTS5176E
9 x 9mm
USB2.0
Port 8
Camera
PAGE 34
USB3.0
5
GPU
Nvidia
N15P-GT
35W 29 x 29 mm
PAGE 20~24
DB PAGE 2
PAGE 40
Port 11
6
TRANSFORMER
USB 3.0
DDR3L x 8
(256 Mb x 16)
14.0" eDP Panel
DB PAGE 2
PCIE Port 4
SD slot
PAGE 40
Port 0 Port 5
PAGE 25~28
PAGE 34
Port 1
USB 3.0
PAGE 39
Port 1 Port 2
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
W / Power Share
BLOCK DIAGRAM
BLOCK DIAGRAM
Thursday, May 08, 2014
Thursday, May 08, 2014
Thursday, May 08, 2014
BLOCK DIAGRAM
7
DB
RJ45
DB PAGE 2
USB 2.0 CONN
DB PAGE 3
NGFF
WLAN + BT
PAGE 41
Port 9
PAGE 39
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
PROJECT :
AM7
AM7
AM7
1 51
1 51
1 51
8
C0
C0
C0
1
2
3
4
5
6
7
8
AM7 GPU Power UP sequence
AM7 GPU GC62.0 Entry/Exit sequence
02
Note.0
PEX_LINK
A A
DGPU_PWR_EN
(PCH)
251us, DGPU_PWR_EN to +3V_AON
+3V_AON
+3V_MAIN_EN
(GPU)
+3V_GFX
150us, +3V_MAIN_EN to +3V_GFX
90%
GPU_PEX_RST_HOLD#
(GPU)
PEGX_RST#
GC6_FB_EN
+3V_AON
GPU Detects PCIE link disabled
Keep High
+3V_MAIN_EN
3V3_MAIN_PWRGD
(+3V_GFX)
1.23ms, 3V3_MAIN_PWRGD to +VGACORE
90%
+VGACORE
B B
+1.05V_GFX
1.23ms, 3V3_MAIN_PWRGD to +1.05V_GFX
90%
DGPU_VC_EN
(+VGACORE_PWRGD)
1.09ms, DGPU_VC_EN to +1.35V_GFX
(GPU)
+3V_GFX
3V3_MAIN_PWRGD
(+3V_GFX)
+VGACORE
+1.05V_GFX
DGPU_VC_EN
(+VGACORE_PWRGD)
+1.35V_GFX
DGPU_PWROK
+1.35V_GFX
DGPU_PWROK
Keep High
Note.1
Note.2
GPU_EVENT#
GC6 Entry GC6 Exit
T0 min = 0.001ms.
Note.0 : GPU driver ACPI call SBIOS to disables PCIE link.
Note.1 : When GC6 2.0 mode, +1.35V_GFX enabled by GC6_FB_EN
C C
Note.2 : GPU driver ACPI call SBIOS then confirm entry complete by
sensing GC6_FB_EN =1, Enable PCIE Link. Then PCH asserts GPU_EVENT#
Note.3 : SBIOS detects GC6_FB_EN =0, then De-asserts GPU_EVENT#
P.S. The entire entry and exit sequence must complete within 200 ms
Detect TrainActive
T1 0.04ms < T1 < 4ms.
Note.3
AM7 Optimus GPU On/Off sequence
PEGX_RST#
(PCH DGPU_HOLD_RST# control)
DGPU_PWR_EN
(PCH)
D D
DGPU_PWROK
(All Rail PGOOD)
0ms< T0 < 5ms
T0 = 220 us, PEGX_RST# to DGPU_PWR_EN
2.21 ms, DGPU_PWR_EN to DGPU_PWROK
0.1ms < T1 < 5ms
< 200ms
< 200ms
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
P.S. The entire entry and exit sequence must
complete within 200 ms
1
2
3
4
5
6
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Thursday, May 08, 2014
Date: Sheet of
Thursday, May 08, 2014
Date: Sheet of
Thursday, May 08, 2014
7
PROJECT :
PROJECT :
PROJECT :
GPU Sequence
GPU Sequence
GPU Sequence
AM7
AM7
AM7
2 51
2 51
2 51
8
C0
C0
C0
5
4
3
2
1
03
Adapter 90W
D D
Charger
BQ24737RGRR
PWR_SRC
VER : 1A
Battery 3S2P
SLP_S4# DGPU_VC_EN
TI
TPS51225RUKR
C C
+15V_ALW
+5V_ALW
RUN_ON DGPU_PWR_EN
Load Switch
AON7506
+3.3V_RUN
B B
Load Switch
AO6402A
+3.3V_SUS
SUS_ON
RUN_ON
Load Switch
AO6402A
+3V_AON +5V_RUN
Load Switch
AO6402A
+3V_GFX
GMT (LDO)
G9661-25ADJTP1U
+1.5V_RUN
Load Switch
AON7507
RUN_ONAONON
TI
TPS51216RUKR
+V_VDDQ+3.3V_ALW
DGPU_PWR_ON#
Load Switch
RQ3E150BNFU7TB
+1.35_GFX
+DDR_VTT
Richtek
RT8228AZQW
Load Switch
AON7508
+1.05_GFX
+1.05V
RUN_ON+3.3V_EN2 ALW_ON
DGFX_VR_PWRGD
ONSemi
NCP81172MNTXG
+VGACORE
IMVP_VR_ON
TI
TPS51631ARSMR
+VCCIN
A A
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Power Block Diagram
Power Block Diagram
Power Block Diagram
Date: Sheet of
Thursday, May 08, 2014 3 51
Date: Sheet of
Thursday, May 08, 2014 3 51
Date: Sheet of
5
4
3
2
Thursday, May 08, 2014 3 51
PROJECT :
AM7
AM7
AM7
1
C0
C0
C0
1
04
A A
+PWR_SRC
+V_VDDQ
B B
C C
AM7 PSequence G3 to S0 Block (Battery mode)
+5V_ALW
VCC
DDR/0.675V
VR
S3
S4
+V_VDDQ
+DDR_VTT
DDR_PWRGD
PG
2
SIO_SLP_S3#
SIO_SLP_S4#
16
18
17
15
1.05V_PWRGD
2414
3
PWR SW
3
POWER_ SW_IN0#
25
HWPG
SUS_ON
8
+3.3V_ALW
VCC
RUN_ON
19
4
EC_PWROK
2634
2
+3.3V_RTC_LDO
SYS_PWR_SW#
EC
IMVP_VR_ON
SIO_SLP_S3#
4
3.3V_ALW_ON
4
SIO_SLP_S5#
SIO_SLP_S4#
131415
3V/5V
VR
6
5
+PWR_SRC
VCC
EN2
ALW_ON
RSMRST#
AC_PRESENT
EC_PWRBTN#
6
+3.3V_RTC_LDO
+3.3V_ALW
+5V_ALW
+15V_ALW
EN1
5
+PWR_SRC
7
7
10
11
12
13
14
15
25
28
29
30
35
34
7
1
SLP_S5#
SLP_S4#
SLP_S3#
HWPG
IMVP_PWRGD
PM_DRAM_PWRGD
PCH_CLK
PCI_PLTRST#
EC_PWROK
8
0
+VCHGR
CHARGER Battery
RSMRST#(DPWROK)
ACPRESENT
PWRBTN#
SLP_S5#
SLP_S4#
SLP_S3#
APWROK
PWROK
DRAMPWROK
PCH_CLK
PLTRST#
SYS_PWROK
PCH
PLTRST_PROC#
+5V_ALW
+PWR_SRC
VCC
+1.05V
20
1.05V
VR
EN
+3.3V_ALW
+3.3V_ALW
D D
VCC
1.5V
PG
1.05V_PWRGD
RUN_ON
+1.5V_RUN
24
19
22
+5V_ALW
+3.3V_ALW
G
G
SUS
LS
RUN
LS
G
SUS_ON
+3.3V_SUS+3V_ALW
+5V_RUN
+3.3V_RUN
9
+PWR_SRC
PG
27
+VCCIN
IMVP_PWRGD
IMVP_VR_ON
28
26
PM_DRAM_PWRGD
29
SVID
33
21
23
8
+PWR_SRC
VCC
IMVP
VR
EN
33
SVID
SVID
H_PWRGOOD
31
CPU
CPU_PLTRST#
36
32
VCCIO_OUT
PWRGOOD PROCPWRGD
PLTRSTIN#
CPU
VR
EN
RUN_ON
19
1
2
3
RUN_ON
RUN_ON
19
Quanta Computer Inc.
Quanta Computer Inc.
19
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Thursday, May 08, 2014 4 51
Date: Sheet of
Thursday, May 08, 2014 4 51
Date: Sheet of
4
5
6
Thursday, May 08, 2014 4 51
7
Quanta Computer Inc.
PROJECT :
PROJECT :
PROJECT :
PSeq_G3 to S0 Block_vPRO
PSeq_G3 to S0 Block_vPRO
PSeq_G3 to S0 Block_vPRO
AM7
AM7
AM7
8
C0
C0
C0
1
2
3
4
5
6
7
8
AM7 PSequence G3 to S0
05
+PWR_SRC
+5V_ALW2 and
+3.3V_RTC_LDO
POWER_ SW_IN0#
A A
3.3V_ALW_ON
+3.3V_ALW
ALW_ON
+5V_ALW
+15V_ALW
SYS_PWR_SW#
SUS_ON(EC)
+3.3V_SUS
+5V_SUS
RSMRST#(EC)
(DPWROK, suspend power well)
EC_PWRBTN# (EC)
B B
SIO_SLP_S5#(PCH)
SIO_SLP_S4#(PCH)
+V_VDDQ
DDR_PWRGD
SIO_SLP_S3#(PCH)
+DDR_VTT
RUN_ON(EC)
+1.05V
+1.5V_RUN
C C
+3.3V_RUN
+5V_RUN
HWPG (APWROK)
(1.05V_PWRGD)
IMVP_VR_ON(EC)
+VCC_CORE
(CPU CORE)
IMVP_PWRGD
(PWROK)
PM_DRAM_PWRGD
PCH CLK
H_PWRGOOD(PCH)
(PWRGOOD)
VCCIO_OUT
D D
CPU SVID BUS(CPU)
SYS_PWROK
(EC_PWROK)
PLTRST#
1
G3 mode: > EC reset time + output ALW_ON
S5 mode: > Power button DE-BOUNCE time
G3 mode: Asserted by HW latch of power button event
S0 mode: Be keeped on high by ALW_ON
G3 mode: > 1650 Tick (50 ms)
Thd = 500 us
(EC)
2
G3 mode: EC don't care this event.
S5 mode: Upon power always exist, and this pin keeped on high. Start from this event.
528 ms (EC, ALW_ON to SUS_ON, EC)
37.6 ms (VCCDSW(+3.3V_SUS) to DPWROK(RSMRST#), t04=min 10ms)
(+3.3V_SUS to RSMRST#, t05=min 10ms)
minimum duration of PWRBTN# assertion=16ms. PWRBTN# can assert before or after than RSMRST#
102 ms (RSMRST# to SLP_S5, t07=min 5ms)
35.2 us (SLP_S5 to SLP_S4, t09=min 30us)
27ms (+V_VDDQ to DDR_PWRGD, t44=min 100ns)
VDDQ (CPU) (-20% of nominal value) to VR_VDDQPWRGD
70.2 us (SLP_S4 to SLP_S3, t10=min 30us)
22 ms(SLP_S3# to RUN_ON,EC)
EC: SIO_SLP_S3# to RUN_ON delay ?ms
163 ms (VccSUS (+3.3_SUS) to VccASW (+1.05V_PCH), t29= min 0ms)
163 ms (+3.3V_SUS to +1.05V, t31 =min 0ms)
2 ms(+1.05V stable to +1.5V_RUN stable , min=0s)
5.68 ms(+1.05V stable to +3.3V_RUN stable , min=0s)
5.7 ms(VCCASW to APWROK, t11 mim =1ms)
APWROK may come up earlier than PWROK, but no later
EC: HWPG to IMVP_VR_ON delay 5ms
Vboot
15.3 ms(APWROK to PWROK, t30 mim =0ms)
15.3 ms(ALL_SYS_PWRGD (HWPG) to PW ROK, t14 mim =5ms)
20.9 ms(PCH CORE to PWROK, t41 mim =5ms)
18.2 ms(PWROK to PM_DRAM_PWRGD, t18 mim =0us)
3
4
(For a non-DeepSx system DPWROK and RSMRST# go high at the same time)
VCC_CORE turn on after SVID vaild.
valid
? ms(PCH CLK stable to H_PWRGOOD, t19 min = 1 ms)
23.6 ms(+VCC_CORE to H_PWRGOOD, min = 5<t13<650 ms)
23.6 ms(PWROK to H_PWRGOOD, t20 min = 2 ms)
124 ms(HPWG to SYS_PWROK, t15 min = 5~99 ms)
EC: HPWG to EC_PWROK(EC) Delay 100 ms
5
Last un-core power rail stable to DRAMPWROK assertion.
valid
2.08 ms (SYS_PWROK to PLTRST#, t21+t22 = min 1.06 ms)
PLTRST# could de-assert prior to final SVID value
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
6
Date: Sheet of
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
PROJECT :
06 PS_G3 to S0
06 PS_G3 to S0
06 PS_G3 to S0
Thursday, May 08, 2014 5 51
Thursday, May 08, 2014 5 51
Thursday, May 08, 2014 5 51
7
AM7
AM7
AM7
8
C0
C0
C0
5
4
3
2
1
06
D D
C C
B B
SMBus Block
SMB0
SMB3
EC
IT8528E
(128 Pin LQFP)
SMB1
PCH
INTEL
(HM87)
27mm X 25mm
Controller
SMLink0
Controller
SMLink1
+3.3V_ALW
4.7K 4.7K
MBCLK_BAT
MBDATA_BAT
+3V_RUN +3V_RUN
2.2K 2.2K
SMBCLK3
SMBDAT3
+3.3V_ALW
2.2K
SMB_RUN_CLK
SMB_RUN_DAT
+3.3V_SUS +3.3V_SUS
SMB_ME0_CLK
SMB_ME0_DAT
Slave address: 4BH
SMB_ME1_DAT
SMB_ME1_CLK
2.2K
+3.3V_ALW
+3V_GFX
G
D
NMOS
D
NMOS
+3.3V_ALW
+3.3V_SUS
2.2K 2.2K 2.2K
D
D
2.2K
G
NMOS
NMOS
+3V_AON +3V_AON
2.2K 2.2K
S
S
+3.3V_SUS +3.3V_SUS
S
S
Slave address: 03H
BAT/CHARGE
GFX_SCL
GFX_SDA
SMB_ME1_CLK
SMB_ME1_DAT
PCIe CLK
PORT 0
PORT 1
PORT 2
PORT 3
GIGA LAN
NGFF WLAN
PORT 4
PORT 5
PORT 6
PORT 7
Slave address: 1001100xb (98h)
CPU
Thermal Sensor
NCT7718W
Slave address: 10011110 (0X9Eh)
GPU
N15P-GT
X
X
X
X
X
X
HSIO Port
PORT 1
PORT 2
PORT 3
PORT 4
PORT 5
PORT 6
PORT 7
PORT 8
PORT 9
PORT 10
PORT 11
PORT 12
PORT 13
PORT 14
PORT 15
PORT 16
PORT 17
PORT 18
HM87 AM7
USB3.0
PORT1
USB3.0
PORT2
USB3.0
PORT5
USB3.0
PORT6
PCIe*
Port 3
PCIe*
Port 4
PCIe*
Port 1
PCIe*
Port 2
GIGA LAN
NGFF WLAN
USB3.0
PORT3
USB3.0
PORT4
PCIe*
Port 5
PCIe*
Port 6
PCIe*
Port 7
PCIe*
Port 8
SATA 6Gb/s
PCIe*
Port 1
PCIe*
Port 2
Port 4
SATA 6Gb/s
Port 5
SATA HDD
SATA ODD
SATA 6Gb/s
Port 0
SATA 6Gb/s
Port 1
SATA 3Gb/s
Port 2
SATA 3Gb/s
Port 3
USB 3.0
CONN 1
USB 3.0
CONN 2
X
X
X
X
X
X
X
X
X
X
X
X
USB 2.0
EHCI #1
PORT 0
PORT 1
PORT 2
PORT 3
PORT 4
PORT 5
PORT 6
PORT 7
USB3.0 Conn
USB2.0 CONN / DB
X
X
X
USB3.0 Conn / PS
X
X
EHCI #2
PORT 8
PORT 9
PORT 10
PORT 11
PORT 12
PORT 13
Camera
BT
X
Card reader
X
X
+3.3V_SUS +3.3V_SUS
A A
2.2K 2.2K
HOST
SMBUS
5
SMB_PCH_CLK
SMB_PCH_DAT
+3V_RUN
G
D
NMOS
D
NMOS
4
+3V_RUN +3V_RUN
2.2K 2.2K
S
S
SMB_RUN_CLK
SMB_RUN_DAT
Slave address: A0H Slave address: A4H
DDR3L-SODIMM
CH.A(STD)
3
DDR3L-SODIMM
CH.B(STD)
Slave address: 2CH
Touch PAD
2
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
PROJECT :
AM7
AM7
AM7
SMBus Block
SMBus Block
SMBus Block
1
6 51Thursday, May 08, 2014
6 51Thursday, May 08, 2014
6 51Thursday, May 08, 2014
C0
C0
C0
5
4
3
2
1
Haswell Processor (DMI,PEG,FDI)
+1V_VCOMP_OUT
07
FDI_CSYNC_R
FDI_INT_R
R581
*1K_4_NC
DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3
DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3
DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3
DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3
DMI_TXN0[12]
DMI_TXN1[12]
D D
FDI_CSYNC[12]
FDI_INT[12]
C C
B B
Layout note:
FDI_CSYNC & FDI_INT
Trace length < 10000 Mils
Impendance = 50 ohm
DMI_TXN2[12]
DMI_TXN3[12]
DMI_TXP0[12]
DMI_TXP1[12]
DMI_TXP2[12]
DMI_TXP3[12]
DMI_RXN0[12]
DMI_RXN1[12]
DMI_RXN2[12]
DMI_RXN3[12]
DMI_RXP0[12]
DMI_RXP1[12]
DMI_RXP2[12]
DMI_RXP3[12]
R750 0_4
R751 0_4
AB2
AB3
AC3
AC1
AB1
AB4
AC4
AC2
AF2
AF4
AG4
AG2
AF1
AF3
AG3
AG1
F11
F12
R582
*1K_4_NC
U1A
DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3
DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3
DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3
DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3
FDI_CSYNC
DISP_INT
HASWELL_BGA_E
DMI
FDI
1 OF 12
PEG_RCOMP
PEG
PEG_RXN0
PEG_RXN1
PEG_RXN2
PEG_RXN3
PEG_RXN4
PEG_RXN5
PEG_RXN6
PEG_RXN7
PEG_RXN8
PEG_RXN9
PEG_RXN10
PEG_RXN11
PEG_RXN12
PEG_RXN13
PEG_RXN14
PEG_RXN15
PEG_RXP0
PEG_RXP1
PEG_RXP2
PEG_RXP3
PEG_RXP4
PEG_RXP5
PEG_RXP6
PEG_RXP7
PEG_RXP8
PEG_RXP9
PEG_RXP10
PEG_RXP11
PEG_RXP12
PEG_RXP13
PEG_RXP14
PEG_RXP15
PEG_TXN0
PEG_TXN1
PEG_TXN2
PEG_TXN3
PEG_TXN4
PEG_TXN5
PEG_TXN6
PEG_TXN7
PEG_TXN8
PEG_TXN9
PEG_TXN10
PEG_TXN11
PEG_TXN12
PEG_TXN13
PEG_TXN14
PEG_TXN15
PEG_TXP0
PEG_TXP1
PEG_TXP2
PEG_TXP3
PEG_TXP4
PEG_TXP5
PEG_TXP6
PEG_TXP7
PEG_TXP8
PEG_TXP9
PEG_TXP10
PEG_TXP11
PEG_TXP12
PEG_TXP13
PEG_TXP14
PEG_TXP15
AH6
E10
C10
B10
E9
D9
B9
L5
L2
M4
L4
M2
V5
V4
V1
Y3
Y2
F10
D10
A10
F9
C9
A9
M5
L1
M3
L3
M1
Y5
V3
V2
Y4
Y1
B6
C5
E6
D4
G4
E3
J5
G3
J3
J2
T6
R6
R2
R4
T4
T1
C6
B5
D6
E4
G5
E2
J6
G2
J4
J1
T5
R5
R1
R3
T3
T2
PEG_RCOMP
PEG_RXN7
PEG_RXN6
PEG_RXN5
PEG_RXN4
PEG_RXN3
PEG_RXN2
PEG_RXN1
PEG_RXN0
PEG_RXP7
PEG_RXP6
PEG_RXP5
PEG_RXP4
PEG_RXP3
PEG_RXP2
PEG_RXP1
PEG_RXP0
PEG_TXN7
PEG_TXN6
PEG_TXN5
PEG_TXN4
PEG_TXN3
PEG_TXN2
PEG_TXN1
PEG_TXN0
PEG_TXP7
PEG_TXP6
PEG_TXP5
PEG_TXP4
PEG_TXP3
PEG_TXP2
PEG_TXP1
PEG_TXP0
R1
24.9/F_4
Layout note:
PEG_RCOMP
TL <= 400 mils
TW >= 12 mils
TS >= 15 mils
PEG_RXN7 [20]
PEG_RXN6 [20]
PEG_RXN5 [20]
PEG_RXN4 [20]
PEG_RXN3 [20]
PEG_RXN2 [20]
PEG_RXN1 [20]
PEG_RXN0 [20]
PEG_RXP7 [20]
PEG_RXP6 [20]
PEG_RXP5 [20]
PEG_RXP4 [20]
PEG_RXP3 [20]
PEG_RXP2 [20]
PEG_RXP1 [20]
PEG_RXP0 [20]
PEG_TXN7 [20]
PEG_TXN6 [20]
PEG_TXN5 [20]
PEG_TXN4 [20]
PEG_TXN3 [20]
PEG_TXN2 [20]
PEG_TXN1 [20]
PEG_TXN0 [20]
PEG_TXP7 [20]
PEG_TXP6 [20]
PEG_TXP5 [20]
PEG_TXP4 [20]
PEG_TXP3 [20]
PEG_TXP2 [20]
PEG_TXP1 [20]
PEG_TXP0 [20]
SM_DRAMPWROK# Topology
+V_VDDQ
DVT2
PM_DRAM_PWRGD[12]
CPU PU/PD setting
CPU_DBR#
PDG 2.2 recommend 100R,
CRB use 1kR.
DS V2.2 -> 1K Ω PU,
CHKRST V2.0 -> 1K Ω PU,
CRB-GR V0.7 -> 100 Ω PU
PM_THRMTRIP#
CPU_TDO
H_PWRGOOD_R
CPU_TCK
CPU_TRST#
R3
1.8K/F_4
R6
3.3K/F_4
R9 *1K_4_NC
R11 *1K_4_NC
R12 *51_4_NC
R14 10K_4
R15 *51_4_NC
R16 *51_4_NC
SM_DRAMPWROK
0.45 * VDDQ < VIH <1.0V
+3.3V_RUN
PM_THRMTRIP# :
+1.05V
Broadwell need PU (OD pin)
HSW is CMOS OUTPUT
Haswell Processor (CLK,MISC,JTAG)
Layout note:
SM_RCOMP[0:2]
TL < 500 mils
U1B
SKTOCC#
TP107
CATERR#
TP109
CPU_PECI[29]
PM_THRMTRIP#[15]
112
112
112
2
2
2
PM_SYNC[12]
H_PWRGOOD[15]
CPU_PLTRST#[15]
A A
R31 *SJ0402_NC
R32 *SJ0402_NC
R33 *SJ0402_NC
CLK_DPLL_NSCLKN[14]
CLK_DPLL_NSCLKP[14]
CLK_DPLL_SSCLKN[14]
CLK_DPLL_SSCLKP[14]
CLK_CPU_BCLKN[14]
CLK_CPU_BCLKP[14]
5
H_PROCHOT#
PM_THRMTRIP#
PM_SYNC_R
H_PWRGOOD_R
PM_DRAM_PWRGD
CPU_RST#_R
CLK_DPLL_NSCLKN
CLK_DPLL_NSCLKP
CLK_DPLL_SSCLKN
CLK_DPLL_SSCLKP
CLK_CPU_BCLKN
CLK_CPU_BCLKP
C51
PROC_DETECT
G50
CATERR
G51
PECI
E50
PROCHOT
D53
THERMTRIP
D52
PM_SYNC
F50
PWRGOOD
AP48
SM_DRAMPW ROK
L54
PLTRSTIN
AC6
DPLL_REF_CLKN
AE6
DPLL_REF_CLKP
V6
SSC_DPLL_REF_CLKN
Y6
SSC_DPLL_REF_CLKP
AB6
BCLKN
AA6
BCLKP
4
HASWELL_BGA_E
MISC
PWRTHERMAL
CLOCK
2 OF 12
SM_RCOMP0
SM_RCOMP1
SM_RCOMP2
SM_DRAMRST
JTAG DDR3
PRDY
PREQ
TCK
TMS
TRST
TDO
DBR
BPM#0
BPM#1
BPM#2
BPM#3
BPM#4
BPM#5
BPM#6
BPM#7
TDI
BB51
SM_RCOMP_0
BB53
SM_RCOMP_1
BB52
SM_RCOMP_2
BE51
DDR3_DRAMRST#
N53
CPU_PRDY#
N52
CPU_PREQ#
N54
CPU_TCK
M51
CPU_TMS
M53
CPU_TRST#
N49
CPU_TDI
M49
CPU_TDO
F53
CPU_DBR#
R51
R50
P49
N50
R49
P53
U51
P51
R26 100/F_4
R29 75/F_4
R30 100/F_4
3
TW = 12~15 mils
Self TS >= 20 mils
Other TS >= 25 mils
DDR3_DRAMRST# [18]
TP110
TP111
TP112
TP113
TP114
TP115
TP116
CPU_DBR# [12]
PROCHOT# Topology
+1V_VCCIO_OUT
VR DS pg11.
>100 deg.C assert.
<97 deg.C de-assert.
IMVP7_PROCHOT#[29,44,49]
2
PDG v2.2
R34
62_4
R35 56_4
Layout note:
Clost to CPU
H_PROCHOT#
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Thursday, May 08, 2014
Date: Sheet of
Thursday, May 08, 2014
Date: Sheet of
Thursday, May 08, 2014
PROJECT :
Haswell 1/5 (PEG/DMI/FDI)
Haswell 1/5 (PEG/DMI/FDI)
Haswell 1/5 (PEG/DMI/FDI)
AM7
AM7
AM7
7 51
7 51
1
7 51
C0
C0
C0
5
4
3
2
1
08
D D
C C
B B
Haswell Processor (DDR3) Haswell Processor (DDR3)
U1C
BD31
RSVD
M_A_BS#0
M_A_BS#1
M_A_BS#2
M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15
BE25
BF25
BE34
BD25
BC25
BF34
BE23
BF23
BC34
BD23
BC23
BD34
BE16
BC17
BE17
BD16
BC16
BF16
BF17
BD17
BC20
BD21
BD32
BC21
BF20
BF21
BE21
BD28
BD27
BF28
BE28
BF32
BC27
BF27
BC28
BE27
BC32
BD20
BF31
BC31
BE20
BE32
BE31
AJ52
AP53
AW52
AY46
BD12
BE7
BA3
AT2
AW39
AJ53
AP52
AW53
BA46
BE12
BD7
BA2
AT3
AW40
BA40
AY40
BA39
AY39
AV40
AU40
AV39
AU39
SA_CKN0
SA_CK0
SA_CKE0
SA_CKN1
SA_CK1
SA_CKE1
SA_CKN2
SA_CK2
SA_CKE2
SA_CKN3
SA_CK3
SA_CKE3
SA_CS#0
SA_CS#1
SA_CS#2
SA_CS#3
SA_ODT0
SA_ODT1
SA_ODT2
SA_ODT3
SA_BS0
SA_BS1
SA_BS2
VSS
SA_RAS
SA_WE
SA_CAS
SA_MA0
SA_MA1
SA_MA2
SA_MA3
SA_MA4
SA_MA5
SA_MA6
SA_MA7
SA_MA8
SA_MA9
SA_MA10
SA_MA11
SA_MA12
SA_MA13
SA_MA14
SA_MA15
SA_DQSN0
SA_DQSN1
SA_DQSN2
SA_DQSN3
SA_DQSN4
SA_DQSN5
SA_DQSN6
SA_DQSN7
RSVD
SA_DQS0
SA_DQS1
SA_DQS2
SA_DQS3
SA_DQS4
SA_DQS5
SA_DQS6
SA_DQS7
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
M_A_CLKN0[18]
M_A_CLKP0[18]
M_A_CKE0[18]
M_A_CLKN1[18]
M_A_CLKP1[18]
M_A_CKE1[18]
M_A_CS#0[18]
M_A_CS#1[18]
M_A_ODT0[18]
M_A_ODT1[18]
M_A_BS#[2:0][18] M_B_BS#[2:0][19]
M_A_RAS#[18]
M_A_WE#[18]
M_A_CAS#[18]
M_A_A[15:0][18]
M_A_DQSN[7:0][18]
M_A_DQSP[7:0][18]
M_A_DQSN0
M_A_DQSN1
M_A_DQSN2
M_A_DQSN3
M_A_DQSN4
M_A_DQSN5
M_A_DQSN6
M_A_DQSN7
M_A_DQSP0
M_A_DQSP1
M_A_DQSP2
M_A_DQSP3
M_A_DQSP4
M_A_DQSP5
M_A_DQSP6
M_A_DQSP7
HASWELL_BGA_E
3 OF 12
SA_DQ0
SA_DQ1
SA_DQ2
SA_DQ3
SA_DQ4
SA_DQ5
SA_DQ6
SA_DQ7
SA_DQ8
SA_DQ9
SA_DQ10
SA_DQ11
SA_DQ12
SA_DQ13
SA_DQ14
SA_DQ15
SA_DQ16
SA_DQ17
SA_DQ18
SA_DQ19
SA_DQ20
SA_DQ21
SA_DQ22
SA_DQ23
SA_DQ24
SA_DQ25
SA_DQ26
SA_DQ27
SA_DQ28
SA_DQ29
SA_DQ30
SA_DQ31
SA_DQ32
SA_DQ33
SA_DQ34
SA_DQ35
SA_DQ36
SA_DQ37
SA_DQ38
SA_DQ39
SA_DQ40
SA_DQ41
SA_DQ42
SA_DQ43
SA_DQ44
SA_DQ45
SA_DQ46
SA_DQ47
SA_DQ48
SA_DQ49
SA_DQ50
SA_DQ51
SA_DQ52
SA_DQ53
SA_DQ54
SA_DQ55
SA_DQ56
SA_DQ57
SA_DQ58
SA_DQ59
SA_DQ60
SA_DQ61
SA_DQ62
SA_DQ63
SM_VREF
SA_DIMM_VREFDQ
SB_DIMM_VREFDQ
RSVD
AH54
M_A_DQ0
AH52
M_A_DQ1
AK51
M_A_DQ2
AK54
M_A_DQ3
AH53
M_A_DQ4
AH51
M_A_DQ5
AK52
M_A_DQ6
AK53
M_A_DQ7
AN54
M_A_DQ8
AN52
M_A_DQ9
AR51
M_A_DQ10
AR53
M_A_DQ11
AN53
M_A_DQ12
AN51
M_A_DQ13
AR52
M_A_DQ14
AR54
M_A_DQ15
AV52
M_A_DQ16
AV53
M_A_DQ17
AY52
M_A_DQ18
AY51
M_A_DQ19
AV51
M_A_DQ20
AV54
M_A_DQ21
AY54
M_A_DQ22
AY53
M_A_DQ23
AY47
M_A_DQ24
AY49
M_A_DQ25
BA47
M_A_DQ26
BA45
M_A_DQ27
AY45
M_A_DQ28
AY43
M_A_DQ29
BA49
M_A_DQ30
BA43
M_A_DQ31
BF14
M_A_DQ32
BC14
M_A_DQ33
BC11
M_A_DQ34
BF11
M_A_DQ35
BE14
M_A_DQ36
BD14
M_A_DQ37
BD11
M_A_DQ38
BE11
M_A_DQ39
BC9
M_A_DQ40
BE9
M_A_DQ41
BE6
M_A_DQ42
BC6
M_A_DQ43
BD9
M_A_DQ44
BF9
M_A_DQ45
BE5
M_A_DQ46
BD6
M_A_DQ47
BB4
M_A_DQ48
BC2
M_A_DQ49
AW3
M_A_DQ50
AW2
M_A_DQ51
BB3
M_A_DQ52
BB2
M_A_DQ53
AW4
M_A_DQ54
AW1
M_A_DQ55
AU3
M_A_DQ56
AU1
M_A_DQ57
AR1
M_A_DQ58
AR4
M_A_DQ59
AU2
M_A_DQ60
AU4
M_A_DQ61
AR2
M_A_DQ62
AR3
M_A_DQ63
AM6
+SM_VREF
AR6
+VREFDQ_SA_CPU
AN6
+VREFDQ_SB_CPU
BC53
M_A_DQ[63:0] [18]
CPU VREFSA M3
R39 *SJ0603_NC
R37 *SJ0603_NC
R41 *SJ0603_NC
DVT2
2
112
2
112
2
112
CPU VREFDQ M3
M_B_CLKN0[19]
M_B_CLKP0[19]
M_B_CKE0[19]
M_B_CLKN1[19]
M_B_CLKP1[19]
M_B_CKE1[19]
M_B_CS#0[19]
M_B_CS#1[19]
M_B_ODT0[19]
M_B_ODT1[19]
M_B_RAS#[19]
M_B_WE#[19]
M_B_CAS#[19]
M_B_A[15:0][19]
M_B_DQSN[7:0][19]
M_B_DQSP[7:0][19]
+VREFSA_M3
+VREFDQ_SA_M3
+VREFDQ_SB_M3
M_B_BS#0
M_B_BS#1
M_B_BS#2
M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_A14
M_B_A15
M_B_DQSN0
M_B_DQSN1
M_B_DQSN2
M_B_DQSN3
M_B_DQSN4
M_B_DQSN5
M_B_DQSN6
M_B_DQSN7
M_B_DQSP0
M_B_DQSP1
M_B_DQSP2
M_B_DQSP3
M_B_DQSP4
M_B_DQSP5
M_B_DQSP6
M_B_DQSP7
AY36
AW27
AV27
AU36
AW26
AV26
AU35
BA26
AY26
AV35
BA27
AY27
AV36
BA20
AY19
AU19
AW20
AY20
BA19
AV19
AW19
AY23
BA23
BA36
AU30
AV23
AW23
AV20
BA30
AW30
AY30
AV30
AW32
AY32
AT30
AV32
BA32
AU32
AU23
AY35
AW35
AU20
AW36
BA35
AD52
AU46
BD48
BD43
AW16
AW10
AW8
AL2
BE38
AD53
AV46
BE48
BE43
AW15
AW12
AW6
AL3
BD38
BF39
BE39
BF37
BE37
BD39
BC39
BC37
BD37
U1D
RSVD
SB_CKN0
SB_CK0
SB_CKE0
SB_CKN1
SB_CK1
SB_CKE1
SB_CKN2
SB_CK2
SB_CKE2
SB_CKN3
SB_CK3
SB_CKE3
SB_CS#0
SB_CS#1
SB_CS#2
SB_CS#3
SB_ODT0
SB_ODT1
SB_ODT2
SB_ODT3
SB_BS0
SB_BS1
SB_BS2
VSS
SB_RAS
SB_WE
SB_CAS
SB_MA0
SB_MA1
SB_MA2
SB_MA3
SB_MA4
SB_MA5
SB_MA6
SB_MA7
SB_MA8
SB_MA9
SB_MA10
SB_MA11
SB_MA12
SB_MA13
SB_MA14
SB_MA15
SB_DQSN0
SB_DQSN1
SB_DQSN2
SB_DQSN3
SB_DQSN4
SB_DQSN5
SB_DQSN6
SB_DQSN7
RSVD
SB_DQS0
SB_DQS1
SB_DQS2
SB_DQS3
SB_DQS4
SB_DQS5
SB_DQS6
SB_DQS7
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
HASWELL_BGA_E
4 OF 12
SB_DQ0
SB_DQ1
SB_DQ2
SB_DQ3
SB_DQ4
SB_DQ5
SB_DQ6
SB_DQ7
SB_DQ8
SB_DQ9
SB_DQ10
SB_DQ11
SB_DQ12
SB_DQ13
SB_DQ14
SB_DQ15
SB_DQ16
SB_DQ17
SB_DQ18
SB_DQ19
SB_DQ20
SB_DQ21
SB_DQ22
SB_DQ23
SB_DQ24
SB_DQ25
SB_DQ26
SB_DQ27
SB_DQ28
SB_DQ29
SB_DQ30
SB_DQ31
SB_DQ32
SB_DQ33
SB_DQ34
SB_DQ35
SB_DQ36
SB_DQ37
SB_DQ38
SB_DQ39
SB_DQ40
SB_DQ41
SB_DQ42
SB_DQ43
SB_DQ44
SB_DQ45
SB_DQ46
SB_DQ47
SB_DQ48
SB_DQ49
SB_DQ50
SB_DQ51
SB_DQ52
SB_DQ53
SB_DQ54
SB_DQ55
SB_DQ56
SB_DQ57
SB_DQ58
SB_DQ59
SB_DQ60
SB_DQ61
SB_DQ62
SB_DQ63
AC54
AC52
AE51
AE54
AC53
AC51
AE52
AE53
AU47
AU49
AV43
AV45
AU43
AU45
AV47
AV49
BC49
BE49
BD47
BC47
BD49
BD50
BE47
BF47
BE44
BD44
BC42
BF42
BF44
BC44
BD42
BE42
BA16
AU16
BA15
AV15
AY16
AV16
AY15
AU15
AU12
AY12
BA10
AU10
AV12
BA12
AY10
AV10
AU8
BA8
AV6
BA6
AV8
AY8
AU6
AY6
AM2
AM3
AK1
AK4
AM1
AM4
AK2
AK3
M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63
M_B_DQ[63:0] [19]
A A
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Thursday, May 08, 2014
Date: Sheet of
Thursday, May 08, 2014
Date: Sheet of
5
4
3
2
Thursday, May 08, 2014
PROJECT :
Haswell 2/5 (DDR3 I/F)
Haswell 2/5 (DDR3 I/F)
Haswell 2/5 (DDR3 I/F)
1
AM7
AM7
AM7
8 51
8 51
8 51
C0
C0
C0
09
5
4
3
2
1
D D
HDMI
C C
Haswell Processor (DDI,eDP,FDI)
U1J
INT_HDMI_TXN2[35]
INT_HDMI_TXP2[35]
INT_HDMI_TXN1[35]
INT_HDMI_TXP1[35]
INT_HDMI_TXN0[35]
INT_HDMI_TXP0[35]
INT_HDMI_TXCN[35]
INT_HDMI_TXCP[35]
C25
D25
A25
B25
C24
D24
A24
B24
C21
D21
A21
B21
C20
D20
A20
B20
C16
D16
A16
B16
C17
D17
A17
B17
DDIB_TXN0
DDIB_TXP0
DDIB_TXN1
DDIB_TXP1
DDIB_TXN2
DDIB_TXP2
DDIB_TXN3
DDIB_TXP3
DDIC_TXN0
DDIC_TXP0
DDIC_TXN1
DDIC_TXP1
DDIC_TXN2
DDIC_TXP2
DDIC_TXN3
DDIC_TXP3
DDID_TXN2
DDID_TXP2
DDID_TXN3
DDID_TXP3
DDID_TXN0
DDID_TXP0
DDID_TXN1
DDID_TXP1
HASWELL_BGA_E
10 OF 12
EDP_AUXN
EDP_AUXP
EDP_HPD
EDP_TXN0
EDP_TXN1
EDP_TXP0
EDP_TXP1
EDP_RCOMP
EDP_DISP_UTIL
FDI_TXN0
FDI_TXP0
FDI_TXN1
FDI_TXP1
F15
EDP_AUXN
F14
EDP_AUXP
E14
EDP_HPD_Q#
C14
EDP_TXN0
A12
EDP_TXN1
D14
EDP_TXP0
B12
EDP_TXP1
AG6
EDP_RCOMP
E12
EDP_DISP_UTIL
C12
D12
A14
B14
EDP_AUXN [34]
EDP_AUXP [34]
EDP_TXN0 [34]
EDP_TXN1 [34]
EDP_TXP0 [34]
EDP_TXP1 [34]
R42 24.9/F_4
TP13
Layout note:
eDP_RCOMP
TL <= 100 mils
TW >= 20 mils
TS >= 25 mils
+1V_VCOMP_OUT
TP118
TP119
TP120
TP121
TP122
B3_A3
TP_A4
TP_A51
A52_B52
A53_B53
C3_B2
B3_A3
A52_B52
A53_B53
B54_C54
TP_BC1
TP_BC54
BE1_BD1
BE54_BD54
BE1_BD1
BE2_BF2
BE3_BF3
BE52_BF52
BE53_BF53
BE54_BD54
BE2_BF2
BE3_BF3
TP_BF4
U1L
A3
DAISY_CHAIN_NCTF_A3
A4
DAISY_CHAIN_NCTF_A4
A51
DAISY_CHAIN_NCTF_A51
A52
DAISY_CHAIN_NCTF_A52
A53
DAISY_CHAIN_NCTF_A53
B2
DAISY_CHAIN_NCTF_B2
B3
DAISY_CHAIN_NCTF_B3
B52
DAISY_CHAIN_NCTF_B52
B53
DAISY_CHAIN_NCTF_B53
B54
DAISY_CHAIN_NCTF_B54
BC1
DAISY_CHAIN_NCTF_BC1
BC54
DAISY_CHAIN_NCTF_BC54
BD1
DAISY_CHAIN_NCTF_BD1
BD54
DAISY_CHAIN_NCTF_BD54
BE1
DAISY_CHAIN_NCTF_BE1
BE2
DAISY_CHAIN_NCTF_BE2
BE3
DAISY_CHAIN_NCTF_BE3
BE52
DAISY_CHAIN_NCTF_BE52
BE53
DAISY_CHAIN_NCTF_BE53
BE54
DAISY_CHAIN_NCTF_BE54
BF2
DAISY_CHAIN_NCTF_BF2
BF3
DAISY_CHAIN_NCTF_BF3
BF4
DAISY_CHAIN_NCTF_BF4
HASWELL_BGA_E
12 OF 12
DAISY_CHAIN_NCTF_BF51
DAISY_CHAIN_NCTF_BF52
DAISY_CHAIN_NCTF_BF53
DAISY_CHAIN_NCTF_C1
DAISY_CHAIN_NCTF_C2
DAISY_CHAIN_NCTF_C3
DAISY_CHAIN_NCTF_C54
DAISY_CHAIN_NCTF_D1
DAISY_CHAIN_NCTF_D54
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
BF51
BF52
BF53
C1
C2
C3
C54
D1
D54
AN35
AN37
AF9
AE9
G14
G17
AD45
AG45
TP_BF51
BE52_BF52
BE53_BF53
C1_C2
C1_C2
C3_B2
B54_C54
TP_D1
TP_D54
TP123
TP124
TP125
Level Shift
B B
+1V_VCCIO_OUT
R43
10K_4
EDP_HPD_Q#
31
2
Q8
2N7002W
A A
5
R44
100K_4
EDP_HPD [34]
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Thursday, May 08, 2014
Date: Sheet of
Thursday, May 08, 2014
Date: Sheet of
4
3
2
Thursday, May 08, 2014
PROJECT :
Haswell 3/5 (DDI/eDP)
Haswell 3/5 (DDI/eDP)
Haswell 3/5 (DDI/eDP)
1
AM7
AM7
AM7
9 51
9 51
9 51
C0
C0
C0
5
HASWELL_BGA_E
U1F
AB45
VCC
AB46
10
D D
C C
B B
A A
AB8
AC46
AC47
AC8
AC9
AD46
AD8
AE46
AE47
AE8
AF8
AG46
AG8
AH46
AH47
AH8
AJ45
AJ46
AK46
AK47
AK8
AL45
AL46
AL8
AL9
AM46
AM47
AM8
AM9
AN10
AN12
AN13
AN14
AN15
AN16
AN17
AN19
AN20
AN21
AN23
AN24
AN25
AN26
AN27
AN29
AN30
AN32
AN34
AN36
AN38
AN39
AN40
AN41
AN42
AN43
AN44
AN45
AN46
AN8
AN9
AP10
AP12
AP13
AP14
AP15
AP16
AP17
AP18
AP19
AP20
AP21
AP22
AP23
AP24
AP25
AP26
AP27
AP29
AP30
AP31
AP32
AP33
AP34
AP35
AP36
AP37
AP38
AP39
AP40
AP41
AP42
AP43
AP44
AP46
AP47
AP8
AP9
AR35
AR37
AR39
AR41
AR43
AR45
AR46
H30
H31
H32
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
6 OF 12
5
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
H33
H34
H36
H37
H38
H39
H40
H42
H43
H45
H46
H48
H8
H9
J10
J14
J19
J24
J29
J33
J36
J37
J38
J39
J40
J42
J43
J45
J46
J48
J8
J9
K38
K40
K43
K44
K45
K46
K48
K8
K9
L37
L38
L39
L40
L42
L43
L44
L46
L47
L8
M37
M38
M39
M40
M42
M43
M44
M45
M46
M8
M9
N37
N38
N39
N40
N42
N43
N44
N46
N47
N8
N9
P45
P46
P8
R46
R47
R8
R9
T45
T46
U46
U47
U8
U9
V45
V46
V8
W46
W47
W8
Y45
Y46
Y8
A27
A28
A31
A32
A34
B27
B28
B31
B32
B34
B36
B38
B39
B42
+VCCIN+VCCIN
Haswell Processor (POWER)
Layout note:
DC,47W,85A
+CPU_FC_PWR
4
1 2
C622U/6.3V_8
1 2
C722U/6.3V_8
1 2
C822U/6.3V_8
1 2
C922U/6.3V_8
1 2
C1022U/6.3V_8
1 2
C1122U/6.3V_8
1 2
C1222U/6.3V_8
1 2
C1322U/6.3V_8
1 2
C1422U/6.3V_8
1 2
C1522U/6.3V_8
1 2
C1622U/6.3V_8
1 2
C1722U/6.3V_8
1 2
C1822U/6.3V_8
1 2
C1922U/6.3V_8
1 2
C2022U/6.3V_8
1 2
C2122U/6.3V_8
1 2
C2222U/6.3V_8
1 2
C2322U/6.3V_8
1 2
C2422U/6.3V_8
1 2
C2522U/6.3V_8
C70810U/6.3V/X6S_8
C72910U/6.3V/X6S_8
C73010U/6.3V/X6S_8
C73110U/6.3V/X6S_8
1 2
C7321U/6.3V_4
1 2
C7331U/6.3V_4
1 2
C7341U/6.3V_4
1 2
C7351U/6.3V_4
1 2
C7361U/6.3V_4
1 2
C7371U/6.3V_4
1 2
C7381U/6.3V_4
1 2
C7391U/6.3V_4
1 2
C7401U/6.3V_4
1 2
C7411U/6.3V_4
1 2
C7421U/6.3V_4
1 2
C7431U/6.3V_4
1 2
C7441U/6.3V_4
1 2
C7451U/6.3V_4
1 2
C7461U/6.3V_4
1 2
C7471U/6.3V_4
1 2
C7481U/6.3V_4
1 2
C7491U/6.3V_4
1 2
C7501U/6.3V_4
1 2
C7511U/6.3V_4
CPU_FC_PWROK
4
+VCCIN
B43
B45
B46
B48
C27
C28
C31
C32
C34
C36
C38
C39
C42
C43
C45
C46
C48
D27
D28
D31
D32
D34
D36
D38
D39
D42
D43
D45
D46
D48
E27
E28
E31
E32
E34
E36
E38
E39
E42
E43
E45
E46
E48
F27
F28
F31
F32
F34
F36
F38
F39
F42
F43
F45
F46
F48
G27
G29
G31
G32
G34
G36
G38
G39
G42
G43
G45
G46
G48
H11
H12
H13
H14
H16
H17
H18
H19
H20
H21
H23
H24
H25
H26
H27
H29
3
2
1
SVID
Layout note:
HASWELL_BGA_E
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
D5
FC_D5
D3
FC_D3
5 OF 12
U1E
RSVD
RSVD
RSVD
RSVD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
RSVD
VCC
VCC
RSVD
RSVD
VCC_SENSE
RSVD
VCCIO_OUT
FC_F17
VCOMP_OUT
RSVD
RSVD
RSVD
RSVD
VIDALERT
VIDSCLK
VIDSOUT
VSS
PWR_DEBUG
VSS
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
3
J17
J21
J26
J31
AR29
AR31
AR33
AT13
AT19
AT23
AT27
AT32
AT36
AV37
AW22
AW25
AW29
AW33
AY18
BB21
BB22
BB26
BB27
BB30
BB31
BB34
BB36
BD22
BD26
BD30
BD33
BE18
BE22
BE26
BE30
BE33
AN31
L6
M6
AN22
AN18
C50
AH9
D51
F17
AK6
AN33
W9
J12
AR49
J53
J52
J50
B51
F19
E52
V49
U49
AM49
W49
V50
AN49
AJ49
AG50
AK49
AJ50
AP49
AB50
AP50
AD50
AM50
A36
A38
A39
A42
A43
A45
A46
A48
AA46
AA47
AA8
AA9
TP14
TP15
TP16
TP17
TP18
TP19
TP20
+VCCIO_OUT_R
+VCCIO_PCH_R
+1V_VCOMP_OUT
TP21
TP22
TP23
TP24
H_CPU_SVIDALRT#
CPU_PW R_DEBUG
+VCCIN
DC,47W,2.1A
+V_VDDQ
C753 10U/6.3V/X6S_8
C754 10U/6.3V/X6S_8
C755 10U/6.3V/X6S_8
C756 *10U/6.3V_6_NC
C757 *10U/6.3V_6_NC
C758 1U/6.3V_4
C759 1U/6.3V_4
C760 1U/6.3V_4
C761 *1U/6.3V_4_NC
C762 *1U/6.3V_4_NC
C763 *1U/6.3V_4_NC
0.1U/16V/X7R_4
+VCCIN
Output capability:
300mA
VR_SVID_CLK
VR_SVID_DATA
TP26
TP27
TP28
TP29
12
12
12
12
12
12
+1V_VCCIO_OUT
C819
R46100/F_4
R470_6
R48*0_6_NC
+VCCIO_PCH
TP25
Layout note:
Place PU resistor close to CPU
H_CPU_SVIDALRT#
+VCCIN
VCCSENSE [49]
C68
0.1U/16V/X7R_4
+1.05V +CPU_FC_PWR
*2K/F_4_NC
CPU_FC_PWROK
*1K/F_4_NC
2
Layout note:
need routing
together and ALERT need
between CLK and DATA
VR_SVID_CLK
Layout note:
Place PU resistor close to CPU
VR_SVID_DATA
+1V_VCCIO_OUT
R45
130/F_4
+1V_VCCIO_OUT
SVID CLK
(50 ohm)
(50 ohm)
SVID DATA
SVID ALERT
R49
75/F_4
R50 43_4
(50 ohm)
Output capability:
300mA
+1V_VCCIO_OUT
R600*0_6_NC
CRB is 22uF & 1uF
DG is 4.7uF & 0.1uF
*4.7U/6.3V_6_NC
R601
C764
PCH_PW ROK
C765
*0.1U/16V/X7R_4_NC
PCH_PW ROK [12]
Reserve to Broadwell
R602
R601,R602 Stuff on the Broadwell platform
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Thursday, May 08, 2014
Date: Sheet of
Thursday, May 08, 2014
Date: Sheet of
Thursday, May 08, 2014
PROJECT :
Haswell 4/5 (POWER)
Haswell 4/5 (POWER)
Haswell 4/5 (POWER)
1
VR_SVID_CLK [49]
VR_SVID_DATA [49]
VR_SVID_ALERT# [49]
AM7
AM7
AM7
10 51
10 51
10 51
C0
C0
C0
5
HASWELL_BGA_E
U1I
BC10
11
D D
C C
B B
A A
BC12
BC15
BC18
BC22
BC26
BC30
BC33
BC36
BC38
BC41
BC43
BC46
BC48
BC50
BC52
BD10
BD15
BD18
BD36
BD41
BD46
BD51
BE10
BE15
BE36
BE41
BE46
BF10
BF12
BF15
BF18
BF22
BF26
BF30
BF33
BF36
BF38
BF41
BF43
BF46
BF48
BC3
BC5
BC7
BD5
BF7
C11
C15
C19
C22
C26
C30
C33
C37
C40
C44
C49
C52
D11
D15
D19
D22
D26
D30
D33
D37
D40
D44
D49
E11
E15
E16
E17
E19
E20
E21
E22
E24
E25
E26
E30
E33
E37
E40
E44
E49
E51
E53
F26
F30
F33
F37
F40
F44
F49
G11
G13
G16
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
C4
VSS
VSS
VSS
VSS
VSS
C8
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
D8
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
E8
VSS
F2
VSS
VSS
F3
VSS
VSS
VSS
VSS
F4
VSS
VSS
VSS
VSS
F5
VSS
VSS
VSS
VSS
5
VSS_SENSE
9 OF 12
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
G20
G23
G25
G26
G30
G33
G37
G40
G44
G49
G52
G54
G7
G8
G9
H44
H49
H7
J44
J49
J51
J54
J7
K1
K2
K3
K4
K5
K6
K7
L48
L7
L9
M48
M50
M52
M54
M7
N48
N7
P1
P2
P3
P4
P48
P5
P50
P52
P54
P6
P7
R48
R7
T48
U1
U2
U3
U4
U48
U5
U50
U52
U54
U6
U7
V48
V7
V9
W48
W50
W52
W54
W7
Y48
Y7
Y9
AR22
AB48
P9
G18
A49
A50
A8
B4
BA1
BA54
BB1
BB54
BD2
BD53
BF49
BF5
BF50
BF6
C53
D2
E54
F54
G1
D50
AA48
AB51
AB52
AB53
AB54
AC48
AC50
AD48
AD51
AD54
AE48
AE50
AG48
AG51
AG52
AG53
AG54
AH48
AH50
R62 100/F_4
A11
A15
A19
A22
A26
A30
A33
A37
A40
A44
AA1
AA2
AA3
AA4
AA5
AA7
AB5
AB7
AB9
AC5
AC7
AD7
AD9
AE1
AE2
AE3
AE4
AE5
AE7
AF5
AF6
AF7
AG5
AG7
AG9
AH1
AH2
AH3
AH4
AH5
AH7
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
U1G
4
HASWELL_BGA_E
VSSSENSE [49]
4
Haswell Processor (GND)
AJ48
VSS
AJ51
VSS
AJ54
VSS
AK48
VSS
AK5
VSS
AK50
VSS
AK7
VSS
AK9
VSS
AL1
VSS
AL4
VSS
AL48
VSS
AL5
VSS
AL7
VSS
AM5
VSS
AM51
VSS
AM52
VSS
AM53
VSS
AM54
VSS
AM7
VSS
AN1
VSS
AN2
VSS
AN3
VSS
AN4
VSS
AN48
VSS
AN5
VSS
AN50
VSS
AN7
VSS
AP51
VSS
AP54
VSS
AP7
VSS
AR12
VSS
AR14
VSS
AR16
VSS
AR18
VSS
AR20
VSS
AR24
VSS
AR26
VSS
AR48
VSS
AR5
VSS
AR50
VSS
AR7
VSS
AR8
VSS
AR9
VSS
AT1
VSS
AT10
VSS
AT12
VSS
AT15
VSS
AT16
VSS
AT18
VSS
AT20
VSS
AT22
VSS
AT25
VSS
AT26
VSS
AT29
VSS
AT33
VSS
AT35
VSS
AT37
VSS
AT39
VSS
AT4
7 OF 12
VSS
Configuration Signals:
CFG[2] PCI Express Static Lane Reversal
CFG[3] MSR Privacy Bit Feature
CFG[4]
CFG[6:5]
eDP enable
PCI Express Bifurcation
AT40
AT42
AT43
AT45
AT46
AT47
AT49
AT50
AT51
AT52
AT53
AT54
AU13
AU18
AU22
AU25
AU29
AU33
AU37
AU42
AU5
AU9
AV1
AV13
AV18
AV2
AV22
AV25
AV29
AV3
AV33
AV4
AV42
AV5
AV50
AV9
AW13
AW18
AW37
AW42
AW43
AW45
AW46
AW47
AW49
AW5
AW50
AW51
AW54
AW9
AY13
AY22
AY25
AY29
AY33
AY37
AY42
AT5
AT6
AT8
AT9
3
HASWELL_BGA_E
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
U1H
8 OF 12
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AY50
AY9
B11
B15
B19
B22
B26
B30
B33
B37
B40
B44
B49
B8
BA13
BA18
BA22
BA25
BA29
BA33
BA37
BA4
BA42
BA5
BA50
BA51
BA52
BA53
BA9
BB10
BB11
BB12
BB14
BB15
BB16
BB17
BB18
BB20
BB23
BB25
BB28
BB32
BB33
BB37
BB38
BB39
BB41
BB42
BB43
BB44
BB46
BB47
BB48
BB49
BB5
BB6
BB7
BB9
For CPU debug
R55
49.9/F_4
R54 49.9/F_4
TP30
TP31
TP32
TP33
TP34
TP35
TP36
TP37
TP38
TP39
TP126
TP127
TP128
TP129
TP130
TP131
TP132
TP133
The CFG signals have a default value of '1' if not terminated on the board.
x1 = Normal operation
x0 = Lane numbers reversed
x1 = Debug capability is determined by
IA32_Debug_Interface_MSR (0xC80)
bit[0] setting
x0 = IA32_Debug_Interface_MSR (0xC80)
bit[0]. Default setting overridden
x1 = Disabled
x0 = Enabled
x00 = 1 x8 & 2 x4 PCI Express
x01 = reserved
x10 = 2 x8 PCI Express
x11 = 1 x16 PCI Express
3
CFG2
CFG3
CFG4
CFG6
CFG5
2
+VCCIN
2
BE4
BD3
F6
G6
G21
G24
F21
RSVD30
G19
F51
F52
F22
L52
L53
L51
F24
RSVD38
F25
RSVD39
F20
TESTLO
AG49
CFG0
AD49
CFG1
AC49
CFG2
AE49
CFG3
Y50
CFG4
AB49
CFG5
V51
CFG6
W51
CFG7
Y49
CFG8
Y54
CFG9
Y53
CFG10
W53
CFG11
U53
CFG12
V54
CFG13
R53
CFG14
R52
CFG15
L50
L49
E5
R56 1K_4
R57 *1K_4_NC
R58 1K_4
R59 *1K_4_NC
R60 1K_4
1
Haswell Processor (CFG,RSVD)
HASWELL_BGA_E
U1K
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
TESTLO_F21
VSS
VSS
VSS
VCC
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
TESTLO_F20
CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
RSVD
RSVD
RSVD
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Thursday, May 08, 2014
Date: Sheet of
Thursday, May 08, 2014
Date: Sheet of
Thursday, May 08, 2014
CFG_RCOMP
11 OF 12
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
PROJECT :
Haswell 5/5 (CFG/GND)
Haswell 5/5 (CFG/GND)
Haswell 5/5 (CFG/GND)
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
CFG16
CFG18
CFG17
CFG19
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD_TP
RSVD_TP
VSS
VSS
VSS
VSS
RSVD
RSVD
RSVD
F1
E1
A5
A6
R54
Y52
V53
Y51
V52
B50
AH49
AM48
AU27
AU26
BD4
BC4
AL6
F8
F16
G12
G10
H54
H53
H51
H52
N51
G53
H50
1
CFG_RCOMP
CFG16
CFG18
CFG17
CFG19
AM7
AM7
AM7
11 51
11 51
11 51
R53
49.9/F_4
TP134
TP135
TP136
TP137
C0
C0
C0
5
4
3
2
1
Lynx Point (DMI,FDI,PM)
12
D D
CPU_DBR#[7]
EC_PWROK[29,38]
IMVP_PWRGD[29,49]
C C
B B
PCH_PWROK[10]
HWPG[29,38]
TP46
PM_DRAM_PWRGD[7]
TP49
RSMRST#[29]
SUS_PWR_ACK[29]
EC_PWRBTN#[29]
AC_PRESENT[29]
TP56
TP57
+1.5V_RUN
SUS_PWR_ACK
DMI_RXN0[7]
DMI_RXN1[7]
DMI_RXN2[7]
DMI_RXN3[7]
DMI_RXP0[7]
DMI_RXP1[7]
DMI_RXP2[7]
DMI_RXP3[7]
DMI_TXN0[7]
DMI_TXN1[7]
DMI_TXN2[7]
DMI_TXN3[7]
DMI_TXP0[7]
DMI_TXP1[7]
DMI_TXP2[7]
DMI_TXP3[7]
R73
*SJ0402_NC
112
R742
112
R84
112
R604
112
R77
R81
*SJ0402_NC
R74 *0_4_NC
R70 *SJ0402_NC
R72 7.5K/F_4
112
112
2
*SJ0402_NC
2
*SJ0402_NC
2
*SJ0402_NC
2
*SJ0402_NC
SUS_PWR_ACK
EC_PWRBTN#
112
TP21
PCH_SLP_WLAN#
DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3
DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3
DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3
DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3
2
DMI_IREF
DMI_RCOMP
2
SUSACK#_R
SYS_RESET#
SYS_PWROK
PCH_PWROK
APWROK
PM_DRAM_PWRGD
PCH_RSMRST#
2
PCH_ACPRESENT
PCH_BATLOW#
PM_RI#
U4B BOMCMB_LPT_PCH_M_EDS/BGA
AW22
DMI_RXN_0
AR20
DMI_RXN_1
AP17
DMI_RXN_2
AV20
DMI_RXN_3
AY22
DMI_RXP_0
AP20
DMI_RXP_1
AR17
DMI_RXP_2
AW20
DMI_RXP_3
BD21
DMI_TXN_0
BE20
DMI_TXN_1
BD17
DMI_TXN_2
BE18
DMI_TXN_3
BB21
DMI_TXP_0
BC20
DMI_TXP_1
BB17
DMI_TXP_2
BC18
DMI_TXP_3
BE16
DMI_IREF
AW17
TP12
AV17
TP7
AY17
DMI_RCOMP
R6
SUSACK#
AM1
SYS_RESET#
AD7
SYS_PWROK
F10
PWROK
AB7
APWROK
H3
DRAMPWROK
J2
RSMRST#
J4
SUSWARN#/SUSPW RNACK/GPIO30
K1
PWRBTN#
E6
ACPRESENT/GPIO31
K7
BATLOW#/GPIO72
N4
RI#
AB10
TP21
D2
SLP_WLAN#/GPIO29
PLTRST# Buffer
+3.3V_RUN
2
PCI_PLTRST#
A A
1
1 2
C72 *0.1U/16V/X7R_4_NC
5
VCC
I0
4
O
I1
GND
U6
3
*TC7SH08FU_NC
R103 0_4
PLTRST#
LPT_PCH_M_EDS
REV = 5
DMI
Layout note:
DMI_RCOMP/DMI_IREF
(DC resistance routing < 1R)
BO TL <= 100 mils
TL <= 500 mils
BO TW >= 3.5 mils
TW = 12-15 mils
TS >= 12 mils
System Power
Management
(SUS)
(DSW)
(SUS)
(DSW)
PLTRST# [20,29,41,42]
R100
100K_4
FDI
(SUS)
(SUS)
(SUS)
FDI_RXN_0
FDI_RXN_1
FDI_RXP_0
FDI_RXP_1
TP16
TP15
TP10
FDI_CSYNC
FDI_INT
FDI_IREF
TP17
TP13
FDI_RCOMP
DSWVRMEN
DPWROK
WAKE#
CLKRUN#
SUS_STAT#/GPIO61
SUSCLK/GPIO62
SLP_S5#/GPIO63
SLP_S4#
SLP_S3#
SLP_A#
SLP_SUS#
PMSYNCH
SLP_LAN#
4 OF 11
PCH PU/PD setting
PCH_GPIO52
SYS_RESET#
PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
HDMI_SCL
HDMI_SDA
CLKRUN#
SUS_PWR_ACK
PM_RI#
PCH_BATLOW#
PCH_WAKE#
PCH_ACPRESENT
SYS_PWROK
PCH_RSMRST#
R40
HDMI_SCL
R39
HDMI_SDA
R35
R36
N40
N38
H45
K43
J42
H43
K45
J44
K40
INT_HDMI_HPD
K38
H39
G17
PCH_GPIO2
F17
SATA_ODD_MD#
L15
KB_LED_DET
M15
EXTTS_SNI_DRV1_PCH
AD10
PCI_PME#
PME#
Y11
PCI_PLTRST#
+3.3V_RUN
RP4
10
1
2
3
56
10K_10P8R_6
1
3
5
7
4
2
R95 8.2K_4
1
3
HDMI_SCL [35]
HDMI_SDA [35]
INT_HDMI_HPD [35]
SATA_ODD_MD# [31]
KB_LED_DET [36]
TP47
SATA_ODD_MD#
PCH_GPIO2
EXTTS_SNI_DRV1_PCH
9
8
7 4
2
RP10 10KX4
4
6
8
3
RP11 2.2KX2
1
2
RP12 10KX2
4
R101 8.2K_4
R102 1K_4
R105 10K_4
R108 *100K_4_NC
R110 *10K_4_NC
R113 10K_4
+3.3V_RUN
+3.3V_SUS
WAKE# :
Check list : 10K PU
CRB : 1K PU
DISPLAY
PCI
(CORE)
(CORE)
(CORE)
(CORE)
+3.3V_RUN
DDPB_CTRLCLK
DDPB_CTRLDATA
DDPC_CTRLCLK
DDPC_CTRLDATA
DDPD_CTRLCLK
DDPD_CTRLDATA
DDPB_AUXN
DDPC_AUXN
DDPD_AUXN
DDPB_AUXP
DDPC_AUXP
DDPD_AUXP
DDPB_HPD
DDPC_HPD
DDPD_HPD
PIRQE#/GPIO2
PIRQF#/GPIO3
PIRQG#/GPIO4
PIRQH#/GPIO5
PLTRST#
5 OF 11
AJ35
AL35
AJ36
AL36
AV43
AY45
TP5
AV45
AW44
AL39
AL40
AT45
AU42
AU44
AR44
C8
L13
K3
AN7
U7
Y6
Y7
C6
H1
F3
F1
AY3
G5
FDI_IREF
FDI_RCOMP
DSWVRMEN
PCH_DPWROK
PCH_WAKE#
CLKRUN#
SUS_STAT#
PCH_SUSCLK
PCH_SLP_S5#
PCH_SLP_S4#
PCH_SLP_S3#
PCH_SLP_ME#
PCH_SLP_SUS#
PM_SYNC
PCH_SLP_LAN#
FDI_CSYNC [7]
FDI_INT [7]
R752 0_4
R753 7.5K/F_4
DSWVRMEN [13]
2
2
2
2
2
EDP_BKLTCTL[34]
EDP_BKLTEN[29,34]
EDP_VDDEN[34]
112
*SJ0402_NC
CLKRUN# [29]
TP44
112
112
112
112
TP53
TP54
TP55
R68 649/F_4
TP45
PCH_GPIO53[13]
STP_A16OVR[13]
RSMRST#
PM_SYNC [7]
R75
R76 *SJ0402_NC
R78 *SJ0402_NC
R79 *SJ0402_NC
R80 *SJ0402_NC
DGPU_HOLD_RST#[20]
DGPU_PWR_EN[50]
+1.5V_RUN
DAC_IREF
EDP_BKLTCTL
EDP_BKLTEN
EDP_VDDEN
PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
DGPU_HOLD_RST#
PCH_GPIO52
DGPU_PWR_EN
BBS_BIT1
PCH_GPIO53
STP_A16OVR
DGPU_HOLD_RST#
DGPU_PWR_EN
SUSCLK [13]
TP50
SIO_SLP_S5# [29,46]
TP51
SIO_SLP_S4# [29,46]
TP52
SIO_SLP_S3# [29,46]
Lynx Point (CRT,PCI,DDI CNTL)
U4E BOMCMB_LPT_PCH_M_EDS/BGA
T45
VGA_BLUE
U44
VGA_GREEN
V45
VGA_RED
M43
VGA_DDC_CLK
M45
VGA_DDC_DATA
N42
VGA_HSYNC
N44
VGA_VSYNC
U40
DAC_IREF
U39
VGA_IRTN
N36
EDP_BKLTCTL
K36
EDP_BKLTEN
G36
EDP_VDDEN
H20
PIRQA#
L20
PIRQB#
K17
PIRQC#
M20
PIRQD#
A12
(CORE)
GPIO50
B13
(CORE)
GPIO52
C12
(CORE)
GPIO54
C10
(CORE)
GPIO51
A10
(CORE)
GPIO53
AL6
(CORE)
GPIO55
R763 *10K_4_NC
R762 10K_4
R761 10K_4
R764 *10K_4_NC
LPT_PCH_M_EV
REV = 5
CRT
EDP
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Thursday, May 08, 2014
Date: Sheet of
Thursday, May 08, 2014
Date: Sheet of
5
4
3
2
Thursday, May 08, 2014
PROJECT :
LPT 1/6 (DMI/FDI/VGA)
LPT 1/6 (DMI/FDI/VGA)
LPT 1/6 (DMI/FDI/VGA)
AM7
AM7
AM7
C0
C0
12 51
12 51
1
12 51
C0
5
4
3
2
1
Lynx Point (RTC,IHDA,SATA,JTAG) Lynx Point (LPC,SPI,SMBUS,C-LINK,THERMAL)
13
+3V_RTC
RTC_X1
RTC_X2
SRTC_RST#
R124
1M_4
SM_INTRUDER#
D D
TP64
C C
TP67
TP68
TP69
TP70
TP71
TP138
TP72
PCH_INVRMEN
RTC_RST#
HDA_BCLK_R
ACZ_SYNC_R
ACZ_SPKR
HDA_RST#_R
HDA_SDIN0[32]
HDA_SDO_R
PCH_GPIO33
PCH_GPIO13
PCH_JTAG_TCK_R
PCH_JTAG_TMS_R
PCH_JTAG_TDI_R
PCH_JTAG_TDO_R
TP25
TP22
TP20
U4A BOMCMB_LPT_PCH_M_EDS/BGA
B5
RTCX1
B4
RTCX2
B9
SRTCRST#
A8
INTRUDER#
G10
INTVRMEN
D9
RTCRST#
B25
HDA_BCLK
A22
HDA_SYNC
AL10
SPKR
C24
HDA_RST#
L22
HDA_SDI0
K22
HDA_SDI1
G22
HDA_SDI2
F22
HDA_SDI3
A24
HDA_SDO
B17
DOCKEN#/GPIO33
C22
HDA_DOCK_RST#/GPIO13
AB3
JTAG_TCK
AD1
JTAG_TMS
AE2
JTAG_TDI
AD3
JTAG_TDO
F8
TP25
C26
TP22
AB6
TP20
HDA EMI
HDA_BITCLK[32]
HDA_RST#[32]
HDA_SDOUT[32]
HDA_SYNC[32]
ACZ_SPKR[32]
B B
R578 33_4
R150 33_4
R151 33_4
R145 33_4
PCH STRAPING
Pin Name
SPKR
GPIO62 / SUSCLK
GPIO55
INTVRMEN
GPIO51
SATA1GP/GPIO19
HDA_SDO
A A
DSWVREN
GPIO53
HDA_DOCK_EN# /
GPIO33
Usage
No Reboot
PLL On-Die Voltage
Regulator Enable
Top-Block Swap Override
Integrated VRM Enable
Boot BIOS Strap bit 1
Boot BIOS Strap bit 0
Flash Descriptor Security
Override / Intel ME Debug Mode
On Die DSW VR Enable
DMI AC / DC-Coupling Mode PWROK 0 = DMI is in AC-coupling mode
DMI TX Termination PWROK 0 = DMI TX is terminated to VSS (int PD)
5
LPT_PCH_M_EDS
(CORE)
JTAGRTC AZALIA
HDA_BCLK_R
HDA_RST#_R
HDA_SDO_R
ACZ_SYNC_R
ACZ_SPKR
Sampled
(SUS)
PWROK
RSMRST#
PWROK
Always
PWROK
PWROK
PWROK
Always
REV = 5
SATA
(CORE)
(CORE)
1 OF 11
SATA_RXN_0
SATA_RXP_0
SATA_TXN_0
SATA_TXP_0
SATA_RXN_1
SATA_RXP_1
SATA_TXN_1
SATA_TXP_1
SATA_RXN_2
SATA_RXP_2
SATA_TXN_2
SATA_TXP_2
SATA_RXN_3
SATA_RXP_3
SATA_TXN_3
SATA_TXP_3
SATA_RXN4/PERN1
SATA_RXP4/PERP1
SATA_TXN4/PETN1
SATA_TXP4/PETP1
SATA_RXN5/PERN2
SATA_RXP5/PERP2
SATA_TXN5/PETN2
SATA_TXP5/PETP2
SATA_RCOMP
SATALED#
SATA0GP/GPIO21
SATA1GP/GPIO19
SATA_IREF
HDA_BITCLK
HDA_SDOUT
Configuration
0 = Disable (Int PD)
1 = Enable
0 = Disable
1 = Enable (Int PU)
0 = Top-Block Swap mode
1 = Default (Int PU)
0 = Disable
1 = Enable
Bit1 Bit0
1 0 Resvered
1 1 SPI
0 0 LPC
0 = Security Effect (Int PD)
1 = Can be Override
0 = Disable
1 = Enable
Must be PU to VCCRTC
1 = DMI is in DC-coupling mode (int PU)
1 = DMI TX is terminated to VCC/2.
BC8
BE8
AW8
AY8
BC10
BE10
AV10
AW10
BB9
BD9
AY13
AW13
BC12
BE12
AR13
AT13
BD13
SATA_RXN4
BB13
SATA_RXP4
AV15
SATA_TXN4
AW15
SATA_TXP4
BC14
SATA_RXN5
BE14
SATA_RXP5
AP15
SATA_TXN5
AR15
SATA_TXP5
AY5
SATA_RCOMP
AP3
AT1
SATA0GP
AU2
BBS_BIT0
BD4
SATA_IREF
BA2
Layout note:
TP9
SATA_RCOMP/SATA_IREF
BB2
TP8
(DC resistance routing < 0.2R)
BO TL <= 100 mils
TL <= 500 mils
BO TW >= 4 mils
TW = 12-15 mils
TS >= 15 mils
EC42 *10P/50V_4_NC
EC43 *10P/50V_4_NC
4
SATA_RXN4 [31]
SATA_RXP4 [31]
SATA_TXN4 [31]
SATA_TXP4 [31]
SATA_RXN5 [31]
SATA_RXP5 [31]
SATA_TXN5 [31]
SATA_TXP5 [31]
R127 7.5K/F_4
R128 0_6
DSWVRMEN[12]
+1.5V_RUN
+1.5V_RUN
Circuitry
ACZ_SPKR
SUSCLK[12]
STP_A16OVR[12]
PCH_INVRMEN
BBS_BIT0
PCH_MELOCK[29]
PCH_GPIO53[12]
PCH_GPIO33
LPC_LAD0[29,41]
LPC_LAD1[29,41]
LPC_LAD2[29,41]
LPC_LAD3[29,41]
LPC_LFRAME#[29,41]
SATA HDD
SATA ODD
R155 *1K_4_NC
R156 *1K_4_NC
R159 *1K_4_NC
R160 330K_4
R714 *330K_4_NC
R161 10K_4
R164 330K_4
R165 *330K_4_NC
R628 *1K_4_NC
R629 *1K_4_NC
R123 22_4
R121 22_4
R122 22_4
R125 22_4
R754 22_4
TP58
TP59
TP60
IRQ_SERIRQ[29]
PCH_SPI_CLK[30]
PCH_SPI_CS0#[30]
PCH_SPI_SI[30]
PCH_SPI_SO[30]
PCH_SPI_IO2[30]
PCH_SPI_IO3[30]
PCH PU/PD setting
Follow SCH CHKRST v2.0
Follow DG v2.2
Follow SCH CHKRST
v2.0 pg27
+3.3V_RUN
+3V_RTC
+3.3V_RUN
HDA_SDO_R
R1621K_4
CRB : 330 K PU
+3V_RTC
DG : 390 K PU
+3.3V_RUN
3
PCH_LAD0
PCH_LAD1
PCH_LAD2
PCH_LAD3
PCH_LFRAME#
PCH_DRQ#0
PCH_DRQ#1
IRQ_SERIRQ
PCH_SPI_CLK
PCH_SPI_CS0#
PCH_SPI_SI
PCH_SPI_SO
PCH_SPI_IO2
PCH_SPI_IO3
PCH_GPIO13
PCH_SPI_CS0#
PCH_JTAG_TMS_R
PCH_JTAG_TDI_R
PCH_JTAG_TDO_R
PCH_JTAG_TCK_R
U4D BOMCMB_LPT_PCH_M_EDS/BGA
A20
LAD_0
C20
LAD_1
A18
LAD_2
C18
LAD_3
B21
LFRAME#
D21
LDRQ0#
G20
LDRQ1#/GPIO23
AL11
SERIRQ
AJ11
SPI_CLK
AJ7
SPI_CS0#
AL7
SPI_CS1#
AJ10
SPI_CS2#
AH1
SPI_MOSI
AH3
SPI_MISO
AJ4
SPI_IO2
AJ2
SPI_IO3
IRQ_SERIRQ
SATA0GP
R130 10K_4
R131 10K_4
R134 10K_4
R141 *10K_4_NC
R137 *210/F_4_NC
R138 *210/F_4_NC
R139 *210/F_4_NC
R144 *51_4_NC
RTC Circuitry
C79
1U/10V/X5R_4
Layout note:
30mils
+3V_RTC
R153 20K_4
R154 20K_4
RTC Clock 32.768KHz
C84
15P/50V_4
C85 15P/50V_4
(CORE)
SPILPC
+3.3V_RUN
+3.3V_SUS
RTC_RST#
SRTC_RST#
C83
1U/10V/X5R_4
LPT_PCH_M_EDS
SMBus
C-Link
Thermal
DVT2
Y1
32.768KHZ
1 2
2
REV = 5
(SUS)
(SUS)
(SUS)
SML1ALERT#/PCHHOT#/GPIO74
(SUS)
(SUS)
3 OF 11
Leakage Isolation
For DIMMs
+3.3V_SUS
SMB_PCH_CLK
SMB_PCH_DAT
Q60
31
*2N7002W_NC
2
RTC_X1
R163
10M_4
RTC_X2
N7
SMBALERT#/GPIO11
SMBCLK
SMBDATA
SML0ALERT#/GPIO60
SML0CLK
SML0DATA
SML1CLK/GPIO58
SML1DATA/GPIO75
CL_CLK
CL_DATA
CL_RST#
TD_IREF
+3.3V_RUN
2
4
RP13
2.2KX2
1
3
EC_RTC_RST [29]
+3.3V_SUS
SMB_ME1_DAT SMBDAT1
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
R10
U11
N8
U8
R7
H6
K6
N11
AF11
AF10
AF7
BA45
TP1
BC45
TP2
BE43
TP4
BE44
TP3
AY43
Q13
2N7002KDW
5
2
6
2
4
RP14
2.2KX2
1
3
Thursday, May 08, 2014
Thursday, May 08, 2014
Thursday, May 08, 2014
SMBALERT#
SMB_PCH_CLK
SMB_PCH_DAT
DRAMRST_CNTRL_PCH
SMB_ME0_CLK
SMB_ME0_DAT
PCH_TEMP_ALERT#
SMB_ME1_CLK
SMB_ME1_DAT
CL_CLK
CL_DAT
CL_RST#
TD_IREF
R126 8.2K_4
DRAMRST_CNTRL_PCH
SMBALERT#
PCH_TEMP_ALERT#
SMB_ME0_CLK
SMB_ME0_DAT
Fast Mode -> 499R (Default)
Normal Mode -> 2.2KR
+3.3V_RUN
2
4
RP16
2.2KX2
1
3
43
1
SMB_RUN_CLK [18,19,36]
SMB_RUN_DAT [18,19,36]
For EC
Q14
2N7002KDW
5
4 3
1
LPT 2/6 (SATA/HDA/SPI)
LPT 2/6 (SATA/HDA/SPI)
LPT 2/6 (SATA/HDA/SPI)
+3.3V_SUS
SMBCLK1SMB_ME1_CLK
2
+3.3V_SUS
6
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
PROJECT :
1
TP61
TP62
TP63
AM7
AM7
AM7
1
3
SMBCLK1 [29]
SMBDAT1 [29]
13 51
13 51
13 51
+3.3V_SUS
R1291K_4
R13210K_4
R13310K_4
2
RP152.2KX2
4
C0
C0
C0
5
4
3
2
1
14
D D
PCIE_RXN3[42]
PCIE_RXP3[42]
LAN
PCIE_TXN3[42]
PCIE_TXP3[42]
PCIE_RXN4[41]
PCIE_RXP4[41]
WLAN
PCIE_TXN4[41]
PCIE_TXP4[41]
C C
+1.5V_RUN
B B
CLK_33M_EC
CLK_33M_DEBUG
CLK_33M_FB
A A
C655 0.1U/16V/X7R_4
C654 0.1U/16V/X7R_4
C656 0.1U/16V/X7R_4
C657 0.1U/16V/X7R_4
112
R174 *SJ0603_NC
R179 7.5K/F_4
Layout note:
PCIE_RCOMP/PCIE_IREF
(DC resistance routing < 0.2R)
BO TL <= 100 mils
TL <= 500 mils
BO TW >= 4 mils
TW = 12-15 mils
TS >= 12 mils
EMI
EC36 *10P/50V_4_NC
EC37 *10P/50V_4_NC
EC38 *10P/50V_4_NC
2
Lynx Point (PCIE,USB3.0,USB2.0)
LPT_PCH_M_EDS
XTAL25_IN
XTAL25_OUT
PCIe
USB
9 OF 11
USB_OC0#
USB_OC1#
USB_OC2#
USB_OC3#
(SUS)
(SUS)
(SUS)
(SUS)
(SUS)
(SUS)
(SUS)
(SUS)
+3.3V_SUS
USB2N10
USB2P10
USB2N11
USB2P11
USB2N12
USB2P12
USB2N13
USB2P13
USB3RN1
USB3RP1
USB3TN1
USB3TP1
USB3RN2
USB3RP2
USB3TN2
USB3TP2
USB3RN5
USB3RP5
USB3TN5
USB3TP5
USB3RN6
USB3RP6
USB3TN6
USB3TP6
USBRBIAS#
USBRBIAS
OC0#/GPIO59
OC1#/GPIO40
OC2#/GPIO41
OC3#/GPIO42
OC4#/GPIO43
OC5#/GPIO9
OC6#/GPIO10
OC7#/GPIO14
RP3
10
9
8
7 4
10K_10P8R_6
3
R190
1M_4
1
PCIE_IREF
PCIE_RCOMP
PETN_3
PETP_3
PETN_4
PETP_4
U4I BOMCMB_LPT_PCH_M_EDS/BGA
AW31
PERN1/USB3RN3
AY31
PERP1/USB3RP3
BE32
PETN1/USB3TN3
BC32
PETP1/USB3TP3
AT31
PERN2/USB3RN4
AR31
PERP2/USB3RP4
BD33
PETN2/USB3TN4
BB33
PETP2/USB3TP4
AW33
PERN_3
AY33
PERP_3
BE34
PETN_3
BC34
PETP_3
AT33
PERN_4
AR33
PERP_4
BE36
PETN_4
BC36
PETP_4
AW36
PERN_5
AV36
PERP_5
BD37
PETN_5
BB37
PETP_5
AY38
PERN_6
AW38
PERP_6
BC38
PETN_6
BE38
PETP_6
AT40
PERN_7
AT39
PERP_7
BE40
PETN_7
BC40
PETP_7
AN38
PERN_8
AN39
PERP_8
BD42
PETN_8
BD41
PETP_8
BE30
PCIE_IREF
BC30
TP11
BB29
TP6
BD29
PCIE_RCOMP
B37
USB2N0
D37
USB2P0
A38
USB2N1
C38
USB2P1
A36
USB2N2
C36
USB2P2
A34
USB2N3
C34
USB2P3
B33
USB2N4
D33
USB2P4
F31
USB2N5
G31
USB2P5
K31
USB2N6
L31
USB2P6
G29
USB2N7
H29
USB2P7
A32
USB2N8
C32
USB2P8
A30
USB2N9
C30
USB2P9
B29
D29
A28
C28
G26
F26
F24
G24
AR26
AP26
BE24
BD23
AW26
AV26
BD25
BC24
AW29
AV29
BE26
BC26
AR29
AP29
BD27
BE28
K24
K26
M33
TP24
L33
TP23
P3
V1
U2
P1
M3
T1
N2
M1
1
USB_OC4#
2
USB_OC5#
3
USB_OC6#
56
C86 12P/50V/_4
4
25MHz
2
C87 15P/50V_4
USB2_N0 [39]
USB2_P0 [39]
USB2_N1 [42]
USB2_P1 [42]
USB2_N5 [39]
USB2_P5 [39]
USB2_N8 [34]
USB2_P8 [34]
USB2_N9 [41]
USB2_P9 [41]
USB2_N11 [40]
USB2_P11 [40]
USB3_RXN1 [39]
USB3_RXP1 [39]
USB3_TXN1 [39]
USB3_TXP1 [39]
USB3_RXN2 [39]
USB3_RXP2 [39]
USB3_TXN2 [39]
USB3_TXP2 [39]
USBCOMP
R170 22.6/F_4
USBCOMP
Impedance = 50 Ohm
Trace length <= 500 mils
Trace spacing >= 15 mils
USB_OC0#
USB_OC1#
USB_OC2#
USB_OC3#
USB_OC4#
USB_OC5#
USB_OC6#
USB_OC7#
USB_OC7#
USB3.0 Conn
USB2.0 CONN / DB
USB3.0 Conn / PS
Camera
BT
Card reader
ext. USB Left
ext. USB Left
USB_OC0# [39]
USB_OC1# [42]
USB_OC2# [39]
USB2.0 Port 1 & port 9
is debug port.
CLK_PCIE_REQ3#
CLK_PEGB_REQ#
CLK_PCIE_REQ4#
CLK_PCIE_REQ7#
CLK_PCIE_REQ6#
CLK_PEGA_REQ#
CLK_PCIE_REQ0#
CLK_PCIE_REQ5#
RP22 10KX4
RP23 10KX4
Lynx Point (CLOCK)
U4C BOMCMB_LPT_PCH_M_EDS/BGA
Y43
CLKOUT_PCIE_N_0
Y45
CLKOUT_PCIE_P_0
CLK_PCIE_REQ0#
CLK_PCIE_REQ1#
CLK_PCIE_LANN[42]
CLK_PCIE_LANP[42]
PCIE_CLKREQ_LAN#[42]
CLK_PCIE_WLANN[41]
CLK_PCIE_WLANP[41]
PCIE_CLKREQ_WLAN#[41]
CLK_33M_DEBUG[41]
CLK_33M_EC[29]
2
CLK_PCIE_REQ2#
112
R167 *SJ0402_NC
2
CLK_PCIE_REQ3#
112
R166 *SJ0402_NC
CLK_PCIE_REQ4#
CLK_PCIE_REQ5#
CLK_PCIE_REQ6#
CLK_PCIE_REQ7#
R172 22_4
R175 22_4
R176 22_4
CLK_33M_PCI2CLK_33M_FB
CLK_33M_PCI3
CLK_33M_PCI4
R175 For Debug Only, Remove at QT
AB1
PCIECLKRQ0#/GPIO73
AA44
CLKOUT_PCIE_N_1
AA42
CLKOUT_PCIE_P_1
AF1
PCIECLKRQ1#/GPIO18
AB43
CLKOUT_PCIE_N_2
AB45
CLKOUT_PCIE_P_2
AF3
PCIECLKRQ2#/GPIO20/SMI#
AD43
CLKOUT_PCIE_N_3
AD45
CLKOUT_PCIE_P_3
T3
PCIECLKRQ3#/GPIO25
AF43
CLKOUT_PCIE_N_4
AF45
CLKOUT_PCIE_P_4
V3
PCIECLKRQ4#/GPIO26
AE44
CLKOUT_PCIE_N5
AE42
CLKOUT_PCIE_P_5
AA2
PCIECLKRQ5#/GPIO44
AB40
CLKOUT_PCIE_N_6
AB39
CLKOUT_PCIE_P_6
AE4
PCIECLKRQ6#/GPIO45
AJ44
CLKOUT_PCIE_N_7
AJ42
CLKOUT_PCIE_P_7
Y3
PCIECLKRQ7#/GPIO46
AH43
CLKOUT_ITPXDP
AH45
CLKOUT_ITPXDP_P
D44
CLKOUT_33MHZ0
E44
CLKOUT_33MHZ1
B42
CLKOUT_33MHZ2
F41
CLKOUT_33MHZ3
A40
CLKOUT_33MHZ4
CLOCK SIGNAL
PCH PU/PD setting
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
LPT_PCH_M_EDS
(SUS)
(SUS)
(CORE)
(SUS)
(CORE)
(SUS)
(SUS)
(SUS)
(SUS)
(SUS)
(CORE)
(CORE)
(CORE)
(CORE)
+3.3V_SUS
CLKOUT_PEG_A
CLKOUT_PEG_A_P
PEGA_CLKRQ#/GPIO47
CLKOUT_PEG_B
CLKOUT_PEG_B_P
PEGB_CLKRQ#/GPIO56
CLKOUT_DMI
CLKOUT_DMI_P
CLKOUT_DP
CLKOUT_DP_P
CLKOUT_DPNS
CLKOUT_DPNS_P
CLKIN_DMI_P
CLKIN_GND
CLKIN_GND_P
CLKIN_DOT96N
CLKIN_DOT96P
CLKIN_SATA
CLKIN_SATA_P
REFCLK14IN
CLKIN_33MHZLOOPBACK
XTAL25_OUT
CLKOUTFLEX0/GPIO64
CLKOUTFLEX1/GPIO65
CLKOUTFLEX2/GPIO66
CLKOUTFLEX3/GPIO67
DIFFCLK_BIASREF
2 OF 11
CLK_PCIE_REQ1#
CLK_PCIE_REQ2#
CLK_BUF_EXPN
CLK_BUF_EXPP
CLK_BUF_CPYCKN
CLK_BUF_CPYCKP
CLK_BUF_DOT96N
CLK_BUF_DOT96P
CLK_BUF_CKSSCDN
CLK_BUF_CKSSCDP
CLK_BUF_REF14
AB35
AB36
AF6
CLK_PEGA_REQ#
Y39
Y38
U4
CLK_PEGB_REQ#
AF39
AF40
AJ40
AJ39
AF35
AF36
AY24
CLKIN_DMI
XTAL25_IN
ICLK_IREF
CLK_BUF_EXPN
AW24
CLK_BUF_EXPP
AR24
CLK_BUF_CPYCKN
AT24
CLK_BUF_CPYCKP
H33
CLK_BUF_DOT96N
G33
CLK_BUF_DOT96P
BE6
CLK_BUF_CKSSCDN
BC6
CLK_BUF_CKSSCDP
F45
CLK_BUF_REF14
D17
CLK_33M_FB
AM43
XTAL25_IN
AL44
XTAL25_OUT
C40
CLK_FLEX0
F38
CLK_FLEX1
F36
CLK_FLEX2
F39
CLK_FLEX3
AM45
ICLK_IREF
*SJ0402_NC
AD39
TP19
AD38
TP18
AN44
ICLK_BIAS
CLKOUT_FLEX[2:3] if enabled, must be
programmed to the same clock frequency
due to sharing the same internal power rail.
2
RP21 10KX2
RP17 10KX2
RP18 10KX2
RP19 10KX2
RP20 10KX2
CLK_PCIE_VGAN [20]
CLK_PCIE_VGAP [20]
CLK_CPU_BCLKN [7]
CLK_CPU_BCLKP [7]
CLK_DPLL_SSCLKN [7]
CLK_DPLL_SSCLKP [7]
CLK_DPLL_NSCLKN [7]
CLK_DPLL_NSCLKP [7]
112
R178 7.5K/F_4Y2
1
4
3
2
1
4
3
2
1
4
3
4
3
2
1
2
1
4
3
R194 10K_4
CLK_PEGA_REQ# [20]
TP73
TP74
TP75
TP117
2
R173
+3.3V_RUN
+1.5V_RUN
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Thursday, May 08, 2014
Date: Sheet of
Thursday, May 08, 2014
Date: Sheet of
5
4
3
2
Thursday, May 08, 2014
PROJECT :
LPT 3/6 (PCIE/USB/CLK)
LPT 3/6 (PCIE/USB/CLK)
LPT 3/6 (PCIE/USB/CLK)
AM7
AM7
AM7
C0
C0
14 51
14 51
1
14 51
C0
5
4
3
2
1
15
BMBUSY#
2
2 1
112
SMC_EXTSMI#
PCIE_MCARD1_DET#
SIO_EXT_SCI#
LAN_PHY_PWR_CTRL
SATA_MCARD3_DET#
DGPU_PW ROK_R
BIOS_REC
LAN_WAKE#
PCH_GPIO28
USB_MCARD1_DET#
STR_DMIRX_TERMI
STR_TLS_CONF
2
PCH_GPIO38
PCH_GPIO39
BIOS_RESP
MODC_EN
SV_DET
PCH_GPIO68
PCH_GPIO69
PCH_GPIO70
PCH_GPIO71
SMC_EXTSMI#[29]
D D
DGPU_PW ROK[20,24]
SIO_EXT_SCI#[29]
R703
*SJ0402_NC
112
DVT2
GPU_EVENT#[23]
C C
GC6_FB_EN[23]
GPU_EVENT# PCH_EVENT#
D25
SDM10K45-7-F
R706
*SJ0402_NC
TP79
DVT2
MODC_EN[31]
Lynx Point (GPIO,CPU/MISC,NCTF)
U4F BOMCMB_LPT_PCH_M_EDS/BGA
AT8
BMBUSY#/GPIO0
F13
TACH1/GPIO1
A14
TACH2/GPIO6
G15
TACH3/GPIO7
Y1
GPIO8
K13
LAN_PHY_PWR_CTRL/GPIO12
AB11
GPIO15
AN2
SATA4GP/GPIO16
C14
TACH0/GPIO17
BB4
SCLOCK/GPIO22
Y10
GPIO24
R11
GPIO27
AD11
GPIO28
AN6
GPIO34
AP1
GPIO35/NMI#
AT3
SATA2GP/GPIO36
AK1
SATA3GP/GPIO37
AT7
SLOAD/GPIO38
AM3
SDATAOUT0/GPIO39
AN4
SDATAOUT1/GPIO48
AK3
SATA5GP/GPIO49
U12
GPIO57
C16
TACH4/GPIO68
D13
TACH5/GPIO69
G13
TACH6/GPIO70
H15
TACH7/GPIO71
BE41
VSS
BE5
VSS
C45
VSS
A5
VSS
(CORE)
(CORE)
(CORE)
(SUS)
(SUS)
(SUS)
(DSW)
(SUS)
(CORE)
(CORE)
(SUS)
LPT_PCH_M_EDS
(CORE)
(CORE)
(CORE)
(CORE)
(CORE)
(CORE)
(CORE)
(CORE)
(CORE)
(CORE)
(CORE)
(CORE)
(CORE)
(CORE)
(SUS)
GPIO
NCTF
CPU/Misc
RCIN#
PROCPWRGD
THRMTRIP#
PLTRST_PROC#
6 OF 11
TP14
PECI
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AN10
AY1
AT6
AV3
AV1
AU4
N10
A2
A41
A43
A44
B1
B2
B44
B45
BA1
BC1
BD1
BD2
BD44
BD45
BE2
BE3
D1
E1
E45
A4
EC_A20GATE
PCH_PECI
EC_RCIN#
TP77
PCH_THRMTRIP#
TP78
R207 390_4
PCH_PECI [29]
EC_RCIN# [29]
H_PWRGOOD [7]
PM_THRMTRIP# [7]
CPU_PLTRST# [7]
PCH PU/PD setting
LAN_WAKE#
LAN_PHY_PWR_CTRL
SMC_EXTSMI#
SIO_EXT_SCI#
EC_A20GATE
PCH_GPIO39
BMBUSY#
EC_RCIN#
USB_MCARD1_DET#
SATA_MCARD3_DET#
PCH_GPIO69
PCH_GPIO70
PCH_GPIO71
PCH_GPIO68
PCH_GPIO38
DGPU_PW ROK_R
PCH_EVENT#
PCIE_MCARD1_DET#
SV_DET
RP25 10KX2
RP24 10KX2
RP27 10KX2
RP26 10KX4
2
1
4
3
2
1
4
3
2
1
4
3
1
2
3
4
5
6
7
8
RP5 10KX4
1
2
3
4
5
6
7
8
R212 *10K_4_NC
R615 10K_4
R616 10K_4
R206 10K_4
R223 100K_4
+3.3V_SUS
+3.3V_RUN
B B
PCH Strap
Sampled ConfigurationPin Name Usage Circuitry
SATA2GP /
GPIO36
SATA3GP /
GPIO37
A A
BIOS RECOVERY
BIOS_REC BIOS_RESP
DMI RX Termination Rising edge
TLS Confidentiality Rising edge
0 = Enable
1 = Disable
R222 *0_4_NC
5
of PWROK
of PWROK
0 = DMI RX is terminated to VSS.
1 = DMI RX is terminated to VCC/2.
0 = Disable Intel ME Crypto Transport
Layer Security
(TLS) cipher suite (no confidentiality).
1 = Enable Intel ME Crypto Transport
Layer Security
(TLS) cipher suite (with confidentiality).
BIOS_RESP
0 = BIOS RESP
1 = Default
R220 10K_4R218 10K_4
R224 *0_4_NC
4
+3.3V_RUN+3.3V_RUN
Ref. Doc.
PCH EDS v2.3
SCH CHKLST v2.0
PCH EDS v2.3
SCH CHKLST v2.0
STR_DMIRX_TERMI
STR_TLS_CONF
R214 10K_4
R215 *200K/F_4_NC
R216 10K_4
R217 *200K/F_4_NC
3
+3.3V_RUN
+3.3V_RUN
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Thursday, May 08, 2014
Date: Sheet of
Thursday, May 08, 2014
Date: Sheet of
2
Thursday, May 08, 2014
PROJECT :
LPT 4/6 (GPIO/MISC)
LPT 4/6 (GPIO/MISC)
LPT 4/6 (GPIO/MISC)
1
AM7
AM7
AM7
15 51
15 51
15 51
C0
C0
C0
5
4
3
2
1
Layout note:
70mA
L1
*PBY160808T-181Y-N_6_NC
C88 *10U/6.3V_6_NC
C89 *0.1U/16V/X7R_4_NC
C90 *0.01U/25V_4_NC
R618 0_4
+V3.3S_ADACBG
C100 *10U/6.3V_6_NC
+V1.05S_VCC_EXP
C102 0.1U/16V/X7R_4
98mA (15mils)
+1V05_DCPSUS1
+3V3S5_PCH
0.476A (30mils)
+1V05_DCPSUS3
C104 *10U/6.3V_6_NC
C105 *10U/6.3V_6_NC
C106 *10U/6.3V_6_NC
+V1.05S_VCC_EXP
+3V3S5_PCH
R20
C113 0.1U/16V/X7R_4
R22
C111 0.1U/16V/X7R_4
A16
AA14
+VCCSST
AE14
AF12
C116 0.01U/25V_4
AG14
+V1.05S_VCC_EXP
U36
C118 0.1U/16V/X7R_4
C119 1U/10V/X5R_4
A26
K8
C121 1U/10V/X5R_4
C123 0.1U/16V/X7R_4
A6
C125 0.1U/16V/X7R_4
P14
+VCCRTCEXT
P16
C129 1U/10V/X5R_4
AJ12
C130 0.1U/16V/X7R_4
AJ14
C132 0.1U/16V/X7R_4
AD12
+VCCSPI
P18
VCC
P20
L17
R18
AW40
AK30
AK32
C135 1U/10V/X5R_4
+V1.05M_VCCASW
+1V5RUN_VCCVRM
C140 0.1U/16V/X7R_4
VCC
R619 0_4
R228 *0_4_NC
13mA (10mils)
C133 1U/10V/X5R_4
VSS
VCCVRM
VCCIO
VCCIO
DCPSUS1
DCPSUS3
DCPSUS3
VCCIO
VCCVRM
VCCVRM
VCCVRM
VCCIO
VCCVRM
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
+VCCA_DAC_1_2
P45
P43
M31
BB44
AN34
AN35
R30
R32
Y12
AJ30
AJ32
AJ26
AJ28
AK20
AK26
AK28
BE22
AK18
AN11
AK22
AM18
AM20
AM22
AP22
AR22
AT22
VCCSUS3_3
VCCSUS3_3
VCCDSW3_3
DCPSST
VCC3_3
VCC3_3
VCC3_3
VCCIO
VCCSUSHDA
VCCSUS3_3
VCCRTC
DCPRTC
DCPRTC
V_PROC_IO
V_PROC_IO
VCCSPI
VCCASW
VCCASW
VCCVRM
VCC3_3
VCC3_3
16
Layout note:
1.312A
+1.05V +V1.05S_PCH_VCC
C103
1U/10V/X5R_4
R230
*0_8_SJ_NC
C107 22U/6.3V_6
R235
*SJ0603_NC
TP165
+1V5RUN_VCCVRM
R236
*SJ0402_NC
+3V3RUN_CLKFLEX
+3V3RUN_CLKFLEX
R239
112
C134 1U/10V/X5R_4
R243
112
C139 1U/10V/X5R_4
R227 0_1206
C99 10U/6.3V_6
C101 1U/10V/X5R_4
C92 1U/10V/X5R_4
C93 1U/10V/X5R_4
5.11/F_4
+PCH_VCCDSW+PCH_VCCDSW_R
R229
Layout note:
0.67A
+V1.05M_VCCASW+1.05V
2
112
C108 1U/10V/X5R_4
C109 1U/10V/X5R_4
C110 0.1U/16V/X7R_4
2
+V1.05S_VCCAUSB
112
C112 0.1U/16V/X7R_4
C115 0.1U/16V/X7R_4
C117 1U/10V/X5R_4
28mA (10mils)
+1V05_DCPSUS2
C120 10U/6.3V_6
C122 *10U/6.3V_6_NC
C124 1U/10V/X5R_4
C126 1U/10V/X5R_4
2
+3V3RUN_CLKFLEX
112
C128 1U/10V/X5R_4
C131 1U/10V/X5R_4
2
+V3.3S_VCC_ASEPCI
2
+VCCCLKF135
+V1.05S_VCC_SSCFF
+V1.05S_VCCCLKF100
+V1.05S_VCCSSCF100
5
D D
DVT2
C C
+3V3S5_PCH
DVT2
+1.05V
+3V3RUN_PCH
B B
+V1.05S_VCC_EXP
+V1.05S_PCH_VCC
DVT2
+3.3V_RUN
Layout note:
55mA
+3.3V_RUN
*SJ0402_NC
+1.05V
*SJ0603_NC
A A
DVT2
Lynx Point (Power)
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VSS
VCCUSBPLL
VCC3_3
VCCIO
VCCIO
VCCIO
VCCIO
DCPSUS2
VCCVRM
VCC
VCCCLK
VCCCLK3_3
VCCCLK3_3
VCCCLK3_3
VCCCLK3_3
VCCCLK3_3
VCCCLK3_3
VCCCLK
VCCCLK
VCCCLK
VCCCLK
VCCCLK
VCCCLK
VCCCLK
VCCCLK
VCCCLK
LPT_PCH_M_EDS
CRT DAC
HVCMOS
Core
USB3
PCIe/DMI
SATA
VCCMPHY
PLL
PLL
CLK_FLEX0
CLK_FLEX1
CLK_FLEX2
CLK_FLEX3
Layout note:
0.306A
FDI
LPT_PCH_M_EDS
USB
7 OF 11
Layout note:
15mA
ICC
4
GPIO/LPC
RTC
Fuse
Thermal
Azalia
CPU
SPI
PLL
PLL
PLL
PLL
PLL
VCCADAC1_5
VCCADACBG3_3
VCC3_3_R30
VCC3_3_R32
VCCSUS3_3
VCCSUS3_3
8 OF 11
U4G BOMCMB_LPT_PCH_M_EDS/BGA
AA24
VCC
AA26
VCC
AD20
VCC
AD22
VCC
AD24
VCC
AD26
VCC
AD28
VCC
AE18
VCC
AE20
VCC
AE22
VCC
AE24
VCC
AE26
VCC
AG18
VCC
AG20
VCC
AG22
VCC
AG24
VCC
Y26
VCC
U14
DCPSUSBYP
AA18
VCCASW
U18
VCCASW
U20
VCCASW
U22
VCCASW
U24
VCCASW
V18
VCCASW
V20
VCCASW
V22
VCCASW
V24
VCCASW
Y18
VCCASW
Y20
VCCASW
Y22
VCCASW
Lynx Point (Power)
U4H BOMCMB_LPT_PCH_M_EDS/BGA
R24
R26
R28
U26
M24
U35
L24
U30
V28
V30
Y30
Y35
AF34
AP45
Y32
M29
L29
L26
M26
U32
V32
AD34
AA30
AA32
AD35
AG30
AG32
AD36
AE30
AE32
+1.5V_RUN
Layout note: 13.3mA
+3.3V_RUN
+1V5RUN_VCCVRM
+3V3RUN_PCH
TP163
TP164
+V1.05S_VCC_EXP
+1V5RUN_VCCVRM
+1V5RUN_VCCVRM
+V1.05S_VCC_EXP
+1V5RUN_VCCVRM
C114 0.1U/16V/X7R_4
+3V3S5_PCH
+3V3S5_PCH
C127 0.1U/16V/X7R_4
2
R237*SJ0402_NC
112
CRB-GR Rev1.5: +1V05
CRB-GR Rev0.7: +3V3
3
+3V3RUN_PCH
Layout note:
10mA
+3V_RTC
Layout note:
+VCCIO_PCH
4mA
+3.3V_SUS
DVT2
+V1.05S_PCH_VCC
+3V3RUN_PCH
Layout note:
22mA
PCH VCCIO Power
+V1.05S_VCC_EXP+1.05V
112
112
2
2
R226 *SJ_1206
R10 *SJ_1206
DVT2
C91
10U/6.3V_6
Layout note:
3.629A
C94
1U/10V/X5R_4
C95
1U/10V/X5R_4
C96
1U/10V/X5R_4
C97
1U/10V/X5R_4
Layout note:
Close to pin
AN34,AN35
C98
1U/10V/X5R_4
DVT2
Layout note:
183mA
+1V5RUN_VCCVRM+1.5V_RUN
+1.05V
*SJ0603_NC
2
112
Layout note:
4mA
+VCCIO_PCH+1.05V
2
112
C839
0.1U/16V/X7R_4
Layout note:
306mA
2
R241
112
C137
1U/10V/X5R_4
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
R231
*SJ0603_NC
R233
*SJ0402_NC
DVT2
+1.05V +V1.05S_VCCCLKF100 +V1.05S_VCC_SSCFF+1.05V +1.05V +V1.05S_VCCSSCF100
2
R240
*SJ0603_NC
112
C136
1U/10V/X5R_4
2
Layout note:
0.133A + 22mA
R232
112
*SJ0603_NC
Layout note:
261mA + 10mA + 15mA
R234
112
*SJ0603_NC
*SJ0603_NC
LPT 5/6 (POWER)
LPT 5/6 (POWER)
LPT 5/6 (POWER)
Thursday, May 08, 2014
Thursday, May 08, 2014
Thursday, May 08, 2014
+3V3RUN_PCH+3.3V_RUN
2
+3V3S5_PCH+3.3V_SUS
2
2
R242
112
C138
AM7
AM7
AM7
16 51
16 51
16 51
C833
1U/10V/X5R_4
1U/10V/X5R_4
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
PROJECT :
1
C0
C0
C0
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