Dell 11-3147 Schematic

5

D D

4

3

2

1

Redwood 11.6" Schematic Document

Bay Trail - M

C C

2014-04-01
REV : A00

DY : None Installed

B B

Wistron Confidential document, Anyone can not
Duplicate, Modify, Forward or any other purpose

A A

5

4

www.vinafix.vn

3

2

application without get Wistron permission

<Core Design>

<Core Design>

<Core Design>

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Title

Title

Size Document N umber Rev

Size Document N umber Rev

Size Document N umber Rev
A3

A3

A3

Tuesday, April 01, 2014

Tuesday, April 01, 2014

Tuesday, April 01, 2014

Date: Sheet of

Date: Sheet of

Date: Sheet of

Cover Page

Cover Page

Cover Page

Redwood 11.6"

Redwood 11.6"

Redwood 11.6"

Taipei Hsien 221, Taiwan, R.O.C.

1 102

1 102

1 102

1

A00

A00

A00

5

D D

4

LCD 11.6"

11.6 HD (1366 x 768)

USB2.0

HDMI 1.4a

C C

USB3.0 / Power share

2CH
SPEAKER

USB3.0

USB2.0

34

USB PowerShare

TI
TPS2544RTER

HD Audio Codec

RealTek
ALC3234

Combo Jack

SPI Flash

W25Q64FWSSIG
8MB

B B

4

3

Redwood 11.6" Board Block Diagram

DDR3L/ 1.35V

Intel CPU

DDR3L 1333MHz Channel A

Bay Trail-M

BGA1170

Package

eDP

52

USB2.0x1

33

HDMI

54

USB2.0

34

HD Audio

27

SPI

25

I2C

25*27*1.4

USB 3.0/2.0 ports (4)

ETHERNET (10/100/1000Mb)

High Definition Audio

SATA ports (2)

PCIe ports (4)

LPC I/F

5,7,8,9,10,
11,15,16,18,19,21

PCIe x 1 Port0

USB2.0 x 1

USB2.0 x 1

SMBus

SATA PORT0

USB 2.0 HUB1

2.0 ports(4)

AU6259661

Free Fall Sensor

ST LNG3DMTR

DDR3L-1333

Slot 1

USB2.0 x 1

USB2.0 x 1

USB2.0 x 1

35

68

12

USB 2.0 HUB2

2.0 ports(4)

AU6259661

Touch Panel

Sensor Hub

ST
STM32L151CBU6

Camera / ALS

INT2

67

64

HDD

USB2.0 x 1

USB2.0 x 1

USB2.0 x 1

52

2

Project code : 4PD00K010001
PCB P/N : 13270
Revision : -1

IO Board

NGFF
WLAN & BT
combo module

Card reader

RealTek
RTS5176

USB2.0

I2C

56

Gyro

ST
L3GD20

G + E-compass

ST
LSM303D

HOME button BD on Panel side

SD/SDHC/MMC

G Sensor

ST LNG3DMTR

1

CHARGER
BQ24715J

INPUTS

DCBATOUT

SYSTEM DC/DC
TPS51225

INPUTS

DCBATOUT

CPU DC/DC
ISL95833

INPUTS

DCBATOUT

SYSTEM DC/DC
SY8206

INPUTS

DCBATOUT

SYSTEM DC/DC
TPS51363

INPUTS

DCBATOUT

SYSTEM LDO
TLV70218

INPUTS

3D3V_S5

SYSTEM LDO
TLV70215

INPUTS

67

3D3V_S5

Step Down Regulator
SYW232

INPUTS

1D0V_S0_PG

LOAD SWITCH
TPS22966

INPUTS OUTPUTS

LOAD SWITCH
TPS22965

INPUTS OUTPUTS

1D0V_S5

5V_S5

3D3V_S5

OUTPUTS

BT+

OUTPUTS

46-47

OUTPUTS

VCC_CORE

OUTPUTS

1D0V_S5

OUTPUTS

1D35V_S3

OUTPUTS

1D8V_S5

OUTPUTS

1D5V_S0

OUTPUTS

1D05V_S0

1D8V_S01D8V_S5

1D0V_S0

44

45

50

49

51

51

51

37

37

LPC BUS

LPC debug port

65

KBC

Touch PAD

SPI Flash

PM25LD010C
128KB

A A

5

PS2

62

SPI

25

4

NUVOTON
NPCE285P

Int.
KB

62

SMBus

SMBus

24

Thermal

NUVOTON
NCT7718W

Charger

TI
BQ24715J

DC FAN Controller

ANPEC
APL5606AKI

3

26

44

DC FAN

26 26

Module

Title

Title

Title

Size Document Num ber Rev

Size Document Num ber Rev

Size Document Num ber Rev
A2

A2

A2

Tuesday, April 01, 2014

Tuesday, April 01, 2014

Tuesday, April 01, 2014
Date: Sheet of

Date: Sheet of

2

Date: Sheet of

PCB LAYER

L1:Top
L2:VCC
L3:Signal

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin T ai Wu Rd., H sichih,

21F, 88, Sec.1, Hsin T ai Wu Rd., H sichih,

21F, 88, Sec.1, Hsin T ai Wu Rd., H sichih,
Taipei Hsie n 221, Taiwan, R.O.C.

Taipei Hsie n 221, Taiwan, R.O.C.

Taipei Hsie n 221, Taiwan, R.O.C.

Block Diagram

Block Diagram

Block Diagram

Redwood 11.6"

Redwood 11.6"

Redwood 11.6"

1

L4:Signal
L5:GND
L6:Bottom

2 102

2 102

2 102

A00

A00

A00

www.vinafix.vn

5

4

3

2

1

USB Port Block Diagram

D D

Intel CPU

Port0 USB2.0x1

USB3.0 CONN

34

Bay Trail-M

BGA1170

Port1

Package
25*27*1.4

C C

25M Xtal

32.768 Xtal

Port3

B B

USB2.0x1

USB2.0x1Port2

USB2.0 x 1

Left USB2.0 CONN [Debug]

HD CAMERA

USB 2.0 HUB1

2.0 ports(4)

52

Port1

AU6259C61

Port2

Port3

Port4

33

USB2.0 x 1

USB2.0 x 1

USB2.0 x 1

Sensor Hub

12M Xtal

Touch Screen

Panel side

Port1

Port2

IO Board

USB2.0 x 1

USB2.0 x 1

SD Card reader

Right USB2.0 CONN

67

USB 2.0 HUB2

2.0 ports(4)

52

AU6259C61

12M Xtal

35

Port3

USB2.0 x 1

NGFF
WLAN & BT
combo module

Port4

12M Xtal

<Core Design>

<Core Design>

A A

www.vinafix.vn

<Core Design>

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Title

Title

Size Document N umber Rev

Size Document N umber Rev

Size Document N umber Rev
A3

A3

A3

Tuesday, April 01, 2014

Tuesday, April 01, 2014

Tuesday, April 01, 2014

Date: Sheet of

Date: Sheet of

Date: Sheet of

USB Block Diagram

USB Block Diagram

USB Block Diagram

Redwood 11.6"

Redwood 11.6"

Redwood 11.6"

Taipei Hsien 221, Taiwan, R.O.C.

3 102

3 102

3 102

A00

A00

A00

5

4

3

2

1

Clock Block Diagram

D D

DIMM

DRAM0_CKP_0

DRAM0_CKN_0

DRAM0_CKP_2

DRAM0_CKN_2

M_A_DIM0_CLK_DDR0

M_A_DIM0_CLK_DDR#0

M_A_DIM0_CLK_DDR1

M_A_DIM0_CLK_DDR#1

Intel CPU

Bay Trail-M

BGA1170

Package
25*27*1.4

CLK_PCI_LPC_RCLK_PCI_LPC

CLK_PCI_KBCCLK_PCI_KBC_R

XDP

Debug Card

KBC

NPCE285PA

EC_SPI_CLK EC_SPI_CLK_FLASH

SPI ROM

PM25LD010C

SPI ROM

W25Q64FW

C C

B B

PCH_SPI_CLK_FLASH PCH_SPI_CLK

25MHz

32.768MHz

ICLK_OSCIN

ICLK_OSCOUT

ILB_RTC_X1

ILB_RTC_X2

CLK_PCIE_WLAN_N0

CLK_PCIE_WLAN_P0

HDA_BITCLK

HDMI_CLK_R

HDMI_CLK_R#

USB2.0 x 1

12MHz

USB2.0 x 1

WLAN

NGFF Card

Audio

ALC3234

HDMI CONN

USB 2.0 HUB1

2.0 ports(4)

AU6259C61

XSCO

XSCI

Sensor Hub

STM32L151

OSC_IN

12MHz

USB2.0 x 1

USB 2.0 HUB1

2.0 ports(4)

AU6259C61

XSCO

XSCI

12MHz

A A

5

4

www.vinafix.vn

3

OSC_OUT

<Core Desig n>

<Core Desig n>

<Core Desig n>

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin T ai Wu Rd., H sichih,

21F, 88, Sec.1, Hsin T ai Wu Rd., H sichih,

21F, 88, Sec.1, Hsin T ai Wu Rd., H sichih,
Taipei Hsie n 221, Taiwan, R.O.C.

Taipei Hsie n 221, Taiwan, R.O.C.

Title

Title

Title

Size Document Num ber Rev

Size Document Num ber Rev

Size Document Num ber Rev
A2

A2

A2

Tuesday, April 01, 2014

Tuesday, April 01, 2014

Tuesday, April 01, 2014

Date: Sheet of

Date: Sheet of

Date: Sheet of

2

Taipei Hsie n 221, Taiwan, R.O.C.

Clock Block diagram

Clock Block diagram

Clock Block diagram

Redwood 11.6"

Redwood 11.6"

Redwood 11.6"

4 102

4 102

4 102

1

A00

A00

A00

SSID = CPU

5

4

3

2

1

D D

M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5

M_A_DIM0_CS#0(12)

M_A_DIM0_CS#1(12)

DRAMA_DRA MRST

DRAM_VREF

ICLK_DRAM_TER MN
ICLK_DRAM_TER MN_AF42

DDR3_DR AM_PWROK
DDR3_VCC A_PWRGD

DRAM_RCO MP_0
DRAM_RCO MP_1
DRAM_RCO MP_2

M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15

DRAMA_DM_0
DRAMA_DM_1
DRAMA_DM_2
DRAMA_DM_3
DRAMA_DM_4
DRAMA_DM_5
DRAMA_DM_6
DRAMA_DM_7

M_A_A[15:0](12)

DRAMA_DM_0(12)
DRAMA_DM_1(12)
DRAMA_DM_2(12)
DRAMA_DM_3(12)
DRAMA_DM_4(12)
DRAMA_DM_5(12)
DRAMA_DM_6(12)
DRAMA_DM_7(12)

M_A_RAS#(12)
M_A_CAS#(12)

M_A_WE#(12)

M_A_BS0( 12)
M_A_BS1( 12)
M_A_BS2( 12)

C C

B B

M_A_DIM0_CKE0(12)

M_A_DIM0_CKE1(12)

M_A_DIM0_ODT0(12)

M_A_DIM0_ODT1(12)

M_A_DIM0_CLK_DDR 0(12)

M_A_DIM0_CLK_DDR #0(12)

M_A_DIM0_CLK_DDR 1(12)

M_A_DIM0_CLK_DDR #1(12)

DRAMA_DRA MRST(12)

DDR3_DR AM_PWROK(3 6)
DDR3_VCC A_PWRGD(36)

CPU1A

CPU1A

K45

DRAM0_MA_0

H47

DRAM0_MA_1

L41

DRAM0_MA_2

H44

DRAM0_MA_3

H50

DRAM0_MA_4

G53

DRAM0_MA_5

H49

DRAM0_MA_6

D50

DRAM0_MA_7

G52

DRAM0_MA_8

E52

DRAM0_MA_9

K48

DRAM0_MA_10

E51

DRAM0_MA_11

F47

DRAM0_MA_12

J51

DRAM0_MA_13

B49

DRAM0_MA_14

B50

DRAM0_MA_15

G36

DRAM0_DM_0

B36

DRAM0_DM_1

F38

DRAM0_DM_2

B42

DRAM0_DM_3

P51

DRAM0_DM_4

V42

DRAM0_DM_5

Y50

DRAM0_DM_6

Y52

DRAM0_DM_7

M45

DRAM0_RAS

M44

DRAM0_CAS

H51

DRAM0_WE

K47

DRAM0_BS_0

K44

DRAM0_BS_1

D52

DRAM0_BS_2

P44

DRAM0_CS_0

P45

DRAM0_CS_2

C47

DRAM0_CKE_0

D48

RESERVED_D48

F44

DRAM0_CKE_2

E46

RESERVED_E46

T41

DRAM0_ODT_0

P42

DRAM0_ODT_2

M50

DRAM0_CKP_0

M48

DRAM0_CKN_0

P50

DRAM0_CKP_2

P48

DRAM0_CKN_2

P41

DRAM0_DRAMRST

AF44

DRAM_VREF

AH42

ICLK_DRAM_TERMN

AF42

ICLK_DRAM_TERMN_AF42

AD42

DRAM_VDD_S4_PWROK

AB42

DRAM_CORE_PWROK

AD44

DRAM_RCOMP_0

AF45

DRAM_RCOMP_1

AD45

DRAM_RCOMP_2

AF40

RESERVED_AF40

AF41

RESERVED_AF41

AD40

RESERVED_AD40

AD41

RESERVED_AD41

BAY-TRAIL-GP

BAY-TRAIL-GP

BAY TRAIL-M/D SOC

BAY TRAIL-M/D SOC

1 OF 13

1 OF 13

DRAM0_DQ_0
DRAM0_DQ_1
DRAM0_DQ_2
DRAM0_DQ_3
DRAM0_DQ_4
DRAM0_DQ_5
DRAM0_DQ_6
DRAM0_DQ_7
DRAM0_DQ_8

DRAM0_DQ9_C32

DRAM0_DQ_10
DRAM0_DQ_11
DRAM0_DQ_12
DRAM0_DQ_13
DRAM0_DQ_14
DRAM0_DQ_15
DRAM0_DQ_16
DRAM0_DQ_17
DRAM0_DQ_18
DRAM0_DQ_19
DRAM0_DQ_20
DRAM0_DQ_21
DRAM0_DQ_22
DRAM0_DQ_23
DRAM0_DQ_24
DRAM0_DQ_25
DRAM0_DQ_26
DRAM0_DQ_27
DRAM0_DQ_28
DRAM0_DQ_29
DRAM0_DQ_30
DRAM0_DQ_31
DRAM0_DQ_32
DRAM0_DQ_33
DRAM0_DQ_34
DRAM0_DQ_35
DRAM0_DQ_36
DRAM0_DQ_37
DRAM0_DQ_38
DRAM0_DQ_39
DRAM0_DQ_40
DRAM0_DQ_41
DRAM0_DQ_42
DRAM0_DQ_43
DRAM0_DQ_44
DRAM0_DQ_45
DRAM0_DQ_46
DRAM0_DQ_47
DRAM0_DQ_48
DRAM0_DQ_49
DRAM0_DQ_50
DRAM0_DQ_51
DRAM0_DQ_52
DRAM0_DQ_53
DRAM0_DQ_54
DRAM0_DQ_55
DRAM0_DQ_56
DRAM0_DQ_57
DRAM0_DQ_58
DRAM0_DQ_59
DRAM0_DQ_60
DRAM0_DQ_61
DRAM0_DQ_62
DRAM0_DQ_63

DRAM0_DQSP_0
DRAM0_DQSN_0
DRAM0_DQSP_1
DRAM0_DQSN_1
DRAM0_DQSP_2
DRAM0_DQSN_2
DRAM0_DQSP_3
DRAM0_DQSN_3
DRAM0_DQSP_4
DRAM0_DQSN_4
DRAM0_DQSP_5
DRAM0_DQSN_5
DRAM0_DQSP_6
DRAM0_DQSN_6
DRAM0_DQSP_7
DRAM0_DQSN_7

M36
J36
P40
M40
P36
N36
K40
K42
B32
C32
C36
A37
C33
A33
C37
B38
F36
G38
F42
J42
G40
C38
G44
D42
A41
C41
A45
B46
C40
B40
B48
B47
K52
K51
T52
T51
L51
L53
R51
R53
T47
T45
Y40
V41
T48
T50
Y42
AB40
V45
V47
AD48
AD50
V48
V50
AB44
Y45
V52
W51
AC53
AC51
W53
Y51
AD52
AD51

J38
K38
C35
B34
D40
F40
B44
C43
N53
M52
T42
T44
Y47
Y48
AB52
AA51

M_A_DQ<0>
M_A_DQ<1>
M_A_DQ<2>
M_A_DQ<3>
M_A_DQ<4>
M_A_DQ<5>
M_A_DQ<6>
M_A_DQ<7>
M_A_DQ<8>

M_A_DQ<9>
M_A_DQ<10>
M_A_DQ<11>
M_A_DQ<12>
M_A_DQ<13>
M_A_DQ<14>
M_A_DQ<15>
M_A_DQ<16>
M_A_DQ<17>
M_A_DQ<18>
M_A_DQ<19>
M_A_DQ<20>
M_A_DQ<21>
M_A_DQ<22>
M_A_DQ<23>
M_A_DQ<24>
M_A_DQ<25>
M_A_DQ<26>
M_A_DQ<27>
M_A_DQ<28>
M_A_DQ<29>
M_A_DQ<30>
M_A_DQ<31>
M_A_DQ<32>
M_A_DQ<33>
M_A_DQ<34>
M_A_DQ<35>
M_A_DQ<36>
M_A_DQ<37>
M_A_DQ<38>
M_A_DQ<39>
M_A_DQ<40>
M_A_DQ<41>
M_A_DQ<42>
M_A_DQ<43>
M_A_DQ<44>
M_A_DQ<45>
M_A_DQ<46>
M_A_DQ<47>
M_A_DQ<48>
M_A_DQ<49>
M_A_DQ<50>
M_A_DQ<51>
M_A_DQ<52>
M_A_DQ<53>
M_A_DQ<54>
M_A_DQ<55>
M_A_DQ<56>
M_A_DQ<57>
M_A_DQ<58>
M_A_DQ<59>
M_A_DQ<60>
M_A_DQ<61>
M_A_DQ<62>
M_A_DQ<63>

M_A_DQS_DP<0>
M_A_DQS_DN< 0>
M_A_DQS_DP<1>
M_A_DQS_DN< 1>
M_A_DQS_DP<2>
M_A_DQS_DN< 2>
M_A_DQS_DP<3>
M_A_DQS_DN< 3>
M_A_DQS_DP<4>
M_A_DQS_DN< 4>
M_A_DQS_DP<5>
M_A_DQS_DN< 5>
M_A_DQS_DP<6>
M_A_DQS_DN< 6>
M_A_DQS_DP<7>
M_A_DQS_DN< 7>

M_A_DQ<0> (12)
M_A_DQ<1> (12)
M_A_DQ<2> (12)
M_A_DQ<3> (12)
M_A_DQ<4> (12)
M_A_DQ<5> (12)
M_A_DQ<6> (12)
M_A_DQ<7> (12)
M_A_DQ<8> (12)

M_A_DQ<9> (12)
M_A_DQ<10> (12)
M_A_DQ<11> (12)
M_A_DQ<12> (12)
M_A_DQ<13> (12)
M_A_DQ<14> (12)
M_A_DQ<15> (12)
M_A_DQ<16> (12)
M_A_DQ<17> (12)
M_A_DQ<18> (12)
M_A_DQ<19> (12)
M_A_DQ<20> (12)
M_A_DQ<21> (12)
M_A_DQ<22> (12)
M_A_DQ<23> (12)
M_A_DQ<24> (12)
M_A_DQ<25> (12)
M_A_DQ<26> (12)
M_A_DQ<27> (12)
M_A_DQ<28> (12)
M_A_DQ<29> (12)
M_A_DQ<30> (12)
M_A_DQ<31> (12)
M_A_DQ<32> (12)
M_A_DQ<33> (12)
M_A_DQ<34> (12)
M_A_DQ<35> (12)
M_A_DQ<36> (12)
M_A_DQ<37> (12)
M_A_DQ<38> (12)
M_A_DQ<39> (12)
M_A_DQ<40> (12)
M_A_DQ<41> (12)
M_A_DQ<42> (12)
M_A_DQ<43> (12)
M_A_DQ<44> (12)
M_A_DQ<45> (12)
M_A_DQ<46> (12)
M_A_DQ<47> (12)
M_A_DQ<48> (12)
M_A_DQ<49> (12)
M_A_DQ<50> (12)
M_A_DQ<51> (12)
M_A_DQ<52> (12)
M_A_DQ<53> (12)
M_A_DQ<54> (12)
M_A_DQ<55> (12)
M_A_DQ<56> (12)
M_A_DQ<57> (12)
M_A_DQ<58> (12)
M_A_DQ<59> (12)
M_A_DQ<60> (12)
M_A_DQ<61> (12)
M_A_DQ<62> (12)
M_A_DQ<63> (12)

M_A_DQS_DP<0> ( 12)
M_A_DQS_DN< 0> (12)
M_A_DQS_DP<1> ( 12)
M_A_DQS_DN< 1> (12)
M_A_DQS_DP<2> ( 12)
M_A_DQS_DN< 2> (12)
M_A_DQS_DP<3> ( 12)
M_A_DQS_DN< 3> (12)
M_A_DQS_DP<4> ( 12)
M_A_DQS_DN< 4> (12)
M_A_DQS_DP<5> ( 12)
M_A_DQS_DN< 5> (12)
M_A_DQS_DP<6> ( 12)
M_A_DQS_DN< 6> (12)
M_A_DQS_DP<7> ( 12)
M_A_DQS_DN< 7> (12)

AW41

AY45
BB47

BB44
BB50
BC53
BB49
BF50
BC52
BE52
AY48
BE51
BD47
BA51
BH49
BH50

BD38
BH36
BC36
BH42
AT51
AM42
AK50
AK52

AV45
AV44
BB51

AY47
AY44
BF52

AT44

AT45

BG47
BE46
BD44
BF48

AP41

AT42

AV50
AV48

AT50
AT48

AT41

CPU1B

CPU1B

DRAM1_MA_0
DRAM1_MA_1
DRAM1_MA_2
DRAM1_MA_3
DRAM1_MA_4
DRAM1_MA_5
DRAM1_MA_6
DRAM1_MA_7
DRAM1_MA_8
DRAM1_MA_9
DRAM1_MA_10
DRAM1_MA_11
DRAM1_MA_12
DRAM1_MA_13
DRAM1_MA_14
DRAM1_MA_15

DRAM1_DM_0
DRAM1_DM_1
DRAM1_DM_2
DRAM1_DM_3
DRAM1_DM_4
DRAM1_DM_5
DRAM1_DM_6
DRAM1_DM_7

DRAM1_RAS
DRAM1_CAS
DRAM1_WE

DRAM1_BS_0
DRAM1_BS_1
DRAM1_BS_2

DRAM1_CS_0

DRAM1_CS_2

DRAM1_CKE_0
RESERVED_BE46
DRAM1_CKE_2
RESERVED_BF48

DRAM1_ODT_0

DRAM1_ODT_2

DRAM1_CKP_0
DRAM1_CKN_0

DRAM1_CKP_2
DRAM1_CKN_2

DRAM1_DRAMRST

BAY-TRAIL-GP

BAY-TRAIL-GP

BAY TRAIL-M/D SOC

BAY TRAIL-M/D SOC

2 OF 13

2 OF 13

DRAM1_DQ_0
DRAM1_DQ_1
DRAM1_DQ_2
DRAM1_DQ_3
DRAM1_DQ_4
DRAM1_DQ_5
DRAM1_DQ_6
DRAM1_DQ_7
DRAM1_DQ_8

DRAM1_DQ_9
DRAM1_DQ_10
DRAM1_DQ_11
DRAM1_DQ_12
DRAM1_DQ_13
DRAM1_DQ_14
DRAM1_DQ_15
DRAM1_DQ_16
DRAM1_DQ_17
DRAM1_DQ_18
DRAM1_DQ_19
DRAM1_DQ_20
DRAM1_DQ_21
DRAM1_DQ_22
DRAM1_DQ_23
DRAM1_DQ_24
DRAM1_DQ_25
DRAM1_DQ_26
DRAM1_DQ_27
DRAM1_DQ_28
DRAM1_DQ_29
DRAM1_DQ_30
DRAM1_DQ_31
DRAM1_DQ_32
DRAM1_DQ_33
DRAM1_DQ_34
DRAM1_DQ_35
DRAM1_DQ_36
DRAM1_DQ_37
DRAM1_DQ_38
DRAM1_DQ_39
DRAM1_DQ_40
DRAM1_DQ_41
DRAM1_DQ_42
DRAM1_DQ_43
DRAM1_DQ_44
DRAM1_DQ_45
DRAM1_DQ_46
DRAM1_DQ_47
DRAM1_DQ_48
DRAM1_DQ_49
DRAM1_DQ_50
DRAM1_DQ_51
DRAM1_DQ_52
DRAM1_DQ_53
DRAM1_DQ_54
DRAM1_DQ_55
DRAM1_DQ_56
DRAM1_DQ_57
DRAM1_DQ_58
DRAM1_DQ_59
DRAM1_DQ_60
DRAM1_DQ_61
DRAM1_DQ_62
DRAM1_DQ_63

DRAM1_DQSP_0
DRAM1_DQSN_0
DRAM1_DQSP_1
DRAM1_DQSN_1
DRAM1_DQSP_2
DRAM1_DQSN_2
DRAM1_DQSP_3
DRAM1_DQSN_3
DRAM1_DQSP_4
DRAM1_DQSN_4
DRAM1_DQSP_5
DRAM1_DQSN_5
DRAM1_DQSP_6
DRAM1_DQSN_6
DRAM1_DQSP_7
DRAM1_DQSN_7

BG38
BC40
BA42
BD42
BC38
BD36
BF42
BC44
BH32
BG32
BG36
BJ37
BG33
BJ33
BG37
BH38
AU36
AT36
AV40
AT40
BA36
AV36
AY42
AY40
BJ41
BG41
BJ45
BH46
BG40
BH40
BH48
BH47
AY52
AY51
AP52
AP51
AW51
AW53
AR51
AR53
AP47
AP45
AK40
AM41
AP48
AP50
AK42
AH40
AM45
AM47
AF48
AF50
AM48
AM50
AH44
AK45
AM52
AL51
AG53
AG51
AL53
AK51
AF52
AF51

BF40
BD40
BG35
BH34
BA38
AY38
BH44
BG43
AU53
AV52
AP42
AP44
AK47
AK48
AH52
AJ51

1D35V_S3

12

R501

R501
4K7R2F-GP

4K7R2F-GP

R502

R502
4K7R2F-GP

4K7R2F-GP

DRAM_VREF

12

C501

C501

SCD1U10V2KX-L-GP

SCD1U10V2KX-L-GP

12

A A

5

4

1 2

R503 100KR2F-L1-GPR503 100KR2F-L1-GP

1 2

R504 100KR2F-L1-GPR504 100KR2F-L1-GP

1 2

R505 23D2R2F-GPR505 23D2R2F-GP

1 2

R506 29D4R2F-GPR506 29D4R2F-GP

1 2

R507 162R2F-GPR507 162R2F-GP

ICLK_DRAM_TER MN

ICLK_DRAM_TER MN_AF42

DRAM_RCO MP_0

DRAM_RCO MP_1

DRAM_RCO MP_2

reserve the 0402 0.1u caps on reset for EMI.

DRAMA_DRA MRST

DDR3_DR AM_PWROK

DDR3_VCC A_PWRGD

3

EC502

EC502

1 2

DY

DY

SCD1U25V2KX- GP

SCD1U25V2KX- GP

EC503

EC503

1 2

DY

DY

SCD1U25V2KX- GP

SCD1U25V2KX- GP

EC504

EC504

1 2

DY

DY

SCD1U25V2KX- GP

SCD1U25V2KX- GP

Wistron Confidential document, Anyone can not
Duplicate, Modify, Forward or any other purpose

<Core Desig n>

<Core Desig n>

<Core Desig n>

Title

Title

Title

Size Document Numb er Rev

Size Document Numb er Rev

Size Document Numb er Rev
A2

A2

A2

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

application without get Wistron permission

CPU (DDR)

CPU (DDR)

CPU (DDR)

Redwood 11.6"

Redwood 11.6"

Redwood 11.6"

Tuesday, April 01, 2014

Tuesday, April 01, 2014

Tuesday, April 01, 2014

1

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin T ai Wu Rd., H sichih,

21F, 88, Sec.1, Hsin T ai Wu Rd., H sichih,

21F, 88, Sec.1, Hsin T ai Wu Rd., H sichih,
Taipei Hsie n 221, Taiwan, R.O.C.

Taipei Hsie n 221, Taiwan, R.O.C.

Taipei Hsie n 221, Taiwan, R.O.C.

5 102

5 102

5 102

A00

A00

A00

www.vinafix.vn

5

4

3

2

1

SSID = CPU

D D

C C

Blanking

B B

Wistron Confidential document, Anyone can not
Duplicate, Modify, Forward or any other purpose
application without get Wistron permission

<Core Design>

<Core Design>

<Core Design>

Wistron Corporation

Wistron Corporation

A A

Title

Title

Title

CPU (CFG)

CPU (CFG)

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev
A4

A4

A4

Date: Sheet of

Date: Sheet of

5

4

www.vinafix.vn

3

Date: Sheet of

CPU (CFG)

Tuesday, April 01, 2014

Tuesday, April 01, 2014

Tuesday, April 01, 2014

2

Redwood 11.6"

Redwood 11.6"

Redwood 11.6"

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

A00

A00

6 102

6 102

6 102

1

A00

5

4

3

2

1

SSID = CPU

VCC_COR E GFX_COR E

12

R703

RN701

1 2

RN701

R1

R1

1

R2

R2

2 3

SRN100F -1-GP

SRN100F -1-GP

CPU1G

CPU1G

P28

CORE_VCC_SENSE_P28

BB8

UNCORE_VNN_SENSE

N28

CORE_VSS_SENSE_N28

AD38

DRAM_VDD_S4_AD38

AF38

DRAM_VDD_S4_AF38

A48

DRAM_VDD_S4

AK38

DRAM_VDD_S4_AK38

AM38

DRAM_VDD_S4_AM38

AV41

DRAM_VDD_S4_AV41

AV42

DRAM_VDD_S4_AV42

BB46

DRAM_VDD_S4_BB46

AA27

CORE_VCC_S0IX_AA27

AA29

CORE_VCC_S0IX_AA29

AA30

CORE_VCC_S0IX_AA30

AC27

CORE_VCC_S0IX_AC27

AC29

CORE_VCC_S0IX_AC29

AC30

CORE_VCC_S0IX_AC30

AD27

CORE_VCC_S0IX_AD27

AD29

CORE_VCC_S0IX_AD29

AD30

CORE_VCC_S0IX_AD30

AF27

CORE_VCC_S0IX_AF27

AF29

CORE_VCC_S0IX_AF29

AG27

CORE_VCC_S0IX_AG27

AG29

CORE_VCC_S0IX_AG29

AG30

CORE_VCC_S0IX_AG30

P26

CORE_VCC_S0IX_P26

P27

CORE_VCC_S0IX_P27

U27

CORE_VCC_S0IX_U27

U29

CORE_VCC_S0IX_U29

V27

CORE_VCC_S0IX_V27

V29

CORE_VCC_S0IX_V29

V30

CORE_VCC_S0IX_V30

Y27

CORE_VCC_S0IX_Y27

Y29

CORE_VCC_S0IX_Y29

Y30

CORE_VCC_S0IX_Y30

AF30

TP_CORE_V1P05_S4

BAY-TRAIL-GP

BAY-TRAIL-GP

4

VCC_AXG _SENSE(48)

BAY TRAIL-M/D SOC

BAY TRAIL-M/D SOC

VCC_AXG _SENSE

UNCORE_VNN_S3_AA24
UNCORE_VNN_S3_AC22
UNCORE_VNN_S3_AC24
UNCORE_VNN_S3_AD22
UNCORE_VNN_S3_AD24

UNCORE_VNN_S3_AF22

UNCORE_VNN_S3_AF24
UNCORE_VNN_S3_AG22
UNCORE_VNN_S3_AG24

UNCORE_VNN_S3_AJ22

UNCORE_VNN_S3_AJ24
UNCORE_VNN_S3_AK22
UNCORE_VNN_S3_AK24
UNCORE_VNN_S3_AK25
UNCORE_VNN_S3_AK27
UNCORE_VNN_S3_AK29
UNCORE_VNN_S3_AK30
UNCORE_VNN_S3_AK32

UNCORE_VNN_S3_AM22

TP2_CORE_VCC_S0IX

D D

VDDQ_CP U1D35V_S 3

PG701

PG701

1 2

GAP-CLOS E-PWR-3-GP

GAP-CLOS E-PWR-3-GP

PG702

PG702

1 2

GAP-CLOS E-PWR-3-GP

GAP-CLOS E-PWR-3-GP

PG703

PG703

1 2

GAP-CLOS E-PWR-3-GP

GAP-CLOS E-PWR-3-GP

PG704

C C

B B

PG704

1 2

GAP-CLOS E-PWR-3-GP

GAP-CLOS E-PWR-3-GP

PG705

PG705

1 2

GAP-CLOS E-PWR-3-GP

GAP-CLOS E-PWR-3-GP

PG706

PG706

1 2

GAP-CLOS E-PWR-3-GP

GAP-CLOS E-PWR-3-GP

VCC_COR E

VDDQ_CP U

VCC_SEN SE(47)
VSS_SEN SE(47)

VSS_AXG _SENSE(48 )

A00

VCC_SEN SE
VSS_SEN SE

R701

R701

0R0402-P AD

0R0402-P AD

VSS_AXG _SENSE

VCC_SEN SE
VCC_AXG _SENSE
VSS_SEN SE

R703

100R2F-L 3-GP

100R2F-L 3-GP

7 OF 13

7 OF 13

DRAM_VDD_S4_BD49
DRAM_VDD_S4_BD52
DRAM_VDD_S4_BD53
DRAM_VDD_S4_BF44
DRAM_VDD_S4_BG51

DRAM_VDD_S4_BJ48

DRAM_VDD_S4_C51
DRAM_VDD_S4_D44
DRAM_VDD_S4_F49
DRAM_VDD_S4_F52
DRAM_VDD_S4_F53
DRAM_VDD_S4_H46
DRAM_VDD_S4_M41
DRAM_VDD_S4_M42
DRAM_VDD_S4_V38
DRAM_VDD_S4_Y38

BD49
BD52
BD53
BF44
BG51
BJ48
C51
D44
F49
F52
F53
H46
M41
M42
V38
Y38

AA24
AC22
AC24
AD22
AD24
AF22
AF24
AG22
AG24
AJ22
AJ24
AK22
AK24
AK25
AK27
AK29
AK30
AK32
AM22

TP2_COR E_VCC_S0IX

AA22

VDDQ_CP U

1

VDDQ_CP U

GFX_COR E

TP702

TP702
TPAD14-O P-GP

TPAD14-O P-GP

VCC_SEN SE

VSS_SEN SE

VSS_AXG _SENSE

VCC_AXG _SENSE

reserve the 0402 0.1u caps on reset for EMI.

A A

DY

DY

DY

DY

DY

DY

DY

DY

5

1 2

1 2

1 2

1 2

EC701

EC701
SCD1U25 V2KX-GP

SCD1U25 V2KX-GP
EC702

EC702
SCD1U25 V2KX-GP

SCD1U25 V2KX-GP
EC703

EC703
SCD1U25 V2KX-GP

SCD1U25 V2KX-GP
EC704

EC704
SCD1U25 V2KX-GP

SCD1U25 V2KX-GP

Wistron Confidential document, Anyone can not
Duplicate, Modify, Forward or any other purpose
application without get Wistron permission

<Core Design>

<Core Design>

<Core Design>

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Title

Title

Size Document N umber Rev

Size Document N umber Rev

Size Document N umber Rev
A3

A3

A3

Date: Sheet of

Date: Sheet of

4

www.vinafix.vn

3

2

Date: Sheet of

CPU (VCC_CORE)

CPU (VCC_CORE)

CPU (VCC_CORE)

Redwood 11.6"

Redwood 11.6"

Tuesday, April 01, 2014

Tuesday, April 01, 2014

Tuesday, April 01, 2014

Redwood 11.6"

Taipei Hsien 221, Taiwan, R.O.C.

7 102

7 102

7 102

1

A00

A00

A00

SSID = CPU

5

4

3

2

1

CPU1C

CPU1C

D D

SRN2K2J -5-GP

SRN2K2J -5-GP

PCH_HDM I_DATA(15,54)

PCH_HDM I_CLK(54)

RN801

RN801

1D8V_S0

2 3

HDMI

4

1

DDBP_DA TA2(54)

DDBP_DA TA2#(54)

DDBP_DA TA1(54)

DDBP_DA TA1#(54)

DDBP_DA TA0(54)

DDBP_DA TA0#(54)

DDBP_DA TA3(54)

DDBP_DA TA3#(54)

HDMI_PCH_ DET(54)

R806

R806
402R2F-G P

402R2F-G P

1 2

DDI0_RCOM P_N
DDI0_RCOM P_P

Close to CPU

C C

AV3
AV2
AT2
AT3
AR3
AR1
AP3
AP2

AL3
AL1

D27

C26
C28

B28
C27
B26

AK13

AK12
AM14
AM13

AM3
AM2

DDI0_TXP_0
DDI0_TXN_0
DDI0_TXP_1
DDI0_TXN_1
DDI0_TXP_2
DDI0_TXN_2
DDI0_TXP_3
DDI0_TXN_3

DDI0_AUXP
DDI0_AUXN

DDI0_HPD

DDI0_DDCDATA
DDI0_DDCCLK

DDI0_VDDEN
DDI0_BKLTEN
DDI0_BKLTCTL

DDI0_RCOMP
DDI0_RCOMP_P
RESERVED_AM14
RESERVED_AM13
VSS_AM3
VSS_AM2

1.0V

1.8V

BAY TRAIL-M/D SOC

BAY TRAIL-M/D SOC

1.0V

1.8V

0.7V

3.3V

T2

RESERVED_T2

T3

RESERVED_T3

AB3

RESERVED_AB3

AB2

RESERVED_AB2

Y3

RESERVED_Y3

Y2

RESERVED_Y2

W3

RESERVED_W3

W1

RESERVED_W1

V2

RESERVED_V2

V3

RESERVED_V3

R3

RESERVED_R3

R1

RESERVED_R1

AD6

RESERVED_AD6

AD4

RESERVED_AD4

AB9

RESERVED_AB9

AB7

RESERVED_AB7

Y4

B B

GPIO_S0_N C13(15)

TP801

TP801

TPAD14-O P-GP

TPAD14-O P-GP

TP802

TP802

TPAD14-O P-GP

TPAD14-O P-GP

GPIO_S0_N C13
GPIO_S0_N C14_C29

1

GPIO_S0_N C12

1

RESERVED_Y4

Y6

RESERVED_Y6

V4

RESERVED_V4

V6

RESERVED_V6

A29

GPIO_S0_NC13

C29

GPIO_S0_NC14_C29

AB14

RESERVED_AB14

B30

GPIO_S0_NC12

C30

RESERVED_C30

BAY-TRAIL-GP

BAY-TRAIL-GP

3 OF 13

3 OF 13

DDI1_TXP_0
DDI1_TXN_0
DDI1_TXP_1
DDI1_TXN_1
DDI1_TXP_2
DDI1_TXN_2
DDI1_TXP_3
DDI1_TXN_3

DDI1_AUXP
DDI1_AUXN

DDI1_HPD

DDI1_DDCDATA

DDI1_DDCCLK

DDI1_VDDEN

DDI1_BKLTEN

DDI1_BKLTCTL

RESERVED_AH14
RESERVED_AH13
RESERVED_AF14
RESERVED_AF13

VSS_AH3
VSS_AH2

VGA_RED

VGA_BLUE

VGA_GREEN

VGA_IREF
VGA_IRTN

VGA_HSYNC
VGA_VSYNC

VGA_DDCCLK

VGA_DDCDATA

RESERVED_T7

RESERVED_T9
RESERVED_AB13
RESERVED_AB12

RESERVED_Y12
RESERVED_Y13
RESERVED_V10

RESERVED_V9
RESERVED_T12
RESERVED_T10
RESERVED_V14
RESERVED_V13
RESERVED_T14
RESERVED_T13

RESERVED_T6
RESERVED_T4

RESERVED_P14

RESERVED_K34

GPIO_S0_NC26

GPIO_S0_NC25

GPIO_S0_NC24

GPIO_S0_NC23

GPIO_S0_NC22

GPIO_S0_NC21

GPIO_S0_NC20

GPIO_S0_NC18

GPIO_S0_NC17

GPIO_S0_NC16

GPIO_S0_NC15

AG3
AG1
AF3
AF2
AD3
AD2
AC3
AC1

AK3
AK2

K30

P30
G30

N30
J30
M30

AH14
AH13
AF14
AF13
AH3
AH2

BA3
AY2
BA1
AW1
AY3

BD2
BF2

BC1
BC2

T7
T9
AB13
AB12
Y12
Y13
V10
V9
T12
T10
V14
V13
T14
T13
T6
T4
P14

K34
D32
N32
J34
K28
F28
F32
D34
J28
D28
M32
F34

DDI1_GEN_ R_DAT

CRT_DDC CLK
CRT_DDC DATA

DP_TXP0 _CPU (52)
DP_TXN0 _CPU (52)

DP_AUXP _CPU (5 2)
DP_AUXN _CPU (52)

DP_HPD (52)

DDI1_GEN_ R_DAT (15)

LVDS_VD D_EN_CPU (52)
L_BKLT_ EN_CPU (24)
L_BKLT_ CTRL_CPU (52)

PANEL

L_BKLT_ EN_CPU

CRT_DDC CLK
CRT_DDC DATA

R813

R813

1MR2J-L3 -GP

1MR2J-L3 -GP

R801

R801
0R0402-P AD

0R0402-P AD

1 2
1 2

R802

R802
0R0402-P AD

0R0402-P AD

12

Wistron Confidential document, Anyone can not
Duplicate, Modify, Forward or any other purpose

A A

5

4

www.vinafix.vn

3

2

application without get Wistron permission

<Core Design>

<Core Design>

<Core Design>

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Title

Title

Size Document N umber Rev

Size Document N umber Rev

Size Document N umber Rev
A3

A3

A3

Date: Sheet of

Date: Sheet of

Date: Sheet of

CPU (DDI/EDP/GPIO)

CPU (DDI/EDP/GPIO)

CPU (DDI/EDP/GPIO)

Redwood 11.6"

Redwood 11.6"

Tuesday, April 01, 2014

Tuesday, April 01, 2014

Tuesday, April 01, 2014

Redwood 11.6"

Taipei Hsien 221, Taiwan, R.O.C.

8 102

8 102

8 102

1

A00

A00

A00

5

4

3

2

1

SSID = CPU

D D

CPU1L

BF30
BF36

BF4
BG31
BG34
BG39
BG42
BG45
BG49

BJ11
BJ15
BJ19
BJ23
BJ27
BJ31
BJ35
BJ39
BJ43
BJ47

BJ7

C14

C31

C34

C39

C42

C45

C49

D12

D16

D24

D30

D36

D38

E19

E35

CPU1L

BAY TRAIL-M/D SOC

BAY TRAIL-M/D SOC

VSS211
VSS212
VSS213
VSS214
VSS215
VSS216
VSS217
VSS218
VSS219
VSS220
VSS221
VSS222
VSS223
VSS224
VSS225
VSS226
VSS227
VSS228
VSS229
VSS230
VSS231
VSS232
VSS233
VSS234
VSS235
VSS236
VSS237
VSS238
VSS239
VSS240
VSS241
VSS242
VSS243
VSS244
VSS245

BAY-TRAIL-GP

BAY-TRAIL-GP

CPU1J

AG38

AH4
AH41
AH45

AH7

AH9

AJ16
AJ21
AJ25
AJ27
AJ29

AJ30
AJ32
AJ33
AJ35
AJ38

AJ53
AK10
AK14
AK16
AK33
AK41
AK44

AM12
AM19
AM24
AM25
AM29
AM33
AM35
AM36
AM40

M28

AJ1

AJ3

CPU1J

BAY TRAIL-M/D SOC

BAY TRAIL-M/D SOC

VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105

BAY-TRAIL-GP

BAY-TRAIL-GP

CPU1I

CPU1I

BAY TRAIL-M/D SOC

BAY TRAIL-M/D SOC

A11

VSS1

A15

VSS2

A19

VSS3

A23

VSS4

A27

VSS5

A31

C C

B B

A35
A39
A43
A47

AA1
AA16
AA19
AA21

AA3
AA32
AA35
AA38
AA53
AB10

AB4
AB41
AB45
AB47
AB48
AB50
AB51

AB6
AC16
AC18
AC19
AC21
AC25
AC33
AC35

VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35

BAY-TRAIL-GP

BAY-TRAIL-GP

9 OF 13

9 OF 13

VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70

AC36
AC38
AD19
AD21
AD25
AD32
AD33
AD47
AD7
AE1
AE11
AE12
AE14
AE3
AE4
AE40
AE42
AE43
AE45
AE46
AE48
AE50
AE51
AE53
AE6
AE8
AE9
AF10
AF12
AF25
AF32
AF47
AG16
AG25
AG36

10 OF 13

10 OF 13

VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140

AH47
AH48
AH50
AH51
AH6
AM44
AM51
AM7
AN1
AN11
AN12
AN14
AN22
AN3
AN33
AN35
AN36
AN38
AN40
AN42
AN43
AN45
AN46
AN48
AN49
AN5
AN51
AN53
AN6
AN8
AN9
AP40
AT12
AT16
AT19

AT24
AT27
AT30
AT35
AT38

AT4
AT47
AT52

AU1

AU24

AU3

AU30
AU38
AU51
AV12
AV13
AV14
AV18
AV19
AV24
AV27
AV30
AV35
AV38
AV47
AV51

AV7

AW13
AW19
AW27

AW3

AW35

AY10
AY22
AY32

CPU1K

CPU1K

BAY TRAIL-M/D SOC

BAY TRAIL-M/D SOC

VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160
VSS161
VSS162
VSS163
VSS164
VSS165
VSS166
VSS167
VSS168
VSS169
VSS170
VSS171
VSS172
VSS173
VSS174
VSS175

BAY-TRAIL-GP

BAY-TRAIL-GP

11 OF 13

11 OF 13

VSS176
VSS177
VSS178
VSS179
VSS180
VSS181
VSS182
VSS183
VSS184
VSS185
VSS186
VSS187
VSS188
VSS189
VSS190
VSS191
VSS192
VSS193
VSS194
VSS195
VSS196
VSS197
VSS198
VSS199
VSS200
VSS201
VSS202
VSS203
VSS204
VSS205
VSS206
VSS207
VSS208
VSS209
VSS210

AY36
AY4
AY50
AY9
BA14
BA19
BA22
BA27
BA32
BA35
BA40
BA53
BB19
BB27
BB35
BC20
BC22
BC26
BC28
BC32
BC34
BC42
BD19
BD24
BD27
BD30
BD35
BE19
BE2
BE35
BE8
BF12
BF16
BF24
BF38

12 OF 13

12 OF 13

VSS246
VSS247
VSS248
VSS249
VSS250
VSS251
VSS252
VSS253
VSS254
VSS255
VSS256
VSS257
VSS258
VSS259
VSS260
VSS261
VSS262
VSS263
VSS264
VSS265
VSS266
VSS267
VSS268
VSS269
VSS270
VSS271
VSS272
VSS273
VSS274
VSS275
VSS276
VSS277
VSS278
VSS279
VSS280

E8
F19
F2
F24
F27
F30
F35
F5
F7
G10
G20
G22
G26
G28
G32
G34
G42
H19
H27
H35
J1
J16
J19
J22
J27
J32
J35
J40
J53
K14
K22
K32
K36
K4
K50

M19
M26
M27
M34
M35
M38
M47
M51

N16
N38
N51
P13
P16
P19
P20
P24
P32
P35
P38

P47
P52

T40

U11
U12
U14
U21

K9
L13
L19
L27
L35

N1

P4

P9

U1

CPU1M

CPU1M

BAY TRAIL-M/D SOC

BAY TRAIL-M/D SOC

VSS281
VSS282
VSS283
VSS284
VSS285
VSS286
VSS287
VSS288
VSS289
VSS290
VSS291
VSS292
VSS293
VSS294
VSS295
VSS296
VSS297
VSS298
VSS299
VSS300
VSS301
VSS302
VSS303
VSS304
VSS305
VSS306
VSS307
VSS308
VSS309
VSS310
VSS311
VSS312
VSS313
VSS314
VSS315

BAY-TRAIL-GP

BAY-TRAIL-GP

13 OF 13

13 OF 13

VSS316
VSS317
VSS318
VSS319
VSS320
VSS321
VSS322
VSS323
VSS324
VSS325
VSS326
VSS327
VSS328
VSS329
VSS330
VSS331
VSS332
VSS333
VSS334
VSS335
VSS336
VSS337
VSS338
VSS339
VSS340
VSS341
VSS342
VSS343
VSS344
VSS345
VSS346
VSS347
VSS348
VSS349
VSS350

U3
U30
U32
U40
U42
U43
U45
U46
U48
U49
U5
U51
U53
U6
U8
U9
V12
V16
V19
V21
V35
V40
V44
V51
V7
Y10
Y14
Y16
Y21
Y25
Y33
Y41
Y44
Y7
Y9

Wistron Confidential document, Anyone can not
Duplicate, Modify, Forward or any other purpose

A A

5

4

www.vinafix.vn

3

2

application without get Wistron permission

<Core Design>

<Core Design>

<Core Design>

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Title

Title

Size Document N umber Rev

Size Document N umber Rev

Size Document N umber Rev
A3

A3

A3

Date: Sheet of

Date: Sheet of

Date: Sheet of

CPU (VSS)

CPU (VSS)

CPU (VSS)

Tuesday, April 01, 2014

Tuesday, April 01, 2014

Tuesday, April 01, 2014

Redwood 11.6"

Redwood 11.6"

Redwood 11.6"

Taipei Hsien 221, Taiwan, R.O.C.

9 102

9 102

9 102

1

A00

A00

A00

5

4

3

2

1

reserve the 0402 0.1u caps on reset for EMI.

VCC_CORE

D D

12

C1024

C1024

SC22U6D3V5MX-L3-GP

SC22U6D3V5MX-L3-GP

12

C1023

C1023

SC22U6D3V5MX-L3-GP

SC22U6D3V5MX-L3-GP

12

C1025

C1025

SC22U6D3V5MX-L3-GP

SC22U6D3V5MX-L3-GP

VCC_CORE

12

EC1026

EC1026

DY

DY

12

EC1028

EC1028

SCD1U25V2KX-GP

SCD1U25V2KX-GP

SCD1U25V2KX-GP

DY

DY

SCD1U25V2KX-GP

Modify 20130806

VCC_CORE

12

C1009

C1009

12

C1010

SC22U6D3V5MX-L3-GP

SC22U6D3V5MX-L3-GP

C1010

12

C1011

SC22U6D3V5MX-L3-GP

SC22U6D3V5MX-L3-GP

C1011

12

C1022

SC22U6D3V5MX-L3-GP

SC22U6D3V5MX-L3-GP

C1022

12

C1012

SC22U6D3V5MX-L3-GP

SC22U6D3V5MX-L3-GP

C1012

12

C1013

SC22U6D3V3MX-1-GP

SC22U6D3V3MX-1-GP

C1013

SC2D2U6D3V2MX-GP

SC2D2U6D3V2MX-GP

放放放放

EC1034

EC1034

SCD1U25V2KX-GP

SCD1U25V2KX-GP

VDDQ_CPU

VDDQ_CPU

1uF

close to pin AD38 & AF38

C1014

C1014

SC1U10V2KX-L1-GP

SC1U10V2KX-L1-GP

12

C1015

C1015

SCD1U10V2KX-L1-GP

SCD1U10V2KX-L1-GP

12

DY

DY

12

EC1029

EC1029

12

EC1030

DY

DY

EC1030

SCD1U25V2KX-GP

SCD1U25V2KX-GP

DY

DY

SCD1U25V2KX-GP

SCD1U25V2KX-GP

reserve the 0402 0.1u caps on reset for EMI.

Wistron Confidential document, Anyone can not
Duplicate, Modify, Forward or any other purpose
application without get Wistron permission

<Core Design>

<Core Design>

<Core Design>

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Title

Title

CPU (Power CAP1)

CPU (Power CAP1)

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev
A4

A4

A4

Date: Sheet of

Date: Sheet of

3

Date: Sheet of

CPU (Power CAP1)

Redwood 11.6"

Redwood 11.6"

Tuesday, April 01, 2014

Tuesday, April 01, 2014

Tuesday, April 01, 2014

2

Redwood 11.6"

10 102

10 102

10 102

12

EC1031

EC1031

SCD1U25V2KX-GP

SCD1U25V2KX-GP

A00

A00

A00

1

C C

VDDQ_CPU

CRB

12

C1001

C1001

B B

GFX_CORE GFX_CORE

12

C1016

C1016

SC1U6D3V2KX-L-1-GP

SC1U6D3V2KX-L-1-GP

A A

12

C1002

12

C1017

C1017

SC1U6D3V2KX-L-1-GP

SC1U6D3V2KX-L-1-GP

C1002

SC2D2U6D3V2MX-GP

SC2D2U6D3V2MX-GP

12

C1003

12

C1018

C1018

SC1U6D3V2KX-L-1-GP

SC1U6D3V2KX-L-1-GP

C1003

SC2D2U6D3V2MX-GP

SC2D2U6D3V2MX-GP

12

C1004

12

C1019

C1019

SC22U6D3V5MX-L3-GP

SC22U6D3V5MX-L3-GP

C1004

SC2D2U6D3V2MX-GP

SC2D2U6D3V2MX-GP

SC2D2U6D3V2MX-GP

SC2D2U6D3V2MX-GP

12

DY

DY

C1020

C1020

SC22U6D3V5MX-L3-GP

SC22U6D3V5MX-L3-GP

12

C1005

C1005

SCD1U10V2KX-L1-GP

SCD1U10V2KX-L1-GP

12

C1021

C1021

SC22U6D3V5MX-L3-GP

SC22U6D3V5MX-L3-GP

12

DY

DY

GFX_CORE

C1006

C1006

SCD1U10V2KX-L1-GP

SCD1U10V2KX-L1-GP

12

DY

DY

12

DY

DY

EC1032

EC1032

SCD1U25V2KX-GP

SCD1U25V2KX-GP

C1007

C1007

SCD1U10V2KX-L1-GP

SCD1U10V2KX-L1-GP

12

DY

DY

12

DY

DY

EC1033

EC1033

SCD1U25V2KX-GP

SCD1U25V2KX-GP

C1008

C1008

SCD1U10V2KX-L1-GP

SCD1U10V2KX-L1-GP

12

DY

DY

reserve the 0402 0.1u caps on reset for EMI.

5

4

www.vinafix.vn

5

4

3

2

1

3D3V_S5 1D35V_S 0

close to pin

N22

12

D D

1D8V_S5

12

C1139

C1139

SC1U6D3V2KX-L-1-GP

SC1U6D3V2KX-L-1-GP

close to pin
AA18

C C

1D35V_S 0

AA25 & AG32

12

12

C1103

C1103

C1104

C1104

SC1U6D3V2KX-L-1-GP

SC1U6D3V2KX-L-1-GP

N18 & P18

12

C1102

C1101

C1101

1D8V_S5 1D8V_S0

C1102

SCD1U10V2KX-L1-GP

SC1U6D3V2KX-L-1-GP

SC1U6D3V2KX-L-1-GP

SCD1U10V2KX-L1-GP

U24 & V25 & N20 & U25

12

C1140

C1140

SC1U6D3V2KX-L-1-GP

SC1U6D3V2KX-L-1-GP

close to pin AD36

12

12

SC1U6D3V2KX-L-1-GP

SC1U6D3V2KX-L-1-GP

C1105

C1105

SC1U6D3V2KX-L-1-GP

SC1U6D3V2KX-L-1-GP

C1106

C1106

SC1U6D3V2KX-L-1-GP

SC1U6D3V2KX-L-1-GP

3D3V_S0 1D35V_S 0

AM27 & AN24

12

C1143

C1143

SC1U6D3V2KX-L-1-GP

SC1U6D3V2KX-L-1-GP

12

C1135

C1135

SC1U6D3V2KX-L-1-GP

close to pin
U38

SC1U6D3V2KX-L-1-GP

12

12

C1136

C1136

SC1U6D3V2KX-L-1-GP

SC1U6D3V2KX-L-1-GP

AJ19 & AG18

C1126

C1126

12

C1127

C1127

SC1U6D3V2KX-L-1-GP

SC1U6D3V2KX-L-1-GP

SC1U6D3V2KX-L-1-GP

SC1U6D3V2KX-L-1-GP

12

C1137

C1137

SC1U6D3V2KX-L-1-GP

SC1U6D3V2KX-L-1-GP

close to pin AF36

close to pin
AG19

close to pin
AM30 & AN32

12

C1138

C1138

SC1U6D3V2KX-L-1-GP

SC1U6D3V2KX-L-1-GP

close to pin AJ18

1D0V_S0

close to pin V36

12

12

C1107

C1107

SC1U6D3V2KX-L-1-GP

SC1U6D3V2KX-L-1-GP

C1108

C1108

close to pin U36

SC1U6D3V2KX-L-1-GP

SC1U6D3V2KX-L-1-GP

12

C1116

C1116

SC1U6D3V2KX-L-1-GP

SC1U6D3V2KX-L-1-GP

12

C1117

C1117

SC1U6D3V2KX-L-1-GP

SC1U6D3V2KX-L-1-GP

12

C1141

C1141

SC1U6D3V2KX-L-1-GP

SC1U6D3V2KX-L-1-GP

1D05V_S 0

12

1D0V_S01D0V_S0

close to pin
AF19

12

C1142

C1142

SC1U6D3V2KX-L-1-GP

SC1U6D3V2KX-L-1-GP

AA33

C1109

C1109

SC1U6D3V2KX-L-1-GP

SC1U6D3V2KX-L-1-GP

close to pin BJ6

12

C1118

C1118

SC1U6D3V2KX-L-1-GP

SC1U6D3V2KX-L-1-GP

12

C1119

C1119

1D5V_S0

X02 RF reqiurement

AM32

12

C1134

C1134

SC1U6D3V2KX-L-1-GP

SC1U6D3V2KX-L-1-GP

1D0V_S5

V18

12

C1120

C1120

SC1U6D3V2KX-L-1-GP

SC1U6D3V2KX-L-1-GP

SC1U6D3V2KX-L-1-GP

SC1U6D3V2KX-L-1-GP

1D35V_S 3

12

DY

DY

12

C1162

C1162

SCD1U25V2KX-GP

SCD1U25V2KX-GP

C1145

C1145

SCD1U10V2KX-L1-GP

SCD1U10V2KX-L1-GP

DY

DY

1D35V_S 0

12

C1149

C1149

SCD1U10V2KX-L1-GP

SCD1U10V2KX-L1-GP

12

C1161

C1161

SCD1U25V2KX-GP

SCD1U25V2KX-GP

DY

DY

12

C1160

C1160

12

12

C1150

C1150

SCD1U10V2KX-L1-GP

SCD1U10V2KX-L1-GP

12

C1159

C1159

SCD1U25V2KX-GP

SCD1U25V2KX-GP

DY

DY

12

C1151

C1151

SCD1U10V2KX-L1-GP

SCD1U10V2KX-L1-GP

12

SCD1U25V2KX-GP

SCD1U25V2KX-GP

DY

DY

C1152

C1152

SCD1U10V2KX-L1-GP

SCD1U10V2KX-L1-GP

C1158

C1158

SCD1U10V2KX-L1-GP

SCD1U10V2KX-L1-GP

DY

DY

12

C1153

C1153

SCD1U10V2KX-L1-GP

SCD1U10V2KX-L1-GP

12

C1157

C1157

SCD1U10V2KX-L1-GP

SCD1U10V2KX-L1-GP

DY

DY

12

C1154

C1154

SCD1U10V2KX-L1-GP

SCD1U10V2KX-L1-GP

3D3V_S05V_S5DCBATOU T

12

C1156

C1156

SCD1U10V2KX-L1-GP

SCD1U10V2KX-L1-GP

DY

DY

12

C1155

C1155

SCD1U10V2KX-L1-GP

SCD1U10V2KX-L1-GP

X02 EMI reqiurement

close to pin
U18 & U19

12

C1114

C1114

SC1U6D3V2KX-L-1-GP

SC1U6D3V2KX-L-1-GP

close to pin
AK18 & AM18

12

C1147

C1147

SC22U6D3V5MX-L3-GP

SC22U6D3V5MX-L3-GP

3

DCBATOU T

12

C1115

C1115

SCD1U10V2KX-L1-GP

SCD1U10V2KX-L1-GP

12

C1148

C1148

SC22U6D3V5MX-L3-GP

SC22U6D3V5MX-L3-GP

2

12

12

EC1102

EC1102

SCD1U25V2KX-GP

SCD1U25V2KX-GP

<Core Design>

<Core Design>

<Core Design>

Title

Title

Title

Size Document N umber Rev

Size Document N umber Rev

Size Document N umber Rev
A3

A3

A3

Date: Sheet of

Date: Sheet of

Date: Sheet of

EC1101

EC1101

SCD1U25V2KX-GP

SCD1U25V2KX-GP

CPU (Power CAP2)

CPU (Power CAP2)

CPU (Power CAP2)

Redwood 11.6"

Redwood 11.6"

Tuesday, April 01, 2014

Tuesday, April 01, 2014

Tuesday, April 01, 2014

Redwood 11.6"

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

11 102

11 102

11 102

1

A00

A00

A00

SC1U6D3V2KX-L-1-GP

SC1U6D3V2KX-L-1-GP

close to pin
V32

1D0V_S0

12

close to pin
AF16 & AF18

1D0V_S0

12

C1110

C1110

SC1U6D3V2KX-L-1-GP

SC1U6D3V2KX-L-1-GP

1D0V_S01D0V_S01D0V_S0

C1133

C1133

SC1U6D3V2KX-L-1-GP

SC1U6D3V2KX-L-1-GP

12

B B

1D0V_S5 1D0V_S01D0V_S0

12

C1121

C1121

SC1U6D3V2KX-L-1-GP

SC1U6D3V2KX-L-1-GP

close to pin C5close to pin

A A

close to pin
AM16

B6

12

12

close to pin
Y19 & C3

C1122

C1122

SC1U6D3V2KX-L-1-GP

SC1U6D3V2KX-L-1-GP

C1130

C1130

SC1U6D3V2KX-L-1-GP

SC1U6D3V2KX-L-1-GP

5

12

C1123

C1123

SCD01U50V2KX-1GP

SCD01U50V2KX-1GP

close to pin
AN18

1D0V_S0

12

12

C1124

C1124

SC1U6D3V2KX-L-1-GP

SC1U6D3V2KX-L-1-GP

close to pin
V22

close to pin
AN25

C1131

C1131

SC1U6D3V2KX-L-1-GP

SC1U6D3V2KX-L-1-GP

12

close to pin
U22

12

C1132

C1132

SC1U6D3V2KX-L-1-GP

SC1U6D3V2KX-L-1-GP

C1125

C1125

C1144

C1144

SCD01U50V2KX-1GP

SCD01U50V2KX-1GP

close to pin
Y18 & G1

4

12

close to pin
AJ36 & AK35 & AK36

12

C1112

C1111

C1111

close to pin
AF21 & AG21

C1112

SC1U6D3V2KX-L-1-GP

SC1U6D3V2KX-L-1-GP

SC1U6D3V2KX-L-1-GP

SC1U6D3V2KX-L-1-GP

close to pin
AA36 & Y35 & Y36

1D0V_S0

12

close to pin
AD35 & AF35

12

C1113

C1113

SC1U6D3V2KX-L-1-GP

SC1U6D3V2KX-L-1-GP

AN29 & AN30 & V24 & Y22 & Y24

C1128

C1128

SC1U6D3V2KX-L-1-GP

SC1U6D3V2KX-L-1-GP

12

C1129

C1129

SC1U6D3V2KX-L-1-GP

SC1U6D3V2KX-L-1-GP

12

C1146

C1146

SC22U6D3V5MX-L3-GP

SC22U6D3V5MX-L3-GP

www.vinafix.vn

5

4

3

2

1

SSID = MEMORY

DIMM1

D D

M_A_A[15:0] (5)

M_A_BS2( 5)

M_A_BS0( 5)
M_A_BS1( 5)

M_A_DQ<0>(5)
M_A_DQ<1>(5)
M_A_DQ<2>(5)
M_A_DQ<3>(5)
M_A_DQ<4>(5)
M_A_DQ<5>(5)
M_A_DQ<6>(5)
M_A_DQ<7>(5)
M_A_DQ<8>(5)
M_A_DQ<9>(5)
M_A_DQ<10>(5)
M_A_DQ<11>(5)
M_A_DQ<12>(5)
M_A_DQ<13>(5)
M_A_DQ<14>(5)
M_A_DQ<15>(5)
M_A_DQ<16>(5)
M_A_DQ<17>(5)

C C

B B

M_A_DIM0_ODT0(5)
M_A_DIM0_ODT1(5)

DRAMA_DRA MRST(5)

A A

M_A_DQ<18>(5)
M_A_DQ<19>(5)
M_A_DQ<20>(5)
M_A_DQ<21>(5)
M_A_DQ<22>(5)
M_A_DQ<23>(5)
M_A_DQ<24>(5)
M_A_DQ<25>(5)
M_A_DQ<26>(5)
M_A_DQ<27>(5)
M_A_DQ<28>(5)
M_A_DQ<29>(5)
M_A_DQ<30>(5)
M_A_DQ<31>(5)
M_A_DQ<32>(5)
M_A_DQ<33>(5)
M_A_DQ<34>(5)
M_A_DQ<35>(5)
M_A_DQ<36>(5)
M_A_DQ<37>(5)
M_A_DQ<38>(5)
M_A_DQ<39>(5)
M_A_DQ<40>(5)
M_A_DQ<41>(5)
M_A_DQ<42>(5)
M_A_DQ<43>(5)
M_A_DQ<44>(5)
M_A_DQ<45>(5)
M_A_DQ<46>(5)
M_A_DQ<47>(5)
M_A_DQ<48>(5)
M_A_DQ<49>(5)
M_A_DQ<50>(5)
M_A_DQ<51>(5)
M_A_DQ<52>(5)
M_A_DQ<53>(5)
M_A_DQ<54>(5)
M_A_DQ<55>(5)
M_A_DQ<56>(5)
M_A_DQ<57>(5)
M_A_DQ<58>(5)
M_A_DQ<59>(5)
M_A_DQ<60>(5)
M_A_DQ<61>(5)
M_A_DQ<62>(5)
M_A_DQ<63>(5)

M_A_DQS_DN< 0>(5)
M_A_DQS_DN< 1>(5)
M_A_DQS_DN< 2>(5)
M_A_DQS_DN< 3>(5)
M_A_DQS_DN< 4>(5)
M_A_DQS_DN< 5>(5)
M_A_DQS_DN< 6>(5)
M_A_DQS_DN< 7>(5)

M_A_DQS_DP<0>(5)
M_A_DQS_DP<1>(5)
M_A_DQS_DP<2>(5)
M_A_DQS_DP<3>(5)
M_A_DQS_DP<4>(5)
M_A_DQS_DP<5>(5)
M_A_DQS_DP<6>(5)
M_A_DQS_DP<7>(5)

5

VREF_CA
VREF_DQ

M_A_DQS_DN< 0>
M_A_DQS_DN< 1>
M_A_DQS_DN< 2>
M_A_DQS_DN< 3>
M_A_DQS_DN< 4>
M_A_DQS_DN< 5>
M_A_DQS_DN< 6>
M_A_DQS_DN< 7>

M_A_DQS_DP<0>
M_A_DQS_DP<1>
M_A_DQS_DP<2>
M_A_DQS_DP<3>
M_A_DQS_DP<4>
M_A_DQS_DP<5>
M_A_DQS_DP<6>
M_A_DQS_DP<7>

M_A_DIM0_ODT0
M_A_DIM0_ODT1

0D675V_S0

M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15

M_A_DQ<0>

M_A_DQ<1>
M_A_DQ<2>
M_A_DQ<3>

M_A_DQ<4>
M_A_DQ<5>
M_A_DQ<6>
M_A_DQ<7>
M_A_DQ<8>
M_A_DQ<9>
M_A_DQ<10>
M_A_DQ<11>
M_A_DQ<12>
M_A_DQ<13>
M_A_DQ<14>
M_A_DQ<15>
M_A_DQ<16>
M_A_DQ<17>
M_A_DQ<18>
M_A_DQ<19>
M_A_DQ<20>
M_A_DQ<21>
M_A_DQ<22>
M_A_DQ<23>
M_A_DQ<24>
M_A_DQ<25>
M_A_DQ<26>
M_A_DQ<27>
M_A_DQ<28>
M_A_DQ<29>
M_A_DQ<30>
M_A_DQ<31>

M_A_DQ<32>

M_A_DQ<33>

M_A_DQ<34>

M_A_DQ<35>

M_A_DQ<36>

M_A_DQ<37>

M_A_DQ<38>

M_A_DQ<39>
M_A_DQ<40>
M_A_DQ<41>
M_A_DQ<42>
M_A_DQ<43>
M_A_DQ<44>
M_A_DQ<45>
M_A_DQ<46>
M_A_DQ<47>
M_A_DQ<48>
M_A_DQ<49>
M_A_DQ<50>
M_A_DQ<51>
M_A_DQ<52>
M_A_DQ<53>
M_A_DQ<54>
M_A_DQ<55>
M_A_DQ<56>
M_A_DQ<57>
M_A_DQ<58>
M_A_DQ<59>
M_A_DQ<60>
M_A_DQ<61>
M_A_DQ<62>
M_A_DQ<63>

DIMM1

98

A0

97

A1

96

A2

95

A3

92

A4

91

A5

90

A6

86

A7

89

A8

85

A9

107

A10/AP

84

A11

83

A12

119

A13

80

A14

78

A15

79

A16/BA2

109

BA0

108

BA1

5

DQ0

7

DQ1

15

DQ2

17

DQ3

4

DQ4

6

DQ5

16

DQ6

18

DQ7

21

DQ8

23

DQ9

33

DQ10

35

DQ11

22

DQ12

24

DQ13

34

DQ14

36

DQ15

39

DQ16

41

DQ17

51

DQ18

53

DQ19

40

DQ20

42

DQ21

50

DQ22

52

DQ23

57

DQ24

59

DQ25

67

DQ26

69

DQ27

56

DQ28

58

DQ29

68

DQ30

70

DQ31

129

DQ32

131

DQ33

141

DQ34

143

DQ35

130

DQ36

132

DQ37

140

DQ38

142

DQ39

147

DQ40

149

DQ41

157

DQ42

159

DQ43

146

DQ44

148

DQ45

158

DQ46

160

DQ47

163

DQ48

165

DQ49

175

DQ50

177

DQ51

164

DQ52

166

DQ53

174

DQ54

176

DQ55

181

DQ56

183

DQ57

191

DQ58

193

DQ59

180

DQ60

182

DQ61

192

DQ62

194

DQ63

10

DQS0#

27

DQS1#

45

DQS2#

62

DQS3#

135

DQS4#

152

DQS5#

169

DQS6#

186

DQS7#

12

DQS0

29

DQS1

47

DQS2

64

DQS3

137

DQS4

154

DQS5

171

DQS6

188

DQS7

116

ODT0

120

ODT1

126

VREF_CA

1

VREF_DQ

30

RESET#

203

VTT1

204

VTT2

SKT_DDR 204P SMD

SKT_DDR 204P SMD

DDR3-204P- 215-GP-U

DDR3-204P- 215-GP-U

62.10024.M31

62.10024.M31

RAS#

CAS#

CS0#
CS1#

CKE0
CKE1

CK0#

CK1#

EVENT#

VDDSPD

NC#1
NC#2

NC#/TEST

VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8

VDD9
VDD10
VDD11
VDD12
VDD13
VDD14
VDD15
VDD16
VDD17
VDD18

NP1

NP1

NP2

NP2

110
113

WE#

115

114
121

73
74

101

CK0

103

102

CK1

104

DRAMA_DM_0

11

DM0

DRAMA_DM_1

28

DM1

DRAMA_DM_2

46

DM2

DRAMA_DM_3

63

DM3

DRAMA_DM_4

136

DM4

DRAMA_DM_5

153

DM5

DRAMA_DM_6

170

DM6

DRAMA_DM_7

187

DM7

200

SDA

202

SCL

SA0
SA1

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

TS#_DIMM0_1

198

199

SA2_DIM0

197

SA2_DIM1

201

77
122

1D35V_S3

125

75
76
81
82
87
88
93
94
99
100
105
106
111
112
117
118
123
124

2
3
8
9
13
14
19
20
25
26
31
32
37
38
43
44
48
49
54
55
60
61
65
66
71
72
127
128
133
134
138
139
144
145
150
151
155
156
161
162
167
168
172
173
178
179
184
185
189
190
195
196
205
206

4

DRAMA_DM_0 (5)
DRAMA_DM_1 (5)
DRAMA_DM_2 (5)
DRAMA_DM_3 (5)
DRAMA_DM_4 (5)
DRAMA_DM_5 (5)
DRAMA_DM_6 (5)
DRAMA_DM_7 (5)

PCU_SMB_DAT A (16)
PCU_SMB_CLK (16)

1D35V_S3

0D675V_S0

12

C1214

C1214

SC1U6D3V2KX-L-1-GP

SC1U6D3V2KX-L-1-GP

12

M_A_RAS# (5)
M_A_WE# (5)
M_A_CAS# (5)

M_A_DIM0_CS#0 (5)
M_A_DIM0_CS#1 (5)

M_A_DIM0_CKE0 (5)
M_A_DIM0_CKE1 (5)

M_A_DIM0_CLK_DDR 0 (5)
M_A_DIM0_CLK_DDR #0 (5)

M_A_DIM0_CLK_DDR 1 (5)
M_A_DIM0_CLK_DDR #1 (5)

Layout Note:
Place these Caps near
SO-DIMMA.

SODIMM A DECOUPLING

12

C1203

C1203

C1204

C1204

SC10U6D3V3MX-L-GP

SC10U6D3V3MX-L-GP

SC10U6D3V3MX-L-GP

SC10U6D3V3MX-L-GP

DY

DY

DY

DY

12

12

C1209

C1209

C1210

C1210

SC1U6D3V2KX-L-1-GP

SC1U6D3V2KX-L-1-GP

SC1U6D3V2KX-L-1-GP

SC1U6D3V2KX-L-1-GP

Place these caps
close to VTT1 and
VTT2.

12

12

C1215

C1215

C1216

C1216

SC1U6D3V2KX-L-1-GP

SC1U6D3V2KX-L-1-GP

SC1U6D3V2KX-L-1-GP

SC1U6D3V2KX-L-1-GP

3D3V_S0 3D3V _S0

R1209

R1209
10KR2J-3-GP

10KR2J-3-GP

DY

DY

1 2

SA2_DIM1 SA2_DIM0

12

R1211

3D3V_S0

12

C1205

C1205

12

C1202

C1202

SCD1U10V2KX-L1-GP

SCD1U10V2KX-L1-GP

12

12

C1206

C1206

C1207

C1207

SC10U6D3V3MX-L-GP

SC10U6D3V3MX-L-GP

SC10U6D3V3MX-L-GP

SC10U6D3V3MX-L-GP

12

C1211

C1211

SC10U6D3V3MX-L-GP

SC10U6D3V3MX-L-GP

DY

DY

12

check list recommend stuff

C1212

C1212

SC1U6D3V2KX-L-1-GP

SC1U6D3V2KX-L-1-GP

SC1U6D3V2KX-L-1-GP

SC1U6D3V2KX-L-1-GP

0.1uF * 8 & 330uF * 1

R1211
0R0402-PAD

0R0402-PAD

12

12

C1221

C1221

C1222

C1222

SC10U10V3MX-GP

SC10U10V3MX-GP

SC10U10V3MX-GP

SC10U10V3MX-GP

DY

DY

DY

DY

check list recommend stuff

12

C1217

C1217

12

12

C1220

C1220

C1219

C1219

SC1U6D3V2KX-L-1-GP

SC1U6D3V2KX-L-1-GP

SC10U10V3MX-GP

SC10U10V3MX-GP

SC10U10V3MX-GP

SC10U10V3MX-GP

DY

DY

DY

DY

Note:
If SA0 DIM0 = 0, SA1_DIM0 = 0
SO-DIMMA SPD Address is 0xA0
SO-DIMMA TS Address is 0x30

If SA0 DIM0 = 1, SA1_DIM0 = 0
SO-DIMMA SPD Address is 0xA2
SO-DIMMA TS Address is 0x32

DY

DY

R1208

R1208
10KR2J-3-GP

10KR2J-3-GP

1 2

12

R1210

R1210
0R0402-PAD

0R0402-PAD

A00

Thermal EVENT

TS#_DIMM0_1

1 2

DY

DY

R1201

R1201
10KR2J-3-GP

10KR2J-3-GP

3D3V_S0

For Intel Recommend Close to DIMM(Bay Trail)

1D35V_S3

12

R1202

R1202
4K7R2F-GP

12

4K7R2F-GP

R1204

R1204
4K7R2F-GP

4K7R2F-GP

R1203

R1203

VREF_DQ_R 1203VREF_DQ

1 2

0R0402-PAD

0R0402-PAD

C1213

C1213

SCD1U10V2KX-L1-GP

SCD1U10V2KX-L1-GP

12

12

C1223

C1223

SC10U10V3MX-GP

SC10U10V3MX-GP

For Intel Recommend Close to DIMM(Bay Trail)

1D35V_S3

12

R1205

R1205
4K7R2F-GP

R1207

R1207

VREF_CA_R1 207VREF_ CA

1 2

0R0402-PAD

0R0402-PAD

12

C1201

C1201

SCD1U10V2KX-L1-GP

SCD1U10V2KX-L1-GP

3

2

4K7R2F-GP

12

R1206

R1206
4K7R2F-GP

4K7R2F-GP

Wistron Confidential document, Anyone can not
Duplicate, Modify, Forward or any other purpose
application without get Wistron permission

<Core Desig n>

<Core Desig n>

<Core Desig n>

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin T ai Wu Rd., H sichih,

21F, 88, Sec.1, Hsin T ai Wu Rd., H sichih,

21F, 88, Sec.1, Hsin T ai Wu Rd., H sichih,
Taipei Hsie n 221, Taiwan, R.O.C.

Taipei Hsie n 221, Taiwan, R.O.C.

Title

Title

Title

DDR3-SODIMM1

DDR3-SODIMM1

DDR3-SODIMM1

Size Document Num ber Rev

Size Document Num ber Rev

Size Document Num ber Rev
A2

A2

A2

Tuesday, April 01, 2014

Tuesday, April 01, 2014

Tuesday, April 01, 2014
Date: Sheet of

Date: Sheet of

Date: Sheet of

Taipei Hsie n 221, Taiwan, R.O.C.

Redwood 11.6"

Redwood 11.6"

Redwood 11.6"

1

12 102

12 102

12 102

A00

A00

A00

www.vinafix.vn

5

D D

C C

4

3

2

1

Blanking

B B

<Core Design>

<Core Design>

<Core Design>

Wistron Corporation

Wistron Corporation

A A

Title

Title

Title

Reserved

Reserved

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev
A4

A4

A4

Date: Sheet of

Date: Sheet of

5

4

www.vinafix.vn

3

Date: Sheet of

Reserved

Tuesday, April 01, 2014

Tuesday, April 01, 2014

Tuesday, April 01, 2014

2

Redwood 11.6"

Redwood 11.6"

Redwood 11.6"

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

A00

A00

13 102

13 102

13 102

1

A00

5

D D

C C

4

3

2

1

Blanking

B B

Wistron Confidential document, Anyone can not
Duplicate, Modify, Forward or any other purpose

<Core Design>

<Core Design>

<Core Design>

A A

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev
A4

A4

A4

Date: Sheet of

Date: Sheet of

5

4

www.vinafix.vn

3

Date: Sheet of

application without get Wistron permission

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

Reserved

Reserved

Redwood 11.6"

Redwood 11.6"

Tuesday, April 01, 2014

Tuesday, April 01, 2014

Tuesday, April 01, 2014

2

Redwood 11.6"

14 102

14 102

14 102

1

A00

A00

A00

5

SSID = STRAP

4

STRAP RESISTORS SHOULD BE PLACED CLOSE TO SOC
SHOULD BE PLACED OUTSIDE KOZ AREA

3

2

1

EDS_Rev1p5 define the strap removed for MDSI P.21

Description

D D

BIOS Boot Selection

GPIO

12

R1509

R1509

10KR2F-2 -GP

10KR2F-2 -GP

Schematic

C C

High

Low

DY

DY

12

R1510

R1510

10KR2F-2 -GP

10KR2F-2 -GP

SPI

LPC

Security Flash
Descriptors

DDI0 Detect DDI1 Detect DDI1 Detect Top swap

GPIO_S0_SC[065] DDI0_DDCDATA

12

R1511

R1511

10KR2F-2 -GP

10KR2F-2 -GP

12

R1512

R1512

4K7R2F-G P

4K7R2F-G P

DY

DY

Normal Operation

Override

12

DY

DY

DDI0 detected DDI1 detected

DDI0 not detected

R1508

R1508

10KR2F-2 -GP

10KR2F-2 -GP

PCH_HDM I_DATA (8,54 )

DDI1_DDCDATA MDSI_DDCDATA GPIO_S0_SC[063]

12

R1502

R1502

2K2R2J-2 -GP

2K2R2J-2 -GP

12

R1504

R1504

10KR2F-2 -GP

10KR2F-2 -GP

DY

DY

DDI1 not detected

1D8V_S0 1D8V_S01D8V_S01D8V_S0 1D8V_S0

12

R1501

R1501

10KR2F-2 -GP

10KR2F-2 -GP

DY

DY

12

R1503

R1503

10KR2F-2 -GP

10KR2F-2 -GP

GPIO_S0_N C13 (8) GPIO_S0_S C_56 (16)DDI1_GEN_ R_DAT (8)LPE_I2S2_ FRM (19 ) LPE_I2S2_ DATAOUT (19,24)

DDI1 detected

DDI1 not detected

GPIO_S0_SC [56]

12

R1505

R1505

10KR2F-2 -GP

10KR2F-2 -GP

DY

DY

12

R1507

R1507

10KR2F-2 -GP

10KR2F-2 -GP

DY

DY

B B

Wistron Confidential document, Anyone can not
Duplicate, Modify, Forward or any other purpose

A A

5

4

www.vinafix.vn

3

2

application without get Wistron permission

<Core Design>

<Core Design>

<Core Design>

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Title

Title

Size Document N umber Rev

Size Document N umber Rev

Size Document N umber Rev
A3

A3

A3

Tuesday, April 01, 2014

Tuesday, April 01, 2014

Tuesday, April 01, 2014

Date: Sheet of

Date: Sheet of

Date: Sheet of

Redwood 11.6"

Redwood 11.6"

Redwood 11.6"

Taipei Hsien 221, Taiwan, R.O.C.

CPU(STRAP)

CPU(STRAP)

CPU(STRAP)

1

15 102

15 102

15 102

A00

A00

A00

5

4

3

2

1

SSID = PCH

CPU1F

CPU1F

G2

GPIO_S5_31

M3

GPIO_S5_32

L1

GPIO_S5_33

K2

GPIO_S5_34

K3

GPIO_S5_35

M2

GPIO_S5_36

N3

GPIO_S5_37

P2

GPIO_S5_38

L3

J3
P3
H3

B12

M16
K16

J14

G14

K12

J12

K10
H10

D10
F10

C20
B20

D6
C7

M13

B4
B5

E2
D2

A7

BF18
BH16

BJ17

BJ13
BG14
BG17
BG15
BH14
BG16
BG13

BG12
BH10
BG11

PCU_SMB_DAT A_FFS(68)

PCU_SMB_CLK_ FFS(68)

GPIO_S5_39

GPIO_S5_40
GPIO_S5_41
GPIO_S5_42
GPIO_S5_43

USB_DP0
USB_DN0

USB_DP1
USB_DN1

USB_DP2
USB_DN2

USB_DP3
USB_DN3

ICLK_USB_TERMN_D10
ICLK_USB_TERMN

USB_OC_0
USB_OC_1

USB_RCOMPO
USB_RCOMPI

USB_PLL_MON

USB_HSIC0_DATA
USB_HSIC0_STROBE

USB_HSIC1_DATA
USB_HSIC1_STROBE

USB_HSIC_RCOMP

LPC_RCOMP
ILB_LPC_AD_0
ILB_LPC_AD_1
ILB_LPC_AD_2
ILB_LPC_AD_3
ILB_LPC_FRAME
ILB_LPC_CLK_0
ILB_LPC_CLK_1
ILB_LPC_CLKRUN
ILB_LPC_SERIRQ

PCU_SMB_DATA
PCU_SMB_CLK
PCU_SMB_ALERT

BAY-TRAIL-GP

BAY-TRAIL-GP

4

D D

USB 3.0

USB 2.0

Camera

USB HUB

1D8V_S5

RN1607

RN1607

1
2 3

1D8V_S0

2 3
1

C C

1D8V_S0

CLK_PCI_LPC( 65)

CLK_PCI_KBC(24)

B B

Connected to package ground.

A A

USB_OC#1

4

USB_OC#0

SRN10KJ-5-G P

SRN10KJ-5-G P

RN1601

RN1601

SMB_DATA
SMB_CLK

4

SRN2K2J-5-G P

SRN2K2J-5-G P

PCU_SMB_ALER T#

1 2

DY

DY

R1612

R1612
2K2R2J-2-GP

2K2R2J-2-GP

LPC_AD0(24,65)
LPC_AD1(24,65)
LPC_AD2(24,65)
LPC_AD3(24,65)

LPC_FRAME#(24,65)

X01

Avoid routing next to

clock/high speed signals.

1 2

R1609 12R2J-GP

R1609 12R2J-GP

1 2

R1610 12R2J-GPR1610 12R2J-GP

5

LPC

LPC

R1604 45D 3R2F-L-GPR1604 45D3R2F -L-GP

R1605 0R2 J-2-GP

R1605 0R2 J-2-GP

R1606 45D 3R2F-L-GPR1606 45D3R2F -L-GP

R1607 49D 9R2F-L1-GPR1607 49D9R2F-L1-G P

USB_PP0(34)
USB_PN0(34)

USB_PP1(33)
USB_PN1(33)

USB_PP2(52)
USB_PN2(52)

USB_PP3(35)
USB_PN3(35)

Close to CPU1

A00

R1608 0R 0402-PADR1608 0R 0402-PAD

1 2

R1611 0R 0402-PADR1611 0R 0402-PAD

1 2

R1614 0R 0402-PADR1614 0R 0402-PAD

1 2

R1615 0R 0402-PADR1615 0R 0402-PAD

1 2

R1616 0R 0402-PADR1616 0R 0402-PAD

1 2

ICLK_USB_TERMN _0

R1601

R1601

12

1KR2F-3-GP

1KR2F-3-GP

ICLK_USB_TERMN _1

R1603

R1603

12

1KR2F-3-GP

1KR2F-3-GP

USB_RCOMP

1 2

USB_PLL_MON

1 2

DY

DY

USB_HSIC_RC OMP

1 2

RCOMP_LPC_H VT

1 2

PM_CLKRUN #_EC(24)

INT_SERIRQ_CPU(24)

TP1603

TP1603

TPAD14-OP-G P

TPAD14-OP-G P

USB_OC#0( 63)
USB_OC#1( 33,34)

TP1604

TP1604

TPAD14-OP-G P

TPAD14-OP-G P

TP1605

TP1605

TPAD14-OP-G P

TPAD14-OP-G P

TP1606

TP1606

TPAD14-OP-G P

TPAD14-OP-G P

TP1607

TP1607

TPAD14-OP-G P

TPAD14-OP-G P

SMB_DATA
SMB_CLK
PCU_SMB_ALER T#

1

ICLK_USB_TERMN _0
ICLK_USB_TERMN _1

USB_RCOMP

USB_PLL_MON

USB_HSIC_0_DAT A

1

USB_HSIC_0_STR OBE

1

USB_HSIC_1_DAT A

1

USB_HSIC_1_STR OBE

1

USB_HSIC_RC OMP

RCOMP_LPC_H VT
LPC_AD0_R
LPC_AD1_R
LPC_AD2_R
LPC_AD3_R
LPC_FRAME#_R
CLK_PCI_LPC_R
CLK_PCI_KBC_R

BAY TRAIL-M/D SOC

BAY TRAIL-M/D SOC

3.3V/1.8V

1.8V

1.8V

A00

R1618 0R 0402-PADR1618 0R 0402-PAD

1 2

R1617 0R 0402-PADR1617 0R 0402-PAD

1 2

1.8V

PCU_SMB_CLK(12)

PCU_SMB_DAT A(12)

6 OF 13

6 OF 13

RESERVED_M9

RESERVED_P7
RESERVED_P6

RESERVED_M7

USB3_REXT0

RESERVED_M4
RESERVED_M6

USB3_RXP0
USB3_RXN0

USB3_TXP0

USB3_TXN0

RESERVED_H8
RESERVED_H7

RESERVED_H5
RESERVED_H4

ILB_8254_SPKR

SIO_I2C0_DATA

SIO_I2C0_CLK

SIO_I2C1_DATA

SIO_I2C1_CLK

SIO_I2C2_DATA

SIO_I2C2_CLK

SIO_I2C3_DATA

SIO_I2C3_CLK

SIO_I2C4_DATA

SIO_I2C4_CLK

SIO_I2C5_DATA

SIO_I2C5_CLK

SIO_I2C6_DATA

SIO_I2C6_CLK

M10

Make sure the signal routing is as short as possible

M9

and isolated from high speed data signal.
Parasitic resistance for the overall routing should be less than 100

P7
P6

M7

USB3_P1_REXT

M12

P10
P12

M4
M6

D4
E3

K6
K7

H8
H7

H5
H4

ALS_INT_R

BD12

GPIO_S0_SC_56

BC12

UART1_TX_G PIO57

BD14

FFS_INT2_C

BC14
BF14

DBC_EN_C

BD16

UART1_RX_G PIO61

BC16

BH12

SIO_I2C0_DATA

BH22

SIO_I2C0_CLK

BG23

BG24
BH24

BG25
BJ25

BG26
BH26

SIO_I2C4_DATA

BF27

SIO_I2C4_CLK

BG27

BH28
BG28

BJ29
BG29

SENSOR_HU B_RST#_R

BH30

CAMERA_DET #_C

BG30

RESERVED_M10

RESERVED_P10
RESERVED_P12

GPIO_S0_SC_55
GPIO_S0_SC_56
GPIO_S0_SC_57
GPIO_S0_SC_58
GPIO_S0_SC_59
GPIO_S0_SC_60
GPIO_S0_SC_61

GPIO_S0_SC_92
GPIO_S0_SC_93

PCU_SMB_DAT A

PCU_SMB_CLK

Level shift

3D3V_S0 1D8V_S0

12

R1621

R1621

2K2R2J-2-GP

2K2R2J-2-GP

D S

DMN5L06K-7-G P

DMN5L06K-7-G P

84.05067.031

84.05067.031

3D3V_S0 1D8V_S0

12

R1624

R1624

2K2R2J-2-GP

2K2R2J-2-GP

D S

DMN5L06K-7-G P

DMN5L06K-7-G P

84.05067.031

84.05067.031

VGS(th) = 1V

3

Q1602

Q1602

Q1603

Q1603

G

G

1 2

R1602

R1602
1K24R2F-GP

1K24R2F-GP

USB3_PRX_CT X_P0 (34)
USB3_PRX_CT X_N0 (34)

USB3_PTX_CR X_P0 (34)
USB3_PTX_CR X_N0 (34)

GPIO_S0_SC_56 (15)

HDA_SPKR ( 27)

SMB_CLK

SMB_DATA

X01

check module that if open drain

R1625

R1625

2K2R2J-2-GP

2K2R2J-2-GP

TP_I2C_CLK(62)

R1629

R1629

2K2R2J-2-GP

2K2R2J-2-GP

TP_I2C_DATA(62)

Ω.

Level shift

1D8V_S0 3D3V_S03D3V_S0 1D8V_S0

1D8V_S0

Q1601

Q1601

12

G

X02

12

R1619

R1619

2K2R2J-2-GP

2K2R2J-2-GP

D S

DY

ALS_INT#(52,67) SENSOR_HU B_RST#(67)

DY

DMN5L06K-7-G P

DMN5L06K-7-G P

84.05067.031

84.05067.031

Level shift

X01

100KR2J-1-GP

100KR2J-1-GP

X01

INT2_SELECT(68)

SIO_I2C0_CLK
SIO_I2C0_DATA

TP_VDD 1D8V_S0

12

I2C

I2C

TP_VDD 1D8V_S0

12

I2C

I2C

3D3V_S0 1D8V_S0

R1626

R1626

DY

DY

1 2

1
2 3

RN1603

RN1603
SRN2K2J-5-G P

SRN2K2J-5-G P

G

I2C

I2C

D S

Q1605

Q1605

DMN5L06K-7-G P

DMN5L06K-7-G P

84.05067.031

84.05067.031

G

I2C

I2C

D S

Q1606

Q1606

DMN5L06K-7-G P

DMN5L06K-7-G P

84.05067.031

84.05067.031

D S

DMN5L06K-7-G P

DMN5L06K-7-G P

84.05067.031

84.05067.031

I2C

I2C

2

G

Q1609

Q1609

TP_VDD_1D8V

4

X01

SIO_I2C0_CLK

SIO_I2C0_DATA

X01

1D8V_S0

12

R1631

R1631
2K2R2J-2-GP

2K2R2J-2-GP

FFS_INT2_C

R1623

R1623
2K2R2J-2-GP

2K2R2J-2-GP

ALS_INT_R

X02

SIO_I2C4_DATA
SIO_I2C4_CLK

12

R1622

R1622

2K2R2J-2-GP

2K2R2J-2-GP

DY

DY

R1627

R1627

2K2R2J-2-GP

2K2R2J-2-GP

DBC_EN(52)

R1628

R1628

2K2R2J-2-GP

2K2R2J-2-GP

CAMERA_DET #(52)

1D8V_S0

1

4

2 3

DY

DY

RN1605

RN1605
SRN2K2J-5-G P

SRN2K2J-5-G P

5V_S5

UART1_TX_G PIO57
UART1_RX_G PIO61

ACES-CON 4-37-GP

ACES-CON 4-37-GP

20.F1897.004

20.F1897.004

<Core Desig n>

<Core Desig n>

<Core Desig n>

Title

Title

Title

CPU (USB/LPC/GPIO)

CPU (USB/LPC/GPIO)

CPU (USB/LPC/GPIO)

Size Document Num ber Rev

Size Document Num ber Rev

Size Document Num ber Rev
A2

A2

A2

Tuesday, April 01, 2014

Tuesday, April 01, 2014

Tuesday, April 01, 2014
Date: Sheet of

Date: Sheet of

Date: Sheet of

G

D S

DMN5L06K-7-G P

DMN5L06K-7-G P

84.05067.031

84.05067.031

3D3V_S0 1D8V_S0

12

3D3V_S0 1D8V_S0

12

DB2

DB2

1

2
3
4

Redwood 11.6"

Redwood 11.6"

Redwood 11.6"

SENSOR_HU B_RST#_R

DY

DY

Q1604

Q1604

1D8V_S0

12

G

D S

Q1610

Q1610

DMN5L06K-7-G P

DMN5L06K-7-G P

84.05067.031

84.05067.031

1D8V_S0

12

G

Q1611

Q1611

CAMERA_DET #_C

D S

DMN5L06K-7-G P

DMN5L06K-7-G P

84.05067.031

84.05067.031

56

DY

DY

X01

Wistron Confidential document, Anyone can not
Duplicate, Modify, Forward or any other purpose
application without get Wistron permission

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin T ai Wu Rd., H sichih,

21F, 88, Sec.1, Hsin T ai Wu Rd., H sichih,

21F, 88, Sec.1, Hsin T ai Wu Rd., H sichih,
Taipei Hsie n 221, Taiwan, R.O.C.

Taipei Hsie n 221, Taiwan, R.O.C.

Taipei Hsie n 221, Taiwan, R.O.C.

16 102

16 102

1

16 102

R1630

R1630
2K2R2J-2-GP

2K2R2J-2-GP

DBC_EN_C

R1632

R1632
2K2R2J-2-GP

2K2R2J-2-GP

A00

A00

A00

www.vinafix.vn

5

4

3

2

1

SSID = PCH

D D

C C

Blanking

B B

Wistron Confidential document, Anyone can not
Duplicate, Modify, Forward or any other purpose
application without get Wistron permission

<Core Design>

<Core Design>

<Core Design>

Wistron Corporation

Wistron Corporation

A A

Title

Title

Title

CPU (DMI/FDI/PM)

CPU (DMI/FDI/PM)

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev
A4

A4

A4

Date: Sheet of

Date: Sheet of

5

4

www.vinafix.vn

3

Date: Sheet of

CPU (DMI/FDI/PM)

Redwood 11.6"

Redwood 11.6"

Tuesday, April 01, 2014

Tuesday, April 01, 2014

Tuesday, April 01, 2014

2

Redwood 11.6"

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

A00

A00

17 102

17 102

17 102

1

A00

5

SSID = PCH

C1801

C1801

SC12P50V2JN-3G P

SC12P50V2JN-3G P

12

D D

C C

RTC_AUX_S5

C1802

C1802

12

1 2

1 2

R1804

R1804
20KR2J-L2-GP

20KR2J-L2-GP

1 2
1 2

R1805

R1805

20KR2J-L2-GP

20KR2J-L2-GP

SC1U6D3V3KX- 2GP

SC1U6D3V3KX- 2GP

SC12P50V2JN-3G P

SC12P50V2JN-3G P

R1802

R1802
4K02R2F-GP

4K02R2F-GP

R1803

R1803
47D5R2F-1-G P

47D5R2F-1-G P

C1805

C1805

ICLK_ICOMP

ICLK_RCOMP

12

12

C1803

C1803

XTAL-25MHZ- 181-GP

XTAL-25MHZ- 181-GP

4 1

1MR2J-L3-GP

1MR2J-L3-GP

23

X1801

X1801

82.30020.G71

82.30020.G71

21

SRTC_RST #

RTC_RST#

G1801

G1801
GAP-OPEN

GAP-OPEN

WLAN

SC1U6D3V3KX-2GP

SC1U6D3V3KX-2GP

X01

RTC Reset

PCH_SPI_CS0#_FLA SH(25)

PCH_SPI_SO(25)

XDP_H_TCK

R1806

R1806

1 2

51R2J-L1-GP

51R2J-L1-GP

XDP_H_TRST _N

R1808

R1808

1 2

51R2J-L1-GP

51R2J-L1-GP

XDP_H_TMS

R1813

R1813

1D8V_S5

1D8V_S5

1D8V_S5

B B

1D8V_S5

If no PCI Express ports is implemented on the platform, pull-up to V1P8 Via a 10-kΩ resistor.

1D8V_S5

1D8V_S5

A A

1 2

51R2J-L1-GP

51R2J-L1-GP

R1814

R1814

1 2

51R2J-L1-GP

51R2J-L1-GP

R1815

R1815

1 2

51R2J-L1-GP

51R2J-L1-GP

PMC_WAKE _PCIE_1#

12

R1833 10KR2J-3-GPR1833 10KR2J-3-GP

12

R1835

R1835
10KR2J-3-GP

10KR2J-3-GP

12

R1837

R1837
10KR2J-3-GP

10KR2J-3-GP

PLT_RST#_CPU

VR_SVID_ALERT#

COREPW ROK

XDP_H_TDI

XDP_H_TDO

EC_SMI#

EC_SWI#

PCH_SPI_SI_FLASH(25)
PCH_SPI_CLK_FLA SH(25)

EC1808

EC1808

1 2

DY

DY

SCD1U25V2KX- GP

SCD1U25V2KX- GP

EC1809

EC1809

1 2

DY

DY

SCD1U25V2KX- GP

SCD1U25V2KX- GP

EC1810

EC1810

1 2

DY

DY

SCD1U25V2KX- GP

SCD1U25V2KX- GP

reserve the 0402 0.1u caps on reset for EMI

5

XTAL25_IN

R1801

R1801

1 2

XTAL25_OUT

CLK_PCIE_WLA N_N0(63)

CLK_PCIE_WLA N_P0(63)

TP1806 T PAD14-OP-GPTP1806 TPAD14-OP-GP
TP1807 T PAD14-OP-GPTP1807 TPAD14-OP-GP

TP1808 T PAD14-OP-GPTP1808 TPAD14-OP-GP
TP1809 T PAD14-OP-GPTP1809 TPAD14-OP-GP

TP1810 T PAD14-OP-GPTP1810 TPAD14-OP-GP
TP1811 T PAD14-OP-GPTP1811 TPAD14-OP-GP

XDP_H_TCK(65)
XDP_H_TRST _N(65)
XDP_H_TMS(65)

XDP_H_TDI(65)
XDP_H_TDO(65)
TAP_PRDY#(65)

1 2

R1809 22R2F-1-G PR1809 22R2F-1-GP

1 2

R1810 22R2F-1-G PR1810 22R2F-1-GP

1 2

R1811 22R2F-1-G PR1811 22R2F-1-GP

10KR2J-3-GP

10KR2J-3-GP

TAP_PREQ#(65)

EC_SWI#(24)

EC_SMI#(24)

1 2

R1812

R1812
49D9R2F-L1-G P

49D9R2F-L1-G P

4

3D3V_AUX_S5

1 2

DY

DY

R1822

R1822
100KR2J-1-GP

1 2

RSMRST#_KBC _G

AH12
AH10

AD9

AD14
AD13

AD10
AD12

AF6
AF4

AF9
AF7

AK4
AK6

AM4
AM6

AM10

AM9

BH7
BH5
BH4
BH8
BH6

BJ9
C12

D14

G12

F14
F12

G16

D18
F16

AT34

C23
C21
B22
A21
C22

B18
B16
C18
A17
C17
C16
B14
C15

C13
A13
C19

N26

4

100KR2J-1-GP

CPU1E

CPU1E

ICLK_OSCIN
ICLK_OSCOUT

RESERVED_AD9

ICLK_ICOMP
ICLK_RCOMP

RESERVED_AD10
RESERVED_AD12

PCIE_CLKN_0
PCIE_CLKP_0

PCIE_CLKN_1
PCIE_CLKP_1

PCIE_CLKN_2
PCIE_CLKP_2

PCIE_CLKN_3
PCIE_CLKP_3

RESERVED_AM10
RESERVED_AM9

PMC_PLT_CLK_0
PMC_PLT_CLK_1
PMC_PLT_CLK_2
PMC_PLT_CLK_3
PMC_PLT_CLK_4
PMC_PLT_CLK_5
ILB_RTC_RST

TAP_TCK
TAP_TRST
TAP_TMS
TAP_TDI
TAP_TDO
TAP_PRDY
TAP_PREQ
RESERVED

PCU_SPI_CS_0
PCU_SPI_CS_1
PCU_SPI_MISO
PCU_SPI_MOSI
PCU_SPI_CLK

GPIO_S5_0
GPIO_S5_1
GPIO_S5_2
GPIO_S5_3
GPIO_S5_4
GPIO_S5_5
GPIO_S5_6
GPIO_S5_7

GPIO_S5_8
GPIO_S5_9
GPIO_S5_10

GPIO_RCOMP

BAY-TRAIL-GP

BAY-TRAIL-GP

1 2

R1832

R1832
0R0402-PAD

0R0402-PAD

R1821

R1821

XTAL25_IN
XTAL25_OUT

ICLK_ICOMP
ICLK_RCOMP

PCIE_CLKN1

1

PCIE_CLKP1

1

PCIE_CLKN2

1

PCIE_CLKP2

1

PCIE_CLKN3

1

PCIE_CLKP3

1

RTC_RST#

XDP_H_TCK
XDP_H_TRST _N
XDP_H_TMS
XDP_H_TDI
XDP_H_TDO
TAP_PRDY#
TAP_PREQ#

PCH_SPI_CS0#

PCH_SPI_SI
PCH_SPI_CLK

PMC_WAKE _PCIE_1#

EC_SMI#

GPIO_RCOMP18

PM_SLP_S4#_CPU PM_SLP_S4#_CPU_G

Q1802

Q1802

5

6

DMN601DW K-7-1-GP

DMN601DW K-7-1-GP

75.00601.07C

75.00601.07C

1.0V

3.3V

1.8V

1.8V

2K2R2J-2-GP

2K2R2J-2-GP

1D8V_S5

R1845

R1845

DY

DY

34

2

1

PM_RSMRST#

BAY TRAIL-M/D SOC

BAY TRAIL-M/D SOC

12

G

PM_SLP_S3#(24,36,37,46,49)

A00

R1823

R1823
0R0402-PAD

0R0402-PAD

1 2

R1825

R1825

10KR2J-3-GP

10KR2J-3-GP

1 2

3D3V_AUX_S5

1 2

DS

12

C1808

C1808

SC22P50V2GN-GP

SC22P50V2GN-GP

DY

DY

1.8V

PMC_SUSPWRDNACK

PMC_SUSCLK0_G24

PMC_WAKE_PCIE_0

3.3V

PMC_CORE_PWROK

3.3V

1.0V_S

R1830

R1830
10KR2J-3-GP

10KR2J-3-GP

PM_SLP_S4#_CPU_D

Q1808

Q1808
DMN5L06K-7-G P

DMN5L06K-7-G P

PM_SLP_S3#

RSMRST#_KBC ( 24,65)

A00

5 OF 13

5 OF 13

SIO_UART1_RXD
SIO_UART1_TXD
SIO_UART1_RTS
SIO_UART1_CTS

SIO_UART2_RXD
SIO_UART2_TXD
SIO_UART2_RTS
SIO_UART2_CTS

PMC_SLP_S0IX

PMC_SLP_S4
PMC_SLP_S3

GPIO_S514_J20

PMC_ACPRESENT

PMC_BATLOW
PMC_PWRBTN

PMC_RSTBTN

PMC_PLTRST

GPIO_S517_J24

PMC_SUS_STAT

ILB_RTC_TEST

PMC_RSMRST

ILB_RTC_X1
ILB_RTC_X2

ILB_RTC_EXTPAD

SVID_ALERT

SVID_DATA

SVID_CLK

SIO_PWM_0
SIO_PWM_1

GPIO_S5_22
GPIO_S5_23
GPIO_S5_24
GPIO_S5_25
GPIO_S5_26
GPIO_S5_27
GPIO_S5_28
GPIO_S5_29
GPIO_S5_30

SIO_SPI_CS
SIO_SPI_MISO
SIO_SPI_MOSI

SIO_SPI_CLK

3D3V_S5

R1856

R1856

10KR2J-3-GP

10KR2J-3-GP

1 2

R1828

R1828
0R0402-PAD

0R0402-PAD

AU34
AV34
BA34
AY34

BF34
BD34
BD32
BF32

D26
G24
F18
F22
D22
J20
D20
F26
K26
J26
BG9
F20
J24
G18

C11

B10
B7

C9
A9
B8

B24
A25
C25

AU32
AT32

K24
N24
M20
J18
M18
K18
K20
M22
M24

AV32
BA28
AY28
AY30

1 2

3

1D8V_S5_PG (24,51)

X01

UART1_RX
UART1_TX
UART1_RTS
UART1_CTS

SUS_PWR DN_ACK_CPU

PMC_SLP_S0IX
PM_SLP_S4#_CPU
PM_SLP_S3#_CPU

PCIE0_WAKE#_C PU
PMC_BATLOW #

PLT_RST#_CPU

PM_SUS_STAT#_C PU

SRTC_RST #

PM_RSMRST#
COREPW ROK

RTC_X1
RTC_X2
BVCCRTC _EXTPAD

SVID_ALERT#
SVID_DATA
SVID_CLK

R1818 0R0402-PADR1818 0R0402-PAD

DBG0
DBG1
DBG2
DBG3

Q1810

Q1810
2N7002KDW -GP

2N7002KDW -GP

84.2N702.A3F

84.2N702.A3F

2nd = 75.00601.07C

2nd = 75.00601.07C

3rd = 84.2N702.F3F

3rd = 84.2N702.F3F

1

2

3 4

3

3V_5V_POK (45,50)

TP1802 TPA D14-OP-GPTP1802 T PAD14-OP-GP

1

TP1803 TPA D14-OP-GPTP1803 T PAD14-OP-GP

1

TP1804 TPA D14-OP-GPTP1804 T PAD14-OP-GP

1

TP1805 TPA D14-OP-GPTP1805 T PAD14-OP-GP

1

PCH_SUSCL K (24)

TP1801

TP1801

1

TPAD14-OP-G P

TPAD14-OP-G P

AC_PRESENT _CPU ( 24)

PM_PWRBT N#_CPU ( 24)
PMC_RSTBTN # (65)
PLT_RST#_CPU (65)

SRTC_RST # (65)

COREPW ROK (36,65)

1 2

C1804

C1804
SCD1U10V2KX- L-GP

SCD1U10V2KX- L-GP

R1816 20R 2F-GPR1816 20R2F-GP

1 2

R1817 16D 9R2F-1-GPR1817 16D9R2F -1-GP

1 2
1 2

DBG0 (65)
DBG1 (65)
DBG2 (65)
DBG3 (65)

Close to SOC

R1824

R1824
69D8R2F-GP

VR_SVID_ALERT#

69D8R2F-GP

12

does not have 73.2 Ω ±1%

3D3V_S5

R1829

R1829
10KR2J-3-GP

10KR2J-3-GP

1 2

PM_SLP_S4#

6

5

R1855

R1855

10KR2J-3-GP

10KR2J-3-GP

PM_SLP_S3#_CPU_D

Q1816

Q1816

DMN5L06K-7-G P

DMN5L06K-7-G P

3D3V_AUX_S5

1 2

DS

PCIE0_WAKE#_C PU

PLT_RST#_CPU PLT_RST#_CPU _G

1 2

R1827

R1827
0R0402-PAD

0R0402-PAD

RTC_X1

1D8V_S5

12

R1852

R1852
2K2R2J-2-GP

2K2R2J-2-GP

DY

DY

PM_SLP_S3#_CPU_G

RTC_X2

C1806

C1806

AC_PRESENT _CPU

PM_PWRBT N#_CPU

1 2

R1836

R1836
0R0402-PAD

0R0402-PAD

VR_SVID_ALERT# (46)

H_CPU_SVIDD AT ( 46)

H_CPU_SVIDC LK (46)

1D0V_S0

PM_SLP_S4# (24,36,49)

G

PM_SLP_S3#_CPU

SC5P50V2CN-2GP

SC5P50V2CN-2GP

1D8V_S5

12

2

R1840

R1840
10KR2J-3-GP

10KR2J-3-GP

1 2

1D8V_S5

R1842

R1842

2K2R2J-2-GP

2K2R2J-2-GP

DY

DY

X1802

X1802

XTAL-32D768KH Z-6-GP

XTAL-32D768KH Z-6-GP

2nd = 82.30001.661

2nd = 82.30001.661

4 1

R1853

R1853
2K2R2J-2-GP

2K2R2J-2-GP

1 2

10KR2J-3-GP

10KR2J-3-GP
R1854

R1854

1 2

2

PMC_BATLOW #

12

R1807

R1807

10MR2J-L-GP

10MR2J-L-GP

23

1

Level shift

1D8V_S5

12

R1839

R1839

20KR2J-L3-GP

20KR2J-L3-GP

3D3V_S5

R1843

R1843
10KR2J-3-GP

10KR2J-3-GP

1 2

PLT_RST#_D

DS

Q1812

Q1812

G

DMN5L06K-7-G P

DMN5L06K-7-G P

84.05067.031

84.05067.031

12

12

C1807

C1807

SC5P50V2CN-2GP

SC5P50V2CN-2GP

PM_SUS_STAT#_C PU

1D8V_S5

X01

R1850

R1850

10KR2J-3-GP

10KR2J-3-GP

SUS_PWR DN_ACK_CPU

1D8V_S5

1D8V_S5

RTCRST_O N(24)

R1826

R1826
0R2J-2-GP

0R2J-2-GP

3D3V_S0

12

R1857

R1857
1KR2J-1-GP

1KR2J-1-GP

X01

PLT_RST# (24,35,63,65)

D

Q1809

Q1809
2N7002K-2-GP

2N7002K-2-GP

84.2N702.J31

84.2N702.J31

2ND = 84.2N702.031

2ND = 84.2N702.031

S

G

1D8V_S5

R1844

R1844

10KR2J-3-GP

10KR2J-3-GP

DY

DY

1 2

5V_S5

R1849

R1849
10KR2J-3-GP

10KR2J-3-GP

DY

DY

1 2

SUS_PWR DN_ACK_B

1 2

G

S

Q1811

Q1811
2N7002K-2-GP

2N7002K-2-GP

DY

DY

84.2N702.J31

DY

DY

1 2

100KR2J-1-GP

100KR2J-1-GP

84.2N702.J31

2ND = 84.2N702.031

2ND = 84.2N702.031

D

R1819

R1819

1 2

Wistron Confidential document, Anyone can not
Duplicate, Modify, Forward or any other purpose
application without get Wistron permission

<Core Desig n>

<Core Desig n>

<Core Desig n>

Title

Title

Title

CPU (CLK/SPI/SIDEBAND/JTAG)

CPU (CLK/SPI/SIDEBAND/JTAG)

CPU (CLK/SPI/SIDEBAND/JTAG)

Size Document Num ber Rev

Size Document Num ber Rev

Size Document Num ber Rev
A2

A2

A2

Tuesday, April 01, 2014

Tuesday, April 01, 2014

Tuesday, April 01, 2014
Date: Sheet of

Date: Sheet of

Date: Sheet of

3D3V_S5

R1858

R1858
10KR2J-3-GP

10KR2J-3-GP

DY

DY

1 2

G

S

Q1801

Q1801
2N7002K-2-GP

2N7002K-2-GP

84.2N702.J31

84.2N702.J31

2ND = 84.2N702.031

2ND = 84.2N702.031

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin T ai Wu Rd., H sichih,

21F, 88, Sec.1, Hsin T ai Wu Rd., H sichih,

21F, 88, Sec.1, Hsin T ai Wu Rd., H sichih,
Taipei Hsie n 221, Taiwan, R.O.C.

Taipei Hsie n 221, Taiwan, R.O.C.

Taipei Hsie n 221, Taiwan, R.O.C.

Redwood 11.6"

Redwood 11.6"

Redwood 11.6"

1

D

18 102

18 102

18 102

SUS_PWR DN_ACK (24)

SRTC_RST #

X01

A00

A00

A00

www.vinafix.vn

5

4

3

2

1

SSID = PCH

D D

CPU1D

CPU1D

MMC1_RCOMP

OS_SELECT1
OS_SELECT2

SD3_RCOMP

BF6

SATA_TXP_0

BG7

SATA_TXN_0

AU16

SATA_RXP_0

AV16

SATA_RXN_0

BD10

SATA_TXP_1

BF10

SATA_TXN_1

AY16

SATA_RXP_1

BA16

SATA_RXN_1

BB10

ICLK_SATA_TERMP

BC10

ICLK_SATA_TERMN

BA12

SATA_GP0

AY14

SATA_GP1

AY12

SATA_LED

AU18

SATA_RCOMP_P_AU18

AT18

SATA_RCOMP_N_AT18

AT22

MMC1_CLK

AV20

MMC1_D0

AU22

MMC1_D1

AV22

MMC1_D2

AT20

MMC1_D3

AY24

MMC1_D4

AU26

MMC1_D5

AT26

MMC1_D6

AU20

MMC1_D7

AV26

MMC1_CMD

BA24

MMC1_RST

AY18

MMC1_RCOMP

BA18

SD2_CLK

AY20

SD2_D0

BD20

SD2_D1

BA20

SD2_D2

BD18

SD2_D3_CD

BC18

SD2_CMD

AY26

SD3_CLK

AT28

SD3_D0

BD26

SD3_D1

AU28

SD3_D2

BA26

SD3_D3

BC24

SD3_CD#

AV28

SD3_CMD

BF22

SD3_1P8EN

BD22

SD3_PWREN

BF26

SD3_RCOMP

BAY-TRAIL-GP

BAY-TRAIL-GP

SATA0_PTX_DR X_P0(56)
SATA0_PTX_DR X_N0(56)

HDD

SATA0_PRX_DT X_P0(56)

SATA0_PRX_DT X_N0(56)

ICLK_SATA_TERMP

R1909

R1909
402R2F-GP

402R2F-GP

ICLK_SATA_TERMN

SATA_RCOMP_ DP
SATA_RCOMP_ DN

12

1 2

R1912

R1912
49D9R2F-L1-G P

49D9R2F-L1-G P

SOC_RUNT IME_SCI#(24)

1D8V_S0 1D8V_S0

12

R1902

R1902
10KR2J-3-GP

10KR2J-3-GP

DY

DY

C C

12

R1904

R1904
10KR2J-3-GP

10KR2J-3-GP

DY

DY

12

12

R1903

R1903
10KR2J-3-GP

10KR2J-3-GP

OS_SELECT1OS_SELECT2

R1905

R1905
10KR2J-3-GP

10KR2J-3-GP

2013/04/08

● = Default

●

Android

Win8.1 Dual OS

0

1

OS_SELECT1

OS_SELECT2

B B

0

0

0

1

1 2

R1922

R1922
49D9R2F-L1-G P

49D9R2F-L1-G P

1.8V

BAY TRAIL-M/D SOC

BAY TRAIL-M/D SOC

1.8V

1.5V

1.8V

1.0V

PCIE_TXP_0

1.0V

PCIE_TXN_0

PCIE_RXP_0

PCIE_RXN_0

PCIE_TXP_1
PCIE_TXN_1

PCIE_RXP_1
PCIE_RXN_1

PCIE_TXP_2
PCIE_TXN_2

PCIE_RXP_2
PCIE_RXN_2

PCIE_TXP_3
PCIE_TXN_3

PCIE_RXP_3
PCIE_RXN_3

VSS_BB7
VSS_BB5

PCIE_CLKREQ_0
PCIE_CLKREQ_1
PCIE_CLKREQ_2
PCIE_CLKREQ_3

SD3_WP_BD5

PCIE_RCOMP_P_AP14
PCIE_RCOMP_N_AP13

RESERVED_BB4
RESERVED_BB3

RESERVED_AV10

RESERVED_AV9

HDA_LPE_RCOMP

HDA_RST

HDA_SYNC

HDA_CLK
HDA_SDO
HDA_SDI0
HDA_SDI1

HDA_DOCKRST

HDA_DOCKEN

LPE_I2S2_CLK

LPE_I2S2_FRM

LPE_I2S2_DATAOUT

LPE_I2S2_DATAIN

RESERVED_P34

RESERVED_N34

RESERVED_AK9
RESERVED_AK7

PROCHOT

4 OF 13

4 OF 13

PCIE_TXP0_C

AY7

PCIE_TXN0_C

AY6

AT14
AT13

PCIE_TXP1

AV6

PCIE_TXN1

AV4

PCIE_RXP1

AT10

PCIE_RXN1

AT9

PCIE_TXP2

AT7

PCIE_TXN2

AT6

PCIE_RXP2

AP12

PCIE_RXN2

AP10

PCIE_TXP3

AP6

PCIE_TXN3

AP4

PCIE_RXP3

AP9

PCIE_RXN3

AP7

BB7
BB5

BG3
BD7

HDD_FALL_INT _C

BG5

PCIE_CLKREQ#_3

BE3
BD5

PCIE_RCOMP_P_AP 14_AP14

AP14

PCIE_RCOMP_N _AP13_AP13

AP13

BB4
BB3
AV10
AV9

HDA_LPE_RC OMP

BF20

HDA_RST#

BG22

HDA_SYNC

BH20

HDA_BITCLK

BJ21

HDA_SDOU T

BG20
BG19

HDA_SDI1

BG21
BH18
BG18

BF28

LPE_I2S2_FRM

BA30

LPE_I2S2_DATAOUT

BC30
BD28

P34
N34

AK9
AK7

H_PROCHO T#_R

C24

SC47P50V2JN-3G P

SC47P50V2JN-3G P

C1901

C1901

1
1

1
1

1
1

1
1

1
1

1
1

1 2

R1914

R1914
49D9R2F-L1-G P

49D9R2F-L1-G P

1

TP1901 TPA D14-OP-GPTP1901 T PAD14-OP-GP

R1923

R1923

12

0R0402-PAD

0R0402-PAD

DY

DY

R1919 402R 2F-GPR1919 4 02R2F-GP

HDA_SDIN0 (27)

C1911SCD1U10V2KX- L1-GP C1911SCD1U 10V2KX-L1-GP

12

C1912SCD1U10V2KX- L1-GP C1912SCD1U 10V2KX-L1-GP

12

TP1902TPAD14-OP-GP TP1902TPAD14-OP-GP
TP1903TPAD14-OP-GP TP1903TPAD14-OP-GP

TP1904TPAD14-OP-GP TP1904TPAD14-OP-GP
TP1905TPAD14-OP-GP TP1905TPAD14-OP-GP

TP1906TPAD14-OP-GP TP1906TPAD14-OP-GP
TP1907TPAD14-OP-GP TP1907TPAD14-OP-GP

TP1908TPAD14-OP-GP TP1908TPAD14-OP-GP
TP1909TPAD14-OP-GP TP1909TPAD14-OP-GP

TP1910TPAD14-OP-GP TP1910TPAD14-OP-GP
TP1911TPAD14-OP-GP TP1911TPAD14-OP-GP

TP1912TPAD14-OP-GP TP1912TPAD14-OP-GP
TP1913TPAD14-OP-GP TP1913TPAD14-OP-GP

CLK_PCIE_WLA N_REQ#_CPU (63)

INT_TP# (62)

12

R1917 33R 2J-L1-GPR1917 33R2J-L1-GP

1 2

LPE_I2S2_FRM (15)
LPE_I2S2_DATAOUT (15,24)

R1931

R1931
71D5R2F-GP

71D5R2F-GP

1 2

12

Modify 20130702
Follow Intel CHKLST V1.2

70.7 Ω ±5% pull-up to V1P0S

1D0V_S0

H_PROCHO T# (24,44,46)

PCIE_PTX_WLA NRX_P0_C (63)
PCIE_PTX_WLA NRX_N0_C (63)

PCIE_PRX_W LANTX_P0 (63)

PCIE_PRX_W LANTX_N0 ( 63)

HDA_CODE C_SDOUT (27)

WLAN

A00

R1924

R1924
0R0402-PAD

0R0402-PAD

ICLK_SATA_TERMP

12

ICLK_SATA_TERMN

12

R1925

R1925
0R0402-PAD

0R0402-PAD

SOC_RUNT IME_SCI#

1D8V_S0

A A

5

R1901

R1901
10KR2J-3-GP

10KR2J-3-GP

12

HDA_CODE C_BITCLK(27)

HDA_CODE C_RST#(27,29 )

HDA_SYNC_RHDA_SYNC

12

R1926

R1926
33R2J-L1-GP

33R2J-L1-GP

4

RN1901

RN1901

1
2 3

SRN33J-5-G P-U

SRN33J-5-G P-U

D

DY

DY

2N7002K-2-GP

2N7002K-2-GP

84.2N702.J31

84.2N702.J31

2ND = 84.2N702.031

2ND = 84.2N702.031

R1929

R1929
0R0402-PAD

0R0402-PAD

Q1902

Q1902

HDA_BITCLK

4

HDA_RST#

5V_S0

G

S

12

HDA_CODE C_SYNC (27)

3

CLK_PCIE_WLA N_REQ#_CPU
PCIE_CLKREQ#_3

RN1902

RN1902

1
2 3

SRN10KJ-5-G P

SRN10KJ-5-G P

HDA_RST#

SC22P50V2JN-L- GP

SC22P50V2JN-L- GP

C1910

C1910

4

12

1D8V_S0

3D3V_S0 1D8V_S0 1D8V_S0

X01

HDD_FALL_INT(67,68)

DY

DY

2

R1906

R1906

2K2R2J-2-GP

2K2R2J-2-GP

12

DY

DY

D S

DMN5L06K-7-G P

DMN5L06K-7-G P

84.05067.031

84.05067.031

<Core Desig n>

<Core Desig n>

<Core Desig n>

Title

Title

Title

Size Document Num ber Rev

Size Document Num ber Rev

Size Document Num ber Rev
A2

A2

A2

Tuesday, April 01, 2014

Tuesday, April 01, 2014

Tuesday, April 01, 2014
Date: Sheet of

Date: Sheet of

Date: Sheet of

12

R1907

R1907
2K2R2J-2-GP

2K2R2J-2-GP

G

HDD_FALL_INT _C

Q1901

Q1901

Wistron Confidential document, Anyone can not
Duplicate, Modify, Forward or any other purpose
application without get Wistron permission

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin T ai Wu Rd., H sichih,

21F, 88, Sec.1, Hsin T ai Wu Rd., H sichih,

21F, 88, Sec.1, Hsin T ai Wu Rd., H sichih,
Taipei Hsie n 221, Taiwan, R.O.C.

Taipei Hsie n 221, Taiwan, R.O.C.

Taipei Hsie n 221, Taiwan, R.O.C.

CPU (SATA/PCIE/IHDA)

CPU (SATA/PCIE/IHDA)

CPU (SATA/PCIE/IHDA)

Redwood 11.6"

Redwood 11.6"

Redwood 11.6"

1

X01

19 102

19 102

19 102

A00

A00

A00

www.vinafix.vn

5

4

3

2

1

SSID = PCH

D D

C C

Blanking

B B

Wistron Confidential document, Anyone can not
Duplicate, Modify, Forward or any other purpose

<Core Design>

<Core Design>

<Core Design>

A A

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev
A4

A4

A4

Date: Sheet of

Date: Sheet of

5

4

www.vinafix.vn

3

Date: Sheet of

application without get Wistron permission

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

Reserved

Reserved

Redwood 11.6"

Redwood 11.6"

Tuesday, April 01, 2014

Tuesday, April 01, 2014

Tuesday, April 01, 2014

2

Redwood 11.6"

20 102

20 102

20 102

1

A00

A00

A00

5

D D

4

3

2

1

1D0V_S0

1D0V_S5

C C

1D0V_S0

1D05V_S 0

1D0V_S0

CRB

接接接接

1.05V

1D05V_S 0

B B

1D0V_S5

1D35V_S 0

CPU1H

CPU1H

V32

SVID_V1P0_S3_V32

BJ6

VGA_V1P0_S3_BJ6

AD35

DRAM_V1P0_S0IX_AD35

AF35

DRAM_V1P0_S0IX_AF35

AF36

DRAM_V1P0_S0IX_AF36

AA36

DRAM_V1P0_S0IX_AA36

AJ36

DRAM_V1P0_S0IX_AJ36

AK35

DRAM_V1P0_S0IX_AK35

AK36

DRAM_V1P0_S0IX_AK36

Y35

DRAM_V1P0_S0IX_Y35

Y36

DRAM_V1P0_S0IX_Y36

AK19

DDI_V1P0_S0IX_AK19

AK21

DDI_V1P0_S0IX_AK21

AJ18

DDI_V1P0_S0IX_AJ18

AM16

DDI_V1P0_S0IX_AM16

U22

UNCORE_V1P0_G3_U22

V22

UNCORE_V1P0_G3_V22

AN29

VIS_V1P0_S0IX_AN29

AN30

VIS_V1P0_S0IX_AN30

AF16

UNCORE_V1P0_S3_AF16

AF18

UNCORE_V1P0_S3_AF18

Y18

UNCORE_V1P0_S3_Y18

G1

UNCORE_V1P0_S3_G1

AM21

PCIE_V1P0_S3_AM21

AN21

PCIE_V1P0_S3_AN21

AN18

PCIE_GBE_SATA_V1P0_S3_AN18

AN19

SATA_V1P0_S3_AN19

AA33

CORE_V1P05_S3_AA33

AF21

UNCORE_V1P0_S0IX_AF21

AG21

UNCORE_V1P0_S0IX_AG21

V24

VIS_V1P0_S0IX_V24

Y22

VIS_V1P0_S0IX_Y22

Y24

VIS_V1P0_S0IX_Y24

M14

USB_V1P0_S3_M14

U18

USB_V1P0_S3_U18

U19

USB_V1P0_S3_U19

AN25

GPIO_V1P0_S3_AN25

Y19

USB3_V1P0_G3_Y19

C3

USB3_V1P0_G3_C3

C5

UNCORE_V1P0_G3_C5

B6

UNCORE_V1P0_G3_B6

AC32

CORE_V1P0_S3_AC32

Y32

CORE_V1P0_S3_Y32

U36

UNCORE_V1P35_S0IX_F4_U36

AA25

UNCORE_V1P35_S0IX_F5_AA25

AG32

UNCORE_V1P35_S0IX_F2_AG32

V36

UNCORE_V1P35_S0IX_F3_V36

BD1

VGA_V1P35_S3_F1_BD1

AF19

UNCORE_V1P35_S0IX_F6

AG19

UNCORE_V1P35_S0IX_F1_AG19

AJ19

ICLK_V1P35_S3_F1_AJ19

AG18

ICLK_V1P35_S3_F2

AN16

VSSA_AN16

U16

USB_VSSA_U16

BAY-TRAIL-GP

BAY-TRAIL-GP

BAY TRAIL-M/D SOC

BAY TRAIL-M/D SOC

DRAM_V1P35_S0IX_F1_AD36

HDA_LPE_V1P5V1P8_S3_AM32

UNCORE_V1P8_S3_AM30

UNCORE_V1P8_S3_AN32

LPC_V1P8V3P3_S3_AM27

UNCORE_V1P8_G3_U24

UNCORE_V1P8_S3_U38

VGA_V3P3_S3_AN24

SD3_V1P8V3P3_S3_AN27

USB_HSIC_V1P2_G3_V18
UNCORE_V1P8_G3_AA18

CORE_V1P05_S3_AF33
CORE_V1P05_S3_AG33
CORE_V1P05_S3_AG35

CORE_V1P05_S3_U33
CORE_V1P05_S3_U35
CORE_V1P05_S3_V33

PCIE_V1P0_S3_AK18
PCIE_V1P0_S3_AM18

8 OF 13

8 OF 13

USB_V3P3_G3_N18

USB_V3P3_G3_P18

PCU_V1P8_G3_V25
PCU_V3P3_G3_N22

VSS_AD16
VSS_AD18

RTC_VCC_P22
USB_V1P8_G3_N20
PMU_V1P8_G3_U25

VSS_A3

VSS_A49

VSS_A5
VSS_A51
VSS_A52

VSS_A6

VSS_B2
VSS_B52
VSS_B53
VSS_BE1

VSS_BE53

VSS_BG1

VSS_BG53

VSS_BH1

VSS_BH2
VSS_BH52
VSS_BH53

VSS_BJ2
VSS_BJ3

VSS_BJ5
VSS_BJ49
VSS_BJ51
VSS_BJ52

VSS_C1

VSS_C53

VSS_E1

VSS_E53

RESERVED_F1

AD36
AM32
AM30
AN32
AM27
U24
N18
P18
U38
AN24
V25
N22
AN27
AD16
AD18
V18
AA18
P22
N20
U25
AF33
AG33
AG35
U33
U35
V33
A3
A49
A5
A51
A52
A6
B2
B52
B53
BE1
BE53
BG1
BG53
BH1
BH2
BH52
BH53
BJ2
BJ3
BJ5
BJ49
BJ51
BJ52
C1
C53
E1
E53
F1
AK18
AM18

1D35V_S 0

SD3_V1P 8V3P3_S3_AN2 7

USB_HSIC_ V1P2_G3_V18

1D5V_S0

1D8V_S0

3D3V_S0

3D3V_S5

1D8V_S0
3D3V_S0

3D3V_S5

RTC_AUX _S5

1D0V_S0

1D05V_S 0

1D8V_S5

1D8V_S5

1D8V_S5

SD3_V1P 8V3P3_S3_AN2 7

USB_HSIC_ V1P2_G3_V18

R2102

R2102
0R0402-P AD

0R0402-P AD

1 2

1 2

DY

DY

R2103

R2103
0R2J-2-GP

0R2J-2-GP

R2104

R2104
0R0402-P AD

0R0402-P AD

1 2

3D3V_S0

1D8V_S0

1D0V_S5

Wistron Confidential document, Anyone can not
Duplicate, Modify, Forward or any other purpose

A A

5

4

www.vinafix.vn

3

2

application without get Wistron permission

<Core Design>

<Core Design>

<Core Design>

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Title

Title

Size Document N umber Rev

Size Document N umber Rev

Size Document N umber Rev
A3

A3

A3

Date: Sheet of

Date: Sheet of

Date: Sheet of

CPU (POWER1)

CPU (POWER1)

CPU (POWER1)

Redwood 11.6"

Redwood 11.6"

Tuesday, April 01, 2014

Tuesday, April 01, 2014

Tuesday, April 01, 2014

Redwood 11.6"

Taipei Hsien 221, Taiwan, R.O.C.

21 102

21 102

21 102

1

A00

A00

A00

5

D D

C C

4

3

2

1

Blanking

B B

<Core Design>

<Core Design>

<Core Design>

Wistron Confidential document, Anyone can not
Duplicate, Modify, Forward or any other purpose
application without get Wistron permission

Wistron Corporation

Wistron Corporation

A A

Title

Title

Title

Reserved

Reserved

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev
A4

A4

A4

Tuesday, April 01, 2014

Tuesday, April 01, 2014

Tuesday, April 01, 2014

Date: Sheet of

Date: Sheet of

5

4

www.vinafix.vn

3

Date: Sheet of

2

Reserved

Redwood 11.6"

Redwood 11.6"

Redwood 11.6"

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

A00

A00

22 102

22 102

22 102

1

A00

5

4

3

2

1

SSID = PCH

D D

C C

Blanking

B B

<Core Design>

<Core Design>

<Core Design>

Wistron Corporation

Wistron Corporation

A A

Title

Title

Title

CPU (VSS)

CPU (VSS)

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev
A4

A4

A4

Date: Sheet of

Date: Sheet of

5

4

www.vinafix.vn

3

Date: Sheet of

CPU (VSS)

Tuesday, April 01, 2014

Tuesday, April 01, 2014

Tuesday, April 01, 2014

2

Redwood 11.6"

Redwood 11.6"

Redwood 11.6"

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

A00

A00

23 102

23 102

23 102

1

A00

SSID = KBC

5

4

3

2

1

SCD1U10V2KX-L1-GP

SCD1U10V2KX-L1-GP

2D2R3-1-U-GP

2D2R3-1-U-GP

12

C2429

C2429

SCD1U10V2KX-L1-GP

SCD1U10V2KX-L1-GP

115

102

100
108

101
105
106
107

119
120

123

117

118

104

110
112

124
121
111

3D3V_AUX_KBC

R2404

R2404

1 2

12

12

C2430

C2430

C2411

C2411

SCD1U10V2KX-L1-GP

SCD1U10V2KX-L1-GP

SC2D2U6D3V2MX-GP

SC2D2U6D3V2MX-GP

KBC24

KBC24

19

VCC

46

VCC

76

VCC

88

VCC
VCC

AVCC

4

VDD

12

VTT

97

GPIO90 /AD0

98

GPIO91 /AD1

99

GPIO92 /AD2
GPIO93 /AD3
GPIO05 /AD4

96

GPIO04 /AD5

95

GPIO03 /EXT_PUR ST#/AD 6

94

GPIO07 /AD7/VD_ IN2

GPIO94 /DA0
GPIO95 /DA1
GPIO96 /DA2
GPIO97 /DA3

70

GPIO17 /SCL1/N2T CK

69

GPIO22 /SDA1/N2T MS

67

GPIO73 /SCL2/N2T CK

68

GPIO74 /SDA2/N2T MS
GPIO23 /SCL3/N2T CK
GPIO31 /SDA3/N2T MS

24

GPIO47 /SCL4A/N2 TCK

28

GPIO53 /SDA4A/N2 TMS

26

GPIO51 /TA3/N2TC K
GPIO67 /SOUT1/N2T MS

72

GPIO37 /PSCLK1

71

GPIO35 /PSDAT1

10

GPIO26 /PSCLK2

11

GPIO27 /PSDAT2

25

GPIO50 /PSCLK3

27

GPIO52 /PSDAT3

31

GPIO56 /TA1
GPIO20 /TA2/IOX _DIN_D IO

63

GPIO14 /TB1

64

GPIO01 /TB2

32

GPIO15 /A_PWM
GPIO21 /B_PWM

62

GPIO13 /C_PWM

65

GPIO32 /D_PWM

22

GPIO45 /E_PWM/D TR1#_ BOUT1

16

GPIO40 /F_PWM/1 _WIR E/RI1#

81

GPIO66 /G_PWM/P SL_GP IO66

66

GPO33/H_ PWM/VD1 _EN#

GPIO80 /VD_IN1

GPIO82 /IOX_LD SH/VD_O UT1
GPIO84 /IOX_SC LK/VD_ OUT2

84

GPIO77 /SPI_MIS O

83

GPIO76 /SPI_MOS I

82

GPIO75 /SPI_SC K

79

GPIO02 /SPI_CS #

GPIO10 /LPCPD#
GPIO85 /GA20
GPIO83 /SOUT_CR

9

GPIO65 /SMI#

8

GPIO11 /CLKRUN#

30

GPIO55 /CLKOUT/I OX_DI N_DIO

NPCE285PA0DX-GP

NPCE285PA0DX-GP

071.00285.000G

071.00285.000G

1KR2J-1-GP

1KR2J-1-GP
R2440

R2440

1 2

KBSIN0/G PIOA0/N2 TCK
KBSIN1/G PIOA1/N2 TMS

KBSIN2/G PIOA2
KBSIN3/G PIOA3
KBSIN4/G PIOA4
KBSIN5/G PIOA5
KBSIN6/G PIOA6
KBSIN7/G PIOA7

KBSOUT0 /GPOB0/S OUT_CR/J ENK#

KBSOUT1 /GPIOB1 /TCK

KBSOUT2 /GPIOB2 /TMS

KBSOUT3 /GPIOB3 /TDI

KBSOUT4 /GPOB4

KBSOUT5 /GPIOB5 /TDO

KBSOUT6 /GPIOB6 /RDY#

KBSOUT7 /GPIOB7
KBSOUT8 /GPIOC0

KBSOUT9 /GPOC1/S DP_VI S#

KBSOUT1 0/P80_C LK/GPI OC2

KBSOUT1 1/P80_D AT/GPI OC3

KBSOUT1 2/GPO64 /TEST#

KBSOUT1 3/GP(I)O6 3/TRIS T#
KBSOUT1 4/GP(I)O6 2/XORT R#
KBSOUT1 5/GPIO6 1/XOR_ OUT

GPIO60 /KBSOUT1 6/DSR1 #

GPIO57 /KBSOUT1 7/DCD1 #

LAD0/GP IOF1
LAD1/GP IOF2
LAD2/GP IOF3
LAD3/GP IOF4

LCLK/GP IOF5
LFRAME# /GPIOF6
LRESET #/GPIOF 7

GPIOC6 /F_CS0#

GPIOC7 /F_SCK

GPIO30 /F_WP# /RTS1#

GPIO41 /F_WP# /PSL_G PIO41

GPIOC5 /F_SDIO /F_SDI O0

GPIOC4 /F_SDI/F _SDIO 1

GPIO81 /F_WP# /F_SDI O2

GPIO00 /32KCLK IN/F_SD IO3

PSL_IN1 #/GPI70

PSL_IN2 #/GPI06 /EXT_P URST#

PSL_OUT #/GPIO7 1

ECSCI# /GPIO54

EXT_RS T#

KBRST# /GPIO86

VCORF

SERIRQ /GPIOF0

GPIO24

GPIO36 /TB3/CTS 1#

GPIO44 /SCL4B
PSL_IN4 #/GPI43
PSL_IN3 #/GPI42

GPIO46 /SDA4B/C IRRXM

GPIO87 /CIRRXM/S IN_CR

GPIO34 /SIN1/CIR RXL

3D3V_AUX_S5 3D3V_AUX_S5

1 2

KBC_ON#_GATE_L

VSBY

VBKUP

PECI

GND
GND
GND
GND
GND
GND

AGND

R2433

R2433
330KR2J-L1-GP

330KR2J-L1-GP

1 2

R2435

R2435
20KR2J-L2-GP

20KR2J-L2-GP

54
55
56
57
58
59
60
61

53
52
51
50
49
48
47
43
42
41
40
39
38
37
36
35
34
33

126
127
128
1
2
3
7

90
92
109
80
87
86
91
77

73
93
74

29
85
122

75
114
44
13
125
6
15

21
20
17
23

113
14

5
18
45
78
89
116

103

EC_SPI_CS#1
EC_SPI_CLK

EC_SPI_SO
EC_SPI_SI

PCH_SUSCLK_KBC

PSL_IN1#
PSL_IN2#
PSL_OUT#

SOC_RUNTIME_SCI#_KBC
ECRST#
H_RCIN#

KBC_VBKUP
KBC_VCORF

INT_SERIRQ

USBDET_CON#

AC_PRESENT

KBC_ON#_GATEPSL_OUT#

KROW0
KROW1
KROW2
KROW3
KROW4
KROW5
KROW6
KROW7

KCOL0
KCOL1
KCOL2
KCOL3
KCOL4
KCOL5
KCOL6
KCOL7
KCOL8
KCOL9
KCOL10
KCOL11
KCOL12
KCOL13
KCOL14
KCOL15

TP_WAKE (62)

LPC_AD0 (16,65)
LPC_AD1 (16,65)
LPC_AD2 (16,65)
LPC_AD3 (16,65)

CLK_PCI_KBC (16)
LPC_FRAME# (16,65)
PLT_RST# (18,35,63,65)

KB_DISABLE (67)

3D3V_AUX_S5

1 2

C2431 SC1U10V2KX-1GPC2431 SC1U10V2KX-1GP

RTC_DET# (25)

RSMRST#_KBC (18,65)

PM_SLP_S4# (18,36,49)

USB_CHG_EN (34)

S5_ENABLE (36)WIFI_RF_EN(63)

R2415

R2415
0R0402-PAD

0R0402-PAD

1 2

EC_AGND

C2419

C2419
SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

1 2

S

G

G

G

D

D

Q2404

Q2404
DMP2130L-7-GP

DMP2130L-7-GP

D

84.02130.031

84.02130.031

2ND = 84.03413.A31

2ND = 84.03413.A31

Q2403

Q2403

G

D

S

2N7002K-2-GP

2N7002K-2-GP

84.2N702.J31

84.2N702.J31

2ND = 84.2N702.031

2ND = 84.2N702.031

3rd = 84.07002.I31

3rd = 84.07002.I31

4th = 84.2N702.W31

4th = 84.2N702.W31

R2431
Reserved for SKU control

C2420

C2420

KROW[0..7] (62)

KCOL[0..15] (62)

R2412 33R2J-L1-GPR2412 33R2J-L1-GP

1 2

R2407 33R2J-L1-GPR2407 33R2J-L1-GP

1 2

R2402 33R2J-L1-GPR2402 33R2J-L1-GP

1 2

RTC_AUX_S5

R2416

R2416
0R0402-PAD

0R0402-PAD

1 2

3D3V_AUX_KBC 3D3V_AUX_KBC

3D3V_AUX_KBC

12

MODEL_ID_AD

12

12

R2436

R2436
100KR2J-1-GP

100KR2J-1-GP
SCD1U10V2KX-L1-GP

SCD1U10V2KX-L1-GP

DY

DY

R2431

R2431
10KR2J-3-GP

10KR2J-3-GP

UMA

UMA

12

R2437

R2437
10KR2J-3-GP

10KR2J-3-GP

S5_ENABLE

www.vinafix.vn

EC_SPI_CS0#_FLASH (25)
EC_SPI_CLK_FLASH (25)
CAP_LED# (62)
BAT_IN# (43)
EC_SPI_SI_FLASH (25)
EC_SPI_SI (25)

PM_CLKRUN#_EC

H_RCIN#

10KR2J-3-GP

10KR2J-3-GP

1KR2J-1-GP

1KR2J-1-GP

R2474

R2474

R2475

R2475

R2473

R2473
10KR2J-3-GP

10KR2J-3-GP

DY

DY

R2469

R2469
10KR2J-3-GP

10KR2J-3-GP

10KR2J-3-GP

10KR2J-3-GP

L_BKLT_EN

1D8V_S0

DY

DY

3D3V_S0

12

12

3D3V_S53D3V_S5

12

12

R2445

R2445

R2451

R2451

4K7R2J-L-GP

4K7R2J-L-GP

2K2R2J-2-GP

2K2R2J-2-GP

DY

DY

DY

DY

EC_SWI#_B

Q2413

Q2413
LMBT3904LT1G-GP

LMBT3904LT1G-GP

CBE

DY

DY

84.T3904.H11

84.T3904.H11

R2434

R2434
0R2J-2-GP

0R2J-2-GP

1 2

1D8V_S03D3V_S0 3D3V_S53D3V_S5 3D3V_S53D3V_S5

12

12

R2455

A00

DY

DY

DY

DY

L_BKLT_EN_B

CBE

DY

DY

84.T3904.H11

84.T3904.H11

1 2

R2430

R2430
0R0402-PAD

0R0402-PAD

R2455
2K2R2J-2-GP

2K2R2J-2-GP

Q2410

Q2410
LMBT3904LT1G-GP

LMBT3904LT1G-GP

L_BKLT_EN_CPU (8) PM_PWRBTN#_CPU (18) AC_PRESENT_CPU (18)

R2439

R2439

EC_SWI# (18)

VOL_UP#

VOL_DOWN#

R2470

R2470

10KR2J-3-GP

10KR2J-3-GP

DY

DY

1 2

PM_PWRBTN#

A00 A00

3D3V_S0

R2458

R2458
100KR2J-1-GP

100KR2J-1-GP

1 2

1 2

R2454

R2454
100KR2J-1-GP

100KR2J-1-GP

3D3V_S53D3V_S5 3D3V_S53D3V_S5

12

12

R2438

R2438

R2443

R2443

4K7R2J-L-GP

4K7R2J-L-GP

2K2R2J-2-GP

2K2R2J-2-GP

DY

DY

DY

DY

SOC_RUNTIME_SCI#_B

Q2407

Q2407
LMBT3904LT1G-GP

LMBT3904LT1G-GP

CBE

DY

DY

84.T3904.H11

84.T3904.H11

R2460

R2460
0R2J-2-GP

0R2J-2-GP

1 2

12

R2456

R2456
2K2R2J-2-GP

2K2R2J-2-GP

DY

DY

PM_PWRBTN#_B

Q2411

Q2411
LMBT3904LT1G-GP

LMBT3904LT1G-GP

CBE

DY

DY

84.T3904.H11

84.T3904.H11

1 2

R2441

R2441
0R0402-PAD

0R0402-PAD

Level shift

12

12

RST Key

3D3V_S0

SCD1U10V2KX-L1-GP

SCD1U10V2KX-L1-GP

12

C2435

C2435

INT_SERIRQ_OE
INT_SERIRQ

PURE_HW_SHUTDOWN#(26,36)

U2402

U2402

6

VCCB

5

OE

4

B

G2129TL1U-GP

G2129TL1U-GP

VCCA should not exceed VCCB

73.02129.02J

73.02129.02J

1D8V_S0

12

C2434

C2434
SCD1U10V2KX-L1-GP

SCD1U10V2KX-L1-GP

1

VCCA

2

GND

3

INT_SERIRQ_CPU (16)

A

PCH_SUSCLK(18)

3D3V_AUX_S5

12

R2421

R2421
10KR2J-3-GP

10KR2J-3-GP

E

B

C

Q2401

Q2401
MMBT3906-4-GP

MMBT3906-4-GP

84.T3906.A11

84.T3906.A11

2nd = 84.03906.F11

2nd = 84.03906.F11

ECRST#

12

C2415

C2415

SC1U6D3V2KX-L-1-GP

SC1U6D3V2KX-L-1-GP

DY

DY

CLK_PCI_KBC

12

C2436

C2436

DY

DY

SC22P50V2GN-GP

SC22P50V2GN-GP

Level shift

SOC_RUNTIME_SCI# (19) EC_SMI# (18)

ECSMI#_KBCECSWI#_KBC SOC_RUNTIME_SCI#_KBC

R2472

R2472

10KR2J-3-GP

10KR2J-3-GP

DY

DY

1 2

AC_PRESENT

3D3V_S5

12

R2450

R2450

4K7R2J-L-GP

4K7R2J-L-GP

DY

DY

PCH_SUSCLK_KBC

RSTSW1

RSTSW1

12

SW-TACT-4P-71-GP

SW-TACT-4P-71-GP

56

DY

DY

62.40089.441

62.40089.441

4 3

2nd = 62.40009.D71

2nd = 62.40009.D71

<Core Design>

<Core Design>

<Core Design>

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev
A1

A1

A1

Tuesday, April 01, 2014

Tuesday, April 01, 2014

Tuesday, April 01, 2014

Date: Sheet of

Date: Sheet of

Date: Sheet of

12

12

R2446

R2446

R2444

R2444

4K7R2J-L-GP

4K7R2J-L-GP

2K2R2J-2-GP

2K2R2J-2-GP

DY

DY

DY

DY

EC_SMI#_B

Q2408

Q2408
LMBT3904LT1G-GP

LMBT3904LT1G-GP

DY

DY

84.T3904.H11

84.T3904.H11

R2461

R2461
0R2J-2-GP

0R2J-2-GP

1 2

12

R2457

R2457
2K2R2J-2-GP

2K2R2J-2-GP

DY

DY

AC_PRESENT_B

Q2412

Q2412
LMBT3904LT1G-GP

LMBT3904LT1G-GP

CBE

DY

DY

84.T3904.H11

84.T3904.H11

1 2

R2453

R2453
0R0402-PAD

0R0402-PAD

Q2409

Q2409

3 4

2

5

DY

DY

PCH_SUSCLK_D

1

6

DMN601DWK-7-1-GP

DMN601DWK-7-1-GP

75.00601.07C

75.00601.07C

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

KBC_NPCE985PB

KBC_NPCE985PB

KBC_NPCE985PB

Redwood 11.6"

Redwood 11.6"

Redwood 11.6"

CBE

3D3V_S5

DY

DY

24 102

24 102

24 102

12

R2447

R2447
10KR2J-3-GP

10KR2J-3-GP

A00

A00

A00

AVCC

3D3V_AUX_KBC

D D

1D05V_S0

3D3V_AUX_KBC

3D3V_S5

3D3V_S0

C C

3D3V_S5

3D3V_AUX_KBC

3D3V_S5

5V_S0

B B

HOME_BTN#(52)

GPIO0 High Active

PROCHOT_EC

12

R2432

R2432
100KR2J-1-GP

100KR2J-1-GP

DY

DY

SYS_PWROK

DY

DY

BLUETOOTH_EN

DY

WIFI_RF_EN

ALL_SYS_PWRGD

S5_ENABLE

DY

DY

DY

DY

DY

DY

DY

A A

1 2

R2401

R2401
10KR2J-3-GP

10KR2J-3-GP

1 2

R2414

R2414
0R0402-PAD

0R0402-PAD

R2442

R2442
100KR2J-1-GP

100KR2J-1-GP

1 2

R2418

R2418
10KR2J-3-GP

10KR2J-3-GP

12

Modify 20130610

RN2401

RN2401

1

4

2 3

SRN2K2J-5-GP

SRN2K2J-5-GP

R2417

R2417
10KR2F-2-GP

10KR2F-2-GP

12

R2420

R2420

1 2

8K2R2J-L-2-GP

8K2R2J-L-2-GP

R2423

R2423
10KR2J-3-GP

10KR2J-3-GP

12

1 2

R2459 100KR2J-1-GPR2459 100KR2J-1-GP

1 2

R2452 100KR2J-1-GPR2452 100KR2J-1-GP

TOUCH_PANEL_EN

1 2

R2403

R2403
10KR2J-3-GP

10KR2J-3-GP

1 2

DY

DY

C2418 SCD1U10V2KX-L1-GP

C2418 SCD1U10V2KX-L1-GP

R2406

R2406
10KR2J-3-GP

10KR2J-3-GP

R2409

R2409
0R2J-2-GP

0R2J-2-GP

1 2

Q2402

Q2402

G

S

2N7002K-2-GP

2N7002K-2-GP

84.2N702.J31

84.2N702.J31

2ND = 84.2N702.031

2ND = 84.2N702.031

EC2440

EC2440

1 2

SCD1U25V2KX-GP

SCD1U25V2KX-GP

EC2436

EC2436

1 2

SCD1U25V2KX-GP

SCD1U25V2KX-GP

EC2437

EC2437

1 2

SCD1U25V2KX-GP

SCD1U25V2KX-GP

EC2438

EC2438

1 2

SCD1U25V2KX-GP

SCD1U25V2KX-GP

EC2439

EC2439

1 2

SCD1U25V2KX-GP

SCD1U25V2KX-GP

RTC_DET#

BAT_IN#

ECRST#

SML1_CLK
SML1_DATA

FAN_TACH1

H_A20GATE

KB_CLOSE#_2

AC_IN_KBC#

USB_DET#

AD_IA

3D3V_AUX_KBC

EC_VTT

12

C2437

C2437

SCD1U10V2KX-L1-GP

SCD1U10V2KX-L1-GP

1 2

HOME_BTN#_KBC

D

BATTERY / CHARGER ------>

2nd G-sensor / Thermal ------>

Note : After 1D2V_S5_PWRGD alerting, >10us for RSMRST#_KBC

LPE_I2S2_DATAOUT(15,19)

A00

H_PROCHOT# (19,44,46)

3D3V_AUX_KBC

A00

PCB_VER_AD

12

C2417

C2417

SCD1U10V2KX-L1-GP

SCD1U10V2KX-L1-GP

DY

DY

12

12

R2424

R2424
47KR2J-2-GP

47KR2J-2-GP

-1

-1

R2426

R2426

LCD_TST(52)

1 2

R2467

R2467
0R0402-PAD

0R0402-PAD

100KR2F-L1-GP

100KR2F-L1-GP

SCD1U10V2KX-L1-GP

SCD1U10V2KX-L1-GP

LCD_TST_EN(52)

SUS_PWRDN_ACK(18)

3D3V_S0

C2432

C2432

R2413 0R0402-PADR2413 0R0402-PAD

ME_UNLOCK#

12

1 2

12

12

C2425

C2425

C2412

C2412

SCD1U10V2KX-L1-GP

SCD1U10V2KX-L1-GP

EC_AGND

12

C2433

C2433

SC2D2U6D3V3MX-1-GP

SC2D2U6D3V3MX-1-GP

DY

DY

EC_AGND

KB_CLOSE#_2(63)

USBCHARGER_CB0(34)

FAN1_DAC_1(26)
AD_IA_HW(44)

BAT_SCL(43,44)
BAT_SDA(43,44)

SML1_CLK(26,67)

SML1_DATA(26,67)

ALL_SYS_PWRGD(36)

PWR_CHG_AD_OFF(42)

1 2

R2411

R2411
0R0402-PAD

0R0402-PAD

X01

EC_BRIGHTNESS(52)

1D8V_S5_PG(18,51)

USB_PWR_EN#(33,63)

BLUETOOTH_EN(63)

TOUCH_PANEL_EN(52)

PM_CLKRUN#_EC(16)

KBC_PWRBTN#(63)

AC_IN#(44)

3D3V_AUX_S5

R2427

R2427

330KR2J-L1-GP

330KR2J-L1-GP

USBDET_CON#(34)

R2405

R2405

1 2

0R0603-PAD

0R0603-PAD

SC2D2U6D3V2MX-GP

SC2D2U6D3V2MX-GP

KBC_VCC

12

12

C2426

C2426

SCD1U10V2KX-L1-GP

SCD1U10V2KX-L1-GP

AD_IA(44)

C2438 SCD1U10V2KX-L1-GPC2438 SCD1U10V2KX-L1-GP

1 2

PSID_EC(42)

EC_GPIO05(54)

TP_ON#(62)

LID_CLOSE#(64)

RTCRST_ON(18)

TPCLK(62)

TPDATA(62)

BLON_OUT(52)

FAN_TACH1(26)

VOL_UP#(63)

PM_SLP_S3#(18,36,37,46,49)

KBC_BEEP(27)

PWRLED#(63)

AC_IN_KBC#(42)

BATTLED#(63)

R2408

R2408
0R2J-2-GP

0R2J-2-GP

1 2

DY

DY

SYS_PWROK(26,36)

1

TP2401T PAD14-OP-GP TP2401TPAD14-OP-GP

VOL_DOWN#(63)

AMP_MUTE#(27)

3D3V_AUX_S5

R2425

R2425
330KR2J-L1-GP

330KR2J-L1-GP

A00

1 2

PSL_IN2#

1 2

R2422

R2422
0R0402-PAD

0R0402-PAD

PSL_IN1#

1 2

R2419

R2419
0R0402-PAD

0R0402-PAD

D2404

D2404

USB_DET#

1

1 2

3

DY

DY

KBC_ON#_GATE_L

2

BAT54CPT-2-GP

BAT54CPT-2-GP

75.00054.K7D

75.00054.K7D

C2427

C2427

SCD1U10V2KX-L1-GP

SCD1U10V2KX-L1-GP

12

C2428

C2428

EC_VTT

PCB_VER_AD

HOME_BTN#_KBC

MODEL_ID_AD

ECSMI#_KBC

PROCHOT_EC

ECSWI#_KBC

SUS_PWR_ACK_R

PM_PWRBTN#

L_BKLT_EN

1D8V_S5_PG_KBC

ME_UNLOCK#

H_A20GATE
E51_TxD

For EMI request

5

4

3

2

1

SSID = Flash.ROM

U2502

D D

1D8V_SP I

PCH_SPI_S I_FLASH

U2502

8

VCC

7

HOLD#/RESET#/IO3

6

CLK

5

DI/IO0

W25 Q64FWSSIG-GP

W25 Q64FWSSIG-GP

72.25Q64.S01

72.25Q64.S01

CS#

DO/IO1

WP#/IO2

GND

SSID = RBAT

C C

SPI FLASH ROM (8M byte) for PCH

RN2501

RN2501

4 5
3
2
1

SRN4K7J -10-GP

SRN4K7J -10-GP

D

1
2
3
4

RTC_AUX _S5

C2505

C2505

SC1U6D3V3KX-2GP

SC1U6D3V3KX-2GP

SPI_HOLD_ 0#
PCH_SPI_W P#
PCH_SPI_C S0#_FLASH

PCH_SPI_S O_FLASHSPI_HOLD_ 0#
PCH_SPI_W P#PCH_SPI_C LK_FLASH

1D8V_SP I 1D8V_S5

R2507

R2507

12

0R0402-P AD

0R0402-P AD

Q2501

Q2501

1

3

2

BAS40C-2 -GP

BAS40C-2 -GP

75.00040.07D

1 2

75.00040.07D

2nd = 75.00040.A7D

2nd = 75.00040.A7D

3rd = 75.00040.C7D

3rd = 75.00040.C7D

3D3V_AU X_S5

R2505

R2505

10MR2J-L -GP

10MR2J-L -GP

12

Width=20mils

Q2505

Q2505

G

S

2N7002K -2-GP

2N7002K -2-GP

84.2N702.J31

84.2N702.J31

2ND = 84.2N702.031

2ND = 84.2N702.031

3rd = 84.07002.I31

3rd = 84.07002.I31

4th = 84.2N702.W31

4th = 84.2N702.W31

6
7
8

12

C2506

C2506

DY

DY

SC10U6D 3V5KX-L-1-GP

SC10U6D 3V5KX-L-1-GP

+RTC_VC C

1D8V_SP I

1D8V_SP I

12

C2507

C2507
SCD1U10 V2KX-L1-GP

SCD1U10 V2KX-L1-GP

RTC_DET # (2 4)

R2506

R2506
22R2F-1-G P

22R2F-1-G P

PCH_SPI_S O(18)

PCH_SPI_C LK_FLASH(18)

PCH_SPI_S I_FLASH(18)PCH_SPI_C S0#_FLASH (18)

1 2

PCH_SPI_S O_FLASH

EC2503

EC2503

12

SC4D7P50V2CN-1GP

SC4D7P50V2CN-1GP

DY

DY

DY

DY

12

EC2502

EC2502

SC4D7P50V2CN-1GP

SC4D7P50V2CN-1GP

DY

DY

12

EC2501

EC2501

SC4D7P50V2CN-1GP

SC4D7P50V2CN-1GP

B B

SPI FLASH ROM (128k byte) for EC

3D3V_S5

SPI ROM Equal length need to less than 500mil

12

R2502

3D3V_S5

12

C2502

C2502

DY

SC10U6D 3V3MX-L-GP

SC10U6D 3V3MX-L-GP

A A

DY

12

C2501

C2501

SCD1U10 V2KX-L1-GP

SCD1U10 V2KX-L1-GP

EC_SPI_CS 0#_FLASH(24)

EC_SPI_SI(24)

R2502

3K3R2F-2 -GP

3K3R2F-2 -GP

1 2

R2501

R2501
33R2J-L1 -GP

33R2J-L1 -GP

12

R2503

R2503
10KR2J-3 -GP

10KR2J-3 -GP

EC_SPI_SO _FLASH
EC_SPI0_W P_0

U2501

U2501

1

CE#

2

SO

HOLD#

3

WP#

4

GND

PM25LD0 10C-SCE-GP

PM25LD0 10C-SCE-GP

VCC

SCK

3D3V_S5

8

EC_SPI0_H OLD_0

7
6
5

SIO

72.25010.N01

5

4

www.vinafix.vn

3

12

R2504

R2504
3K3R2F-2 -GP

3K3R2F-2 -GP

EC_SPI_CL K_FLASH (24)
EC_SPI_SI_FL ASH (24)

<Core Design>

<Core Design>

<Core Design>

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Title

Title

Size Document N umber Rev

Size Document N umber Rev

Size Document N umber Rev
A3

A3

A3

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

Flash(KBC+PCH)/RTC

Flash(KBC+PCH)/RTC

Flash(KBC+PCH)/RTC

Redwood 11.6"

Redwood 11.6"

Tuesday, April 01, 2014

Tuesday, April 01, 2014

Tuesday, April 01, 2014

Redwood 11.6"

Taipei Hsien 221, Taiwan, R.O.C.

25 102

25 102

25 102

1

A00

A00

A00

5

4

3

2

1

SSID = Thermal

D D

C C

Thermal sensor NCT 7718W

3D3V_S0

Layout notice :
Both DXN and DX P routing 10 m il
trace width and 10 mil spacin g.

Q2601

Q2601
LMBT390 4LT1G-GP

LMBT390 4LT1G-GP

84.T3904.H11

84.T3904.H11

2nd = 84.03904.E11

2nd = 84.03904.E11

DY

DY

12

R2604

R2604

C

NTC-100K-8-GP

NTC-100K-8-GP

B

E

2.System Sensor, Put on palm rest

P2800_D XP

12

C2604

C2604
SC470P5 0V3JN-2GP

SC470P5 0V3JN-2GP

P2800_D XN

12

C2605

C2605

SC2K2P50V2KX-L-GP

SC2K2P50V2KX-L-GP

THERM_S YS_SHDN#

20120809

C2601

C2601

SCD1U10V2KX-L1-GP

SCD1U10V2KX-L1-GP

12

C2602

C2602

12

SC10U6D3V3MX-L-GP

SC10U6D3V3MX-L-GP

1
2
3

U2601

U2601

NCT7718 W-GP

NCT7718 W-GP

74.07718.0B9

74.07718.0B9

NCT_CLK

NCT_DAT A

VDD
D+
D­T_CRIT#4GND

SCL

SDA

ALERT#

8
7
6
5

3D3V_S0

NCT_CLK
NCT_DAT A
ALERT#

1

23

RN2601

RN2601
SRN2K2J -5-GP

SRN2K2J -5-GP

4

Q2604

Q2604

1

2

3 4

DMN601D WK-7-1-GP

DMN601D WK-7-1-GP

75.00601.07C

75.00601.07C

*Layout* 15 mil

6

5

SML1_CL K (24,67)

SML1_DA TA (24,67)

Layout Note:

Signal Routing Guideline:
Trace width = 15mil

Fan controller1

R2611

R2611
0R2J-2-GP

0R2J-2-GP

1 2

DY

C2608

C2608

SC1U10V2KX-L1-GP

SC1U10V2KX-L1-GP

DY

FAN_VCC 1

12

5V_S0

FAN1_DA C_1(24)

Layout Note:

Need 10 mil tra ce width.

FAN_TAC H1(24)

FON#

R2610

R2610
0R0402-P AD

0R0402-P AD

1 2

KA

D2601

D2601

DY

DY

FAN261

FAN261

1

FSM#

2

VIN

3

VOUT
VSET4GND

APL5606 AKI-TRG-GP

APL5606 AKI-TRG-GP

74.05606.A71

74.05606.A71

2nd = 74.02113.0E1

2nd = 74.02113.0E1

12

C2603

C2603

RB551V30-1-GP

RB551V30-1-GP

SC2200P 50V2KX-2GP

SC2200P 50V2KX-2GP

DY

DY

GND
GND
GND

FAN_TAC H1_C

FAN_VCC 1

8
7
6
5

FAN1

FAN1

6
4
3
2

1

5

ACES-CON 4-29-GP

ACES-CON 4-29-GP

20.F1639.004

20.F1639.004

5V_S0

C2611

C2611

C2607

C2607

12

12

SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

X02

1.H/W T8 Shutdown

083.55130.008F

083.55130.008F

AFTP260 3AFTP26 03

1

3D3V_S0

3D3V_S0

12

R7

R2607 0R2J-2-GP

R2607 0R2J-2-GP

R2609 0R0402-PADR2609 0R0402-PAD

R2606

R2606
7K5R2F-1 -GP

7K5R2F-1 -GP

1 2

DY

DY

1 2

3D3V_S0

SYS_PW ROK (24,36)

B B

ALERT#

PURE_HW _SHUTDOW N#(24,36)

R5

12

R2605

R2605
7K5R2F-1 -GP

7K5R2F-1 -GP

DY

DY

12

C2606

C2606

SCD1U10V2KX-L1-GP

SCD1U10V2KX-L1-GP

Q2603

Q2603

D

2N7002K -2-GP

2N7002K -2-GP

84.2N702.J31

84.2N702.J31

2ND = 84.2N702.031

2ND = 84.2N702.031

3rd = 84.2N702.W31

3rd = 84.2N702.W31

THERM_S YS_SHDN#

S

SYS_PW ROK_G

G

FAN_TAC H1_C
FAN_VCC 1

AFTP260 1AFTP26 01

1

AFTP260 2AFTP26 02

1

T8=89 degree

Wistron Confidential document, Anyone can not
Duplicate, Modify, Forward or any other purpose

A A

5

4

www.vinafix.vn

3

2

application without get Wistron permission

<Core Design>

<Core Design>

<Core Design>

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Title

Title

Thermal 7718/Fan Controllor P2793

Thermal 7718/Fan Controllor P2793

Thermal 7718/Fan Controllor P2793

Size Document N umber Rev

Size Document N umber Rev

Size Document N umber Rev
A3

A3

A3

Tuesday, April 01, 2014

Tuesday, April 01, 2014

Tuesday, April 01, 2014

Date: Sheet of

Date: Sheet of

Date: Sheet of

Redwood 11.6"

Redwood 11.6"

Redwood 11.6"

Taipei Hsien 221, Taiwan, R.O.C.

26 102

26 102

26 102

1

A00

A00

A00

5

4

3

2

1

SSID = AUDIO

A00

EC2710 S CD1U50V2KX-1-G PEC2710 SC D1U50V2KX-1-GP

1 2

EC2711 S CD1U50V2KX-1-G PEC2711 SC D1U50V2KX-1-GP

D D

C2714

C2714

SC10U6D3V3MX-L-GP

SC10U6D3V3MX-L-GP

1 2

+3V_AVDD3D3V_S0

C2708

C2708

C2709

C2709

12

12

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP

Layout Note:

Close pin46

+3V_1D5V_AVDD

AUD_AGND

DVDD_1D5V

Close pin9

C2721

C2721

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

1 2

25mA for CPVDD & DVDD

12

C2701

C2701

SC4D7U6D3V 3KX-GP

SC4D7U6D3V 3KX-GP

Close pin36

12

C2715

C2715

SC4D7U6D3V 3KX-GP

SC4D7U6D3V 3KX-GP

Close pin40

SC1U10V2KX-L1- GP

SC1U10V2KX-L1- GP

AUD_AGND

AUD_AGND

AMP_MUTE#(24)

C2712 SC10U6D3V3MX-L- GPC2712 SC10U6D3V3MX-L-GP

AUD_SPK_L+(29)

AUD_SPK_L-( 29)

AUD_SPK_R-(29)

AUD_SPK_R+(29)

1 2

R2708

R2708
0R0402-PAD

0R0402-PAD

1 2

+3V_1D5V_AVDD

5V_S0

5V_S0

remove D2702 R2710 R2711 Add R2708_0R(PDB pin)

TP2702

TP2702
TPAD14-OP-G P

TPAD14-OP-G P

DMIC_CLK(52)

SC22P50V2JN-4G P

SC22P50V2JN-4G P

Close pin3

C2723

C2723

DY

DY

1 2

4

DMIC_DATA(52)

HDA_CODE C_SDOUT(19)

HDA_CODE C_BITCLK(19)

HDA_SDIN0(19)

HDA_CODE C_SYNC(19)

HDA_CODE C_RST#(19,29 )

LINE1_VREFO_R(29)

LINE1_VREFO_L(29)

AUD_HP1_JAC K_L(29)

AUD_HP1_JAC K_R(29)

12

C2703

C2703

CBP

LDO2_CAP

AUD_SPK_L+

AUD_SPK_L-

AUD_SPK_R-

AUD_SPK_R+

EAPD#

1

C2716

C2716

SC4D7U6D3V 3KX-GP

SC4D7U6D3V 3KX-GP

1 2

R2714 0R2J-2-GPR2714 0R2J-2-GP

1 2

R2716 0R2J-2-GPR2716 0R2J-2-GP

1 2

R2718 0R 0402-PADR 2718 0R0402- PAD

HDA27

HDA27

37

CBP

38

AVSS2

39

LDO2-CAP

40

AVDD2

41

PVDD1

42

SPK-OUT-L+

43

SPK-OUT-L-

44

SPK-OUT-R-

45

SPK-OUT-R+

46

PVDD2

47

PDB

48

SPDIF-OUT/GPIO2

49

GND

ALC3234-CG-G P

ALC3234-CG-G P

3D3V_S0

12

C2704

C2704
SC1U10V2KX-L1- GP

SC1U10V2KX-L1- GP

1 2

+3V_AVDD

CPVEE

CBN

31

32

33

34

35

36

CBN

CPVEE

CPVDD

HPOUT-L/PORT-I-L

HPOUT-R/PORT-I-R

71.03234.003

71.03234.003

DVDD1GPIO0/DMIC-DATA2GPIO1/DMIC-CLK3DVSS4SDATA-OUT5BCLK6LDO3-CAP7SDATA-IN8DVDD-IO9SYNC10RESET#11PCBEEP

12

C2717

C2717

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

DMIC_DATA_R

DMIC_CLK_R

HDA_CODE C_SDIN0

HDA_CODE C_SYNC

HDA_CODE C_RST#

3

C2705

C2705

C2702

C2702

SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP

12

SC2D2U6D3V2MX-GP

SC2D2U6D3V2MX-GP

12

AUD_VREF

LDO1_CAP

27

28

29

30

VREF

LDO1-CAP
LINE2_L/PORT-E-L

MIC2-VREFO

LINE2_R/PORT-E-R

LINE1-VREFO-L

LINE1-VREFO-R

LINE1_L/PORT-C-L

LINE1_R/PORT-C-R

MIC2_R/PORT-F-R/SLEEVE

MIC2_L/PORT-F-L/RING

SPDIFO/FRONT_JD/JD3/GPIO3

MIC2/LINE2_JD/JD2

HP/LINE1_JD/JD1

LDO3_CAP

C2718SC4D7U6D3V3KX-GP C2718SC4D7U6D3V 3KX-GP

12

12

C2719SCD1U10V2KX-5GP C2719SCD1U10V2KX-5GP

12

26

AVDD1

MONO-OUT

R2704

R2704
100KR2J-1-GP

100KR2J-1-GP

25

AVSS1

NC#20

MIC-CAP

12

AUD_PC_BEEP

DVDD_1D5V

MIC2_VREFO (29)

AUD_AGND

X01

+5V_AVDD

AUD_AGND

24

23

22

21

20

19

18

17

16

15

14

13

CPVREF

MIC_CAP

C2713 SC10U6D3V3MX-L- GPC2713 SC10U6D3V3MX-L-GP

JDREF

R2707 20KR2F-L-GP

R2707 20KR2F-L-GP

1 2

AUD_SENSE_A

1 2

Layout Note:

Place close to Pin 13

HDA_SPKR(16)
KBC_BEEP(24)

C2710

C2710

LINE1_L (29)

LINE1_R (29)

1 2

SLEEVE (29)

RING2 (29 )

DY

DY

R2709

R2709
200KR2J-L1-GP

200KR2J-L1-GP

A00

A00

12

12

C2711

C2711

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

AUD_AGND

SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP

A00

AUD_SENSECOMBO-GPI

5V_S0+5V_AVDD

1 2

R2703

R2703
0R0603-PAD

0R0603-PAD

Layout Note:

Place close to Pin 26

3D3V_S5

R2711

R2711
0R0402-PAD

0R0402-PAD

1 2

AUD_AGND

Layout Note:

Width>40mil, to improve
Headpohone Crosstalk noise

AUD_AGND

AUD_SENSE (29)

AUD_AGND

X01

X01

X01

D2701

RN2701

RN2701

2 3
1

SRN0J-6-GP

SRN0J-6-GP

2

HDA_SPKR_R

4

KBC_BEEP_R

D2701

1

AUD_PC_BEEP _C

3

2

BAT54C-7-F- 3-GP

BAT54C-7-F- 3-GP

75.00054.E7D

75.00054.E7D

2nd = 075.00054.0C7D

2nd = 075.00054.0C7D

3rd = 75.00054.A7D

3rd = 75.00054.A7D

C2720 SCD 1U10V2KX-5GPC2720 SCD1U10V2K X-5GP

12

R2717

R2717
1KR2J-1-GP

1KR2J-1-GP

<Core Desig n>

<Core Desig n>

<Core Desig n>

Title

Title

Title

Size Document Num ber Rev

Size Document Num ber Rev

Size Document Num ber Rev
A2

A2

A2

Tuesday, April 01, 2014

Tuesday, April 01, 2014

Tuesday, April 01, 2014
Date: Sheet of

Date: Sheet of

Date: Sheet of

1D5V_S0

R2701

R2701
0R0402-PAD

0R0402-PAD

1 2

3D3V_S0

1 2

DY

DY

R2712 0R2J-2-GP

R2712 0R2J-2-GP

A00

R2713

R2713
0R0402-PAD

0R0402-PAD

1 2

C C

5V_S0

1.5A

C2707

C2707

C2706

C2706

12

12

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP

Layout Note:

Close pin41

3D3V_S0

B B

A00

1D5V_S0

R2705

R2705
0R0402-PAD

0R0402-PAD

1 2

R2710 0R2J-2-GP

R2710 0R2J-2-GP

1 2

DY

DY

Add R2710 DY(3D3V_S0)

Azalia I/F EMI

HDA_CODE C_SDOUT

EC2708

EC2708

12

DY

DY

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

A A

HDA_CODE C_BITCLK

EC2709

EC2709

12

DY

DY

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

5

1 2

EC2712 S CD1U50V2KX-1-G PEC2712 SC D1U50V2KX-1-GP

1 2

EC2713 S CD1U50V2KX-1-G PEC2713 SC D1U50V2KX-1-GP

1 2

EC2707 S CD1U50V2KX-1-G P

EC2707 S CD1U50V2KX-1-G P

1 2

DY

DY

EC2706 S CD1U50V2KX-1-G P

EC2706 S CD1U50V2KX-1-G P

1 2

DY

DY

EC2705 S CD1U50V2KX-1-G PEC2705 SC D1U50V2KX-1-GP

1 2

EC2704 S CD1U50V2KX-1-G PEC2704 SC D1U50V2KX-1-GP

1 2

EC2703 S CD1U50V2KX-1-G PEC2703 SC D1U50V2KX-1-GP

1 2

A00

1 2

R2706

R2706
0R0603-PAD

0R0603-PAD

Layout Note:

AUD_AGND

Tied at point only under
Codec or near the Codec

3D3V_S0

12

R2702

R2702
100KR2J-1-GP

100KR2J-1-GP

AUD_SENSE_A

AUD_PC_BEEP

1 2

Wistron Confidential document, Anyone can not Duplicate, Modify,
Forward or any other purpose application without get Wistron
permission

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin T ai Wu Rd., H sichih,

21F, 88, Sec.1, Hsin T ai Wu Rd., H sichih,

21F, 88, Sec.1, Hsin T ai Wu Rd., H sichih,
Taipei Hsie n 221, Taiwan, R.O.C.

Taipei Hsie n 221, Taiwan, R.O.C.

Taipei Hsie n 221, Taiwan, R.O.C.

Audio Codec_ALC3225

Audio Codec_ALC3225

Audio Codec_ALC3225

Redwood 11.6"

Redwood 11.6"

Redwood 11.6"

1

27 102

27 102

27 102

A00

A00

A00

www.vinafix.vn

5

D D

C C

4

3

2

1

Blanking

B B

Wistron Confidential document, Anyone can not
Duplicate, Modify, Forward or any other purpose
application without get Wistron permission

<Core Design>

<Core Design>

<Core Design>

Wistron Corporation

Wistron Corporation

A A

Title

Title

Title

Reserved

Reserved

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev
A4

A4

A4

Tuesday, April 01, 2014

Tuesday, April 01, 2014

Tuesday, April 01, 2014

Date: Sheet of

Date: Sheet of

5

4

www.vinafix.vn

3

Date: Sheet of

2

Reserved

Redwood 11.6"

Redwood 11.6"

Redwood 11.6"

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

A00

A00

28 102

28 102

28 102

1

A00

5

4

3

2

1

SSID = AUDIO

Speaker

SPK1

SPK1

R2904 0R0603-P ADR2904 0R0603 -PAD

D D

AUD_SPK _R+(27)

AUD_SPK _R-(27)
AUD_SPK _L+(27)
AUD_SPK _L-(27 )

12

12

DY

DY

DY

DY

EC2901

EC2901

SC2200P50V2KX-2GP

SC2200P50V2KX-2GP

SC2200P50V2KX-2GP

SC2200P50V2KX-2GP

DY

DY

EC2902

EC2902

EC2903

EC2903

SC2200P50V2KX-2GP

SC2200P50V2KX-2GP

12

12

DY

DY

EC2904

EC2904

SC2200P50V2KX-2GP

SC2200P50V2KX-2GP

1 2

R2903 0R0603-P ADR2903 0R0603 -PAD

1 2

R2902 0R0603-P ADR2902 0R0603 -PAD

1 2

R2901 0R0603-P ADR2901 0R0603 -PAD

1 2

AUD_SPK _R+_C

AUD_SPK _R-_C
AUD_SPK _L+_C
AUD_SPK _L-_C

2nd = 20.F1804.004

2nd = 20.F1804.004

AUD_SPK _L-_C
AUD_SPK _L+_C
AUD_SPK _R-_C
AUD_SPK _R+_C

5

1

2
3
4

6

ACES-CON 4-29-GP

ACES-CON 4-29-GP

20.F1639.004

20.F1639.004

CONN Pin

Pin1

Pin2

Pin3

Pin4

AFTP290 1AFTP29 01

1

AFTP290 2AFTP29 02

1

AFTP290 3AFTP29 03

1

AFTP290 4AFTP29 04

1

Net name

SPK_R+

SPK_R-

SPK_L+

SPK_L_

C C

RN2901

RN2901

MIC2_VREF O(27)

RING2(27)

AUD_HP1 _JACK_L(27)

LINE1_L(27)

LINE1_VRE FO_L(27)

AUD_HP1 _JACK_R(27)

LINE1_R(27)

LINE1_VRE FO_R(27)

SLEEVE(27)

B B

ED2901

AZ2025-01H-R7G-GPDYED2901

AZ2025-01H-R7G-GP

12

DY

A A

DY

ED2902

AZ2025-01H-R7G-GPDYED2902

AZ2025-01H-R7G-GP

12

C2907

C2907

1 2

SC4D7U6 D3V3KX-GP

SC4D7U6 D3V3KX-GP

C2908

C2908

1 2

SC4D7U6 D3V3KX-GP

SC4D7U6 D3V3KX-GP

DY

5

2 3
1

LINE1-L_C

LINE1-L_R

ED2903

AZ2025-01H-R7G-GPDYED2903

AZ2025-01H-R7G-GP

12

DY

4

SRN2K2J -5-GP

SRN2K2J -5-GP

R2908 10R2F-L-G PR2908 10R2F-L-G P

1 2

R2922 1KR2J-1-G PR2922 1KR2J-1-G P

1 2

R2912 2K2R2J-2 -GPR2912 2K2R2J-2 -GP

1 2

R2910 10R2F-L-G PR2910 10R2F-L-G P

1 2

R2921 1KR2J-1-G PR2921 1KR2J-1-G P

1 2

R2913 2K2R2J-2 -GPR2913 2K2R2J-2 -GP

1 2

AUD_POR TA_R_R_B
AUD_POR TA_L_R_B
RING2_R
AUD_SEN SE
SLEEVE_ R

ED2904

AZ2025-01H-R7G-GPDYED2904

AZ2025-01H-R7G-GP

ED2905

AZ2025-01H-R7G-GPDYED2905

12

AZ2025-01H-R7G-GP

12

DY

AUD_HP1 _JACK_L1

AUD_HP1 _JACK_R1

SC100P50V2JN-3GPDYEC2908

SC100P50V2JN-3GP

R2920

10KR2J-3-GP

R2920

10KR2J-3-GP

12

5V_PW R_2

4

SC100P50V2JN-3GPDYEC2906

EC2907

SC100P50V2JN-3GPDYEC2907

SC100P50V2JN-3GP

EC2908

12

12

DY

DY

AUD_AGN D AUD_AGND

12

R2915

R2915
470KR2J -2-GP

470KR2J -2-GP

DY

DY

AUD_AGN D

SLEEVE_ CTRL

84.2N702.A3F

84.2N702.A3F

2nd = 84.DM601.03F

2nd = 84.DM601.03F

3rd = 84.2N702.E3F

3rd = 84.2N702.E3F

4th = 84.2N702.F3F

4th = 84.2N702.F3F

SC100P50V2JN-3GP

R2919

10KR2J-3-GP

R2919

10KR2J-3-GP

12

S

D

www.vinafix.vn

EC2906

EC2905

SC100P50V2JN-3GPDYEC2905

SC100P50V2JN-3GP

12

DY

U2901

U2901

5

DY

DY

6

2N7002K DW-GP

2N7002K DW-GP

DY

A00

R2906 0R0603-P ADR2906 0R0603 -PAD
R2907 0R3J-6-GPR2907 0R3J-6-GP

3D3V_S0

R2909 0R3J-6-GPR2909 0R3J-6-GP
R2911 0R0603-P ADR2911 0R0603 -PAD

A00

12

D

34

GG

HDA_COD EC_RST#_CTRL

2

S

1

1 2
1 2

Delay

Delay

R2916 10KR2J-3 -GP

R2916 10KR2J-3 -GP

1 2

1 2
1 2

3D3V_S0

12

R2918

R2918

100KR2J -1-GP

100KR2J -1-GP

DY

DY

SLEEVE (27)

12

DY

DY

3

RING2_R
AUD_POR TA_L_R_B

JACK_PO WER
JACK_PL UG
AUD_POR TA_R_R_B
SLEEVE_ R

R2923

R2923
0R3J-6-GP

0R3J-6-GP

1 2

DY

DY

C2901

C2901
SC1U6D3 V2KX-L-1-GP

SC1U6D3 V2KX-L-1-GP

Combo Jack

MS

AUD_AGN D

HDA_COD EC_RST# (19,27)

HPMIC1

HPMIC1

3
1

5
6
2
4

Audio(IP/NK comb)

Audio(IP/NK comb)

AUDIO-JK44 3-GP

AUDIO-JK44 3-GP

022.10002.0141

022.10002.0141

R2917

R2917
10KR2J-3 -GP

10KR2J-3 -GP

Non-Delay

Non-Delay

1 2

AUD_AGN D

Delay circuit

JACK_PL UG

R2905

R2905

100KR2J -1-GP

100KR2J -1-GP

AUD_AGN D

2

JACK_PO WER

AUD_POR TA_L_R_B

AUD_AGN D

12

Delay

Delay

C2902

C2902

SC10U6D3V3MX-L-GP

SC10U6D3V3MX-L-GP

Delay

Delay

1 2

AUD_AGN D

1 2

DY

DY

R2914

R2914
0R3J-6-GP

0R3J-6-GP

Wistron Confidential document, Anyone can not Duplicate, Modify,
Forward or any other purpose application without get Wistron
permission

<Core Design>

<Core Design>

<Core Design>

Title

Title

Title

Audio Jack

Audio Jack

Size Document N umber Rev

Size Document N umber Rev

Size Document N umber Rev
Custom

Custom

Custom

Tuesday, April 01, 2014

Tuesday, April 01, 2014

Tuesday, April 01, 2014

Date: Sheet of

Date: Sheet of

Date: Sheet of

Audio Jack

Redwood 11.6"

Redwood 11.6"

Redwood 11.6"

AUD_POR TA_R_R_B

AUD_SEN SE

Delay

Delay

G

S

D

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

1

1
1
1
1

AUD_AGN D

Q2901

Q2901
2N7002K -2-GP

2N7002K -2-GP

84.2N702.J31

84.2N702.J31

2nd = 84.2N702.W31

2nd = 84.2N702.W31

3rd = 84.07002.I31

3rd = 84.07002.I31

AUD_SEN SE (2 7)

29 102

29 102

29 102

AFTP290 6AFTP29 06
AFTP290 7AFTP29 07
AFTP290 8AFTP29 08
AFTP290 9AFTP29 09

A00

A00

A00

5

D D

C C

4

3

2

1

Blanking

B B

<Core Design>

<Core Design>

<Core Design>

Wistron Corporation

Wistron Corporation

A A

Title

Title

Title

Reserved

Reserved

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev
A4

A4

A4

Date: Sheet of

Date: Sheet of

5

4

www.vinafix.vn

3

Date: Sheet of

Reserved

Tuesday, April 01, 2014

Tuesday, April 01, 2014

Tuesday, April 01, 2014

2

Redwood 11.6"

Redwood 11.6"

Redwood 11.6"

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

A00

A00

30 102

30 102

30 102

1

A00