Datasheet XR16L2752 Datasheet (EXAR)

Page 1

查询XR16L2752供应商

AUGUST 2004 REV. 1.2.0

GENERAL DESCRIPTION

The XR16L27521 (2752) is a low voltage dual universal asynchronous receiver and transmitter (UART) with 5 Volt tolerant inputs. The device operates from 2.25 to 5.5 Volt supply range and is pin-to-pin compatible to Exar’s ST16C2552 and XR16C2852. The 2752 register set is compatible to the ST16C2552 and the XR16C2852 enhanced features. It supports the Exar’s enhanced features of 64 bytes of TX and RX FIFOs, programmable FIFO trigger level and FIFO level counters, automatic hardware (RTS/CTS) and software flow control, automatic RS-485 half duplex direction control output and a complete modem interface. Onboard registers provide the user with operational status and data error flags. An internal loopback capability allows system diagnostics. Independent programmable baud rate generators are provided in each channel to select data rates up to 6.25 Mbps at 5 Volt and 8X sampling. The 2752 is available in the 44-pin PLCC package.

OTE

1 Covered by U.S. Patent #5,649,122 and #5,949,787

APPLICATIONS

Portable Appliances

•

Telecommunication Network Routers

•

Ethernet Network Routers

•

Cellular Data Devices

•

Factory Automation and Process Controls

•

XR16L2752

2.25V TO 5.5V DUART WITH 64-BYTE FIFO

FEATURES

•

2.25 to 5.5 Volt Operation

•

5 Volt Tolerant Inputs

Pin-to-pin compatible to Exar’s ST16C2552 and

•

XR16C2852

• Larger FIFO version of PC16C552

Two independent UART channels

•

Reg set compatible to 16C2552 and 16C2852

■

Up to 6.25 Mbps at 5 Volt, 4 Mbps at 3.3 Volt

■

and 3 Mbps at 2.5 Volt with 8X sampling rate Transmit and Receive FIFOs of 64 bytes

■

Programmable TX and RX FIFO Trigger Levels

■

Transmit and Receive FIFO Level Counters

■

Automatic Hardware (RTS/CTS) Flow Control

■

Selectable Auto RTS Flow Control Hysteresis

■

Automatic Software (Xon/Xoff) Flow Control

■

Automatic RS-485 Half-duplex Direction

■

Control Output via RTS# Wireless Infrared (IrDA 1.0) Encoder/Decoder

■

Automatic sleep mode

■

Full modem interface

■

Alternate Function Register

•

Device Identification and Revision

•

Crystal oscillator or external clock input

•

Industrial and commercial temperature ranges

•

44-PLCC package

•

IGURE 1. XR16L2752 BLOCK DIAGRAM

A2:A0

D7:D0

IOR#

IOW#

CS#

CHSEL

INTA

INTB TXRDYA# TXRDYB#

MFA#

(OP2A#,

BAUDOUTA#, or

RXRDYA#)

MFB#

(OP2B#,

BAUDOUTB#, or

RXRDYB#)

Reset

Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com

Exar

8-bit Data

Bus

Interface

*5 Volt Tolerant Inputs

(Except External Clock Input)

UART Channel A

64 Byte TX FIFO

UART

Regs

TX & RX

BRG

64 Byte RX FIFO

UART Channel B

(same as Channel A)

Crystal Osc/Buffer

Modem Control Logic

ENDEC

2.25 V to 5.5 V VCC GND

TXA (or TXIRA)

RXA (or RXIRA)

TXB (or TXIRB)

RXB (or RXIRB)

XTAL1 XTAL2

CTS#A/B, RI#A/B, CD#A/B, DSR#A/B

DTR#A/B, RTS#A/B

2752BLK

Page 2

XR16L2752

2.25V TO 5.5V DUART WITH 64-BYTE FIFO

FIGURE 2. PIN OUT ASSIGNMENT

XTAL1

GND

XTAL2

INTB

CHSEL

XR16L2752

44-pin PLCC

REV. 1.2.0

TXRDYA#

VCC

RIA#

CDA#

DSRA#

CTSA#

RXA

TXA

DTRA#

RTSA#

MFA#

INTA

VCC

TXRDYB#

RIB#

CDB#

DSRB#

CS#

IOW#

MFB#

RESET

GND

RTSB#

IOR#

TXB

RXB

CTSB#

DTRB#

ORDERING INFORMATION

ART NUMBER

XR16L2752CJ 44-Lead PLCC 0°C to +70°C Active

XR16L2752IJ 44-Lead PLCC -40°C to +85°C Active

ACKAGE

PERATING TEMPERATURE RANGE

EVICE STATUS

Page 3

REV. 1.2.0

PIN DESCRIPTIONS

Pin Description

XR16L2752

2.25V TO 5.5V DUART WITH 64-BYTE FIFO

AME

DATA BUS INTERFACE

A2 A1 A0

D7 D6 D5 D4 D3 D2 D1 D0

IOR# 24 I Input/Output Read Strobe (active low). The falling edge instigates an internal read

IOW# 20 I Input/Output Write Strobe (active low). The falling edge instigates an internal write

CS# 18 I UART chip select (active low). This function selects channel A or B in accordance

CHSEL 16 I Channel Select - UART channel A or B is selected by the logical state of this pin when

INTA 34 O UART channel A Interrupt output (active high). A logic high indicates channel A is

INTB 17 O UART channel B Interrupt output (active high). A logic high indicates channel B is

TXRDYA# 1 O

44-PLCC

15 14 10

9 8 7 6 5 4 3 2

YPE

I Address data lines [2:0]. These 3 address lines select one of the internal registers in

UART channel A/B during a data bus transaction.

I/O Data bus lines [7:0] (bidirectional).

cycle and retrieves the data byte from an internal register pointed to by the address lines [A2:A0]. The data byte is placed on the data bus to allow the host processor to read it on the rising edge.

cycle and the rising edge transfers the data byte on the data bus to an internal register pointed by the address lines.

with the logical state of the CHSEL pin. This allows data to be transferred between the user CPU and the 2752.

the CS# pin is a logic 0. A logic 0 on the CHSEL selects the UART channel B while a logic 1 selects UART channel A. Normally, CHSEL could just be an address line from the user CPU such as A4. Bit-0 of the Alternate Function Register (AFR) can temporarily override CHSEL function, allowing the user to write to both channel register simultaneously with one write cycle when CS# is low. It is especially useful during the initialization routine.

requesting for service. For more details, see

ESCRIPTION

Figures 18- 23

UART channel A Transmitter Ready (active low). The output provides the TX FIFO/THR status for transmit channel A. See Table 2 on page 8.

TXRDYB# 32 O UART channel B Transmitter Ready (active low). The output provides the TX FIFO/

THR status for transmit channel B.

MODEM OR SERIAL I/O INTERFACE

TXA 38 O

UART channel A Transmit Data or infrared encoder data. Standard transmit and receive interface is enabled when MCR[6] = 0. In this mode, the TX signal will be HIGH during reset or idle (no data). Infrared IrDA transmit and receive interface is enabled when MCR[6] = 1. In the Infrared mode, the inactive state (no data) for the Infrared encoder/decoder interface is LOW. If it is not used, leave it unconnected.

See Table 2 on page 8.

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XR16L2752

2.25V TO 5.5V DUART WITH 64-BYTE FIFO

Pin Description

REV. 1.2.0

AME

RXA 39 I

RTSA# 36 O UART channel A Request-to-Send (active low) or general purpose output. This output

CTSA# 40 I UART channel A Clear-to-Send (active low) or general purpose input. It can be used

DTRA# 37 O UART channel A Data-Terminal-Ready (active low) or general purpose output. If this

DSRA# 41 I UART channel A Data-Set-Ready (active low) or general purpose input. This input

CDA# 42 I

RIA# 43 I

MFA# 35 O Multi-Function Output Channel A. This output pin can function as the OP2A#, BAUD-

44-PLCC

PIN #

YPE

UART channel A Receive Data or infrared receive data. Normal receive data input must idle HIGH. The infrared receiver pulses typically idles LOW but can be inverted by software control prior going in to the decoder, see MCR[6] and FCTR[2]. If this pin is not used, tie it to VCC or pull it high via a 100k ohm resistor.

must be asserted prior to using auto RTS flow control, see EFR[6], MCR[1], FCTR[1:0], EMSR[5:4] and IER[6]. For auto RS485 half-duplex direction control, see FCTR[3] and EMSR[3].

for auto CTS flow control, see EFR[7], and IER[7]. This input should be connected to VCC when not used.

pin is not used, leave it unconnected.

should be connected to VCC when not used. This input has no effect on the UART.

UART channel A Carrier-Detect (active low) or general purpose input. This input should be connected to VCC when not used. This input has no effect on the UART.

UART channel A Ring-Indicator (active low) or general purpose input. This input should be connected to VCC when not used. This input has no effect on the UART.

OUTA#, or RXRDYA# pin. One of these output signal functions can be selected by the user programmable bits 1-2 of the Alternate Function Register (AFR). These signal functions are described as follows:

ESCRIPTION

1) OP2A# - When OP2A# (active low) is selected, the MF# pin is LOW when MCR bit3 is set to a logic 1 (see MCR bit-3). MCR bit-3 defaults to a logic 1 condition after a reset or power-up.

2) BAUDOUTA# - When BAUDOUTA# function is selected, the 16X Baud rate clock output is available at this pin.

3) RXRDYA# - RXRDYA# (active low) is intended for monitoring DMA data transfers.

Table 2 on page 8

See

TXB 26 O

RXB 25 I

RTSB# 23 O UART channel B Request-to-Send (active low) or general purpose output. This port

UART channel B Transmit Data or infrared encoder data. Standard transmit and receive interface is enabled when MCR[6] = 0. In this mode, the TX signal will be HIGH during reset or idle (no data). Infrared IrDA transmit and receive interface is enabled when MCR[6] = 1. In the Infrared mode, the inactive state (no data) for the Infrared encoder/decoder interface is LOW. If it is not used, leave it unconnected.

UART channel B Receive Data or infrared receive data. Normal receive data input must idle HIGH. The infrared receiver pulses typically idles LOW but can be inverted by software control prior going in to the decoder, see MCR[6] and FCTR[2]. If this pin is not used, tie it to VCC or pull it high via a 100k ohm resistor.

must be asserted prior to using auto RTS flow control, see EFR[6], MCR[1], FCTR[1:0], EMSR[5:4] and IER[6]. For auto RS485 half-duplex direction control, see FCTR[3] and EMSR[3].

for more details.

Page 5

REV. 1.2.0

Pin Description

XR16L2752

2.25V TO 5.5V DUART WITH 64-BYTE FIFO

AME

CTSB# 28 I UART channel B Clear-to-Send (active low) or general purpose input. It can be used

DTRB# 27 O UART channel B Data-Terminal-Ready (active low) or general purpose output. If this

DSRB# 29 I UART channel B Data-Set-Ready (active low) or general purpose input. This input

CDB# 30 I

RIB# 31 I

MFB# 19 O Multi-Function Output Channel B. This output pin can function as the OP2B#, BAUD-

44-PLCC

PIN #

YPE

for auto CTS flow control, see EFR[7], and IER[7]. This input should be connected to VCC when not used.

pin is not used, leave it unconnected.

should be connected to VCC when not used. This input has no effect on the UART.

UART channel B Carrier-Detect (active low) or general purpose input. This input should be connected to VCC when not used. This input has no effect on the UART.

UART channel B Ring-Indicator (active low) or general purpose input. This input should be connected to VCC when not used. This input has no effect on the UART.

OUTB#, or RXRDYB# pin. One of these output signal functions can be selected by the user programmable bits 1-2 of the Alternate Function Register (AFR). These signal functions are described as follows:

1) OP2B# - When OP2B# (active low) is selected, the MF# pin is LOW when MCR bit3 is set HIGH (see MCR bit-3). MCR bit-3 defaults to a logic 1 condition after a reset or power-up.

2) BAUDOUTB# - When BAUDOUTB# function is selected, the 16X Baud rate clock output is available at this pin.

ESCRIPTION

3) RXRDYB# - RXRDYB# (active low) is intended for monitoring DMA data transfers.

Table 2 on page 8

See

ANCILLARY SIGNALS

XTAL1 11 I Crystal or external clock input. Caution: this input is not 5V tolerant.

XTAL2 13 O Crystal or buffered clock output.

RESET 21 I Reset (active high) - A longer than 40 ns HIGH pulse on this pin will reset the internal

registers and all outputs. The UART transmitter output will be held HIGH, the receiver input will be ignored and outputs are reset during reset period (see External Reset Conditions).

VCC 44, 33 Pwr 2.25 to 5.5V power supply. All input pins, except XTAL1, are 5V tolerant.

GND 22, 12 Pwr Power supply common, ground.

for more details.

Pin type: I=Input, O=Output, I/O= Input/output, OD=Output Open Drain.

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XR16L2752

2.25V TO 5.5V DUART WITH 64-BYTE FIFO

1.0 PRODUCT DESCRIPTION

The XR16L2752 (2752) integrates the functions of 2 enhanced 16C550 Universal Asynchronous Receiver and Transmitter (UART). Each UART is independently controlled having its own set of device configuration registers. The configuration registers set is 16550 UART compatible for control, status and data transfer. Additionally, each UART channel has 64-bytes of transmit and receive FIFOs, automatic RTS/CTS hardware flow control with hysteresis control, automatic Xon/Xoff and special character software flow control, programmable transmit and receive FIFO trigger levels, FIFO level counters, infrared encoder and decoder (IrDA ver 1.0), programmable baud rate generator with a prescaler of divide by 1 or 4, and data rate up to 6.25 Mbps with 8X sampling clock rate or 3.125 Mbps in the 16X rate. The XR16L2752 is a 2.25 to 5.5V device with 5 volt tolerant inputs. The 2752 is fabricated with an advanced CMOS process.

Enhanced Features

The 2752 DUART provides a solution that supports 64 bytes of transmit and receive FIFO memory, instead of 128 bytes provided in the XR16C2852 and 16 bytes in the ST16C2552. The 2752 is designed to work with low supply voltage and high performance data communication systems, that require fast data processing time. Increased performance is realized in the 2752 by the larger transmit and receive FIFOs, FIFO trigger level control, FIFO level counters and automatic flow control mechanism. This allows the external processor to handle more networking tasks within a given time. For example, the ST16C2552 with a 16 byte FIFO, unloads 16 bytes of receive data in 1.53 ms (This example uses a character length of 11 bits, including start/stop bits at

115.2 Kbps). This means the external CPU will have to service the receive FIFO at 1.53 ms intervals. However with the 64 byte FIFO in the 2752, the data buffer will not require unloading/loading for 6.1 ms. This increases the service interval giving the external CPU additional time for other applications and reducing the overall UART interrupt servicing time. In addition, the programmable FIFO level trigger interrupt and automatic hardware/software flow control is uniquely provided for maximum data throughput performance especially when operating in a multi-channel system. The combination of the above greatly reduces the CPU’s bandwidth requirement, increases performance, and reduces power consumption.

The 2752 supports a half-duplex output direction control signaling pin, RTS# A/B, to enable and disable the external RS-485 transceiver operation. It automatically switches the logic state of the output pin to the receive state after the last stop-bit of the last character has been shifted out of the transmitter. After receiving, the logic state of the output pin switches back to the transmit state when a data byte is loaded in the transmitter. The auto RS-485 direction control pin is not activated after reset. To activate the direction control function, user has to set FCTR Bit-3 to “1”. This pin is normally high for receive state, low for transmit state.

Data Rate

The 2752 is capable of operation up to 3.125 Mbps at 5V with 16X internal sampling clock rate, and 6.25 Mbps at 5V with 8X sampling clock rate. The device can operate with an external 24 MHz crystal on pins XTAL1 and XTAL2, or external clock source of up to 50 MHz on XTAL1 pin. With a typical crystal of 14.7456 MHz and through a software option, the user can set the prescaler bit for data rates of up to 1.84 Mbps.

The rich feature set of the 2752 is available through the internal registers. Automatic hardware/software flow control, selectable transmit and receive FIFO trigger levels, selectable TX and RX baud rates, infrared encoder/decoder interface, modem interface controls, and a sleep mode are all standard features.

Following a power on reset or an external reset, the 2752 is software compatible with previous generation of UARTs 16C2552 and 16C2852.

REV. 1.2.0

Page 7

REV. 1.2.0

XR16L2752

2.25V TO 5.5V DUART WITH 64-BYTE FIFO

2.0 FUNCTIONAL DESCRIPTIONS

2.1 CPU Interface

The CPU interface is 8 data bits wide with 3 address lines and control signals to execute data bus read and write transactions. The 2752 data interface supports the Intel compatible types of CPUs and it is compatible to the industry standard 16C550 UART. No clock (oscillator nor external clock) is required to operate a data bus transaction. Each bus cycle is asynchronous using CS#, IOR# and IOW# signals. Both UART channels share the same data bus for host operations. The data bus interconnections are shown in Figure 3

IGURE 3. XR16L2750 DATA BUS INTERCONNECTIONS

D0 D1 D2 D3 D4 D5 D6 D7

A0 A1 A2

IOR #

IOW #

UART_CS#

UART_CHSEL

UART_INTA

UART_INTB

TXRDYA#

(RXRDYA#)

TXRDYB#

(RXRDYB#)

UART_RESET RESET

Pins in parentheses become available through the MF# pin. MF# A/B becomes RXRDY# A/B when AFR[2:1] = '10'. MF# A/B becomes OP2# A/B when AFR[2:1] = '00'. MF# A/B becomes BAUDOUT# A/B when AFR[1:0] = '01'.

D0 D1 D2 D3 D4 D5 D6 D7

A0 A1

IOR #

IOW #

CS#

CHSEL

INT A

INT B

TXRDYA#

(RXRDYA#)

TXRDYB#

(RXRDYB#)

UART

Channel A

UART

Channel B

VCC

TXA

RXA

DTRA# RTSA#

CTSA#

DSRA#

CDA#

RIA#

(O P2A #)

(BAUDOUTA#)

TXB

RXB

DTRB#

RTSB#

CTSB#

DSRB#

CDB#

RIB#

(O P2B #)

(BAUDOUTB#)

GND

VCC

Serial Interface of

RS-232, RS-485

Serial Interface of

RS-232, RS-485

2750int

2.2 5-Volt Tolerant Inputs

The 2752 can accept up to 5V inputs even when operating at 3.3V or 2.5V. But note that if the 2752 is operating at 2.5V, its V

may not be high enough to meet the requirements of the VIH of a CPU or a serial

transceiver that is operating at 5V. Caution: XTAL1 is not 5 volt tolerant.

2.3 Device Reset

The RESET input resets the internal registers and the serial interface outputs in both channels to their default state (see Table 16 on page 38). An active high pulse of longer than 40 ns duration will be required to activate the reset function in the device.

2.4 Device Identification and Revision

The XR16L2752 provides a Device Identification code and a Device Revision code to distinguish the part from other devices and revisions. To read the identification code from the part, it is required to set the baud rate generator registers DLL and DLM both to 0x00. Now reading the content of the DLM will provide 0x0A for the XR16L2752 and reading the content of DLL will provide the revision of the part; for example, a reading of 0x01 means revision A.

2.5 Channel A and B Selection

The UART provides the user with the capability to bi-directionally transfer information between an external CPU and an external serial communication device. A logic 0 on chip select pin (CS#) allows the user to select the UART and then using the channel select (CHSEL) pin, the user can select channel A or B to configure, send transmit data and/or unload receive data to/from the UART. Individual channel select functions are shown in Ta bl e 1 .

Page 8

XR16L2752

2.25V TO 5.5V DUART WITH 64-BYTE FIFO

ABLE 1: CHANNEL A AND B SELECT

REV. 1.2.0

CS# CHSEL F

1 X UART de-selected

0 1 Channel A selected

0 0 Channel B selected

UNCTION

2.6 Channel A and B Internal Registers

Each UART channel in the 2752 has a set of enhanced registers for control, monitoring and data loading and unloading. The configuration register set is compatible to those already available in the standard single 16C550 and dual ST16C2550. These registers function as data holding registers (THR/RHR), interrupt status and control registers (ISR/IER), a FIFO control register (FCR), receive line status and control registers (LSR/ LCR), modem status and control registers (MSR/MCR), programmable data rate (clock) divisor registers (DLL/ DLM), and a user accessible Scratchpad Register (SPR).

Beyond the general 16C2550 features and capabilities, the 2752 offers enhanced feature registers (AFR, EMSR, FLVL, EFR, Xon/Xoff 1, Xon/Xoff 2, FCTR, TRG, FC) that provide automatic RTS and CTS hardware flow control, Xon/Xoff software flow control, automatic RS-485 half-duplex direction output enable/disable, FIFO trigger level control, FIFO level counters, and simultaneous writes to both channels. All the register functions are discussed in full detail later in “Section 3.0, UART INTERNAL REGISTERS” on page 20.

2.7 Simultaneous Write to Channel A and B

During a write mode cycle, the setting of Alternate Function Register (AFR) bit-0 to a logic 1 will override the CHSEL selection and allows a simultaneous write to both UART channel sections. This functional capability allow the registers in both UART channels to be modified concurrently, saving individual channel initialization time. Caution should be considered, however, when using this capability. Any in-process serial data transfer may be disrupted by changing an active channel’s mode.

2.8 DMA Mode

The device does not support direct memory access. The DMA Mode (a legacy term) in this document doesn’t mean “direct memory access” but refers to data block transfer operation. The DMA mode affects the state of the RXRDY# A/B (MF# A/B becomes RXRDY# A/B output when AFR[2:1] = ‘10’) and TXRDY# A/B output pins. The transmit and receive FIFO trigger levels provide additional flexibility to the user for block mode operation. The LSR bits 5-6 provide an indication when the transmitter is empty or has an empty location(s) for more data. The user can optionally operate the transmit and receive FIFO in the DMA mode (FCR bit-3=1). When the transmit and receive FIFO are enabled and the DMA mode is disabled (FCR bit-3 = 0), the 2752 is placed in single-character mode for data transmit or receive operation. When DMA mode is enabled (FCR bit3 = 1), the user takes advantage of block mode operation by loading or unloading the FIFO in a block sequence determined by the programmed trigger level. In this mode, the 2752 sets the TXRDY# pin when the transmit FIFO becomes full, and sets the RXRDY# pin when the receive FIFO becomes empty. The following table shows their behavior. Also see Figures 18 through 23.

TABLE 2: TXRDY# AND RXRDY# OUTPUTS IN FIFO AND DMA MODE

INS

RXRDY# A/B LOW = 1 byte.

TXRDY# A/B LOW = THR empty.

FCR

(FIFO D

HIGH = no data.

HIGH = byte in THR.

-0=0

BIT

ISABLED

)

FCR Bit-3 = 0

(DMA Mode Disabled)

LOW = at least 1 byte in FIFO. HIGH = FIFO empty.

LOW = FIFO empty. HIGH = at least 1 byte in FIFO.

FCR BIT-0=1 (FIFO E

HIGH to LOW transition when FIFO reaches the trigger level, or time-out occurs.

LOW to HIGH transition when FIFO empties.

LOW = FIFO has at least 1 empty location. HIGH = FIFO is full.

)

NABLED

FCR Bit-3 = 1

(DMA Mode Enabled)

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REV. 1.2.0

XR16L2752

2.25V TO 5.5V DUART WITH 64-BYTE FIFO

2.9 INTA and INTB Outputs

The INTA and INTB interrupt output changes according to the operating mode and enhanced features setup.

Ta bl e 3 and 4 summarize the operating behavior for the transmitter and receiver. Also see Figures 18

through 23.

ABLE 3: INTA AND INTB PINS OPERATION FOR TRANSMITTER

Auto RS485

Mode

INTA/B Pin NO LOW = a byte in THR

INTA/B Pin YES LOW = a byte in THR

FCR B

(FIFO D

HIGH = THR empty

HIGH = transmitter empty

-0 = 0

ISABLED

)

LOW = FIFO above trigger level HIGH = FIFO below trigger level or FIFO empty

LOW = FIFO above trigger level HIGH = FIFO below trigger level or transmitter empty

FCR BIT-0 = 1 (FIFO E

NABLED

)

TABLE 4: INTA AND INTB PIN OPERATION FOR RECEIVER

FCR BIT-0 = 0

(FIFO D

INTA/B Pin LOW = no data

HIGH = 1 byte

ISABLED

FCR B

)

LOW = FIFO below trigger level HIGH = FIFO above trigger level

(FIFO E

-0 = 1

NABLED

)

2.10 Crystal Oscillator or External Clock Input

The 2752 includes an on-chip oscillator (XTAL1 and XTAL2) to produce a clock for both UART sections in the device. The CPU data bus does not require this clock for bus operation. The crystal oscillator provides a system clock to the Baud Rate Generators (BRG) section found in each of the UART. XTAL1 is the input to the oscillator or external clock buffer input with XTAL2 pin being the output. For programming details, see “Programmable Baud Rate Generator.”

FIGURE 4. TYPICAL OSCILLATOR CONNECTIONS

22-47 pF

XTAL1 XTAL2

500 KΩ − 1 MΩ

22-47 pF

0-120 Ω

(Optional)

1.8432 MHz to

24 MHz

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XR16L2752

2.25V TO 5.5V DUART WITH 64-BYTE FIFO

REV. 1.2.0

The on-chip oscillator is designed to use an industry standard microprocessor crystal (parallel resonant, fundamental frequency with 10-22 pF capacitance load, ESR of 20-120 ohms and 100ppm frequency tolerance) connected externally between the XTAL1 and XTAL2 pins (see Figure 4). The programmable Baud Rate Generator is capable of operating with a crystal oscillator frequency of up to 24 MHz. However, with an external clock input on XTAL1 pin and a 2K ohms pull-up resistor on XTAL2 pin (as shown in Figure 5) it can extend its operation up to 50 MHz (6.25 Mbps serial data rate) and 5V with an 8X sampling rate.

IGURE 5. EXTERNAL CLOCK CONNECTION FOR EXTENDED DATA RATE

External Clock

vcc

gnd

VCC

R1 2K

XTAL1

XTAL2

For further reading on the oscillator circuit please see the Application Note DAN108 on the EXAR web site at

http://www.exar.com.

2.11 Programmable Baud Rate Generator

Each UART has its own Baud Rate Generator (BRG) with a prescaler. The prescaler is controlled by a software bit in the MCR register. The MCR register bit-7 sets the prescaler to divide the input crystal or external clock by 1 or 4. The clock output of the prescaler goes to the BRG. The BRG further divides this clock by a

programmable divisor between 1 and (2 sampling rate clock is used by the transmitter for data bit shifting and

-1) to obtain a 16X sampling rate clock of the serial data rate. The receiver for data sampling. The BRG

divisor defaults to the maximum baud rate (DLL = 0x01 and DLM = 0x00) upon power up.

FIGURE 6. BAUD RATE GENERATOR AND PRESCALER

DLL and DLM

Registers

MCR Bit-7=0

(default)

Baud Rate

Generator

MCR Bit-7=1

Logic

16X

Sam plin g

Rate C loc k to

Transmitter

XTAL1

XTAL2

Prescaler

Divide by 1

Crystal

Osc/

Bu ffer

Prescaler

Divide by 4

Programming the Baud Rate Generator Registers DLM and DLL provides the capability of selecting the operating data rate. Ta bl e 5 shows the standard data rates available with a 14.7456 MHz crystal or external clock at 16X sampling rate clock rate. A 16X sampling clock is typically used. However, user can select the 8X sampling clock rate mode (EMSR bit-7=0) to double the operating data rate. When using a non-standard data rate crystal or external clock, the divisor value can be calculated for DLL/DLM with the following equation.

Page 11

REV. 1.2.0

divisor (decimal) = (XTAL1 clock frequency / prescaler) / (serial data rate x 16), with 16XMode [EMSR bit-7] = 1 divisor (decimal) = (XTAL1 clock frequency / prescaler) / (serial data rate x 8), with 16XMode [EMSR bit-7] = 0

2.25V TO 5.5V DUART WITH 64-BYTE FIFO

TABLE 5: TYPICAL DATA RATES WITH A 14.7456 MHZ CRYSTAL OR EXTERNAL CLOCK

XR16L2752

Data Rate

UTPUT

MCR Bit-7=1

100 400 2304 900 09 00 0

600 2400 384 180 01 80 0

1200 4800 192 C0 00 C0 0

2400 9600 96 60 00 60 0

4800 19.2k 48 30 00 30 0

9600 38.4k 24 18 00 18 0

19.2k 76.8k 12 0C 00 0C 0

38.4k 153.6k 6 06 00 06 0

57.6k 230.4k 4 04 00 04 0

115.2k 460.8k 2 02 00 02 0

230.4k 921.6k 1 01 00 01 0

Data Rate

UTPUT

MCR Bit-7=0

EFAULT

IVISOR FOR

Clock (Decimal)

)

16x

IVISOR FOR

Clock (HEX)

16x

ALUE

DLM

ROGRAM

(HEX)

DLL

ALUE

ROGRAM

(HEX)

ATA RATE

RROR

(%)

2.12 Transmitter

The transmitter section comprises of an 8-bit Transmit Shift Register (TSR) and 64 bytes of FIFO which includes a byte-wide Transmit Holding Register (THR). TSR shifts out every data bit with the 16X internal clock. A bit time is 16 clock periods (see EMSR bit-7). The transmitter sends the start-bit followed by the number of data bits, inserts the proper parity-bit if enabled, and adds the stop-bit(s). The status of the FIFO and TSR are reported in the Line Status Register (LSR bit-5 and bit-6).

2.12.1 Transmit Holding Register (THR) - Write Only

The transmit holding register is an 8-bit register providing a data interface to the host processor. The host writes transmit data byte to the THR to be converted into a serial data stream including start-bit, data bits, parity-bit and stop-bit(s). The least-significant-bit (Bit-0) becomes first data bit to go out. The THR is the input register to the transmit FIFO of 64 bytes when FIFO operation is enabled by FCR bit-0. Every time a write operation is made to the THR, the FIFO data pointer is automatically bumped to the next sequential data location.

2.12.2 Transmitter Operation in non-FIFO Mode

The host loads transmit data to THR one character at a time. The THR empty flag (LSR bit-5) is set when the data byte is transferred to TSR. THR flag can generate a transmit empty interrupt (ISR bit-1) when it is enabled by IER bit-1. The TSR flag (LSR bit-6) is set when TSR becomes completely empty.

Page 12

XR16L2752

2.25V TO 5.5V DUART WITH 64-BYTE FIFO

IGURE 7. TRANSMITTER OPERATION IN NON-FIFO MODE

REV. 1.2.0

Data Byte

16X or 8X Clock

(EMSR bit-7)

Transmit Shift Register (TSR)

Transmit

Holding

(THR)

THR Interrupt (ISR bit-1)

Enabled by IER bit-1

M S B

L S B

TXNOFIFO1

2.12.3 Transmitter Operation in FIFO Mode

The host may fill the transmit FIFO with up to 64 bytes of transmit data. The THR empty flag (LSR bit-5) is set whenever the FIFO is empty. The THR empty flag can generate a transmit empty interrupt (ISR bit-1) when the amount of data in the FIFO falls below its programmed trigger level. The transmit empty interrupt is enabled by IER bit-1. The TSR flag (LSR bit-6) is set when TSR/FIFO becomes empty.

FIGURE 8. TRANSMITTER OPERATION IN FIFO AND FLOW CONTROL MODE

Transmit

Data Byte

Auto CTS Flow Control (CTS# pin)

Flow Control Characters

(Xoff1/2 and Xon1/2 Reg.

Auto S oftware Flo w C ontrol

Transmit

FIFO

THR Interrupt (ISR bit-1) falls

below the program med Trigger

Level and then when becomes empty. FIFO is Enabled by FCR

bit-0=1

16X or 8X Clock

(EMSR bit-7 = 1)

Transmit Data Shift Register

(TSR )

TXFIFO1

2.13 Receiver

The receiver section contains an 8-bit Receive Shift Register (RSR) and 64 bytes of FIFO which includes a byte-wide Receive Holding Register (RHR). The RSR uses the 16X for timing. It verifies and validates every bit on the incoming character in the middle of each data bit. On the falling edge of a start or false start bit, an internal receiver counter starts counting at the 16X. After 8 clocks the start bit period should be at the center of the start bit. At this time the start bit is sampled and if it is still a logic 0 it is validated. Evaluating the start bit in this manner prevents the receiver from assembling a false character. The rest of the data bits and stop bits are sampled and validated in this same manner to prevent false framing. If there were any error(s), they are reported in the LSR register bits 2-4. Upon unloading the receive data byte from RHR, the receive FIFO pointer is bumped and the error tags are immediately updated to reflect the status of the data byte in RHR register. RHR can generate a receive data ready interrupt upon receiving a character or delay until it reaches the FIFO trigger level. Furthermore, data delivery to the host is guaranteed by a receive data ready time-out interrupt

Page 13

REV. 1.2.0

XR16L2752

2.25V TO 5.5V DUART WITH 64-BYTE FIFO

when data is not received for 4 word lengths as defined by LCR[1,0] plus 12 bits time. This is equivalent to 3.7-

4.6 character times. The RHR interrupt is enabled by IER bit-0.

2.13.1 Receive Holding Register (RHR) - Read-Only

The Receive Holding Register is an 8-bit register that holds a receive data byte from the Receive Shift Register. It provides the receive data interface to the host processor. The RHR register is part of the receive FIFO of 64 bytes by 11-bits wide, the 3 extra bits are for the 3 error tags to be reported in LSR register. When the FIFO is enabled by FCR bit-0, the RHR contains the first data character received by the FIFO. After the RHR is read, the next character byte is loaded into the RHR and the errors associated with the current data byte are immediately updated in the LSR bits 2-4.

FIGURE 9. RECEIVER OPERATION IN NON-FIFO MODE

16X or 8X Clock

(EMSR bit-7)

Receive Data Shift

Data Bit

Validation

Receive Data Characters

Receive

Data Byte

and Errors

Error

Tags in

LSR bits

4:2

Receive Data

Holding Register

(RHR)

RHR Interrupt (ISR bit-2)

FIGURE 10. RECEIVER OPERATION IN FIFO AND AUTO RTS FLOW CONTROL MODE

16X or 8X Clock

(EMSR bit-7)

64 bytes by 11-bit

wide FIFO

Receive Data Byte and Errors

Receive Data Shift

Receive

Data FIFO

(64-sets)

Error Tags

Receive

Data

LSR bits 4:2

Error Tags in

Data Bit

Validation

Example

- RX FIFO trigger level selected at 16

Data falls to 8

FIFO Trigger=16

Data fills to 24

bytes

(See No te Below)

RTS# re-asserts when data falls below the flow control trigger level to restart remote transmitter. Enable by EFR bit-6=1, MCR bit-2.

RHR Interrupt (ISR bit-2) programmed for desired FIFO trigger level. FIFO is Enabled by FCR bit-0=1

RTS# de-asserts when data fills above the flow control trigger level to suspend remote transmitter. Enable by EFR bit-6=1, MCR bit-2.

RXFIFO1

Receive Data Characters

RXFIFO1

OTE

Table-B selected as Trigger Table for

Figure 10 (Table 10 on page 27

Page 14

XR16L2752

2.25V TO 5.5V DUART WITH 64-BYTE FIFO

2.14 Auto RTS (Hardware) Flow Control

Automatic RTS hardware flow control is used to prevent data overrun to the local receiver FIFO. The RTS# output is used to request remote unit to suspend/resume data transmission. The auto RTS flow control features is enabled to fit specific application requirement (see Figure 11):

Enable auto RTS flow control using EFR bit-6.

•

The auto RTS function must be started by asserting RTS# output pin (MCR bit-1 to logic 1 after it is enabled).

•

If using the Auto RTS interrupt:

Enable RTS interrupt through IER bit-6 (after setting EFR bit-4). The UART issues an interrupt when the

•

RTS# pin makes a transition from low to high: ISR bit-5 will be set to logic 1.

2.15 Auto RTS Hysteresis

The 2752 has a new feature that provides flow control trigger hysteresis while maintaining compatibility with the XR16C850, ST16C650A and ST16C550 family of UARTs. With the Auto RTS function enabled, an interrupt is generated when the receive FIFO reaches the programmed RX trigger level. The RTS# pin will not be forced HIGH (RTS off), until the receive FIFO reaches the upper limit of the hysteresis level. The RTS# pin will return LOW after the RX FIFO is unloaded to the lower limit of the hysteresis level. Under the above described conditions, the 2752 will continue to accept data until the receive FIFO gets full. The Auto RTS function is initiated when the RTS# output pin is asserted LOW (RTS On). Ta b l e 1 3 shows the complete details for the Auto RTS# Hysteresis levels. Please note that this table is for programmable trigger levels only (Table D). The hysteresis values for Tables A-C are the next higher and next lower trigger levels in Tables A-C.

2.16 Auto CTS Flow Control

Automatic CTS flow control is used to prevent data overrun to the remote receiver FIFO. The CTS# input is monitored to suspend/restart the local transmitter. The auto CTS flow control feature is selected to fit specific application requirement (see Figure 11):

REV. 1.2.0

Enable auto CTS flow control using EFR bit-7.

•

If using the Auto CTS interrupt:

Enable CTS interrupt through IER bit-7 (after setting EFR bit-4). The UART issues an interrupt when the

•

CTS# pin is de-asserted (HIGH): ISR bit-5 will be set to 1, and UART will suspend transmission as soon as the stop bit of the character in process is shifted out. Transmission is resumed after the CTS# input is reasserted (LOW), indicating more data may be sent.

Page 15

REV. 1.2.0

FIGURE 11. AUTO RTS AND CTS FLOW CONTROL OPERATION

XR16L2752

2.25V TO 5.5V DUART WITH 64-BYTE FIFO

Local UART

Receiver FIFO

Trigger Reached

Auto RTS

Trigger Level

Transmitter

Auto CTS

RTSA#

CTSB#

TXB

RXA FIFO

INTA

(RXA FIFO

Interrupt)

UARTA

Monitor

Data Starts

Assert RTS# to Begin

Transmission

Receive

Data

RX FIFO

Trigger Level

RXA TXB

RTSA# CTSB#

RXBTXA

RTSB#CTSA#

RTS High Threshold

OFF

Suspend

Restart

RTS Low Threshold

Remote UART

UARTB

Transmitter

Auto CTS

Monitor

Receiver FIFO

Trigger Reached

Auto RTS

Trigger Level

RX FIFO

Trigger Level

RTSCTS1

The local UART (UARTA) starts data transfer by asserting RTSA# (1). RTSA# is normally connected to CTSB# (2) of remote UART (UARTB). CTSB# allows its transmitter to send data (3). TXB data arrives and fills UARTA receive FIFO

(4). When RXA data fills up to its receive FIFO trigger level, UARTA activates its RXA data ready interrupt (5) and continues to receive and put data into its FIFO. If interrupt service latency is long and data is not being unloaded, UARTA monitors its receive data fill level to match the upper threshold of RTS delay and de-assert RTSA# (6). CTSB# follows (7) and request UARTB transmitter to suspend data transfer. UARTB stops or finishes sending the data bits in its transmit shift register (8). When receive FIFO data in UARTA is unloaded to match the lower threshold of RTS delay (9), UARTA re-asserts RTSA# (10), CTSB# recognizes the change (11) and restarts its transmitter and data flow again until next receive FIFO trigger (12). This same event applies to the reverse direction when UARTA sends data to UARTB with RTSB# and CTSA# controlling the data flow.

Page 16

XR16L2752

2.25V TO 5.5V DUART WITH 64-BYTE FIFO

REV. 1.2.0

2.17 Auto Xon/Xoff (Software) Flow Control

When software flow control is enabled (See Table 15), the 2752 compares one or two sequential receive data characters with the programmed Xon or Xoff-1,2 character value(s). If receive character(s) (RX) match the programmed values, the 2752 will halt transmission (TX) as soon as the current character has completed transmission. When a match occurs, the Xoff (if enabled via IER bit-5) flag will be set and the interrupt output pin will be activated. Following a suspension due to a match of the Xoff character, the 2752 will monitor the receive data stream for a match to the Xon-1,2 character. If a match is found, the 2752 will resume operation and clear the flags (ISR bit-4).

Reset initially sets the contents of the Xon/Xoff 8-bit flow control registers to a logic 0. Following reset the user can write any Xon/Xoff value desired for software flow control. Different conditions can be set to detect Xon/ Xoff characters (See Table 15) and suspend/resume transmissions. When double 8-bit Xon/Xoff characters are selected, the 2752 compares two consecutive receive characters with two software flow control 8-bit values (Xon1, Xon2, Xoff1, Xoff2) and controls TX transmissions accordingly. Under the above described flow control mechanisms, flow control characters are not placed (stacked) in the user accessible RX data buffer or FIFO.

In the event that the receive buffer is overfilling and flow control needs to be executed, the 2752 automatically sends an Xoff message (when enabled) via the serial TX output to the remote modem. The 2752 sends the Xoff-1,2 characters two-character-times (= time taken to send two characters at the programmed baud rate) after the receive FIFO crosses the programmed trigger level (for all trigger tables A-D). To clear this condition, the 2752 will transmit the programmed Xon-1,2 characters as soon as receive FIFO is less than one trigger level below the programmed trigger level (for Trigger Tables A, B, and C) or when receive FIFO is less than the trigger level minus the hysteresis value (for Trigger Table D). This hysteresis value is the same as the Auto RTS Hysteresis value in Ta bl e 1 3. Ta bl e 6 below explains this when Trigger Table-B (See Ta bl e 1 0 ) is selected.

ABLE 6: AUTO XON/XOFF (SOFTWARE) FLOW CONTROL

RX T

RIGGER LEVEL

88 8* 0

16 16 16* 8

24 24 24* 16

28 28 28* 24

After the trigger level is reached, an xoff character is sent after a short span of time (= time required to send 2

characters); for example, after 2.083ms has elapsed for 9600 baud and 10-bit word length setting.

INT PIN A

CTIVATION

OFF CHARACTER(S

(

CHARACTERS IN RX FIFO

) S

ENT

)

ON CHARACTER(S

(

CHARACTERS IN RX FIFO

) S

ENT

)

2.18 Special Character Detect

A special character detect feature is provided to detect an 8-bit character when bit-5 is set in the Enhanced Feature Register (EFR). When this character (Xoff2) is detected, it will be placed in the FIFO along with normal incoming RX data.

The 2752 compares each incoming receive character with Xoff-2 data. If a match exists, the received data will be transferred to FIFO and ISR bit-4 will be set to indicate detection of special character. Although the Internal Register Table shows Xon, Xoff Registers with eight bits of character information, the actual number of bits is dependent on the programmed word length. Line Control Register (LCR) bits 0-1 defines the number of character bits, i.e., either 5 bits, 6 bits, 7 bits, or 8 bits. The word length selected by LCR bits 0-1 also determines the number of bits that will be used for the special character comparison. Bit-0 in the Xon, Xoff Registers corresponds with the LSB bit for the receive character.

2.19 Auto RS485 Half-duplex Control

The auto RS485 half-duplex direction control changes the behavior of the transmitter when enabled by FCTR bit-3. By default, it de-asserts RTS# (HIGH) output following

the last stop bit of the last character that has been transmitted. This helps in turning around the transceiver to receive the remote station’s response. When the host is ready to transmit next polling data packet again, it only has to load data bytes to the transmit FIFO. The transmitter automatically re-asserts RTS# (LOW) output prior to sending the data. The RS485 half-duplex direction control output can be inverted by enabling EMSR bit-3.

Page 17

REV. 1.2.0

XR16L2752

2.25V TO 5.5V DUART WITH 64-BYTE FIFO

2.20 Infrared Mode

The 2752 UART includes the infrared encoder and decoder compatible to the IrDA (Infrared Data Association) version 1.0. The IrDA 1.0 standard that stipulates the infrared encoder sends out a

3/16 of a bit wide HIGHpulse for each “0” bit in the transmit data stream. This signal encoding reduces the on-time of the infrared LED, hence reduces the power consumption. See

Figure 12 below.

The infrared encoder and decoder are enabled by setting MCR register bit-6 to a ‘1’. When the infrared feature is enabled, the transmit data output, TX, idles at logic zero level. Likewise, the RX input assumes an idle level of logic zero from a reset and power up, see Figure 12.

Typically, the wireless infrared decoder receives the input pulse from the infrared sensing diode on the RX pin. Each time it senses a light pulse, it returns a logic 1 to the data bit stream. However, this is not true with some infrared modules on the market which indicate a logic 0 by a light pulse. So the 2752 has a provision to invert the input polarity to accommodate this. In this case user can enable FCTR bit-2 to invert the input signal.

IGURE 12. INFRARED TRANSMIT DATA ENCODING AND RECEIVE DATA DECODING

Character

Data B its

Stop

TX D ata

Start

11 111

0000 0

Transmit

IR Pulse (TX Pin)

Receive IR Pulse (RX pin)

RX Data

Bit Time

1/16 Clock Delay

11 111

0000 0

Start

3/16 Bit Time

Data Bits

Character

1/2 Bit Time

Stop

IrEncoder-1

IRdecoder-1

Page 18

XR16L2752

2.25V TO 5.5V DUART WITH 64-BYTE FIFO

REV. 1.2.0

2.21 Sleep Mode with Auto Wake-Up

The 2752 supports low voltage system designs, hence, a sleep mode is included to reduce its power consumption when the chip is not actively used.

All of these conditions must be satisfied for the 2752 to enter sleep mode:

no interrupts pending for both channels of the 2752 (ISR bit-0 = 1)

■

sleep mode of both channels are enabled (IER bit-4 = 1)

■

modem inputs are not toggling (MSR bits 0-3 = 0)

■

RX input pins are idling HIGH

■

The 2752 stops its crystal oscillator to conserve power in the sleep mode. User can check the XTAL2 pin for no clock output as an indication that the device has entered the sleep mode.

The 2752 resumes normal operation by any of the following:

a receive data start bit transition (HIGH to LOW)

■

a data byte is loaded to the transmitter, THR or FIFO

■

a change of logic state on any of the modem or general purpose serial inputs: CTS#, DSR#, CD#, RI#

■

If the 2752 is awakened by any one of the above conditions, it will return to the sleep mode automatically after all interrupting conditions have been serviced and cleared. If the 2752 is awakened by the modem inputs, a read to the MSR is required to reset the modem inputs. In any case, the sleep mode will not be entered while an interrupt is pending from channel A or B. The 2752 will stay in the sleep mode of operation until it is disabled by setting IER bit-4 to a logic 0.

If the address lines, data bus lines, IOW#, IOR#, CSA#, CSB#, and modem input lines remain steady when the 2752 is in sleep mode, the maximum current will be in the microamp range as specified in the DC Electrical Characteristics on page 39. If the input lines are floating or are toggling while the 2752 is in sleep mode, the current can be up to 100 times more. If any of those signals are toggling or floating, then an external buffer would be required to keep the address, data and control lines steady to achieve the low current. As an alternative, please refer to the XR16L2751 with the PowerSave feature that eliminates any unnecessary external buffer.

A word of caution: owing to the starting up delay of the crystal oscillator after waking up from sleep mode, the first few receive characters may be lost. The number of characters lost during the restart also depends on your operating data rate. More characters are lost when operating at higher data rate. Also, it is important to keep RX A/B inputs idling HIGH or “marking” condition during sleep mode to avoid receiving a “break” condition upon the restart. This may occur when the external interface transceivers (RS-232, RS-485 or another type) are also put to sleep mode and cannot maintain the “marking” condition. To avoid this, the designer can use a 47k-100k ohm pull-up resistor on the RXA and RXB pins.

Page 19

REV. 1.2.0

XR16L2752

2.25V TO 5.5V DUART WITH 64-BYTE FIFO

2.22 Internal Loopback

The 2752 UART provides an internal loopback capability for system diagnostic purposes. The internal loopback mode

is enabled by setting MCR register bit-4 to logic 1. All regular UART functions operate normally.

Figure 13 shows how the modem port signals are re-configured. Transmit data from the transmit shift register

output is internally routed to the receive shift register input allowing the system to receive the same data that it was sending. The TX pin is held HIGH or mark condition while RTS# and DTR# are de-asserted, and CTS#, DSR# CD# and RI# inputs are ignored. Caution: the RX input must be held HIGH during loopback test else upon exiting the loopback test the UART may detect and report a false “break” signal. Also, Auto RTS/CTS hardware flow control is not supported during internal loopback.

IGURE 13. INTERNAL LOOP BACK IN CHANNEL A AND B

VCC

Transmit Shift Register

(THR/FIFO)

MCR bit-4=1

Receive Shift Register

(RHR/FIFO)

VCC

TXA/TXB

RXA/RXB

Internal Data Bus Lines and Control Signals

RTS#

CTS#

VCC

DTR#

DSR#

OP1#

RI#

VCC

OP2#

Modem / General Purpose Control Logic

CD#

RTSA#/RTSB#

CTSA#/CTSB#

DTRA#/DTRB#

DSRA#/DSRB#

RIA#/RIB#

(OP2A#/OP2B#)

CDA#/CDB#

Page 20

XR16L2752

2.25V TO 5.5V DUART WITH 64-BYTE FIFO

REV. 1.2.0

3.0 UART INTERNAL REGISTERS

Each of the UART channel in the 2752 has its own set of configuration registers selected by address lines A0, A1 and A2 with CS# and CHSEL selecting the channel. The complete register set is shown in Ta b l e 7 and

Ta bl e 8 .

ABLE 7: UART CHANNEL A AND B UART INTERNAL REGISTERS

DDRESSES

A2 A1 A0

EGISTER

EAD/WRITE

OMMENTS

16C550 C

0 0 0 RHR - Receive Holding Register

THR - Transmit Holding Register

0 0 0 DLL - Div Latch Low Byte Read/Write

0 1 0 AFR - Alternate Function Register Read/Write

0 0 0 DREV - Device Revision Code Read-only

0 0 1 DVID - Device Identification Code Read-only

0 0 1 IER - Interrupt Enable Register Read/Write LCR[7] = 0

0 1 0 ISR - Interrupt Status Register

FCR - FIFO Control Register

0 1 1 LCR - Line Control Register Read/Write

1 0 0 MCR - Modem Control Register Read/Write

1 0 1 LSR - Line Status Register

Reserved

1 1 0 MSR - Modem Status Register

Reserved

OMPATIBLE REGISTERS

Read-only Write-only

LCR[7] = 0

LCR[7] = 1, LCR ≠ 0xBF0 0 1 DLM - Div Latch High Byte Read/Write

DLL, DLM = 0x00,

LCR[7] = 1, LCR ≠ 0xBF

LCR[7] = 0

LCR ≠ 0xBF

1 1 1 SPR - Scratch Pad Register Read/Write LCR ≠ 0xBF, FCTR[6] = 0

1 1 1 FLVL - RX/TX FIFO Level Counter Register Read-only

1 1 1 EMSR - Enhanced Mode Select Register Write-only

NHANCED REGISTERS

0 0 0 TRG -RX/TX FIFO Trigger Level Register

FC - RX/TX FIFO Level Counter Register

0 0 1 FCTR - Feature Control Register Read/Write

0 1 0 EFR - Enhanced Function Register Read/Write

1 0 0 Xon-1 - Xon Character 1 Read/Write

1 0 1 Xon-2 - Xon Character 2 Read/Write

1 1 0 Xoff-1 - Xoff Character 1 Read/Write

1 1 1 Xoff-2 - Xoff Character 2 Read/Write

Write-only Read-only

LCR ≠ 0xBF, FCTR[6] = 1

LCR = 0xBF

Page 21

REV. 1.2.0

XR16L2752

2.25V TO 5.5V DUART WITH 64-BYTE FIFO

TABLE 8: INTERNAL REGISTERS DESCRIPTION.

DDRESS

A2-A0

0 0 0 RHR RD Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0

0 0 0 THR WR Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0

0 0 1 IER RD/WR 0/ 0/ 0/ 0/ Modem

0 1 0 ISR RD FIFOs

0 1 0 FCR WR RX FIFO

AME

EAD

RITE

BIT-7 BIT-6 BIT-5 BIT-4 BIT-3 BIT-2 BIT-1 BIT-0 C

16C550 Compatible Registers

CTS Int.

Enable

Enabled

Trigger

RTS Int.

Enable

FIFOs

Enabled

RX FIFO

Tr i gg e r

Xoff Int.

Enable

0/ 0/ INT

INT

Source

Bit-5

0/ 0/ DMA

T X F I F O

Trigger

Sleep Mode

Enable

INT

Source

Bit-4

TX FIFO

Tr i gg e r

HADED BITS ARE ENABLED WHEN

Stat.

Int.

Enable

Source

Bit-3

Mode

Enable

RX Line

Stat.

Int.

Enable

INT

Source

Bit-2

FIFO

Reset

Empty

Int

Enable

INT

Source

Bit-1

FIFO

Reset

EFR BIT-4=1

Data

Int.

Enable

INT

Source

Bit-0

FIFOs

Enable

OMMENT

LCR[7] = 0

0 1 1 LCR RD/WR Divisor

Enable

1 0 0 MCR RD/WR 0/ 0/ 0/ Internal

BRG

Pres-

caler

1 0 1 LSR RD RX FIFO

Global

Error

1 1 0 MSR RD CD#

Input

1 1 1 SPR RD/WR Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0 LCR ≠ 0xBF

1 1 1 EMSR WR 16X

Sam-

pling Rate

Mode

Set TX

Break

IR Mode

ENable

THR &

TSR

Empty

RI#

Input

LSR

Error

Inter-

rupt.

Imd/Dly#

Set Par-

ity

XonAny

THR

Empty

DSR#

Input

Auto

RTS

Hyst. bit-3

Even

Parity

Lopback

Enable

Break

CTS#

Input

Auto RTS

Hyst. bit-2

Parity

Enable

OP2#

Output

Control

Fram-

ing

Error

Delta

CD#

Auto RS485 Output

Inver-

sion

Stop

Bits

Rsrvd

(OP1#)

Parity

Error

Delta

RI#

Rsrvd Rx/Tx

Word

Length

Bit-1

RTS#

Output

Control

Over-

run

Error

Delta

DSR#

FIFO

Count

Word

Length

Bit-0

DTR#

Output

Control

Data

Ready

Delta

CTS#

Rx/Tx

FIFO

Count

LCR ≠ 0xBF

FCTR bit-6=0

LCR ≠ 0xBF

FCTR bit-6=1

1 1 1 FLVL RD Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0

Page 22

XR16L2752

2.25V TO 5.5V DUART WITH 64-BYTE FIFO

REV. 1.2.0

DDRESS

A2-A0

TABLE 8: INTERNAL REGISTERS DESCRIPTION.

AME

R W

EAD

RITE

BIT-7 BIT-6 BIT-5 BIT-4 BIT-3 BIT-2 BIT-1 BIT-0 C

HADED BITS ARE ENABLED WHEN

EFR BIT-4=1

OMMENT

Baud Rate Generator Divisor

0 0 0 DLL RD/WR Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0

0 0 1 DLM RD/WR Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0

LCR[7] = 1

LCR ≠ 0xBF

0 1 0 AFR RD/WR Rsvd Rsvd Rsvd Rsvd Rsvd

RXRDY#

Select

Baudout#

Select

Concur-

rent Write

0 0 0 DREV RD Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0 LCR[7] = 1

0 0 1DVIDRD0 0 0 0 1010

LCR ≠ 0xBF

DLL=0x00

DLM=0x00

Enhanced Registers

0 0 0 TRG WR Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0

0 0 0 FC RD Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0

0 0 1 FCTR RD/WR RX/TX

Mode

SCPAD

Swap

Tr i g

Ta bl e

Bit-1

Tr i g

Ta b l e

Bit-0

Auto

RS485

Direc-

tion

RX IR

Input

Inv.

Auto RTS Hyst Bit-1

Auto RTS Hyst Bit-0

Control

0 1 0 EFR RD/WR Auto

CTS

Enable

Auto RTS

Enable

Special

Char

Select

Enable

IER [7:4], ISR [5:4], FCR[5:4],

MCR[7:5]

Software Flow

Cntl

Bit-3

Soft-

ware

Flow

Cntl

Bit-2

Soft-

ware

Flow

Cntl

Bit-1

Software Flow

Cntl

Bit-0

LCR=0

1 0 0 XON1 RD/WR Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0

1 0 1 XON2 RD/WR Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0

1 1 0 XOFF1 RD/WR Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0

1 1 1 XOFF2 RD/WR Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0

4.0 INTERNAL REGISTER DESCRIPTIONS

4.1 Receive Holding Register (RHR) - Read- Only

See “Receiver” on page 12.

4.2 Transmit Holding Register (THR) - Write-Only

See “Transmitter” on page 11.

4.3 Interrupt Enable Register (IER) - Read/Write

The Interrupt Enable Register (IER) masks the interrupts from receive data ready, transmit empty, line status and modem status registers. These interrupts are reported in the Interrupt Status Register (ISR).

Page 23

REV. 1.2.0

4.3.1 IER versus Receive FIFO Interrupt Mode Operation

When the receive FIFO (FCR BIT-0 = 1) and receive interrupts (IER BIT-0 = 1) are enabled, the RHR interrupts (see ISR bits 2 and 3) status will reflect the following:

A. The receive data available interrupts are issued to the host when the FIFO has reached the programmed

trigger level. It will be cleared when the FIFO drops below the programmed trigger level.

B. FIFO level will be reflected in the ISR register when the FIFO trigger level is reached. Both the ISR register

status bit and the interrupt will be cleared when the FIFO drops below the trigger level.

C. The receive data ready bit (LSR BIT-0) is set as soon as a character is transferred from the shift register to

the receive FIFO. It is reset when the FIFO is empty.

4.3.2 IER versus Receive/Transmit FIFO Polled Mode Operation

When FCR BIT-0 equals a logic 1 for FIFO enable; resetting IER bits 0-3 enables the XR16L2752 in the FIFO polled mode of operation. Since the receiver and transmitter have separate bits in the LSR either or both can be used in the polled mode by selecting respective transmit or receive control bit(s).

A. LSR BIT-0 indicates there is data in RHR

B. LSR BIT-1 indicates an overrun error has occurred and that data in the FIFO may not be valid.

C. LSR BIT 2-4 provides the type of receive data errors encountered for the data byte in RHR, if any.

D. LSR BIT-5 indicates THR is empty.

E. LSR BIT-6 indicates when both the transmit FIFO and TSR are empty.

F. LSR BIT-7 indicates a data error in at least one character in the RX FIFO.

IER[0]: RHR Interrupt Enable

The receive data ready interrupt will be issued when RHR has a data character in the non-FIFO mode the receive FIFO has reached the programmed trigger level in the FIFO mode.

RX FIFO.

2.25V TO 5.5V DUART WITH 64-BYTE FIFO

XR16L2752

or when

Logic 0 = Disable the receive data ready interrupt (default).

•

Logic 1 = Enable the receiver data ready interrupt.

•

IER[1]: THR Interrupt Enable

This bit enables the Transmit Ready interrupt which is issued whenever the THR becomes empty in the nonFIFO mode or when data in the FIFO falls below the programmed trigger level in the FIFO mode. If the THR is empty when this bit is enabled, an interrupt will be generated.

Logic 0 = Disable Transmit Ready interrupt (default).

•

Logic 1 = Enable Transmit Ready interrupt.

•

IER[2]: Receive Line Status Interrupt Enable

If any of the LSR register bits 1, 2, 3 or 4 is a logic 1, it will generate an interrupt to inform the host controller about the error status of the current data byte in FIFO. LSR bits 1-4 generate an interrupt immediately when the character has been received.

Logic 0 = Disable the receiver line status interrupt (default).

•

Logic 1 = Enable the receiver line status interrupt.

•

IER[3]: Modem Status Interrupt Enable

Logic 0 = Disable the modem status register interrupt (default).

•

Logic 1 = Enable the modem status register interrupt.

•

IER[4]: Sleep Mode Enable (requires EFR bit-4 = 1)

Logic 0 = Disable Sleep Mode (default).

•

Logic 1 = Enable Sleep Mode. See Sleep Mode section for further details.

•

Page 24

XR16L2752

2.25V TO 5.5V DUART WITH 64-BYTE FIFO

IER[5]: Xoff Interrupt Enable (requires EFR bit-4=1)

Logic 0 = Disable the software flow control, receive Xoff interrupt. (default)

•

Logic 1 = Enable the software flow control, receive Xoff interrupt. See Software Flow Control section for

•

details.

IER[6]: RTS# Output Interrupt Enable (requires EFR bit-4=1)

Logic 0 = Disable the RTS# interrupt (default).

•

Logic 1 = Enable the RTS# interrupt. The UART issues an interrupt when the RTS# pin makes a transition

•

from low to high.

IER[7]: CTS# Input Interrupt Enable (requires EFR bit-4=1)

Logic 0 = Disable the CTS# interrupt (default).

•

Logic 1 = Enable the CTS# interrupt. The UART issues an interrupt when CTS# pin makes a transition from

•

low to high.

4.4 Interrupt Status Register (ISR) - Read-Only

The UART provides multiple levels of prioritized interrupts to minimize external software interaction. The Interrupt Status Register (ISR) provides the user with six interrupt status bits. Performing a read cycle on the ISR will give the user the current highest pending interrupt level to be serviced, others are queued up to be serviced next. No other interrupts are acknowledged until the pending interrupt is serviced. The Interrupt Source Table, Ta b le 9, shows the data values (bit 0-5) for the interrupt priority levels and the interrupt sources associated with each of these interrupt levels.

4.4.1 Interrupt Generation:

REV. 1.2.0

LSR is by any of the LSR bits 1, 2, 3 and 4.

•

RXRDY is by RX trigger level.

•

RXRDY Time-out is by a 4-char plus 12 bits delay timer.

•

TXRDY is by TX trigger level or TX FIFO empty (or transmitter empty in auto RS-485 control).

•

MSR is by any of the MSR bits 0, 1, 2 and 3.

•

Receive Xoff/Special character is by detection of a Xoff or Special character.

•

CTS# is when its transmitter toggles the input pin (from LOW to HIGH) during auto CTS flow control.

•

RTS# is when its receiver toggles the output pin (from LOW to HIGH) during auto RTS flow control.

•

4.4.2 Interrupt Clearing:

LSR interrupt is cleared by a read to the LSR register.

•

RXRDY interrupt is cleared by reading data until FIFO falls below the trigger level.

•

RXRDY Time-out interrupt is cleared by reading RHR.

•

TXRDY interrupt is cleared by a read to the ISR register or writing to THR.

•

MSR interrupt is cleared by a read to the MSR register.

•

Xoff interrupt is cleared by a read to ISR or when Xon character(s) is received.

•

Special character interrupt is cleared by a read to ISR or after the next character is received.

•

RTS# and CTS# flow control interrupts are cleared by a read to the MSR register.

•

Page 25

REV. 1.2.0

]

2.25V TO 5.5V DUART WITH 64-BYTE FIFO

ABLE 9: INTERRUPT SOURCE AND PRIORITY LEVEL

XR16L2752

RIORITY

EVEL

1 0 0 0 1 1 0 LSR (Receiver Line Status Register)

2 0 0 1 1 0 0 RXRDY (Receive Data Time-out)

3 0 0 0 1 0 0 RXRDY (Received Data Ready)

4 0000 1 0TXRDY (Transmit Ready)

5 0 0 0 0 0 0 MSR (Modem Status Register)

6 0 1 0 0 0 0 RXRDY (Received Xoff or Special character)

7 1 0 0 0 0 0 CTS#, RTS# change of state

- 0 0 0 0 0 1 None (default)

BIT-5 BIT-4 BIT-3 BIT-2 BIT-1 BIT-0

ISR R

EGISTER STATUS BITS

OURCE OF INTERRUPT

ISR[0]: Interrupt Status

Logic 0 = An interrupt is pending and the ISR contents may be used as a pointer to the appropriate interrupt

•

service routine.

Logic 1 = No interrupt pending (default condition).

•

ISR[3:1]: Interrupt Status

These bits indicate the source for a pending interrupt at interrupt priority levels (See Interrupt Source Ta bl e 9 ).

ISR[5:4]: Interrupt Status

These bits are enabled when EFR bit-4 is set to a logic 1. ISR bit-4 indicates that the receiver detected a data match of the Xoff character(s). Note that once set to a logic 1, the ISR bit-4 will stay a logic 1 until a Xon character is received. ISR bit-5 indicates that CTS# or RTS# has changed state.

ISR[7:6]: FIFO Enable Status

These bits are set to a logic 0 when the FIFOs are disabled. They are set to a logic 1 when the FIFOs are enabled.

4.5 FIFO Control Register (FCR) - Write-Only

This register is used to enable the FIFOs, clear the FIFOs, set the transmit/receive FIFO trigger levels, and select the DMA mode. The DMA, and FIFO modes are defined as follows:

FCR[0]: TX and RX FIFO Enable

Logic 0 = Disable the transmit and receive FIFO (default).

•

Logic 1 = Enable the transmit and receive FIFOs. This bit must be set to logic 1 when other FCR bits are

•

written or they will not be programmed.

FCR[1]: RX FIFO Reset

This bit is only active when FCR bit-0 is a ‘1’.

Logic 0 = No receive FIFO reset (default)

•

Logic 1 = Reset the receive FIFO pointers and FIFO level counter logic (the receive shift register is not

•

cleared or altered). This bit will return to a logic 0 after resetting the FIFO.

Page 26

XR16L2752

2.25V TO 5.5V DUART WITH 64-BYTE FIFO

FCR[2]: TX FIFO Reset

This bit is only active when FCR bit-0 is a ‘1’.

Logic 0 = No transmit FIFO reset (default).

•

Logic 1 = Reset the transmit FIFO pointers and FIFO level counter logic (the transmit shift register is not

•

cleared or altered). This bit will return to a logic 0 after resetting the FIFO.

FCR[3]: DMA Mode Select

Controls the behavior of the TXRDY# and RXRDY# pins. See DMA operation section for details.

Logic 0 = Normal Operation (default).

•

Logic 1 = DMA Mode.

•

FCR[5:4]: Transmit FIFO Trigger Select

(logic 0 = default, TX trigger level = one)

These 2 bits set the trigger level for the transmit FIFO. The UART will issue a transmit interrupt when the number of characters in the FIFO falls below the selected trigger level, or when it gets empty in case that the FIFO did not get filled over the trigger level on last re-load. Ta bl e 1 0 must be set to ‘1’ before these bits can be accessed. Note that the receiver and the transmitter cannot use different trigger tables. Whichever selection is made last applies to both the RX and TX side.

FCR[7:6]: Receive FIFO Trigger Select

(logic 0 = default, RX trigger level =1)

The FCTR Bits 5-4 are associated with these 2 bits. These 2 bits are used to set the trigger level for the receive FIFO. The UART will issue a receive interrupt when the number of the characters in the FIFO crosses the trigger level. Ta bl e 1 0 shows the complete selections. Note that the receiver and the transmitter cannot use different trigger tables. Whichever selection is made last applies to both the RX and TX side.

below shows the selections. EFR bit-4

REV. 1.2.0

Page 27

REV. 1.2.0

2.25V TO 5.5V DUART WITH 64-BYTE FIFO

ABLE 10: TRANSMIT AND RECEIVE FIFO TRIGGER TABLE AND LEVEL SELECTION

XR16L2752

Tabl e-A 00

Tabl e-B 01

Tabl e-C 10

RIGGER

ABLE

FCTR

-5

FCTR

BIT-4

FCR

BIT-7

0 0 1 1

FCR

BIT-6

0 1 0 1

FCR

BIT-5

FCR

-4

BIT

0 0 1 1

0 1 0 1

ECEIVE

RIGGER LEVEL

1 (default)

4 8

8 16 24 28

8 16 56 60

RANSMIT

RIGGER

1 (default) 16C550, 16C2550,

EVEL

8 24 30

8 16 32 56

OMPATIBILITY

16C2552, 16C554, 16C580

16C650A

16C654

Tabl e-D 11XXXXProgrammable

via TRG register.

FCTR[7] = 0.

Programmable

via TRG

FCTR[7] = 1.

16L2752, 16C2850, 16C2852, 16C850, 16C854, 16C864

4.6 Line Control Register (LCR) - Read/Write

The Line Control Register is used to specify the asynchronous data communication format. The word or character length, the number of stop bits, and the parity are selected by writing the appropriate bits in this register.

LCR[1:0]: TX and RX Word Length Select

These two bits specify the word length to be transmitted or received.

BIT-1 BIT-0 W

0 0 5 (default)

01 6

10 7

11 8

ORD LENGTH

Page 28

XR16L2752

2.25V TO 5.5V DUART WITH 64-BYTE FIFO

REV. 1.2.0

LCR[2]: TX and RX Stop-bit Length Select

The length of stop bit is specified by this bit in conjunction with the programmed word length.

BIT-2

0 5,6,7,8 1 (default)

15 1-1/2

1 6,7,8 2

ORD

LENGTH

TOP BIT LENGTH

(BIT

TIME(S

))

LCR[3]: TX and RX Parity Select

Parity or no parity can be selected via this bit. The parity bit is a simple way used in communications for data integrity check. See Ta b le 1 1 for parity selection summary below.

Logic 0 = No parity.

•

Logic 1 = A parity bit is generated during the transmission while the receiver checks for parity error of the

•

data character received.

LCR[4]: TX and RX Parity Select

If the parity bit is enabled with LCR bit-3 set to a logic 1, LCR BIT-4 selects the even or odd parity format.

Logic 0 = ODD Parity is generated by forcing an odd number of logic 1’s in the transmitted character. The

•

receiver must be programmed to check the same format (default).

Logic 1 = EVEN Parity is generated by forcing an even number of logic 1’s in the transmitted character. The

•

receiver must be programmed to check the same format.

LCR[5]: TX and RX Parity Select

If the parity bit is enabled, LCR BIT-5 selects the forced parity format.

LCR BIT-5 = logic 0, parity is not forced (default).

•

LCR BIT-5 = logic 1 and LCR BIT-4 = logic 0, parity bit is forced to a logical 1 for the transmit and receive

•

data.

LCR BIT-5 = logic 1 and LCR BIT-4 = logic 1, parity bit is forced to a logical 0 for the transmit and receive

•

data.

ABLE

LCR BIT-5 LCR BIT-4 LCR BIT-3 P

XX 0 No parity

0 0 1 Odd parity

01 1 Even parity

1 0 1 Force parity to mark,

ARITY SELECTION

11: P

ARITY SELECTION

“1”

1 1 1 Forced parity to

space, “0”

Page 29

REV. 1.2.0

LCR[6]: Transmit Break Enable

When enabled, the Break control bit causes a break condition to be transmitted (the TX output is forced to a “space”, LOW state). This condition remains, until disabled by setting LCR bit-6 to a logic 0.

Logic 0 = No TX break condition (default).

•

Logic 1 = Forces the transmitter output (TX) to a “space”, LOW, for alerting the remote receiver of a line

•

break condition.

LCR[7]: Baud Rate Divisors Enable

Baud rate generator divisor (DLL/DLM) enable.

Logic 0 = Data registers are selected (default).

•

Logic 1 = Divisor latch registers are selected.

•

4.7 Alternate Function Register (AFR) - Read/Write

This register is used to select specific modes of MF# operation and to allow both UART register sets to be written concurrently.

AFR[0]: Concurrent Write Mode

When this bit is set, the CPU can write concurrently to the same register in both UARTs. This function is intended to reduce the dual UART initialization time. It can be used by the CPU when both channels are initialized to the same state. The external CPU can set or clear this bit by accessing either register set. When this bit is set, the channel select pin still selects the channel to be accessed during read operations. The user should ensure that LCR Bit-7 of both channels are in the same state before executing a concurrent write to the registers at address 0, 1, or 2.

2.25V TO 5.5V DUART WITH 64-BYTE FIFO

XR16L2752

Logic 0 = No concurrent write (default).

•

Logic 1 = Register set A and B are written concurrently with a single external CPU I/O write operation.

•

AFR[2:1]: MF# Output Select

These bits select a signal function for output on the MF# A/B pins. These signal function are described as: OP2#, BAUDOUT#, or RXRDY#. Only one signal function can be selected at a time.

BIT-2 BIT-1 MF# F

0 0 OP2# (default)

0 1 BAUDOUT#

1 0 RXRDY#

11 Reserved

AFR[7:3]: Reserved

All are initialized to logic 0.

4.8 Modem Control Register (MCR) or General Purpose Outputs Control - Read/Write

The MCR register is used for controlling the serial/modem interface signals or general purpose inputs/outputs.

MCR[0]: DTR# Output

The DTR# pin is a modem control output. If the modem interface is not used, this output may be used as a general purpose output.

Logic 0 = Force DTR# output HIGH (default).

•

Logic 1 = Force DTR# output LOW.

•

UNCTION

Page 30

XR16L2752

2.25V TO 5.5V DUART WITH 64-BYTE FIFO

MCR[1]: RTS# Output

The RTS# pin is a modem control output and may be used for automatic hardware flow control by enabled by EFR bit-6. If the modem interface is not used, this output may be used as a general purpose output.

Logic 0 = Force RTS# output HIGH (default).

•

Logic 1 = Force RTS# output LOW.

•

MCR[2]: Reserved

OP1# is not available as an output pin on the 2752. But it is available for use during Internal Loopback Mode. In the Loopback Mode, this bit is used to write the state of the modem RI# interface signal.

MCR[3]: OP2# Output / INT Output Enable

OP2# is available as an output pin on the 2752 when AFR[2:1] = ‘00’. In the Loopback Mode, MCR[3] is used to write the state of the modem CD# interface signal. Also see pin descriptions for MF# pins.

Logic 0 = Forces OP2# output HIGH (default).

•

Logic 1 = Forces OP2# output LOW.

•

MCR[4]: Internal Loopback Enable

Logic 0 = Disable loopback mode (default).

•

Logic 1 = Enable local loopback mode, see loopback section and Figure 13.

•

MCR[5]: Xon-Any Enable

REV. 1.2.0

Logic 0 = Disable Xon-Any function (for 16C550 compatibility, default).

•

Logic 1 = Enable Xon-Any function. In this mode, any RX character received will resume transmit operation.

•

The RX character will be loaded into the RX FIFO, unless the RX character is an Xon or Xoff character and the 2752 is programmed to use the Xon/Xoff flow control.

MCR[6]: Infrared Encoder/Decoder Enable

Logic 0 = Enable the standard modem receive and transmit input/output interface (default).

•

Logic 1 = Enable infrared IrDA receive and transmit inputs/outputs. The TX/RX output/input are routed to the

•

infrared encoder/decoder. The data input and output levels conform to the IrDA infrared interface requirement. While in this mode, the infrared TX output will be a logic 0 during idle data conditions.

MCR[7]: Clock Prescaler Select

Logic 0 = Divide by one. The input clock from the crystal or external clock is fed directly to the Programmable

•

Baud Rate Generator without further modification, i.e., divide by one (default).

Logic 1 = Divide by four. The prescaler divides the input clock from the crystal or external clock by four and

•

feeds it to the Programmable Baud Rate Generator, hence, data rates become one forth.

4.9 Line Status Register (LSR) - Read Only

This register provides the status of data transfers between the UART and the host.

LSR[0]: Receive Data Ready Indicator

Logic 0 = No data in receive holding register or FIFO (default).

•

Logic 1 = Data has been received and is saved in the receive holding register or FIFO.

•

LSR[1]: Receiver Overrun Flag

Logic 0 = No overrun error. (default)

•

Logic 1 = Overrun error. A data overrun error condition occurred in the receive shift register. This happens

•

when additional data arrives while the FIFO is full. In this case the previous data in the receive shift register is overwritten. Note that under this condition the data byte in the receive shift register is not transferred into the FIFO, therefore the data in the FIFO is not corrupted by the error.

Page 31

REV. 1.2.0

LSR[2]: Receive Data Parity Error Flag

Logic 0 = No parity error (default).

•

Logic 1 = Parity error. The receive character in RHR does not have correct parity information and is suspect.

•

This error is associated with the character available for reading in RHR.

LSR[3]: Receive Data Framing Error Flag

Logic 0 = No framing error (default).

•

Logic 1 = Framing error. The receive character did not have a valid stop bit(s). This error is associated with

•

the character available for reading in RHR.

LSR[4]: Receive Break Flag

Logic 0 = No break condition (default).

•

Logic 1 = The receiver received a break signal (RX was a logic 0 for at least one character frame time). In the

•

FIFO mode, only one break character is loaded into the FIFO.

LSR[5]: Transmit Holding Register Empty Flag

This bit is the Transmit Holding Register Empty indicator. The THR bit is set to a logic 1 when the last data byte is transferred from the transmit holding register to the transmit shift register. The bit is reset to logic 0 concurrently with the data loading to the transmit holding register by the host. In the FIFO mode this bit is set when the transmit FIFO is empty, it is cleared when the transmit FIFO contains at least 1 byte.

LSR[6]: THR and TSR Empty Flag

This bit is set to a logic 1 whenever the transmitter goes idle. It is set to logic 0 whenever either the THR or TSR contains a data character. In the FIFO mode this bit is set to a logic 1 whenever the transmit FIFO and transmit shift register are both empty.

LSR[7]: Receive FIFO Data Error Flag

2.25V TO 5.5V DUART WITH 64-BYTE FIFO

XR16L2752

Logic 0 = No FIFO error (default).

•

Logic 1 = A global indicator for the sum of all error bits in the RX FIFO. At least one parity error, framing error

•

or break indication is in the FIFO data. This bit clears when there is no more error(s) in any of the bytes in the RX FIFO.

4.10 Modem Status Register (MSR) - Read Only

This register provides the current state of the modem interface input signals. Lower four bits of this register are used to indicate the changed information. These bits are set to a logic 1 whenever a signal from the modem changes state. These bits may be used as general purpose inputs when they are not used with modem signals.

MSR[0]: Delta CTS# Input Flag

Logic 0 = No change on CTS# input (default).

•

Logic 1 = The CTS# input has changed state since the last time it was monitored. A modem status interrupt

•

will be generated if MSR interrupt is enabled (IER bit-3).

MSR[1]: Delta DSR# Input Flag

Logic 0 = No change on DSR# input (default).

•

Logic 1 = The DSR# input has changed state since the last time it was monitored. A modem status interrupt

•

will be generated if MSR interrupt is enabled (IER bit-3).

MSR[2]: Delta RI# Input Flag

Logic 0 = No change on RI# input (default).

•

Logic 1 = The RI# input has changed from a LOW to HIGH, ending of the ringing signal. A modem status

•

interrupt will be generated if MSR interrupt is enabled (IER bit-3).

Page 32

XR16L2752

2.25V TO 5.5V DUART WITH 64-BYTE FIFO

MSR[3]: Delta CD# Input Flag

Logic 0 = No change on CD# input (default).

•

Logic 1 = Indicates that the CD# input has changed state since the last time it was monitored. A modem

•

status interrupt will be generated if MSR interrupt is enabled (IER bit-3).

MSR[4]: CTS Input Status

CTS# pin may function as automatic hardware flow control signal input if it is enabled and selected by Auto CTS (EFR bit-7). Auto CTS flow control allows starting and stopping of local data transmissions based on the modem CTS# signal. A HIGH on the CTS# pin will stop UART transmitter as soon as the current character has finished transmission, and a LOW will resume data transmission. Normally MSR bit-4 bit is the complement of the CTS# input. However in the loopback mode, this bit is equivalent to the RTS# bit in the MCR register. The CTS# input may be used as a general purpose input when the modem interface is not used.

MSR[5]: DSR Input Status

Normally this bit is the complement of the DSR# input. In the loopback mode, this bit is equivalent to the DTR# bit in the MCR register. The DSR# input may be used as a general purpose input when the modem interface is not used.

MSR[6]: RI Input Status

Normally this bit is the complement of the RI# input. In the loopback mode this bit is equivalent to bit-2 in the MCR register. The RI# input may be used as a general purpose input when the modem interface is not used.

MSR[7]: CD Input Status

Normally this bit is the complement of the CD# input. In the loopback mode this bit is equivalent to bit-3 in the MCR register. The CD# input may be used as a general purpose input when the modem interface is not used.

4.11 Scratch Pad Register (SPR) - Read/Write

This is a 8-bit general purpose register for the user to store temporary data. The content of this register is preserved during sleep mode but becomes 0xFF (default) after a reset or a power off-on cycle.

4.12 Enhanced Mode Select Register (EMSR)

This register replaces SPR (during a Write) and is accessible only when FCTR[6] = 1.

EMSR[1:0]: Receive/Transmit FIFO Count (Write-Only)

When Scratchpad Swap (FCTR[6]) is asserted, EMSR bits 1-0 controls what mode the FIFO Level Counter is operating in.

REV. 1.2.0

ABLE 12: SCRATCHPAD SWAP SELECTION

FCTR[6] EMSR[1] EMSR[0] Scratchpad is

0 X X Scratchpad

1 0 0 RX FIFO Counter Mode

1 0 1 TX FIFO Counter Mode

1 1 0 RX FIFO Counter Mode

1 1 1 Alternate RX/TX FIFO

Counter Mode

During Alternate RX/TX FIFO Counter Mode, the first value read after EMSR bits 1-0 have been asserted will always be the RX FIFO Counter. The second value read will correspond with the TX FIFO Counter. The next value will be the RX FIFO Counter again, then the TX FIFO Counter and so on and so forth.

EMSR[2]: Reserved

EMSR[3]: Automatic RS485 Half-Duplex Control Output Inversion

Logic 0 = RTS# output is a logic 0 during TX and a logic 1 during RX (default, compatible with 16C2850).

•

Logic 1 = RTS# output is a logic 1 during TX and a logic 0 during RX.

•

Page 33

REV. 1.2.0

EMSR[5:4]: Extended RTS Hysteresis

ABLE 13: RTS Hysteresis Levels

XR16L2752

2.25V TO 5.5V DUART WITH 64-BYTE FIFO

EMSR

0000 0

0001 ±4

0010 ±6

0011 ±8

0100 ±8

0101 ±16

0110 ±24

0111 ±32

1000 ±40

1001 ±44

1010 ±48

1011 ±52

1100 ±12

1101 ±20

-5

EMSR

BIT-4

FCTR

BIT-1

FCTR

BIT-0

RTS# H

HARACTERS

YSTERESIS

)

1110 ±28

1111 ±36

EMSR[6]: LSR Interrupt Mode

Logic 0 = LSR Interrupt Delayed (for 16C2550 compatibility, default). LSR bits 2, 3, and 4 will generate an

•

interrupt when the character with the error is in the RHR.

Logic 1 = LSR Interrupt Immediate. LSR bits 2, 3, and 4 will generate an interrupt as soon as the character is

•

received into the FIFO.

EMSR[7]: 16X Sampling Rate Mode

Logic 0 = 8X Sampling Rate.

Logic 1 = 16X Sampling Rate (for 16C2550 compatibility, default).

4.13 FIFO Level Register (FLVL) - Read-Only

The FIFO Level Register replaces the Scratchpad Register (during a Read) when FCTR[6] = 1. Note that this is not identical to the FIFO Data Count Register which can be accessed when LCR = 0xBF.

FLVL[7:0]: FIFO Level Register

This register provides the FIFO counter level for the RX FIFO or the TX FIFO or both depending on EMSR[1:0].

See Table 12 for details.

Page 34

XR16L2752

2.25V TO 5.5V DUART WITH 64-BYTE FIFO

4.14 Baud Rate Generator Registers (DLL and DLM) - Read/Write

The concatenation of the contents of DLM and DLL gives the 16-bit divisor value which is used to calculate the baud rate:

Baud Rate = (Clock Frequency / 16) / Divisor

•

See MCR bit-7 and the baud rate table also.

4.15 Device Identification Register (DVID) - Read Only

This register contains the device ID (0x0A for XR16C2752). Prior to reading this register, DLL and DLM should be set to 0x00.

4.16 Device Revision Register (DREV) - Read Only

This register contains the device revision information. For example, 0x01 means revision A. Prior to reading this register, DLL and DLM should be set to 0x00.

4.17 Trigger Level Register (TRG) - Write-Only

User Programmable Transmit/Receive Trigger Level Register.

TRG[7:0]: Trigger Level Register

These bits are used to program desired trigger levels when trigger Table-D is selected. FCTR bit-7 selects between programming the RX Trigger Level (a logic 0) and the TX Trigger Level (a logic 1).

4.18 RX/TX FIFO Level Count Register (FC) - Read-Only

This register is accessible when LCR = 0xBF. Note that this register is not identical to the FIFO Level Count Register which is located in the general register set when FCTR bit-6 = 1 (Scratchpad Register Swap). It is suggested to read the FIFO Level Count Register at the Scratchpad Register location when FCTR bit-6 = 1. See Ta bl e 1 2.

FC[7:0]: RX/TX FIFO Level Count

Receive/Transmit FIFO Level Count. Number of characters in Receiver FIFO (FCTR[7] = 0) or Transmitter FIFO (FCTR[7] = 1) can be read via this register.

4.19 Feature Control Register (FCTR) - Read/Write

This register controls the XR16L2752 new functions.

FCTR[1:0]: RTS Hysteresis

User selectable RTS# hysteresis levels for hardware flow control application. After reset, these bits are set to “0” to select the next trigger level for hardware flow control. See Table 13 on page 19 for more details.

FCTR[2]: IrDa RX Inversion

REV. 1.2.0

Logic 0 = Select RX input as encoded IrDa data.

•

Logic 1 = Select RX input as active high encoded IrDa data.

•

FCTR[3]: Auto RS-485 Direction Control

Logic 0 = Standard ST16C550 mode. Transmitter generates an interrupt when transmit holding register

•

becomes empty and transmit shift register is shifting data out.

Logic 1 = Enable Auto RS485 Direction Control function. The direction control signal, RTS# pin, changes its

•

output logic state from LOW to HIGH one bit time after the last stop bit of the last character is shifted out. Also, the Transmit interrupt generation is delayed until the transmitter shift register becomes empty. The RTS# output pin will automatically return LOW when a data byte is loaded into the TX FIFO. However, RTS# behavior can be inverted by setting EMSR[3] = 1.

Page 35

REV. 1.2.0

FCTR[5:4]: Transmit/Receive Trigger Table Select

See Table 10 on page 27.

ABLE 14: TRIGGER TABLE SELECT

2.25V TO 5.5V DUART WITH 64-BYTE FIFO

XR16L2752

FCTR

-5

0 0 Table-A (TX/RX)

0 1 Table-B (TX/RX)

1 0 Table-C (TX/RX)

1 1 Table-D (TX/RX)

FCTR[6]: Scratchpad Swap

Logic 0 = Scratch Pad register is selected as general read and write register. ST16C550 compatible mode.

•

Logic 1 = FIFO Count register (Read-Only), Enhanced Mode Select Register (Write-Only). Number of

•

characters in transmit or receive FIFO can be read via scratch pad register when this bit is set. Enhanced Mode Select Register is selected when it is written into.

FCTR[7]: Programmable Trigger Register Select

Logic 0 = Registers TRG and FC selected for RX.

•

Logic 1 = Registers TRG and FC selected for TX.

•

Enhanced Feature Register (EFR)

Enhanced features are enabled or disabled using this register. Bit 0-3 provide single or dual consecutive character software flow control selection (see Ta b le 15 ). When the Xon1 and Xon2 and Xoff1 and Xoff2 modes are selected, the double 8-bit words are concatenated into two sequential characters. Caution: note that whenever changing the TX or RX flow control bits, always reset all bits back to logic 0 (disable) before programming a new setting.

EFR[3:0]: Software Flow Control Select

Single character and dual sequential characters software flow control is supported. Combinations of software flow control can be selected by programming these bits.

FCTR

BIT-4

ABLE

Page 36

XR16L2752

2.25V TO 5.5V DUART WITH 64-BYTE FIFO

ABLE 15: SOFTWARE FLOW CONTROL FUNCTIONS

REV. 1.2.0

EFR

-3

BIT

-3

ONT

0 0 0 0 No TX and RX flow control (default and reset)

0 0 X X No transmit flow control

1 0 X X Transmit Xon1, Xoff1

0 1 X X Transmit Xon2, Xoff2

1 1 X X Transmit Xon1 and Xon2, Xoff1 and Xoff2

X X 0 0 No receive flow control

X X 1 0 Receiver compares Xon1, Xoff1

X X 0 1 Receiver compares Xon2, Xoff2

1 0 1 1 Transmit Xon1, Xoff1

0 1 1 1 Transmit Xon2, Xoff2

1 1 1 1 Transmit Xon1 and Xon2, Xoff1 and Xoff2,

0 0 1 1 No transmit flow control,

EFR

ONT

BIT

-2

EFR

ONT

BIT

-1

EFR

ONT

BIT

-0

RANSMIT AND RECEIVE SOFTWARE FLOW CONTROL

Receiver compares Xon1 or Xon2, Xoff1 or Xoff2

Receiver compares Xon1 and Xon2, Xoff1 and Xoff2

EFR[4]: Enhanced Function Bits Enable

Enhanced function control bit. This bit enables IER bits 4-7, ISR bits 4-5, FCR bits 4-5, and MCR bits 5-7 to be modified. After modifying any enhanced bits, EFR bit-4 can be set to a logic 0 to latch the new values. This feature prevents legacy software from altering or overwriting the enhanced functions once set. Normally, it is recommended to leave it enabled, logic 1.

Logic 0 = modification disable/latch enhanced features. IER bits 4-7, ISR bits 4-5, FCR bits 4-5, and MCR

•

bits 5-7 are saved to retain the user settings. After a reset, the IER bits 4-7, ISR bits 4-5, FCR bits 4-5, and MCR bits 5-7 are set to a logic 0 to be compatible with ST16C550 mode (default).

Logic 1 = Enables the above-mentioned register bits to be modified by the user.

•

EFR[5]: Special Character Detect Enable

Logic 0 = Special Character Detect Disabled (default).

•

Logic 1 = Special Character Detect Enabled. The UART compares each incoming receive character with

•

data in Xoff-2 register. If a match exists, the receive data will be transferred to FIFO and ISR bit-4 will be set to indicate detection of the special character. Bit-0 corresponds with the LSB bit of the receive character. If flow control is set for comparing Xon1, Xoff1 (EFR [1:0]= ‘10’) then flow control and

special character work normally. However, if flow control is set for comparing Xon2, Xoff2 (EFR[1:0]= ‘01’) then flow control works normally, but Xoff2 will not

go to the FIFO, and will generate an Xoff interrupt and a special character

interrupt, if enabled via IER bit-5.

Page 37

REV. 1.2.0

EFR[6]: Auto RTS Flow Control Enable

RTS# output may be used for hardware flow control by setting EFR bit-6 to logic 1. When Auto RTS is selected, an interrupt will be generated when the receive FIFO is filled to the programmed trigger level and RTS de-asserts HIGH at the next upper trigger level. RTS# will return LOW when FIFO data falls below the next lower trigger level. The RTS# output must be asserted (LOW) before the auto RTS can take effect. RTS# pin will function as a general purpose output when hardware flow control is disabled.

Logic 0 = Automatic RTS flow control is disabled (default).

•

Logic 1 = Enable Automatic RTS flow control.

•

EFR[7]: Auto CTS Flow Control Enable

Automatic CTS Flow Control.

Logic 0 = Automatic CTS flow control is disabled (default).

•

Logic 1 = Enable Automatic CTS flow control. Data transmission stops when CTS# input de-asserts to logic

•

1. Data transmission resumes when CTS# returns to a logic 0.

4.20 Software Flow Control Registers (XOFF1, XOFF2, XON1, XON2) - Read/Write

These registers are used as the programmable software flow control characters xoff1, xoff2, xon1, and xon2. For more details, see Table 6 on page 16.

2.25V TO 5.5V DUART WITH 64-BYTE FIFO

XR16L2752

Page 38

XR16L2752

2.25V TO 5.5V DUART WITH 64-BYTE FIFO

TABLE 16: UART RESET CONDITIONS FOR CHANNEL A AND B

REGISTERS RESET STATE

DLM and DLL DLM = 0x00 and DLL = 0x01. Only resets to these values during a

power up. They do not reset when the Reset Pin is asserted.

AFR Bits 7-0 = 0x00

RHR Bits 7-0 = 0xXX

THR Bits 7-0 = 0xXX

IER Bits 7-0 = 0x00

FCR Bits 7-0 = 0x00

ISR Bits 7-0 = 0x01

LCR Bits 7-0 = 0x00

MCR Bits 7-0 = 0x00

LSR Bits 7-0 = 0x60

MSR Bits 3-0 = Logic 0

Bits 7-4 = Logic levels of the inputs inverted

REV. 1.2.0

SPR Bits 7-0 = 0xFF

EMSR Bits 7-0 = 0x80

FLVL Bits 7-0 = 0x00

EFR Bits 7-0 = 0x00

XON1 Bits 7-0 = 0x00

XON2 Bits 7-0 = 0x00

XOFF1 Bits 7-0 = 0x00

XOFF2 Bits 7-0 = 0x00

FC Bits 7-0 = 0x00

I/O SIGNALS RESET STATE

TX HIGH

OP1# HIGH

MF# HIGH

RTS# HIGH

DTR# HIGH

TXRDY# LOW

INT LOW

Page 39

REV. 1.2.0

2.25V TO 5.5V DUART WITH 64-BYTE FIFO

ABSOLUTE MAXIMUM RATINGS

Power Supply Range 7 Volts

Voltage at Any Pin GND-0.3 V to 7 V

XR16L2752

Operating Temperature

Storage Temperature

-40

to +150oC

-65

to +85oC

Package Dissipation 500 mW

TYPICAL PACKAGE THERMAL RESISTANCE DATA

Thermal Resistance (44-PLCC)

(MARGIN OF ERROR: ± 15%)

theta-ja = 50

C/W, theta-jc = 21oC/W

ELECTRICAL CHARACTERISTICS

DC ELECTRICAL CHARACTERISTICS

UNLESS OTHERWISE NOTED: TA=0

YMBOL

ILCK

IHCK

Clock Input Low Level -0.3 0.6 -0.3 0.6 -0.5 0.6 V

Clock Input High Level 2.0 VCC 2.4 VCC 3.0 VCC V

Input Low Voltage -0.3 0.8 -0.3 0.8 -0.5 0.8 V

ARAMETER

70OC (-40O TO +85OC FOR INDUSTRIAL GRADE PACKAGE), VCC=2.25 -5.5V

IMITS

2.5V

MIN M

IMITS

3.3V

MIN M

IMITS

5.0V

MIN M

NITS

ONDITIONS

SLEEP

Input High Voltage 2.0 5.5 2.0 5.5 2.2 5.5 V

Output Low Voltage

0.4

Output High Voltage

2.4 V

2.0

1.8

Input Low Leakage Current ±10 ±10 ±10 uA

Input High Leakage Current ±10 ±10 ±10 uA

Input Pin Capacitance 5 5 5 pF

0.4 V V V

V V

Power Supply Current 2.7 2.7 4 mA

Sleep Current 6 15 30 uA See Test 1

IOL = 6 mA

= 4 mA

= 2 mA

IOH = -6 mA

= -1 mA

= -400 uA

Test 1: The following inputs must remain steady at VCC or GND state to minimize Sleep current: A0-A2, D0D7, IOR#, IOW#, CS#, CHSEL, and all modem inputs. Also, RXA and RXB inputs must idle at logic 1 state while asleep. Floating inputs will result in sleep currents in the mA range. For PowerSave feature that isolates address, data and control signals, please see the XR16L2751 datasheet.

Page 40

XR16L2752

2.25V TO 5.5V DUART WITH 64-BYTE FIFO

AC ELECTRICAL CHARACTERISTICS

UNLESS OTHERWISE NOTED: TA=0

PF LOAD WHERE APPLICABLE

70OC (-40O TO +85OC FOR INDUSTRIAL GRADE PACKAGE), VCC=2.25-5.5V,

REV. 1.2.0

YMBOL

ARAMETER

IMITS

2.5

IMITS

3.3

IMITS

5.0

- Crystal Frequency 16 20 24 MHz

CLK External Clock Low/High Time 20 15 10 ns

OSC External Clock Frequency 24 33 50 MHz

Address Setup Time 10 10 10 ns

Address Hold Time 10 10 10 ns

Chip Select Width 150 75 50 ns

IOR# Strobe Width 150 75 50 ns

Read Cycle Delay 150 75 50 ns

Data Access Time 175 100 60 ns

Data Disable Time 045030030ns

IOW# Strobe Width 150 75 50 ns

Write Cycle Delay 150 75 50 ns

Data Setup Time 25 20 15 ns

RDV

NIT

WDO

MOD

RSI

SSI

RRI

INT

WRI

SSR

Data Hold Time 15 10 10 ns

Delay From IOW# To Output 150 75 50 ns

Delay To Set Interrupt From MODEM Input 150 75 50 ns

Delay To Reset Interrupt From IOR# 150 75 50 ns

Delay From Stop To Set Interrupt 1 1 1 Bclk

Delay From IOR# To Reset Interrupt 150 75 50 ns

Delay From Stop To Interrupt 150 75 50 ns

Delay From Initial INT Reset To Transmit

824824824Bclk

Start

Delay From IOW# To Reset Interrupt 150 75 50 ns

Delay From Stop To Set RXRDY# 1 1 1 Bclk

Delay From IOR# To Reset RXRDY# 150 75 50 ns

Delay From IOW# To Set TXRDY# 150 75 50 ns

Page 41

REV. 1.2.0

AC ELECTRICAL CHARACTERISTICS

UNLESS OTHERWISE NOTED: TA=0

70 PF LOAD WHERE APPLICABLE

70OC (-40O TO +85OC FOR INDUSTRIAL GRADE PACKAGE), VCC=2.25-5.5V,

XR16L2752

2.25V TO 5.5V DUART WITH 64-BYTE FIFO

YMBOL

SRT

ARAMETER

Delay From Center of Start To Reset

IMITS

2.5

MIN M

888Bclk

IMITS

3.3

MIN M

IMITS

5.0

TXRDY#

RST

Reset Pulse Width 40 40 40 ns

N Baud Rate Divisor 1

-1

216-1

Bclk Baud Clock 16X or 8X of data rate Hz

FIGURE 14. CLOCK TIMING

CLK

EXTERNAL

CLOCK

OSC

CLK

NIT

IGURE

15. M

IO W #

RTS# DTR#

CD# CTS# DSR#

IN T

IO R #

RI#

ODEM INPUT/OUTPUT TIMING FOR CHANNELS

Active

WDO

Change of state

MOD

Change of state

A & B

Change of state

MOD

Active Active Active

RSI

Active

Active Active

Change of state

MOD

Page 42

XR16L2752

2.25V TO 5.5V DUART WITH 64-BYTE FIFO

FIGURE 16. DATA BUS READ TIMING

REV. 1.2.0

IGURE

A0-A2

CSA#/ CSB#

IOR#

D0-D7

ATA BUS WRITE TIMING

17. D

Valid Address Valid Address

RDV

Valid Data Valid Data

RDTm

A0-A2

CSA#/

CSB#

IOW#

D0-D7

Valid Address Valid Address

Valid Data Valid Data

16Write

Page 43

REV. 1.2.0

2.25V TO 5.5V DUART WITH 64-BYTE FIFO

FIGURE 18. RECEIVE READY & INTERRUPT TIMING [NON-FIFO MODE] FOR CHANNELS A & B

XR16L2752

INT

RXRDY#

IOR#

(Reading data out of RHR)

Start

Bit

D0:D7

Stop

Bit

1 Byte

in RHR

Active

Data

Ready

SSR

D0:D7

in RHR

SSR

1 Byte

SSR

Active

Data

Ready

D0:D7

in RHR

SSR

1 Byte

SSR

Active

Data

Ready

RXNFM

IGURE 19. TRANSMIT READY & INTERRUPT TIMING [NON-FIFO MODE] FOR CHANNELS A & B

(Unloading)

IER[1] enabled

Start

Bit

D0:D7

ISR is read ISR is readISR is read

Stop

Bit

D0:D7

INT*

WRI

SRT

WRI

TXRDY#

IOW#

(Loading data into THR)

*INT is cleared when the ISR is read or when data is loaded into the THR.

D0:D7

SRT

TXNonFIFO

Page 44

XR16L2752

2.25V TO 5.5V DUART WITH 64-BYTE FIFO

FIGURE 20. RECEIVE READY & INTERRUPT TIMING [FIFO MODE, DMA DISABLED] FOR CHANNELS A & B

Start

Bit

REV. 1.2.0

IGURE

INT

RXRDY#

First Byte is Received in

RX FIFO

IOR#

(Reading data out of RX FIFO)

ECEIVE READY

21. R

Start

Bit

D0:D7

Stop

Bit

D0:D7

SSR

NTERRUPT TIMING

& I

Stop

Bit

D0:D7

SSI

RX FIFO fills up to RX

Trigger Level or RX Data

Timeout

[FIFO M

D0:D7

ODE

D0:D7

, DMA E

D0:D7

RX FIFO drops

below RX

Trigger Level

Empties

RRI

NABLED] FOR CHANNELS

FIFO

RXINTDMA#

A & B

INT

RXRDY#

IOR#

(Reading data out of RX FIFO)

D0:D7

RX FIFO fills up to RX

Trigger Level or RX Data

D0:D7

Timeout

D0:D7T D0:D7

SSI

SSR

D0:D7

RX FIFO drops

below RX

Trigger Level

FIFO

Empties

RRI

RXFIFODMA

Page 45

REV. 1.2.0

XR16L2752

2.25V TO 5.5V DUART WITH 64-BYTE FIFO

FIGURE 22. TRANSMIT READY & INTERRUPT TIMING [FIFO MODE, DMA MODE DISABLED] FOR CHANNELS A & B

(Unloading)

INT*

TXRDY#

TX FIFO

Empty

IER[1]

enabled

Data in

TX FIFO

Start

Bit

D0:D7

ISR is read

TX FIFO fills up

to trigger level

Stop

Bit

Last Data Byte

Transmitted

D0:D7

WRI

D0:D7

ISR is read

TX FIFO drops

below trigger level

D0:D7

TX FIFO

Empty

SRT

IOW#

(Loading data

into FIFO)

*INT is cleared when the ISR is read or when TX FIFO fills up to the trigger level.

IGURE 23. TRANSMIT READY & INTERRUPT TIMING [FIFO MODE, DMA MODE ENABLED] FOR CHANNELS A & B

TXDMA#

Stop

Bit

D0:D7

ISR Read

D0:D7

(Unloading)

IER[1]

enabled

Start

Bit

INT*

TX FIFO fills up

to trigger level

TXRDY#

IOW#

(Loading data

into FIFO)

*INT cleared when the ISR is read or when TX FIFO fills up to trigger level.

D0:D7

WRI

TX FIFO

Full

Last Data Byte

Transmitted

D0:D7S

SRT

D0:D7

TX FIFO drops

below trigger level

At least 1

empty l ocation

ISR Read

in FIFO

D0:D7S

TXDMA

Page 46

XR16L2752

2.25V TO 5.5V DUART WITH 64-BYTE FIFO

PACKAGE DIMENSIONS (44 PIN PLCC)

REV. 1.2.0

44 LEAD PLASTIC LEADED CHIP CARRIER

(PLCC)

Rev. 1.00

D D

244

45° x H

Note: The control dimension is the millimeter column

INCHES MILLIMETERS

45° x H

Seating Plane

SYMBOL MIN MAX MIN MAX

A 0.165 0.180 4.19 4.57

0.090 0.120 2.29 3.05

0.020 --- 0.51 ---

B 0.013 0.021 0.33 0.53

0.026 0.032 0.66 0.81

C 0.008 0.013 0.19 0.32

D 0.685 0.695 17.40 17.65

0.650 0.656 16.51 16.66

0.590 0.630 14.99 16.00

0.500 typ. 12.70 typ.

e 0.050 BSC 1.27 BSC

0.042 0.056 1.07 1.42

0.042 0.048 1.07 1.22

R 0.025 0.045 0.64 1.14

Page 47

REV. 1.2.0

REVISION HISTORY

XR16L2752

2.25V TO 5.5V DUART WITH 64-BYTE FIFO

ATE

November 2001 Rev P1.0.0 Prelim data sheet.

March 2002 Rev P1.1.0 Corrected INTA/B pin descriptions and reset state. Renamed Sclk to Bclk. Changed

September 2002 Rev 1.0.0 Release into production. Clarified RTS# pin descriptions, XTAL1 pin description,

March 2003 Rev 1.1.0 Updated AC Electrical Characteristics.

August 2004 Rev 1.2.0 Added Device Status to Ordering Information. Clarified pin descriptions- changed

EVISION

ESCRIPTION

A0-A7 in Figures 16 and 17 to A0-A2.

external clock description, auto RS485 half-duplex control description, EMSR bit-3 description and updated 2.5 V, I

from using logic 1 and logic 0 to HIGH (VCC) and LOW (GND) for input and output pin descriptions.

and I

DC Electrical Characteristics.

SLEEP

NOTICE

EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user’s specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies.

EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances.

Datasheet August 2004.

Send your UART technical inquiry with technical details to hotline: uarttechsupport@exar.com.

Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.

Page 48

XR16L2750

2.25V TO 5.5V DUART WITH 64-BYTE FIFO

REV. 1.1.0

TABLE OF CONTENTS

GENERAL DESCRIPTION .................................................................................................1

PPLICATIONS

EATURES

1. XR16L2752 B

IGURE

2. PIN OUT A

IGURE

ORDERING

PIN DESCRIPTIONS .........................................................................................................3

1.0 Product DESCRIPTION ........................................................................................................... 6

2.0 FUNCTIONAL DESCRIPTIONS .............................................................................................. 7

2.1 CPU I

2.2 5-V

EVICE RESET

2.3 D

EVICE IDENTIFICATION AND REVISION

2.4 D

HANNEL

2.5 C

3. XR16L2750 D

IGURE

HANNEL

2.6 C

2.7 SIMULTANEOUS

2.8 DMA MODE

1: C

ABLE

2.9 INTA

2.10 C

ABLE

T F

IGURE

2.11 P

IGURE

2.12 T

ABLE

2.13 R

IGURE

2.14 A

2.15 AUTO

2.16 AUTO

IGURE

2.17 A

2.18 SPECIAL

2.19 AUTO

ABLE

2.20 I

IGURE

2.21 S

2.22 INTERNAL

IGURE

3.0 UART INTERNAL REGISTERS ............................................................................................. 20

ABLE

HANNEL

2: TXRDY#

RYSTAL OSCILLATOR OR EXTERNAL CLOCK INPUT

3: INTA 4: INTA

4. T

ROGRAMMABLE BAUD RATE GENERATOR

5. E

6. B

RANSMITTER

2.12.1 Transmit Holding Register (THR) - Write Only ....................................................................................... 11

2.12.2 Transmitter Operation in non-FIFO Mode .............................................................................................. 11

5: T

YPICAL DATA RATES WITH A

2.12.3 Transmitter Operation in FIFO Mode...................................................................................................... 12

ECEIVER

7. T

8. T

2.13.1 Receive Holding Register (RHR) - Read-Only ....................................................................................... 13

9. R

10. R

UTO

11. A

UTO XON/XOFF

6: A

UTO XON/XOFF

NFRARED MODE

12. I

LEEP MODE WITH AUTO WAKE-UP

13. I

7: UART CHANNEL A AND B UART INTERNAL REGISTERS.............................................................................................. 20

8: INTERNAL REGISTERS DESCRIPTION. S

.............................................................................................................................................1

...................................................................................................................................................1

LOCK DIAGRAM

SSIGNMENT

INFORMATION

NTERFACE

OLT TOLERANT INPUTS

................................................................................................................................. 7

................................................................................................................................................. 1

............................................................................................................................................................. 2

..............................................................................................................................2

................................................................................................................... 7

.................................................................................................................................... 7

................................................................................................. 7

AND

ELECTION

B S

ATA BUS INTERCONNECTIONS

NTERNAL REGISTERS

B I

RITE TO CHANNEL

............................................................................................................. 7

........................................................................................................................... 7

............................................................................................. 8

AND

B ...................................................................................... 8

........................................................................................................................................ 8

AND

B S

AND

RXRDY# O

AND

INTB O

....................................................................................................................................................... 8

ELECT

UTPUTS IN

UTPUTS

FIFO

................................................................................................................... 9

AND

DMA M

.................................................................................................... 8

ODE

............................................................................ 9

INTB P

AND

YPICAL OSCILLATOR CONNECTIONS

INS OPERATION FOR TRANSMITTER

INTB PIN O

PERATION FOR RECEIVER

........................................................................................................................................ 9

................................................................................................................ 9

....................................................................................................................... 9

....................................................................................... 10

XTERNAL CLOCK CONNECTION FOR EXTENDED DATA RATE

AUD RATE GENERATOR AND PRESCALER

............................................................................................................................. 10

................................................................................................. 10

.................................................................................................................................. 11

14.7456 MHZ

CRYSTAL OR EXTERNAL CLOCK

.............................................................................. 11

....................................................................................................................................... 12

RANSMITTER OPERATION IN NON

RANSMITTER OPERATION IN

ECEIVER OPERATION IN NON

ECEIVER OPERATION IN

RTS

AND

ARDWARE

YSTERESIS

LOW CONTROL

CTS F

RTS (H

RTS H CTS F

UTO

HARACTER DETECT

RS485 H

ALF-DUPLEX CONTROL

OFTWARE

FIFO

-FIFO M

FIFO

) F

................................................................................................................. 14

LOW CONTROL OPERATION

OFTWARE

) F

LOW CONTROL

-FIFO M

AND FLOW CONTROL MODE

AND AUTO

LOW CONTROL

............................................................................................................ 14

) F

........................................................................................................ 16

...................................................................................................................... 12

ODE

........................................................................................................................... 13

ODE

RTS F

LOW CONTROL MODE

............................................................................................. 12

............................................................................... 13

........................................................................................ 14

.............................................................................................................. 15

LOW CONTROL

................................................................................ 16

............................................................................................ 16

....................................................................................................................... 16

............................................................................................................................. 17

NFRARED TRANSMIT DATA ENCODING AND RECEIVE DATA DECODING

................................................................................. 17

................................................................................................ 18

OOPBACK

NTERNAL LOOP BACK IN CHANNEL

...................................................................................................................... 19

B........................................................................................................................ 19

AND

HADED BITS ARE ENABLED WHEN

EFR BIT-4=1 ................................................ 21

Page 49

XR16L2750

2.25V TO 5.5V DUART WITH 64-BYTE FIFO

REV. 1.1.0

4.0 INTERNAL Register descriptions ........................................................................................ 22

ECEIVE HOLDING REGISTER

4.1 R

4.2 TRANSMIT

4.3 INTERRUPT

OLDING REGISTER

NABLE REGISTER

(RHR) - R

(THR) - W

(IER) - R

4.3.1 IER versus Receive FIFO Interrupt Mode Operation ............................................................................... 23

4.3.2 IER versus Receive/Transmit FIFO Polled Mode Operation.................................................................... 23

NTERRUPT STATUS REGISTER

4.4 I

(ISR) - R

4.4.1 Interrupt Generation: ................................................................................................................................ 24

4.4.2 Interrupt Clearing: .................................................................................................................................... 24

4.5 FIFO C

9: I

ABLE

4.6 L

10: T

ABLE

11: P

ABLE

4.7 A

4.8 MODEM

4.9 LINE

4.10 MODEM

4.11 SCRATCH

4.12 ENHANCED

12: S

ABLE

4.13 FIFO L

13: RTS H

ABLE

4.14 B

4.15 D

4.16 D

4.17 TRIGGER

4.18 RX/TX FIFO LEVEL

4.19 FEATURE

14: T

ABLE

15: S

ABLE

4.20 S

16: UART RESET CONDITIONS FOR CHANNEL A AND B ................................................................................................... 38

ABLE

ONTROL REGISTER

NTERRUPT SOURCE AND PRIORITY LEVEL

INE CONTROL REGISTER

RANSMIT AND RECEIVE

ARITY SELECTION

LTERNATE FUNCTION REGISTER

ONTROL REGISTER

TATUS REGISTER

CRATCHPAD SWAP SELECTION

EVEL REGISTER

YSTERESIS LEVELS

AUD RATE GENERATOR REGISTERS

EVICE IDENTIFICATION REGISTER

EVICE REVISION REGISTER

RIGGER TABLE SELECT

OFTWARE FLOW CONTROL FUNCTIONS

OFTWARE FLOW CONTROL REGISTERS

................................................................................................................................................................ 28

TATUS REGISTER

PAD R

EGISTER

ODE SELECT REGISTER

EVEL REGISTER

ONTROL REGISTER

(FCR) - W

(LCR) - R

FIFO T

RIGGER TABLE AND LEVEL SELECTION

(AFR) - R

(MCR) OR G

(LSR) - R

(MSR) - R

(SPR) - R

............................................................................................................................................ 32

(FLVL) - R

.................................................................................................................................................... 33

(DREV) - R

(TRG) - W

OUNT REGISTER

(FCTR) - R

....................................................................................................................................................... 35

EAD

EAD/WRITE

EAD-ONLY

RITE-ONLY

............................................................................................................................... 25

EAD/WRITE

EAD ONLY

EAD/WRITE

NLY

- O

........................................................................... 22

RITE-ONLY

......................................................................... 22

.......................................................................... 22

............................................................................ 24

............................................................................... 25

................................................................................ 27

.................................................................................. 27

EAD/WRITE

ENERAL PURPOSE OUTPUTS CONTROL

..................................................................... 29

EAD/WRITE

- R

....... 29

..................................................................................... 30

............................................................................. 31

............................................................................... 32

(EMSR) ................................................................................. 32

EAD-ONLY

(DLL

(DVID) - R

............................................................................................................................... 36

.................................................................................. 33

AND

DLM) - R

EAD ONLY

RITE-ONLY

(FC) - R

............................................................................ 34

EAD-ONLY

EAD/WRITE

(XOFF1, XOFF2, XON1, XON2) - R

EAD/WRITE

.............................................. 34

................................................................. 34

......................................................................... 34

.............................................................. 34

..................................................................... 34

EAD/WRITE

............... 37

ABSOLUTE MAXIMUM RATINGS .................................................................................. 39

TYPICAL PACKAGE THERMAL RESISTANCE DATA (MARGIN OF ERROR: ± 15%) 39

ELECTRICAL CHARACTERISTICS................................................................................ 39

LECTRICAL CHARACTERISTICS

DC E

LECTRICAL CHARACTERISTICS

AC E

........................................................................................................... 39

........................................................................................................... 40

Unless otherwise noted: TA=0o to 70oC (-40o to +85oC for industrial grade package), Vcc=2.25-5.5V, ......... 40

70 pF load where applicable .............................................................................................................................. 40

IGURE

F F

IGURE

F F

IGURE

F F

IGURE

14. C

LOCK TIMING

15. M

ODEM INPUT/OUTPUT TIMING FOR CHANNELS

16. D

ATA BUS READ TIMING

17. D

ATA BUS WRITE TIMING

18. R

ECEIVE READY

19. T

RANSMIT READY

20. R

ECEIVE READY

21. R

ECEIVE READY

22. T

RANSMIT READY

23. T

RANSMIT READY

.................................................................................................................................................................... 41

..................................................................................................................................................... 42

.................................................................................................................................................... 42

& I

NTERRUPT TIMING

& I

NTERRUPT TIMING

& I

NTERRUPT TIMING

& I

NTERRUPT TIMING

& I

NTERRUPT TIMING

& I

NTERRUPT TIMING

[NON-FIFO M

[FIFO M [FIFO M

A & B......................................................................................................... 41

[NON-FIFO M

, DMA D

ODE

, DMA E

ODE

[FIFO M [FIFO M

ODE

ODE] FOR CHANNELS

ISABLED] FOR CHANNELS

NABLED] FOR CHANNELS

, DMA M , DMA M

ODE DISABLED] FOR CHANNELS

ODE ENABLED] FOR CHANNELS

A & B................................................................. 43

A & B............................................................... 43

A & B ............................................... 44

A & B ................................................ 44

A & B................................... 45

A & B.................................... 45

PACKAGE DIMENSIONS (44 PIN PLCC) ....................................................................... 46

EVISION HISTORY

TABLE OF CONTENTS ................................................................................................................................. I

.................................................................................................................................... 47

Datasheet XR16L2752 Datasheet (EXAR)

Specifications and Main Features

Frequently Asked Questions

User Manual