Datasheet XR16C854 Datasheet (EXAR)

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Preliminary Information

XR16C854

QUAD UART WITH RX/TX FIFO

COUNTERS,128-BYTE FIFO

DESCRIPTION

The XR16C854 *1 (854) is a universal asynchronous receiver and transmitter (UART) with a dual foot print interface compatible with the ST16C554D/654 and ST68C554/654. The 854 is an enhanced UART with 128 byte FIFOs, Independent Transmit and Receive FIFO counter, automatic hardware/software flow control, and data rates up to 1.5Mbps. Onboard status registers provide the user with error indications and operational status, modem interface control. System interrupts may be tailored to meet user requirements. An internal loop-back capability allows onboard diagnostics. The 854 is available in 64 pin TQFP, 68 pin PLCC, and 100 pin QFP packages. The 64 pin package offers the 16 interface mode which is compatible with the industry standard ST16C554. The 68 and 100 pin packages offer an additional 68 mode which allows easy integration with Motorola, and other popular microprocessors. The XR16C854CV (64 pin) offers three state interrupt control while the XR16C854DV provides constant active interrupt outputs. The 64 pin devices do not offer TXRDY/RXRDY outputs or the default clock select option (CLKSEL). The 100 pin packages offer faster channel status access by providing separate outputs for TXRDY and RXRDY, offer separate Infrared TX outputs and a musical instrument clock input (MIDICLK). The 854 combines the package interface modes of the 16C554/654 and 68C554/654 series on a single integrated chip.

FEATURES

• Compatibility with the Industry Standard

ST16C554/654, ST68C554/654, TL16C554

• 1.5 Mbps transmit/receive operation (24MHz)

• 128 byte transmit and receive FIFO

• Independent transmit and receive FIFO counter

• Automatic software/hardware flow control

• Programmable Xon/Xoff characters

• Software selectable Baud Rate Generator pre-

scaleable clock rates of 1X, 4X.

• Four selectable, and Programmable Transmit/

Receive FIFO interrupt trigger levels

• Standard modem interface or infrared IrDA en-

coder/decoder interface

• Software flow control turned off optionally by any

(Xon) RX character

• Independent MIDI interface on 100 pin packages

• 100 pin packages offer internal register FIFO

monitoring and separate IrDA TX outputs

• Sleep mode ( 200µA stand-by)

ORDERING INFORMATION

-DSRA

-CTSA

-DTRA

VCC

-RTSA

INTA

-CSA

TXA

-IOW

TXB

-CSB

INTB

-RTSB

GND

-DTRB

-CTSB

-DSRB

PLCC Package

-CDA

-RIA

RXA

987654321

2728293031323334353637383940414243

-CDB

GNDD7D6D5D4D3D2D1D0

XR16C854CJ

16 MODE

-RIB

A2A1A0

RXB

16/-68

CLKSEL

68676665646362

XTAL1

XTAL2

INTSEL

RESET

-TXRDY

-RXRDY

VCC

GND

RXD

-RID

-CDD

-DSRD

-CTSD

-DTRD

GND

-RTSD

INTD

-CSD

TXD

-IOR

TXC

-CSC

INTC

-RTSC

VCC

-DTRC

-CTSC

-DSRC

-RIC

RXC

-CDC

Part number Pins Package Operating temperature

XR16C854CJ 68 PLCC 0° C to + 70° C XR16C854CV 64 TQFP 0° C to + 70° C XR16C854DCV 64 TQFP 0° C to + 70° C XR16C854CQ 100 QFP 0° C to + 70° C

Part number Pins Package Operating temperature

XR16C854IJ 68 PLCC -40° C to + 85° C XR16C854IV 64 TQFP -40° C to + 85° C XR16C854DIV 64 TQFP -40° C to + 85° C XR16C854IQ 100 QFP -40° C to + 85° C

Note *1: Patent Pending

Rev. 1.00P

EXAR Corporation, 48720 Kato Road, Fremont, CA 94538 • (510) 668-7000 • FAX (510) 668-7017

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XR16C854

Figure 1, Package Descriptions

64 Pin TQFP Package 68 Pin PLCC Package

-CDA

-RIA

RXA

GNDD7D6D5D4D3D2D1D0

646362616059585756555453525150

-DSRA

-CTSA

-DTRA

VCC

-RTSA

INTA

-CSA

TXA

-IOW

-TXB

-CSB

INTB

-RTSB

GND

-DTRB

-CTSB

171819202122232425262728293031

-CDB

-DSRB

XR16C854CV

XR16C854DCV

RXB

VCC

A2A1A0

-RIB XTAL1

XTAL2

VCC

RXD

-RID

-CDD

-DSRD

-CTSD

-DTRD

GND

-RTSD

INTD

-CSD

TXD

-IOR

TXC

-CSC

INTC

-RTSC

VCC

-DTRC

-CTSC

-DSRA

-CTSA

-DTRA

VCC

-RTSA

-IRQ

TXA

R/-W

TXB

N.C.

-RTSB

GND

-DTRB

-CTSB

-RIC

RXC

GND

RESET

-CDC

-DSRC

-CDA-RIA

RXA

GNDD7D6D5D4D3D2D1D0

987654321

-CS

XR16C854CJ

68 MODE

272829303132333435363738394041

-RIB

RXB

-CDB

A2A1A0

16/-68

CLKSEL

68676665646362

N.C.

XTAL1

XTAL2

-RESET

-TXRDY

-RXRDY

VCC

GND

RXD

-RID

-DSRD

-CTSD

-DTRD

GND

-RTSD

N.C.

TXD

N.C.

TXC

N.C.

-RTSC

VCC

-DTRC

-CTSC

-RIC

RXC

Rev. 1.00P

100 Pin QFP Package

N.C.

-CSRDY

IRTXD

-DSRD

-CTSD

-DTRD

GND

-RTSD

INTD

-CSD

TXD

-IOR

TXC

-CSC

INTC

-RTSC

VCC

-DTRC

-CTSC

8079787776757473727170696867666564636261605958575655545352

-TXRDYD

-RXRDYD

-CDD

-RID

RXD

VCC

INTSEL

GND

RXA

-RIA

-CDA

100

-RXRDYA

123456789

N.C.

IRTXA

-CTSA

-DSRA

-TXRDYA

XR16C854CQ

101112131415161718192021222324252627282930

TXA

VCC

INTA

-RTSA

-DTRA

TXB

INTB

-IOW

-CSA

-CSB

-RTSB

-DSRC

GND

-CTSB

-DTRB

-DSRB

IRTXC

-TXRDYC

N.C.

IRTXB

-TXRDYB

N.C.

-RXRDYC

-CDC

-RIC

RXC

GND

-TXRDY

-RXRDY

RESET

MIDICLK

XTAL2

XTAL1

16/-68

CLKSEL

RXB

-RIB

-CDB

-RXRDYB

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Figure 2, Block Diagram 16 Mode

XR16C854

D0-D7

-IOR

-IOW

RESET

A0-A2

-CS A-D

INT A-D

-RXRDY A-D

-TXRDY A-D INTSEL

Data bus

Select

Control

Interrupt

Control Logic

Logic

Transmit

FIFO

Registers

Flow

Control

Logic

Receive

FIFO

Registers

Flow

Control signals

Inter Connect Bus Lines

Control

Logic

Transmit

Shift

Receive

Shift

TX A-D

Encoder

RX A-D RXIR A-D

Decoder

-DTR A-D

-RTS A-D

XTAL1

MIDI

XTAL2

Rev. 1.00P

Clock

Modem

Control

Logic

Generator

Baud Rate

-CTS A-D

-RI A-D

-CD A-D

-DSR A-D

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XR16C854

Figure 3, Block Diagram 68 Mode

D0-D7

R/-W

-RESET

A0-A4

-CS

IRQ

-RXRDY A-D

-TXRDY A-D

Data bus

Interrupt

Select

Control

Control Logic

Logic

Transmit

FIFO

Registers

Flow

Control

Logic

Receive

FIFO

Registers

Flow

Control signals

Inter Connect Bus Lines

Control

Logic

Transmit

Shift

Receive

Shift

TX A-D

Encoder

RX A-D RXIR A-D

Decoder

-DTR A-D

-RTS A-D

XTAL1

MIDI

XTAL2

Rev. 1.00P

Clock

Generator

Baud Rate

Modem Control

Logic

-CTS A-D

-RI A-D

-CD A-D

-DSR A-D

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XR16C854

SYMBOL DESCRIPTION

Symbol Pin Signal Pin Description

68 100 64 type

16/-68 31 36 - I 16/68 Interface Type Select (input with internal pull-up). -

This input provides the 16 (Intel) or 68 (Motorola) bus interface type select. The functions of -IOR, -IOW, INT AD, and -CS A-D are re-assigned with the logical state of this pin. When this pin is a logic 1, the 16 mode interface 16C554 is selected. When this pin is a logic 0, the 68 mode interface (68C554) is selected. When this pin is a logic 0, -IOW is reassigned to R/-W, RESET is re-assigned to -RESET, -IOR is not used, and INT A-D(s) are connected in a WIRE-OR configuration. The WIRE-OR outputs are connected internally to the open source IRQ signal output. This pin is not available on 64 pin packages which operate in the 16 mode only.

A0 34 39 24 I Address-0 Select Bit. Internal registers address selection in

16 and 68 modes.

A1 33 38 23 I Address-1 Select Bit. Internal registers address selection in

16 and 68 modes.

A2 32 37 22 I Address-2 Select Bit. - Internal registers address selection

in 16 and 68 modes.

A3-A4 20,50 17,64 - I Address 3-4 Select Bits. - When the 68 mode is selected,

these pins are used to address or select individual UARTs (providing -CS is a logic 0). In the 16 mode, these pins are reassigned as chip selects, see -CSB and -CSC. These pins are not available on 64 pin packages which operate in the 16 mode only.

CLKSEL 30 35 - I Clock Select. - The 1X or 4X pre-scaleable clock is selected

by this pin. The 1X clock is selected when CLKSEL is a logic 1 (connected to VCC) or the 4X is selected when CLKSEL is a logic 0 (connected to GND). MCR bit-7 can override the state of this pin following reset or initialization (see MCR bit-

7). This pin is not available on 64 pin packages which provide MCR bit-7 selection only.

-CS 16 13 - I Chip Select. (active low) - In the 68 mode, this pin functions as a multiple channel chip enable. In this case, all four

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XR16C854

SYMBOL DESCRIPTION

Symbol Pin Signal Pin Description

68 100 64 type

UARTs (A-D) are enabled when the -CS pin is a logic 0. An individual UART channel is selected by the data contents of address bits A3-A4. When the 16 mode is selected (68/100 pin devices), this pin functions as -CSA, see definition under

-CS A-B. This pin is not available on 64 pin packages which operate in the 16 mode only.

-CS A-B 16,20 13,17 7,11

-CS C-D 50,54 64,68 38,42 I Chip Select A, B, C, D (active low) - This function is associated with the 16 mode only, and for individual channels, A through D. When in 16 Mode, these pins enable data transfers between the user CPU and the XR16C854 for the channel(s) addressed. Individual UART sections (A, B, C, D) are addressed by providing a logic 0 on the respective

-CS A-D pin. When the 68 mode is selected, the functions of these pins are reassigned. 68 mode functions are described under the their respective name/pin headings.

-CSRDY - 76 - I Control Status Ready (active low) - This feature is available on 100 pin QFP packages only. On 100 pin packages, the Contents of the FIFORDY Register is read when this pin is a logic 0. However it should be noted, D0-D3 will contain the inverted logic states of TXRDY, status bits A-D, and D4-D7 the inverted logic states of RXRDY, status bits D4-D7.

D0-D2 66-68 88-90 53-55 I/O D3-D7 1-5 91-95 56-60 Data Bus (Bi-directional) - These pins are the eight bit, three

state data bus for transferring information to or from the controlling CPU. D0 is the least significant bit and the first data bit in a transmit or receive serial data stream.

GND 6,23 96,20 14,28 GND 40,57 46,71 45,61 Pwr Signal and power ground.

INT A-B 15,21 12,18 6,12 INT C-D 49,55 63,69 37,43 O Interrupt A, B, C, D (active high) - This function is associated

with the 16 mode only. These pins provide individual channel interrupts, INT A-D. INT A-D are enabled when MCR bit-3 is set to a logic 1, interrupts are enabled in the interrupt enable register (IER), and when an interrupt con-

Rev. 1.00P

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XR16C854

SYMBOL DESCRIPTION

Symbol Pin Signal Pin Description

68 100 64 type

dition exists. Interrupt conditions include: receiver errors, available receiver buffer data, transmit buffer empty, or when a modem status flag is detected. When the 68 mode is selected, the functions of these pins are reassigned. 68 mode functions are described under the their respective name/pin headings.

INTSEL 65 87 - I Interrupt Select. (active high, with internal pull-down) - This

function is associated with the 16 mode only. When the 16 mode is selected, this pin can be used in conjunction with MCR bit-3 to enable or disable the three state interrupts, INT A-D or override MCR bit-3 and force continuous interrupts. Interrupt outputs are enabled continuously by making this pin a logic 1. Making this pin a logic 0 allows MCR bit-3 to control the three state interrupt output. In this mode, MCR bit-3 is set to a logic 1 to enable the three state outputs. This pin is disabled in the 68 mode. Due to pin limitations on 64 pin packages, this pin is not available. To cover this limitation, two 64 pin QFP package versions are offered. The XR16C854DCV operates in the continuos interrupt enable mode by bonded this pin to VCC internally. The XR16C854CV operates with MCR bit-3 control by bonding this pin to GND.

-IOR 52 66 40 I Input/Output Read. (active low Strobe) - This function is associated with the 16 mode only. A logic 0 transition on this pin will load the contents of an Internal register defined by address bits A0-A2 onto the XR16C854 data bus (D0-D7) for access by an external CPU. This pin is disabled in the 68 mode.

-IOW 18 15 9 I Input/Output Write. (active low strobe) - This function is associated with the 16 mode only. A logic 0 transition on this pin will transfer the contents of the data bus (D0-D7) from the external CPU to an internal register that is defined by address bits A0/A2. When the 16 mode is selected (68/100 pin devices), this pin functions as R/-W, see definition under R/W.

Rev. 1.00P

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XR16C854

SYMBOL DESCRIPTION

Symbol Pin Signal Pin Description

68 100 64 type

-IRQ 15 12 - O Interrupt Request or Interrupt A - This function is associated with the 68 mode only. In the 68 mode, interrupts from UART channels A-D are WIRE-ORed internally to function as a single IRQ interrupt. This pin transitions to a logic 0 (if enabled by the interrupt enable register) whenever a UART channel(s) requires service. Individual channel interrupt status can be determined by addressing each channel through its associated internal register, using -CS and A3A4. In the 68 mode an external pull-up resistor must be connected between this pin and Vcc. The function of this pin changes to INTA when operating in the 16 mode, see definition under INTA.

IRTX A-B - 6,24 IRTX C-D - 57,75 - O Infrared Transmit Data Output (IrDA) - This function is

associated with 100 pin packages only. These pins provide separate infrared IrDA TX outputs for UART channels (AD). The serial infrared IRTX data is transmitted via these pins with added start, stop and parity bits. The IRTX signal will be a logic 0 during reset, idle (no data), or when the transmitter is disabled. MCR bit-6 selects the standard modem or infrared interface.

MIDICLK - 42 - I MIDI (Musical Instrument Digital Interface) Clock Input -

This function is associated with 100 pin packages only. RXC and TXC can function as MIDI input/output ports when an external MIDI Clock is provided at this pin. External Clock or a crystal is connected to the XTAL2 pins for normal operation (see XTAL 1 & 2).

-RESET

RESET 37 43 27 I Reset. - In the 16 mode a logic 1 on this pin will reset the

internal registers and all the outputs. The UART transmitter output and the receiver input will be disabled during reset time. (See XR16C854 External Reset Conditions for initialization details.) When 16/-68 is a logic 0 (68 mode), this pin functions similarly but, as an inverted reset interface signal,

-RESET.

Rev. 1.00P

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XR16C854

SYMBOL DESCRIPTION

Symbol Pin Signal Pin Description

68 100 64 type

R/-W 18 15 - I Read/Write Strobe (active low) - This function is associated

with the 68 mode only. This pin provides the combined functions for Read or Write strobes. A logic 1 to 0 transition transfers the contents of the CPU data bus (D0-D7) to the register selected by -CS and A0-A4. Similarly a logic 0 to 1 transition places the contents of a 854 register selected by

-CS and A0-A4 on the data bus, D0-D7, for transfer to an external CPU.

-RXRDY 38 44 - O Receive Ready (active low) - This function is associated with 68 and 100 pin packages only. -RXRDY contains the wire OR-ed status of all four receive channel FIFOs, RXRDY A-D. A logic 0 indicates receive data ready status, i.e. the RHR is full or the FIFO has one or more RX characters available for unloading. This pin goes to a logic 1 when the FIFO/RHR is full or when there are no more characters available in either the FIFO or RHR. The 100 pin chip-sets provide both the combined wire ored output and individual channel RXRDY-A-D outputs. RXRDY A-D is discussed in a following paragraph. For 64/68 pin packages, individual channel RX status is read by examining individual internal registers via -CS and A0-A4 pin functions.

-RXRDY A-B - 100,31

-RXRDY C-D - 50,82 - O Receive Ready A-D (active low) - This function is associated with 100 pin packages only. This function provides the RX FIFO/RHR status for individual receive channels (A-D). A logic 0 indicates there is receive data to read/unload, i.e., receive ready status with one or more RX characters available in the FIFO/RHR. This pin is a logic 1 when the FIFO/RHR is empty or when the programmed trigger level has not been reached.

-TXRDY 39 45 - O (active low) - This function is associated with 68 and 100 pin packages only. -TXRDY contains the wire OR-ed status of all four transmit channel FIFOs, TXRDY A-D. A logic 0 indicates a buffer ready status, i.e., at least one location is empty and available in one of the TX channels (A-D). This pin goes to a logic 1 when all four channels have no more empty locations in the TX FIFO or THR. The 100 pin chip-

Rev. 1.00P

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XR16C854

SYMBOL DESCRIPTION

Symbol Pin Signal Pin Description

68 100 64 type

sets provide both the combined wire ored output and individual channel TXRDY-A-D outputs. TXRDY A-D is discussed in a following paragraph For 64/68 pin packages, individual channel TX status can be read by examining individual internal registers via -CS and A0-A4 pin functions.

-TXRDY A-B - 5,25

-TXRDY C-D - 56,81 - O This function is associated with 100 pin packages only. These outputs provide the TX FIFO/THR status for individual transmit channels (A-D). As such, an individual channels -TXRDY A-D buffer ready status is indicated by logic 0, i.e., at least one location is empty and available in the FIFO or THR. This pin goes to a logic 1 when there are no more empty locations in the FIFO or THR.

VCC 13 10 4,21 VCC 47,64 61,86 35,52 I Power supply inputs.

XTAL1 35 40 25 I Crystal or External Clock Input - Functions as a crystal input

or as an external clock input. A crystal can be connected between this pin and XTAL2 to form an internal oscillator circuit (see figure 8). Alternatively, an external clock can be connected to this pin to provide custom data rates (see Baud Rate Generator Programming and optional MIDCLK).

XTAL2 36 41 26 O Output of the Crystal Oscillator or Buffered Clock - (See also

XTAL1). Crystal oscillator output or buffered clock output.

-CD A-B 9,27 99,32 64,18

-CD C-D 43,61 49,83 31,49 I Carrier Detect (active low) - These inputs are associated with individual UART channels A through D. A logic 0 on this pin indicates that a carrier has been detected by the modem for that channel.

-CTS A-B 11,25 8,22 2,16

-CTS C-D 45,59 59,73 33,47 I Clear to Send (active low) - These inputs are associated with individual UART channels, A through D. A logic 0 on the CTS pin indicates the modem or data set is ready to accept transmit data from the 854. Status can be tested by reading

Rev. 1.00P

Page 11

XR16C854

SYMBOL DESCRIPTION

Symbol Pin Signal Pin Description

68 100 64 type

MSR bit-4. This pin only affects the transmit and receive operations when Auto CTS function is enabled via the Enhanced Feature Register (EFR) bit-7, for hardware flow control operation.

-DSR A-B 10,26 7,23 1,17

-DSR C-D 44,60 58,74 32,48 I Data Set Ready (active low) - These inputs are associated with individual UART channels, A through D. A logic 0 on this pin indicates the modem or data set is powered-on and is ready for data exchange with the UART. This pin has no effect on the UARTs transmit or receive operation.

-DTR A-B 12,24 9,21 3,15

-DTR C-D 46,58 60,72 34,46 O Data Terminal Ready (active low) - These inputs are associated with individual UART channels, A through D. A logic 0 on this pin indicates that the 854 is powered-on and ready. This pin can be controlled via the modem control register. Writing a logic 1 to MCR bit-0 will set the -DTR output to logic 0, enabling the modem. This pin will be a logic 1 after writing a logic 0 to MCR bit-0, or after a reset. This pin has no effect on the UARTs transmit or receive operation.

-RI A-B 8,28 98,33 63,19

-RI C-D 42,62 48,84 30,50 I Ring Indicator (active low) - These inputs are associated with individual UART channels, A through D. A logic 0 on this pin indicates the modem has received a ringing signal from the telephone line. A logic 1 transition on this input pin will generate an interrupt.

-RTS A-B 14,22 11,19 5,13

-RTS C-D 48,56 62,70 36,44 O Request to Send (active low) - These outputs are associated with individual UART channels, A through D. A logic 0 on the

-RTS pin indicates the transmitter has data ready and waiting to send. Writing a logic 1 in the modem control register (MCR bit-1) will set this pin to a logic 0 indicating data is available. After a reset this pin will be set to a logic

1. This pin only affects the transmit and receive operations when Auto RTS function is enabled via the Enhanced Feature Register (EFR) bit-6, for hardware flow control

Rev. 1.00P

Page 12

XR16C854

SYMBOL DESCRIPTION

Symbol Pin Signal Pin Description

68 100 64 type

operation. RX/IRRX A-B 7,29 97,34 62,20 RX/IRRX C-D 41,63 47,85 29,51 I Receive Data Input RX/IRRX A-D. - These inputs are

associated with individual serial channel data to the

XR16C854. Two user selectable interface options are avail-

able. The first option supports the standard modem inter-

face. The second option provides an Infrared decoder

interface, see figures 2/3. When using the standard modem

interface, the RX signal will be a logic 1 during reset, idle (no

data), or when the transmitter is disabled. The inactive state

(no data) for the Infrared decoder interface is a logic 0. MCR

bit-6 selects the standard modem or infrared interface.

During the local loop-back mode, the RX input pin is

disabled and TX data is internally connected to the UART

RX Input, internally.

TX/IRTX A-B 17,19 14,16 8,10 TX/IRTX C-D 51,53 65,67 39,41 O Transmit Data - These outputs are associated with indi-

vidual serial transmit channel data from the 854. Two user

selectable interface options are available. The first user

option supports a standard modem interface. The second

option provides an Infrared encoder interface, see figures 2/

3. When using the standard modem interface, the TX signal

will be a logic 1 during reset, idle (no data), or when the

transmitter is disabled. The inactive state (no data) for the

Infrared encoder/ decoder interface is a Logic 0. MCR bit-

6 selects the standard modem or infrared interface. During

the local loop-back mode, the TX input pin is disabled and

TX data is internally connected to the UART RX Input.

Rev. 1.00P

Page 13

XR16C854

GENERAL DESCRIPTION

The 854 provides serial asynchronous receive data synchronization, parallel-to-serial and serial-to-parallel data conversions for both the transmitter and receiver sections. These functions are necessary for converting the serial data stream into parallel data that is required with digital data systems. Synchronization for the serial data stream is accomplished by adding start and stops bits to the transmit data to form a data character (character orientated protocol). Data integrity is insured by attaching a parity bit to the data character. The parity bit is checked by the receiver for any transmission bit errors. The electronic circuitry to provide all these functions is fairly complex especially when manufactured on a single integrated silicon chip. The XR16C854 represents such an integration with greatly enhanced features. The 854 is fabricated with an advanced CMOS process to achieve low drain power and high speed requirements.

The 854 is an upward solution that provides 128 bytes of transmit and receive FIFO memory, instead of 64 bytes provided in ST16C654, 16 bytes provided in the 16/68C554, or none in the 16/68C454. The 854 is designed to work with high speed modems and shared network environments, that require fast data processing time. Increased performance is realized in the 854 by the larger transmit and receive FIFOs. This allows the external processor to handle more networking tasks within a given time. For example, the ST16C554 with a 16 byte FIFO, unloads 16 bytes of receive data in 1.53 ms (This example uses a character length of 11 bits, including start/stop bits at 115.2Kbps). This means the external CPU will have to service the receive FIFO at 1.53 ms intervals. However with the 128 byte FIFO in the 854, the data buffer will not require unloading/loading for 12.2 ms. This increases the service interval giving the external CPU additional time for other applications and reducing the overall UART interrupt servicing time. In addition, the 4 selectable levels of FIFO trigger interrupt and automatic hardware/software flow control is uniquely provided for maximum data throughput performance especially when operating in a multi-channel environment. The combination of the above greatly reduces the bandwidth requirement of the external controlling CPU, increases performance, and reduces power consumption.

The 854 combines the package interface modes of the 16C554/654 and 68/C554/654 series on a single integrated chip. The 16 mode interface is designed to operate with the Intel type of microprocessor bus while the 68 mode is intended to operate with Motorola, and other popular microprocessors. Following a reset, the 854 is down-ward compatible with the ST16C454/ ST68C454 or the ST68C454/ST68C554 dependent on the state of the interface mode selection pin, 16/-

68.

The 854 is capable of operation to 1.5Mbps with a 24 MHz crystal or external clock input. With a crystal of

14.7464 MHz and through a software option, the user can select data rates up to 460.8Kbps or 921.6Kbps, 8 times faster than the 16C554.

The rich feature set of the 854 is available through internal registers. Automatic hardware/software flow control, selectable transmit and receive FIFO trigger levels, selectable TX and RX baud rates, infrared encoder/decoder interface, modem interface controls, and a sleep mode are all standard features. MCR bit-5 provides a facility for turning off (Xon) software flow control with any incoming (RX) character. In the 16 mode INTSEL and MCR bit-3 can be configured to provide a software controlled or continuous interrupt capability. Due of pin limitations for the 64 pin 854 this feature is offered by two different QFP packages. The XR16C854DCV operates in the continuos interrupt enable mode by bonded INTSEL to VCC internally. The XR16C854CV operates in conjunction with MCR bit-3 by bonding INTSEL to GND internally.

The 68 and 100 pin XR16C854 packages offer a clock select pin to allow system/board designers to preset the default baud rate table. The CLKSEL pin selects the 1X or 4X pre-scaleable baud rate generator table during initialization, but can be overridden following initialization by MCR bit-7.

The 100 pin packages offer several enhances features. These features include an MIDI clock input, an internal FIFO monitor register, and separate IrDA TX outputs. The MIDI (Musical Instrument Digital Interface) can be connected to the XTAL2 pin for normal

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XR16C854

operation or to external MIDI oscillator for MIDI applications. A separate register is provided for monitoring the real time status of the FIFO signals -TXRDY and

-RXRDY for each of the four UART channels (A-D). This reduces polling time involved in accessing individual channels. The 100 pin QFP package also offers, four separate IrDA (Infrared Data Association Standard) outputs for Infrared applications. These outputs are provided in addition to the standard asynchronous modem data outputs.

FUNCTIONAL DESCRIPTIONS

Interface Options

Two user interface modes are selectable for the 854 package. These interface modes are designated as the 16 mode and the 68 mode. This nomenclature corresponds to the early 16C554/654 and 68C554/ 654 package interfaces respectively.

The 16 Mode Interface

The 16 mode configures the package interface pins for connection as a standard 16 series (Intel) device and operates similar to the standard CPU interface available on the 16C554/654. In the 16 mode (pin 16/-68 logic 1) each UART is selected with individual chip select (CSx) pins as shown in Table 2 below.

Table 2, SERIAL PORT CHANNEL SELECTION GUIDE, 16 MODE INTERFACE

-CSA -CSB -CSC -CSD UART CHANNEL

1111 None 0111 A 1011 B 1101 C 1110 D

The 68 Mode Interface

The 68 mode configures the package interface pins for connection with Motorola, and other popular microprocessor bus types. The interface operates similar to the 68C554/654. In this mode the 854 decodes two additional addresses, A3-A4 to select one of the four UART ports. The A3-A4 address decode function is used only when in the 68 mode (16/-68 logic 0), and is shown in Table 3 below.

Table 3, SERIAL PORT CHANNEL SELECTION GUIDE, 68 MODE INTERFACE

-CS A4 A3 UART CHANNEL

1 N/A N/A None 000 A 001 B 010 C 011 D

Internal Registers

The 854 provides 15 (64/68 pin packages) or 16 (100 pin packages) internal registers for monitoring and control. These resisters are shown in Table 4 below. Twelve registers are similar to those already available in the standard 16C554. These registers function as data holding registers (THR/RHR), interrupt status and control registers (IER/ISR), a FIFO control register (FCR), line status and control registers (LCR/LSR), modem status and control registers (MCR/MSR), programmable data rate (clock) control registers (DLL/ DLM), and a user assessable scratchpad register (SPR). Beyond the general 16C554 features and capabilities, the 854 offers an enhanced feature register set (EFR, Xon/Xoff 1-2) that provides on board hardware/software flow control. Register functions are more fully described in the following paragraphs.

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XR16C854

Table 4, INTERNAL REGISTER DECODE

A2 A1 A0 READ MODE WRITE MODE

General Register Set (THR/RHR, IER/ISR, MCR/MSR, LCR/LSR, SPR):

0 0 0 Receive Holding Register Transmit Holding Register 0 0 1 Interrupt Enable Register 0 1 0 Interrupt Status Register FIFO Control Register 0 1 1 Line Control Register 1 0 0 Modem Control Register 1 0 1 Line Status Register 1 1 0 Modem Status Register 1 1 1 Scratchpad Register Scratchpad Register

Baud Rate Register Set (DLL/DLM): Note *2

0 0 0 LSB of Divisor Latch LSB of Divisor Latch 0 0 1 MSB of Divisor Latch MSB of Divisor Latch

Enhanced Register Set (EFR, Xon/off 1-2): Note *3

0 0 0 FIFO Trigger Register FIFO trigger counter 0 0 1 Feature Control Register 0 1 0 Enhanced Feature Register Enhanced Feature Register 1 0 0 Xon-1 Word Xon-1 Word 1 0 1 Xon-2 Word Xon-2 Word 1 1 0 Xoff-1 Word Xoff-1 Word 1 1 1 Xoff-2 Word Xoff-2 Word

FIFO Ready Register: Note *4

X X X RXRDY (A-D), TXRDY (A-D)

Note *2: These registers are accessible only when LCR bit-7 is set to a logic 1. Note *3: Enhanced Feature Register, Xon 1,2 and Xoff 1,2 are accessible only when the LCR is set to BF(HEX). Note *4: FIFO Ready Register is available through the CSRDY interface pin only.

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XR16C854

FIFO Operation

The 128 byte transmit and receive data FIFOs are enabled by the FIFO Control Register (FCR) bit-0. With 16C554 devices, the user can set the receive trigger level but not the transmit trigger level. The 854 provides independent trigger levels for both receiver and transmitter. To remain compatible with ST16C554, the transmit interrupt trigger level is set to 8 following a reset. It should be noted that the user can set the transmit trigger levels by writing to the FCR register, but activation will not take place until EFR bit4 is set to a logic 1. The receiver FIFO section includes a time-out function to ensure data is delivered to the external CPU. An interrupt is generated whenever the Receive Holding Register (RHR) has not been read following the loading of a character or the receive trigger level has not been reached. (see hardware flow control for a description of this timing).

Hardware Flow Control

When automatic hardware flow control is enabled, the 854 monitors the -CTS pin for a remote buffer overflow indication and controls the -RTS pin for local buffer overflows. Automatic hardware flow control is selected by setting bits 6 (RTS) and 7 (CTS) of the EFR register to a logic 1. If -CTS transitions from a logic 0 to a logic 1 indicating a flow control request, ISR bit5 will be set to a logic 1 (if enabled via IER bit 6-7), and the 854 will suspend TX transmissions as soon as the stop bit of the character in process is shifted out. Transmission is resumed after the -CTS input returns to a logic 0, indicating more data may be sent.

With the Auto RTS function enabled, an interrupt is generated when the receive FIFO reaches the programmed trigger level. The -RTS pin will not be forced to a logic 1 (RTS Off), until the receive FIFO reaches the next trigger level. However, the -RTS pin will return to a logic 0 after the data buffer (FIFO) is unloaded to the next trigger level below the programmed trigger. However, under the above described conditions the 854 will continue to accept data until the receive FIFO is full.

Selected INT -RTS -RTS

Trigger Pin Logic 1 Logic 0

Level Activation (characters) (characters)

(characters)

88 16 0 16 16 56 8 56 56 60 16 60 60 60 56

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XR16C854

Software Flow Control

When software flow control is enabled, the 854 compares one or two sequential receive data characters with the programmed Xon or Xoff-1,2 character value(s). If receive character(s) (RX) match the programmed values, the 854 will halt transmission (TX) as soon as the current character(s) has completed transmission. When a match occurs, the receive ready (if enabled via Xoff IER bit-5) flags will be set and the interrupt output pin (if receive interrupt is enabled) will be activated. Following a suspension due to a match of the Xoff characters values, the 854 will monitor the receive data stream for a match to the Xon-1,2 character value(s). If a match is found, the 854 will resume operation and clear the flags (ISR bit-

4). The 854 offers a special Xon mode via MCR bit-5. The initialized default setting of MCR bit-5 is a logic 0. In this state Xoff and Xon will operate as defined above. Setting MCR bit-5 to a logic 1 sets a special operational mode for the Xon function. In this case Xoff operates normally however, transmission (Xon) will resume with the next character received, i.e., a match is declared simply by the receipt of an incoming (RX) character.

Special Feature Software Flow Control

A special feature is provided to detect an 8-bit character when bit-5 is set in the Enhanced Feature Register (EFR). When 8 bit character is detected, it will be placed on the user accessible data stack along with normal incoming RX data. This condition is selected in conjunction with EFR bits 0-3. Note that software flow control should be turned off when using this special mode by setting EFR bit 0-3 to a logic 0.

The 854 compares each incoming receive character with Xoff-2 data. If a match exists, the received data will be transferred to FIFO and ISR bit-4 will be set to indicate detection of special character (see Figure 9). Although the Internal Register Table shows each XRegister with eight bits of character information, the actual number of bits is dependent on the programmed word length. Line Control Register (LCR) bits 0-1 defines the number of character bits, i.e., either 5 bits, 6 bits, 7 bits, or 8 bits. The word length selected by LCR bits 0-1 also determines the number of bits that will be used for the special character comparison. Bit-0 in the X-registers corresponds with the LSB bit for the receive character.

Reset initially sets the contents of the Xon/Xoff 8-bit flow control registers to a logic 0. Following reset the user can write any Xon/Xoff value desired for software flow control. Different conditions can be set to detect Xon/Xoff characters and suspend/resume transmissions. When double 8-bit Xon/Xoff characters are selected, the 854 compares two consecutive receive characters with two software flow control 8-bit values (Xon1, Xon2, Xoff1, Xoff2) and controls TX transmissions accordingly. Under the above described flow control mechanisms, flow control characters are not placed (stacked) in the user accessible RX data buffer or FIFO.

In the event that the receive buffer is overfilling and flow control needs to be executed, the 854 automatically sends an Xoff message (when enabled) via the serial TX output to the remote modem. The 854 sends the Xoff-1,2 characters as soon as received data passes the programmed trigger level. To clear this condition, the 854 will transmit the programmed Xon1,2 characters as soon as receive data drops below the programmed trigger level.

Rev. 1.00P

Xon Any Feature

A special feature is provided to return the Xoff flow control to the inactive state following its activation. In this mode any RX character received will return the Xoff flow control to the inactive state so that transmissions may be resumed with a remote buffer. This feature is more fully defined in the Software Flow Control section.

Device Identification

The XR16C854 provides Device identification and Device Revision code to distinguish the part from others.

To read the identification number from the part, its is required to set the baud rate generator divisor latch to 1 and then set the content of the baud rate generator DLL and DLM registers to 0. Reading the content of the DLM will provide 14 hex for XR16C854 part and reading the content of the DLL will provide the revision of the part.

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XR16C854

Hardware/Software and Timeout Interrupts

Three special interrupts have been added to monitor the hardware and software flow control. The interrupts are enabled by IER bits 5-7. Care must be taken when handling these interrupts. Following a reset the transmitter interrupt is enabled, the 854 will issue an interrupt to indicate that transmit holding register is empty. This interrupt must be serviced prior to continuing operations. The LSR register provides the current singular highest priority interrupt only. It could be noted that CTS and RTS interrupts have lowest interrupt priority. A condition can exist where a higher priority interrupt may mask the lower priority CTS/ RTS interrupt(s). Only after servicing the higher pending interrupt will the lower priority CTS/ RTS interrupt(s) be reflected in the status register. Servicing the interrupt without investigating further interrupt conditions can result in data errors.

When two interrupt conditions have the same priority, it is important to service these interrupts correctly. Receive Data Ready and Receive Time Out have the same interrupt priority (when enabled by IER bit-3). The receiver issues an interrupt after the number of characters have reached the programmed trigger level. In this case the 854 FIFO may hold more characters than the programmed trigger level. Following the removal of a data byte, the user should recheck LSR bit-0 for additional characters. A Receive Time Out will not occur if the receive FIFO is empty. The time out counter is reset at the center of each stop bit received or each time the receive holding register (RHR) is read. The actual time out value is T (Time out length in bits) = 4 X P (Programmed word length) + 12. To convert the time out value to a character value, the user has to consider the complete word length, including data information length, start bit, parity bit, and the size of stop bit, i.e., 1X, 1.5X, or 2X bit times.

Example -B: If the user programs the word length = 7, with parity and one stop bit, the time out will be: T = 4 X 7(programmed word length) + 12 = 40 bit times. Character time = 40 / 10 [ (programmed word length = 7) + (parity = 1) + (stop bit = 1) + (start bit = 1) = 4 characters.

In the 16 mode for 68/100 pin packages, the system/ board designer can optionally provide software controlled three state interrupt operation. This is accomplished by INTSEL and MCR bit-3. When INTSEL interface pin is left open or made a logic 0, MCR bit3 controls the three state interrupt outputs, INT A-D. When INTSEL is a logic 1, MCR bit-3 has no effect on the INT A-D outputs and the package operates with interrupt outputs enabled continuously.

Programmable Baud Rate Generator

The 854 supports high speed modem technologies that have increased input data rates by employing data compression schemes. For example a 33.6Kbps modem that employs data compression may require a

115.2Kbps input data rate. A 128.0Kbps ISDN modem that supports data compression may need an input data rate of 460.8Kbps. The 854 can support a standard data rate of 921.6Kbps.

Figure 8, Crystal oscillator connection

XTAL1

XTAL2

Example -A: If the user programs a word length of 7, with no parity and one stop bit, the time out will be: T = 4 X 7( programmed word length) +12 = 40 bit times. The character time will be equal to 40 / 9 = 4.4 characters, or as shown in the fully worked out example: T = [(programmed word length = 7) + (stop bit = 1) + (start bit = 1) = 9]. 40 (bit times divided by 9) =

4.4 characters.

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1.8432 MHz

C1 22pF

C2 33pF

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XR16C854

Single baud rate generator is provided for the transmitter and receiver, allowing independent TX/ RX channel control. The programmable Baud Rate Generator is capable of accepting an input clock up to 24 MHz, as required for supporting a 1.5Mbps data rate. The 854 can be configured for internal or external clock operation. For internal clock oscillator operation, an industry standard microprocessor crystal (parallel resonant/ 22-33 pF load) is connected externally between the XTAL1 and XTAL2 pins (see figure ). Alternatively, an external clock can be connected to the XTAL1 pin to clock the internal baud rate generator for standard or custom rates. (see Baud Rate Generator Programming).

The generator divides the input 16X clock by any divisor from 1 to 216 -1. The 854 divides the basic crystal or external clock by 16. Further division of this 16X clock provides two table rates to support low and

high data rate applications using the same system design. After a hardware reset and during initialization, the 854 sets the default baud rate table according to the state of the CLKSEL. pin. A logic 1 on CLKSEL will set the 1X clock default whereas, logic 0 will set the 4X clock default table. Following the default clock rate selection during initialization, the rate tables can be changed by the internal register, MCR bit-7. Setting MCR bit-7 to a logic 1 when CLKSEL is a logic 1 provides an additional divide by 4 whereas, setting MCR bit-7 to a logic 0 only divides by 1. (See Table 5 and Figure 11). Customized Baud Rates can be achieved by selecting the proper divisor values for the MSB and LSB sections of baud rate generator.

Programming the Baud Rate Generator Registers DLM (MSB) and DLL (LSB) provides a user capability for selecting the desired final baud rate. The example in Table 5 below, shows the two selectable baud rate tables available when using a 7.3728 MHz crystal.

Table 5, BAUD RATE GENERATOR PROGRAMMING TABLE (7.3728 MHz CLOCK):

Output Output User User DLM DLL

Baud Rate Baud Rate 16 x Clock 16 x Clock Program Program

MCR MCR Divisor Divisor Value Value

BIT-7=1 Bit-7=0 (Decimal) (HEX) (HEX) (HEX)

50 200 2304 900 09 00 300 1200 384 180 01 80 600 2400 192 C0 00 C0

1200 4800 96 60 00 60 2400 9600 48 30 00 30 4800 19.2K 24 18 00 18 9600 38.4k 12 0C 00 0C

19.2k 76.8k 6 06 00 06

38.4k 153.6k 3 03 00 03

57.6k 230.4k 2 02 00 02

115.2k 460.8k 1 01 00 01

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XR16C854

TAL1 TAL2

Clock

Oscillator

Logic

Figure 11, Baud Rate Generator Circuitry

MCR

Divide

Bit-7=0

1 logic

Divide

4 logic

MCR Bit-7=1

Baudrate

Generator

Logic

-BAUDOU

DMA Operation

The 854 FIFO trigger level provides additional flexibility to the user for block mode operation. LSR bits 5-6 provide an indication when the transmitter is empty or has an empty location(s). The user can optionally operate the transmit and receive FIFOs in the DMA mode (FCR bit-3). When the transmit and receive FIFOs are enabled and the DMA mode is deactivated (DMA Mode 0), the 854 activates the interrupt output pin for each data transmit or receive operation. When DMA mode is activated (DMA Mode 1), the user takes the advantage of block mode operation by loading or unloading the FIFO in a block sequence determined by the preset trigger level. In this mode, the 854 sets the interrupt output pin when characters in the transmit FIFOs are below the transmit trigger level, or the characters in the receive FIFOs are above the receive trigger level.

Rev. 1.00P

Sleep Mode

The 854 is designed to operate with low power consumption. A special sleep mode is included to further reduce power consumption when the chip is not being used. With EFR bit-4 and IER bit-4 enabled (set to a logic 1), the 854 enters the sleep mode but resumes normal operation when a start bit is detected, a change of state on any of the modem input pins RX, -RI, -CTS,

-DSR, -CD, or transmit data is provided by the user. If the sleep mode is enabled and the 854 is awakened by one of the conditions described above, it will return to the sleep mode automatically after the last character is transmitted or read by the user. In any case, the sleep mode will not be entered while an interrupt(s) is pending. The 854 will stay in the sleep mode of operation until it is disabled by setting IER bit-4 to a logic 0.

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Loop-back Mode

The internal loop-back capability allows onboard diagnostics. In the loop-back mode the normal modem interface pins are disconnected and reconfigured for loop-back internally. MCR register bits 0-3 are used for controlling loop-back diagnostic testing. In the loop-back mode OP1 and OP2 in the MCR register (bits 3/2) control the modem -RI and -CD inputs respectively. MCR signals -DTR and -RTS (bits 0-1) are used to control the modem -CTS and -DSR inputs respectively. The transmitter output (TX) and the receiver input (RX) are disconnected from their associated interface pins, and instead are connected together internally (See Figure 12). The -CTS, -DSR, CD, and -RI are disconnected from their normal modem control inputs pins, and instead are connected internally to -DTR, -RTS, -OP1 and -OP2. Loop-back test data is entered into the transmit holding register via the user data bus interface, D0-D7. The transmit UART serializes the data and passes the serial data to the receive UART via the internal loop-back connection. The receive UART converts the serial data back into parallel data that is then made available at the user data interface, D0-D7. The user optionally compares the received data to the initial transmitted data for verifying error free operation of the UART TX/RX circuits.

XR16C854

In this mode, the receiver and transmitter interrupts are fully operational. The Modem Control Interrupts are also operational. However, the interrupts can only be read using lower four bits of the Modem Control Register (MCR bits 0-3) instead of the four Modem Status Register bits 4-7. The interrupts are still controlled by the IER.

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XR16C854

Figure 12, INTERNAL LOOP-BACK MODE DIAGRAM

D0-D7

-IOR,-IOW RESET

A0-A2

-CS A-D

Transmit

FIFO

Registers

Data bus

Control Logic

Logic

Select

Control signals

Flow

Control

Logic

Receive

FIFO

Registers

Flow

Control

Logic

Transmit

Shift

Encoder

Receive

Shift

Decoder

TX A-D

MCR Bit-4=1

RX A-D

-RTS A-D

INT A-D

-RXRDY

-TXRDY

XTAL1 XTAL2

Rev. 1.00P

Inter C onnect Bus Lines

Logic

Control

Interrupt

Modem Control Logic

Clock

Generator

Baud Rate

-CD A-D

-DTR A-D

-RI A-D

-OP1 A-D

-DSR A-D

-OP2 A-D

-CTS A-D

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XR16C854

The following table delineates the assigned bit functions for the fifteen 854 internal registers. The assigned bit functions are more fully defined in the following paragraphs.

XR16C854 ACCESSIBLE REGISTERS

A2 A1 A0 Register BIT-7 BIT-6 BIT-5 BIT-4 BIT-3 BIT-2 BIT-1 BIT-0

[Default]

Note *5

General Register Set

0 0 0 RHR [XX] bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0

0 0 0 THR [XX] bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0

0 0 1 IER [00] 0/ 0/ 0/ 0/ modem receive transmit receive

0 1 0 FCR [00] RCVR RCVR 0/TX 0/TX DMA XMIT RCVR FIFO

0 1 0 ISR [01] 0/ 0/ 0/ 0/ int int int int

0 1 1 LCR [00] divisor set set even parity stop word word

1 0 0 MCR [00] Clock 0/ 0/ loop -OP2 -OP1 -RTS -DTR

-CTS -RTS Xoff Sleep status line holding holding

int errup t i nter rupt in terr upt mode inte rrupt status register register

interrupt

trigger trigger trigger trigger mode FIFO FIFO enable (MSB) (LSB) (MSB) (LSB) select reset reset

FIFOs FIFOs -RTS, Xoff priority priority priority status

enabled enabled -CTS bit-2 bit-1 bit-0

latch break parity parity enable bits length length

enable bit-1 bit-0

select IRRT Xon back

enable Any

1 0 1 LSR [60] 0/ trans. trans. break framing parity overrun receive

1 1 0 MSR [X0] -CD -RI -DSR -CTS delta delta delta delta

1 1 1 SCPAD [FF] bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0

FIFO empty holding interrupt error error error data

error empty ready

-CD -RI -DSR -CTS

Special Register Set Note *2

0 0 0 DLL [XX] bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0

0 0 1 DLM [XX] bit-15 bit-14 bit-13 bit-12 bit-11 bit-10 bit-9 bit-8

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XR16C854

A2 A1 A0 Register BIT-7 BIT-6 BIT-5 BIT-4 BIT-3 BIT-2 BIT-1 BIT-0

[Default]

Note *5

Enhanced Register Set Note*3

0 0 0 TRG [00] Trig/ Trig/ Trig/ Trig/ Trig Trig/ Trig/ Trig/

0 0 1 FCTR [00] Rx/Tx SCPAD Trig Trig RS-485 IrRx -RTS -RTS

0 1 0 EFR [00] Auto Auto Special Enable Cont-3 Cont-2 Cont-1 Cont-0

1 1 1 EMSR [00] Not Not Not Not Not Not ALT. Rx/-Tx

1 0 0 Xon-1[00] bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 1 0 1 Xon-2[00] bit-15 bit-14 bit-13 bit-12 bit-11 bit-10 bit-9 bit-8 1 1 0 Xoff-1[00] bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 1 1 1 Xoff-2[00] bit-15 bit-14 bit-13 bit-12 bit-11 bit-10 bit-9 bit-8

FC FC FC FC FC FC FC FC

Mode Swap Bit-1 Bit-0 Auto Inv. Delay Delay

control Bit-1 Bit-0

-CTS -RTS Char. IER Tx,Rx Tx,Rx Tx,Rx Tx,Rx select Bits 4-7, Control Control Control Control

ISR, FCR

Bits 4-5,

MCR

Bits 5-7

Used Used Used Used Used Used Rx/Tx FIFO

FIFO Count

Count

FIFO Ready Register: Note *4

X X X FIFORdy RXRDY RXRDY RXRDY RXRDY TXRDY TXRDY TXRDY TXRDY

DCBADCBA

Note *2: The Special register set is accessible only when LCR bit-7 is set to 1. Note *3: Enhanced Feature Register, Xon 1,2 and Xoff 1,2 are accessible only when LCR is set to BF HEX. Note *4: FIFORdy register is available only in 100 pin QFP packages and is selected by -CSRDY vice A0-A2. Note *5: The value between the square brackets represents the registers initialized HEX value.

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XR16C854

Transmit (THR) and Receive (RHR) Holding Registers

The serial transmitter section consists of an 8-bit Transmit Hold Register (THR) and Transmit Shift Register (TSR). The status of the THR is provided in the Line Status Register (LSR). Writing to the THR transfers the contents of the data bus (D7-D0) to the THR, providing that the THR or TSR is empty. The THR empty flag in the LSR register will be set to a logic 1 when the transmitter is empty or when data is transferred to the TSR. Note that a write operation can be performed when the transmit holding register empty flag is set (logic 0 = FIFO full, logic 1= at least one FIFO location available).

The serial receive section also contains an 8-bit Receive Holding Register, RHR. Receive data is removed from the 854 and receive FIFO by reading the RHR register. The receive section provides a mechanism to prevent false starts. On the falling edge of a start or false start bit, an internal receiver counter starts counting clocks at 16x clock rate. After 7 1/2 clocks the start bit time should be shifted to the center of the start bit. At this time the start bit is sampled and if it is still a logic 0 it is validated. Evaluating the start bit in this manner prevents the receiver from assembling a false character. Receiver status codes will be posted in the LSR.

Interrupt Enable Register (IER)

The Interrupt Enable Register (IER) masks the interrupts from receiver ready, transmitter empty, line status and modem status registers. These interrupts would normally be seen on the INT A-D output pins in the 16 mode, or on WIRE-OR IRQ output pin, in the 68 mode.

IER Vs Receive FIFO Interrupt Mode Operation

When the receive FIFO (FCR BIT-0 = a logic 1) and receive interrupts (IER BIT-0 = logic 1) are enabled, the receive interrupts and register status will reflect the following:

FIFO drops below the programmed trigger level.

B) FIFO status will also be reflected in the user accessible ISR register when the FIFO trigger level is reached. Both the ISR register status bit and the interrupt will be cleared when the FIFO drops below the trigger level.

C) The data ready bit (LSR BIT-0) is set as soon as a character is transferred from the shift register to the receive FIFO. It is reset when the FIFO is empty.

IER Vs Receive/Transmit FIFO Polled Mode Operation

When FCR BIT-0 equals a logic 1; resetting IER bits 0-3 enables the 854 in the FIFO polled mode of operation. Since the receiver and transmitter have separate bits in the LSR either or both can be used in the polled mode by selecting respective transmit or receive control bit(s).

A) LSR BIT-0 will be a logic 1 as long as there is one byte in the receive FIFO.

B) LSR BIT 1-4 will provide the type of errors encountered, if any.

C) LSR BIT-5 will indicate when the transmit FIFO is empty.

D) LSR BIT-6 will indicate when both the transmit FIFO and transmit shift register are empty.

E) LSR BIT-7 will indicate any FIFO data errors.

IER BIT-0:

This interrupt will be issued when the FIFO has reached the programmed trigger level or is cleared when the FIFO drops below the trigger level in the FIFO mode of operation. Logic 0 = Disable the receiver ready interrupt. (normal default condition) Logic 1 = Enable the receiver ready interrupt.

A) The receive data available interrupts are issued to the external CPU when the FIFO has reached the programmed trigger level. It will be cleared when the

Rev. 1.00P

IER BIT-1:

This interrupt will be issued whenever the THR is empty and is associated with bit-1 in the LSR register.

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XR16C854

Logic 0 = Disable the transmitter empty interrupt. (normal default condition) Logic 1 = Enable the transmitter empty interrupt.

IER BIT-2:

This interrupt will be issued whenever a fully assembled receive character is transferred from the RSR to the RHR/FIFO, i.e., data ready, LSR bit-0. Logic 0 = Disable the receiver line status interrupt. (normal default condition) Logic 1 = Enable the receiver line status interrupt.

IER BIT-3:

Logic 0 = Disable the modem status register interrupt. (normal default condition) Logic 1 = Enable the modem status register interrupt.

IER BIT -4:

Logic 0 = Disable sleep mode. (normal default condition) Logic 1 = Enable sleep mode. See Sleep Mode section for details.

IER BIT-5:

Logic 0 = Disable the software flow control, receive Xoff interrupt. (normal default condition) Logic 1 = Enable the software flow control, receive Xoff interrupt. See Software Flow Control section for details.

IER BIT-6:

Logic 0 = Disable the RTS interrupt. (normal default condition) Logic 1 = Enable the RTS interrupt. The 854 issues an interrupt when the RTS pin transitions from a logic 0 to a logic 1.

IER BIT-7:

Logic 0 = Disable the CTS interrupt. (normal default condition) Logic 1 = Enable the CTS interrupt. The 854 issues an interrupt when CTS pin transitions from a logic 0 to a logic 1.

DMA MODE

Mode 0 Set and enable the interrupt for each single transmit or receive operation, and is similar to the ST16C454 mode. Transmit Ready (-TXRDY) will go to a logic 0 when ever an empty transmit space is available in the Transmit Holding Register (THR). Receive Ready (-RXRDY) will go to a logic 0 whenever the Receive Holding Register (RHR) is loaded with a character.

Mode 1 Set and enable the interrupt in a block mode operation. The transmit interrupt is set when the transmit FIFO is below the programmed trigger level.

-TXRDY remains a logic 0 as long as one empty FIFO location is available. The receive interrupt is set when the receive FIFO fills to the programmed trigger level. However the FIFO continues to fill regardless of the programmed level until the FIFO is full. -RXRDY remains a logic 0 as long as the FIFO fill level is above the programmed trigger level.

FCR BIT-0:

Logic 0 = Disable the transmit and receive FIFO. (normal default condition) Logic 1 = Enable the transmit and receive FIFO. This bit must be a 1 when other FCR bits are written to or they will not be programmed.

FCR BIT-1:

Logic 0 = No FIFO receive reset. (normal default condition) Logic 1 = Clears the contents of the receive FIFO and resets the FIFO counter logic (the receive shift register is not cleared or altered). This bit will return to a logic 0 after clearing the FIFO.

FCR BIT-2:

Logic 0 = No FIFO transmit reset. (normal default condition) Logic 1 = Clears the contents of the transmit FIFO and resets the FIFO counter logic (the transmit shift register is not cleared or altered). This bit will return to a logic 0 after clearing the FIFO.

FIFO Control Register (FCR)

This register is used to enable the FIFOs, clear the FIFOs, set the transmit/receive FIFO trigger levels, and select the DMA mode. The DMA, and FIFO modes are defined as follows:

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XR16C854

FCR BIT-3:

Logic 0 = Set DMA mode 0. (normal default condition) Logic 1 = Set DMA mode 1.

Transmit operation in mode 0:

When the 854 is in the ST16C450 mode (FIFOs disabled, FCR bit-0 = logic 0) or in the FIFO mode (FIFOs enabled, FCR bit-0 = logic 1, FCR bit-3 = logic

0) and when there are no characters in the transmit FIFO or transmit holding register, the -TXRDY pin will be a logic 0. Once active the -TXRDY pin will go to a logic 1 after the first character is loaded into the transmit holding register.

Receive operation in mode 0:

When the 854 is in mode 0 (FCR bit-0 = logic 0) or in the FIFO mode (FCR bit-0 = logic 1, FCR bit-3 = logic 0) and there is at least one character in the receive FIFO, the -RXRDY pin will be a logic 0. Once active the -RXRDY pin will go to a logic 1 when there are no more characters in the receiver.

Transmit operation in mode 1:

When the 854 is in FIFO mode ( FCR bit-0 = logic 1, FCR bit-3 = logic 1 ), the -TXRDY pin will be a logic 1 when the transmit FIFO is completely full. It will be a logic 0 if one or more FIFO locations are empty.

Receive operation in mode 1:

When the 854 is in FIFO mode (FCR bit-0 = logic 1, FCR bit-3 = logic 1) and the trigger level has been reached, or a Receive Time Out has occurred, the RXRDY pin will go to a logic 0. Once activated, it will go to a logic 1 after there are no more characters in the FIFO.

TRIGGER TABLE-A (Transmit) Default setting after reset ST16C550 mode

BIT-5 BIT-4 FIFO trigger level

X X None

TRIGGER TABLE-B (Transmit)

BIT-5 BIT-4 FIFO trigger level

00 16 01 8 10 24 11 30

TRIGGER TABLE-C (Transmit)

BIT-5 BIT-4 FIFO trigger level

00 8 01 16 10 32 11 56

TRIGGER TABLE-D (Transmit)

BIT-5 BIT-4 FIFO trigger level

X X User programmable

Trigger levels

FCR BIT 4-5: (logic 0 or cleared is the default condition, TX trigger level = none)

The XR16C854 provide 4 user selectable trigger levels, The FCTR Bits 4-5 selects one of the following table. These bits are used to set the trigger level for the transmit FIFO interrupt. The XR16C854 will issue a transmit empty interrupt when number of characters in FIFO drops below the selected trigger level.

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FCR BIT 6-7: (logic 0 or cleared is the default condition, RX trigger level =8)

These bits are used to set the trigger level for the receiver FIFO interrupt. The FCTR Bits 4-5 selects one of the following table.

TRIGGER TABLE-A (Receive) Default setting after reset ST16C550 mode

BIT-7 BIT-6 FIFO trigger level

00 1 01 4 10 8 11 14

TRIGGER TABLE-B (Receive)

BIT-7 BIT-6 FIFO trigger level

00 8 01 16 10 24 11 28

Interrupt Status Register (ISR)

The 854 provides six levels of prioritized interrupts to minimize external software interaction. The Interrupt Status Register (ISR) provides the user with six interrupt status bits. Performing a read cycle on the ISR will provide the user with the highest pending interrupt level to be serviced. No other interrupts are acknowledged until the pending interrupt is serviced. Whenever the interrupt status register is read, the interrupt status is cleared. However it should be noted that only the current pending interrupt is cleared by the read. A lower level interrupt may be seen after rereading the interrupt status bits. The Interrupt Source Table 7 (below) shows the data values (bit 0-5) for the six prioritized interrupt levels and the interrupt sources associated with each of these interrupt levels:

TRIGGER TABLE-C (Receive)

BIT-7 BIT-6 FIFO trigger level

00 8 01 16 10 56 11 60

TRIGGER TABLE-D (Receive)

BIT-7 BIT-6 FIFO trigger level

X X User programmable

Trigger levels

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XR16C854

Table 7, INTERRUPT SOURCE TABLE

Priority [ ISR BITS ]

Level Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0 Source of the interrupt

1 000110 LSR (Receiver Line Status Register) 2 000100 RXRDY (Received Data Ready) 2 001100 RXRDY (Receive Data time out) 3 000010 TXRDY ( Transmitter Holding Register Empty) 4 000000 MSR (Modem Status Register) 5 010000 RXRDY (Received Xoff signal)/ Special character 6 100000 CTS, RTS change of state

ISR BIT-0:

Logic 0 = An interrupt is pending and the ISR contents may be used as a pointer to the appropriate interrupt service routine. Logic 1 = No interrupt pending. (normal default condition)

ISR BIT 1-3: (logic 0 or cleared is the default condition)

These bits indicate the source for a pending interrupt at interrupt priority levels 1, 2, and 3 (See Interrupt Source Table).

ISR BIT 4-5: (logic 0 or cleared is the default condition)

These bits are enabled when EFR bit-4 is set to a logic

1. ISR bit-4 indicates that matching Xoff character(s) have been detected. ISR bit-5 indicates that CTS, RTS have been generated. Note that once set to a logic 1, the ISR bit-4 will stay a logic 1 until Xon character(s) are received.

ISR BIT 6-7: (logic 0 or cleared is the default condition)

These bits are set to a logic 0 when the FIFO is not being used. They are set to a logic 1 when the FIFOs are enabled.

Line Control Register (LCR)

LCR BIT 0-1: (logic 0 or cleared is the default condition)

These two bits specify the word length to be transmitted or received.

BIT-1 BIT-0 Word length

00 5 01 6 10 7 11 8

LCR BIT-2: (logic 0 or cleared is the default condition)

The length of stop bit is specified by this bit in conjunction with the programmed word length.

BIT-2 Word length Stop bit

length

(Bit time(s))

0 5,6,7,8 1 1 5 1-1/2 1 6,7,8 2

The Line Control Register is used to specify the asynchronous data communication format. The word length, the number of stop bits, and the parity are selected by writing the appropriate bits in this register.

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XR16C854

LCR BIT-3:

Parity or no parity can be selected via this bit. Logic 0 = No parity. (normal default condition) Logic 1 = A parity bit is generated during the transmission, receiver checks the data and parity for transmission errors.

LCR BIT-4:

If the parity bit is enabled with LCR bit-3 set to a logic 1, LCR BIT-4 selects the even or odd parity format. Logic 0 = ODD Parity is generated by forcing an odd number of logic 1s in the transmitted data. The receiver must be programmed to check the same format. (normal default condition) Logic 1 = EVEN Parity is generated by forcing an even the number of logic 1s in the transmitted. The receiver must be programmed to check the same format.

LCR BIT-5:

If the parity bit is enabled, LCR BIT-5 selects the forced parity format. LCR BIT-5 = logic 0, parity is not forced. (normal default condition) LCR BIT-5 = logic 1 and LCR BIT-4 = logic 0, parity bit is forced to a logical 1 for the transmit and receive data. LCR BIT-5 = logic 1 and LCR BIT-4 = logic 1, parity bit is forced to a logical 0 for the transmit and receive data.

LCR LCR LCR Parity selection

Bit-5 Bit-4 Bit-3

Logic 1 = Forces the transmitter output (TX) to a logic 0 for alerting the remote receiver to a line break condition.

LCR BIT-7:

The internal baud rate counter latch and Enhance Feature mode enable. Logic 0 = Divisor latch disabled. (normal default condition) Logic 1 = Divisor latch and enhanced feature register enabled.

Modem Control Register (MCR)

This register controls the interface with the modem or a peripheral device.

MCR BIT-0:

Logic 0 = Force -DTR output to a logic 1. (normal default condition) Logic 1 = Force -DTR output to a logic 0.

MCR BIT-1:

Logic 0 = Force -RTS output to a logic 1. (normal default condition) Logic 1 = Force -RTS output to a logic 0. Automatic RTS may be used for hardware flow control by enabling EFR bit-6 (See EFR bit-6).

MCR BIT-2:

This bit is used in the Loop-back mode only. In the loop-back mode this bit is use to write the state of the modem -RI interface signal via -OP1.

X X 0 No parity

0 0 1 Odd parity 0 1 1 Even parity 1 0 1 Force parity 1 1 1 1 Forced parity 0

LCR BIT-6:

When enabled the Break control bit causes a break condition to be transmitted (the TX output is forced to a logic 0 state). This condition exists until disabled by setting LCR bit-6 to a logic 0. Logic 0 = No TX break condition. (normal default condition)

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MCR BIT-3: (Used to control the modem -CD signal in the loop-back mode.) Logic 0 = Forces INT (A-D) outputs to the three state mode during the 16 mode. (normal default condition) In the Loop-back mode, sets -OP2 (-CD) internally to a logic 1. Logic 1 = Forces the INT (A-D) outputs to the active mode during the 16 mode. In the Loop-back mode, sets -OP2 (-CD) internally to a logic 0.

MCR BIT-4:

Logic 0 = Disable loop-back mode. (normal default condition) Logic 1 = Enable local loop-back mode (diagnostics).

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XR16C854

MCR BIT-5:

Logic 0 = Disable Xon any function (for 16C550 compatibility). (normal default condition) Logic 1 = Enable Xon any function. In this mode any RX character received will enable Xon.

MCR BIT-6:

Logic 0 = Enable the standard modem receive and transmit input/output interface. (normal default condition) Logic 1 = Enable infrared IrDA receive and transmit inputs/outputs. While in this mode, the TX/RX output/ Inputs are routed to the infrared encoder/decoder. The data input and output levels will conform to the IrDA infrared interface requirement. As such, while in this mode the infrared TX output will be a logic 0 during idle data conditions.

MCR BIT-7:

Logic 0 = Divide by one. The input clock (crystal or external) is divided by sixteen and then presented to the Programmable Baud Rate Generator (BGR) without further modification, i.e., divide by one. (normal, default condition) Logic 1 = Divide by four. The divide by one clock described in MCR bit-7 equals a logic 0, is further divided by four (also see Programmable Baud Rate Generator section).

Line Status Register (LSR)

This register provides the status of data transfers between the 854 and the CPU.

LSR BIT-0:

Logic 0 = No data in receive holding register or FIFO. (normal default condition) Logic 1 = Data has been received and is saved in the receive holding register or FIFO.

LSR BIT-1:

Logic 0 = No overrun error. (normal default condition) Logic 1 = Overrun error. A data overrun error occurred in the receive shift register. This happens when additional data arrives while the FIFO is full. In this case the previous data in the shift register is overwritten. Note that under this condition the data byte in the receive shift register is not transferred into the FIFO,

therefore the data in the FIFO is not corrupted by the error.

LSR BIT-2:

Logic 0 = No parity error. (normal default condition) Logic 1 = Parity error. The receive character does not have correct parity information and is suspect. In the FIFO mode, this error is associated with the character at the top of the FIFO.

LSR BIT-3:

Logic 0 = No framing error. (normal default condition) Logic 1 = Framing error. The receive character did not have a valid stop bit(s). In the FIFO mode this error is associated with the character at the top of the FIFO.

LSR BIT-4:

Logic 0 = No break condition. (normal default condition) Logic 1 = The receiver received a break signal (RX was a logic 0 for one character frame time). In the FIFO mode, only one break character is loaded into the FIFO.

LSR BIT-5:

This bit is the Transmit Holding Register Empty indicator. This bit indicates that the UART is ready to accept a new character for transmission. In addition, this bit causes the UART to issue an interrupt to CPU when the THR interrupt enable is set. The THR bit is set to a logic 1 when a character is transferred from the transmit holding register into the transmitter shift register. The bit is reset to logic 0 concurrently with the loading of the transmitter holding register by the CPU. In the FIFO mode this bit is set when the transmit FIFO is empty; it is cleared when at least 1 byte is written to the transmit FIFO.

LSR BIT-6:

This bit is the Transmit Empty indicator. This bit is set to a logic 1 whenever the transmit holding register and the transmit shift register are both empty. It is reset to logic 0 whenever either the THR or TSR contains a data character. In the FIFO mode this bit is set to one whenever the transmit FIFO and transmit shift register are both empty.

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XR16C854

LSR BIT-7:

Logic 0 = No Error. (normal default condition) Logic 1 = At least one parity error, framing error or break indication is in the current FIFO data. This bit is cleared when LSR register is read.

Modem Status Register (MSR)

This register provides the current state of the control interface signals from the modem, or other peripheral device that the 854 is connected to. Four bits of this register are used to indicate the changed information. These bits are set to a logic 1 whenever a control input from the modem changes state. These bits are set to a logic 0 whenever the CPU reads this register.

MSR BIT-0:

Logic 0 = No -CTS Change (normal default condition) Logic 1 = The -CTS input to the 854 has changed state since the last time it was read. A modem Status Interrupt will be generated.

MSR BIT-1:

Logic 0 = No -DSR Change. (normal default condition) Logic 1 = The -DSR input to the 854 has changed state since the last time it was read. A modem Status Interrupt will be generated.

modem -CTS signal. A logic 1 at the -CTS pin will stop 854 transmissions as soon as current character has finished transmission.

Normally MSR bit-4 bit is the compliment of the -CTS input. However in the loop-back mode, this bit is equivalent to the RTS bit in the MCR register.

MSR BIT-5:

DSR (active high, logical 1). Normally this bit is the compliment of the -DSR input. In the loop-back mode, this bit is equivalent to the DTR bit in the MCR register.

MSR BIT-6:

RI (active high, logical 1). Normally this bit is the compliment of the -RI input. In the loop-back mode this bit is equivalent to the OP1 bit in the MCR register.

MSR BIT-7:

CD (active high, logical 1). Normally this bit is the compliment of the -CD input. In the loop-back mode this bit is equivalent to the OP2 bit in the MCR register.

Scratchpad Register (SPR)

The XR16C854 provides a temporary data register to store 8 bits of user information.

Enhanced Feature Register (EFR)

MSR BIT-2:

Logic 0 = No -RI Change. (normal default condition) Logic 1 = The -RI input to the 854 has changed from a logic 0 to a logic 1. A modem Status Interrupt will be generated.

MSR BIT-3:

Logic 0 = No -CD Change. (normal default condition) Logic 1 = Indicates that the -CD input to the has changed state since the last time it was read. A modem Status Interrupt will be generated.

MSR BIT-4:

-CTS functions as hardware flow control signal input if it is enabled via EFR bit-7. The transmit holding register flow control is enabled/disabled by MSR bit-4. Flow control (when enabled) allows the starting and stopping the transmissions based on the external

Rev. 1.00P

Enhanced features are enabled or disabled using this register.

Bits-0 through 4 provide single or dual character software flow control selection (see table 8). When the Xon1 and Xon2 and/or Xoff1 and Xoff2 modes are selected, the double 8-bit words are concatenated into two sequential characters.

EFR BIT 0-3: (logic 0 or cleared is the default condition)

Combinations of software flow control can be selected by programming these bits.

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Table 8, SOFTWARE FLOW CONTROL FUNCTIONS

Cont-3 Cont-2 Cont-1 Cont-0 TX, RX software flow controls

0 0 X X No transmit flow control 1 0 X X Transmit Xon1/Xoff1 0 1 X X Transmit Xon2/Xoff2

1 1 X X Transmit Xon1 and Xon2/Xoff1 and Xoff2 X X 0 0 No receive flow control X X 1 0 Receiver compares Xon1/Xoff1 X X 0 1 Receiver compares Xon2/Xoff2 1011Transmit Xon1/ Xoff1.

Receiver compares Xon1 and Xon2, Xoff1 and Xoff2

0111Transmit Xon2/Xoff2

Receiver compares Xon1 and Xon2/Xoff1 and Xoff2

1111Transmit Xon1 and Xon2/Xoff1 and Xoff2

Receiver compares Xon1 and Xon2/Xoff1 and Xoff2

0011No transmit flow control

Receiver compares Xon1 and Xon2/Xoff1 and Xoff2

XR16C854

EFR BIT-4:

Enhanced function control bit. The content of the IER bits 4-7, ISR bits 4-5, FCR bits 4-5, and MCR bits 5-7 can be modified and latched. After modifying any bits in the enhanced registers, EFR bit-4 can be set to a logic 0 to latch the new values. This feature prevents existing software from altering or overwriting the 854 enhanced functions.

Logic 0 = disable/latch enhanced features. IER bits 47, ISR bits 4-5, FCR bits 4-5, and MCR bits 5-7 are saved to retain the user settings, then IER bits 4-7, ISR bits 4-5, FCR bits 4-5, and MCR bits 5-7 are initialized to the default values shown in the Internal Resister Table. After a reset, the IER bits 4-7, ISR bits 4-5, FCR bits 4-5, and MCR bits 5-7 are set to a logic 0 to be compatible with ST16C554 mode. (normal default condition). Logic 1 = Enables the enhanced functions. When this bit is set to a logic 1 all enhanced features of the 854 are enabled and user settings stored during a reset will be restored.

EFR BIT-5:

Logic 0 = Special Character Detect Disabled. (normal default condition) Logic 1 = Special Character Detect Enabled. The 854 compares each incoming receive character with Xoff2 data. If a match exists, the received data will be transferred to FIFO and ISR bit-4 will be set to indicate detection of special character. Bit-0 in the X-registers corresponds with the LSB bit for the receive character. When this feature is enabled, the normal software flow control must be disabled (EFR bits 0-3 must be set to a logic 0).

EFR BIT-6:

Automatic RTS may be used for hardware flow control by enabling EFR bit-6. When AUTO RTS is selected, an interrupt will be generated when the receive FIFO is filled to the programmed trigger level and -RTS will go to a logic 1 at the next trigger level. -RTS will return to a logic 0 when data is unloaded below the next lower trigger level (Programmed trigger level -1). The state of this register bit changes with the status of the

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XR16C854

hardware flow control. -RTS functions normally when hardware flow control is disabled.

0 = Automatic RTS flow control is disabled. (normal default condition) 1 = Enable Automatic RTS flow control.

EFR bit-7:

Automatic CTS Flow Control. Logic 0 = Automatic CTS flow control is disabled. (normal default condition) Logic 1 = Enable Automatic CTS flow control. Transmission will stop when -CTS goes to a logical 1. Transmission will resume when the -CTS pin returns to a logical 0.

FIFO READY REGISTER

This register is applicable to 100 pin XR16C854s only. The FIFO resister provides the real time status of the transmit and receive FIFOs. Each TX and RX cannel (A-D) has its own 128 byte FIFO. When any of the eight TX/RX FIFOs become full, a bit associated with its TX/RX function and channel A-D is set in the FIFO status register.

FIFO channel A-D RDY Bit 0-3:

0 = The transmit FIFO A-D associated with this bit is full. This channel will not accept any more transmit data. 1 = One or more empty locations exist in the FIFO.

FIFORdy Bit 4-7:

0 = The receive FIFO is above the programmed trigger level or time-out is occurred. 1 = Receiver is ready and is below the programmed trigger level.

FEATURE CONTROL REGISTER

This register controls the XR16C854 new functions that are not available on ST16C550 or ST16C650.

FCTR BIT 0-1: User selectable -RTS delay timer for hardware flow control application. After reset, these bits are set to 0 to select the next trigger level for hardware flow control.

FCTR FCTR Trigger

Bit-1 Bit-0 level

0 0 Next trigger

level 0 1 4 word+trigger level 1 0 6 word+trigger level 1 1 8 word+trigger level

FCTR BIT-2: 0 = Select RX input as encoded IrDa data. 1 = Select RX input as active high encoded IrDa data.

FCTR BIT-3: Interrupt type select. 0 = Standard ST16C550 mode. Transmitter generates interrupt when transmit holding register is empty and transmit shift register is shifting data out. 1 = Transmit empty interrupt. Transmit interrupt is generated when transmit holding and shift register is empty.

FCTR BIT 4-5: Transmit / receive trigger table select.

FCTR FCTR Table

Bit-5 Bit-4

0 0 Table-A (TX/RX) 0 1 Table-B (TX/RX) 1 0 Table-C (TX/RX) 1 1 Table-D (TX/RX)

FCTR BIT-6: Register mode select. 0 = Scratch Pad register is selected as general read and write register. ST16C550 compatible mode. 1 = FIFO count register, Enhanced Mode Select Register. Number of characters in transmit or receive holding register can be read via scratch pad register when this bit is set. Enhanced Mode is selected when it is written into it.

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FCTR BIT-7: Programmable trigger register select. 0 = Receiver programmable trigger level register is selected. 1 = Transmitter programmable trigger level register is selected.

TRIGGER LEVEL / FIFO DATA COUNT REGISTER

User programmable transmit / receive trigger level register.

TRG BIT 0-7: Write only. these bits are used to programmed desire trigger levels that are not available in standard tables.

TRG BIT 0-7: Read only. Transmit / receive FIFO count. Number of characters in transmit or receive FIFO can be read via this register.

ENHANCED MODE SELECT REGISTER

This register is accessible only when FCTR Bit-6 is set to 1.

EMSR BIT-0: Write only 0 = Receive FIFO count register. The scratch pad register is used to provide the receive FIFO count when it is read. 1 = Transmit FIFO count register. The scratch pad register is used to provide the transmit FIFO count when it is read.

XR16C854 EXTERNAL RESET CONDITIONS

REGISTERS RESET STATE

IER IER BITS 0-7=0 ISR ISR BIT-0=1, ISR BITS 1-7=0 LCR LCR BITS 0-7=0 MCR MCR BITS 0-7=0 LSR LSR BITS 0-4=0,

LSR BITS 5-6=1 LSR, BIT 7=0

MSR MSR BITS 0-3=0,

MSR BITS 4-7= input signals FCR FCR BITS 0-7=0 EFR EFR BITS 0-7=0 FCTR FCTR BITS 0-7=0 EMSR EMSR BITS 0-7=0 TRG TRG BITS 0-7=0

SIGNALS RESET STATE

TX A-D High

-RTS A-D High

-DTR A-D High

-RXRDY A-D High

-TXRDY A-D Low

EMSR BIT-1: Write only 0 = Normal. 1 = Alternate receive - transmit FIFO count. When EMSR Bit-0=1 and EMSR Bit=1, scratch pad register is used to provide the receive - transmit FIFO count when it is read every alternate read cycle. The TRG Bit-7 will provide the FIFO count mode information, TRG Bit-7=0 receive mode, TRG Bit-7=1 transmit mode.

EMSR BIT 4-7: Reserved for future use.

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XR16C854

AC ELECTRICAL CHARACTERISTICS

TA=0° - 70°C (-40° - +85°C for Industrial grade packages), Vcc=3.3 - 5.0 V ± 10% unless otherwise specified.

Symbol Parameter Limits Limits Units Conditions

3.3 5.0

Min Max Min Max

T1w,T2w Clock pulse duration 20 20 ns T3w Oscillator/Clock frequency 8 24 MHz T6s Address setup time 10 5 ns T7d -IOR delay from chip select 10 10 ns T7w -IOR strobe width 50 25 ns T7h Chip select hold time from -IOR 5 5 ns T9d Read cycle delay 50 50 ns T12d Delay from -IOR to data 35 25 ns T12h Data disable time 35 35 35 ns T13d -IOW delay from chip select 10 10 ns T13w -IOW strobe width 40 40 ns T13h Chip select hold time from -IOW 0 0 ns T15d Write cycle delay 50 50 ns T16s Data setup time 20 15 ns T16h Data hold time 50 35 ns T17d Delay from -IOW to output 50 50 ns 100 pF load T18d Delay to set interrupt from MODEM 50 35 ns 100 pF load

input T19d Delay to reset interrupt from -IOR 50 35 ns 100 pF load T20d Delay from stop to set interrupt 1Rclk 1Rclk Rclk T21d Delay from -IOR to reset interrupt 200 200 ns 100 pF load T22d Delay from stop to interrupt 100 100 ns T23d Delay from initial INT reset to transmit 8 24 8 24 Rclk

start T24d Delay from -IOW to reset interrupt 175 175 ns T25d Delay from stop to set -RxRdy 1 1 Rclk T26d Delay from -IOR to reset -RxRdy 175 175 ns T27d Delay from -IOW to set -TxRdy 175 175 ns T28d Delay from start to reset -TxRdy 8 8 Rclk T30s Address setup time 10 10 ns T30w Chip select strobe width 40 40 ns T30h Address hold time 15 15 ns T30d Read cycle delay 70 70 ns T31d Delay from -CS to data 15 15 ns T31h Data disable time 15 ns T32s Write strobe setup time 10 10 ns T32h Write strobe hold time 10 10 ns T32d Write cycle delay 70 70 ns T33s Data setup time 20 15 ns

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XR16C854

AC ELECTRICAL CHARACTERISTICS

TA=0° - 70°C (-40° - +85°C for Industrial grade packages), Vcc=3.3 - 5.0 V ± 10% unless otherwise specified.

Symbol Parameter Limits Limits Units Conditions

3.3 5.0

Min Max Min Max

T33h Data hold time 10 10 ns TR Reset pulse width 40 40 ns N Baud rate devisor 1 216-1 1 216-1 Rclk

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ABSOLUTE MAXIMUM RATINGS

Supply range 7 Volts Voltage at any pin GND - 0.3 V to VCC +0.3 V Operating temperature -40° C to +85° C Storage temperature -65° C to 150° C Package dissipation 500 mW

DC ELECTRICAL CHARACTERISTICS

TA=0° - 70°C (-40° - +85°C for Industrial grade packages), Vcc=3.3 - 5.0 V ± 10% unless otherwise specified.

Symbol Parameter Limits Limits Units Conditions

3.3 5.0

Min Max Min Max

ILCK

IHCK

Clock input low level -0.3 0.6 -0.5 0.6 V

Clock input high level 2.4 VCC 3.0 VCC V

Input low level -0.3 0.8 -0.5 0.8 V

Input high level 2.0 2.2 VCC V

Output low level on all outputs 0.4 V IOL= 5 mA

Output low level on all outputs 0.4 V IOL= 4 mA

Output high level 2.4 V IOH= -5 mA

Output high level 2.0 V IOH= -1 mA

Input leakage ±10 ±10 µA

Clock leakage ±10 ±10 µA

Avg power supply current 3 6 mA

Avg stand by current 100 200 µA

Input capacitance 5 5 pF RIN Internal pull-up resistance 3 15 kΩ

Note: See the Symbol Description Table, for a listing of pins having internal pull-up resistors.

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A0-A4

XR16C854

-CS

R/-W

D0-D7

T30s

T30w

T31d

T30h

T31h

General read timing in 68 mode

T30d

8654-RD-1

A0-A4

-CS

R/-W

D0-D7

Rev. 1.00P

T32s

T30s

T30h

T32h

T30w

T33h

T33s

General write timing in 68 mode

T32d

8654-WD-1

Page 40

XR16C854

A0-A2

-CS

-IOR

D0-D7

Valid

Address

T6s

Active

T7wT7d T7h T9d

Active

T12d T12h

Data

X654-RD-2

General write timing in 16 mode

A0-A2

-CS

-IOW

D0-D7

Rev. 1.00P

T6s

Valid

Address

Active

T13wT13d

Active

T16s T16h

Data

T13h

T15d

General read timing in 16 mode

X654-WD-2

Page 41

XR16C854

-IOW

-RTS

-DTR

-CD

-CTS

-DSR

INT

-IOR

-RI

Active

Change of state

T17d

Change of state

T18d T18d

Active Active

T19d

Active

Change of state

Active

Active Active

T18d

Change of state

EXTERNAL

CLOCK

T2w

Modem input/output timing

T1w

T3w

External clock timing

X654-MD-1

X654-CK-1

Rev. 1.00P

Page 42

XR16C854

INT

-IOR

START

BIT

DATA BITS (5-8)

D0 D1 D2 D3 D4 D5 D6 D7

5 DATA BITS

6 DATA BITS

7 DATA BITS

PARITY

BIT

STOP

BIT

NEXT DATA

START

BIT

T20d

Active

T21d

Active

16 BAUD RATE CLOCK

Receive timing

X654-RX-1

Rev. 1.00P

Page 43

XR16C854

-RXRDY

-IOR

START

BIT

D0 D1 D2 D3 D4 D5 D6 D7

DATA BITS (5-8)

Receive ready timing in none FIFO mode

PARITY

BIT

STOP

BIT

NEXT DATA

START

BIT

T25d

Active

Data

Ready

T26d

Active

X654-RX-2

-RXRDY

-IOR

Rev. 1.00P

START

BIT

D0 D1 D2 D3 D4 D5 D6 D7

DATA BITS (5-8)

Receive timing in FIFO mode

PARITY

BIT

STOP

BIT

First byte that reaches the trigger level

T25d

Active

Data

Ready

T26d

Active

X654-RX-3

Page 44

XR16C854

INT

-IOW Active

START

BIT

DATA BITS (5-8)

D0 D1 D2 D3 D4 D5 D6 D7

5 DATA BITS

6 DATA BITS

7 DATA BITS

T23d

PARITY

BIT

STOP

BIT

NEXT DATA

START

BIT

T22d

Active

Tx Ready

T24d

Active

16 BAUD RATE CLOCK

Transmit timing

X654-TX-1

Rev. 1.00P

Page 45

XR16C854

-IOW

D0-D7

-TXRDY

Active

BYTE #1

START

BIT

DATA BITS (5-8)

D0 D1 D2 D3 D4 D5 D6 D7

T27d

Active

Transmitter ready

PARITY

BIT

STOP

BIT

NEXT DATA

START

BIT

T28d

Transmitter

not ready

X654-TX-2

Rev. 1.00P

Transmit ready timing in none FIFO mode

Page 46

XR16C854

START BIT

DATA BITS (5-8)

STOP BIT

-IOW

D0-D7

-TXRDY

Active

BYTE #128

T27d

D0 D1 D2 D3 D4 D5 D6 D7

5 DATA BITS

6 DATA BITS

7 DATA BITS

T28d

FIFO Full

PARITY BIT

X552-TX-3

Rev. 1.00P

Transmit ready timing in FIFO mode

Page 47

UART Frame

XR16C854

TX DATA

IRTX (A-D) TX

IRRX (A-D) RX

Data Bits

Start

11 111

0000 0

Bit Time

Infrared transmit timing

3/16 Bit Time

Stop

1/2 Bit Time

RX DATA

Rev. 1.00P

Bit Time

11 111

0000 0

Data Bits

Start

UART Frame

Infrared receive timing

0-1 16x clock delay

X654-IR-1

Stop

Page 48

Package Dimensions

Page 49

Package Dimensions

64 LEAD THIN QUAD FLAT PACK

(10 x 10 x 1.4 mm, TQFP)

Rev. 2.00

48 33

Seating Plane

116

INCHES MILLIMETERS

SYMBOL MIN MAX MIN MAX

A 0.055 0.063 1.40 1.60 A

B 0.005 0.009 0.13 0.23 C 0.004 0.008 0.09 0.20 D 0.465 0.480 11.80 12.20 D

e 0.020 BSC 0.50 BSC L 0.018 0.030 0.45 0.75

0.002 0.006 0.05 0.15

0.053 0.057 1.35 1.45

0.390 0.398 9.90 10.10

α 0° 7° 0° 7°

Note: The control dimension is the millimeter column

Page 50

Package Dimensions

68 LEAD PLASTIC LEADED CHIP CARRIER

(PLCC)

Rev. 1.00

D D

268

45° x H2

45° x H1

Seating Plane

INCHES MILLIMETERS

SYMBOL MIN MAX MIN MAX

A 0.165 0.200 4.19 5.08 A

B 0.013 0.021 0.33 0.53 B

C 0.008 0.013 0.19 0.32 D 0.985 0.995 25.02 25.27 D

e 0.050 BSC 1.27 BSC H1 0.042 0.056 1.07 1.42 H2 0.042 0.048 1.07 1.22 R 0.025 0.045 0.64 1.14

0.090 0.130 2.29 3.30

0.020 –––. 0.51 –––

0.026 0.032 0.66 0.81

0.950 0.958 24.13 24.33

0.890 0.930 22.61 23.62

0.800 typ. 20.32 typ.

Note: The control dimension is the inch column

Page 51

NOTICE

EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability . EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user’s specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies.

EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances.