Datasheet X95820 Datasheet (intersil)

®

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X95820

Dual Digital Controlled Potentiometers (XDCP™)

Data Sheet July 18, 2006

Low Noise/Low Power/I2C® Bus/256 Taps

The X95820 integrates two digitally controlled
potentiometers (XDCP) on a monolithic CMOS integrated
circuit.

The digitally controlled potentiometers are implemented with
a combination of resistor elements and CMOS switches. The
position of the wipers are controlled by the user through the

2

I

C bus interface. Each potentiometer has an associated
volatile Wiper Register (WR) and a non-volatile Initial Value
Register (IVR), that can be directly written to and read by the
user. The contents of the WR controls the position of the
wiper. At power up the device recalls the contents of the two
DCP’s IVR to the corresponding WRs.

The DCPs can be used as three-terminal potentiometers or
as two-terminal variable resistors in a wide variety of
applications including control, parameter adjustments, and
signal processing.

Ordering Information

FN8212.2

Features

• Two potentiometers in one package

• 256 resistor taps-0.4% resolution

•I2C serial interface

- Three address pins, up to eight devices/bus

• Wiper resistance: 70Ω typical @ 3.3V

• Non-volatile storage of wiper position

• Standby current < 5µA max

• Power supply: 2.7V to 5.5V

•50kΩ, 10kΩ total resistance

• High reliability

- Endurance: 150,000 data changes per bit per register

- Register data retention: 50 years @ T ≤ 75°C

• 14 Ld TSSOP

• Pb-free plus anneal available (RoHS compliant)

PART

PART NUMBER

X95820WV14I-2.7* X95820WV G 10kΩ 14 Ld TSSOP
X95820WV14IZ-2.7*

(Note)
X95820UV14I-2.7* X95820UV G 50kΩ 14 Ld TSSOP
X95820UV14IZ-2.7*

(Note)

*Add "T1" suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free

material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.

MARKING

X95820WV Z G 10kΩ 14 Ld TSSOP

X95820UV Z G 50kΩ 14 Ld TSSOP

RESISTANCE

OPTION PACKAGE

(Pb-free)

(Pb-free)

Pinouts

V

CC

WP

RH0

RL0

RW0

A2

SCL

X95820

(14 LD TSSOP)

TOP VIEW

1

2

3

4

5

6

7

14

A1

A0

13

RH1

12

11

RL1

RW1

10

GND

9

SDA

8

1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005-2006. All Rights Reserved

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

Block Diagram

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X95820

V

CC

PiN Descriptions

PIN SYMBOL DESCRIPTION

1V
2WP
3 RH0 “High” terminal of DCP0
4 RL0 “Low” terminal of DCP0
5 RW0 “Wiper” terminal of DCP0
6 A2 Device address for the I
7SCLI
8 SDA Serial data I/O for the I

9 GND Ground
10 RW1 “Wiper” terminal of DCP1
11 RL1 “Low” terminal of DCP1
12 RH1 “High” terminal of DCP1
13 A0 Device address for the I
14 A1 Device address for the I

SDA

SCL

A2

A1

A0

CC

I2C

INTERFACE

POWER-UP,

INTERFACE,
CONTROL AND
STATUS LOGIC

NON-VOLATILE

REGISTERS

WP

WR1

WR0

GND

R

H1

R

W1

R

L1

R

H0

R

W0

R

L0

Power supply pin
Hardware write protection pin. Active low. Prevents any “Write” operation of the I2C interface.

2

C interface

2

C interface clock

2

C interface

2

C interface

2

C interface

2

FN8212.2

July 18, 2006

X95820

www.BDTIC.com/Intersil

Absolute Maximum Ratings Recommended Operating Conditions

Storage Temperature. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C

Voltage at Any Digital Interface Pin

with Respect to GND . . . . . . . . . . . . . . . . . . . . . . .-0.3V to V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +6V

V

CC

Voltage at Any DCP Pin with Respect to GND . . . . . . -0.3V to V

Lead Temperature (soldering, 10s) . . . . . . . . . . . . . . . . . . . . .300°C

(10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6mA

I

W

CAUTION: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional
operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.

CC

+0.3

CC

Analog Specifications Over recommended operating conditions unless otherwise stated.

SYMBOL PARAMETER TEST CONDITIONS MIN

R

TOTAL

R

W

C

H/CL/CW

I

LkgDCP

VOLTAGE DIVIDER MODE (0V @ RL

INL (Note 6) Integral Non-linearity -1 1 LSB

DNL (Note 5) Differential Non-linearity Monotonic over all tap positions -0.5 0.5 LSB

ZSerror
(Note 3)

FSerror
(Note 4)

V

MATCH

(Note 7)

(Note 8) Ratiometric Temperature Coefficient DCP Register set to 80 hex ±4 ppm/°C

TC

V

RESISTOR MODE (Measurements between RW
connected. i = 0 or 1)

RINL

(Note 12)

RDNL

(Note 11)

Roffset

(Note 10)

R

MATCH

(Note 13)

TC

(Note 14)

RH to RL Resistance W, U versions respectively 10, 50 kΩ
RH to RL Resistance Tolerance -20 +20 %
Wiper Resistance VCC = 3.3V @ 25°C

Wiper current = V
Potentiometer Capacitance (Note 15) 10/10/25 pF
Leakage on DCP Pins (Note 15) Voltage at pin from GND to V

; VCC @ RHi; measured at RWi, unloaded; i = 0 or 1)

i

Zero-scale Error U option 0 1 7 LSB

W option 0 0.5 2
Full-scale Error U option -7 -1 0 LSB

W option -2 -1 0
DCP to DCP Matching Any two DCPs at same tap position, same

voltage at all RH terminals, and same

voltage at all RL terminals

and RLi with RHi not connected, or between RWi and RHi with RLi not

i

Integral Non-linearity DCP register set between 20 hex and

FF hex. Monotonic over all tap positions
Differential Non-linearity -0.5 0.5 MI

Offset DCP Register set to 00 hex, U option 0 1 7 MI

DCP Register set to 00 hex, W option 0 0.5 2 MI

DCP to DCP Matching Any two DCPs at the same tap position with

the same terminal voltages.
Resistance Temperature Coefficient DCP register set between 20 hex and FF

R

hex

Temperature Range (Industrial). . . . . . . . . . . . . . . . . .-40°C to 85°C

V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V

CC

Power Rating of Each DCP . . . . . . . . . . . . . . . . . . . . . . . . . . . .5mW

Wiper Current of Each DCP. . . . . . . . . . . . . . . . . . . . . . . . . .±3.0mA

TYP

(Note 1) MAX UNIT

70 200 Ω

CC/RTOTAL

CC

-2 2 LSB

-1 1 MI

-2 2 MI

0.1 1 µA

±45 ppm/°C

(Note 2)

(Note 2)

(Note 2)

(Note 2)

(Note 2)

(Note 9)

(Note 9)

(Note 9)

(Note 9)

(Note 9)

3

FN8212.2

July 18, 2006

X95820

www.BDTIC.com/Intersil

Operating Specifications Over the recommended operating conditions unless otherwise specified.

TYP

SYMBOL PARAMETER TEST CONDITIONS MIN

I

CC1

I

CC2

I

SB

I

LkgDig

t

DCP

(Note 15)

Vpor Power-on Recall Voltage Minimum V

VccRamp VCC Ramp Rate 0.2 V/ms

(Note 15) Power-up Delay VCC above Vpor, to DCP Initial V alue Register recall

t

D

EEPROM SPECS

SERIAL INTERFACE SPECS

V

IL

V

IH

Hysterisis

(Note 15)

V

OL

(Note 15)

Cpin

(Note 15)

f

SCL

t

IN

(Note 15)

t

AA

(Note 15)

t

BUF

(Note 15)

t

LOW

t

HIGH

t

SU:STA

t

HD:STA

VCC Supply Current
(Volatile write/read)

VCC Supply Current
(nonvolatile write)

VCC Current (standby) V

Leakage Current, at Pins A0,
A1, A2, SDA, SCL, and WP
Pins

DCP Wiper Response Time SCL falling edge of last bit of DCP Data Byte to

EEPROM Endurance 150,000 Cycles
EEPROM Retention Temperature ≤ 75°C 50 Years

WP, A2, A1, A0, SDA, and
SCL input buffer LOW
voltage

WP, A2, A1, A0, SDA, and
SCL Input Buffer HIGH
Voltage

SDA and SCL input buffer
hysterisis

SDA Output Buffer LOW
Voltage, Sinking 4mA

, A2, A1, A0, SDA, and

WP
SCL Pin Capacitance

SCL Frequency 400 kHz
Pulse Width Suppression

Time at SDA and SCL Inputs
SCL Falling Edge to SDA

Output Data Valid
Time the Bus Must be Free

Before the Start of a New
Transmission

Clock LOW Time Measured at the 30% of VCC crossing. 1300 ns
Clock HIGH Time Measured at the 70% of VCC crossing. 600 ns
START Condition Setup

Time
STAR T Condition Hold Time From SDA falling edge crossing 30% of VCC to SCL

f

= 400kHz;SDA = Open; (for I2C,

SCL

Active, Read and Volatile Write States only)
f

= 400kHz; SDA = Open; (for I2C,

SCL

Active, Nonvolatile Write State only)

= +5.5V, I

CC

= +3.6V, I

V

CC

Voltage at pin from GND to V

wiper change

completed, and

Any pulse narrower than the max spec is
suppressed.

SCL falling edge crossing 30% of V
exits the 30% to 70% of V

SDA crossing 70% of V
to SDA crossing 70% of V
START condition.

SCL rising edge to SDA falling edge. Both crossing
70% of V

falling edge crossing 70% of V

2

C Interface in Standby State 5 µA

2

C Interface in Standby State 2 µA

CC

at which memory recall occurs 1.8 2.6 V

CC

I2C Interface in standby state

, until SDA

CC

window.

CC

during a STOP condition,

CC

during the following

CC

.

CC

.

CC

-10 10 µA

-0.3 0.3*Vcc V

0.7*Vcc Vcc+0.3 V

0.05*
Vcc

1300 ns

600 ns

600 ns

(Note 1) MAX UNITS

1mA

3mA

1µs

3ms

00.4V

10 pF

50 ns

900 ns

V

4

FN8212.2

July 18, 2006

X95820

www.BDTIC.com/Intersil

Operating Specifications Over the recommended operating conditions unless otherwise specified. (Continued)

SYMBOL PARAMETER TEST CONDITIONS MIN

t

SU:DAT

t

HD:DAT

t

SU:STO

t

HD:STO

t

(Note 15) Output Data Hold Time From SCL falling edge crossing 30% of VCC, until

DH

t

(Note 15) SDA and SCL Rise Time From 30% to 70% of V

R

(Note 15) SDA and SCL Fall Time From 70% to 30% of V

t

F

Cb (Note 15) Capacitive Loading of SDA

Input Data Setup Time From SDA exiting the 30% to 70% of VCC

window, to SCL rising edge crossing 30% of V

CC

Input Data Hold T ime From SCL rising edge crossing 70% of VCC to SDA

entering the 30% to 70% of V

window.

CC

STOP Condition Setup Time From SCL rising edge crossing 70% of VCC, to SDA

rising edge crossing 30% of V

CC

.

STOP Condition Setup Time From SDA rising edge to SCL falling edge. Both

crossing 70% of V

SDA enters the 30% to 70% of V

CC

.

window.

CC

CC

CC

Total on-chip and off-chip 10 400 pF

or SCL

Rpu (Note 15) SDA and SCL Bus Pull-up

resIstor Off-chip

Maximum is determined by t

For Cb = 400pF, max is about 2~2.5kΩ.

and tF.

R

For Cb = 40pF, max is about 15~20kΩ.

t

WP

(Notes 15, 16)

t

SU:WPA

t

HD:WPA

Non-volatile Write Cycle
Time

A2, A1, A0, and WP Setup
Time

A2, A1, A0, and WP Hold
Time

Before START condition 600 ns

After STOP condition 600 ns

100 ns

0ns

600 ns

600 ns

0ns

20 +

0.1 * Cb
20 +

0.1 * Cb

1kΩ

TYP

(Note 1) MAX UNITS

12 20 ms

250 ns

250 ns

SDA vs. SCL Timing

SCL

t

SU:STA

(INPUT TIMING)

(OUTPUT TIMING)

WP

, A0, A1, and A2 Pin Timing

SDA

SDA

SCL

SDA IN

WP, A0, A1, or A2

t

HD:STA

START

t

F

t

SU:DAT

t

SU:WPA

Clk 1

t

HIGH

t

LOW

t

HD:DAT

t

HD:WPA

t

R

t

SU:STO

t

AA

STOP

t

DH

t

BUF

5

FN8212.2

July 18, 2006

X95820

www.BDTIC.com/Intersil

NOTES:

1. Typical values are for T

2. LSB: [V(RW)

255

incremental voltage when changing from one tap to an adjacent tap.

3. ZS error = V(RW)

4. FS error = [V(RW)

5. DNL = [V(RW)

6. INL = [V(RW)

7. V

MATCH

TC

8.

V

- V(RW)

i

– (i • LSB – V(RW)0)]/LSB for i = 1 to 255.

i

= [V(RWx)i - V(RWy)i] / LSB, for i = 0 to 255, x = 0 to 1 and y = 0 to 1.

Max V RW()

()Min V RW()

--------------------------------------------------------------------------------------------- -

()Min V RW()

Max V RW()

for i = 16 to 240 decimal, T = -40°C to 85°C. Max( ) is the maximum value of the wiper voltage and Min ( ) is the minimum value of the wiper
voltage over the temperature range.

|R

- R

9. MI =

10. Roffset = R
Roffset = R

11. RDNL = (R

12. RINL = [R

13. R

MATCH

14.

TC

R

| / 255. R

255

0

/ MI, when measuring between RW and RL.

0

/ MI, when measuring between RW and RH.

255

- R

i

i-1

- (MI • i) - R0] / MI, for i = 32 to 255.

i

= (R

- R

i,x

Max Ri()Min Ri()–[]

----------------------------------------------------------------

Max Ri()Min Ri()+[]2⁄

for i = 32 to 255, T = -40°C to 85°C. Max( ) is the maximum value of the resistance and Min ( ) is the minimum value of the resistance over the
temperature range.

15. This parameter is not 100% tested.

is the minimum cycle time to be allowed for any non-volatile Write by the user, unless Acknowledge Polling is used. It is the time from a

16. t

WC

valid STOP condition at the end of a Write sequence of a I
write cycle.

= 25°C and 3.3V supply voltage.

A

- V(RW)0] / 255. V(RW)

/ LSB.

0

- VCC] / LSB.

255

] / LSB-1, for i = 1 to 255. i is the DCP register setting.

i-1

()–

i

()+[]2⁄

i

and R0 are the measured resistances for the DCP register set to FF hex and 00 hex respectively.

255

and V(RW)0 are V(RW) for the DCP register set to FF hex and 00 hex respectively . LSB is the

255

6

10

i

---------------- -

×=

125°C

i

) / MI, for i = 32 to 255.

) / MI, for i = 0 to 255, x = 0 to 1 and y = 0 to 1.

i,y

---------------- -

×=

125°C

10

6

2

C serial interface Write operation, to the end of the self-timed internal non-volatile

Typical Performance Curves

160

140

VCC = 2.7, T = -40°C

120

100

80

60

40

WIPER RESISTANCE (Ω)

20

VCC = 5.5, T = -40°C

0

0 50 100 150 200 250

FIGURE 1. WIPER RESISTANCE vs T AP POSITION

[ I(RW) = V

VCC = 2.7, T = 85°C

VCC = 5.5, T = 25°C

TAP POSITION (DECIMAL)

CC/RTOTAL

] FOR 50kΩ (U)

VCC = 2.7, T = 25°C

VCC = 5.5, T = 85°C

1.8

1.6

1.4

1.2

(µA)

1.0

CC

0.8

0.6

STANDBY I

0.4

0.2

0.0

2.7 3.2 3.7 4.2 4.7 5.2

FIGURE 2. STANDBY I

25°C

-40°C

V

(V)

CC

vs V

CC

CC

85°C

6

FN8212.2

July 18, 2006

Typical Performance Curves (Continued)

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X95820

0.2

-0.05

DNL (LSB)

-0.15

0.15

0.1

0.05

-0.1

-0.2

VCC = 2.7, T = 25°C

0

VCC = 2.7, T = 85°C

0 50 100 150 200 250

VCC = 5.5, T = -40°C

VCC = 5.5, T = 25°C

VCC = 5.5, T = 85°C

TAP POSITION (DECIMAL)

VCC = 2.7, T = -40°C

FIGURE 3. DNL vs TAP POSITION IN VOLTAGE DIVIDER

MODE FOR 10kΩ (W)

0.4

0.35

0.3

0.25

ZSerror (LSB)

0.2

0.15

-40-200 20406080

2.7V

5.5V

TEMPERATURE (°C)

FIGURE 5. ZSerror vs TEMPERATURE

0.3

VCC = 5.5, T = -40°C

0.2

0.1

0

INL (LSB)

VCC = 2.7, T = 85°C

-0.1

-0.2

-0.3
0 50 100 150 200 250

VCC = 2.7, T = -40°C

VCC = 5.5, T = 85°C

VCC = 2.7, T = 25°C

VCC = 5.5, T = 25°C

TAP POSITION (DECIMAL)

FIGURE 4. INL vs TAP POSITION IN VOL TAGE DIVIDER

MODE FOR 10kΩ (W)

0

-0.1

-0.2

-0.3

-0.4

-0.5

-0.6

FSerror (LSB)

-0.7

-0.8

-0.9

-1

-40

-20

0

TEMPERATURE (°C)

VCC = 5.5V

VCC = 2.7V

20 40 60 80

FIGURE 6. FSerror vs TEMPERATURE

0.3

VCC = 2.7, T = 25°C

0.2

0.1

0

DNL (LSB)

-0.1

-0.2

-0.3
32 82 132 182 232

VCC = 5.5, T = 25°C

V

= 5.5, T = 85°C

CC

VCC = 2.7, T = -40°C

TAP POSITION (DECIMAL)

VCC = 2.7, T = 85°C

= 5.5, T = -40°C

V

CC

FIGURE 7. DNL vs TAP POSITION IN Rheostat MODE FOR

0.5

0.4

0.3

0.2

0.1

0

-0.1

INL (LSB)

-0.2

-0.3

VCC = 2.7, T = 85°C

-0.4

-0.5
32 82 132 182 232

FIGURE 8. INL vs TAP POSITION IN Rheostat MODE FOR

50kΩ (U)

7

V

50kΩ (U)

VCC = 5.5, T = -40°C

VCC = 5.5, T = 85°C

= 5.5, T = 25°C

CC

TAP POSITION (DECIMAL)

VCC = 2.7, T = 25°C

VCC = 2.7, T = -40°C

FN8212.2

July 18, 2006

Typical Performance Curves (Continued)

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X95820

1.50

1.00

0.50

CHANGE (%)

5.5V

0.00

TOTAL

-0.50

-1.00

END TO END R

-1.50

-40-200 20406080

FIGURE 9. END TO END R

2.7V

TEMPERATURE (°C)

% CHANGE vs

TOTAL

TEMPERATURE

35

25

15

5

20

10

0

TC (ppm/°C)

-10

-20

32 82 132 182 232

TAP POSITION (DECIMAL)

FIGURE 10. TC FOR VOLTAGE DIVIDER MODE IN ppm

INPUT

OUTPUT

TC (ppm/°C)

-5

-15

-25
32 57 82 107 132 157 182 207 232

TAP POSITION (DECIMAL)

FIGURE 11. TC FOR Rheostat MODE IN ppm

Signal at Wiper (Wiper Unloaded)

Wiper Movement Mid Point
From 80h to 7fh

FIGURE 13. MIDSCALE GLITCH, CODE 80h TO 7Fh (WIPER 0)

Tap Position = Mid Point

= 9.4K

R

TOTAL

FIGURE 12. FREQUENCY RESPONSE (2.2MHz)

SCL

Signal at Wiper
(Wiper Unloaded Movement
From ffh to 00h)

FIGURE 14. LARGE SIGNAL SETTLING TIME

8

FN8212.2

July 18, 2006

X95820

www.BDTIC.com/Intersil

Principles of Operation

The X95820 in as integrated circuit incorporating two DCPs
with their associated registers, non-volatile memory, and a

2

I

C serial interface providing direct communication between

a host and the potentiometers and memory.

DCP Description

Each DCP is implemented with a combination of resistor
elements and CMOS switches. The physical ends of each
DCP are equivalent to the fixed terminals of a mechanical
potentiometer (RH and RL pins). The RW pin of each DCP is
connected to intermediate nodes, and is equivalent to the
wiper terminal of a mechanical potentiometer. The position
of the wiper terminal within the DCP is controlled by an 8-bit
volatile Wiper Register (WR). Each DCP has its own WR.
When the WR of a DCP cont ains all zeroes (WR<7: 0>: 00h),
its wiper terminal (RW) is closest to its “Low” terminal (RL).
When the WR of a DCP contains all ones (WR<7:0>: FFh),
its wiper terminal (RW) is closest to its “High” terminal (RH).
As the value of the WR increases from all zeroes (00h) to all
ones (255 decimal), the wiper moves monotonically from the
position closest to RL to the closest to RH. At the same time,
the resistance between RW and RL increases monotonically,
while the resistance between RH and RW decreases
monotonically.

While the X95820 is being powered up, all two WRs are
reset to 80h (128 decimal), which locates RW roughly at the
center between RL and RH. Soon after the power supply
voltage becomes large enough for reliable non-volatile
memory reading, the X95820 reads the value stored on two
different non-volatile Initial Value Registers (IVRs) and loads
them into their corresponding WRs.

The WRs and IVRs can be read or written directly using the

2

I

C serial interface as described in the following sections.

Memory Description

The X95820 contains eight non-volatile bytes. they are
accessed by I
through 7 decimal. The first two non-volatile bytes at
addresses 0 and 1 contain the initial value loaded at power­up into the volatile Wiper Registers (WRs) of DCP0 and
DCP1 respectively. Bytes at addresses 2, 3, 4, 5, and 6 are
available to the user as general purpose registers. The byte
at address 7 is reserved; the user should not write to it, and
its value should be ignored if read.

The volatile WR, and the non-volatile Initial Value Register
(IVR) of a DCP are accessed with the same Address Byte.

2

C interface operations with Address Bytes 0

When the byte at address 8 is all zeroes, which is the default
at power up:

• A read operation to addresses 0 or 1 outputs the value of
the non-volatile IVRs.

• A write operation to addresses 0 or 1 writes the same
value to the WR and IVR of the corresponding DCP.

When the byte at address 8 is 80h (128 decimal):

• A read operation to addresses 0 or 1 outputs the value of
the volatile WR.

• A write operation to addresses 0 or 1only writes to the
corresponding volatile WR.

It is not possible to write to an IVR without writing the same
value to its corresponding WR.

00h and 80h are the only values that should be written to
address 8. All other values are reserved and must not be
written to address 8.

To access the general purpose bytes at addresses 2, 3, 4, 5,
or 6, the value at address 8 must be all zeros.

The X95820 is pre-programmed with 80h in the two IVRs.

TABLE 1. MEMORY MAP

ADDRESS NON-VOLATILE VOLATILE

8 - Access Control
7Reserved
6

5
4
3
2

1
0

WR: Wiper Register, IVR: Initial value Register.

General Purpose Not Available

IVR1
IVR0

WR1
WR0

I2C Serial Interface

The X95820 supports a bidirectional I2C bus oriented
protocol. The protocol defines any device that sends data
onto the bus as a transmitter and the receiving device as the
receiver. The device controlling the transfer is a master and
the device being controlled is the slave. The master always
initiates data transfers and provides the clock for both
transmit and receive operations. Therefore, the X95820
operates as a slave device in all applications.

All communication over the I
sending the MSB of each byte of data first.

2

C interface is conducted by

A volatile byte at address 8 decimal, controls what byte is
read or written when accessing DCP registers: the WR, the
IVR, or both.

9

Protocol Conventions

Data states on the SDA line can change only during SCL
LOW periods. SDA state changes during SCL HIGH are
reserved for indicating START and STOP conditions (See
Figure 15). On power up of the X95820 the SDA pin is in the
input mode.

FN8212.2

July 18, 2006

X95820

www.BDTIC.com/Intersil

All I2C interface operations must begin with a START
condition, which is a HIGH to LOW transition of SDA while
SCL is HIGH. The X95820 continuously monitors the SDA
and SCL lines for the START condition and does not
respond to any command until this condition is met (See
Figure 15). A START condition is ignored during the power
up sequence and during internal non-volatile write cycles.

2

All I

C interface operations must be terminated by a STOP
condition, which is a LOW to HIGH transition of SDA while
SCL is HIGH (See Figure 15). A STOP condition at the end
of a read operation, or at the end of a write operation to
volatile bytes only places the device in its standby mode. A
STOP condition during a write operation to a non-volatile
byte, initiates an internal non-volatile write cycle. The device
enters its standby state when the internal non-volatile write
cycle is completed.

An ACK, Acknowledge, is a software convention used to
indicate a successful data transfer. The transmitting device,
either master or slave, releases the SDA bus after
transmitting eight bits. During the ninth clock cycle, the

SCL

receiver pulls the SDA line LOW to acknowledge the
reception of the eight bits of data (See Figure 16).

The X95820 responds with an ACK after recognition of a
START condition followed by a valid Identification Byte, and
once again after successful receipt of an Address Byte. The
X95820 also responds with an ACK after receiving a Data
Byte of a write operation. The master must respond with an
ACK after receiving a Data Byte of a read operation

A valid Identification Byte contains 1010 as the four MSBs,
and the following three bits matching the logic values
present at pins A2, A1, and A0. The LSB in the Read/Write
bit. Its value is “1” for a Read operation, and “0” for a Write
operation (See Table 2).

TABLE 2. IDENTIFICATION BYTE FORMAT

Logic values at pins A2, A1, and A0 respectively

1 0 1 0 A2 A1 A0 R/W

(MSB) (LSB)

SDA

SCL from Master

SDA Output from

Transmitter

SDA Output from

Receiver

START DATA DATA STOP

FIGURE 15. VALID DATA CHANGES, START, AND STOP CONDITIONS

START ACK

FIGURE 16. ACKNOWLEDGE RESPONSE FROM RECEIVER

Signals from the

Master

STABLE CHANGE

High Impedance

S

t

Identification

a

r
t

Byte

Write

DATA

STABLE

Address

Byte

81 9

Data
Byte

High Impedance

S

t
o
p

Signal at SDA

Signals from the

X95820

10100

FIGURE 17. BYTE WRITE SEQUENCE

000 0A2A1A0

A
C
K

10

A
C
K

A
C
K

FN8212.2

July 18, 2006

X95820

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Write Operation

A Write operation requires a START condition, followed by a
valid Identification Byte, a valid Address Byte, a Data Byte,
and a STOP condition. After each of the three bytes, the
X95820 responds with an ACK. At this time, if the Data Byte
is to be written only to volatile registers, then the device
enters its standby state. If the Data Byte is to be written also
to non-volatile memory, the X95820 begins its internal write
cycle to non-volatile memory. During the internal non-volatile
write cycle, the device ignores transitions at the SDA and
SCL pins, and the SDA output is at a high impedance state.
When the internal non-volatile write cycle is completed, the
X95820 enters its standby state (See Figure 17).

The byte at address 00001000 bin (8 decimal) determines if
the Data Byte is to be written to volatile and/or non-volatile
memory. See “Memory Description” on page 9.

Data Protection

The WP pin has to be at logic HIGH to perform any Write
operation to the device. When the WP
device ignores Data Bytes of a Write Operation, does not
respond to the Data Bytes with an ACK, and instead, goes to
its standby state waiting for a new START condition.

A STOP condition also acts as a protection of non-volatile
memory. A valid Identification Byte, Address Byte, and total
number of SCL pulses act as a protection of both volatile
and non-volatile registers. During a Write sequence, the
Data Byte is loaded into an internal shift register as it is
received. If the Address Byte is 0, 1, or 8 decimal, the Dat a
Byte is transferred to the appropriate Wiper Register (WR) or
to the Access Control Register, at the falling edge of the SCL

is active (LOW) the

pulse that loads the last bit (LSB) of the Data Byte. If the
Address Byte is between 0 and 6 (inclusive), and the Access
Control Register is all zeros (default), then the STOP
condition initiates the internal write cycle to non-volatile
memory.

Read Operation

A Read operation consists of a three byte instruction
followed by one or more Data Bytes (See Figure 18). The
master initiates the operation issuing the following
sequence: a START, the Identification byte with the R/W
set to “0”, an Address Byte, a second START, and a second
Identification byte with the R/W

bit set to “1”. After each of
the three bytes, the X95820 responds with an ACK. Then the
X95820 transmits Data Bytes as long as the master
responds with an ACK during the SCL cycle following the
eight bit of each byte. The master terminates the read
operation (issuing a STOP condition) following the last bit of
the last Data Byte (See Figure 18).

The Data Bytes are from the memory location indicated by
an internal pointer. This pointer initial value is determined by
the Address Byte in the Read operation instruction, and
increments by one during transmission of each Data Byte.
After reaching the memory location 01Fh (8 decimal) the
pointer “rolls over” to 00h, and the device continues to output
data for each ACK received.

The byte at address 00001000 bin (8 decimal) determines if
the Data Bytes being read are from volatile or non-volatile
memory. See “Memory Description” on page 9.

bit

Signals

from the

Master

Signal at SDA

Signals from the

Slave

S

t

a

r
t

10100

Identification

Byte
with

=0

R/W

11

S

Identification

t

t

11100

Byte
with

R/W

=1

A
C

First Read Data

K

Byte

A
C
K

A
C
K

Last Read Data

Byte

Address

Byte

A
C
K

FIGURE 18. READ SEQUENCE

a
r

A
C
K

S

t
o
p

FN8212.2

July 18, 2006

X95820

www.BDTIC.com/Intersil

Thin Shrink Small Outline Plastic Packages (TSSOP)

N

INDEX
AREA

123

0.05(0.002)

-A­D

e

b

0.10(0.004) C AM BS

NOTES:

1. These package dimensions are within allowable dimensions of
JEDEC MO-153-AC, Issue E.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm
(0.006 inch) per side.

4. Dimension “E1” does not include interlead flash or protrusions. Inter­lead flash and protrusions shall not exceed 0.15mm (0.006 inch) per
side.

5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. Dimension “b” does not include dambar protrusion. Allowable dambar
protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimen­sion at maximum material condition. Minimum space between protru­sion and adjacent lead is 0.07mm (0.0027 inch).

10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact. (Angles in degrees)

E1

-B-

SEATING PLANE

A

-C-

M

0.25(0.010) BM M

E

α

A1

0.10(0.004)

GAUGE

PLANE

0.25

0.010

A2

L

c

M14.173

14 LEAD THIN SHRINK SMALL OUTLINE PLASTIC
PACKAGE

INCHES MILLIMETERS

SYMBOL

A - 0.047 - 1.20 -

A1 0.002 0.006 0.05 0.15 -

A2 0.031 0.041 0.80 1.05 -

b 0.0075 0.0118 0.19 0.30 9

c 0.0035 0.0079 0.09 0.20 -

D 0.195 0.199 4.95 5.05 3

E1 0.169 0.177 4.30 4.50 4

e 0.026 BSC 0.65 BSC -

E 0.246 0.256 6.25 6.50 -

L 0.0177 0.0295 0.45 0.75 6

N14 147

o

α

0

o

8

o

0

o

8

NOTESMIN MAX MIN MAX

-

Rev. 2 4/06

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implic atio n or other wise u nde r any p a tent or patent rights of Intersil or its subsidiaries.

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12

FN8212.2

July 18, 2006