Datasheet W78C52D, W78C052D Datasheet (winbond)

W78C52D/W78C052D

8-BIT MICROCONTROLLER

Publication Release Date: December 4, 2006

- 1 - Revision A5

Table of Contents-

1. GENERAL DESCRIPTION ......................................................................................................... 2

2. FEATURES ................................................................................................................................. 2

3. PIN CONFIGURATIONS ............................................................................................................ 3

4. PIN DESCRIPTION..................................................................................................................... 4

5. FUNCTIONAL DESCRIPTION ................................................................................................... 6

6. ABSOLUTE MAXIMUM RATINGS ........................................................................................... 10

7. DC CHARACTERISTICS.......................................................................................................... 11

8. AC CHARACTERISTICS .......................................................................................................... 13

9. TIMING WAVEFORMS ............................................................................................................. 15

10. APPLICATION CIRCUITS ........................................................................................................ 17

11. PACKAGE DIMENSIONS......................................................................................................... 19

12. REVISION HISTORY ................................................................................................................21

查询W78C052D40DL供应商

W78C52D/W78C052D

- 2 -

1. GENERAL DESCRIPTION

The W78C052D microcontroller supplies a wider frequency and supply voltage range than most 8-bit
microcontrollers on the market. It is compatible with the industry standard 80C52 microcontroller
series. The W78C052D contains four 8-bit bidirectional parallel ports, one extra 4-bit bit-addressable

I/O port (Port 4) and two additional external interrupts (

INT2

, INT3 ), three 16-bit timer/counters, one
watchdog timer and a serial port. These peripherals are supported by a eight-source, two-level
interrupt capability. There are 256 bytes of RAM and an 8K byte mask ROM for application programs.

The W78C052D microcontroller has two power reduction modes, idle mode and power-down mode,
both of which are software selectable. The idle mode turns off the processor clock but allows for
continued peripheral operation. The power-down mode stops the crystal oscillator for minimum power
consumption. The external clock can be stopped at any time and in any state without affecting the
processor.

2. FEATURES

y Fully static design

y

Supply voltage of 4.5V to 5.5V

y DC-40 MHz operation

y 256 bytes of on-chip scratchpad RAM

y 8K bytes of on-chip mask ROM

y 64K bytes program memory address space

y 64K bytes data memory address space

y Four 8-bit bidirectional ports

y Three 16-bit timer/counters

y One full duplex serial port

y

Eight-source, two-level interrupt capability

y One extra 4-bit bit-addressable I/O port

y

Two additional external interrupts INT2 / INT3

y Watchdog timer

y EMI reduction mode

y Built-in power management

y Code protection

y Packages:

− Lead Free (RoHS) DIP 40: W78C052D40DL

− Lead Free (RoHS) PLCC 44: W78C052D40PL

− Lead Free (RoHS) PQFP 44: W78C052D40FL

W78C52D/W78C052D

Publication Release Date: December 4, 2006

- 3 - Revision A5

3. PIN CONFIGURATIONS

VDD1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

39

40

34

35

36

37

38

30

31

32

33

26

27

28

29

21

22

23

24

25

P0.0, AD0
P0.1, AD1

P0.2, AD2

P0.3, AD3

P0.4, AD4

P0.5, AD5

P0.6, AD6

P0.7, AD7

EA
ALE

PSEN

P2.5, A13

P2.6, A14

P2.7, A15

P2.0, A8

P2.1, A9

P2.2, A10

P2.3, A11

P2.4, A12

T2, P1.0

40-Pin DIP

P1.2

P1.3

P1.4

P1.5

P1.6

RXD, P3.0
TXD, P3.1

P1.7

RST

INT0, P3.2

INT1, P3.3

T0, P3.4
T1, P3.5

WR, P3.6

RD, P3.7

XTAL1

XTAL2

VSS

T2EX, P1.1

44-Pin PLCC

44-Pin QFP

40

2 1 44 43 42

41

6543

39
38

37

36

35

34

33

32

31

30
29

2827262524232221201918

17

10

9

8

7

14

13

12

11

16

15

P1.5

P1.6

P1.7

RST

RXD, P3.0

TXD, P3.1

INT0, P3.2

INT1, P3.3

T0, P3.4

T1, P3.5

A
D
3
,
P
0
.
3

T
2
,
P
1
.
0

P
1
.
2

V
D
D

A
D
2
,
P
0
.
2

A
D
1
,
P
0
.
1

A
D
0
,
P
0
.
0

T
2
E
X
,
P
1
.
1

P
1
.
3

P
1
.
4

X
T
A
L
1

V
S
S

P
2
.
4
,
A
1
2

P
2
.
3
,
A
1
1

P
2
.
2
,
A
1
0

P
2
.
1
,
A
9

P
2
.
0
,
A
8

X
T
A
L
2

P
3
.
7
,
/
R
D

P
3
.
6
,
/
W
R

P0.4, AD4

P0.5, AD5

P0.6, AD6

P0.7, AD7

EA

ALE

PSEN
P2.7, A15

P2.6, A14

P2.5, A13

P4.1

P
4
.
0

INT2, P4.3

/
I
N
T
3
,
P
4
.
2

34

403938 37 36 35

44

43 42 41

33
32

31

30

29

28

27

26

25

24
23

P0.4, AD4

P0.5, AD5

P0.6, AD6

P0.7, AD7

EA

ALE

PSEN
P2.7, A15

P2.6, A14

P2.5, A13

22212019181716151413

12

11

4

3

2

1

8

7

6

5

10

9

P1.5

P1.6

P1.7
RST

RXD, P3.0

TXD, P3.1
INT0, P3.2

INT1, P3.3

T0, P3.4
T1, P3.5

X
T
A
L
1

V
S
S

P
2
.
4
,
A
1
2

P
2
.
3
,
A
1
1

P
2
.
2
,
A
1
0

P
2
.
1
,
A
9

P
2
.
0
,
A
8

X
T
A
L
2

P
3
.
7
,
/
R
D

P
3
.
6
,
/
W
R

A
D
3
,
P
0
.
3

T
2
,
P
1
.
0

P
1
.
2

V
D
D

A
D
2
,
P
0
.
2

A
D
1
,
P
0
.
1

A
D
0
,
P
0
.
0

T
2
E
X
,
P
1
.
1

P
1
.
3

P
1
.
4

P
4
.
0

/
I
N
T
3
,
P
4
.
2

P4.1

INT2, P4.3

W78C52D/W78C052D

- 4 -

4. PIN DESCRIPTION

P0.0−P0.7

Port 0, Bits 0 through 7. Port 0 is a bidirectional I/O port. This port also provides a multiplexed low
order address/data bus during accesses to external memory.

P1.0−P1.7

Port 1, Bits 0 through 7. Port 1 is a bidirectional I/O port with internal pull-ups. Pins P1.0 and P1.1
also serve as T2 (Timer 2 external input) and T2EX (Timer 2 capture/reload trigger), respectively.

P2.0−P2.7

Port 2, Bits 0 through 7. Port 2 is a bidirectional I/O port with internal pull-ups. This port also provides
the upper address bits for accesses to external memory.

P3.0−P3.7

Port 3, Bits 0 through 7. Port 3 is a bidirectional I/O port with internal pull-ups. All bits have alternate
functions, which are described below:

PIN ALTERNATE FUNCTION

P3.0 RXD Serial Receive Data
P3.1 TXD Serial Transmit Data

P3.2

INT0 External Interrupt 0

P3.3

INT1 External Interrupt 1

P3.4 T0 Timer 0 Input
P3.5 T1 Timer 1 Input

P3.6

WR Data Write Strobe

P3.7

RD Data Read Strobe

P4.0−P4.3

Another bit-addressable bidirectional I/O port P4. P4.3 and P4.2 are alternative function pins. It can be
used as general I/O pins or external interrupt input sources (

INT2 / INT3 ).

EA

External Address Input, active low. This pin forces the processor to execute out of external ROM. This
pin should be kept low for all W78C31 operations.

RST

Reset Input, active high. This pin resets the processor. It must be kept high for at least two machine
cycles in order to be recognized by the processor.

ALE

Address Latch Enable Output, active high. ALE is used to enable the address latch that separates the
address from the data on Port 0. ALE runs at 1/6th of the oscillator frequency. A single ALE pulse is
skipped during external data memory accesses. ALE goes to a high impedance state during reset with
a weak pull-up.

W78C52D/W78C052D

Publication Release Date: December 4, 2006

- 5 - Revision A5

PSEN

Program Store Enable Output, active low.

PSEN enables the external ROM onto the Port 0

address/data bus during fetch and MOVC operations.

PSEN goes to a high impedance state during

reset with a weak pull-up.

XTAL1

Crystal 1. This is the crystal oscillator input. This pin may be driven by an external clock.

XTAL2

Crystal 2. This is the crystal oscillator output. It is the inversion of XTAL1.

VSS, VDD

Power Supplies. These are the chip ground and positive supplies.

W78C52D/W78C052D

- 6 -

5. FUNCTIONAL DESCRIPTION

The W78C052D architecture consists of a core controller surrounded by various registers, five general
purpose I/O ports, 256 bytes of RAM, three timer/counters, one watchdog timer and a serial port. The
processor supports 111 different opcodes and references both a 64K program address space and a
64 K data storage space.

Timers 0, 1, and 2

Timers 0, 1, and 2 each consist of two 8-bit data registers. These are called TL0 and TH0 for Timer 0,
TL1 and TH1 for Timer 1, and TL2 and TH2 for Timer 2. The TCON and TMOD registers provide
control functions for timers 0, 1. The T2CON register provides control functions for Timer 2. RCAP2H
and RCAP2L are used as reload/capture registers for Timer 2. The operations of Timer 0 and Timer 1
are the same as in the W78C51. Timer 2 is a special feature of the W78C052D: it is a 16-bit
timer/counter that is configured and controlled by the T2CON register. Like Timers 0 and 1, Timer 2
can operate as either an external event counter or as an internal timer, depending on the setting of bit
C/T2 in T2CON. Timer 2 has three operating modes: capture, auto-reload, and baud rate generator.
The clock speed at capture or auto-reload mode is the same as that of Timers 0 and 1.

Clock

The W78C052D is designed to be used with either a crystal oscillator or an external clock. Internally,
the clock is divided by two before it is used. This makes the W78C052D relatively insensitive to duty
cycle variations in the clock.

Crystal Oscillator

The W78C052D incorporates a built-in crystal oscillator. To make the oscillator work, a crystal must
be connected across pins XTAL1 and XTAL2. In addition, a load capacitor must be connected from
each pin to ground, and a resistor must also be connected from XTAL1 to XTAL2 to provide a DC
bias when the crystal frequency is above 24 MHz.

External Clock

An external clock should be connected to pin XTAL1. Pin XTAL2 should be left unconnected. The
XTAL1 input is a CMOS-type input, as required by the crystal oscillator. As a result, the external clock
signal should have an input one level of greater than 3.5 volts when V

DD

= 5 volts.

Power Management

Idle Mode

The idle mode is entered by setting the IDL bit in the PCON register. In the idle mode, the internal
clock to the processor is stopped. The peripherals and the interrupt logic continue to be clocked. The
processor will exit idle mode when either an interrupt or a reset occurs.

Power-down Mode

When the PD bit of the PCON register is set, the processor enters the power-down mode. In this
mode all of the clocks, including the oscillator are stopped. The only way to exit power-down mode is
by a reset.

Reset

The external RESET signal is sampled at S5P2. To take effect, it must be held high for at least two
machine cycles while the oscillator is running. An internal trigger circuit in the reset line is used to
deglitch the reset line when the W78C052D is used with an external RC network. The reset logic also
has a special glitch removal circuit that ignores glitches on the reset line. During reset, the ports are
initialized to FFH, the stack pointer to 07H, PCON (with the exception of bit 4) to 00H, and all of the
other SFR registers except SBUF to 00H. SBUF is not reset.

W78C52D/W78C052D

Publication Release Date: December 4, 2006

- 7 - Revision A5

New Defined Peripheral

In order to be more suitable for I/O, an extra 4-bit bit-addressable port P4 and two external interrupts

INT2 , INT3 have been added to either the PLCC or QFP package. And description follows:

1.

INT2 / INT3

Two additional external interrupts,

INT2 and INT3 , whose functions are similar to those of external

interrupt 0 and 1 in the standard 80C52. The functions/status of these interrupts are
determined/shown by the bits in the XICON (External Interrupt Control) register. The XICON register is
bit-addressable but is not a standard register in the standard 80C52. Its address is at 0C0H. To
set/clear bits in the XICON register, one can use the "SETB (/CLR) bit" instruction. For example,
"SETB 0C2H" sets the EX2 bit of XICON.

***XICON - external interrupt control (C0H)

PX3 EX3 IE3 IT3 PX2 EX2 IE2 IT2

PX3: External interrupt 3 priority high if set

EX3: External interrupt 3 enable if set

IE3: If IT3 = 1, IE3 is set/cleared automatically by hardware when interrupt is detected/serviced

IT3: External interrupt 3 is falling-edge/low-level triggered when this bit is set/cleared by software

PX2: External interrupt 2 priority high if set

EX2: External interrupt 2 enable if set

IE2: If IT2 = 1, IE2 is set/cleared automatically by hardware when interrupt is detected/serviced

IT2: External interrupt 2 is falling-edge/low-level triggered when this bit is set/cleared by software

Eight-source interrupt informations:

INTERRUPT SOURCE

VECTOR

ADDRESS

POLLING

SEQUENCE WITHIN

PRIORITY LEVEL

ENABLE

REQUIRED

SETTINGS

INTERRUPT

TYPE

EDGE/LEVEL

External Interrupt 0 03H 0 (highest) IE.0 TCON.0

Timer/Counter 0 0BH 1 IE.1 -

External Interrupt 1 13H 2 IE.2 TCON.2

Timer/Counter 1 1BH 3 IE.3 -

Serial Port 23H 4 IE.4 -

Timer/Counter 2 2BH 5 IE.5 -

External Interrupt 2 33H 6 XICON.2 XICON.0

External Interrupt 3 3BH 7 (lowest) XICON.6 XICON.3

W78C52D/W78C052D

- 8 -

2. PORT4

Another bit-addressable port P4 is also available and only 4 bits (P4<3:0>) can be used. This port
address is located at 0D8H with the same function as that of port P1, except the P4.3 and P4.2 are

alternative function pins. It can be used as general I/O pins or external interrupt input sources (

INT2

/

INT3 ).

Example: P4 REG 0D8H
MOV P4, #0AH ; Output data "A" through P4.0−P4.3.
MOV A, P4 ; Read P4 status to Accumulator.
SETB P4.0 ; Set bit P4.0
CLR P4.1 ; Clear bit P4.1

Watchdog Timer

The Watchdog timer is a free-running timer which can be programmed by the user to serve as a
system monitor, a time-base generator or an event timer. It is basically a set of dividers that divide
the system clock. The divider output is selectable and determines the time-out interval. When the time­out occurs a system reset can also be caused if it is enabled. The main use of the Watchdog timer is
as a system monitor. This is important in real-time control applications. In case of power glitches or
electro-magnetic interference, the processor may begin to execute errant code. If this is left
unchecked the entire system may crash. The watchdog time-out selection will result in different time­out values depending on the clock speed. The Watchdog timer will de disabled on reset. In general,
software should restart the Watchdog timer to put it into a known state. The control bits that support
the Watchdog timer are discussed below.

Watchdog Timer Control Register

Bit: 7 6 5 4 3 2 1 0

ENW CLRW WIDL - - PS2 PS1 PS0

Mnemonic: WDTC Address: 8FH

ENW : Enable watch-dog if set.
CLRW: Clear watch-dog timer and prescaler if set. This flag will be cleared automatically
WIDL : If this bit is set, watch-dog is enabled under IDLE mode. If cleared, watch-dog is disabled

under IDLE mode. Default is cleared.

PS2, PS1, PS0: Watch-dog prescaler timer select. Prescaler is selected when set PS2~0 as follows:

PS2 PS1 PS0 PRESCALER SELECT

0 0 0 2
0 1 0 4
0 0 1 8
0 1 1 16
1 0 0 32
1 0 1 64
1 1 0 128
1 1 1 256

The time-out period is obtained using the following formula :

W78C52D/W78C052D

Publication Release Date: December 4, 2006

- 9 - Revision A5

1

2 1000 12

14

OSC

PRESCALER×× × × mS

Before Watchdog time-out occurs, the program must clear the 14-bit timer by writing 1 to WDTC.6
(CLRW). After 1 is written to this bit, the 14-bit timer , prescaler and this bit will be reset on the next
instruction cycle. The Watchdog timer is cleared on reset.

OSC 1/12

PRESCALER

14-BIT TIMER

CLEAR

CLRW

EXTERNAL

RESET

INTERNAL

RESET

WIDL

IDLE

ENW

Watchdog Timer Block Diagram

Typical Watchdog time-out period when OSC = 20 MHz

PS2 PS1 PS0 WATCHDOG TIME-OUT PERIOD

0 0 0 19.66 mS
0 1 0 39.32 mS
0 0 1 78.64 mS
0 1 1 157.28 mS
1 0 0 314.57 mS
1 0 1 629.14 mS
1 1 0 1.25 S
1 1 1 2.50 S

Reduce EMI Emission

Because of the on-chip ROM, when a program is running in internal ROM space, the ALE will be
unused. The transition of ALE will cause noise, so it can be turned off to reduce the EMI emission if it
is not needed. Turning off the ALE signal transition only requires setting the bit 0 of the AUXR SFR,
which is located at 08Eh. When ALE is turned off, it will be reactivated when the program accesses
external ROM/RAM data or jumps to execute an external ROM code. The ALE signal will turn off
again after it has been completely accessed or the program returns to internal ROM code space.

AUXR - Auxiliary Register

Bit: 7 6 5 4 3 2 1 0

- - - - - - - AO

Mnemonic: AUXR Address: 8Eh

AO: Turn off ALE signal.

W78C52D/W78C052D

- 10 -

6. ABSOLUTE MAXIMUM RATINGS

PARAMETER SYMBOL MIN. MAX. UNIT

DC Power Supply

V

CC−VSS

-0.3 +7.0 V

Input Voltage VIN VSS -0.3 VCC +0.3 V

Operating Temperature TA 0 70

°C

Storage Temperature TST -55 +150

°C

Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability
of the device.

W78C52D/W78C052D

Publication Release Date: December 4, 2006

- 11 - Revision A5

7. DC CHARACTERISTICS

Vss = 0V ; TA = 25° C; unless otherwise specified.

SPECIFICATION

PARAMETER SYM.

MIN. MAX. UNIT

TEST CONDITIONS

Operating Voltage VDD 4.5 5.5 V

Operating Current IDD - 20 mA VDD = 5.5V, 20 MHz, no load

Idle Current IIDLE - 6 mA VDD = 5.5V, 20 MHz, no load

Power Down Current IPWDN - 50

µA

VDD = 5.5V, no load

Input

Input Current

P1, P2, P3, P4

I

IN -50 +10

µA

V

DD = 5.5V

V

IN

= 0V or VDD

Input Leakage Current

P0,

EA

I

LK -10 +10

µA

V

DD = 5.5V

V

SS < VIN < VDD

Input Current

RST

I

IN2 -10 +300

µA

V

DD = 5.5V

0 < V

IN < VDD

Logic 1-to-0 Transition Current

P1, P2, P3, P4

I

TL -500 -

µA

V

DD = 5.5V

V

IN

= 2V

Input Low Voltage

RST

V

IL2 0 0.8 V VDD = 4.5V

Input Low Voltage

P1, P2, P3, P4

V

IL1 0 0.8 V VDD = 4.5V

Input Low Voltage

XTAL1

[*4]

V

IL3 0 0.8 V VDD = 4.5V

Input High Voltage

P1, P2, P3, P4

VIH1 2.4

VDD

+0.2

V

VDD = 5.5V

Input High Voltage

RST

VIH2 3.5

VDD

+0.2

V VDD = 5.5V

Input High Voltage

XTAL1[*4]

VIH3 3.5

VDD

+0.2

V

VDD = 5.5V

W78C52D/W78C052D

- 12 -

DC Characteristics, continued

SPECIFICATION

PARAMETER SYM.

MIN. MAX. UNIT

TEST CONDITIONS

Output

Output Low Voltage

P1, P2, P3, P4

V

OL1 - 0.45 V

V

DD = 4.5V

I

OL

= +2 mA

Output Low Voltage

P0, ALE,

PSEN

[*4]

V

OL2 - 0.45 V

V

DD = 4.5V

I

OL

= +4 mA

Sink Current

P1, P2, P3, P4

I

SK1 4 8 mA

V

DD = 4.5V

Vin = 0.45V

Sink Current

P0, ALE,

PSEN

I

SK2 8 16 mA

V

DD = 4.5V

V

IN = 0.45V

Output High Voltage

P1, P2, P3, P4

V

OH1 2.4 - V

V

DD = 4.5V

I

OH

= -100 µA

Output High Voltage

P0, ALE,

PSEN

[*4]

V

OH2 2.4 - V

V

DD = 4.5V

I

OH

= -400 µA

Source Current

P1, P2, P3, P4

ISR1

-100 -250

µA

VDD = 4.5V

V

IN = 2.4V

Source Current

P0, ALE,

PSEN

I

SR2 -8 -14 mA

V

DD = 4.5V

V

IN = 2.4V

Notes:
*1. RST pin has an internal pull-down.
*2. Pins of P1 and P3 can source a transition current when they are being externally driven from 1 to 0.
*3. RST is a Schmitt trigger input and XTAL1 is a CMOS input.

*4. P0, P2, ALE and

PSEN

are tested in the external access mode.

W78C52D/W78C052D

Publication Release Date: December 4, 2006

- 13 - Revision A5

8. AC CHARACTERISTICS

The AC specifications are a function of the particular process used to manufacture the part, the ratings
of the I/O buffers, the capacitive load, and the internal routing capacitance. Most of the specifications
can be expressed in terms of multiple input clock periods (TCP), and actual parts will usually
experience less than a ±20 nS variation. The numbers below represent the performance expected
from a 0.5 micron CMOS process when using 2 and 4 mA output buffers.

Clock Input Waveform

T

T

XTAL1

F

CH

CL

OP,

T

CP

PARAMETER SYMBOL MIN. TYP. MAX. UNIT NOTES

Operating Speed FOP 0 - 40 MHz 1

Clock Period TCP 25 - - nS 2

Clock High TCH 10 - - nS 3

Clock Low TCL 10 - - nS 3

Notes:

1. The clock may be stopped indefinitely in either state.

2. The T

CP specification is used as a reference in other specifications.

3. There are no duty cycle requirements on the XTAL1 input.

Program Fetch Cycle

PARAMETER SYMBOL MIN. TYP. MAX. UNIT NOTES

Address Valid to ALE Low TAAS

1 T

CP-∆

- - nS 4

Address Hold from ALE Low TAAH

1 T

CP-∆

- - nS 1, 4

ALE Low to

PSEN

Low

TAPL

1 T

CP-∆

- - nS 4

PSEN

Low to Data Valid

T

PDA - - 2 TCP nS 2

Data Hold after PSEN High

T

PDH 0 - 1 TCP nS 3

Data Float after PSEN High

T

PDZ 0 - 1 TCP nS

ALE Pulse Width TALW

2 T

CP-∆

2 T

CP - nS 4

PSEN Pulse Width

T

PSW

3 T

CP-∆

3 T

CP - nS 4

Notes:

1. P0.0

−P0.7, P2.0−P2.7 remain stable throughout entire memory cycle.

2. Memory access time is 3 T

CP.

3. Data have been latched internally prior to

PSEN going high.

4. "

∆" (due to buffer driving delay and wire loading) is 20 nS.

W78C52D/W78C052D

- 14 -

Data Read Cycle

PARAMETER SYMBOL MIN. TYP. MAX. UNIT NOTES

ALE Low to RD Low

T

DAR

3 T

CP-∆

-

3 TCP+∆

nS 1, 2

RD Low to Data Valid

T

DDA - - 4 TCP nS 1

Data Hold from RD High

T

DDH 0 - 2 TCP nS

Data Float from RD High

T

DDZ 0 - 2 TCP nS

RD Pulse Width

T

DRD

6 T

CP-∆

6 T

CP - nS 2

Notes:

1. Data memory access time is 8 T

CP.

2. "

∆" (due to buffer driving delay and wire loading) is 20 nS.

Data Write Cycle

PARAMETER SYMBOL MIN. TYP. MAX. UNIT

ALE Low to WR Low

T

DAW

3 T

CP-∆

-

3 TCP+∆

nS

Data Valid to WR Low

T

DAD

1 T

CP-∆

- - nS

Data Hold from WR High

T

DWD

1 T

CP-∆

- - nS

WR Pulse Width

T

DWR

6 T

CP-∆

6 T

CP - nS

Note: "∆" (due to buffer driving delay and wire loading) is 20 nS.

Port Access Cycle

PARAMETER SYMBOL MIN. TYP. MAX. UNIT

Port Input Setup to ALE Low TPDS 1 TCP - - nS

Port Input Hold from ALE Low TPDH 0 - - nS

Port Output to ALE TPDA 1 TCP - - nS

Note: Ports are read during S5P2, and output data becomes available at the end of S6P2. The timing data are referenced to

ALE, since it provides a convenient reference.

W78C52D/W78C052D

Publication Release Date: December 4, 2006

- 15 - Revision A5

9. TIMING WAVEFORMS

Program Fetch Cycle

S1

XTAL1

S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6

ALE

PORT 2

A0-A7

A0-A7

Data

A0-A7

Code

T

A0-A7

Data

Code

PORT 0

PSEN

PDH,TPDZ

T

PDA

T

AAH

T

AAS

T

PSW

T

APL

T

ALW

Data Read Cycle

S2 S3S5 S6 S1S2 S3 S4S5 S6 S1S4

XTAL1

ALE

PSEN

DATA

A8-A15

PORT 2

PORT 0

A0-A7

RD

T

DDH,TDDZ

T

DDA

T

DRD

T

DAR

W78C52D/W78C052D

- 16 -

Data Write Cycle

S2 S3S5 S6 S1S2 S3 S4S1S5 S6S4

XTAL1

ALE

PSEN

A8-A15

DATA OUT

PORT 2

PORT 0

A0-A7

WR

T

T

DAW

DAD

T

DWR

T

DWD

Port Access Cycle

XTAL1

ALE

S5 S6 S1

DATA OUT

T

T

PORT

INPUT

T

SAMPLE

PDA

PDHPDS

W78C52D/W78C052D

Publication Release Date: December 4, 2006

- 17 - Revision A5

10. APPLICATION CIRCUITS

Expanded External Program Memory and Crystal

AD0

A0

A0

A0

10

A1

9

A2

8

A3

7

A4

6

A5

5

A6

4

A7

3

A8

25

A9

24

A10

21

A11

23

A12

2

A13

26

A14

27

A15

1

CE

20

OE

22

O0

11

O1

12

O2

13

O3

15

O4

16

O5

17

O6

18

O7

19

27512

AD0

D0

3

Q0

2

D1

4

Q1

5

D2

7

Q2

6

D3

8

Q3

9

D4

13

Q4

12

D5

14

Q5

15

D6

17

Q6

16

D7

18

Q7

19

OC

1

G

11

74HC373

AD0

EA

31

XTAL1

19

XTAL2

18

RST

9

INT0

12

INT1

13

T0

14

T1

15

P1.0

1

P1.1

2

P1.2

3

P1.3

4

P1.4

5

P1.5

6

P1.6

7

P1.7

8

39
38
37
36
35
34

33
32

21
22
23
24
25
26
27
28

17

WR

P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7

P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7

RD

16

PSEN

29

ALE

30

TXD

11

RXD

10

W78C52D/W78C052D

10 u

8.2 K

DD

CRYSTAL

C1

C2

R

AD1
AD2
AD3
AD4
AD5
AD6
AD7

A8

AD1
AD2
AD3
AD4
AD5
AD6
AD7

GND

A1
A2
A3
A4
A5
A6
A7

A1
A2
A3
A4
A5
A6
A7
A8
A9

AD1
AD2
AD3
AD4
AD5
AD6
AD7

A10
A11
A12
A13
A14
A15

GND

A9
A10
A11
A12
A13
A14
A15

V

DD

V

Figure A

CRYSTAL C1 C2 R

16 MHz 30P 30P

−

24 MHz 15P 15P

−

33 MHz 10P 10P 6.8K

40 MHz 5P 5P 4.7K

Above table shows the reference values for crystal applications.

Note: C1, C2, R components refer to Figure A.

W78C52D/W78C052D

- 18 -

Expanded External Data Memory and Oscillator

10 u

8.2 K

DD

OSCILLATO

R

EA

31

XTAL1

19

XTAL2

18

RST

9

INT0

INT1
T0
T1

P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7

12
13
14
15

1
2
3

4
5
6
7
8

P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7

39
38
37
36
35
34
33
32

P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7

RD

17

WR

16

PSEN

29

ALE

30

TXD

11

RXD

10

W78C52D/W78C052D

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7

A0
A1
A2
A3
A4
A5
A6
A7

D0 Q0

2

D1 Q1

5

D2 Q2

6

D3 Q3

9

D4 Q4

12

D5 Q5

15

D6 Q6

16

D7

AD7

AD0

AD1

AD2
AD3
AD4
AD5
AD6

3
4
7
8
13
14
17
18

Q7

19

OC

1

G 11

74HC373

A0
A1
A2

A3
A4
A5
A6
A7

10

9
8
7
6
5
4
3

A0
A1
A2
A3
A4
A5
A6
A7

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7

11

12
13
15
16
17
18
19

D0
D1
D2
D3
D4
D5
D6
D7

A8
A9
A10
A11
A12
A13
A14

25
24
21
23

26

1

20

2

A8
A9

A10
A11
A12
A13
A14

CE

GND

21
22

23
24
25
26
27
28

A8

A9

A10
A11
A12
A13
A14

GND

22
27

OE
WR

20256

V

DD

V

Figure B

W78C52D/W78C052D

Publication Release Date: December 4, 2006

- 19 - Revision A5

11. PACKAGE DIMENSIONS

40-pin DIP

Seating Plane

1. Dimension D Max. & S include mold flash or
tie bar burrs.

2. Dimension E1 does not include interlead flash

.

3. Dimension D & E1 include mold mismatch and
are determined at the mold parting line.

6. General appearance spec. should be based o

n

final visual inspection spec.

.

1.3721.219

0.0540.048

Notes:

Symbol

Min.

Nom.

Max. Max.

Nom.

Min.

Dimension in inchDimension in m

m

0.050 1.27

0.210

5.334

0.010

0.150

0.016

0.155

0.018

0.160

0.022

3.81

0.406

0.254

3.937

0.457

4.064

0.559

0.008

0.120

0.670

0.010

0.130

0.014

0.140

0.203

3.048

0.254

3.302

0.356

3.556

0.540

0.550

0.545

13.72

13.97

13.84

17.01

15.24

14.986

15.494

0.6000.590

0.610

2.286 2.54 2.7940.090 0.100

0.110

A

B

c
D

e

A

L

S

A
A

1

2

E

B

1

1

e

E

1

a

2.055 2.070

52.20

52.58

015

0.090

2.286

0.650

0.630 16.00

16.51

protrusion/intrusion.

4. Dimension B1 does not include dambar

5. Controlling dimension: Inches.

150

e

A

A

a

c

E

Base Plane

1

A

1

e

L

A

S

1

E

D

1

B

B

40

21

20

1

2

44-pin PLCC

44 40

39

29

2818

17

7

61

L

c

1

b

2A

H

D

D

e

b

E

H

E

y

A

A

1

Seating Plane

D

G

G

E

Symbol

Min.

Nom.

Max. Max.

Nom.

Min.

Dimension in inch Dimension in mm

A

e

H

E

L

y

b
c
D

A
A

1

2

E

b

1

H

D

G

G

D

E

Notes:

on final visual inspection spec.

4. General appearance spec. should be based

3. Controlling dimension: Inches

protrusion/intrusion.

2. Dimension b1 does not include dambar

flash.

1. Dimension D & E do not include interlead

0.020

0.145

0.026

0.016

0.008

0.648

0.590

0.680

0.090

0.150

0.028

0.018

0.010

0.653

0.610

0.690

0.100

0.050

BSC

0.185

0.155

0.032

0.022

0.014

0.658

0.630

0.700

0.110

0.004

0.508

3.683

0.66

0.406

0.203

16.46

14.99

17.27

2.296

3.81

0.711

0.457

0.254

16.59

15.49

17.53

2.54

1.27

4.699

3.937

0.813

0.559

0.356

16.71

16.00

17.78

2.794

0.10

BSC

16.71

16.59

16.46

0.658

0.653

0.648

16.00

15.4914.99

0.6300.610

0.590

17.7817.53

17.27

0.700

0.690

0.680

θ

W78C52D/W78C052D

- 20 -

44-pin QFP

Seating Plane

11

22

12

See Detail F

e

b

A

y

1

A

A

L

L

1

c

E

E

H

1

D

44

H

D

34

33

Detail F

1. Dimension D & E do not include interl
flash.

2. Dimension b does not include dam

b

protrusion/intrusion.

3. Controlling dimension: Millimet

e

4. General appearance spec. should be b

a

on final visual inspection spec

0.2540.101

0.0100.004

Notes:

Symbol

Min.

Nom.

Max. Max.

Nom.

Min.

Dimension in inch

Dimension in mm

A

b
c
D

e

H

D

H

E

L

y

A
A

L

1

1

2

E

0.006 0.152

---

0.002

0.075

0.01

0.081

0.014

0.087

0.018

1.90

0.25

0.05

2.05

0.35

2.20

0.45

0.390

0.025

0.063

0.003

0

7

0.394

0.031

0.398

0.037

9.9

0.80

0.65

1.6

10.00

0.8

10.1

0.95

0.3980.394

0.390

0.530

0.520

0.510 13.45

13.2

12.95

10.1

10.00

9.9

7

0

0.08

0.031

0.01 0.02 0.25

0.5

---

---

--- ---

---

θ

2

θ

0.025

0.036

0.635

0.952

0.530

0.520

0.510

13.45

13.2

12.95

0.051

0.075 1.295

1.905

W78C52D/W78C052D

Publication Release Date: December 4, 2006

- 21 - Revision A5

12. REVISION HISTORY

VERSION DATE PAGE DESCRIPTION

A1 December 1998 - Initial Issued

A2 April 20, 2005 19 Add Important Notice

A3 December 27, 2005

-

2

13

Remove “Preliminary” from sheet header

Add lead-free(RoHS) parts, Remove 24MHz parts

Amend 24MHz as 40MHz

A4 October 3, 2006 Remove block diagram

A5 December 4, 2006 2 Remove all Leaded package parts

Important Notice

Winbond products are not designed, intended, authorized or warranted for use as components
in systems or equipment intended for surgical implantation, atomic energy control
instruments, airplane or spaceship instruments, transportation instruments, traffic signal
instruments, combustion control instruments, or for other applications intended to support or
sustain life. Further more, Winbond products are not intended for applications wherein failure
of Winbond products could result or lead to a situation wherein personal injury, death or
severe property or environmental damage could occur.

Winbond customers using or selling these products for use in such applications do so at their
own risk and agree to fully indemnify Winbond for any damages resulting from such improper
use or sales.

Headquarters

No. 4, Creation Rd. III,
Science-Based Industrial Park,
Hsinchu, Taiwan
TEL: [phone]
FAX: [phone]
http://www.winbond.com.tw/

Taipei Office

TEL: [phone]
FAX: [phone]

Winbond Electronics Corporation America

2727 North First Street, San Jose,
CA 95134, U.S.A.
TEL: [phone]
FAX: [phone]

Winbond Electronics (H.K.) Ltd.

No. 378 Kwun Tong Rd.,
Kowloon, Hong Kong

FAX: [phone]

Unit 9-15, 22F, Millennium City,

TEL: [phone]

Please note that all data and specifications are subject to change without notice.
All the trademarks of products and companies mentioned in this datasheet belong to their respective owners.

Winbond Electronics (Shanghai) Ltd.

200336 China

FAX: [phone]

27F, 2299 Yan An W. Rd. Shanghai,

TEL: [phone]

Winbond Electronics Corporation Japan

Shinyokohama Kohoku-ku,
Yokohama, 222-0033

FAX: [phone]

7F Daini-ueno BLDG, 3-7-18

TEL: [phone]

9F, No.480, Rueiguang Rd.,

Neihu District, Taipei, 114,

Taiwan, R.O.C.