Datasheet W741C260 Datasheet (Winbond Electronics)

W741C260

4-BIT MICROCONTROLLER

Table of Contents--

GENERAL DESCRIPTION.........................................................................................................................2

FEATURES.................................................................................................................................................2

PIN CONFIGURATION...............................................................................................................................3

PIN DESCRIPTION.....................................................................................................................................4

BLOCK DIAGRAM......................................................................................................................................5

FUNCTIONAL DESCRIPTION ...................................................................................................................6

ABSOLUTE MAXIMUM RATINGS.............................................................................................................34

DC CHARACTERISTICS............................................................................................................................35

AC CHARACTERISTICS............................................................................................................................36

PAD ASSIGMENT & POSITIONS..............................................................................................................37

TYPICAL APPLICATION CIRCUIT.............................................................................................................39

INSTRUCTION SET TABLE.......................................................................................................................40

PACKAGE DIMENSION.............................................................................................................................90

Publication Release Date: March 1998

- 1 - Revision A3

W741C260

GENERAL DESCRIPTION

The W741C260 is a high-performance 4-bit microcontroller (µC) with an LCD driver. The device
contains a 4-bit ALU, two 8-bit timers, two dividers, a 32 × 4 LCD driver, and five 4-bit I/O ports
(including 1 output port to drive the LEDs). There are also five interrupt sources and 8-level
subroutine nesting for interrupt applications. The W741C260 has two power reduction modes, hold
mode and stop mode, which help to minimize power dissipation.

The W741C260 has two oscillator circuits and can work in dual-clock or single-clock operation mode.
It is suitable for remote controllers, watches and clocks, speech synthesis LSI controllers, hand-held
games and other products.

FEATURES

• Operating voltage: 2.2V to 5.5V (LCD drive voltage: 3.0V, or 4.5V)

• Operating frequency up to 4 MHz

• Crystal/RC oscillation circuit selectable by code option for system clock

• 32.768 KHz crystal oscillation circuit for sub-oscillator

• High-frequency clock (400 KHz to 4 MHz) or low-frequency clock (32.768 KHz) for crystal mode;

selectable by code option

• Memory

− 2048 × 16 bit program ROM (including 2K × 4 bit look-up table)

− 128 × 4 bit data RAM (including 16 working registers)

− 32 × 4 LCD data RAM

• 21 input/output pins

− Ports for input only: 2 ports/8 pins

− Input/output ports: 2 ports/8 pins

− Port for output only: 1 port /4 pins (high sink current to drive LEDs)

− MFP output pin: 1 pin (MFP)

• Power-down mode

− Hold function: no operation (except for oscillator)

− Stop function: no operation (including main oscillator)

• Five types of interrupts

− Four internal interrupts (Divider 0, Divider 1, Timer 0, Timer 1)

− One external interrupt (Port RC)

• LCD driver output

− 32 segment × 4 common

− Static, 1/2 duty (1/2 bias), 1/3 duty (1/2 or 1/3 bias), 1/4 duty (1/3 bias) driving mode can be

selected

− LCD driver output pins can be used as DC output ports; selectable by code option

- 2 -

W741C260

• MFP output pin

− Output is software selectable as modulating or nonmodulating frequency

− Works as frequency output specified by Timer 1

• Two built-in 14-bit clock frequency divider circuit (divider 0 and divider 1)

• Two built-in 8-bit programmable countdown timers

− Timer 0: one of two internal clock frequencies (FOSC/4 or FOSC/1024) can be selected

− Timer 1: includes an auto-reload function; and one of two internal clock frequencies (FOSC or

FOSC/64) can be selected or falling edge of pin RC.0 can be selected (output through MFP pin)

• Built-in 18/14-bit watchdog timer selectable for system reset

• Powerful instruction set: 118 instructions

• 8-level subroutine (include interrupt) nesting

• Up to 1 µS instruction cycle (with 4 MHz operating frequency)

• Packaged in 80-pin QFP

PIN CONFIGURATION

RA2
RA3
RB0
RB1
RB2
RB3
RC0
RC1
RC2
RC3
RD0
RD1

RD3
RE0

X

X

M

R

R

F

A

A

P

0 1

1

64

62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46

65
66
67
68
69
70
71
72
73
74
75
76
77RD2
78
79
80RE1

1 2 3 4 5 6 7 8 9

R R

NCN

E E

C

2 3

I

UTV

R

N

N

E
S

C

C

11

V

NCN

C

S

C

O

S

M
3 2 1 0 0 1 2 3 4 5

O

/

X
I

D N N

NCN

N

D C C

C

10 11 12 13 14 15 16 17 18 19

C

C

C

S

O

O

O

E

M

M

M

G

S

S S

X
O

D

U

H

T

1

22

S

S

S

S

E

E

E

E

G

G

G

G

V

V

V

D

D

D

D

H

D

D

D

2

3

2

45 44 43 42 41

20 21 22 23 24

S

S

S

S

E

E

E

E

G

G

G

G

6 7 8 9 101

E
G
3
1

S
E
G

G
3 2 2N
0 9 8

S

S
E

E
G

G

1

S
EEGE
G

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25

N
C

SEG27
SEG26
SEG25
SEG24
SEG23
SEG22
SEG21
SEG20
SEG19
SEG18
SEG17
SEG16
SEG15
SEG14
SEG13
SEG12

Publication Release Date: March 1998

- 3 - Revision A3

W741C260

RES

PIN DESCRIPTION

SYMBOL I/O FUNCTION

XIN1 I Input pin for oscillator.

Connected to crystal or resistor to generate system clock by code option.

XOUT1 O Output pin for oscillator.

Connected to crystal or resistor to generate system clock by code option.
XIN2 I Input pin for sub-oscillator. Connected to a 32.768 KHz crystal.
XOUT2 O Output pin for sub-oscillator. Connected to a 32.768 KHz crystal.
RA0−RA3

RB0−RB3

RC0−RC3

RD0−RD3
RE0−RE3

MFP O

I/O Input/Output port.

Input/output mode specified by port mode 1 register (PM1).

I/O Input/Output port.

Input/output mode specified by port mode 2 register (PM2).

I 4-bit port for input only.

Each pin has an independent interrupt capability.

I 4-bit port for input only.

O Output port only.

This port provides high sink current to drive LEDs.

Output pin only.

This pin can output modulating or nonmodulating frequency, or Timer 1

clock output specified by mode register 1 (MR1).

I System reset pin with pull-high resistor.

SEG0−SEG31

O LCD segment output pins.

Can also be used as DC output ports specified by code option.
COM0−COM3

O LCD common signal output pins.

COM0
COM1
COM2
COM3

Static

Used
Not Used
Not Used
Not Used

1/2 Duty

Used

Used
Not Used
Not Used

1/3 Duty

Used
Used
Used

Not Used

1/4 Duty

Used
Used
Used
Used

The LCD alternating frequency can be selected by code option.
DH1, DH2 I Connection terminals for voltage doubler (halver) capacitor.
VDD1, VDD2,

VDD3 I

Positive (+) supply voltage terminal.

Refer to Functional Description.
VDD I Positive power supply (+).
VSS I Negative power supply (-).

- 4 -

BLOCK DIAGRAM

W741C260

(128 x 4)

(2048 x 16)

(look_up table

+1(+2)

(8 Levels)

RAM

ROM

2K x 4)

PC

STACK

SEG0 to SEG31

ACC

ALU

Central Control

Unit

IEF

HCF

EVF

PSR0 PR MR1

. . .

COM0 to COM3

LCD DRIVER

PEFHEF

SEF

VDD1 to 3 DH1 to 2

PORT RA

PORT RB

PORT RC

PORT RD

PORT RE

SEL

MUX

RA0 to 3

RB0 to 3

RC0 to 3

RD0 to 3

RE0 to 3

MFP

Timer 0

(8-bit)

Watchdog Timer

(4-bit)

Timer 1

(8-bit)

Divider 0

(14-bit)

Modulation
Frequency
Pulse

XIN1 XOUT1

Timing Generator

Divider 1

(13/14-bit)

VDD
VSS

RES

XIN2 XOUT2

Publication Release Date: March 1998

- 5 - Revision A3

W741C260

FUNCTIONAL DESCRIPTION

Program Counter (PC)

Organized as an 11-bit binary counter (PC0 to PC10), the program counter generates the addresses
of the 2048 × 16 on-chip ROM containing the program instructions. When the jump or subroutine call
instructions or the interrupt or initial reset conditions are to be executed, the address corresponding to
the instruction will be loaded into the program counter. The format used is shown below.

ITEM ADDRESS INTERRUPT PRIORITY

Initial Reset 000H ­INT 0 (Divider 0) 004H 1st
INT 1 (Timer 0) 008H 2nd
INT 2 (Port RC) 00CH 3rd
INT 4 (Divider 1) 014H 4th
INT 7 (Timer 1) 020H 5th
JP Instruction XXXH ­Subroutine Call XXXH -

Stack Register (STACK)

The stack register is organized as 11 bits × 8 levels (first-in, last-out). When either a call subroutine or
an interrupt is executed, the program counter will be pushed onto the stack register automatically. At
the end of a call subroutine or an interrupt service subroutine, the RTN instruction must be executed
to pop the contents of the stack register into the program counter. When the stack register is pushed
over the eighth level, the contents of the first level will be lost. In other words, the stack register is
always eight levels deep.

Program Memory (ROM)

The read-only memory (ROM) is used to store program codes; the look-up table is arranged as 2048
× 4 bits. The first three quarters of ROM (000H to 5FFH) are used to store instruction codes only, but
the last quarter (600H to 7FFH) can store both instruction codes and the look-up table. Each look-up
table element is composed of 4 bits, so the look-up table can be addressed up to 2048 elements.
There are two registers (TABL and TABH) to be used in look-up table addressing and they are
controlled by MOV TABH, R and MOV TABL, R instructions. When the instruction MOVC R is
executed, the contents of the look-up table location address specified by TABH, TABL and ACC will
be read and transfered to the data RAM. Refer to the instruction table for more details. The
organization of the program memory is shown in Figure 1.

- 6 -

000H

W741C260

16 bits

ACCTABLTABH

2048

address

600H

7FFH

- x x x x x x x x x y y

0 1 1 x x x x x x x x x

ROM address = 600H + Offset/4

3 2 1 0

2048 x 16-bit

Figure 1. Program Memory Organization

This area can be used to store both instruction code
and look-up table

Each element (4 bits) of the look-up table

Offset

Data Memory (RAM)

1. Architecture

The static data memory (RAM) used to store data is arranged as 128 × 4 bits. The data memory can
be addressed directly or indirectly. The organization of the data memory is shown in Figure 2.

4 bits

00H

:

Working Register

0FH

128

address

7FH

128 x 4-bit

Figure 2. Data Memory Organization

The first sixteen addresses (00H to 0FH) in the data memory are known as the working registers
(WR). The other data memory is used as general memory and cannot operate directly with immediate
data. The relationship between data memory locations and the page register (PAGE) in indirect
addressing mode is described in the next section.

Publication Release Date: March 1998

- 7 - Revision A3

W741C260

2. Page Register (PAGE)

The page register is organized as a 4-bit binary register. The bit descriptions are as follows:

0123

PAGE

Note: R/W means read/write available.

Bit 3 is reserved.
Bit 2, Bit 1, Bit 0 Indirect addressing mode preselect bits:

000 = Page 0 (00H−0FH) 001 = Page 1 (10H−1FH)
010 = Page 2 (20H−2FH) 011 = Page 3 (30H−3FH)
100 = Page 4 (40H−4FH) 101 = Page 5 (50H−5FH)
110 = Page 6 (60H−6FH) 111 = Page 7 (70H−7FH)

R/WR/W R/W R/W

Accumulator (ACC)

The accumulator (ACC) is a 4-bit register used to hold results from the ALU and transfer data
between the memory, I/O ports, and registers.

Arithmetic and Logic Unit (ALU)

This is a circuit which performs arithmetic and logic operations. The ALU provides the following
functions:

• Logic operations: ANL, XRL, ORL

• Branch decisions: JB0, JB1, JB2, JB3, JNZ, JZ, JC, JNC, DSKZ, DSKNZ, SKB0, SKB1, SKB2,

SKB3

• Shift operations: SHRC, RRC, SHLC, RLC

• Binary additions/subtractions: ADC, SBC, ADD, SUB, ADU, DEC, INC

After any of the above instructions are executed, the status of the carry flag (CF) and zero flag (ZF) is
stored in the internal registers. Otherwise CF can be stored or be read out by executing MOVA R, CF
or MOV CF, R.

Clock Generator

The W741C260 provides two oscillation circuits, main-oscillator and sub-oscillator. The main­oscillator can select the crystal or RC oscillation circuit by option codes to generate the system clock
through external connections. If a crystal oscillator is used, a crystal or a ceramic resonator must be
connected to XIN1 and XOUT1, and a capacitor must be connected if an accurate frequency is
needed. When the oscillator is used, a high-frequency clock (400 KHz to 4 MHz) or low-frequency
clock (32 KHz) can be selected for the system clock by means of option codes. If the RC oscillator is
used, a resistor must be connected to XIN1 and XOUT1, and the high/low frequency clock option
must be selected to suit the operation frequency. The sub-oscillator must be connected to a 32.768
KHz crystal through XIN2 and XOUT2 external pins when the dual-clock operation mode is selected
by option code. The connection is shown in Figure 3. One machine cycle consists of a four-state
system clock sequence and can run up to 1 µS with a 4 MHz system clock.

- 8 -

W741C260

XIN2

XOUT2

32 KHz or

400K to 4MHz

XIN1

Crystal Crystal

or

Figure 3. Oscillator Configuration

Resistor

32 KHz

XOUT1

Dual-clock operation

This operation mode is selected by code option. In the dual-clock mode, the clock source of the LCD
frequency selector should be the sub-oscillator clock (32768 Hz) only. But in the single-clock mode,
the clock source of the LCD frequency selector will be Fm or Fm/32 (Fm: main oscillator clock).

In this dual-clock mode, the normal operation is performed by generating the system clock from the
main-oscillator clock (Fm). As required, the slow operation can be performed by generating the
system clock from the sub-oscillator clock (Fs). The exchange of the normal operation and the slow
operation is performed by resetting or setting the bit 0 of the system clock control register (SCR). If
the SCR.0 is reset to 0, the clock source of the system clock generator is the main-oscillator clock; if
the SCR.0 is set to 1, the clock source of the system clock generator is the sub-oscillator clock. In
dual-clock mode, the main-oscillator can stop oscillating when SCR.1 is set to 1. But in the single­clock mode, the main-oscillator can not be stop from oscillating because the SCR would be disabled
in single-clock mode. Therefore, in sigle-clock mode, the clock source of the system clock generator
is the main-oscillator clock (FOSC = Fm).

When the SCR is set or reset, we must pay attention to the following:

1. X000B → X011B: Disable the main-oscillator (Fm) should not be done simultaneously with
changing the system clock source (FOSC) from Fm to Fs. The FOSC should be changed first from
Fm to Fs before the main-oscillator (Fm) is disabled. The correct seqence is:
X000B→X001B→X011B.

2. X011B → X000B: Enabling the main-oscillator (Fm) should not be done simultaneously with
changing the FOSC from Fs into Fm. The main-oscillator (Fm) should be enabled first before a
delay subroutine is called to allow the main-oscillator to oscillate stably. The FOSC can now be
changed from Fs into Fm. The correct sequence is therefore X011B→X001B→delay
subroutine→X000B. The suggested delay for Fm is 20 mS for 455 KHz ceramic resonator and 10
mS for 4 MHz crystal.

We must remember that the X010B state is inhibitive, because it will induce a system shutdown.
The organization of the dual-clock operation mode is shown below.

Publication Release Date: March 1998

- 9 - Revision A3

W741C260

XIN1

XOUT1

SCR.1

XIN2

XOUT2

Mask Option

(Single/Dual Clock)

Mask Option (High/Low Freq.)

SCR.0

Main Oscillator

enable/disable

Sub-oscillator

enable/disable

Figure 4. The Dual Clock Operation Mode Control Diagram

Fm

Fs

Fosc/32

Fosc

Fosc

HOLD

System Clock

Generator

Divider 0

Mask Option (High/Low Freq.)

LCD Frequency

Selector

Mask Option (Single/Dual Clock)

Divider 1

SCR.3 (14/13 bit)

T1

T2
T3
T4

INT4

HCF.4

F

LCD

Divider

Each divider is organized as a 14-bit binary up-counter designed to generate periodic interrupts.
When the main oscillator starts action, the divider0 is incremented by each clock (FOSC). When an
overflow occurs, the divider0 event flag is set to 1 (EVF.0 = 1). The interrupt is executed if the
divider0 interrupt enable flag has been set (IEF.0 = 1), and the hold state is terminated if the hold
release enable flag has been set (HEF.0 = 1). The last 4-stage of the divider0 can be reset by
executing a CLR DIVR0 instruction. If the main oscillator is connected to the 32768 Hz crystal, the
EVF.0 will be set to 1 periodically at each 500 mS interval.

If the sub-oscillator is enabled, the divider1 is incremented by each clock (Fs). When an overflow
occurs, the divider1 event flag is set to 1 (EVF.4 = 1). The interrupt is executed if the divider1
interrupt enable flag has been set (IEF.4 = 1), and the hold state is terminated if the hold release
enable flag has been set (HEF.4 = 1). There are two time periods (250 mS & 500 mS) that can be
selected by setting the SCR.3 bit. When SCR.3 = 0 (default), the 500 mS period time is selected;
when SCR.3 = 1, the 250 mS period time is selected.

Watchdog Timer (WDT)

The watchdog timer (WDT) is organized as a 4-bit up counter and is designed to protect the program

from unknown errors. The WDT is enabled when the corresponding option code bit of the WDT is set
to 1. If the WDT overflows, the chip will be reset. At initial reset, the input clock of the WDT is
FOSC/1024. The input clock of the WDT can be switched to FOSC/16384 (or FOSC/1024) by executing
the SET PMF, #08H (or CLR PMF, #08H) instruction. The contents of the WDT can be reset by the
instruction CLR WDT. In normal operation, the application program must reset WDT before it
overflows. A WDT overflow indicates that the operation is not under control and the chip will be reset.
The WDT minimun overflow period is 468.75 mS when the system clock (FOSC) is 32 KHz and WDT
clock input is FOSC/1024. When the corresponding option code bit of the WDT is set to 0, and the
WDT function is disabled. The organization of the Divider0 and watchdog timer is shown in Figure 4.

- 10 -

W741C260

S

Fosc

Divider0

Q1 Q2 Q9 Q10 Q11 Q12

...

Fosc/16384
Fosc/1024

PMF.3

Mask Option

Figure 4. Organization of Divider 0 and Watchdog Timer

Q13

Enable
/Disable

Q14

RRRR

EVF.0

Q

R

WDT

Qw1 Qw2

R R R R

Qw3

HEF.0

IEF.0

1. Reset

2. CLR EVF, #01H

3. CLR DIVR0

Overflow signal

Qw4

1. Reset

2. CLR WDT

Hold mode release (HCF.0)

Divider0 interrupt (INT0)

System Reset

Timer/Counter

1. Timer 0 (TM0)

Timer 0 (TM0) is a programmable 8-bit binary down-counter. The specified value can be loaded into
TM0 by executing the MOV TM0L (TM0H), R or MOV TM0, #I instructions. When the MOV TM0L
(TM0H), R instructions are executed, the TM0 will stop down-counting (if the TM0 is down-counting),
the MR0.3 will be reset to 0, and the specified value is loaded into TM0. If MR0.3 is set to 1, the
event flag 1 (EVF.1) is reset and the TM0 starts to count. When it decrements to FFH, Timer 0 stops
operating and generates an underflow (EVF.1 = 1). The interrupt is executed if the Timer 0 interrupt
enable flag has been set (IEF.1 = 1); and the hold state is terminated if the hold release enable flag 1
has been set (HEF.1 = 1). The Timer 0 clock input can be set as FOSC/1024 or FOSC/4 by setting
MR0.0 to 1 or by resetting MR0.0 to 0. The default timer value is FOSC/4. The organization of Timer 0
is shown in Figure 5.

If the Timer 0 clock input is FOSC/4, then:

Desired Time 0 interval = (preset value +1) × 4 × 1/FOSC

If the Timer 0 clock input is FOSC/1024, then:

Desired Time 0 interval = (preset value +1) × 1024 × 1/FOSC
Preset value: Decimal number of Timer 0 preset value
FOSC: Clock oscillation frequency

Publication Release Date: March 1998

- 11 - Revision A3

1. Reset

2. CLR EVF, #02H

3. Reset MR0.3 to 0

4. MOV TM0L, R or MOV TM0H, R

W741C260

MR0.0

Fosc/1024

Fosc/4

1. Set MR0.3 to 1

2. MOV TM0, #I

Disable

8-bit Binary

Down Counter

Enable

MOV TM0H, R

MOV TM0, #I

S

(Timer 0)

4

Figure 5. Organization of Timer 0

4

8

MOV TM0L, R

Q

R

EVF.1

HEF.1
IEF.1

Hold mode release (HCF.1)
Timer 0 interrupt (INT1)

1. Reset

2. CLR EVF, #02H

3. Set MR0.3 to 1

4. MOV TM0, #I

2. Timer 1 (TM1)

Timer 1 (TM1) is also a programmable 8-bit binary down counter, as shown in Figure 6. Timer 1 can
be used as a counter to count external events or to output an arbitrary frequency to the MFP pin. The
input clock of Timer 1 can be one of three sources: FOSC/64, FOSC, or an external clock from the
RC.0 input pin. The source can be selected by setting bit 0 and bit 1 of mode register 1 (MR1). At
initial reset, the Timer 1 clock input is FOSC. If an external clock is selected as the clock source of
Timer 1, the content of Timer 1 is decreased by 1 at the falling edge of RC.0. When the MOV TM1L,
R or MOV TM1H, R instruction is executed, the specified data are loaded into the auto-reload buffer
and the TM1 down-counting will be disabled (i.e. MR1.3 is reset to 0). If the bit 3 of MR1 is set
(MR1.3 = 1), the contents of the auto-reload buffer will be loaded into the TM1 down counter, Timer 1
starts to down count, and the event flag 7 is reset (EVF.7 = 0). When the MOV TM1, #I instruction is
executed, the event flag 7 (EVF.7) and MR1.3 are reset and the specified value is loaded into auto­reload buffer and TM1 by the internal hardware, then the MR1.3 is set, that is the TM1 starts to count
by the hardware. When the timer decrements to FFH, it will generate an underflow (EVF.7 = 1) and
be auto-reloaded with the specified data, after which it will continue to count down. An interrupt is
executed if the interrupt enable flag 7 has been set to 1 (IEF.7 = 1), and the hold state is terminated if
the hold mode release enable flag 7 is set to 1 (HEF.7 = 1). The specified frequency of Timer 1 can
be delivered to the MFP output pin by programming bit 2 of MR1. Bit 3 of MR1 can be used to make
Timer 1 stop or start counting.

If the Timer 1 clock input is FT, then:
Desired Timer 1 interval = (preset value +1) / FT

Desired frequency for MFP output pin = FT ÷ (preset value + 1) ÷ 2 (Hz)
Preset value: Decimal number of Timer 1 preset value, and
FOSC: Clock oscillation frequency

- 12 -

MOV TM1, #I

W741C260

4

(Timer 1)

Reset

MOV TM1L, R

8

4

8 bits

Underflow

signal

2

circuit

Reset

MFP signal

S

Q

R

1. Reset

2. INT 7 accept

3. CLR EVF, #80H

4. Set MR1.3 to 1

5. MOV TM1, #I

output pin

MR1.2

EVF.7

MFP

External clock

via RC.0

Fosc/64

Fosc

1. MR1.3 = 1

2. MOV TM1, #I

MR1.0

MR1.1

MOV TM1H, R

Enable

F

T

Disable

1. MR1.3 = 0

Auto-reload buffer

8-bit Binary

Down Counter

Set MR1.3 to 1

MOV TM1, #I

Figure 6. Organization of Timer 1

For example, when FT equals 32768 Hz, depending on the preset value of TM1, the MFP pin will
output a single tone signal in the tone frequency range from 64 Hz to 16384 Hz. The relation between
the tone frequency and the preset value of TM1 is shown in the table below.

3 4

Tone

frequency

C 130.81 7CH 131.07 261.63 3EH 260.06 523.25 1EH 528.51
C# 138.59 75H 138.84 277.18 3AH 277.69 554.37 1CH 564.96

T D 146.83 6FH 146.28 293.66 37H 292.57 587.33 1BH 585.14

D# 155.56 68H 156.03 311.13 34H 309.13 622.25 19H 630.15

O E 164.81 62H 165.49 329.63 31H 327.68 659.26 18H 655.36

F 174.61 5DH 174.30 349.23 2EH 372.36 698.46 16H 712.34

N F# 185.00 58H 184.09 369.99 2BH 390.09 739.99 15H 744.72

G 196.00 53H 195.04 392.00 29H 420.10 783.99 14H 780.19

E G# 207.65 4EH 207.39 415.30 26H 443.81 830.61 13H 819.20

A 220.00 49H 221.40 440.00 24H 442.81 880.00 12H 862.84
A# 233.08 45H 234.05 466.16 22H 468.11 932.23 11H 910.22
B 246.94 41H 248.24 493.88 20H 496.48 987.77 10H 963.76

TM1 preset value &

MFP frequency

Tone

frequency

TM1 preset value &

MFP frequency

Tone

frequency

5

TM1 preset value &

MFP frequency

Note: Central tone is A4 (440 Hz).

Publication Release Date: March 1998

- 13 - Revision A3

W741C260

Mode Register 0 (MR0)

Mode Register 0 is organized as a 4-bit binary register (MR0.0 to MR0.3). MR0 can be used to control
the operation of Timer 0. The bit descriptions are as follows:

0123

MR0

Note: W means write only.

Bit 0 = 0 The internal fundamental frequency of Timer 0 is FOSC/4.

= 1 The internal fundamental frequency of Timer 0 is FOSC/1024.
Bit 1 Reserved
Bit 2 Reserved

Bit 3 = 0 Timer 0 stops down-counting.

= 1 Timer 0 starts down-counting.

Mode Register 1 (MR1)

Mode Register 1 is organized as a 4-bit binary register (MR1.0 to MR1.3). MR1 can be used to control
the operation of Timer 1. The bit descriptions are as follows:

MR1

Note: W means write only.

Bit 0 = 0 The internal fundamental frequency of Timer 1 is FOSC.

= 1 The internal fundamental frequency of Timer 1 is FOSC/64.

W W

0123

WW W W

Bit 1 = 0 The fundamental frequency source of Timer 1 is the internal clock.

= 1 The fundamental frequency source of Timer 1 is the external clock from RC.0 input pin.
Bit 2 = 0 The specified waveform of the MFP generator is delivered at the MFP output pin.

= 1 The specified frequency of Timer 1 is delivered at the MFP output pin.
Bit 3 = 0 Timer 1 stops down-counting.

= 1 Timer 1 starts down-counting.

- 14 -

W741C260

Interrupts

The W741C260 provides four internal interrupt sources (Divider 0, Divider 1, Timer 0, Timer 1) and
one external interrupt source (port RC). Vector addresses for each of the interrupts are located in the
range of program memory (ROM) addresses 004H to 020H. The flags IEF, PEF, and EVF are used to
control the interrupts. When EVF is set to "1" by hardware and the corresponding bits of IEF and PEF
have been set by software, an interrupt is generated. When an interrupt occurs, all of the interrupts
are inhibited until the EN INT or MOV IEF,#I instruction is invoked. The interrupts can also be
disabled by executing the DIS INT instruction. When an interrupt is generated in hold mode, the hold
mode will be released momentarily and interrupt subroutine will be executed. After the RTN
instruction is executed in an interrupt subroutine, the µC will enter hold mode again. The operation
flow chart is shown in Figure 8. The control diagram is shown below.

Divider 0

overflow signal

Timer 0

underflow signal

Port RC

signal change

Divider 1

overflow signal

Timer 1

underflow signal

SRQ

SRQ

SRQ

SRQ

SRQ

MOV IEF, #I

EN INT

EVF.0

EVF.1

EVF.2

EVF.4

EVF.7

Initial Reset

IEF.0

IEF.1

IEF.2

IEF.4

IEF.7

Initial Reset
CLR EVF, #I instruction

Disable

Interrupt
Process

Circuit

Enable

Interrupt

Vector

Generator

DIS INT instruction

004H
008H
00CH
014H
020H

Figure 7. Interrupt Event Control Diagram

Interrupt Enable Flag (IEF)

The interrupt enable flag is organized as an 8-bit binary register (IEF.0 to IEF.7). These bits are used
to control the interrupt conditions. It is controlled by the MOV IEF, #I instruction. When one of these
interrupts is accepted, the corresponding to the bit of the event flag will be reset, but the other bits are
unaffected. In interrupt subroutine, these interrupts will be disabled till the instruction MOV IEF, #I or
EN INT is executed again. Therefore, to enable these interrupts, the instructions MOV IEF, #I or EN

Publication Release Date: March 1998

- 15 - Revision A3

W741C260

INT must be executed again. Otherwise, these interrupts can be disabled by executing DIS INT
instruction. The bit descriptions are as follows:

w w

123

ww

7

IEF

Note: W means write only.

IEF.0 = 1 Interrupt 0 is accepted by overflow from the Divider 0.
IEF.1 = 1 Interrupt 1 is accepted by underflow from the Timer 0.
IEF.2 = 1 Interrupt 2 is accepted by a signal change on port RC.
IEF.3 Reserved
IEF.4 = 1 Interrupt 0 is accepted by overflow from the Divider 1.
IEF.5 & IEF.6 are reserved.
IEF.7 = 1 Interrupt 7 is accepted by underflow from Timer 1.

56 0

4
w

Stop Mode Operation

In stop mode, all operations of the µC cease (excluding the operation of sub-oscillator and divider 1
when the dual-clock operation mode is selected). The µC enters stop mode when the STOP
instruction is executed and exits stop mode when an external trigger is activated (by a falling signal
on the RC port). When the designated signal is accepted, the µC awakens and executes the next
instruction (if the corresponding bits of IEF and PEF have been set, It will enter the interrupt service
routine after stop mode released). To prevent erroneous execution, the NOP instruction should follow
the STOP command.

Stop Mode Wake-up Enable Flag for Port RC (SEF)

The stop mode wake-up flag for port RC is organized as a 4-bit binary register (SEF.0 to SEF.3).
Before port RC may be used to make the device exit the stop mode, the content of the SEF must be
set first. The SEF is controlled by the MOV SEF, #I instruction. The bit descriptions are as follows:

3

SEF w w w w

Note: W means write only.

SEF 0 = 1 Device will exit stop mode when falling edge signal is applied to pin RC.0.
SEF 1 = 1 Device will exit stop mode when falling edge signal is applied to pin RC.1.
SEF 2 = 1 Device will exit stop mode when falling edge signal is applied to pin RC.2.
SEF 3 = 1 Device will exit stop mode when falling edge signal is applied to pin RC.3.

012

- 16 -

W741C260

Hold Mode Operation

In hold mode, all operations of the µC cease, except for the operation of the oscillator, timer, divider
and LCD driver. The µC enters hold mode when the HOLD instruction is executed. The hold mode
can be released in one of five ways: by the action of timer 0, timer 1, divider 0, divider 1 or the RC
port. Before the device enters the hold mode, the HEF, PEF, and IEF flags must be set to define the
hold mode release conditions. For more details, refer to the instruction-set table and the following flow
chart.

Divider 0, Divider 1,Timer 0

Timer1, Signal Change on

Port RC

In
HOLD
Mode?

Interrupt

Enable?

Yes

IEF

Flag Set?

Yes

Reset EVF.n Flag

Execute

Interrupt Service Routine

Disable interrupt

HOLD

Note : The bit of EVF corresponding to the interrupt request signal will be reset.

No

HEF

Flag Set?

(Note) (Note)

NoYes

YesNo

Interrupt

Enable?

Yes

IEF

Flag Set?

Yes

Reset EVF.n Flag

Execute

Interrupt Service Routine

Disable interrupt

PC <- (PC+1)

NoNo

No

Figure 8. Hold Mode and Interrupt Operation Flow Chart

Publication Release Date: March 1998

- 17 - Revision A3

W741C260

Hold Mode Release Enable Flag (HEF)

The hold mode release enable flag is organized as an 8-bit binary register (HEF.0 to HEF.7). The
HEF is used to control the hold mode release conditions. It is controlled by the MOV HEF, #I
instruction. The bit descriptions are as follows:

34567

HEF w w w w

Note: W means write only.

HEF.0 = 1 Overflow from the Divider 0 causes hold mode to be released.
HEF.1 = 1 Underflow from Timer 0 causes hold mode to be released.
HEF.2 = 1 Signal change on port RC causes hold mode to be released.
HEF.3 Reserved
HEF.4 = 1 Overflow from the Divider 1 causes hold mode to be released.
HEF.5 & HEF.6 are reserved.
HEF.7 = 1 Underflow from Timer 1 causes hold mode to be released.

w

012

Port Enable Flag (PEF)

The port enable flag is organized as 4-bit binary register (PEF.0 to PEF.3). Before port RC may be
used to release the hold mode or preform interrupt function, the content of the PEF must be set first.
The PEF is controlled by the MOV PEF, #I instruction. The bit descriptions are as follows:

3

PEF w w w

Note: W means write only.

012
w

PEF.0: Enable/disable the signal change on pin RC.0 to release hold mode or perform interrupt.
PEF.1: Enable/disable the signal change on pin RC.1 to release hold mode or perform interrupt.
PEF.2: Enable/disable the signal change on pin RC.2 to release hold mode or perform interrupt.
PEF.3: Enable/disable the signal change on pin RC.3 to release hold mode or perform interrupt.

Hold Mode Release Condition Flag (HCF)

The hold mode release condition flag is organized as a 8-bit binary register (HCF0 to HCF7). It
indicates by which interrupt source the hold mode has been released, and is loaded by hardware. The
HCF can be read out by the MOVA R, HCFL and MOVA R, HCFH instructions. When any of the HCF
bits is "1," the hold mode will be released and the HOLD instruction is invalid. The HCF can be reset
by the CLR EVF,#I (EVF.n = 0) or MOV HEF,#I (HEF.n = 0) instructions. When EVF or HEF have
been reset, the corresponding bit of HCF is reset simultaneously. The bit descriptions are as follows:

012345

Note: R means read only.

67

R RHCF

R R R

- 18 -

W741C260

HCF.0 = 1 Hold mode was released by overflow from the Divider0.
HCF.1 = 1 Hold mode was released by underflow from the Timer 0.
HCF.2 = 1 Hold mode was released by a signal change on port RC
HCF.3 Reservsd
HCF.4 = 1 Hold mode was released by overflow from the Divider 1.
HCF.5 = 1 Hold mode was released by underflow from the Timer 1.
HCF.6 & HCF.7 are reserved.

Event Flag (EVF)

The event flag is organized as an 8-bit binary register (EVF0 to EVF7). It is set by hardware and reset
by CLR EVF,#I instruction or the occurrence of an interrupt. The bit descriptions are as follows:

67

EVF

Note: R means read only.

EVF.0 = 1 Overflow from Divider 0 occurred.
EVF.1 = 1 Underflow from Timer 0 occurred.
EVF.2 = 1 Signal change on port RC occurred.
EVF.3 Reserved
EVF.4 = 1 Overflow from Divider 1 occurred.
EVF.5 & EVF.6 are reserved.
EVF.7 = 1 Underflow from Timer 1 occurred.

R R R

012345

RR

Parameter Flag (PMF)

The parameter flag is organized as a 4-bit binary register (PMF.0 to PMF.3). The PMF is controlled
by the SET PMF, #I or CLR PMF, #I instruction. The bit descriptions are as follows:

0123

PMF

Note: W means write only.

W

Bit 0, Bit1, Bit2 Reserved
Bit 3 = 0 The fundamental frequency of the watchdog timer is FOSC/1024.

= 1 The fundamental frequency of the watchdog timer is FOSC/16384.

Publication Release Date: March 1998

- 19 - Revision A3

W741C260

Port Mode 0 Register (PM0)

The port mode 0 register is organized as a 4-bit binary register (PM0.0 to PM0.3). PM0 can be used
to determine the structure of the input/output ports; it is controlled by the MOV PM0, #I instruction.
The bit descriptions are as follows:

3

PM0 w w w

Note: W means write only.

Bit 0 = 0 RA port is CMOS output type. Bit 0 = 1 RA port is NMOS open drain output type.
Bit 1 = 0 RB port is CMOS output type. Bit 0 = 1 RB port is NMOS open drain output type.
Bit 2 = 0 RC port pull-high resistor is disabled.

= 1 RC port pull-high resistor is enabled.

Bit 3 = 0 RD port pull-high resistor is disabled.

= 1 RD port pull-high resistor is enabled.

012
w

Port Mode 1 Register (PM1)

The port mode 1 register is organized as a 4-bit binary register (PM1.0 to PM1.3). PM1 can be used
to control the input/output mode of port RA. PM1 is controlled by the MOV PM1, #I instruction. The bit
descriptions are as follows:

3

PM1 w w w

Note: W means write only.

012
w

Bit 0 = 0 RA.0 works as output pin; Bit 0 = 1 RA.0 works as input pin
Bit 1 = 0 RA.1 works as output pin; Bit 1 = 1 RA.1 works as input pin
Bit 2 = 0 RA.2 works as output pin; Bit 2 = 1 RA.2 works as input pin
Bit 3 = 0 RA.3 works as output pin; Bit 3 = 1 RA.3 works as input pin
At initial reset, port RA is input mode (PM1 = 1111B).

Port Mode 2 Register (PM2)

The port mode 2 register is organized as a 4-bit binary register (PM2.0 to PM2.3). PM2 can be used
to control the input/output mode of port RB. PM2 is controlled by the MOV PM2, #I instruction. The bit
descriptions are as follows:

3

PM2 w w w

Note: W means write only.

Bit 0 = 0 RB.0 works as output pin; Bit 0 = 1 RB.0 works as input pin

012
w

- 20 -

Bit 1 = 0 RB.1 works as output pin; Bit 1 = 1 RB.1 works as input pin

RES

Bit 2 = 0 RB.2 works as output pin; Bit 2 = 1 RB.2 works as input pin
Bit 3 = 0 RB.3 works as output pin; Bit 3 = 1 RB.3 works as input pin
At initial reset, the port RB is input mode (PM2 = 1111B).

Reset Function

W741C260

The W741C260 is reset either by a power-on reset or by using the external
of the W741C260 after the reset function is executed is described below.

Program Counter (PC) 000H
TM0, TM1 Reset
MR0, MR1, PM0, PAGE, PMF registers Reset
PM1, PM2 registers Set (1111B)
PSR0 register Reset
IEF, HEF, PEF, SEF, HCF, EVF flags Reset
Timer 0 input clock FOSC/4
Timer 1 input clock FOSC
MFP output Low
Input/output ports RA, RB Input mode
Output port RE High
RA & RB ports output type CMOS type
RC & RD ports pull-high resistors Disable
Input clock of the watchdog timer FOSC/1024
LCD display OFF
Segment output mode LCD drive output

pin. The initial state

Publication Release Date: March 1998

- 21 - Revision A3

W741C260

Input/Output Ports RA, RB

Port RA consists of pins RA.0 to RA.3 and port RB consists of pins RB.0 to RB.3. At initial reset,
input/output ports RA and RB are both in input mode. When RA and RB are used as output ports,
CMOS or NMOS open drain output type can be selected by the PM0 register. Each pin of port RA or
RB can be specified as input or output mode independently by the PM1 and PM2 registers. The
MOVA R, RA or MOVA R, RB instructions operate the input functions and the MOV RA, R or MOV
RB, R operate the output functions. For more details, refer to the instruction table and Figure 9.

Input/Output Pin of the RA(RB)

V

DD

PM0.0 (or PM0.1)

Output

DATA

BUS

Buffer

Enable

MOV RA, R
(or MOV RB, R)
Instruction

PM1.n

(or PM2.n)

I/O PIN

RA.n(RB.n)

Enable

Figure 9. Architecture of Input/Output Pins

MOVA R, RA
(or MOVA R, RB)
instruction

Input Ports RC, RD

Port RC consists of pins RC.0 to RC.3, and port RD consists of pins RD.0 to RD.3. Each pin of port
RC and port RD can be connected to a pull-up resistor, which is controlled by the port mode 0 register
(PM0). When the PEF, HEF, and IEF corresponding to the RC port are set, a signal change at the
specified pins of port RC will execute the hold mode release or interrupt subroutine. Port status
register 0 (PSR0) record the signal changing status on the port RC. PSR0 can be read out and
cleared by the MOVA R, PSR0, and CLR PSR0 instructions. Refer to Figure 10 and the instruction
table for more details. The RD port is used as input port only, it has no hold mode release or interrupt
functions.

- 22 -

W741C260

RC.0

RC.1

RC.2

RC.3

PM0.2

PM0.2

PM0.2

PM0.2

DATA BUS

Signal

change

detector

Signal

change

detector

Signal

change

detector

Signal

change

detector

Falling

edge

detector

Falling

edge

detector

Falling

edge

detector

Falling

edge

detector

PEF.0

PEF.1

PEF.2

PEF.3

SEF.0

SEF.1

SEF.2

SEF.3

DckQ

R

DckQ

R

DckQ

R

DckQ

R

PSR0.0

PSR0.1

PSR0.2

PSR0.3

DckQ

R

Reset

MOV PEF, #I

CLR PSR0

Wake up from STOP mode

EVF.2

CLR EVF, #I
Reset

HEF.2

HCF.2

IEF.2

INT 2

Figure 10. Architecture of Input Ports RC

Output Port RE

When the MOV RE, R instruction is executed, the data in the RAM will be output to port RE and it
provides a high sink current to drive LEDs.

Port Status Register 0 (PSR0)

Port status register 0 is organized as 4-bit binary register (PSR0.0 to PSR0.3). PSR0 can be read or
cleared by the MOVA R, PSR0, and CLR PSR0 instructions. The bit descriptions are as follows:

0123

PSR0

Note: R means read only.

Bit 0 = 1 Signal change on RC.0
Bit 1 = 1 Signal change on RC.1
Bit 2 = 1 Signal change on RC.2
Bit 3 = 1 Signal change on RC.3

RR R R

Publication Release Date: March 1998

- 23 - Revision A3

W741C260

MFP Output Pin (MFP)

The MFP output pin can output the Timer 1 clock or the modulation frequency; the output of the pin is
determined by mode register 1 (MR1). The organization of MR1 is shown in Figure 6. When bit 2 of
MR1 is reset to "0," the MFP output can deliver a modulation output in any combination of one signal
from among DC, 4096 Hz, 2048 Hz, and one or more signals from among 128 Hz, 64 Hz, 8 Hz, 4 Hz,
2 Hz, or 1 Hz (when using a 32.768 KHz system clock). The MOV MFP, #I instruction is used to
specify the modulation output combination. The data specified by the 8-bit operand and the MFP
output pin are shown as below:

(Fosc = 32.768 KHz)

R7 R6 R5 R4 R3 R2 R1 R0 FUNCTION

0 0 0 0 0 0 Low level
0 0 0 0 0 1 128 Hz
0 0 0 0 1 0 64 Hz

0 0 0 0 0 1 0 0 8 Hz

0 0 1 0 0 0 4 Hz
0 1 0 0 0 0 2 Hz
1 0 0 0 0 0 1 Hz
0 0 0 0 0 0 High level
0 0 0 0 0 1 128 Hz
0 0 0 0 1 0 64 Hz

0 1 0 0 0 1 0 0 8 Hz

0 0 1 0 0 0 4 Hz
0 1 0 0 0 0 2 Hz
1 0 0 0 0 0 1 Hz
0 0 0 0 0 0 2048 Hz
0 0 0 0 0 1 2048 Hz * 128 Hz
0 0 0 0 1 0 2048 Hz * 64 Hz

1 0 0 0 0 1 0 0 2048 Hz * 8 Hz

0 0 1 0 0 0 2048 Hz * 4 Hz
0 1 0 0 0 0 2048 Hz * 2 Hz
1 0 0 0 0 0 2048 Hz * 1 Hz
0 0 0 0 0 0 4096 Hz
0 0 0 0 0 1 4096 Hz * 128 Hz
0 0 0 0 1 0 4096 Hz * 64 Hz

1 1 0 0 0 1 0 0 4096 Hz * 8 Hz

0 0 1 0 0 0 4096 Hz * 4 Hz
0 1 0 0 0 0 4096 Hz * 2 Hz
1 0 0 0 0 0 4096 Hz * 1 Hz

- 24 -

W741C260

LCD Controller/Driver

The W741C260 can directly drive an LCD with 32 segment output pins and 4 common output pins for
a total of 32 × 4 dots. Option codes can be used to select one of five options for the LCD driving
mode: static, 1/2 bias 1/2 duty, 1/2 bias 1/3 duty, 1/3 bias 1/3 duty, or 1/3 bias 1/4 duty (see Figure

12). The alternating frequency of the LCD can be set as Fw/64, Fw/128, Fw/256, or Fw/512. In
addition, option codes can also be used to set up four of the LCD driver output pins (segment 0 to
segment 31) as a DC output port. The structure of the LCD alternating frequency (FLCD) is shown in
the figure below.

Fosc or Fosc/32

Fs

Mask Option

(Single/Dual Clock)

Figure 11. LCD Alternating Frequency (FLCD) Circuit Diagram

LCD
Frequency
Selection

Fw LCD Mode

Power Selection

DH1
DH2

Clock

Generator

Controller

Fw

Option Codes

Controller

F

LCD

CommomLCD Voltage

Driver

Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9

LCD Duty & Bias

Fw/64

Fw/128

LCD Drive
Mode
Selection

LCD

Waveform

Fw/256

Fw/512

Selector

LCD Data RAM

(32 x 4 bits)

Segment

Driver/Controller

Data Bus

F

LCD

MOV LCDM, #I
Instruction

VDD
VSS

VDD1 to 3

COM0 to 3

Figure 12. LCD Driver/Controller Circuit Diagram

Publication Release Date: March 1998

- 25 - Revision A3

SEG0 to 31

W741C260

When Fw = 32.768 KHz, the LCD frequency is as shown in the table below.

LCD FREQUENCY STATIC 1/2 DUTY 1/3 DUTY 1/4 DUTY

Fw/512 (64 Hz) 64 32 21 16
Fw/256 (128 Hz) 128 64 43 32
Fw/128 (256 Hz) 256 128 85 64
Fw/64 (512 Hz) 512 256 171 128

Corresponding to the 32 LCD drive output pins, there are 32 LCD data RAM segments (LCDR00 to
LCDR1F). Instructions such as MOV LCDR, #I; MOV WR, LCDR; MOV LCDR, WR; and MOV LCDR,
ACC are used to control the LCD data RAM. The data in the LCD data RAM are transferred to the
segment output pins automatically without program control. When the bit value of the LCD data RAM
is "1," the LCD is turned on. When the bit value of the LCD data RAM is "0," LCD is turned off. The
contents of the LCD data RAM (LCDR) are sent out through the segment 0 to segment 31 pins by a
direct memory access. The relationship between the LCD data RAM and segment/common pins is
shown below.

COM3 COM2 COM1 COM0

LCD data RAM Output pin bit 3 bit 2 bit 1 bit 0
LCDR00 SEG0 0/1 0/1 0/1 0/1
LCDR01 SEG1 0/1 0/1 0/1 0/1

.
.
.

.
.
.

.
.
.

.
.
.

.
.
.

.
.
.

LCDR1E SEG30 0/1 0/1 0/1 0/1
LCDR1F SEG31 0/1 0/1 0/1 0/1

The LCDON instruction turns the LCD display on (even in HOLD mode), and the LCDOFF instruction
turns the LCD display off. At initial reset, all the LCD segments are lit. When the initial reset state
ends, the LCD display is turned off automatically. To turn on the LCD display, the instruction LCDON
must be executed. When the drive output pins are used as DC output ports (set by option codes,
please refer the user's manual of ASM741S assembler for more detail), CMOS output type or NMOS
output type can be selected by executing the instruction MOV LCDM, #I. The relation between the
LCD data RAM and segment/common pins is shown below. The data in LCDR00 are transferred to
the corresponding segment output port (SEG3 to SEG0) by a direct memory access. The other LCD
data RAM segments can be used as normal data RAM to store data.

LCD DATA RAM OUTPUT PIN BIT 3 BIT 2 BIT 1 BIT 0

LCDR00
LCDR03−LCDR01

LCDR04

SEG3−SEG0

- - - - -

SEG7−SEG4

SEG3 SEG2 SEG1 SEG0

SEG7 SEG6 SEG5 SEG4

LCDR07−LCDR05

- - - - -

- 26 -

W741C260

Continued

.
.
.

LCDR1C

SEG31−SEG28

LCDR1F−LCDR1D

The relationship between the LCD drive mode and the maximum number of drivable LCD segments
is shown below.

.
.
.

.
.
.

.
.
.

.
.
.

SEG31 SEG30 SEG29 SEG28

- - - - -

.
.
.

LCD DRIVE MODE MAX. NUMBER OF

DRIVABLE LCD SEGMENT

CONNECTION AT

POWER INPUT

Static 32 (COM1) Connect VDD3, VDD2 to VDD1
1/2 Bias 1/2 Duty
1/2 Bias 1/3 Duty
1/3 Bias 1/3 Duty
1/3 Bias 1/4 Duty

64 (COM1−COM2)
96 (COM1−COM3)
96 (COM1−COM3)
128 (COM1−COM4)

Connect VDD3 to VDD2
Connect VDD3 to VDD2

-

-

LCD Output Mode Type Flag (LCDM)

The LCD output mode type flag is organized as an 8-bit binary register (LCDM.0 to LCDM.7). These
bits are used to control the LCD output pins architecture. When LCD output pins are set to DC output
mode by option codes, the architecture of these output pins (segment 0 to segment 31) can be
selected as CMOS or NMOS type. It is controlled by the MOV LCDM, #I instruction. The bit
descriptions are as follows:

7 6

LCDM

Note: W means write only.

5 0

w

4

w w

ww w w w

LCDM.0 = 0 SEG0 to SEG3 work as CMOS output type.

= 1 SEG0 to SEG3 work as NMOS output type.

LCDM.1 = 0 SEG4 to SEG7 work as CMOS output type.

= 1 SEG4 to SEG7 work as NMOS output type.

LCDM.2 = 0 SEG8 to SEG11 work as CMOS output type.

= 1 SEG8 to SEG11 work as NMOS output type.

LCDM.3 = 0 SEG12 to SEG15 work as CMOS output type.

= 1 SEG12 to SEG15 work as NMOS output type.

LCDM.4 = 0 SEG16 to SEG19 work as CMOS output type.

= 1 SEG16 to SEG19 work as NMOS output type.

LCDM.5 = 0 SEG20 to SEG23 work as CMOS output type.

= 1 SEG20 to SEG23 work as NMOS output type.

123

Publication Release Date: March 1998

- 27 - Revision A3

LCDM.6 = 0 SEG24 to SEG27 work as CMOS output type.

= 1 SEG24 to SEG27 work as NMOS output type.

LCDM.7 = 0 SEG28 to SEG31 work as CMOS output type.

= 1 SEG28 to SEG31 work as NMOS output type.

The output waveforms for the five LCD driving modes are shown below.

Static Lighting System (Example)

Normal Operating Mode

W741C260

COM0

Unlit LCD driver

outputs

Lit LCD driver

outputs

1/2 Bias 1/2 Duty Lighting System (Example)

Normal Operating Mode

COM0

COM1

LCD driver
outputs for
seg. on COM0,
COM1 sides
being unlit

VDD2
VDD1
VSS

VDD2
VDD1
VSS

VDD2
VDD1
VSS

VDD2
VDD1
VSS

VDD2
VDD1
VSS

VDD2
VDD1
VSS

LCD driver
outputs for
only seg. on
COM0 side
being lit

VDD2
VDD1
VSS

- 28 -

1/2 Bias 1/2 Duty Lighting System (Example)- Normal Operating Mode, continued

W741C260

LCD driver
outputs for
only seg. on
COM1 side
being lit

LCD driver
outputs for
seg. on COM0,
COM1 sides
being lit

1/2 Bias 1/3 Duty Lighting System (Example)

Normal Operating Mode

COM0

COM1

COM2

VDD2
VDD1
VSS

VDD2
VDD1
VSS

VDD2
VDD1
VSS

VDD2
VDD1
VSS

VDD2
VDD1
VSS

LCD driver
outputs for all
seg. on COM0,1,2
sides being unlit

LCD driver
outputs for only
seg. on COM0
side being lit

LCD driver
outputs for only
seg. on COM1
side being lit

LCD driver
outputs for only
seg. on COM0,1
sides being lit

VDD2
VDD1
VSS

VDD2
VDD1
VSS

VDD2
VDD1
VSS

VDD2
VDD1
VSS

Publication Release Date: March 1998

- 29 - Revision A3

1/2 Bias 1/3 Duty Lighting System (Example)- Normal Operating Mode, continued

W741C260

LCD driver
outputs for only
seg. on COM2
side being lit

LCD driver
outputs for only
seg. on COM0,2
sides being lit

1/3 Bias 1/3 Duty Lighting System (Example)

Normal Operating Mode

COM0

COM1

COM2

LCD driver
outputs for all
seg. on COM0,1,2
sides being unlit

LCD driver
outputs for only
seg. on COM0
side being lit

VDD2
VDD1
VSS

VDD2
VDD1
VSS

VDD3
VDD2
VDD1
VSS

VDD3
VDD2
VDD1
VSS

VDD3
VDD2
VDD1
VSS

VDD3
VDD2
VDD1
VSS

VDD3
VDD2
VDD1
VSS

LCD driver
outputs for only
seg. on COM1
side being lit

outputs for seg.
on COM0,2
sides being lit

LCD driver
outputs for seg.
on COM1,2
sides being lit

LCD driver
outputs for seg.
on COM0,1,2
sides being lit

VDD3
VDD2
VDD1
VSS

VDD3LCD driver
VDD2
VDD1
VSS

VDD3
VDD2
VDD1
VSS

VDD3
VDD2
VDD1
VSS

- 30 -

1/3 Bias 1/4 Duty Lighting System (Example)

Normal Operating Mode

W741C260

COM0

COM1

COM2

COM3

LCD driver
outputs for
only seg. on
COM0 side
being lit

LCD driver
outputs for
only seg. on
COM1 side
being lit

VDD3
VDD2
VDD1
VSS

VDD3
VDD2
VDD1
VSS

VDD3
VDD2
VDD1
VSS

VDD3
VDD2
VDD1
VSS

VDD3
VDD2
VDD1
VSS

VDD3
VDD2
VDD1
VSS

Publication Release Date: March 1998

- 31 - Revision A3

1/3 Bias 1/4 Duty Lighting System (Example)- Normal Operating Mode, continued

W741C260

LCD driver
outputs for
seg. on COM0,
COM1 sides
being lit

LCD driver
outputs for
seg. on COM1,
COM2,3 sides
being lit

LCD driver
outputs for
seg. on COM1
COM2 sides
being lit

LCD driver
outputs for
seg. on COM0
COM2,3 sides
being lit

LCD driver
outputs for
seg. on COM0
COM1,2,3 sides
being lit

VDD3
VDD2
VDD1
VSS

VDD3
VDD2
VDD1
VSS

VDD3
VDD2
VDD1
VSS

VDD3
VDD2
VDD1
VSS

VDD3
VDD2
VDD1
VSS

- 32 -

W741C260

The power connections for each LCD driving mode, which are determined by a mask option, are
shown below.

Static LCD Configuration

DH1

DH1, DH2 floating

DH2

VSS

C
H

I
P

VDD

VDD1

VDD2

VDD3

VDD1 = VDD2 = VDD3 = VDD

VDD

C
H

I
P

1/2 Bias LCD Configuration

DH1

0.1uF

DH2

VSS

VDD

VDD

0.1uF

VDD1

VDD2

VDD3

VDD1 = 1/2 VDD, VDD2 = VDD3 = VDD

1/3 Bias LCD Configuration

DH1

0.1uF

DH2

VSS

C
H

I
P

VDD

0.1uF

VDD

VDD1

VDD2

VDD3

VDD1 = 1/2 VDD, VDD2 = VDD, VDD3 = 3/2 VDD

Publication Release Date: March 1998

- 33 - Revision A3

LCD Configuration, continued

W741C260

1/3 Bias LCD Configuration

DH1

0.1uF

DH2

VSS

C
H

I
P

VDD

0.1uF

VDD1

VDD2

VDD3

VDD

VDD1 = 1/3 VDD, VDD2 = 2/3 VDD, VDD3 = VDD

ABSOLUTE MAXIMUM RATINGS

PARAMETER RATING UNIT

Supply Voltage to Ground Potential -0.3 to +7.0 V
Applied Input/Output Voltage -0.3 to +7.0 V
Power Dissipation 120 mW
Ambient Operating Temperature 0 to +70
Storage Temperature -55 to +150

Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the
device.

°C
°C

- 34 -

W741C260

DC CHARACTERISTICS

(VDD−VSS = 3.0V, Fm = 4.19 MHz, Fs = 32.768 KHz, TA = 25° C, LCD on; unless otherwise specified)

PARAMETER SYM. CONDITIONS MIN. TYP. MAX. UNIT

Op. Voltage VDD - 2.2 - 5.5 V
Op. Current (Crystal Type) IOP1 No load (Ext-V)

In dual-clock normal
operation

Op. Current (RC Type) IOP2 No load (Ext-V)

In dual-clock normal
operation

Op. Current (Crystal Type) IOP3 No load (Ext-V)

In dual-clock slow
operation and Fm is
stopped

Hold Current (Crystal
Type)

IHM1 Hold mode No load (Ext-V)

In dual-clock normal
operation

- 0.6 2.5 mA

- 1 4 mA

- 8.5 20

- 280 450

µA

µA

Hold Current (RC Type) IHM2 Hold mode No load (Ext-V)

In dual-clock normal
operation

Hold Current (Crystal
Type)

Stop Current (Crystal type) ISM1 Stop mode No load (Ext-V)

Stop Current (Crystal type) ISM2 Stop mode No load (Ext-V)

Input Low Voltage VIL - VSS - 0.3 VDD V
Input High Voltage VIH - 0.7 VDD - VDD V
MFP Output Low Voltage VML IOL = 3.5 mA - - 0.4 V
MFP Output High Voltage VMH IOH = 3.5 mA 2.4 - - V
Port RA, RB Output Low

Voltage
Port RA, RB Output High

Voltage

IHM3 Hold mode No load (Ext-V)

In dual-clock slow
operation and Fm is
stopped

In dual-clock normal
operation

In single-clock operation

VABL IOL = 2.0 mA - - 0.4 V

VABH IOH = 2.0 mA 2.4 - - V

- 500 600

- 4.0 6

- 4.0 6

- 0.1 2

µA

µA

µA

µA

Publication Release Date: March 1998

- 35 - Revision A3

W741C260

RES

−

DC Characteristics, continue

PARAMETER SYM. CONDITIONS MIN. TYP. MAX. UNIT

LCD Supply Current ILCD All Seg. ON - - 6
SEG0−SEG31 Sink Current

(Used as LCD Output)
SEG0−SEG31 Drive Current
(Used as LCD Output)

IOL1 VOL = 0.4V

VLCD = 0.0V

IOH1 VOH = 2.4V

VLCD = 3.0V

0.4 - -

0.3 - -

µA
µA

µA

Segment Output Low
Voltage

(Used as DC Output)
Segment Output High

Voltage
(Used as DC Output)
Port RE Sink Current IEL VOL = 0.9V 9 13.5 - mA
Port RE Source Current IEH VOH = 2.4V 0.4 1.2 - mA
Input Port Pull-up Resistor RCD Port RC, RD 100 350 1000

Pull-up Resistor

VSL IOL = 0.6 mA - - 0.4 V

VSH

RRES - 20 100 500

IOH = 3 µA

2.4 - - V

AC CHARACTERISTICS

(VDD−VSS = 3.0V, TA = 25° C, unless otherwise specified)

PARAMETER SYM. CONDITIONS MIN. TYP. MAX. UNIT

RC type - - 4000

Op. Frequency FOSC Crystal type 1 (Option low

speed type)
Crystal type 2 (Option

high speed type)

- 32.768 - KHz

400 - 4190

KΩ
KΩ

Frequency Deviation by
Voltage Drop for RC
Oscillator

Instruction Cycle Time TI One machine cycle - 4/FOSC - S
Reset Active Width TRAW FOSC = 32.768 KHz 1 - ­Interrupt Active Width TIAW FOSC = 32.768 KHz 1 - -

∆f

f

f(3V) f(2.4V)

f(3V)

- 36 -

- - 10 %

µS
µS

PAD ASSIGMENT & POSITIONS

69
1

2
3
4
5
6
7
8

3330 m

µ

9

10

11
12
13
14
15
16
17
18
19

20 21 22 23 24 25 26 27 28 29 30 31

2850 m

Y

(0,0)

µ

60 5962 6164 6366 6568 67

58 57 56 55 54

X

32 33 34 35

W741C260

53
52
51

50
49
48
47
46

45
44
43
42
41
40
39
38
37
36

Note: The chip substrate must be connected to system ground (VSS).

PAD NO. PAD NAME X Y PAD NO. PAD NAME X Y

1 RE2 -1227.00 1122.00 11 SEG3 -1227.00 -178.00
2 RE3 -1227.00 992.00 12 SEG4 -1227.00 -308.00
3 VSS -1227.00 862.00 13 SEG5 -1227.00 -438.00
4 COM3 -1227.00 732.00 14 SEG6 -1227.00 -568.00
5 COM2 -1227.00 602.00 15 SEG7 -1227.00 -698.00
6 COM1 -1227.00 472.00 16 SEG8 -1227.00 -828.00
7 COM0 -1227.00 342.00 17 SEG9 -1227.00 -958.00
8 SEG0 -1227.00 212.00 18 SEG10 -1227.00 -1088.00
9 SEG1 -1227.00 82.00 19 SEG11 -1227.00 -1218.00

10 SEG2 -1227.00 -48.00 20 SEG12 -975.00 -1468.00

Publication Release Date: March 1998

- 37 - Revision A3

W741C260

RES

Continued

PAD NO. PAD NAME X Y PAD NO. PAD NAME X Y

21 SEG13 -845.00 -1468.00 46 XIN2 1227.00 82.00
22 SEG14 -715.00 -1468.00 47 VDD 1227.00 212.00
23 SEG15 -585.00 -1468.00 48 XOUT1 1227.00 342.00
24 SEG16 -455.00 -1468.00 49 XIN1 1227.00 472.00
25 SEG17 -325.00 -1468.00 50

26 SEG18 -195.00 -1468.00 51 MFP 1227.00 862.00
27 SEG19 -65.00 -1468.00 52 RA0 1227.00 992.00
28 SEG20 65.00 -1468.00 53 RA1 1227.00 1122.00
29 SEG21 195.00 -1468.00 54 RA2 1041.10 1453.20
30 SEG22 325.00 -1468.00 55 RA3 911.10 1453.20
31 SEG23 455.00 -1468.00 56 RB0 781.10 1453.20
32 SEG24 585.00 -1468.00 57 RB1 651.10 1453.20
33 SEG25 715.00 -1468.00 58 RB2 521.10 1453.20
34 SEG26 845.00 -1468.00 59 RB3 391.10 1453.20
35 SEG27 975.00 -1468.00 60 RC0 261.10 1453.20
36 SEG28 1227.00 -1218.00 61 RC1 131.10 1453.20
37 SEG29 1227.00 -1088.00 62 RC2 1.10 1453.20
38 SEG30 1227.00 -958.00 63 RC3 -128.90 1453.20
39 SEG31 1227.00 -828.00 64 RD0 -258.90 1453.20
40 VDD3 1227.00 -698.00 65 RD1 -388.90 1453.20
41 VDD2 1227.00 -568.00 66 RD2 -518.90 1453.20

1227.00 602.00

42 VDD1 1227.00 -438.00 67 RD3 -648.90 1453.20
43 DH2 1227.00 -308.00 68 RE0 -778.90 1453.20
44 DH1 1227.00 -178.00 69 RE1 -908.90 1453.20
45 XOUT2 1227.00 -48.00

- 38 -

TYPICAL APPLICATION CIRCUIT

Output Signal

RA0

RA3
RB0

RB1
RB2
RB3

RC0
RC1

RC2
RC3

RD0
RD1
RD2
RD3

Vcc

V

DD

COM0

COM3
SEG0

SEG31

DH1
DH2

V

DD1

V

DD2

V

DD3

W741C260

LCD

PANEL

(1/3 Bias
1/4 Duty)

0.1 uF

Connect to capacitor and VDD

to generate LCD voltage

Vcc

0.1 uF

32.768
KHz

RES

XOUT

XIN
OSCOUT

OSCIN

RE0
RE1

Vcc

RE2
RE3

MFP

470

V

SS

Ω

0.1 uF

Publication Release Date: March 1998

- 39 - Revision A3

INSTRUCTION SET TABLE

Symbol Description

ACC: Accumulator
ACC.n: Accumulator bit n
WR: Working Register
PAGE: Page Register
MR0: Mode Register 0
MR1: Mode Register 1
PM0: Port Mode 0
PM1: Port Mode 1
PM2: Port Mode 2
PSR0: Port Status Register 0
R: Memory (RAM) of address R
LCDR: LCD data RAM of address LDR
R.n: Memory bit n of address R
I: Constant parameter
L: Branch or jump address

W741C260

CF: Carry Flag
ZF: Zero Flag

PC: Program Counter
TM0: Timer 0
TM1: Timer 1
IEF.n: Interrupt Enable Flag n
HCF.n: HOLD mode release Condition Flag n
HEF.n: HOLD mode release Enable Flag n
PEF.n: Port Enable Flag n
EVFn: Event Flag n

! =: Not equal
&: AND
^: OR

- 40 -

Symbol Description, continued

EX: Exclusive OR
←:

[PAGE*10H+()]: Contents of address PAGE(bit2, bit1, bit0)*10H+()
[P()]: Contents of port P()

Transfer direction, result

Instruction Set Table 1

W741C260

MNEMONIC

Arithmetic

ADD R, ACC
ADD WR, #I
ADDR R, ACC
ADDR WR, #I
ADC R, ACC
ADC WR, #I
ADCR R, ACC
ADCR WR, #I
ADU R, ACC
ADU WR, #I
ADUR R, ACC
ADUR WR, #I
SUB R, ACC
SUB WR, #I
SUBR R, ACC
SUBR WR, #I
SBC R, ACC
SBC WR, #I
SBCR R, ACC
SBCR WR, #I
INC R
DEC R

FUNCTION

ACC←(R) + (ACC)
ACC←(WR) + I
ACC, R←(R) + (ACC)
ACC, WR←(WR) + I
ACC←(R) + (ACC) + (CF)
ACC←(WR) + I + (CF)
ACC, R←(R) + (ACC) + (CF)
ACC, WR←(WR) + I + (CF)
ACC←(R) + (ACC)
ACC←(WR) + I
ACC, R←(R) + (ACC)
ACC, W R←(WR) + I
ACC←(R) - (ACC)
ACC←(WR) - I
ACC, R←(R) - (ACC)
ACC, WR←(WR) - I
ACC←(R) - (ACC) - (CF)
ACC←(WR) - I - (CF)
ACC, R←(R) - (ACC) - (CF)
ACC, WR←(WR) - I - (CF)
ACC, R←(R) + 1
ACC, R←(R) - 1

FLAG

AFFECTED

ZF, CF 1
ZF, CF 1
ZF, CF 1
ZF, CF 1
ZF, CF 1
ZF, CF 1
ZF, CF 1
ZF, CF 1

ZF 1
ZF 1
ZF 1

ZF 1
ZF, CF 1
ZF, CF 1
ZF, CF 1
ZF, CF 1
ZF, CF 1
ZF, CF 1
ZF, CF 1
ZF, CF 1
ZF, CF 1
ZF, CF 1

CYCLE

Publication Release Date: March 1998

- 41 - Revision A3

Instruction Set Table 1, continued

W741C260

MNEMONIC FUNCTION FLAG

AFFECTED

Logic Operations

ANL R, ACC
ANL WR, #I
ANLR R, ACC
ANLR WR, #I
ORL R, ACC
ORL WR, #I
ORLR R, ACC
ORLR WR, #I
XRL R, ACC
XRL WR, #I
XRLR R, ACC
XRLR WR, #I

Branch

JMP L
JB0 L
JB1 L
JB2 L
JB3 L
JZ L
JNZ L
JC L
JNC L
DSKZ R
DSKNZ R
SKB0 R Skip if R.0 = "1" 1
SKB1 R Skip if R.1 = "1" 1
SKB2 R Skip if R.2 = "1" 1
SKB3 R Skip if R.3 = "1" 1

ACC←(R) & (ACC)
ACC←(WR) & I
ACC, R←(R) & (ACC)
ACC, WR←(WR) & I
ACC←(R) ∧ (ACC)
ACC←(WR) ∧ I
ACC, R←(R) ∧ (ACC)
ACC, WR←(WR) ∧ I
ACC←(R) EX (ACC)
ACC←(WR) EX I
ACC, R←(R) EX (ACC)
ACC, WR←(WR) EX I

PC10−PC0←L10−L0
PC10−PC0←L10−L0; if ACC.0 = "1"
PC10−PC0←L10−L0; if ACC.1 = "1"
PC10−PC0←L10−L0; if ACC.2 = "1"
PC10−PC0←L10−L0; if ACC.3 = "1"
PC10−PC0←L10−L0; if ACC = 0
PC10−PC0←L10−L0; if ACC ! = 0
PC10−PC0←L10−L0; if CF = "1"
PC10−PC0←L10−L0; if CF ! = "1"
ACC, R←(R) - 1; skip if ACC = 0
ACC, R←(R) - 1; skip if ACC ! = 0

ZF 1
ZF 1
ZF 1
ZF 1
ZF 1
ZF 1
ZF 1
ZF 1
ZF 1
ZF 1
ZF 1
ZF 1

ZF, CF 1
ZF, CF 1

CYCLE

1
1
1
1
1
1
1
1
1

- 42 -

Instruction Set Table 1, continued

W741C260

MNEMONIC FUNCTION FLAG

Data Move

MOV WR, R
MOV R, WR
MOVA WR, R
MOVA R, WR
MOV R, ACC
MOV ACC, R
MOV R, #I
MOV WR, @R
MOV @R, WR
MOV TABH, R
MOV TABL, R
MOVC R
MOVC WR, #I

Input & Output

WR←(R)
R←(WR)
ACC, WR←(R)
ACC, R←(WR)
R←(ACC)
ACC←(R)
R←I
WR←[PR (bit2, bit1, bit0) × 10H + (R)]
[PR (bit2, bit1, bit0) × 10H +(R)]←WR
TAB High addresss ← R
TAB Low addresss ← R
R←[ TAB × 10H + (ACC)]
WR ← [(I6 ~ I0) × 10H + (ACC)]

CYCLE

AFFECTED

1

1
ZF 1
ZF 1

1
ZF 1

1

2

2

1

1

2

2

MOVA R, RA
MOVA R, RB
MOVA R, RC
MOVA R, RD
MOV RA, R
MOV RB, R
MOV RE, R
MOV MFP, #I

Flag & Register

MOVA R, PAGE
MOV PAGE, R
MOV PAGE, #I
MOV MR0, #I
MOV MR1, #I

ACC, R←[RA]
ACC, R←[RB]
ACC, R←[RC]
ACC, R←[RD]
[RA]←(R)
[RB]←(R)
[RE]←(R)
[MFP]← I

ACC, R←PAGE (Page Register)
PAGE←(R)
PAGE←I
MR0←I
MR1←I

- 43 - Revision A3

ZF 1
ZF 1
ZF 1
ZF 1

1

1

1

1

ZF 1

1

1

1

1

Publication Release Date: March 1998

Instruction Set Table 1, continued

W741C260

MNEMONIC FUNCTION FLAG

AFFECTED

MOVA R, CF
MOV CF, R
MOVA R, HCFL
MOVA R, HCFH
CLR PMF, #I Clear Parameter Flag if In = 1 1
SET PMF, #I Set Parameter Flag if In = 1 1
MOV PM0, #I
MOV PM1, #I
MOV PM2, #I
CLR EVF, #I Clear Event Flag if In = 1 1
MOV PEF, #I Set/Reset Port Enable Flag 1
MOV IEF, #I Set/Reset Interrupt Enable Flag 1
MOV HEF, #I Set/Reset HOLD mode release Enable Flag 1
MOV SEF, #I Set/Reset STOP mode wake-up Enable Flag

MOV SCR, #I Set/Reset System clock Control Resgister 1

ACC.0, R.0←CF
CF←(R.0)
ACC, R←HCF0−HCF3
ACC, R←HCF4−HCF7

Port Mode 0← I
Port Mode 1← I
Port Mode 2← I

for RC port

ZF 1
CF 1
ZF 1
ZF 1

CYCLE

1
1
1

1

MOVA R, PSR0
CLR PSR0 Clear Port Status Register 0 1
SET CF Set Carry Flag CF 1
CLR CF Clear Carry Flag CF 1
CLR DIVR0 Clear the last 4-bit of the Divider 1
CLR WDT Clear WatchDog Timer 1

Shift & Rotate

SHRC R

RRC R

SHLC R

RLC R

ACC, R←Port Status Register 0

ACC.n, R.n←(R.n+1);
ACC.3, R.3←0; CF←R.0

ACC.n, R.n←(R.n+1);
ACC.3, R.3←CF; CF←R.0

ACC.n, R.n←(R.n-1);
ACC.0, R.0←0; CF←R.3

ACC.n, R.n←(R.n-1);
ACC.0, R.0←CF; CF←R.3

- 44 -

ZF 1

ZF, CF 1

ZF, CF 1

ZF, CF 1

ZF, CF 1

Instruction Set Table 1, continued

W741C260

MNEMONIC FUNCTION FLAG

AFFECTED

LCD

MOV LCDR, #I
MOV WR, LCDR
MOV LCDR, WR
MOV LCDR, ACC
MOV LCDM, #I Select LCD output mode type 1
LCDON LCD ON 1
LCDOFF LCD OFF 1

Timer

MOV TM0H, R
MOV TM0L, R
MOV TM0, #I Timer 0 set 1
MOV TM1H, R
MOV TM1L, R
MOV TM1, #I Timer 1 set 1

LCDR← I
WR←(LCDR)
LCDR←(WR)
LCDR←(ACC)

Timer 0 High register ← R
Timer 0 Low register ← R

Timer 1 High register ← R
Timer 1 Low register ← R

CYCLE

1
1
1
1

1
1

1
1

Subroutine

CALL L

RTN

Other

HOLD Enter Hold mode 1
STOP Enter Stop mode 1
NOP No Operation 1
EN INT Enable Interrupt Function 1
DIS INT Disable Interrupt Function 1

STACK ← (PC)+1;
PC10−PC0 ← L10−L0

(PC)←STACK

Publication Release Date: March 1998

- 45 - Revision A3

1

1

Instruction Set Table 2

ADC R, ACC Add R to ACC with CF

W741C260

Machine Code:

Machine Cycle:

Operation:

Description:

Flag Affected:

0

0 0 0 1 0 0 0 0

1

ACC ← (R) + (ACC) + (CF)

The contents of the data memory location addressed by R6 to R0, ACC,
and CF are binary added and the result is loaded into the ACC.

CF & ZF

ADC WR, #I Add immediate data to WR with CF

Machine Code:

Machine Cycle:

Operation:

Description:

0 0 0 0 1 1 0 0 I3 I2 I1 I0 W3 W2 W1 W0

1

ACC ← (WR) + I + (CF)

The contents of the Working Register (WR), I and CF are binary added and
the result is loaded into the ACC.

R6

R5 R4 R3 R2 R1 R0

Flag Affected:

CF & ZF

ADCR R, ACC Add R to ACC with CF

Machine Code:

Machine Cycle:

Operation:
Description:

0

0 0 0 1 0 0 1 0 R6 R5 R4 R3 R2 R1 R0

1

ACC, R ← (R) + (ACC) + (CF)
The contents of the data memory location addressed by R6 to R0, ACC,

and CF are binary added and the result is placed in the ACC and the data
memory.

Flag Affected:

CF & ZF

- 46 -

Instruction Set Table 2, continued

ADCR WR, #I Add immediate data to WR with CF

W741C260

Machine Code:

Machine Cycle:

Operation:

Description:

0 0 0 0 1 1 0 1 I3 I2 I1 I0 W3 W2 W1 W0

1

ACC, WR ← (WR) + I + (CF)

The contents of the Working Register (WR), I, CF are binary added and the
result is placed in the ACC and the WR.

Flag Affected:

CF & ZF

ADD R, ACC Add R to ACC

Machine Code:

Machine Cycle:

Operation:

Description:

0

0 0 1 1 0

1

ACC ← (R) + (ACC)

The contents of the data memory location addressed by R6 to R0 and ACC
are binary added and the result is loaded into the ACC.

0

0 0 R6 R5 R4 R3 R2 R1 R0

Flag Affected:

CF & ZF

ADD WR, #I Add immediate data to WR

Machine Code:

Machine Cycle:

Operation:

Description:

0 0 0 1 1 1 0 0 I3 I2 I1 I0 W3 W2 W1 W0

1

ACC ← (WR) + I

The contents of the Working Register (WR) and the immediate data I are
binary added and the result is loaded into the ACC.

Flag Affected:

CF & ZF

- 47 - Revision A3

Publication Release Date: March 1998

Instruction Set Table 2, continued

ADDR R, ACC Add R to ACC

W741C260

Machine Code:

Machine Cycle:

Operation:

Description:

0

0 0 1 1 0 0 1 0 R6 R5 R4 R3 R2 R1 R0

1

ACC, R ← (R) + (ACC)

The contents of the data memory location addressed by R6 to R0 and ACC
are binary added and the result is placed in the ACC and the data memory.

Flag Affected:

CF & ZF

ADDR WR, #I Add immediate data to WR

Machine Code:

Machine Cycle:

Operation:

Description:

0 0 0 1 1 1 0 1 I3 I2 I1 I0

1

ACC, WR ← (WR) + I

The contents of the Working Register (WR) and the immediate data I are
binary added and the result is placed in the ACC and the WR.

W2 W1 W0

W3

Flag Affected:

CF & ZF

ADU R, ACC Add R to ACC with Carry Flag unchanged

Machine Code:

Machine Cycle:

Operation:

Description:

0 0 1 0 1 0 0 0 0 R6 R5 R4 R3 R2 R1 R0

1

ACC ← (R) + (ACC)

The contents of the data memory location addressed by R6 to R0 and ACC
are binary added and the result is loaded into the ACC.

Flag Affected:

ZF

- 48 -

Instruction Set Table 2, continued

ADU WR, #I Add immediate data to WR with Carry Flag unchanged

W741C260

Machine Code:

Machine Cycle:

Operation:

Description:

0 0 1 0 1 1 0 0 I3 I2 I1 I0 W3 W2 W1 W0

1

ACC ← (WR) + I

The contents of the Working Register (WR) and the immediate data I are
binary added and the result is loaded into the ACC.

Flag Affected:

ZF

ADUR R, ACC Add R to ACC with Carry Flag unchanged

Machine Code:

Machine Cycle:

Operation:

Description:

0 0 1 0 1 0 0 1 0 R6 R5 R4 R3 R2 R1 R0

1

ACC, R ← (R) + (ACC)

The contents of the data memory location addressed by R6 to R0 and ACC
are binary added and the result is placed in the ACC and the data memory.

Flag Affected:

ZF

ADUR WR, #I Add immediate data to WR with Carry Flag unchanged

Machine Code:

Machine Cycle:

Operation:

Description:

0 0 1 0 1 1 0 1 I3 I2 I1 I0 W3 W2 W1 W0

1

ACC, WR ← (WR) + I

The contents of the Working Register (WR) and the immediate data I are
binary added and the result is placed in the WR and the ACC.

Flag Affected:

ZF

Publication Release Date: March 1998

- 49 - Revision A3

Instruction Set Table 2, continued

ANL R, ACC And R to ACC

W741C260

Machine Code:

Machine Cycle:

Operation:

Description:

0 0 1 0 1 0 1 0 0 R6 R5 R4 R3 R2 R1 R0

1

ACC ← (R) & (ACC)

The contents of the data memory location addressed by R6 to R0 and the
ACC are ANDed and the result is loaded into the ACC.

Flag Affected:

ZF

ANL WR, #I And immediate data to WR

Machine Code:

Machine Cycle:

Operation:

Description:

0 0 1 0 1 1 1 0 I3 I2 I1 I0 W3 W2 W1 W0

1

ACC ← (WR) & I

The contents of the Working Register (WR) and the immediate data I are
ANDed and the result is loaded into the ACC.

Flag Affected:

ZF

ANLR R, ACC And R to ACC

Machine Code:

Machine Cycle:

Operation:

Description:

0 0 1 0 1 0 1 1 0 R6 R5 R4 R3 R2 R1 R0

1

ACC, R ← (R) & (ACC)

The contents of the data memory location addressed by R6 to R0 and the
ACC are ANDed and the result is placed in the data memory and the ACC.

Flag Affected:

ZF

- 50 -

Instruction Set Table 2, continued

ANLR WR, #I And immediate data to WR

W741C260

Machine Code:

Machine Cycle:

Operation:

Description:

0 0 1 0 1 1 1 1 I3 I2 I1 I0 W3 W2 W1 W0

1

ACC, WR ← (WR) & I

The contents of the Working Register (WR) and the immediate data I are
ANDed and the result is placed in the WR and the ACC.

Flag Affected:

ZF

CALL L Call subroutine

Machine Code:

Machine Cycle:

Operation:

0 1 1 0 0 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0

1

STACK ← (PC)+1;
PC10−PC0 ← L10−L0

Description:

The next program counter (PC10 to PC0) is saved in the STACK and then
the direct address (L10 to L0) is loaded into the program counter.

A subroutine is called.

CLR CF Clear CF

Machine Code:

Machine Cycle:

Operation:

Description:

Flag Affected:

0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0

1

Clear CF

Clear Carry Flag to 0.

CF

Publication Release Date: March 1998

- 51 - Revision A3

Instruction Set Table 2, continued

CLR DIVR0 Reset the last 4 bits of the DIVideR0

W741C260

Machine Code:

Machine Cycle:

Operation:

Description:

0 0 0 1 0 1 1 1 0 0 0 0 0 0 0 0

1

Reset the last 4 bits of the Divider0

When this instruction is executed, the last 4 bits of the Divider0 (14 bits)
are reset.

CLR EVF, #I Clear EVent Flag

Machine Code:

Machine Cycle:

Operation:

Description:

0 1 0 0 0 0 0 0 I7 I6 I5 I4 I3 I2 I1 I0

1

Clear event flag

The condition corresponding to the data specified by I7 to I0 is controlled.

I0 to I8 Mode after execution of instruction
I0 = 1 EVF0 caused by overflow from the Divider0 is reset.

I1 = 1
I2 = 1
I3 = 1

I4 = 1

I5, I6

I7 = 1

EVF1 caused by underflow from the Timer 0 is reset.

EVF2 caused by signal change on port RC is reset.
Reserved

EVF4 caused by overflow from the Divider1 is reset.

Reserved
EVF7 caused by underflow from the Timer 1 is reset.

- 52 -

Instruction Set Table 2, continued

CLR PMF, #I Clear ParaMeter Flag

W741C260

Machine Code:

Machine Cycle:

Operation:

Description:

0 0 0 1 0 1 1 0 1 0 0 0 I3 I2 I1 I0

1

Clear Parameter Flag

Description of each flag:
I0, I1, I2 : Reserved

I3 = 1 : The input clock of the watchdog timer is Fosc/1024.

CLR PSR0 Clear Port Status Register 0 (RC port signal change flag)

Machine Code:

Machine Cycle:

Operation:

Description:

0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0

1

Clear Port Status Register 0 (RC port signal change flag)

When this instruction is executed, the RC port signal change flag (PSR0) is
cleared.

CLR WDT Reset the last 4 bits of the WatchDog Timer

Machine Code:

Machine Cycle:

Operation:

Description:

0 0 0 1 0 1 1 1 1 0 0 0 0 0 0 0

1

Reset the last 4 bits of the watchdog timer

When this instruction is executed, the last 4 bits of the watchdog timer are
reset.

Publication Release Date: March 1998

- 53 - Revision A3

Instruction Set Table 2, continued

DEC R Decrement R contents

W741C260

Machine Code:

Machine Cycle:

Operation:

Description:

0 1 0 0 1 0 1 0 1 R6 R5 R4 R3 R2 R1 R0

1

ACC, R ← (R) - 1

Decrement the data memory contents and load result into the ACC and the
data memory.

Flag Affected:

CF & ZF

DIS INT Disable Interrupt function

Machine Code:

Machine Cycle:

Operation:

Description:

0 1 0 1 0 0 0 0 1 0 0 0 0 0 0 0

1

Disable interrupt function

Interrupt function is inhibited by executing this instruction.

DSKNZ R Decrement R contents then skip if ACC ! = 0

Machine Code:

Machine Cycle:

Operation:

0 1 0 0 1 0 0 0 1 R6 R5 R4 R3 R2 R1 R0

1

ACC, R ← (R) - 1;
PC ← (PC) + 2 if ACC ! = 0

Description:

Decrement the data memory contents and load result into the ACC and the
data memory. If ACC ! = 0, the program counter is incremented by 2 and
produces a skip.

Flag Affected:

CF & ZF

- 54 -

Instruction Set Table 2, continued

DSKZ R Decrement R contents then skip if ACC is zero

W741C260

Machine Code:

0 1 0 0 1 0 0 0 0 R6 R5 R4 R3 R2 R1 R0

Machine Cycle:

1

Operation:

ACC, R ← (R) - 1;
PC ← (PC) + 2 if ACC = 0

Description:

Decrement the data memory contents and load result into the ACC and the
data memory. If ACC = 0, the program counter is incremented by 2 and
produces a skip.

Flag Affected:

CF & ZF

EN INT Enable Interrupt function

Machine Code:

Machine Cycle:

Operation:

Description:

0 1 0 1 0 0 0 0 1 1 0 0 0 0 0 0

1

Enable interrupt function

This instruction enables the interrupt function.

HOLD Enter the HOLD mode

Machine Code:

Machine Cycle:

Operation:

Description:

0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0

1

Enter the HOLD mode

The following two conditions cause the HOLD mode to be released.
(1) An interrupt is accepted.
(2) The HOLD release condition specified by the HEF is met.
In HOLD mode, when an interrupt is accepted the HOLD mode will be

released and the interrupt service routine will be executed. After
completing the interrupt service routine by executing the RTN instruction,
the µC will enter HOLD mode again.

Publication Release Date: March 1998

- 55 - Revision A3

Instruction Set Table 2, continued

INC R Increment R contents

W741C260

Machine Code:

Machine Cycle:

Operation:

Description:

0 1 0 0 1 0 1 0 0 R6 R5 R4 R3 R2 R1

1

ACC, R ← (R) + 1

Increment the data memory contents and load the result into the ACC and
the data memory.

Flag Affected:

CF & ZF

JB0 L Jump when bit 0 of ACC is "1"

Machine Code:

Machine Cycle:

Operation:

Description:

1 0 0 0 0 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0

1

PC10−PC0 ← L10−L0; if ACC.0 = "1"

If bit 0 of the ACC is "1," PC10 to PC0 of the program counter are replaced
with the data specified by L10 to L0 and a jump occurs. If bit 0 of the ACC
is "0," the program counter (PC) is incremented.

R0

JB1 L Jump when bit 1 of ACC is "1"

Machine Code:

Machine Cycle:

Operation:

Description:

1 0 0 1 0 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0

1

PC10−PC0 ← L10−L0; if ACC.1 = "1"

If bit 1 of the ACC is "1," PC10 to PC0 of the program counter are replaced
with the data specified by L10 to L0 and a jump occurs. If bit 1 of the ACC
is "0," the program counter (PC) is incremented.

- 56 -

Instruction Set Table 2, continued

JB2 L Jump when bit 2 of ACC is "1"

W741C260

Machine Code:

Machine Cycle:

Operation:

Description:

1 0 1 0 0 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0

1

PC10−PC0 ← L10−L0; if ACC.2 = "1"

If bit 2 of the ACC is "1," PC10 to PC0 of the program counter are replaced
with the data specified by L10 to L0 and a jump occurs. If bit 2 of the ACC
is "0," the program counter (PC) is incremented.

JB3 L Jump when bit 3 of ACC is "1"

Machine Code:

Machine Cycle:

Operation:

Description:

1 0 1 1 0 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0

1

PC10−PC0 ← L10−L0; if ACC.3 = "1"

If bit 3 of the ACC is "1," PC10 to PC0 of the program counter are replaced
with the data specified by L10 to L0 and a jump occurs. If bit 3 of the ACC
is "0," the program counter (PC) is incremented.

JC L Jump when CF is "1"

Machine Code:

Machine Cycle:

Operation:

Description:

1 1 1 1 0 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0

1

PC10−PC0 ← L10−L0; if CF = "1"

If CF is "1," PC10 to PC0 of the program counter are replaced with the data
specified by L10 to L0 and a jump occurs. If the CF is "0," the program
counter (PC) is incremented.

Publication Release Date: March 1998

- 57 - Revision A3

Instruction Set Table 2, continued

JMP L Jump absolutely

W741C260

Machine Code:

Machine Cycle:

Operation:

Description:

0 1 1 1 0 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0

1

PC10−PC0 ← L10−L0

PC10 to PC0 of the program counter are replaced with the data specified
by L10 to L0 and an unconditional jump occurs.

JNC L Jump when CF is not "1"

Machine Code:

Machine Cycle:

Operation:

Description:

1 1 0 1 0 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0

1

PC10−PC0 ← L10−L0; if CF = "0"

If CF is "0," PC10 to PC0 of the program counter are replaced with the data
specified by L10 to L0 and a jump occurs. If CF is "1," the program counter
(PC) is incremented.

JNZ L Jump when ACC is not zero

Machine Code:

Machine Cycle:

Operation:

Description:

1 1 0 0 0 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0

1

PC10−PC0 ← L10−L0; if ACC ! = 0

If the ACC is not zero, PC10 to PC0 of the program counter are replaced
with the data specified by L10 to L0 and a jump occurs. If the ACC is zero,
the program counter (PC) is incremented.

- 58 -

Instruction Set Table 2, continued

JZ L Jump when ACC is zero

W741C260

Machine Code:

Machine Cycle:

Operation:

Description:

1 1 1 0 0 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0

1

PC10−PC0 ← L10−L0; if ACC = 0

If the ACC is zero, PC10 to PC0 of the program counter are replaced with
the data specified by L10 to L0 and a jump occurs. If the ACC is not zero,
the program counter (PC) is incremented.

LCDON LCD ON

Machine Code:

Machine Cycle:

Operation:

Description:

0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0

1

LCD ON

Turn on LCD display.

LCDOFF LCD OFF

Machine Code:

Machine Cycle:

Operation:

Description:

0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0

1

LCD OFF

Turn off LCD display.

Publication Release Date: March 1998

- 59 - Revision A3

Instruction Set Table 2, continued

MOV ACC, R Move R content to ACC

W741C260

Machine Code:

Machine Cycle:

Operation:

Description:

Flag Affected:

MOV CF, R Move R.0 content to CF

Machine Code:

Machine Cycle:

Operation:

0 1 0 0 1 1 1 0 1 R6 R5 R4 R3 R2 R1 R0

1

ACC ← (R)

The contents of the data memory location addressed by R6 to R0 are
loaded into the ACC.

ZF

0 1 0 1 1 0 0 0 0 R6 R5 R4 R3 R2 R1 R0

1

CF ← (R.0)

Description:

Flag Affected:

The bit 0 content of the data memory location addressed by R6 to R0 is
loaded into CF.

CF

- 60 -

Instruction Set Table 2, continued

MOV HEF, #I Set/Reset Hold mode release Enable Flag

W741C260

Machine Code:

Machine Cycle:

Operation:

Description:

0 1 0 0 0 0 0 1 I7 I6 I5 I4 I3 I2 I1 I0

1

Hold mode release enable flag control

I0 to I7

I0 = 1

I1 = 1

I2 = 1

I3 = 1

I4 = 1

I5 & I6

I7 = 1

Operation
HEF0 is set so that overflow from Divider0 will caused

the HOLD mode to be released.

HEF1 is set so that underflow from Timer 0 will caused

the HOLD mode to be released.

HEF2 is set so that signal change on port RC caused
the HOLD mode to be released.

Reserved
HEF4 is set so that overflow from Divider1 will caused

the HOLD mode to be released.
Reserved
HEF7 is set so that underflow from Timer 1 will caused

the HOLD mode to be released.

Publication Release Date: March 1998

- 61 - Revision A3

Instruction Set Table 2, continued

MOV IEF, #I Set/Reset Interrupt Enable Flag

W741C260

Machine Code:

Machine Cycle:

Operation:

Description:

0 1 0 1 0 0 0 1 I7 I6 I5 I4 I3 I2 I1 I0

1

Interrupt Enable flag Control

The interrupt enable flag corresponding to the data specified by I7−I0 is
controlled:

I0 to I5 Operation

I0 = 1

I1 = 1

I2 = 1

I3 = 1

I4 = 1

I5 & I6

I7 = 1

The IEF0 is set so that interrupt 0 (overflow from the
Divider0) is accepted.

The IEF1 is set so that interrupt 1 (underflow from the
Timer 0) is accepted.

The IEF2 is set so that interrupt 2 (signal change on port
RC) is accepted.

Reserved

The IEF4 is set so that interrupt 4 (overflow from the
Divider1) is accepted.

Reserved
The IEF7 is set so that interrupt 7 (underflow from the

Timer 1) is accepted.

MOV LCDM, #I Select LCD output Mode type

Machine Code:

Machine Cycle:

Operation:

Description:

0 0 0 0 0 0 1 1 I7 I6 I5 I4 I3 I2 I1 I0

1

Select LCD output mode type

When LCD output pins are set to DC output mode, user can select CMOS
or NMOS as output type.

I0−I7 = 0 => CMOS type; I0−I7 = 1 => NMOS type

- 62 -

Instruction Set Table 2, continued

MOV LCDR, ACC Move ACC content to LCDR

W741C260

Machine Code:

Machine Cycle:

Operation:

Description:

0 0 0 0 0 1 1 D4 D3 D2 D1 D0 0 0 0 0

1

LCDR ← (ACC)

The contents of the ACC are loaded to the LCD data RAM (LCDR) location
addressed by D4 to D0.

MOV LCDR, WR Load WR content to LCDR

Machine Code:

Machine Cycle:

Operation:

Description:

0 1 0 0 0 1 0 D4 D3 D2 D1 D0 W3 W2 W1 W0

1

LCDR ← (WR)

The contents of the WR are loaded to the LCD data RAM (LCDR) location
addressed by D4 to D0.

MOV LCDR, #I Load immediate data to LCDR

Machine Code:

Machine Cycle:

Operation:

Description:

0 0 0 0 0 1 0 D4 D3 D2 D1 D0 I3 I2 I1 I0

1

LCDR ← I

The immediate data I are loaded to the LCD data RAM (LCDR) location
addressed by D4 to D0.

- 63 - Revision A3

Publication Release Date: March 1998

Instruction Set Table 2, continued

MOV MFP, #I Modulation Frequency Pulse generator

W741C260

Machine Code:

Machine Cycle:

Operation:

Description:

0 0 0 1 0 0 1 I7 I6 I5 I4 I3 I2 I1 I0

0

1

[MFP] ← I

If the bit 2 of MR1 is "0," the waveform specified by I7 to I0 is delivered at
the MFP output pin (MFP). The relationship between the waveform and
immediate data I is as follows:

I5~I0 I0 = 1 I1 = 1 I2 = 1 I3 = 1 I4 = 1 I5 = 1
Signal

I7 I6 Signal
0
0
1
1

Fosc

256

0
1
0
1

Fosc

512

Low

High
Fosc/16
Fosc/8

Fosc
4096

Fosc

8192

Fosc

16384

Fosc

32768

- 64 -

Instruction Set Table 2, continued

MOV MR0, #I Load immediate data to Mode Register 0 (MR0)

W741C260

Machine Code:

Machine Cycle:

Operation:

Description:

0 0 0 1 0 0 1 1 1 0 0 0 I3 I2 I1 I0

1

MR0 ← I

The immediate data I are loaded to the MR0.
MR0 bits description:

= 0 The fundamental frequency of Timer 0 is Fosc/4

bit 0

= 1 The fundamental frequency of Timer 0 is Fosc/1024
Reserved

bit 1
bit 2

Reserved
= 0 Timer 0 stop down-counting

bit 3

= 1 Timer 0 start down-counting

MOV MR1, #I Load immediate data to Mode Register 1 (MR1)

Machine Code:

0 0 0 1 0 0 1 1 0 0 0 0 I3 I2 I1 I0

Machine Cycle:

Operation:

Description:

1

MR1 ← I

The immediate data I are loaded to the MR1.
MR1 bit description:

= 0 The internal fundamental frequency of Timer 1 is Fosc

bit0

= 1 The internal fundamental frequency of Timer 1 is Fosc/64
= 0 The fundamental frequency source of Timer 1 is

internal clock

bit1

= 1 The fundamental frequency source of Timer 1 is
external clock via RC.0 input pin

= 0 The specified waveform of the MFP generator is
delivered at the MFP output pin

bit2

= 1 The specified frequency of the Timer 1 is delivered at
the MFP output pin

= 0 Timer 1 stop down-counting

bit3

= 1 Timer 1 start down-counting

Publication Release Date: March 1998

- 65 - Revision A3

Instruction Set Table 2, continued

MOV PAGE, #I Load immediate data to Page Register

W741C260

Machine Code:

Machine Cycle:

Operation:

Description:

0 1 0 1 0 1 1 0 1 0 0 0 I3 I2 I1 I0

1

Page Register ← I

The immediate data I are loaded to the PR.
Bit 3 is reserved.
Bit 0, bit 1, and bit 2 indirect addressing mode preselect bits:

bit1

bit2

0
0
0
0
1
1
1
1

bit0

0

0

= Page 0 (00H to 0FH)

0

1

= Page 1 (10H to 1FH)

1

0

= Page 2 (20H to 2FH)

1

1

= Page 3 (30H to 3FH)

0

0

= Page 4 (40H to 4FH)

0

1

= Page 5 (50H to 5FH)

1

0

= Page 6 (60H to 6FH)

1

1

= Page 7 (70H to 7FH)

MOV PEF, #I Set/Reset Port Enable Flag

Machine Code:

Machine Cycle:

Operation:

Description:

0 1 0 0 0 0 1 1 0 0 0 0 I3 I2 I1 I0

1

Port enable flag control

The data specified by I can cause HOLD mode to be released or an
interrupt to occur. The signal change on port RC is specified.

I0 to I3
I0 = 1
I1 = 1
I2 = 1
I3 = 1

Signal change at port RC

RC0
RC1
RC2
RC3

- 66 -

Instruction Set Table 2, continued

MOV PM0, #I Set/Reset Port Mode 0 register

W741C260

Machine Code:

Machine Cycle:

Operation:

Description:

0 1 0 1 0 0 1 1 0 0 0 0 I2 I1 I0

1

Set/Reset Port mode 0 register

I0 = 0: RA port is CMOS type; I0 = 1: RA port is NMOS type.
I1 = 0: RB port is CMOS type; I1 = 1: RB port is NMOS type.
I2 = 0: RC port pull-high resistor is disabled;
I2 = 1: RC port pull-high resistor is enabled.
I3 = 0: RD port pull-high resistor is disabled;
I3 = 1: RD port pull-high resistor is enabled.

MOV PM1, #I RA port independent Input/Output control

Machine Code:

Machine Cycle:

0 1 0 1 0 1 1 1 0 0 0 0 I3 I2 I1 I0

1

I3

Operation:

Description:

Input/output control of 4 RA port pins is independent.

I0 = 0: RA.0 is output pin; I0 = 1: RA.0 is input pin.
I1 = 0: RA.1 is output pin; I1 = 1: RA.1 is input pin.
I2 = 0: RA.2 is output pin; I2 = 1: RA.2 is input pin.
I3 = 0: RA.3 is output pin; I3 = 1: RA.3 is input pin.
Default condition RA port is input mode (PM = 1111B).

Publication Release Date: March 1998

- 67 - Revision A3

Instruction set table 2, continued

MOV PM2, #I RB port independent Input/Output control

W741C260

Machine Code:

Machine Cycle:

Operation:

Description:

0 1 0 1 0 1 1 1 1 0 0 0 I3 I2 I1 I0

1

Input/output control of 4 RB port pins is independent.

I0 = 0: RB.0 is output pin; I0 = 1: RB.0 is input pin.
I1 = 0: RB.1 is output pin; I1 = 1: RB.1 is input pin.
I2 = 0: RB.2 is output pin; I2 = 1: RB.2 is input pin.
I3 = 0: RB.3 is output pin; I3 = 1: RB.3 is input pin.
Default condition RB port is input mode (PM2 = 1111B).

MOV R, ACC Move ACC contents to R

Machine Code:

Machine Cycle:

Operation:

0 1 0 1 1 0 0 1 1 R6 R5 R4 R3 R2 R1 R0

1

R ← (ACC)

Description:

The contents of the ACC are loaded to the data memory location
addressed by R6 to R0.

MOVA R, RA Input RA port data to ACC & R

Machine Code:

Machine Cycle:

Operation:

Description:

0 1 0 1 1 0 1 1 0 R6 R5 R4 R3 R2 R1 R0

1

ACC , R ← [RA]

The data on port RA are loaded into the data memory location addressed
by R6 to R0 and the ACC.

Flag Affected:

ZF

- 68 -

Instruction Set Table 2, continued

MOVA R, RB Input RB port data to ACC & R

W741C260

Machine Code:

Machine Cycle:

Operation:

Description:

Flag Affected:

0 1 0 1 1 0 1 1 1 R6 R5 R4 R3 R2 R1 R0

1

ACC , R ← [RB]

The data on port RB are loaded into the data memory location addressed
by R6 to R0 and the ACC.

ZF

MOVA R, RC Input RC port data to ACC & R

Machine Code:

Machine Cycle:

Operation:

Description:

0 1 0 0 1 0 1 1 0 R6 R5 R4 R3 R2 R1 R0

1

ACC , R ← [RC]

The input data on the input port RC are loaded into the data memory
location addressed by R6 to R0 and the ACC.

Flag Affected:

ZF

MOVA R, RD Input RD port data to ACC & R

Machine Code:

0 1 0 0 1 0 1 1 1 R6 R5 R4 R3 R2 R1 R0

Machine Cycle:

1

Operation:

ACC , R ← [RD]

Description:

The input data on the input port RD are loaded into the data memory
location addressed by R6 to R0 and the ACC.

Flag Affected:

ZF

- 69 - Revision A3

Publication Release Date: March 1998

Instruction Set Table 2, continued

MOV R, WR Move WR contents to R

W741C260

Machine Code:

1 1 1 1 1 W3 W2 W1 W0 R6 R5 R4 R3 R2 R1 R0

Machine Cycle:

1

Operation:

Description:

R ← (WR)

The contents of the WR are loaded to the data memory location addressed
by R6 to R0.

MOV R, #I Load immediate data to R

Machine Code:

1 0 1 1 1 I3 I2 I1 I0 R6 R5 R4 R3 R2 R1 R0

Machine Cycle:

1

Operation:

Description:

R ← I
The immediate data I are loaded to the data memory location addressed by

R6 to R0.

MOV RA, R Output R contents to RA port

Machine Code:

Machine Cycle:

Operation:

Description:

0 1 0 1 1 0 1 0 0 R6 R5 R4 R3 R2 R1 R0

1

[RA] ← (R)

The data in the data memory location addressed by R6 to R0 are output to
the port RA.

- 70 -

Instruction Set Table 2, continued

MOV RB, R Output R contents to RB port

W741C260

Machine Code:

Machine Cycle:

Operation:

Description:

0 1 0 1 1 0 1 0 1 R6 R5 R4 R3 R2 R1 R0

1

[RB] ← (R)

The contents of the data memory location addressed by R6 to R0 are
output to the port RB.

MOV RE, R Output R contents to port RE

Machine Code:

Machine Cycle:

Operation:

Description:

0 1 0 1 1 1 1 0 0 R6 R5 R4 R3 R2 R1 R0

1

[RE] ← (R)

The contents of the data memory location addressed by R6 to R0 are
output to port RE.

MOV SCR, #I System Clock Register control

Machine Code:

Machine Cycle:

Operation:

Description:

0 1 0 1 0 1 0 0 0 0 0 0 I3 I2 I1 I0

1
System clock control

If the operation mode is the dual clock operation selected by the option
codes, the system clock and oscillator can be arranged by controlling the
system clock register.

SCR bits decription:

Bit 0

Bit 1
Bit 2
Bit 3

= 0, Fosc = Fm
= 1, Fosc = Fs

= 0, main oscillator is enabled
= 1, main oscillator is disabled

Reserved
= 0, divider 1 is 14-stage

= 1, divider 1 is 13-stage

Publication Release Date: March 1998

- 71 - Revision A3

Instruction Set Table 2, continued

MOV SEF, #I Set/Reset STOP mode wake-up Enable Flag for port RC

W741C260

Machine Code:

Machine Cycle:

Operation:

Description:

0 1 0 1 0 0 1 0 0 0 0 0 I3 I2 I1 I0

1

Set/reset STOP mode wake-up enable flag for port RC

The data specified by I cause a wake-up from the STOP mode. The falling­edge signal on port RC can be specified independently.

I0 to I3

I0 = 1
I1 = 1
I2 = 1
I3 = 1

MOV TM0, #I Timer 0 set

Machine Code:

Machine Cycle:

0 0 0 1 0 0 0 0 I7 I6 I5 I4 I3 I2 I1 I0

1

Falling edge signal on port RC

RC0
RC1
RC2
RC3

Operation:

Description:

Timer 0 set

The data specified by I7 to I0 is loaded to the Timer 0 to start the timer.

MOV TM0L, R Move R contents to TM0L

Machine Code:

Machine Cycle:

Operation:

Description:

0 0 0 1 0 1 0 0 0 R6 R5 R4 R3 R2 R1 R0

1

TM0L ← (R)

The contents of the data memory location addressed by R6 to R0 are
loaded into the TM0L.

- 72 -

Instruction Set Table 2, continued

MOV TM0H, R Move R contents to TM0H

W741C260

Machine code:

Machine Cycle:

Operation:

Description:

0 0 0 1 0 1 0 0 1 R6 R5 R4 R3 R2 R1 R0

1

TM0H ← (R)

The contents of the data memory location addressed by R6 to R0 are
loaded into the TM0H.

MOV TM1, #I Timer 1 set

Machine Code:

Machine Cycle:

Operation:

Description:

0 0 0 1 0 0 0 1 I7 I6 I5 I4 I3 I2 I1 I0

1

Timer 1 set

The data specified by I7 to I0 is loaded to the Timer 1 to start the timer.

MOV TM1L, R Move R contents to TM1L

Machine Code:

Machine Cycle:

Operation:

Description:

0 0 0 1 0 1 0 1 0 R6 R5 R4 R3 R2 R1 R0

1

TM1L ← (R)

The contents of the data memory location addressed by R6 to R0 are
loaded into the TM1L.

Publication Release Date: March 1998

- 73 - Revision A3

Instruction Set Table 2, continued

MOV TM1H, R Move R contents to TM1H

W741C260

Machine code:

Machine Cycle:

Operation:

Description:

0 0 0 1 0 1 0 1 1 R6 R5 R4 R3 R2 R1 R0

1

TM1H ← (R)

The contents of the data memory location addressed by R6 to R0 are
loaded into the TM1H.

MOV TABL, R Move R contents to TABL

Machine Code:

Machine Cycle:

Operation:

Description:

1 0 0 1 1 0 0 0 0 R6 R5 R4 R3 R2 R1 R0

1

TABL ← (R)

The contents of the data memory location addressed by R6 to R0 are
loaded into the TABL.

MOV TABH, R Move R contents to TABH

Machine code:

Machine Cycle:

Operation:

Description:

1 0 0 1 1 0 0 0 1 R6 R5 R4 R3 R2 R1 R0

1

TABH ← (R)

The contents of the data memory location addressed by R6 to R0 are
loaded into the TABH.

- 74 -

Instruction Set Table 2, continued

MOV WR, LCDR Load LCDR contents to WR

W741C260

Machine Code:

Machine Cycle:

Operation:

Description:

0 1 0 0 0 1 1 D4 D3 D2 D1 D0 W3 W2 W1 W0

1

WR ← (LCDR)

The contents of the LCD data RAM location addressed by D4 to D0 are
loaded to the WR.

MOV WR, R Move R contents to WR

Machine Code:

Machine Cycle:

Operation:

Description:

1 1 1 0 1 W3 W2 W1 W0 R6 R5 R4 R3 R2 R1 R0

1

WR ← (R)

The contents of the data memory location addressed by R6 to R0 are
loaded to the WR.

MOV WR, @R Indirect load from R to WR

Machine Code:

Machine Cycle:

Operation:

Description:

1 1 0 0 1 W3 W2 W1 W0 R6 R5 R4 R3 R2 R1 R0

2

WR ← [PR (bit2, bit1, bit0) × 10H + (R)]

The data memory contents of address [PR (bit2, bit1, bit0) × 10H + (R)] are
loaded to the WR.

- 75 - Revision A3

Publication Release Date: March 1998

Instruction Set Table 2, continued

MOV @R, WR Indirect load from WR to R

W741C260

Machine Code:

Machine Cycle:

Operation:

Description:

1 1 0 1 1 W3 W2 W1 W0 R6 R5 R4 R3 R2 R1 R0

2

[PR (bit2, bit1, bit0) × 10H + (R)] ← WR

The contents of the WR are loaded to the data memory location addressed
by [PR (bit2, bit1, bit0) × 10H + (R)] .

MOV PAGE, R Move R contents to Page Register

Machine Code:

Machine Cycle:

Operation:

Description:

0 1 0 1 1 1 1 0 1 R6 R5 R4 R3 R2 R1 R0

1

PR ← (R)

The contents of the data memory location addressed by R6 to R0 are
loaded to the Page Register.

MOVA R, CF Move CF contents to ACC.0 & R.0

Machine Code:

Machine Cycle:

Operation:

Description:

0 1 0 1 1 0 0 1 0 R6 R5 R4 R3 R2 R1 R0

1

ACC.0, R.0 ← (CF)

The contents of CF is loaded to bit 0 of the data memory location
addressed by R6 to R0 and the ACC. The other bits of the data memory
and ACC are reset to "0."

Flag Affected:

ZF

- 76 -

Instruction Set Table 2, continued

W741C260

MOVA R, HCFH

Machine Code:

Machine Cycle:
Operation:

Description:

Flag Affected:

MOVA R, HCFL

Machine Code:

Move HCF4−7 to ACC & R

0 1 0 0 1 0 0 1 1 R6 R5 R4 R3 R2 R1 R0

1
ACC, R ← HCF4−7

The contents of HCF bit 4 to bit 7 (HCF4 to HCF7) are loaded to the data
memory location addressed by R6 to R0 and the ACC. The ACC contents
and the meaning of the bits after execution of this instruction are as
follows:

Bit 0

HCF4: "1" when the HOLD mode is released by overflow from Divider 1.

Bit 1

HCF5: "1" when the HOLD mode is released by underflow from Timer 1.

Bit 2

Reserved.
Reserved.

Bit 3

ZF

Move HCF0−3 to ACC & R

0 1 0 0 1 0 0 1 0 R6 R5 R4 R3 R2 R1 R0

Machine Cycle:

Operation:

Description:

Flag Affected:

1

ACC, R ← HCF0−3

The contents of HCF bit 0 to bit 3 (HCF0 to HCF3) are loaded to the data
memory location addressed by R6 to R0 and the ACC. The ACC contents
and the meaning of the bits after execution of this instruction are as
follows:

Bit 0

HCF0: "1" when the HOLD mode is released by
overflow from the Divider 0.

Bit 1

HCF1: "1" when the HOLD mode is released by
underflow from Timer 0.

Bit 2

HCF2: "1" when the HOLD mode is released by
a signal change on port RC.

Bit 3

Reserved

ZF

Publication Release Date: March 1998

- 77 - Revision A3

Instruction Set Table 2, continued

MOVA R, PAGE Move Page Register contents to ACC & R

W741C260

Machine Code:

Machine Cycle:

Operation:

Description:

0 1 0 1 1 1 1 1 1 R6 R5 R4 R3 R2 R1 R0

1

ACC , R ← (Page Register)

The contents of the Page Register (PR) are loaded to the data memory
location addressed by R6 to R0 and the ACC.

Flag Affected:

ZF

MOVA R, PSR0 Move Port Status Register 0 contents to ACC & R

Machine Code:

Machine Cycle:

Operation:

Description:

0 1 0 0 1 1 1 1 0 R6 R5 R4 R3 R2 R1 R0

1

ACC, R ← RC port signal change flag (PSR0)

The contents of the RC port signal change flag (PSR0) are loaded to the
data memory location addressed by R6 to R0 and the ACC. When the
signal changes on any pin of the RC port, the corresponding signal change
flag should be set to 1. Otherwise, it should be 0.

Flag Affected:

ZF

MOVA R, WR Move WR contents to ACC & R

Machine Code:

Machine Cycle:

Operation:

Description:

0 1 1 1 1 W3 W2 W1 W0 R6 R5 R4 R3 R2 R1 R0

1

ACC, R ← (WR)

The contents of the WR are loaded to the ACC and the data memory
location addressed by R6 to R0.

Flag Affected:

ZF

- 78 -

Instruction Set Table 2, continued

MOVA WR, R Move R contents to ACC & WR

W741C260

Machine Code:
Machine Cycle:

Operation:
Description:

0 1 1 0 1 W3 W2 W1 W0 R6 R5 R4 R3 R2 R1 R0

1
ACC, WR ← (R)

The contents of the data memory location addressed by R6 to R0 are
loaded to the WR and the ACC.

Flag Affected:

ZF

MOVC R Move look-up table ROM addressed by TABL and TABH to R

Machine code:

Machine Cycle:
Operation:

Description:

1 0 0 1 1 0 0 1 0 R6 R5 R4 R3 R2 R1 R0

2
WR ← [((TABH) × 100H + (TABL)) × 10H + ACC]
The contents of the look-up table ROM location addressed by TABH, TABL

and ACC are loaded to R.

MOVC WR, #I Move look-up table ROM addressed by #I and ACC to WR

Machine code:
Machine Cycle:

Operation:
Description:

1 0 1 0 1 W3 W2 W1 W0 I6 I5 I4 I3 I2 I1 I0

2
WR ← [(I6 ~ I0) × 10H + (ACC)]

The contents of the look-up table ROM location addressed by I6 to I0 and
the ACC are loaded to R.

NOP No Operation

Machine Code:

Machine Cycle:
Operation:

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

1
No Operation

Publication Release Date: March 1998

- 79 - Revision A3

Instruction Set Table 2, continued

ORL R, ACC OR R to ACC

W741C260

Machine Code:

Machine Cycle:

Operation:

Description:

0 0 1 1 1 0 1 0 0 R6 R5 R4 R3 R2 R1 R0

1

ACC ← (R) ∧ (ACC)

The contents of the data memory location addressed by R6 to R0 and the
ACC are ORed and the result is loaded into the ACC.

Flag Affected:

ZF

ORL WR , #I OR immediate data to WR

Machine Code:

Machine Cycle:
Operation:

Description:

0 0 1 1 1 1 1 0 I3 I2 I1 I0 W3 W2 W1 W0

1
ACC ← (WR) ∧ I

The contents of the Working Register (WR) and the immediate data I are
ORed and the result is loaded into the ACC.

Flag Affected:

ZF

ORLR R, ACC OR R to ACC

Machine Code:

Machine Cycle:

Operation:

Description:

0 0 1 1 1 0 1 1 0 R6 R5 R4 R3 R2 R1 R0

1

ACC, R ← (R) ∧ (ACC)

The contents of the data memory location addressed by R6 to R0 and the
ACC are ORed and the result is placed in the data memory and the ACC.

Flag Affected:

ZF

- 80 -

Instruction Set Table 2, continued

ORLR WR , #I OR immediate data to WR

W741C260

Machine Code:

Machine Cycle:

Operation:

Description:

0 0 1 1 1 1 1 1 I3 I2 I1 I0 W3 W2 W1 W0

1

ACC, WR ← (WR) ∧ I

The contents of the Working Register(WR) and the immediate data I are
ORed and the result is placed in the WR and the ACC.

Flag Affected:

ZF

RLC R Rotate Left R with CF

Machine Code:

Machine Cycle:

Operation:

Description:

0 1 0 0 1 1 0 0 1 R6 R5 R4 R3 R2 R1 R0

1

ACC.n, R.n ← R.n-1; ACC.0, R.0 ← CF; CF ← R.3

The contents of the ACC and the data memory location addressed by R6 to
R0 are rotated left one bit, bit 3 is rotated into CF, and CF rotated into bit 0
(LSB). The same contents are loaded into the ACC.

Flag Affected:

CF & ZF

RRC R Rotate Right R with CF

Machine Code:

Machine Cycle:

Operation:

Description:

0 1 0 0 1 1 0 1 1 R6 R5 R4 R3 R2 R1 R0

1

ACC.n, R.n ← R.n+1; ACC.3, R.3 ← CF; CF ← R.0
The contents of the ACC and the data memory location addressed by R6 to

R0 are rotated right one bit, bit 0 is rotated into CF, and CF is rotated into
bit 3 (MSB). The same contents are loaded into the ACC.

Flag Affected:

CF & ZF

Publication Release Date: March 1998

- 81 - Revision A3

Instruction Set Table 2, continued

RTN Return from subroutine

W741C260

Machine Code:

Machine Cycle:

Operation:

Description:

0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0

1

(PC) ← STACK

The program counter (PC10 to PC0) is restored from the stack. A return
from a subroutine occurs.

SBC R, ACC Subtract ACC from R with Borrow

Machine Code:

Machine Cycle:

Operation:

Description:

0

0 0 0 1 0 1 0 0 R6 R5 R4 R3 R2 R1 R0

1

ACC ← (R) - (ACC) - (CF)

The contents of the ACC and CF are binary subtracted from the contents of
the data memory location addressed by R6 to R0 and the result is loaded
into the ACC.

Flag Affected:

CF & ZF

SBC WR, #I Subtract immediate data from WR with Borrow

Machine Code:

Machine Cycle:

Operation:

Description:

0 0 0 0 1 1 1 0 I3 I2 I1 I0 W3 W2 W1 W0

1

ACC ← (WR) - I - (CF)

The immediate data I and CF are binary subtracted from the contents of
the WR and the result is loaded into the ACC.

Flag Affected:

CF & ZF

- 82 -

Instruction Set Table 2, continued

SBCR R, ACC Subtract ACC from R with Borrow

W741C260

Machine Code:

Machine Cycle:

Operation:

Description:

0

0 0 0 1 0 1 1 0

1

ACC, R ← (R) - (ACC) - (CF)

The contents of the ACC and CF are binary subtracted from the contents of

R6

R5 R4 R3 R2 R1 R0

the data memory location addressed by R6 to R0 and the result is placed in
the ACC and the data memory.

Flag Affected:

CF & ZF

SBCR WR, #I Subtract immediate data from WR with Borrow

Machine Code:

Machine Cycle:

Operation:

Description:

0 0 0 0 1 1 1 1 I3 I2 I1 I0 W3 W2 W1 W0

1

ACC, R ← (WR) - I - (CF)

The immediate data I and CF are binary subtracted from the contents of
the WR and the result is placed in the ACC and the WR.

Flag Affected:

CF & ZF

SET CF Set CF

Machine Code:

Machine Cycle:

Operation:

Description:

Flag Affected:

0 1 0 1 0 0 0 0 0 1 0 0 0 0 0 0

1

Set CF

Set Carry Flag to 1.

CF

Publication Release Date: March 1998

- 83 - Revision A3

Instruction Set Table 2, continued

SET PMF, #I Set ParaMeter Flag

W741C260

Machine Code:

Machine Cycle:

Operation:

Description:

0 0 0 1 0 1 1 0 0 0 0 0 I3 I2 I1 I0

1

Set Parameter Flag
Description of each flag:

I0, I1, I2 : Reserved

I3 = 1 : The input clock of the watchdog timer is Fosc/16384.

SHLC R SHift Left R with CF and LSB = 0

Machine Code:

Machine Cycle:

Operation:

Description:

0 1 0 0 1 1 0 0 0 R6 R5 R4 R3 R2 R1 R0

1

ACC.n, R.n ← R.n-1; ACC.0, R.0 ← 0; CF ← R.3

The contents of the ACC and the data memory location addressed by R6 to
R0 are shifted left one bit, but bit 3 is shifted into CF, and bit 0 (LSB) is
replaced with "0." The same contents are loaded into the ACC.

Flag Affected:

CF & ZF

SHRC R SHift Right R with CF and MSB = 0

Machine Code:

Machine Cycle:

Operation:

Description:

0 1 0 0 1 1 0 1 0 R6 R5 R4 R3 R2 R1 R0

1

ACC.n, R.n ← R.n+1; ACC.3, R.3 ← 0; CF ← R.0

The contents of the ACC and the data memory location addressed by R6 to
R0 are shifted right one bit, but bit 0 is shifted into CF, and bit 3 (MSB) is
replaced with "0." The same contents are loaded into the ACC.

Flag Affected:

CF & ZF

- 84 -

Instruction Set Table 2, continued

SKB0 R If bit 0 of R is equal to 1 then skip

W741C260

Machine Code:

Machine Cycle:

Operation:

Description:

1 0 0 0 1 0 0 0 0 R6 R5 R4 R3 R2 R1 R0

1

PC ← (PC) + 2; if R.0 = "1"

If bit 0 of R is equal to 1, the program counter is incremented by 2 and a
skip is produced. If bit 0 of R is not equal to 1, the program counter (PC) is
incremented.

SKB1 R If bit 1 of R is equal to 1 then skip

Machine Code:

Machine Cycle:

Operation:

Description:

1 0 0 0 1 0 0 0 1 R6 R5 R4 R3 R2 R1 R0

1

PC ← (PC) + 2; if R.1 = "1"

If bit 1 of R is equal to 1, the program counter is incremented by 2 and a
skip is produced. If bit 1 of R is not equal to 1, the program counter (PC) is
incremented.

SKB2 R If bit 2 of R is equal to 1 then skip

Machine Code:

Machine Cycle:

Operation:

Description:

1 0 0 0 1 0 1 0 0 R6 R5 R4 R3 R2 R1 R0

1

PC ← (PC) + 2; if R.2 = "1"

If bit 2 of R is equal to 1, the program counter is incremented by 2 and a
skip is produced. If bit 2 of R is not equal to 1. The program counter (PC) is
incremented.

- 85 - Revision A3

Publication Release Date: March 1998

Instruction Set Table 2, continued

SKB3 R If bit 3 of R is equal to 1 then skip

W741C260

Machine Code:

Machine Cycle:

Operation:

Description:

1 0 0 0 1 0 1 0 1 R6 R5 R4 R3 R2 R1 R0

1

PC ← (PC) + 2; if R.3 = "1"

If bit 3 of R is equal to 1, the program counter is incremented by 2 and a
skip is produced. If bit 3 of R is not equal to 1, the program counter (PC) is
incremented.

STOP Enter the STOP mode

Machine Code:

Machine Cycle:

Operation:

Description:

0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0

1

STOP oscillator

Device enters STOP mode. When the falling edge signal of RC port is
accepted, the µC will wake up and execute the next instruction.

SUB R, ACC Subtract ACC from R

Machine Code:

Machine Cycle:

Operation:

Description:

Flag Affected:

0

0 0 1 1 0 1 0 0 R6 R5 R4 R3 R2 R1 R0

1

ACC ← (R) - (ACC)

The contents of the ACC are binary subtracted from the contents of the
data memory location addressed by R6 to R0 and the result is loaded into
the ACC.

CF & ZF

- 86 -

Instruction Set Table 2, continued

SUB WR , #I Subtract immediate data from WR

W741C260

Machine Code:

Machine Cycle:

Operation:

Description:

0 0 0 1 1 1 1 0 I3 I2 I1 I0 W3 W2 W1 W0

1

ACC ← (WR) - I

The immediate data I are binary subtracted from the contents of the WR
and the result is loaded into the ACC.

Flag Affected:

CF & ZF

SUBR R, ACC Subtract ACC from R

Machine Code:

Machine Cycle:

Operation:

Description:

0 0 1 1 0 1 1 0 R6 R5 R4 R3 R2 R1 R0

0

1

ACC, R ← (R) - (ACC)

The contents of the ACC are binary subtracted from the contents of the
data memory location addressed by R6 to R0 and the result is placed in the
ACC and the data memory.

Flag Affected:

CF & ZF

SUBR WR , #I Subtract immediate data from WR

Machine Code:

Machine Cycle:

Operation:

Description:

0 0 0 1 1 1 1 1 I3 I2 I1 I0 W3 W2 W1 W0

1

ACC, WR ← (WR) - I

The immediate data I are binary subtracted from the contents of the WR
and the result is placed in the ACC and the WR.

Flag Affected:

CF & ZF

- 87 - Revision A3

Publication Release Date: March 1998

Instruction Set Table 2, continued

XRL R, ACC Exclusive OR R to ACC

W741C260

Machine Code:

Machine Cycle:

Operation:

Description:

0 0 1 1 1 0 0 0 0 R6 R5 R4 R3 R2 R1 R0

1

ACC ← (R) EX (ACC)

The contents of the data memory location addressed by R6 to R0 and the
ACC are exclusive-ORed and the result is loaded into the ACC.

Flag Affected:

ZF

XRL WR, #I Exclusive OR immediate data to WR

Machine Code:

Machine Cycle:

Operation:

Description:

0 0 1 1 1 1 0 0 I3 I2 I1 I0 W3 W2 W1 W0

1

ACC ← (WR) EX I

The contents of the Working Register (WR) and the immediate data I are
exclusive-ORed and the result is loaded into the ACC.

Flag Affected:

ZF

XRLR R, ACC Exclusive OR R to ACC

Machine Code:

Machine Cycle:

Operation:

Description:

0 0 1 1 1 0 0 1 0 R6 R5 R4 R3 R2 R1 R0

1

ACC, R ← (R) EX (ACC)

The contents of the data memory location addressed by R6 to R0 and the
ACC are exclusive-ORed and the result is placed in the data memory and
the ACC.

Flag Affected:

ZF

- 88 -

Instruction Set Table 2, continued

XRLR WR, #I Exclusive OR immediate data to WR

W741C260

Machine Code:

Machine Cycle:

Operation:

Description:

Flag Affected:

0 0 1 1 1 1 0 1 I3 I2 I1 I0 W3 W2 W1 W0

1

ACC, WR ← (WR) EX I

The contents of the Working Register(WR) and the immediate data I are
exclusive-ORed and the result is placed in the WR and the ACC.

ZF

Publication Release Date: March 1998

- 89 - Revision A3

PACKAGE DIMENSION

80-Lead QFP

W741C260

D

H

80

D

65

1

24

Seating Plane

See Detail F

Symbol

A

1

A

2

A

b
c

D
E
e

D

H

E

H
L

1

L
y

θ

64

41

e

Dimension in Inches Dimension in mm

Min.

0.004

0.107

0.012

0.004

0.546

0.782

0.025 0.037

0.728

0.964

0.039

0.087 0.103

4025

b

A

y

Max.

Nom.

0.112

0.014

0.006 0.15

0.551

0.787

0.031

0.740

0.976

0.047

0.094

Min.

0.130

0.10

2.73

0.117

0.30

0.018

0.10

0.010

13.87

0.556

19.87

0.792

0.65

0.752

18.49

0.988

24.49 24.80 25.10

1.00

0.055

2.21 2.62

0.004
0120

E H

E

c

2

AA

1

Max.Nom.

3.30

2.97

2.85

0.45

0.35

0.25

14.00

14.13

20.00

20.13

0.80

0.95

19.10

18.80

1.40

1.20

2.40

0.10
12

θ

L

L

1

Detail F

- 90 -

Notes:

W741C260

Publication Release Date: March 1998

- 91 - Revision A3

W741C260

Headquarters

No. 4, Creation Rd. III,
Science-Based Industrial Park,
Hsinchu, Taiwan
TEL: [phone]
FAX: [phone]
http://www.winbond.com.tw/
Voice & Fax-on-demand: 886-2-27197006

Winbond Electronics (H.K.) Ltd.

Rm. 803, World Trade Square, Tower II,
123 Hoi Bun Rd., Kwun Tong,
Kowloon, Hong Kong
TEL: [phone]
FAX: [phone]

Taipei Office

11F, No. 115, Sec. 3, Min-Sheng East Rd.,
Taipei, Taiwan
TEL: [phone]
FAX: [phone]

Note: All data and specifications are subject to change without notice.

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Winbond Electronics North America Corp.
Winbond Memory Lab.
Winbond Microelectronics Corp.
Winbond Systems Lab.

2727 N. First Street, San Jose,
CA 95134, U.S.A.
TEL: [phone]
FAX: [phone]