Page 1
VT86C926
A
MAZON
PCI E
THERNET CONTROLLER
DATA SHEET
(Preliminary)
DATE : June 27, 1995
VIA TECHNOLOGIES, INC.
Page 2
P
RELIMINARY RELEASE
Please contact Via Technologies for the latest documentation.
Copyright Notice:
Copyright © 1995, Via Technologies Incorporated. Printed in Taiwan. A
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Technologies Incorporated.
The VT86C926 may only be used to identify products of Via Technologies.
All trademarks are the properties of their respective owners.
LL RIGHTS RESERVED
.
Disclaimer Notice:
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Via Technologies mak es no warranties, implied or otherwise, in regard to this document and to
the products described in this document. T he information provided by this docum ent is believed
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assumes no responsibility for any errors in this document. Furthermore, Via Technologies
assumes no respons ibility for the use or misuse of the inf ormation in this document and for any
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ECHNOLOGIES
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RELIMINARY
VT86C926
VT86C926 A
PCI E
THERNET CONTROLLER FEATURES
MAZON
* Single chip Ethernet controller for PCI bus interface
* Software compatible to NE2000+, NE2000
* Support 35ns access time SRAM
* Integrated 10BaseT TP interface
-- Built-in pre-equalization circuitry for transmitter
-- smart squelch circuit with programmable threshold for receiver
-- Selective Link integrity test and link disable
-- Selective polarity detection and correction
-- Automatic selection between TP and AUI interfaces
* Full IEEE 802.3 AUI interface
-- Meet 10Base5 and 10Base2 standards
-- Thin-net or Thick-net enable signal
* Jumper or Jumperless configuration
-- Jumperl2ess configuration with EEPROM
-- Jumper configuration with EEPROM storing Ethernet Address
* Direct drive to 4 status LED indicators: transmit, receive, collision, and Thin select
-- Transmit LED for packet transmitting status and power indicator
-- Receive LED for packet receiving status and Link status
-- Collision LED for collision status
-- Thin select LED for Thin 10Base-2 port select
* ISA NE2000 compatible mode, register compatible to National Semiconductor DP83905 & DP83906
* Optional Full duplex operation with speed up to 20Mbps
* Early receive interrupt allows parallel processing of data during receiving
* Early transmit correction ability allows parallel processing of data during transmission
* Support 16K, 32K Bootrom size
* Support PCI 32-bit data path transfaer with enhance 32-bit driver
* Software controllable power down feature
* Single +5V supply, 0.8um standard CMOS technology
* 100 pin PQFP package
EEPROM
AD[31:0]
PCICLK
PCIRST#
INTA#
CBE#[3:0]
IDSEL
FRAME#
IRDY#
TRDY#
DEVSEL#
STOP#
PAR
Buffer
RAM
Boot
ROM
Config.
MA0-14
MD0-7
_MSRD,
_MSWR,
EECS
PCI
Bus
Interface
Unit
M-Bus Arbitrator
Data Bus FIFO
for Remote DMA
Remote
DMA
Registers
&
State
Machine
PCI CFG
MA0 - MA14
MD0 - MD7
Rcv. Data
Local
DMA
Registers
&
State
Machine
&
Buffer
Mgmt.
Internal Bus
Xmt Data
Figure 1: Block Diagram
Configuration
Registers &
EEPROM Control
MAC Receiver
Protocol State
Machine &
Registers
MAC Xmitter
Protocol State
Machine &
Registers
Shadow Ethernet
Address PROM
Page 1 Registers
&
Tally Counters
TP MAU
PLL &
EnDec
Interface
LED &
Testing
AUI
RD+,RDTD+,TD-
RX+,RXTX+,TXCI+,CI-
THIN
_RXLED,
_TXLED,
_COLED
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IN DIAGRAM
P
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VT86C926
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IN DESCRIPTIONS
P
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VT86C926
No. Name Type Description
PCI Bus Interface
98-100, 1-
5, 8-13,
16-17,
26-33,
35-40,
43,44
95 PCICLK I PCICLK provides timing for all transactions on PCI and is an input pin
96 INTA# OD INTA# is an asynchronous signal which is used to request an interrupt
97 PCIRST# I When PCIRST# is asserted low, the VT86C926 chip performs an
6, 18, 25,
34
7 IDSEL I Used as a chip select during PCI configuration cycle.
19 FRAME# I Cycle Frame is driven by the current master to indicate the beginning
20 IRDY# I Initiator Ready indicates the initiating agent's ability to complete the
21 TRDY I/O Target Ready indicates the target's agent's ability to complete the current
22 DEVSEL# I/O Device Select, when actively driven, indicates the driving device has
23 STOP# I/O VT86C926 drives STOP# to disconnect further traction.
24 PAR T/S Parity is even parity across AD31-0 and CBE3-0B. PARis stable and
AD31-0 I/O Address/Data are multiplexed on the same PCI pins. A bus transaction
consists of an address phase followed by one or more data phases. The
address phase is the clock cycle in which FRAME# is asserted. Write
data is stable and valid when IRDYB is asserted and read data is stable
and valid when TRDYB is asserted.
to every PCI device.
internal system hardware reset. PCIRST# may be asynchronous to CLK
when asserted or deasserted. It is recommended that the deassertion be
synchronous to guarantee clean and bounce free edge.
CBE#[3:0] I Bus Command/Byte Enables are multiplexed on the same PCI pins.
During the address phase of a transaction, CBE3-0B define the Bus
Command. Buring the data phase, CBE3-0B are used as Byte Enables.
The Byte Enables define which physical byte lanes carry meaningful
data. CBE0B applies to byte 0 and CBE3B applies to byte 3.
and duration of an access. FRAME# is asserted to indicate a bus
transaction is beginning. While FRAME# is asserted, data transfers
continue. When FRAME# is deasserted, the transaction is in the final
data phase.
current data phase of the transaction. IRDY# is used in conjunction with
TRDY#. A data phase is completed on any clock when both IRDY# and
TRDY# are asserted. During a write, IRDY# indicates that valid data is
present on AD31-0. During a read, it indicates the master is prepared to
accept data. Wait cycles are inserted until both IRDY# and TRDY# are
asserted simultaneously.
data phase of the transaction. TRDY# is used in conjunction with
IRDY#. A data phase is completed on any clock when both IRDY# and
TRDY# are asserted. During a read, TRDY# indicates that valid data is
present on AD31-0. During a write, it indicates the target is prepared to
accept data. Wait cycles are inserted until both IRDY# and TRDY# are
asserted simultaneously.
decoded its address as the target of the current access. As an input,
DEVSEL# indicates whether any device on the bus has been selected.
valid one clock after the address phase. For data phaases PAR is stable
and valid one clock after either IRDY# is asserted on a write transaction
or TRDY# is asserted on a read transaction.
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Network Interface
85,86 TX+
83,84 RX+
81,82 CD+
91,92 TD+
89,90 RD+
80 THIN O
69 X1 I Crystal or external oscillator input.
68 X2 O Cystal feedback output. Used in crystal connections only. Should be left
78 TXLED# O
79 RXLED# O
77 COLED# O
76 TSTPIN I/O N.C.
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TX-
RX-
CD-
TD-
RD-
, INC.P
O
AUI Transmit Output:
Manchester-encode d data to the AUI DO c ircuitry through transfo rmer
coupler. Use a local terminator resistor 75 Ohm.
I
AUI Receive Input:
through a decoupled transformer.
I
AUI Collision Input:
transceiver. The SQE signal is 10MHz +/- 15% square wave.
O
Twister Pair Transmit Outputs:
sends pre-equalized TP data signal to TP network medium through a
filter and transformer. Use a local terminator resistor 100 Ohm.
I
Twisted Pair Receive Inputs:
medium through a decoupled transformer passes Manchester -encoded
data to the ENDEC module.
Thin-net selection:
converter of 10Base2 MAU module. It is asserted when PHYS1 and
PHYS0 in Configuration Register B selects 10Base2 mode.
completely unconnected when using oscillator module.
Transmit/Power LED:
indicates a transmission onto the TP is in progress. It turns o ff for 90ms
if a packet is transmitted. A minimum on time 18ms is maintained
between blinking of transmitting packets.
Receive/Link LED:
indicates a reception from the TP is in progress. It turns off 90ms if a
packet is received. If the Link Test is enabled it will turn off as long as
the link fails. After the link is up, it will turn on for at least 786ms and
then become a normal receiver indicator.
Collision/Jabber LED:
It turns on for minimum 25ms whenever VT86C926 detects a collision.
It is retriggerable. During jabber state it stays on.
Differential current mode driver which sends the
Differential receive input pair form the transceiver
Differential collision (SQE) signal input from
This output is used to control the power DC-DC
An open drain active low output. Normally on. It
An open drain active low output. Normally on. It
An open drain active low output. Normally off.
RELIMINARY
Different current mode driver which
This differential input pair from TP
VT86C926
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External Memory Support
75-72,
67-58,
55
52-45 MD0-MD7 I/O
57 MSRD# O
56 MSWR# O
54 BPCS# O
53 EECS O
Power Supply & Ground
14, 42, 93,71VDD, VDDIF,
15, 41, 94,70VSS, VSSIF,
88 VDDA P
87 VSSA G
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MA14
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Memory Support Address Bus:
drive the memory support address bus. These 15 address lines cover up
to 16K bytes memory space. When RESET is active these pins are used
for jumper setting. There are 100K pull-down device on pins.
Memory Support Data Bus:
used to access external memory. When RESET is active pin MD3 to
MD7 are used for jumper setting. There are 100K pull-down device on
pins. MD0 to MD2 are used for EEPROM programming interface.
Memory Support Bus Read:
VT86C926 controller via the memory support data bus.
The Chip Select of external buffer RAM is always enabled.
Note 1:
Memory Support Bus Write:
into the external RAM via the memory support data bus. A 100K pulldown device is connected.
Boot PROM Chip Select:
data bus. The ROM address bus is connected to SA bus directly.
EEPROM Chip Select:
when a EEPROM is used to provide the configuration data and
Ethernet Address. A 100K pull-up resistor is connected.
P
Positive 5V Supply:
pads, and TD, TX pads. Double bonding may be required.
G
Negative Supply:
separate core and I/O pads ground.
Analog 5V Supply:
pads. Seperate power plane may be required.
Negative Supply:
required.
Supply power to Internal digital logic, Digital I/O
digital ground. Multiple bonding pads are required to
Supply power to Analog circuit and RX, CI, RD
Analog ground. Sepearte ground plane may be
When RESET is inactive these pins can be
Select the Boot ROM on the memory support
Chip select signal for the external EEPROM
RELIMINARY
When RESET is inactive these pins
Strobes data from external RAM into
Strobes data from VT86C926 controller
VT86C926
(Note 1)
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F
UNCTIONAL DESCRIPTIONS
1. G
ENERAL DESCIPTION
The VT86C926 PCI Ethernet controller is CMOS VLSI designed for easy
implementation of CSMA/CD local area networks. Significant features
include: twisted-pair interface, PCI Plug&Play compatability and Early
Interrupt Receive/Transmit.
The VT86C926 integrates the entire bus interface of PCI systems. Setting hardware jumpers or software
configures the VT86C926 bus interface. The VT86C926 also complies with PCI specification v2.0. and is
software compatible to either the NE2000. The VT86C926 supports the 10BASE5 or 10BAE2 network
interfaces via an external transciever connected to its AUI port. The VT82C926's integrated 10BASE-T
transciever supports 10BASE-T and fully complies with IEEE 802.3i specifications.
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VT86C926
2. TP (T
The five main functions of the TP interface are: smart squelch, collision detection, link de tector/generator,
jabber and transmit driver.
2.1. Smart Squelch
The basic function of smart squelch is to distinguish between impulse noise and va lid signals on the RXI±
differential inputs. To determine the validity of data, the squelch function applies specific timing and
amplitute criteria to the incoming signals. Also, there are two squelch modes, selectable by the SQSEL pin.
The two selectable squelch modes are: 1) 10BASE-T compatible and 2) reduced squelch mode.
2.2. Collsion
The TP interface will detect a collision when the transmit and receive channels are active at the same time.
If the TPI module is receiving when a collision is detected it is reported to the controller immediately .
Approximately 1 us after the transmission of each packet, a signal called the Signal Quality Error (SQE) is
generated. The SQE consists typically of 10 cycles of 10 MHz and is also refered as the "Heartbeat."
2.3. Link Detector/Generator
The link generator is a timer circuit that generates a link pulse as defined by the 10 Base-T specification.
The link pulse will be generated by transmitter. The pulse is used to check the integrity of the connection to
the remote MAU. The link detection circuit checks for valid pulses from the remote MAU; if it receives no
valid pulse, then the transmitter will be disabled.
WISTED PAIR
NTERFACE
) I
2.4. Jabber
The jabber timer monitors the transmitter and disables the transmission
if the transmitter is active for longer than 26 ms.
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VT86C926
6. EEPROM I
NTERFACE AND PROGRAMMING
VT86C926 uses an 93C46 to store configuration data and Ethernet address.
.1. EEPROM Contents
6
D15 D0
3FH
.
.
.
.
.
.
10H
0FH
Reserved for 93C46
.
.
.
.
.
.
.
73H
Reserved for 93C46
.
.
.
.
.
.
.
Conf. C
0EH Conf. B Conf. A
.
Reserved
.
.
Reserved
.
08H 57H 42H
07H SUBVID1 SUBVID0
.
Reserved
.
.
Reserved
.
03H Checksum Board ID
02H Ethernet Address 5 Ethernet Address 4
01H Ethernet Address 3 Ethernet Address 2
00H Ethernet Address 1 Ethernet Address 0
The word on location 03H is optional to user's application requirement.
Note 1.
Programming 73H into the upper address is required to protect the Ethernet address from being destroyed accidentally.
Note 2.
6.2. Emulated PROM map for NE2000 16-bit mode (WTS=1)
D15 D0
1EH 00
1CH 00
.
00
.
57H
57H
(DWID=1)
(DWID=1)
or
42H
or
42H
.
Reserved
.
(DWID=0)
(DWID=0)
0EH 00 Checksum
0CH 00 Board ID
0AH 00 Ethernet Address 5
08H 00 Ethernet Address 4
06H 00 Ethernet Address 3
04H 00 Ethernet Address 2
02H 00 Ethernet Address 1
00H 00 Ethernet Address 0
The address shown above on the left side is the Remote DMA Address.
Note 1.
The jumper DWID will determine the contents of the upper bytes. The software uses the upper bytes to distinguish the data
Note 2.
width of the system bus interface to be used.
During the initialization of the software driver, the program should set WTS to 1 and try 8-bit I/O instruction to get the
Note 3.
PROM contents (since data width is unknown). Then the program should set the WTS bit of DCR to the value revealed on
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jumper DWID. Remember that as long as WTS is set to 1, the VT86C926 sends one word at one time with _IOCS16
asserted -- regardless of the data width of I/O instruction used.
Regardless of the data width of I/O instruction used, the VT86C926 sends one byte at one time with _IOCS16 deasserted
Note 4.
and WTS set to 0. This map is only for reference. Users should never need to access the PROM contents in this way.
6.3. Memory Map of VT86C926
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NE2000 16-bit mode (WTS=1)
D15 D0
0000H
00H PROM
001FH
0020H
Aliased PROM
3FFFH
4000H
16K X 8 Buffer RAM
7FFFH
8000H
Aliased 0000H - 7FFFH
FFFFH
VT86C926
0000H
001FH
0020H
3FFFH
4000H
5FFFH
6000H
7FFFH
8000H
FFFFH
NE2000 8-bit mode (WTS=0)
D7 D0
Interleaved PROM
Aliased PROM
8K X 8 Buffer RAM
Aliased Buffer RAM
Aliased 0000H-7FFFH
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6.4. PCI Configuration Space
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Device ID
( 0926 )
STATUS
(DEVS1, DEVS0 ) = ( 1 , 0 )
CLASS CODE
( 02_00_00 )
BIST
( 00 )
EXP ROM BASE [ 31: 15 ] ROM14 0000_0000_00000 EN 30 h
Reserved
Header type
( 00 )
IO SPACE 0
Reserved
Vendor ID
( 1106 )
Latency Timer
( 00 )
SUB Vendor ID
FR EEPROM contents
COMMAND
( MMSPACE, IOSOACE)
Revision ID
Reserved
Reserved
( 00 )
Cache Line
( 00 )
0001
00 h
04 h
08 h
0c h
10 h
2c h
Max_LAT
( 00 )
6.5. Direct Programming of EEPROM
The VT86C926 features a easy way to program external EEPROM in-situ. When the RESET is active and
if the upper byte of 0FH on EEPROM is not 73H, the EEPR bit will not be set to indicate that the current
EEPROM has not been programmed yet. This will allow the VT86C926 to enter Direct Programming
mode if EELOAD is also set. In this mode the user can directly control the EEPROM interface signals by
writing to the ECSR Port and the value on the EECS, ESK and EDI bits will be driven onto the EECS,
SK(MD2), and DI(MD1) outputs respectively. These outputs will be latched so the user can generate a
clock on SK by repetitively writing 1 then 0 to the appropriate bit. This can be used to generate the
EEPROM signals as per the 93C46 data sheet.
To read the EEPROM data, users have to generate EEPROM interface signals into EECS, DI and SK as
described above and in the mean time read the data from DO(MD0) input via pin SD0. Reading Data
Transfer Port during programming will not affect the latched data on EECS, SK, and DI outputs. When the
EEPROM has been programmed and verified (remember to program the upper byte of 0EH with 73H), the
user must give VT86C926 a power-on reset to return to normal operation and to read in the new data.
The Direct Programming mode is mainly used for production to program every bit of the EEPROM. Once
the upper byte of 0EH has been programmed with 073H and a power-on reset has been performed, there is
Min_GNT
( 00 )
INT PIN
( 01 )
INTLINE
3c h
INTL [7:0]
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no way to change the contents of EEPROM except Configuration Registers A, B, and C, which will be
discussed in the following paragraph. For more information, refer to EECSR.
6.6. Embedded Programming of EEPROM
If the upper byte of 0FH of EEPROM has been programmed to 073H when VT86C926 is loading the
EEPROM data during power-on reset, the EEPR bit of Signature Register will be set to prohibit the Direct
Programming mode. However, the user can still program the configuration registers A, B, and C using the
Embedded Programming mode by following the routine specified in the pseudo code below. This operation
will work regardless of the value of EECONFIG. The setting of the EELOAD bit of Configuration Register
B starts the EEPROM write process. Care should be taken not to accidentally modify the POL and GDLNK
bits because these two bits return the value indifferent from the setting. This programming process is ended
when the EELOAD bit goes to zero.
EEPROM_EMB_PROG ( )
{ // defined constant:
// declared register: value, config_for_A, config_for_B, config_for_C
// declared function: DISABLE_INTERRUPTS, ENABLE_INTERRUPTS, READ, WRITE, WAIT
DISABLE_INTERRUPTS ( );
value = READ (
value = value & !
value = value |
WRITE (
READ (
WRITE (
WRITE (
WRITE (
while (value ||
{
value = READ (
WAIT ( );
}
ENABLE_INTERRUPTS ( );
}
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CONFIG_B
GDLNK
EELOAD
CONFIG_B
CONFIG_B
CONFIG_B
CONFIG_B
CONFIG_B
EELOAD
CONFIG_B, GDLNK, POL, EELOAD
, value);
);
, config_for_A);
, config_for_B);
, config_for_C);
CONFIG_B
, INC.P
);
& !
;
)
POL
;
);
RELIMINARY
VT86C926
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7. C
ONTROL AND STATUS REGISTERS
* VT86C926 supports the control and status registers of DP8390 except those explained as follows.
* VT86C926 supports all page 1 registers. Only part of Page 2 is supported.
* VT86C926 supports Early Transmit Underrun (ETUN)
* VT86C926 supports most of page 0 registers.
* The meaning and use of 01H (CLAD0) and 02H (CLAD1) of page 0 is altered.
* The 06H (FIFO port) of page 0 is not supported.
* The following control/status bits in page 0 are not supported:
-- (D3,D4,D5) == (0,1,1) of CR (00H) : Send Packet Command (RD0 - RD2)
-- D1 of DCR: Byte Order Select (BOS)
-- D2 of DCR: Long Address Select (LAS)
-- D4 of DCR: Auto-initialize Remote (ARM)
-- D5, D6 of DCR: FIFO Threshold Select (FT0 and FT1)
-- D4 of TCR: Collision Offset Enable (OFST)
-- D5 of TSR: FIFO Underrun (FU)
-- D7 of TSR: Out of Window Collision (OWC)
-- D3 of RSR: FIFO Overrun (FO)
OWER DOWN MODE
8. P
The VT86C926 provides an one level power down mode. The BIOS or
Network OS device driver can configure Register A to diagnostic mode
then set the Power-on bit of the diagnostic port to "on." When the
VT86C926 is in Power down mode, all power to the analog port is cut off
and the chip clock is stopped. Other registers are read only. Only the
diagnostic port is read-writeable.
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VT86C926
9. J
UMPERED OPERATION SUPPORT
9.1 Fully Jumpered Operation
Figure 8 below depicts this operation. In this configuration, most
options are selected by jumpers on the VT86C926 controller memory bus
+5V
VT86C926
MD0
⇓
⇓
⇓
⇓
⇓
MD2
MD3
⇓
MD6
MD0
⇓
MD1
MA3 ISA mode
MD4
⇓
MD7
MD10
MSWR#
ISA I/O Base
INT 0~f
Media Select
Boot ROM Select
Software Enable
Configure from EEPROM
Figure 3: Example of Jumper Configuration
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ACKET TRANSMISSION DESCRIPTION
10. P
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VT86C926
The VT86C926 NIC is CSMA/CD compliant and offers scheduled retransmission of packets up to 15 times
on collisions according to the truncated binary exponential backoff algorithm. The following is an
overview of the transmission process.
10.1.Transmission Setup
In order for the transmit packet to be ready for transmission, it must follow the IEEE 820.3 specification
(see figure 4). When the transmit packet is set up in the memory, the VT86C926 will initialize the packet
starting address (TPSR) and the packet length (TPCR0, TBCR1). Then the PTX bit (transmit packet) of the
command register will be set to start transmission.
TX Byte Count
(TBCT0.1)
Destination Address
Source Address
Type Length
Data
Pad (If data < 46 bytes)
Figure 4. Transmit Packet Format
6 Bytes
6 Bytes
2 Bytes
46 Bytes
10.2.Transmission Process
After the PTX bit is set to start transmission, the TXE (transmit enable) signal is asserted and transmission
begins (see figure 5). T he CRC is calculate d after the 62 b it prea mble (alterna ting ONEs and ZEROs) and
the start of the frame delimiter (two ONEs) are sent out as NRZ data (pin TxD) with a clock (TxC). This
process does not end until the byte count reaches zero. After all bytes are serialized, the 4 CRC bytes are
then serialized and added to the packet. In case of collisions, transmissions would cease and jam sequence
of 32 ONEs would be transmitted to notify every node of the collision. Once the jam sequence is
transmitted, the packet would be rescheduled for transmission according to the truncated binary exponential
backoff algorithm.
Transmit Buffer
Byte Count
TxE
TxC
TxD
Serializer
CRC
PSTART
Destination Address
Source Address
Type Length
Data
DMA PLA
CRS
COL
Protocol PLA
Figure 5. Packet Transmission
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VT86C926
10.3.Transmission Status
An interrupt is generated at the end of transmission: either the PTX bit (complete packet transmitted) or the
TXE bit (packet transmission aborted) of the ISR (Interrupt Status Register) is set. This interrupt routine
discerns the specific details of the transmission by reading the TSR. If the PTX bit is set, reading the TSR
can reveal the following: if a carrier was present when the transmission was initiated (DFR), if the carrier
was lost during the transmission (CRS -- This would point to a short somewhere on the network), if the
collision detect circuitry is working properly (CDH) and if a collision occured (COL). The collision co unt
register (NCR) is incremented each time a collision occurs. The out of window collision (OWC) bit of the
TSR is set whenever a collision occurs outside the 512K window (slot time). If 16 collisions occur, then the
TXE but if the ISR is set. If 16 collisions abort a transmission, then the ABT bit of the TSR is set.
11. P
ACKET RECEPTION
The VT86C926 uses a receive filter scheme to manage packet reception. Because every node receives all
packet transmissions in CSMA/CD compliant networks, this receive filter is needed to filter out all packets
without matching addresses.
11.1.Reception Process
The VT86C926 will begin to check for the two consecutive ONEs than indicates the start of the frame
delimiter (SFD) once VT86C926 dectects the active CTS signal and the ONE-ZERO preamble. After the
detection of the SFD, the incoming data is deserialized and sent to the address filter (see figure 6). If the
packet passes the address filter, then the packet is sent to the receive buffer ring through the DMA. An
interrupt is generated when the packet is received into the buffer ring.
To determine the acceptance and rejection of packets, the calculated value of the CRC, at the point in which
the CRS signal is low, is compared with the last four bytes received. If a match occurs on the last byte
boundary, then the packet is accepted. If the CRCs do not match at the last byte boundary and the CRC
goes LOW, the packet is re jected and an CRC error is ind icated (CRC bit of RSR set); that is to say the
recieve buffer ring is not upd ated. If the CRCs do not match a t the last byte boundary and the CRC d oes
not go LOW, then a frame alignment error occurs and is flagged (FAE bit of RSR set). However, frame
alignment errors occur only when CRC errors occur.
Receive Buffer Ring
RxD
RxC
CRS
Deserializer
CRC
Address
Filter
CRS
COL
Figure 6. Packet Reception
16
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11.2.Receive Buffer Ring
Incoming packets are placed by the NIC into the Receive Buffer Ring to await processing. As each packet
is processed, it is then removed from the ring. The NIC allocates an area of memory to use as the buffer
ring during initialization. Because ring pointers are located on the chip, the buffer management scheme
works at a high efficiency. The DMA channels can transfer data at 10 Mbyte per second. The second
DMA or the remote DMA channel removes packets from the rings after the packets have been processed.
Though the receive buffer ring allows packets to be processed in the or der of arrival, it is no t a FIFO b uffer.
It is just a portion of memory that works effectively as a FIFO buffer
The four on-chip pointers that control the ring are the page start (PSTART) pointer, page stop (PSTOP)
pointer, current page (CURR) pointer and boundary (BNRY) pointer. The PSTART and PSTOP pointers
determine the size of the buffer ring. The CURR pointer determines the location of the next packet to be
received and the BNRY pointer determines the location of the next packet to be removed. When packets
are received, the CURR pointer moves to the next location (in the direction of rotation) and the BNRY
follows the CURR pointer. However, the PSTART and PSTOP remains the same throughout the
procedure.
To receive packets, buffers are linked as necessary to accomodate the incoming packets. Up to 256 buffers
can be linked together in a single ring. Each buffer is 256 bytes. That effectively yields a maximum of 64K
bytes for the entire ring. Therefore, the theoretical maximum space between PSTART and PSTOP is 64K
and all the pointers refer to 256 byte boundaries (see figure 7).
Direction
of Rotation
Buffer Ram (up to 64 KB)
Buffer # 1
Buffer # 2
Buffer # 3
Buffer # n
Figure 7. Receive Buffer Ring
Page Start Address
Page Stop
Address
3
4
Receive Buffer Ring
2
256 Bytes
1
n
Direction
of Rotation
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t
t
e
n
e
e
e
t
g
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The pointers PSTART and PSTOP are determined during initialization. The first valid packet received is
placed at the CURR pointer plus a four byte offset (see figure 8). If the packet is greater than the 256 byte
buffer, then the buffers are linked together until the packet is received in its entirety. Because of the ring
design of the buffer, the first and the last buffer may be linked together. When a packet is completely
received, the status from the Receive Status Register (RSR), a pointer to the next packet and the byte count
of the current packet are written into the four byte offset.
n
Packet Status
1
2
3
4
n-2
n-1
Begining Curren
Page Register
Packet Ends
Current PageRegister
(after reception of 3 packe
Begin Receptio
& Packet Storag
Direction
of Rotation
n
4 Byte Offset for Pack
1
4 Byte Offset for Pack
(after reception of first pack
2
3
4
n-2
n-1
Begining Curren
Page Register
Current Page
Register
(after reception of first pack
Status
Next Page
Length (L)
Length (H)
Direction
of Rotation
Figure 8. Receive Packet Buffering
Note:
Figures 5, 6, 7 and 8 are flat illustrations of the Receive
Buffer Rin
When an error occurs, be it FAE or CRC, it is automatically overwritten. The CURR is no t moved to next
buffer boundary, hence the next incoming packet will overwrite the previous packet (see figure 9). The
error-overwrite feat ure can be toggled on and off by setting the save er rored pa cket (SEP) bit in the RCR.
Runt packets are also overwritten. The runt packet overwrite may be toggled on and off by setting the AR
bit in the TCR.
. See figure 4 for graphical conceptualization.
Direction
of Rotation
n
1
2
3
4
n-2
n-1
Figure 9. Packet Rejection
18
Begining Current
Page Register
Runt Packet,
CRC, FAE
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The BNRY is updated each time a packet is removed. In that way, the BNRY always follow the CURR
around the ring (see figure 10). However, in situations in which the packet processing is slower than the
packet reception, the ring may be full. When the ring becomes full, all incoming packets are aborted so that
packets already in the ring would not be overwritten (see figure 11). New packets will start to arrive after
the BNRY is updated. The missed packet tally counter would keep track of all missed packets. This
situation is unlikely if enough memory is allocated for the receive buffer ring. If the BNRY is located
outside the buffering, the overwrite protection function will not be available. All incoming packets would
overwrite packets already on the ring, whether the packets on the ring have been processed or not.
n
Boundary Pointer
Direction
of Rotation
Boundary Pointer
(after the removal of packet)
1
2
3
4
Remote DMA
Removes Packet
1st Packet
2nd Packet
Current Page Register
n-2
n-1
New Packets
Arriving
Figure 10. Removing Packets from the Receive Buffer Ring
Reception Aborted
by NIC overflow
Boundary Pointer
Direction
of Rotation
n-1
n-2
1
2
3
4
5
n
Remote DMA
Removes Packet
New Packets
Arriving
1st Packet
2nd Packet
Figure 11. Receive Buffer Ring Overwrite Protection
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ARLY INTERRUPT RECEIVE MODE
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The VT86C926, under normal mode, will generate an interrupt to the host after a complete packet is
received and decide to accept it. This, ho wever, will introduce a throughput latency at least longer than the
transmission time of the received packet. To allow the host driver program look ahead the contents of the
packet under receiving, the VT86C926 provides the Early Interrupt Receive Mode which is enabled by
setting the EIEN bit of Diagnostic Register.
During the Early Interrupt Receive Mode, several interrupts are generated based on the receiving conditions
as depicted in the following paragraph.
1.Packet header interrupt
When an incoming packet matches the address (physical or not) of the network controller and the total
received bytes count exceeds 64, the VT86C926 will generate an interrupt to notify the host an addressed
packet in on the way. The driver can distinguish this early interrupt by reading ISR and RSR. If the I SR
shows an PRX status and RSR doesn't reflect that status on its PRX bit, an early interrupt is being
generated.
2.Packet page interrupt
Every time the receiver buffer is completly filled and a new buffer is requested, the VT86C926 will
generate an interrupt with PRX of RSR unset as Packet header interrupt. Therefore, this kind of interrupt
is issued every 256 byte time (~200us) until packet reception is done. The current byte count of packet
being received can be accessed from register 01H (CLDC0) and 02H (CLDC1) of page 0.
3.Receive status interrupt
This is the normal interrupt generated after an addressed packet is completely received. If the received
packet is a good packet, both the ISR and RSR will set PRX bit high. Otherwise, the RXE or OVW will
be reflected on ISR and FAE, XRXE, or MPA on RSR.
Buffer RAM
Buffer RAM
Data Bus
MAC Receiver
Protocol State
Machine &
Registers
PLL & EnDec
TP MAU
AUI Interface
RD+, RDTD+, TD-
RX+, RXTX+, TXCI+, CI-
Host Address Bus
Host Data Bus
Bus Control
& Interface
RX_Interrupt
Buffer RAM
Address Bus
Interrupt
Status
Internal
Control
Signals
Control Signals
Buffer
Management
State Machine
& Register
& Data Bus
FIFO
EIEN
Receive
Status
Internal
Data Bus
Internal
Address Bus
Internal
Control Signals
Figure 12: Early Interrupt Receive Block Diagram
12.1. Early Interrupt Architecture Programming Algorithm
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12.1.1. Enable Early Interrupt Mode
To set the VT86C926 to Early Interrupt mode, set bit 3 (EIEN) of the Diagnostic Register to high. To set
the VT86C926 back to normal mode, set bit 3 (EIEN) of the Diagnostic Register to low. You can set Early
interrupt mode in any state. But your receive interrupt service routine must able to receive fragments from
Ethernet data. If the routine cannot handle the fragment data, you may get corrupt data.
12.1.2. Early interrupt Receive Routine Refence register
The receive interrupt service routine algorithm fetches one page data from the SRAM upon reception of an
interrupt. Refer to the following register and status bit for Early Interrupt service routine:
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Interrupt Status Register
Receive Status Register
Current Local DMA Counter Low and High
Current Page Register
But we suggest that you use this method as below, in order to red uce the interrupt occured times. Please
refer the CLDC counter for currently received bytes.
This algorithm sample enables the VT86C926's early interrupt drivers to increase the LAN system peer to
peer transfer rate. Programmers can modify the orignal NE2000 driver sources to add this function.
1. When driver is initialized,
set PktPointer = 0 and allocate PktBuffer = 1.5 KByte.
2. When interrupt is received, check ISR, CURR and RSR.
If RXE bit in ISR has been set, reset PktPointer = 0. (it is a packet error interrupt, STATE 0)
Else If PRX bit in ISR has been set, compare CURR with BNRY+1,
If CURR == BNRY+1, (it is a early interrupt condition)
Read and save CLDC (Current Local Data Count)
Evenlize CLDC. (CLDC = CLDC - CLDC % 2)
If PRX bit in RSR has not been set,
If RXE bit in ISR has been set, goto packet error condition (STATE 0).
If CLDC <= PktPointer, goto packet error condition (STATE 0).
RSAR = ((BNRY + 1) << 8) + PktPointer.
If RSAR >= PSTOP, set RSAR = RSAR - (PSTOP - PSTART).
RBCR = CLDC - PktPointer.
Use remote DMA to read packet data into offset PktBuffer + PktPointer.
PktPointer = CLDC.
(ISR, 0x07(0) bit0 PRX, bit 2 RXEE)
(RSR,0x0C(0) bit0 EARLY PRX)
(CLDC(0), 0x01, 0x02)
(CURR, 0x07(1))
Else goto packet complete condition (STATE 1).
Else (it is a packet complete interrupt, STATE 1)
RSAR = (BNRY + 1) << 8.
RBCR = 4.
Use remote DMA to packet header into offset PktBuffer.
If RXE bit in ISR has been set, set PktPointer = 0.
Get PktLen = packet length from PktBuffer.
PktLen = (PktLen + 1) - (PktLen + 1) % 2.
if PktLen <= PktPointer, set PktPointer = 0.
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RSAR = ((BNRY + 1) << 8) + PktPointer.
RBCR = PktLen - PktPointer.
Use remote DMA to read packet data into offset PktBuffer + PktPointer.
PktPointer = 0.
If PktPointer = 0,
Do the normal driver packet received procedure,
but get packet data from PktBuffer, not the receive buffer ring.
Else go to interrupt entry to poll ISR again.
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Rx condition ISR RSR CURR CLDC
Packet header or
page data received
Total packet received 1 1 BNRY+1 +
More then one packet 1 0 BNRY+1 +
CRC or page align
error
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1 0 BNRY+1 <>0
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(packet pages)
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VT86C926
13. E
In order to provide the VT86C926 with parallel processing between the ISA bus and Ethernet media, the
VT86C926 must be set to detect early transmit error mode. This error may occur when the system's master
device uses the ISA bus and then uses the data bus.
If the ETEN bit is set in the configuration register B, the transmit status status bit5 (ETUN) and the transmit
error status bit (TXE) in the interrupt service register (ISR) bit 3 would be set on. If the interrupt mask
register TXEE bit is set to on, an interrupt will be generated when the local DMA pass the remote DMA
machine.
This mode is essentially similar to the Early Interrupt Receive Mode. When the VT86C926 is under the
normal mode, the CPU can issue the "transmit packet" command to the VT86C926 and the internal local
DMA will tranfer the data from the SRAM to the Ethernet. However, the packet data must already exist in
SRAM.
In the situation in which the "transmit packet" command is issued to the local DMA and the remote DMA
(to fill SRAM) at the same time, a corrupt packet may be transmitted to the network and remain undetected.
ARLY TRANSMIT MODE
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Address Bus
RAM Bus Arbitrator
& Data Bus FIFO
Remote DMA
Registers &
State
Machines
Remote_
DMA_
Status
Data Bus
ETEN
Write_point
Early Transmit
State Machine
Address Bus
Read_point
Local_
DMA_
Status
Buffer RAM
Local DMA
Registers &
State
Machines
Host Data Bus
Figure 13: Early Transmit Error Detect Block Diagram
Early_Tx_Error Stop_Local_DMA
Note: If Write_point<Read_point, then Early_Tx_Error.
If Write_point>Read_point, then Stop_Local_DMA.
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